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Date: Fri, 22 Mar 2002 16:53:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Flattening a board during assembly
Hi Michael,
I know that board flattening procedure isn't board friendly thing but what's
a better alternative? It came down to either do the bake & twist procedure
or scrap the panels.
You are 100% correct that excesses could cause irreparable damage to the
panels but the procedure was only done by the PE (me), QEs and the Final
Inspect Leads. Your caution/warning could apply to any manual operation.
At least a flattened board stayed flat and didn't curl up when it saw an
elevated temp. (smt reflow) at the assembly house. If I could have figured
a way to laminate an unbalanced construction flat the extra procedure
wouldn't have been necessary.
Hans
-----Original Message-----
From: Mcmaster, Michael [mailto:[log in to unmask]]
Sent: Thursday, March 21, 2002 7:10 PM
To: [log in to unmask]
Subject: Re: [TN] Flattening a board during assembly
Rumor has it that we've reached the bottom of the recent economic downturn.
That may or may not be true. All I know is that I'm busy enough that I've
fallen a few weeks and a few hundred Technet e-mails behind. Maybe I need
to introduce my Technet E-mail Backlog Index and see how it corresponds to
the other financial indicators.
All kidding aside, Hans your "manual assist" process is not advised. I've
seen boards with cracked soldermask that were traced down to someone
"flattening" a warped board before placing on a driller or router bed. I
don't recommend flexing cold boards to remove warpage.
> ----------
> From: Hinners Hans M Civ
> WRALC/LUGE[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Hinners Hans M Civ WRALC/LUGE
> Sent: Friday, March 08, 2002 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] Flattening a board during assembly
>
> Hey Daan,
>
> Here's a generic dewarp I've used in the past. You or preferably the Fab
> house should have an oven large enough to load the panels or boards. If
> done properly you won't see re-warp during the assembly process. Dewarp
> is
> not a board friendly process and I shudder to consider the longer term
> reliability issues but it gets them flat when nothing else will. It's
> usually better to dewarp boards instead of panels because of stress relief
> that occurs at Route. On the other hand a 2 or 4 up panel cuts your cycle
> time down considerably.
>
> 1. Load warped panels into oven. (Keep stacks reasonable sized: ~500
> mils
> of board stock or less - 6-10 panels depending on thickness)
> 2. Place several Caul plates (that match or overlap panel size) ~50
> pounds
> of weight & Use Kraft Paper (Sulfur Free) to protect panels
> 3. Bake at 340+ F for 4-6 hours (Material must be at or slightly above
> Tg)
> 4. Cool slowly to room temp.
> 5. Manually assist (Bend & Twist) the dewarp at Final Inspect. (Great
> upper body workout on those 200+ board shipments)
> 6. Inspect Panels on Flatness (Granite) Table. ("Tap" test the 4
> corners.
> If the board's corners don't touch the table you've got more flexing to
> do.)
>
> Hans
>
> AC-130 Gunship Motto: "You can run but, you'll only die tired."
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax: (478) 926 - 4911
> DSN Prefix: 468
>
>
>
> -----Original Message-----
> From: d. terstegge [mailto:[log in to unmask]]
> Sent: Thursday, March 07, 2002 11:48 AM
> To: [log in to unmask]
> Subject: [TN] Flattening a board during assembly
>
>
> Hi Technetters,
>
> We've got a batch of boards here that's really twisted (about 1.5 % when
> measured according to IPC-TM-650) due to imbalanced design. The customers
> is
> not willing to change the design, and we discussed with them the
> possibility
> of using a carrier-frame for flattening these boards while they are
> processed through our SMT-line.
>
> My worry is that this results in unacceptable stress in the solder joints
> as
> soon as the board is released from the carrier. Fortunately there's no BGA
> on this board, but it does have a small QFP and some 40 mm long
> SMT-connectors. It's supposed to be a high-reliability military product.
>
> Does anyone have any data on the effects of such internal stresses ?
> Also other comments are welcome.
>
> Best regards.
>
> Daan Terstegge
> SMT Centre
> Thales Communications
> Unclassified mail
> Personal Website: http://www.smtinfo.net
>
> --------------------------------------------------------------------------
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Date: Fri, 22 Mar 2002 17:22:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB exposure to solvents
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Toluene or xylene or butyl acetate generally work well on acrylics, with less
damage to the PCB.
Jon Moore
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Date: Sat, 23 Mar 2002 02:30:04 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: PCB exposure to solvents
X-To: "KIPPING, Michael (York Rd)" <[log in to unmask]>
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Michael
It all depends on the solvent. MEK is a fairly aggressive and toxic
solvent. I'd suggest trying to find a milder one, such as one of the
paraffins. I'll answer your question with another: how long is a piece
of string?
Brian
"KIPPING, Michael (York Rd)" wrote:
>
> Hi there
>
> We conformally coat our PCB assemblies using an acrylic and use Methyl Ethyl
> Ketone to strip assemblies if they require rework.
> Has anyone carried out any work on the maximum exposure time you can expose
> PCBs to solvents? (I realise that it will depend on the laminate materials,
> component constuction etc.)
>
> Thanks
>
> Michael Kipping
>
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Date: Mon, 25 Mar 2002 07:05:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Atkinson, Neil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: BGA reballing
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
I guess the key here is to minimise the heat sustained by the BGA.
I have seen one company here in the UK (Retronix) who use a laser system for
reballing BGAs. I don't have direct experience of using their service for
BGAs but having witnessed it working, it looks pretty good at only applying
the minimum amount of heat exactly where it is required...
Neil
-----Original Message-----
From: Peter Swanson [mailto:[log in to unmask]]
Sent: 21 March 2002 16:57
Subject: Re: BGA reballing
Justin,
A good question. Number of BGA reflow steps:
1) Initial placement
2) Removal from pcb
3) Reball
4) Replacement on pcb
4 temp excursions. When this issue has been brought up before in this forum,
I do not believe that a written spec for the maximum number of reflow cycles
of a BGA was ever found. The specific part manufacturer might state
something... There was a rumour that Motorola specified 3 reflow cycles for
its parts, but I never saw anything in writing, and this may be an "urban
myth".
In the TechNet archives there is an e-mail from Axiom Electronics stating
"In all of the parts we have removed, reballed, and replaced, we have not
seen damage due to numerous reflow cycles." This was in 1996 tho... (Message
no 005489). There may be more info there.
It would be important to strictly observe the baking requirements as
determined by the moisture sensitivity level of the device. The reflow
cycles should all be to the correct profiles to minimise thermal shock, etc.
Declaring a commercial interest (as we sell this product), no customer has
reported issues to us.
I would be interested to hear further views!
Regards,
Peter
--
=========================================================
Peter Swanson [log in to unmask]
INTERTRONICS http://www.intertronics.co.uk
INTERTRONICS is dedicated to providing quality material,
consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
the highest levels of technical support and customer
service.
-----Original Message-----
From: Braime, Justin [mailto:[log in to unmask]]
Sent: 21 March 2002 14:28
To: [log in to unmask]
Subject: [TN] BGA reballing
Hi guys,
I am looking at using the SolderQuik preforms for reballing some BGAs, but I
am concerned about the reliability of this process in terms of the number of
thermal cycles being sustained by the BGA component. Does anybody know of
any studies done on this?
Thanks
Justin Braime
Senior Production Engineer
Racal Instruments Ltd
480 Bath Rd, Slough
Berkshire, SL1 6BE
England
Tel: +44 (0)1628 604455
Fax: +44 (0)1628 662017
E-mail: [log in to unmask]
****************************************************************************
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Date: Mon, 25 Mar 2002 10:08:26 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Busko, Wolfgang" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: 2-sided SMT assemblies
X-To: Jim Mathis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1D3DC.9F4DDAB0"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------_=_NextPart_001_01C1D3DC.9F4DDAB0
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Hi Jim,
=20
depends on what your assemblies look like. With the usual stuff (R=B4s =
and C=B4s
and smaller (lighter parts)) on one side, usually called bottom side, =
it=B4s
should really not be a problem at all, just do the heavy stuff last.
As mentioned before look after possible mechanical impact of the =
already
populated side, especially during second reflow.=20
If you go for glueing and wavesolder SMD the same caution should be =
taken.
If the latter is true for you it might take a bit more effort to =
implement
the process of glueing and handling your workpieces, with doubleside =
reflow
it=B4s not that much of a problem ... except for your THT-parts.
=20
Good luck=20
=20
Wolfgang
=20
------_=_NextPart_001_01C1D3DC.9F4DDAB0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR></HEAD>
<BODY=20
style=3D"BORDER-RIGHT: medium none; BORDER-TOP: medium none; FONT: 10pt =
verdana; BORDER-LEFT: medium none; BORDER-BOTTOM: medium none">
<DIV><SPAN class=3D737355508-25032002><FONT face=3Dverdana>Hi=20
Jim,</FONT></SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002></SPAN> </DIV>
<DIV><SPAN class=3D737355508-25032002><FONT face=3Dverdana>depends on =
what your=20
assemblies look like. With the usual stuff (R=B4s and C=B4s and smaller =
(lighter=20
parts)) on one side, usually called bottom side, it=B4s should really =
not be a=20
problem at all, just do the heavy stuff last.</FONT></SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002>As mentioned before look after =
possible=20
mechanical impact of the already populated side, especially during =
second=20
reflow. </SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002>If you go for glueing and =
wavesolder SMD the=20
same caution should be taken.</SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002>If the latter is true for you it =
might take=20
a bit more effort to implement the process of glueing and handling your =
workpieces, with doubleside reflow it=B4s not that much of a problem =
... except=20
for your THT-parts.</SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002></SPAN> </DIV>
<DIV><SPAN class=3D737355508-25032002><FONT face=3Dverdana>Good luck=20
</FONT></SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002></SPAN> </DIV>
<DIV><SPAN class=3D737355508-25032002><FONT=20
face=3Dverdana>Wolfgang</FONT></SPAN></DIV>
<DIV><SPAN class=3D737355508-25032002></SPAN><FONT=20
face=3DTahoma><BR> </DIV></FONT></BODY></HTML>
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Date: Mon, 25 Mar 2002 06:29:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dieselberg, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: Card Edge Connector
X-To: Scott Kauling <[log in to unmask]>
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Scott, in one of my former lives I used to do printer servicing for IBM. We
used an oil type of material (about the consistency of mineral oil) to lube
and protect the fingers and sockets. I cannot remember the name of the
material, but if you can contact your local IBM printer service engineer he
can probably tell you where you can get it. It is used very sparingly!
Good luck.
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Scott Kauling [mailto:[log in to unmask]]
Sent: Wednesday, March 20, 2002 16:01 PM
To: [log in to unmask]
Subject: [TN] Card Edge Connector
We are inserting a backplane board with gold fingers into a
mother board with three connectors to accept the gold fingers.
Is anyone out there that has heard of, or is using some sort
of lubricant to insert boards into such connectors?
If you are what are you using?
SCOTT
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<TITLE>RE: [TN] Card Edge Connector</TITLE>
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<BODY>
<P><FONT SIZE=3D2 FACE=3D"Arial">Scott, in one of my former lives I =
used to do printer servicing for IBM. We used an oil type of material =
(about the consistency of mineral oil) to lube and protect the fingers =
and sockets. I cannot remember the name of the material, but if you can =
contact your local IBM printer service engineer he can probably tell =
you where you can get it.</FONT><U> <FONT SIZE=3D2 FACE=3D"Arial">It is =
used very sparingly!</FONT></U></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Good luck.</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From: Scott Kauling =
[<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>=
]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent: </FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Wednesday, March 20, 2002 16:01 PM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject: </FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">[TN] Card Edge Connector</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">We are inserting a backplane board =
with gold fingers into a mother board with three connectors to accept =
the gold fingers.</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Is anyone out there that has heard of, =
or is using some sort of lubricant to insert boards into such =
connectors?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">If you are what are you using?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">SCOTT</FONT>
</P>
<P><FONT SIZE=3D2 =
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Date: Mon, 25 Mar 2002 13:46:20 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: 2-sided SMT assemblies
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Hi Jim,
Another issue that you should think about is that you need to have some =
free areas on the first-assembled side of the board, so that you can =
support the board during stencilprinting of the second side. Especially =
when stencilling fine-pitch components board-support becomes a critical =
parameter.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net=20
>>> Jim Mathis <[log in to unmask]> 03/22 3:56 pm >>>
My fellow TechNetters,
Can someone please point me to where I can find information for implementin=
g 2-sided SMT assembly processes? Any information about 2-sided reflow =
soldering, necessary equipment, inspection and testing, anything at all =
will be greatly appreciated.
Thanks, all!Get more from the Web. FREE MSN Explorer download : http://exp=
lorer.msn.com
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Date: Mon, 25 Mar 2002 08:20:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dieselberg, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: PCB exposure to solvents
X-To: Brian Ellis <[log in to unmask]>
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Brian, I have the answer to the string quiz. Long enough to reach from one
tin can to the other tin can. Was I rite?
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Friday, March 22, 2002 19:30 PM
To: [log in to unmask]
Subject: Re: [TN] PCB exposure to solvents
Michael
It all depends on the solvent. MEK is a fairly aggressive
and toxic
solvent. I'd suggest trying to find a milder one, such as
one of the
paraffins. I'll answer your question with another: how long
is a piece
of string?
Brian
"KIPPING, Michael (York Rd)" wrote:
>
> Hi there
>
> We conformally coat our PCB assemblies using an acrylic
and use Methyl Ethyl
> Ketone to strip assemblies if they require rework.
> Has anyone carried out any work on the maximum exposure
time you can expose
> PCBs to solvents? (I realise that it will depend on the
laminate materials,
> component constuction etc.)
>
> Thanks
>
> Michael Kipping
>
>
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<TITLE>RE: [TN] PCB exposure to solvents</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=3D2 FACE=3D"Arial">Brian, I have the answer to the string =
quiz. Long enough to reach from one tin can to the other tin can. Was I =
rite?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From: Brian Ellis [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>=
]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent: </FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Friday, March 22, 2002 19:30 PM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject: </FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">Re: [TN] PCB exposure to =
solvents</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Michael</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">It all depends on the solvent. MEK is =
a fairly aggressive and toxic</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">solvent. I'd suggest trying to find a =
milder one, such as one of the</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">paraffins. I'll answer your question =
with another: how long is a piece</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">of string?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Brian</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">"KIPPING, Michael (York Rd)" =
wrote:</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> Hi there</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> We conformally coat our PCB =
assemblies using an acrylic and use Methyl Ethyl</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> Ketone to strip assemblies if =
they require rework.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> Has anyone carried out any work =
on the maximum exposure time you can expose</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> PCBs to solvents? (I =
realise that it will depend on the laminate materials,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> component constuction =
etc.)</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> Thanks</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> Michael Kipping</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">> =
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Date: Mon, 25 Mar 2002 07:45:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: 2-sided SMT assemblies
X-To: [log in to unmask]
Good point Daan. Although, if you're fortunate enough to have the latest DEK
stuff as FormFlex, this needn't necessarily be the case.
Old Steve has one of those 288's, or whatever the number (I can't remember
them as 265's or is it 283 GSX'S and LITE'S like my old Chevy engines), I
think, and I got to play with one two years ago and again a few months ago.
Anyway, anyone care to comment on the form flex stuff? I remember
programming the fine pitch auto flex (fpa) and using the non fine pitch
version as well as machining permanent fixtures to do the same job but
expensive.
Hell, I'm going down a stencil printing memory lane over the past 5 years
plus I'm snowed in, bored, and freezing in MI. How times have changed!
MoonMan
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Date: Mon, 25 Mar 2002 15:06:27 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: 2-sided SMT assemblies
X-To: [log in to unmask]
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Hi Earl,
Since a few weeks we do have this formflex-system in our 265 and it seems =
to work quite good, although set-up time is a bit longer than DEK =
promised. We were used to making a board-specific metal plate with holes =
in it to place DEK's support pins in, and that's no longer needed. With =
about 3 new boards per week that saves an awefull lot of time for =
production engineering.=20
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Earl Moon <[log in to unmask]> 03/25 2:45 pm >>>
Good point Daan. Although, if you're fortunate enough to have the latest =
DEK
stuff as FormFlex, this needn't necessarily be the case.
Old Steve has one of those 288's, or whatever the number (I can't remember
them as 265's or is it 283 GSX'S and LITE'S like my old Chevy engines), I
think, and I got to play with one two years ago and again a few months =
ago.
Anyway, anyone care to comment on the form flex stuff? I remember
programming the fine pitch auto flex (fpa) and using the non fine pitch
version as well as machining permanent fixtures to do the same job but
expensive.
Hell, I'm going down a stencil printing memory lane over the past 5 years
plus I'm snowed in, bored, and freezing in MI. How times have changed!
MoonMan
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Date: Mon, 25 Mar 2002 14:17:21 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"KIPPING, Michael (York Rd)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "KIPPING, Michael (York Rd)" <[log in to unmask]>
Subject: PCB exposure to solvents
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
So I take it from the responses so far that no-one has carried out any
testing to determine the length of time they are able to leave electronic
assemblies in solvent strip tanks?
Leaving an assembly in for 'the shortest possible time' is ok in theory but
it isn't a specification for operators to work by. Does this mean that we
are all relying on manufacturing operatives to make their own decisions on
how long to leave assemblies in for (do they have the training to make
decisions like that)?
Regards
Michael Kipping
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Date: Mon, 25 Mar 2002 08:48:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charles Caswell <[log in to unmask]>
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From: Charles Caswell <[log in to unmask]>
Subject: Re: PCB exposure to solvents
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=20
-----Original Message-----
From: Dieselberg, Ron [mailto:[log in to unmask]]
Sent: Monday, March 25, 2002 7:20 AM
To: [log in to unmask]
Subject: Re: [TN] PCB exposure to solvents
I use plain isopropyl to strip acrylic conf. coat. Usually half hour =
soak brushing once or twice with a soft brush followed by aqueous =
cleaning. Sometimes have to repeat but works well and is safer for you =
and the product.
Charles Caswell
Process Lead, PCB
Frontier Electronic Systems
"KIPPING, Michael (York Rd)" wrote:=20
>=20
> Hi there=20
>=20
> We conformally coat our PCB assemblies using an acrylic and use Methyl =
Ethyl=20
> Ketone to strip assemblies if they require rework.=20
> Has anyone carried out any work on the maximum exposure time you can =
expose=20
> PCBs to solvents? (I realise that it will depend on the laminate =
materials,=20
> component constuction etc.)=20
>=20
> Thanks=20
>=20
> Michael Kipping=20
>=20
> =
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<TITLE>RE: [TN] PCB exposure to solvents</TITLE>
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<DIV> </DIV>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Dieselberg, Ron=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, March 25, =
2002 7:20=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] PCB =
exposure to=20
solvents<BR><BR></DIV></FONT>
<UL>
<UL>
<P><SPAN class=3D290424214-25032002>I use plain isopropyl to strip =
acrylic=20
conf. coat. Usually half hour soak brushing once or twice with a =
soft=20
brush followed by aqueous cleaning. Sometimes have to repeat but =
works=20
well and is safer for you and the product.</SPAN></P>
<P><SPAN class=3D290424214-25032002>Charles Caswell</SPAN></P>
<P><SPAN class=3D290424214-25032002>Process Lead, PCB</SPAN></P>
<P><SPAN class=3D290424214-25032002>Frontier Electronic =
Systems</SPAN></P>
<P><FONT face=3DArial size=3D2>"KIPPING, Michael (York Rd)" =
wrote:</FONT>=20
<BR><FONT face=3DArial size=3D2>></FONT> <BR><FONT face=3DArial =
size=3D2>>=20
Hi there</FONT> <BR><FONT face=3DArial size=3D2>></FONT> =
<BR><FONT=20
face=3DArial size=3D2>> We conformally coat our PCB assemblies =
using an=20
acrylic and use Methyl Ethyl</FONT> <BR><FONT face=3DArial =
size=3D2>>=20
Ketone to strip assemblies if they require rework.</FONT> =
<BR><FONT=20
face=3DArial size=3D2>> Has anyone carried out any work on the =
maximum=20
exposure time you can expose</FONT> <BR><FONT face=3DArial =
size=3D2>> PCBs=20
to solvents? (I realise that it will depend on the laminate=20
materials,</FONT> <BR><FONT face=3DArial size=3D2>> component =
constuction=20
etc.)</FONT> <BR><FONT face=3DArial size=3D2>></FONT> <BR><FONT =
face=3DArial=20
size=3D2>> Thanks</FONT> <BR><FONT face=3DArial =
size=3D2>></FONT>=20
<BR><FONT face=3DArial size=3D2>> Michael Kipping</FONT> =
<BR><FONT=20
face=3DArial size=3D2>></FONT> <BR><FONT face=3DArial =
size=3D2>>=20
=
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Date: Mon, 25 Mar 2002 08:51:06 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: 2-sided SMT assemblies
X-To: [log in to unmask]
Thanks Daan,
Doing this DFM/CE stuff, I don't get chances to keep up. So you can retro
older machines as well? Always hated programming FPA (don't know the time
delta between formflex and that) and the damn table kept having problems
like pins sticking, etc.
Enjoy,
Earl
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Date: Mon, 25 Mar 2002 15:56:01 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: PCB exposure to solvents
In-Reply-To: <[log in to unmask]>
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RE: [TN] PCB exposure to solventsOn advanced training course [to answer hard
questions],
I was taught the answer
"twice half its length"
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dieselberg, Ron
Sent: Monday, March 25, 2002 1:20 PM
To: [log in to unmask]
Subject: Re: [TN] PCB exposure to solvents
Brian, I have the answer to the string quiz. Long enough to reach from one
tin can to the other tin can. Was I rite?
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Friday, March 22, 2002 19:30 PM
To: [log in to unmask]
Subject: Re: [TN] PCB exposure to solvents
Michael
It all depends on the solvent. MEK is a fairly aggressive and toxic
solvent. I'd suggest trying to find a milder one, such as one of the
paraffins. I'll answer your question with another: how long is a piece
of string?
Brian
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<BODY>
<DIV>
<DIV><SPAN class=3D926355115-25032002><FONT face=3DArial><FONT =
color=3D#0000ff><SPAN=20
class=3D067245315-25032002>On</SPAN> advanced training =
course <SPAN=20
class=3D067245315-25032002>[</SPAN>to answer hard questions<SPAN=20
class=3D067245315-25032002>],</SPAN></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D926355115-25032002><SPAN =
class=3D067245315-25032002></SPAN><FONT=20
face=3DArial><FONT color=3D#0000ff><SPAN =
class=3D067245315-25032002>I</SPAN> was=20
taught the answer</FONT></FONT></SPAN></DIV>
<DIV><FONT face=3DArial color=3D#0000ff><SPAN=20
class=3D926355115-25032002></SPAN></FONT> </DIV>
<DIV><SPAN class=3D926355115-25032002><FONT face=3DArial><FONT =
color=3D#0000ff><SPAN=20
class=3D067245315-25032002>"</SPAN>twice half its length<SPAN=20
class=3D067245315-25032002>"</SPAN></FONT></FONT></SPAN></DIV></DIV>
<DIV> </DIV>
<P><FONT face=3DArial color=3D#0000ff>Kind Regards</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Mike Fenner</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Applications Engineer, European=20
Operations</FONT> <BR><B><FONT face=3DArial color=3D#0000ff>Indium=20
Corporation</FONT></B> <BR><FONT face=3DArial color=3D#0000ff> T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial color=3D#0000ff>M: + 44 7810 526 =
317</FONT>=20
<BR><FONT face=3DArial color=3D#0000ff> F: + 44 1908 580 411</FONT> =
<BR><FONT=20
face=3DArial color=3D#0000ff> E: [log in to unmask]</FONT> =
<BR><FONT face=3DArial=20
color=3D#0000ff>W:<U> www.indium.com</U> </FONT><BR><FONT =
face=3DArial=20
color=3D#0000ff>Leadfree:</FONT><U> <FONT face=3DArial=20
color=3D#0000ff>www.Pb-Free.com</FONT></U> </P>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Dieselberg, =
Ron<BR><B>Sent:</B>=20
Monday, March 25, 2002 1:20 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] PCB exposure to=20
solvents<BR><BR></FONT></DIV>
<P><FONT face=3DArial size=3D2>Brian, I have the answer to the string =
quiz. Long=20
enough to reach from one tin can to the other tin can. Was I =
rite?</FONT> </P>
<P><FONT face=3D"Courier New" size=3D2>Ron Dieselberg</FONT> <BR><FONT =
face=3D"Courier New" size=3D2>Trainer/Auditor</FONT> <BR><FONT =
face=3D"Courier New"=20
size=3D2>CMC ELECTRONICS</FONT> <BR><FONT face=3D"Courier New"=20
size=3D2>CINCINNATI</FONT> <BR><FONT face=3D"Courier New"=20
size=3D2>[log in to unmask]</FONT> </P>
<UL>
<UL>
<P><A name=3D_MailData><FONT face=3DArial size=3D2>-----Original=20
Message-----</FONT></A> <BR><B><FONT face=3DArial =
size=3D2>From: =20
Brian Ellis [<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]=
</FONT></B>=20
<BR><B><FONT face=3DArial size=3D2>Sent: </FONT></B> =
<FONT=20
face=3DArial size=3D2>Friday, March 22, 2002 19:30 PM</FONT> =
<BR><B><FONT=20
face=3DArial size=3D2>To: </FONT></B> <FONT =
face=3DArial=20
size=3D2>[log in to unmask]</FONT> <BR><B><FONT face=3DArial=20
=
size=3D2>Subject: </FONT></B> =
<FONT=20
face=3DArial size=3D2>Re: [TN] PCB exposure to solvents</FONT> =
</P>
<P><FONT face=3DArial size=3D2>Michael</FONT> </P>
<P><FONT face=3DArial size=3D2>It all depends on the solvent. MEK =
is a fairly=20
aggressive and toxic</FONT> <BR><FONT face=3DArial =
size=3D2>solvent. I'd=20
suggest trying to find a milder one, such as one of the</FONT> =
<BR><FONT=20
face=3DArial size=3D2>paraffins. I'll answer your question with =
another: how=20
long is a piece</FONT> <BR><FONT face=3DArial size=3D2>of =
string?</FONT> </P>
<P><FONT face=3DArial size=3D2>Brian</FONT>=20
</P></UL></UL></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 25 Mar 2002 10:20:08 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB exposure to solvents
X-To: [log in to unmask]
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So I take it from the responses so far that no-one has carried out any
testing to determine the length of time they are able to leave electronic
assemblies in solvent strip tanks?
*Well, yes and no. I occasionally get the same situations that you
describe and am asked if the assembly is still good. We do some testing on
the hardware to see if we notice any real change or degradation of
properties. That becomes part of our experience, not part of the
specifications or work instructions for operators. And, the data is only
good for that solvent, for that exposure, on that solder mask, on that
laminate, etc. It is not an exhaustive testing to determine process
windows by any stretch of the imagination.
Leaving an assembly in for 'the shortest possible time' is ok in theory but
it isn't a specification for operators to work by. Does this mean that we
are all relying on manufacturing operatives to make their own decisions on
how long to leave assemblies in for (do they have the training to make
decisions like that)?
*No, the operators do not have the training for that. This is why we
employ materials experts or Experts On Call, to answer the questions when
they come up. In our work instruction, we do use "minimal time" and so on.
The operators understand that. We don't put in "up to one hour" because
some might take it the wrong way and use all of that time, if they figure
it acceptable.
Doug Pauls
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Date: Mon, 25 Mar 2002 08:39:09 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Pelkey, Glenn" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Pelkey, Glenn" <[log in to unmask]>
Subject: Balanced Constructions
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Hello all,
We've talked before about the importance of balancing copper weights
within a multilayer board. What are your thoughts of balancing glass
styles? What if the glass is not balanced but all the dielectric spacings
are within tolerance?
Thanks,
Glenn
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<P><FONT SIZE=3D2 FACE=3D"Arial">Hello all,</FONT>
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<P> <FONT SIZE=3D2 =
FACE=3D"Arial">We've talked before about the importance of balancing =
copper weights within a multilayer board. What are your thoughts =
of balancing glass styles? What if the glass is not balanced but =
all the dielectric spacings are within tolerance?</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks,</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Glenn</FONT>
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Date: Mon, 25 Mar 2002 10:46:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Solderability testing
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Hello,
We have the opportunity to buy parts that are up to 4 years old ('98 date
code) for an excellent price. Still in original factory packaging. They
are warranteed by the supplier for a few months after purchase, but we may
not use them until late summer. We are bringing a few of them in to check
their condition out, but I don't know how to test them, and couldn't find
anything in the IPC-TM-650 that seemed to apply. These are IC's that are
normally worth over $100 a pop to us so we don't want to waste too many.
We are a design and test type company - we do not fab our own boards or
populate them in house other than a few hand installed components on most
products. So we don't have reflow ovens, etc. We have a very small solder
pot. There is a small CM in our city that we use that say they can do the
testing, but the cost seems high - for the quantity we want to buy they say
we should test 32 of them and they will not be useable for pick and place
afterwards. There is a small chance some of them may be salvageable for
manual installation.
Can anybody direct me to some information - test procedures, equipment - on
whether we might be able to evaluate these PQFP, fine pitch, high lead count
devices ourselves? And what is a reasonable condition for the components to
be in after this testing?
Genny Gibbard (mailto:[log in to unmask])
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Date: Mon, 25 Mar 2002 10:56:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Balanced Constructions
X-To: [log in to unmask]
Depends on what is meant by balanced glass styles. I have commented before
on this and prefer unbalanced constructions within each dielectric thickness
requiring multiple plies. The caveat is using homogeneous styles to promote
dimensional stability.
As an example when 5 mil thickness is required it is advantageous, instead
of using 2 plies of 1080, to use a single ply of 106 and one of 2113 to
acheive the same result. This allows a high resin to glass ratio, as the
106, for better bond characteristics and lower resin content, as the 2113,
for higher dimensional stability. Plus, the two ply 1080 is very "juicy" and
tends to slip about too much.
If you are talking about using, say, a balanced construction on one board
side, as several two ply 2113 styles per dielectric thickness, and another
on the other side, this too has merit. I recently used a construcion, when
the copper foil was heavier on one side than the other, consisting of
several plies of 7628, sandwiched between two plies of 2113, to counter the
copper imbalance to minimize bow and twist.
This is a good question and has many answers depending on design requirements.
MoonMan
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Date: Mon, 25 Mar 2002 14:12:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: large plastic blocks/bars needed
MIME-Version: 1.0
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Good afternoon all,
We have a project that needs plastic blocks 6x10x12 (in inches). It can =
be Polyethylene (Low Density), Polyethylene (High Density), =
Polypropylene or PVC. "Bar stock" would also work as long as we can cut =
the above sized blocks out of it.
Any ideas for a source?
Thanks in advance,
Phil Nutting
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Date: Mon, 25 Mar 2002 15:13:49 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Solderability testing
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Genny! The test details/methods you need can be found in the
specification for solderability testing of components: IPC-JSTD-002A.
Obtain a copy from IPC and if you have any questions please contact me.
Dave Hillman
CoChairman JSTD-002A committee
[log in to unmask]
Genny Gibbard <[log in to unmask]>@ipc.org> on 03/25/2002 10:46:09 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Genny Gibbard <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Solderability testing
Hello,
We have the opportunity to buy parts that are up to 4 years old ('98 date
code) for an excellent price. Still in original factory packaging. They
are warranteed by the supplier for a few months after purchase, but we may
not use them until late summer. We are bringing a few of them in to check
their condition out, but I don't know how to test them, and couldn't find
anything in the IPC-TM-650 that seemed to apply. These are IC's that are
normally worth over $100 a pop to us so we don't want to waste too many.
We are a design and test type company - we do not fab our own boards or
populate them in house other than a few hand installed components on most
products. So we don't have reflow ovens, etc. We have a very small solder
pot. There is a small CM in our city that we use that say they can do the
testing, but the cost seems high - for the quantity we want to buy they say
we should test 32 of them and they will not be useable for pick and place
afterwards. There is a small chance some of them may be salvageable for
manual installation.
Can anybody direct me to some information - test procedures, equipment - on
whether we might be able to evaluate these PQFP, fine pitch, high lead
count
devices ourselves? And what is a reasonable condition for the components
to
be in after this testing?
Genny Gibbard (mailto:[log in to unmask])
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Date: Mon, 25 Mar 2002 19:08:23 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: large plastic blocks/bars needed
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_168.aebe5ff.29d115f7_boundary"
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Hi Phil!
From the sites that I visited, that size block is pretty non-standard, you
might have to get something custom fabricated. Can you have some sheet stock
bonded together to get that size? Anyways, here's a few places to try:
http://www.adaptplastics.com/plasticmaterials.htm
http://www.plastic-products.com/stock.htm
http://www.vision-plastics.com/plastics.htm
http://www.modernplastics.com/
http://www.professionalplastics.com/
-Steve Gregory-
> Good afternoon all,
>
> We have a project that needs plastic blocks 6x10x12 (in inches). It can be
> Polyethylene (Low Density), Polyethylene (High Density), Polypropylene or
> PVC. "Bar stock" would also work as long as we can cut the above sized
> blocks out of it.
>
> Any ideas for a source?
>
> Thanks in advance,
>
> Phil Nutting
>
--part1_168.aebe5ff.29d115f7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Phil!<BR>
<BR>
From the sites that I visited, that size block is pretty non-standard, you might have to get something custom fabricated. Can you have some sheet stock bonded together to get that size? Anyways, here's a few places to try:<BR>
<BR>
http://www.adaptplastics.com/plasticmaterials.htm<BR>
http://www.plastic-products.com/stock.htm<BR>
http://www.vision-plastics.com/plastics.htm<BR>
http://www.modernplastics.com/<BR>
http://www.professionalplastics.com/<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Good afternoon all,<BR>
<BR>
We have a project that needs plastic blocks 6x10x12 (in inches). It can be Polyethylene (Low Density), Polyethylene (High Density), Polypropylene or PVC. "Bar stock" would also work as long as we can cut the above sized blocks out of it.<BR>
<BR>
Any ideas for a source?<BR>
<BR>
Thanks in advance,<BR>
<BR>
Phil Nutting<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_168.aebe5ff.29d115f7_boundary--
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Date: Mon, 25 Mar 2002 18:46:21 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: PADS POWER PCB DESIGNER
Any Pads Power PCB designers out there wanting to get real serious about DC
and RF MLB boards needing serious improvement through correction and
complete redesign. Must know BGA's as well and be able to get along with
someone intense like me. You know how I LOVE DFM/CE and all that goes with it.
MoonMan
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Date: Mon, 25 Mar 2002 21:11:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Valquirio N. Carvalho" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Valquirio N. Carvalho" <[log in to unmask]>
Subject: Re: large plastic blocks/bars needed
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; format=flowed
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Laminated Plastics in Billerica, MA (978) 663-8800 has an extensive
stock of matierials and will cut to order in most instances. You will
have to inquire about lead time and toleances. We have gotten a quick
turn on some odd ball stuff from them in the past.
Valquirio N. Carvalho
Mfg. Engineer
Teradyne, Inc.
Phil Nutting wrote:
>Good afternoon all,
>
>We have a project that needs plastic blocks 6x10x12 (in inches). It can be Polyethylene (Low Density), Polyethylene (High Density), Polypropylene or PVC. "Bar stock" would also work as long as we can cut the above sized blocks out of it.
>
>Any ideas for a source?
>
>Thanks in advance,
>
>Phil Nutting
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
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Date: Mon, 25 Mar 2002 23:23:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Leland Woodall <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leland Woodall <[log in to unmask]>
Subject: Lifted Resistors and Resistor Modules
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All,
We've lately noticed a marked increase in the number of lifted chip
resistors and castellated termination resistor packs on one of our SMT
manufacturing lines. This began after we upped our reflow profile to solve
some solderability issues. When we recognized this new problem, we restored
to profile to its original settings, but we're still seeing the increased
volume of "floating" components. They're not completely tombstoned, but God
love 'em, they're trying their best to be.
Our solder prints measure as they always have, both in height and pad
coverage.
Any suggestions?
Thanks in advance,
Leland Woodall
Quality Coordinator
Keihin Carolina System Technology, Inc.
4047 McNair Road
Tarboro, NC 27886
Phone: (252) 641-6750, Ext. 2865
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Date: Tue, 26 Mar 2002 10:13:57 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Busko, Wolfgang" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: Lifted Resistors and Resistor Modules
X-To: Leland Woodall <[log in to unmask]>
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Leland,
sorry, but I don=B4t believe you, namely in that point that you=B4ve =
gone back
to the previous settings and things are still wrong.
If it was Ok and than turned bad something has to have changed, your =
task is
to find out what is was.
If you are lucky it=B4s just "the one thing", experience showed that =
most of
the times there are more than one slight (little) changes that cause a =
great
mess.
The obvious things in your case to look at first are the profile =
(especially
the ramps), the paste (handling, environment and datecode), the parts =
in
question (solderability, contamination, handling and may the PCB too) =
and
the landpattern design (especially the castellated R-nets do need a =
good pad
design).
I would go through all procedures first and look for point that=B4s =
been
changed and not set back, have been through that more than one time.
Good luck
Wolfgang
=20
> -----Original Message-----
> From: Leland Woodall [mailto:[log in to unmask]]
> Sent: Tuesday, March 26, 2002 5:24 AM
> To: [log in to unmask]
> Subject: [TN] Lifted Resistors and Resistor Modules
>=20
>=20
> All,
>=20
> We've lately noticed a marked increase in the number of lifted chip
> resistors and castellated termination resistor packs on one of our =
SMT
> manufacturing lines. This began after we upped our reflow=20
> profile to solve
> some solderability issues. When we recognized this new=20
> problem, we restored
> to profile to its original settings, but we're still seeing=20
> the increased
> volume of "floating" components. They're not completely=20
> tombstoned, but God
> love 'em, they're trying their best to be.
>=20
> Our solder prints measure as they always have, both in height and pad
> coverage.
>=20
> Any suggestions?
>=20
> Thanks in advance,
>=20
> Leland Woodall
> Quality Coordinator
> Keihin Carolina System Technology, Inc.
> 4047 McNair Road
> Tarboro, NC 27886
>=20
> Phone: (252) 641-6750, Ext. 2865
>=20
> --------------------------------------------------------------
> -------------------
> Technet Mail List provided as a free service by IPC using=20
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> the BODY (NOT the subject field): SIGNOFF Technet
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> for additional
> information, or contact Keach Sasamori at [log in to unmask] or=20
> 847-509-9700 ext.5315
> --------------------------------------------------------------
> -------------------
>=20
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Date: Tue, 26 Mar 2002 09:32:08 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Geoff Layhe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Geoff Layhe <[log in to unmask]>
Subject: Re: Balanced Constructions
X-To: "Pelkey, Glenn" <[log in to unmask]>
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To quote a much used technical phrase:- It depends.
In general to make a flat multilayer you need to have the construction so
that it's symmetrical around the centre line with respect to copper
thickness and pre-preg styles. To keep the dielectric the same is not enough
because the different glass styles have different stresses in them due to
the glass strand thickness and the number of strands in the warp & fill.
However it's possible to "balance" the construction and use different
pre-pregs side to side to compensate for different copper weights, but I
guess this is an art rather than a science.
Geoff Layhe
www.lamar-uk.co.uk <http://www.lamar-uk.co.uk>
-----Original Message-----
From: Pelkey, Glenn [mailto:[log in to unmask]]
Sent: 25 March 2002 16:39
To: [log in to unmask]
Subject: [TN] Balanced Constructions
Hello all,
We've talked before about the importance of balancing copper weights
within a multilayer board. What are your thoughts of balancing glass
styles? What if the glass is not balanced but all the dielectric spacings
are within tolerance?
Thanks,
Glenn
Private & Confidential:
This e-mail message is confidential and is intended solely for the person or
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other than the addressee please return the message to the sender by replying
to it and then delete the message from your computer.
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Balanced Constructions</TITLE>
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=680401109-26032002><FONT face=Arial color=#0000ff size=2>To
quote a much used technical phrase:- It depends.</FONT></SPAN></DIV>
<DIV><SPAN class=680401109-26032002><FONT face=Arial color=#0000ff size=2>In
general to make a flat multilayer you need to have the construction so that
it's symmetrical around the centre line with respect to copper thickness
and pre-preg styles. To keep the dielectric the same is not enough because the
different glass styles have different stresses in them due to the glass strand
thickness and the number of strands in the warp &
fill.</FONT></SPAN></DIV>
<DIV><SPAN class=680401109-26032002><FONT face=Arial color=#0000ff
size=2>However it's possible to "balance" the construction and use
different pre-pregs side to side to compensate for different copper weights, but
I guess this is an art rather than a science.</FONT></SPAN></DIV>
<DIV><SPAN class=680401109-26032002><FONT face=Arial color=#0000ff size=2>Geoff
Layhe</FONT> </SPAN></DIV>
<DIV><SPAN class=680401109-26032002><FONT face=Arial color=#0000ff size=2><A
href="http://www.lamar-uk.co.uk">www.lamar-uk.co.uk</A></FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Pelkey, Glenn
[mailto:[log in to unmask]]<BR><B>Sent:</B> 25 March 2002
16:39<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Balanced
Constructions<BR><BR></FONT></DIV>
<P><FONT face=Arial size=2>Hello all,</FONT> </P>
<P> <FONT face=Arial size=2>We've
talked before about the importance of balancing copper weights within a
multilayer board. What are your thoughts of balancing glass
styles? What if the glass is not balanced but all the dielectric
spacings are within tolerance?</FONT></P>
<P><FONT face=Arial size=2>Thanks,</FONT> </P>
<P><FONT face=Arial size=2>Glenn</FONT> </P></BLOCKQUOTE></BODY></HTML>
<BR>
<BR>
<P><B><FONT SIZE=2 FACE="Arial">Private & Confidential:</FONT></B></P>
<P><B><FONT SIZE=2 FACE="Arial">This e-mail message is confidential and is intended solely for the person or</FONT></B></P>
<P><B><FONT SIZE=2 FACE="Arial">organisation to whom it is addressed. If the message is received by anyone</FONT></B></P>
<P><B><FONT SIZE=2 FACE="Arial">other than the addressee please return the message to the sender by replying</FONT></B></P>
<P><B><FONT SIZE=2 FACE="Arial">to it and then delete the message from your computer.</FONT></B></P>
<BR>
<BR>
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Date: Tue, 26 Mar 2002 15:48:44 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Vinit Verma <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Vinit Verma <[log in to unmask]>
Subject: Blistering in PCBs
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Probably the following message did not get delivered to this forum a few
days before since I did not get ANY reply hence posting it again.
Hi Technetters,
We are currently running an 8 layer PCB, 1.6mm thickness. In the last run of
approx. 400 nos. we found approx. 10 nos PCBs with blisters in some specific
areas. In approx. 40-50 nos. the blistering is not there but the laminate
has discoloration. More specifically, the blistering is seen in a
particular area with a ground plane just beneath. In some PCBs the
blistering is there on both sides of the PCB (just mirrored on both sides)
and in some cases just on one side.
Looking carefully at the bare PCBs I observed that there is a small ring
around all the vias/PTHs with a width of approx. 0.2-0.3mm. This ring is
basically the laminate itself but slightly raised and hence looking like a
small ring. Is this normal? Can this be causing the blistering? OR is this
an indication of some other phenomenon which is causing the blistering?
Actually this ring is visible in ALL vias and PTHs all over the board, but
blistering is happening ONLY in one particular area. What bothers me the
most is that ALL PCBs have this ring around the vias/PTHs but the
blistering has happened in approx. only 10 out of 400 PCBs.
Somebody pointed it out to the reflow profile, which actually is withing the
the paste manufacturer's specified range. Even if it IS due to the profile
then why ONLY 10/400? Why not more?
Can anybody suggest any possible causes of the same.
We are not baking the PCBs prior to processing, but the boards are in vacuum
packing with 10 PCBs per bag and the packing is opened only at the Stencil
printing stage.
Any suggestions welcome.
Regards
Vinit Verma
Flextronics Technologies (India) Pvt. Ltd.
88A, Electronic City, Hosur Road,
Bangalore-561 229
Tel: +91-80-852 0022, Ext. 161 ; Fax: +91-80-852-1022
E-Mail : [log in to unmask]
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Date: Tue, 26 Mar 2002 05:48:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Balanced Constructions
X-To: [log in to unmask]
It's only an art, whether MLB constructions and material selections
comprising them, until the experiment is conducted and the effects are
proven acceptable.
MoonMan
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Date: Tue, 26 Mar 2002 05:53:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: Vinit Verma <[log in to unmask]>
You know some blistering/delamination causes as poor design rules, poor
material selections, poor material, poor relamination process management,
poor thermal management.
You need the x-sections to make a proper determination. The rings may be
pink types. Though IPC does not consider this condition rejectable, it may
be an indicator of process management issues that need to be addressed.
MoonMan
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Date: Tue, 26 Mar 2002 06:12:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PADS POWER PCB DESIGNER
Folks,
The following is an ad I'm considering for the Pads designer I need. I'm
posting it here only to get reactions from you all, as PCB experts,
concerning the job responsibilities and requirements. Let me know what you
think, please.
Pads Power Printed Circuit Board Design Engineer/Designer
Serious growing telecommunications company needs serious PCB designer.
Boards consist of several MLB types from 6 to 12 layers with BGA?s, CSP?s,
and other fine pitch devices and attendant components. Both DC and Analog
circuitry reside on these boards and impedance is critical in specified
areas. Designer MUST:
Be very focused on fulfilling responsibilities in a timely, professional manner
Be capable of working in small company environment under ?quality? pressure
first, then schedule
Be capable of managing design processes for several board types as
management directs priority
Have 5 years minimum experience using Pads Power
Have clear understanding of DFM principles using concurrent engineering (CE)
Have clear understanding of MLB design, fabrication, assembly, and test
requirements
Have clear understanding of microstrip and stripline impedance requirements
Have clear understanding of micro, blind, and buried vias
Have clear understanding of MLB materials, constructions, and solderability
Have clear understanding of MLB?s and all that comprise them
Have AutoCad 14 experience to create mechanicals as master, assembly
drawings, etc.
Have extensive experience working with many component types
Have clear understanding of all applicable IPC guidelines and requirements
Have ability to communicate PCB requirements clearly to management,
purchasing, engineering, and suppliers using concurrent engineering
Have understanding of ISO 9000 (4.6): 94 and/or 2000 (7.3) design control
requirements
Prefer:
MoonMan
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Date: Tue, 26 Mar 2002 05:34:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: Vinit Verma <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Vinit,
The "raised" area around the vias/PTHs is probably due to damage to the laminates when the holes were
made.
You did not say if the blistered/discolored areas were around the holes.
If possible try to post some pictures at steve's web site: http://stevezeva.homestead.com/index.html
You may need to do a cross section of the damaged area.
David A. Douthit
Manager
LoCan LLC
Vinit Verma wrote:
> Probably the following message did not get delivered to this forum a few
> days before since I did not get ANY reply hence posting it again.
>
> Hi Technetters,
>
> We are currently running an 8 layer PCB, 1.6mm thickness. In the last run of
> approx. 400 nos. we found approx. 10 nos PCBs with blisters in some specific
> areas. In approx. 40-50 nos. the blistering is not there but the laminate
> has discoloration. More specifically, the blistering is seen in a
> particular area with a ground plane just beneath. In some PCBs the
> blistering is there on both sides of the PCB (just mirrored on both sides)
> and in some cases just on one side.
>
> Looking carefully at the bare PCBs I observed that there is a small ring
> around all the vias/PTHs with a width of approx. 0.2-0.3mm. This ring is
> basically the laminate itself but slightly raised and hence looking like a
> small ring. Is this normal? Can this be causing the blistering? OR is this
> an indication of some other phenomenon which is causing the blistering?
> Actually this ring is visible in ALL vias and PTHs all over the board, but
> blistering is happening ONLY in one particular area. What bothers me the
> most is that ALL PCBs have this ring around the vias/PTHs but the
> blistering has happened in approx. only 10 out of 400 PCBs.
>
> Somebody pointed it out to the reflow profile, which actually is withing the
> the paste manufacturer's specified range. Even if it IS due to the profile
> then why ONLY 10/400? Why not more?
>
> Can anybody suggest any possible causes of the same.
>
> We are not baking the PCBs prior to processing, but the boards are in vacuum
> packing with 10 PCBs per bag and the packing is opened only at the Stencil
> printing stage.
>
> Any suggestions welcome.
>
> Regards
> Vinit Verma
> Flextronics Technologies (India) Pvt. Ltd.
> 88A, Electronic City, Hosur Road,
> Bangalore-561 229
> Tel: +91-80-852 0022, Ext. 161 ; Fax: +91-80-852-1022
> E-Mail : [log in to unmask]
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Tue, 26 Mar 2002 06:47:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tostevin, Bruce" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tostevin, Bruce" <[log in to unmask]>
Subject: Re: large plastic blocks/bars needed
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Phil,
I'm not sure what the plastic is (polystyrene?) ... but otherwise, what
about building them out of LEGOs?
Bruce Tostevin
Benchmark Electronics
Hudson, NH
> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Monday, March 25, 2002 2:12 PM
> To: [log in to unmask]
> Subject: [TN] large plastic blocks/bars needed
>
> Good afternoon all,
>
> We have a project that needs plastic blocks 6x10x12 (in inches). It can
> be Polyethylene (Low Density), Polyethylene (High Density), Polypropylene
> or PVC. "Bar stock" would also work as long as we can cut the above sized
> blocks out of it.
>
> Any ideas for a source?
>
> Thanks in advance,
>
> Phil Nutting
>
> --------------------------------------------------------------------------
> -------
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> -------
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Date: Tue, 26 Mar 2002 07:38:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: large plastic blocks/bars needed
X-To: Phil Nutting <[log in to unmask]>
In-Reply-To: <[log in to unmask]
sys.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Call your local machine shop. They should have plenty of catalogs, possibly
material in house.
Ed
At 02:12 PM 3/25/2002 -0500, you wrote:
>Good afternoon all,
>
>We have a project that needs plastic blocks 6x10x12 (in inches). It can
>be Polyethylene (Low Density), Polyethylene (High Density), Polypropylene
>or PVC. "Bar stock" would also work as long as we can cut the above sized
>blocks out of it.
>
>Any ideas for a source?
>
>Thanks in advance,
>
>Phil Nutting
>
>---------------------------------------------------------------------------------
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>ext.5315
>---------------------------------------------------------------------------------
>
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Date: Tue, 26 Mar 2002 09:16:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: Re: PADS POWER PCB DESIGNER
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Hey Earl,
Our CAD guys could probably help you if you want to send the design here.
Call John Gralewski at 412 858-6144 for details.
Don't know if this is what you're looking for, just trying to help.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Tuesday, March 26, 2002 7:12 AM
To: [log in to unmask]
Subject: Re: [TN] PADS POWER PCB DESIGNER
Folks,
The following is an ad I'm considering for the Pads designer I need. I'm
posting it here only to get reactions from you all, as PCB experts,
concerning the job responsibilities and requirements. Let me know what you
think, please.
Pads Power Printed Circuit Board Design Engineer/Designer
Serious growing telecommunications company needs serious PCB designer.
Boards consist of several MLB types from 6 to 12 layers with BGA?s, CSP?s,
and other fine pitch devices and attendant components. Both DC and Analog
circuitry reside on these boards and impedance is critical in specified
areas. Designer MUST:
Be very focused on fulfilling responsibilities in a timely, professional
manner
Be capable of working in small company environment under ?quality? pressure
first, then schedule
Be capable of managing design processes for several board types as
management directs priority
Have 5 years minimum experience using Pads Power
Have clear understanding of DFM principles using concurrent engineering (CE)
Have clear understanding of MLB design, fabrication, assembly, and test
requirements
Have clear understanding of microstrip and stripline impedance requirements
Have clear understanding of micro, blind, and buried vias
Have clear understanding of MLB materials, constructions, and solderability
Have clear understanding of MLB?s and all that comprise them
Have AutoCad 14 experience to create mechanicals as master, assembly
drawings, etc.
Have extensive experience working with many component types
Have clear understanding of all applicable IPC guidelines and requirements
Have ability to communicate PCB requirements clearly to management,
purchasing, engineering, and suppliers using concurrent engineering
Have understanding of ISO 9000 (4.6): 94 and/or 2000 (7.3) design control
requirements
Prefer:
MoonMan
----------------------------------------------------------------------------
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=========================================================================
Date: Tue, 26 Mar 2002 08:23:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PADS POWER PCB DESIGNER
X-To: [log in to unmask]
Really do thank you Joseph,
First I'm looking for someone to work in house. Failing that, I will look at
a bureau. However, I must have a senior person capable of doing it all as I
said. I've had too many situations where musical chairs were the game name
and had to jump through hoops to get the job done in a reasonable time.
I know you folks are very professional, but I need complete attention on
these jobs. Quality is first then time then cost. Can't afford to strecht
this thing out for someone else's benefit.
Looking forward to talking more if I can't find a contractor to come in house.
Earl
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Date: Tue, 26 Mar 2002 15:36:39 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Volkmar Huss <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Volkmar Huss <[log in to unmask]>
Organization: =?iso-8859-1?Q?Dr=E4ger?= Electronics GmbH
Subject: Measuring "No Clean" process quality
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DQogIEZheDogKzQ5LTQ1MS04ODItNDM2NQ0KICBtYWlsdG86dm9sa21hci5odXNzQGRyYWVn
ZXIuY29tDQogIFdlYnNpdGUgaHR0cDovL3d3dy5kcmFlZ2VyLmNvbS9kZS9FTA0KICBfIF8g
XyBfIF8gXyBfIF8gXyBfIF8gXyBfIF8gXyBfIF8gXyBfIF8gXyBfIF8NCg0KDQo=
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Date: Tue, 26 Mar 2002 06:57:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: large plastic blocks/bars needed
X-To: Phil Nutting <[log in to unmask]>
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Phil,
As if you don't already have enough choices to look into try,
http://www.polymerplastics.com
I have used them a few times, it's usually easy to get samples but I feel
they are a bit pricey for cutting. Try to have a local shop do the final
cuts.
Dan
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Date: Tue, 26 Mar 2002 09:18:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, jim <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: jim <[log in to unmask]>
Subject: Re: large plastic blocks/bars needed
X-To: "Edward S. Wheeler" <[log in to unmask]>
MIME-Version: 1.0
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The MSC catalog has these and all you have to do is cut them to length and
width ( easily done on a band saw).
give me a call if you need thier number or have any questions.
Jim Gleason
972-494-1911
----- Original Message -----
From: "Edward S. Wheeler" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 26, 2002 6:38 AM
Subject: Re: [TN] large plastic blocks/bars needed
> Call your local machine shop. They should have plenty of catalogs,
possibly
> material in house.
>
> Ed
>
>
> At 02:12 PM 3/25/2002 -0500, you wrote:
> >Good afternoon all,
> >
> >We have a project that needs plastic blocks 6x10x12 (in inches). It can
> >be Polyethylene (Low Density), Polyethylene (High Density), Polypropylene
> >or PVC. "Bar stock" would also work as long as we can cut the above
sized
> >blocks out of it.
> >
> >Any ideas for a source?
> >
> >Thanks in advance,
> >
> >Phil Nutting
> >
>
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Date: Tue, 26 Mar 2002 07:30:07 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
J G <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: J G <[log in to unmask]>
Subject: I'm back
MIME-Version: 1.0
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Hello everybody,
Jason Gregory here. I've been off for a while due to
employment reasons and looking forward to catching up.
It's only been a week or so, but I know a lot can lost
on Technet in only a week. Earl, contact me
directly....I have questions for ya.
Jason Gregory
__________________________________________________
Do You Yahoo!?
Yahoo! Movies - coverage of the 74th Academy Awards®
http://movies.yahoo.com/
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Date: Tue, 26 Mar 2002 08:06:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Re: BGA reballing
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Hi all,
One more temp excursion that hasn't been mentioned is the site prep of =
the pads after de-soldering from the PCB and prior to reballing. We =
developed a system that does this quite nicely with minimal risk of =
lifting pads (something to worry about as well).=20
Our reballer uses a pallet that the devices go through reflow in which =
acts as a heat sink for the topside of the BGA (the part is run balls =
up, bottom side) minimizing thermal stress. There have been several =
studies by fortune 500 companies to determine reliability and this =
method has been approved, however, they are not willing to publish them =
to the world at large.
Once again, my two cents worth.
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
------=_NextPart_000_0012_01C1D49D.33CCD360
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>One more temp excursion that hasn't =
been mentioned=20
is the site prep of the pads after de-soldering from the PCB and prior =
to=20
reballing. We developed a system that does this quite nicely with =
minimal risk=20
of lifting pads (something to worry about as well). </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Our reballer uses a pallet that the =
devices go=20
through reflow in which acts as a heat sink for the topside of the BGA =
(the part=20
is run balls up, bottom side) minimizing thermal stress. There have been =
several=20
studies by fortune 500 companies to determine reliability and this =
method has=20
been approved, however, they are not willing to publish them to the =
world at=20
large.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Once again, my two cents =
worth.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
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Date: Tue, 26 Mar 2002 11:45:42 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: I'm back
X-To: J G <[log in to unmask]>
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Jason,
Talk to me babe,
Earl
----- Original Message -----
From: "J G" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 26, 2002 7:30 AM
Subject: [TN] I'm back
> Hello everybody,
> Jason Gregory here. I've been off for a while due to
> employment reasons and looking forward to catching up.
> It's only been a week or so, but I know a lot can lost
> on Technet in only a week. Earl, contact me
> directly....I have questions for ya.
>
> Jason Gregory
>
> __________________________________________________
> Do You Yahoo!?
> Yahoo! Movies - coverage of the 74th Academy Awards®
> http://movies.yahoo.com/
>
> --------------------------------------------------------------------------
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Date: Tue, 26 Mar 2002 12:25:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Volkmar Huss <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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IPC/ANSI J-STD-004 estabishes methods classification and testing of fluxes.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Volkmar Huss
> Sent: Tuesday, March 26, 2002 9:37 AM
> To: [log in to unmask]
> Subject: [TN] Measuring "No Clean" process quality
>
>
> Hi TechNetters,
>
> we are working on defining our "No Clean" soldering process. The
> solder-paste and flux manufacturers certify the "No Clean" capability of
>
> their products to some extend, but what is the definition of "No Clean"?
>
> And I don't mean the statement, that only inert residues of flux and
> solder-paste additives remain on the board.
> Are there any standards that can used as a reference?
> How do you measure the:
> "No Clean" capability of solder paste, flux and tubular solder with flux
>
> core?
> "No Clean" quality of printed board assemblies?
> "No Clean" quality of printed board assemblies onto which devices have
> been hand-soldered?
> and all of this for prototype and series production?
>
> I have gleaned some insights from the TechNet archives, but any
> additional input is very welcome.
>
> Best regards
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> --
> Best regards / Mit freundlichen Grüßen
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
>
> Mçëj) Ë®‹u籧yë®øy¼<+ x!$ ñÔº{nlj·zw™ëj
> ²M!Tƒ9 Ø¢YÂ)µì {x `Ó¶ ¹¸r×zW
> c Tr µ:zjª—(–×–+¯*Mçëzw™¨¶‚²Û®ør HDyÈzÓ0 N qèx㙨 xz·Ê‡–[zš¶Ë×j
> ) ¸¶Ç¾*¢¸ 4r ´8zËyª†š¾*²š¶)±«Ã r :r䲋qëjÖjÇ f”
> †+°ùjÇ È ðy»µè¶ŸÃ > ¥Êƒøš_¢»†Ù¢¶v+¢v w®f ‰Êµ§)æ…&jj‰«jÆ¢*¢¸¯ÎçOïMÆÞ
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Date: Tue, 26 Mar 2002 11:03:14 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Vitronics Isotherm 500
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Hi all,
I'm looking for a "used" manual for a Vitronics Isotherm 500C. Can =
anyone help here?
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
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<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I'm looking for a "used" manual for a =
Vitronics=20
Isotherm 500C. Can anyone help here?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
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Date: Tue, 26 Mar 2002 15:14:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Double Sided Reflow Flux and surface tension
Mime-Version: 1.0
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Hello Tech-Net users! I am new to the group here, and would like your
assistance on a couple of matters concerning a double sided reflow process
we are undertaking. We are new to this process, so we would appreciate any
expertise on the matter.
We are using an OA type solder paste, and like to wash our boards within 2
hours, 4 being the maximum in house limit. To perform our double sided
reflow process in mass production, we may want to run all day on one side
and do the other side the next. My question is... does any of the residual
flux material aid the second reflow process, or can we wash it off before
the second reflow and get as good of results? I am concerned that the
solder joint may have an outer layer of oxidation or graininess due to the
lack of flux once it reflows again. Is there any flux left over that is
active, or is it simply the remainder of the carrier?
What luck are people having with BGAs populated on the bottom side? Is
there more of a concern with warp on the second pass?
Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?
Does anybody use adhesives to stake heavy parts on the first pass?
Does anybody have a solid rule of thumb for pin-in-paste apertures? On our
first try we used an 8 mil step up and had the aperture the same size as
outer edge of the PTH. Would an oversize print work better?
Thanks in advance for any help.
Ed
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Date: Tue, 26 Mar 2002 15:00:56 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Double Sided Reflow Flux and surface tension
X-To: Edward Wheeler <[log in to unmask]>
Ed,
You ask some of the best questions ever even though they've been covered
before. I'm not one to welcome anyone but WELCOME.
I'm only answering with no answers to ilicit more responses even though I've
been involved in most of what you're attempting. It all works so stand by
for some very specific answers to your postings.
Earl Moon
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Date: Tue, 26 Mar 2002 16:45:09 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Re: Vitronics Isotherm 500
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Have you tried contacting Vitronics-Soltec and asking for a copy of the
manual ? Their number (in Stratham, NH) is 603-772-7778.
Phil Zarrow
ITM Consulting
Durham, NH USA
www.ITM-SMT.com
T: (603) 868-1754
F: (603) 868-3623
EM:[log in to unmask]
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Have you tried contacting Vitronics-Soltec and asking for a copy of the manual ? Their number (in Stratham, NH) is 603-772-7778. <BR>
<BR>
Phil Zarrow<BR>
<BR>
<B>ITM Consulting <BR>
Durham, NH USA<BR>
www.ITM-SMT.com<BR>
T: (603) 868-1754<BR>
F: (603) 868-3623<BR>
EM:[log in to unmask]</B></FONT></HTML>
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Date: Tue, 26 Mar 2002 15:33:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: ICT
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G'day
Was asked if I could come up with some information on ICT.
Where can I find if any on standards that govern ICT "if any" or
how to's on fixturing etc.
Barry.
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Date: Wed, 27 Mar 2002 01:32:58 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Volkmar Huss <[log in to unmask]>
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Volkmar
Manufacturers of fluxes produce and sell a wide range of fluxes which
are sold as "no-clean". Some contain rosin, others don't. Some contain
halogenated activators, others don't. Some are very active and are
consequently easy to solder with, but leave more dangerous residues,
others don't, but are the devil to solder with. Some you can clean,
others you cannot.
To answer your questions: you have to select a shortlist of, say, 5
fluxes which meet your criteria, on paper. You then do extensive trials,
with various parameters (Taguchi is very useful for this, as you can cut
the number of experiments drastically). After having optimised the
process for each flux, you have to produce some test boards that you
need to qualify as meeting your requirements for reliability under the
conditions the boards will be used in (electrochemical migration etc.)
and for setting up your process for quality control. As a result of
this, you can select your #1 candidate and #2 to fall back on if there
is an interruption of supply. No one here can do your homework for you,
I'm afraid.
Brian
Volkmar Huss wrote:
>
> Hi TechNetters,
>
> we are working on defining our "No Clean" soldering process. The
> solder-paste and flux manufacturers certify the "No Clean" capability of
>
> their products to some extend, but what is the definition of "No Clean"?
>
> And I don't mean the statement, that only inert residues of flux and
> solder-paste additives remain on the board.
> Are there any standards that can used as a reference?
> How do you measure the:
> "No Clean" capability of solder paste, flux and tubular solder with flux
>
> core?
> "No Clean" quality of printed board assemblies?
> "No Clean" quality of printed board assemblies onto which devices have
> been hand-soldered?
> and all of this for prototype and series production?
>
> I have gleaned some insights from the TechNet archives, but any
> additional input is very welcome.
>
> Best regards
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> --
> Best regards / Mit freundlichen Grüßen
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> Mç!ëLj)K Ëi®‹âuçZ±§ëyë ®øœy¼ˆ<+¬ x!$Ò uñÔèº{.nÇ+‰·¬zwZ™ë,j ² M! TƒÂ9 ° Ø_¢YhÂ)àµìm {ax ƒ`Ó“¶ ¬¹¸Þr×âzWR cN TÞr Þµ:-zjhªâ—(Z–×^–+Þ¯* Mç!ëlzw^™¨¥¶‚â²Û ®ø©r àHDÓyÈgzÓN0 N Þqè¯xãD™¨¥ x)z·Zʇږ[azš,¶Ë צj)m ¸¬¶Ç«¾*\¢¸ 4Þr Þ´8 zËRyªÜ†šÞ¾*.²š,¶)౫pà ©r à:râä^²‹«që jÖ›jǬ f¢”
> ܆+Þ°ù^jǯ È ð°y»"µèm¶ŸÿÃ"¥Ê+ƒømš_ߢ»¦†ÙŸ¢¶v+b¢v¥ wè®f ‰èÊ'µ§-)朅&¬jj+‰«ljƤ¢*\¢¸(¯Î;çO}ïM ÆÞw15==
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Date: Tue, 26 Mar 2002 15:38:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
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This e-mail may contain SEL confidential information. The opinions expressed
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other use is prohibited. If you received this e-mail in error, please notify
the sender, permanently delete it, and destroy any printout. Thank you.
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Date: Wed, 27 Mar 2002 11:32:32 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
DUTTON Phil <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: DUTTON Phil <[log in to unmask]>
Subject: Re: ICT
X-To: Barry Gallegos <[log in to unmask]>
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Hello Barry,
IPC-2221 3.5 has some good info on testing and In Circuit Testing design
requirements.
Can be quite involved, and the circuit design needs to consider the test
requirements as well. Test probe lands are typically 0.040" and pitched at
0.100" centres for bed-of-nails type test fixtures. Different types/sizes of
probe pins are available.
Good idea to talk to the people who will be testing your boards very early.
Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer
-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Wednesday, 27 March 2002 09:03
To: [log in to unmask]
Subject: [TN] ICT
G'day
Was asked if I could come up with some information on ICT.
Where can I find if any on standards that govern ICT "if any" or
how to's on fixturing etc.
Barry.
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Date: Tue, 26 Mar 2002 20:45:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Thin Laminates with low dielectric constant..
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Hi all,
Just checking with everyone, but looking for a laminate that can stay at
3-mils with half ounce copper plated for the features, and can maintain a Er
of 3-5...know that's asking a lot...we're trying to push the envelope with a
VME card, and use Stablecor material...I think that Stablecor has great
potential...just gotta shrink everything else.
Found a site that talks about a product called SpeedBoard C that is very
thin, and improves the dielectric constant when used with standard core
materials. Go to:
http://www.goreelectronics.com/products/dielectric_materials/Speedboard_C_Prep
reg.cfm
Trying to pack a 16-layer board (including Stablecor material) to stay under
.070"...fun stuff huh?
Have any of you had any experience with SpeedBoard C?
As always, thanks in advance...
-Steve Gregory-
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Date: Wed, 27 Mar 2002 09:48:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating BGA's
X-To: "Misner, Bruce" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Bruce,
We apply Humiseal acrylic coating to boards that fit your description and
application precisely, except that we do underfill the BGA's with a
reworkable epoxy, applied after assembly. The only exception was for the
case of two boards destined for temperature cycling measurement, for which
we couldn't get a supply of underfill material at the time. We substituted
thinned Humiseal as the boards would not be flying, as we were concerned
about entrapped air and also no suuport for the BGA joints. Humiseal is not
a proper substitute for the specialised proper epoxy, but was sufficient
for our particular purpose.
The main issue as I see it would be moisture and other contaminants in the
entrapped air, but I have no first hand data to help you decide if that
causes problems or not.
Good luck
Peter
"Misner,
Bruce" To: [log in to unmask]
<Bruce_Misner cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
@ATK.COM> Aero/ST Group)
Sent by: Subject: [TN] Conformal Coating BGA's
TechNet
<[log in to unmask]
ORG>
03/20/02
03:48 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Misner,
Bruce"
My question of the day: Is anyone conformal coating (not parylene) plastic
BGA's on FR-4 in Hi-Rel applications (aircraft; -20 to +71C ambient
operating temperature requirement) without benefit of an underfil? If yes,
has entrapped air been a major issue? Anyone care to comment on this
approach?
Regards,
Bruce Misner
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Date: Tue, 26 Mar 2002 20:20:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Brian Ellis <[log in to unmask]>
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Brian,
Well said!!!
Particularly the qualification testing part!
David A. Douthit
Manager
LoCan LLC
Brian Ellis wrote:
> Volkmar
>
> Manufacturers of fluxes produce and sell a wide range of fluxes which
> are sold as "no-clean". Some contain rosin, others don't. Some contain
> halogenated activators, others don't. Some are very active and are
> consequently easy to solder with, but leave more dangerous residues,
> others don't, but are the devil to solder with. Some you can clean,
> others you cannot.
>
> To answer your questions: you have to select a shortlist of, say, 5
> fluxes which meet your criteria, on paper. You then do extensive trials,
> with various parameters (Taguchi is very useful for this, as you can cut
> the number of experiments drastically). After having optimised the
> process for each flux, you have to produce some test boards that you
> need to qualify as meeting your requirements for reliability under the
> conditions the boards will be used in (electrochemical migration etc.)
> and for setting up your process for quality control. As a result of
> this, you can select your #1 candidate and #2 to fall back on if there
> is an interruption of supply. No one here can do your homework for you,
> I'm afraid.
>
> Brian
>
> Volkmar Huss wrote:
> >
> > Hi TechNetters,
> >
> > we are working on defining our "No Clean" soldering process. The
> > solder-paste and flux manufacturers certify the "No Clean" capability of
> >
> > their products to some extend, but what is the definition of "No Clean"?
> >
> > And I don't mean the statement, that only inert residues of flux and
> > solder-paste additives remain on the board.
> > Are there any standards that can used as a reference?
> > How do you measure the:
> > "No Clean" capability of solder paste, flux and tubular solder with flux
> >
> > core?
> > "No Clean" quality of printed board assemblies?
> > "No Clean" quality of printed board assemblies onto which devices have
> > been hand-soldered?
> > and all of this for prototype and series production?
> >
> > I have gleaned some insights from the TechNet archives, but any
> > additional input is very welcome.
> >
> > Best regards
> >
> > Volkmar Huß
> >
> > Engineering Electronic Circuit Boards
> > Aufbau- und Verbindungstechnik
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > DRÄGER ELECTRONICS
> >
> > Draeger Electronics GmbH
> > Moislinger Allee 53-55
> > D-23558 Lübeck
> >
> > Tel: +49-451-882-3998
> > Fax: +49-451-882-4365
> > mailto:[log in to unmask]
> > Website http://www.draeger.com/de/EL
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > --
> > Best regards / Mit freundlichen Grüßen
> >
> > Volkmar Huß
> >
> > Engineering Electronic Circuit Boards
> > Aufbau- und Verbindungstechnik
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > DRÄGER ELECTRONICS
> >
> > Draeger Electronics GmbH
> > Moislinger Allee 53-55
> > D-23558 Lübeck
> >
> > Tel: +49-451-882-3998
> > Fax: +49-451-882-4365
> > mailto:[log in to unmask]
> > Website http://www.draeger.com/de/EL
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > Mç!*ëLj)K Ëi®?âuçZ±§ëyë ®øœy*ˆ<+¬ x!$Ò uñÔèº{.nÇ+‰·¬zwZ™ë,j ? 2 M! TƒÂ9 ° Ø_¢YhÂ)àµìm {ax ƒ`Ó“¶ ¬1¸?rxâzWR cN T?r ?µ:-zjh?ªâ—(Z?x^?+?¯* Mç!*ëlzw^™¨¥¶‚â2Û ®ø©r àHDÓyÈgzÓN0 N ?qè¯xãD™¨¥ x)z·ZÊ?Ú?[azs,¶Ë *x|j)m ¸¬¶Ç«**\¢¸ 4?r ?´8 zËRyªÜ?s?**.2s,¶)౫pà ©r à:râ*ä^2?«që jÖ?jǬ f¢”
> > Ü?+?°ù^jǯ È? ?°y»"µèm¶ŸÿÃ"¥Ê+ƒøms_ߢ»|?ÙŸ¢¶*v+b¢v¥ wè®f? ‰è?Ê'µ§-)朅&¬jj+‰«ljÆ€¢*\¢¸(¯Î;çO}ïM Æ?w15==
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Wed, 27 Mar 2002 01:04:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: another materials question
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I'm learning about laminate materials and read with interest several recent
tecnet emails on the subject.
I'd like to submit a question about a particular construction that is a
challenge with respect to registration.
The construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The construction
is balanced with respect to copper weights, glass styles, core thicknesses,
and prepreg openings.
What I am observing with this part is variation in how much certain cores
shrink, lot to lot,
and variation that I would describe as a shift or possibly a rotation in some
of the internal layers.
Am I correct in assuming that these thin cores and these particular prepregs
will contribute to lower yields due to misregistration? If anyone would
care to offer up ideas on how to tackle the registration challenge that I am
observing on this kind of construction, I would appreciate hearing your ideas.
Mark J.
--part1_157.b36cee5.29d2baf1_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I'm learning about laminate materials and read with interest several recent tecnet emails on the subject.
<BR>I'd like to submit a question about a particular construction that is a challenge with respect to registration.
<BR>
<BR>The construction is all 2 core and 3 core. The prepregs are 1-106 and 1-1080, which I have learned are described as resin rich. The construction is balanced with respect to copper weights, glass styles, core thicknesses, and prepreg openings.
<BR>
<BR>What I am observing with this part is variation in how much certain cores shrink, lot to lot,
<BR>and variation that I would describe as a shift or possibly a rotation in some of the internal layers.
<BR>
<BR>Am I correct in assuming that these thin cores and these particular prepregs will contribute to lower yields due to misregistration? If anyone would care to offer up ideas on how to tackle the registration challenge that I am observing on this kind of construction, I would appreciate hearing your ideas.
<BR>
<BR>Mark J.</FONT></HTML>
--part1_157.b36cee5.29d2baf1_boundary--
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Date: Wed, 27 Mar 2002 10:11:27 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Busko, Wolfgang" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Brian,=20
short and to the point, really a nice one.
But knowing a bit about the special situation, and I think that=B4s =
also true
for many other small- and mediumsize CM=B4s, there is no or only vague
knowledge regarding the precise requirements for reliability under
(sometimes)not very well known conditions.
It=B4s also often a question of time and resources to perform all =
necessary
steps to get where you want or need to be.
The first and IMHO most important step is to agree on the criteria one =
wants
to meet, the rest is business and routine. To master this first =
"obstacle"
it might be best for many in the same situation to look for external
assistance especially regarding the necessary testing that has to be =
done
during qualifying.
In Volkmars case I would discuss that topic also with ISIT, an =
institute
that does a lot of the needed qualification tests and offers consulting =
for
the electronic industry. I think he knows the contact already.
Greetings from sunny but still cold Hamburg
Wolfgang
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: Wednesday, March 27, 2002 12:33 AM
> To: [log in to unmask]
> Subject: Re: [TN] Measuring "No Clean" process quality
>=20
>=20
> Volkmar
>=20
> Manufacturers of fluxes produce and sell a wide range of fluxes which
> are sold as "no-clean". Some contain rosin, others don't. Some =
contain
> halogenated activators, others don't. Some are very active and are
> consequently easy to solder with, but leave more dangerous residues,
> others don't, but are the devil to solder with. Some you can clean,
> others you cannot.
>=20
> To answer your questions: you have to select a shortlist of, say, 5
> fluxes which meet your criteria, on paper. You then do=20
> extensive trials,
> with various parameters (Taguchi is very useful for this, as=20
> you can cut
> the number of experiments drastically). After having optimised the
> process for each flux, you have to produce some test boards that you
> need to qualify as meeting your requirements for reliability under =
the
> conditions the boards will be used in (electrochemical migration =
etc.)
> and for setting up your process for quality control. As a result of
> this, you can select your #1 candidate and #2 to fall back on if =
there
> is an interruption of supply. No one here can do your=20
> homework for you,
> I'm afraid.
>=20
> Brian
>=20
> Volkmar Huss wrote:
> >
> > Hi TechNetters,
> >
> > we are working on defining our "No Clean" soldering process. The
> > solder-paste and flux manufacturers certify the "No Clean"=20
> capability of
> >
> > their products to some extend, but what is the definition=20
> of "No Clean"?
> >
> > And I don't mean the statement, that only inert residues of flux =
and
> > solder-paste additives remain on the board.
> > Are there any standards that can used as a reference?
> > How do you measure the:
> > "No Clean" capability of solder paste, flux and tubular=20
> solder with flux
> >
> > core?
> > "No Clean" quality of printed board assemblies?
> > "No Clean" quality of printed board assemblies onto which=20
> devices have
> > been hand-soldered?
> > and all of this for prototype and series production?
> >
> > I have gleaned some insights from the TechNet archives, but any
> > additional input is very welcome.
> >
> > Best regards
> >
> > Volkmar Hu=DF
> >
> > Engineering Electronic Circuit Boards
> > Aufbau- und Verbindungstechnik
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > DR=C4GER ELECTRONICS
> >
> > Draeger Electronics GmbH
> > Moislinger Allee 53-55
> > D-23558 L=FCbeck
> >
> > Tel: +49-451-882-3998
> > Fax: +49-451-882-4365
> > mailto:[log in to unmask]
> > Website http://www.draeger.com/de/EL
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > --
> > Best regards / Mit freundlichen Gr=FC=DFen
> >
> > Volkmar Hu=DF
> >
> > Engineering Electronic Circuit Boards
> > Aufbau- und Verbindungstechnik
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > DR=C4GER ELECTRONICS
> >
> > Draeger Electronics GmbH
> > Moislinger Allee 53-55
> > D-23558 L=FCbeck
> >
> > Tel: +49-451-882-3998
> > Fax: +49-451-882-4365
> > mailto:[log in to unmask]
> > Website http://www.draeger.com/de/EL
> > _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
> >
> > M=E7!=9D=EBLj)K =CBi=AE<=E2u=E7Z=B1=A7=EBy=EB =AE=F8oey=BC^<+=AC =
x!$=D2 =20
> u=F1=D4=E8=BA{.n=C7+?=B7=ACzwZ(tm)=EB,j =AD =B2 M! Tf=C29 =B0 =
=D8_=A2Yh=C2)=E0=B5=ECm {ax f`=D3"=B6=20
> =AC=B9=B8=DEr=D7=E2zWR cN T=DEr =DE=B5:-zjh=AD=AA=E2-(Z-=D7^-+=DE=AF* =
M=E7!=9D=EBlzw^(tm)=A8=A5=B6'=E2=B2=DB=20
> =AE=F8=A9r =E0HD=D3y=C8gz=D3N0 N =DEq=E8=AFx=E3D(tm)=A8=A5 =
x)z=B7Z=CA?=DA-[azs,=B6=CB =9D=D7=A6j)m=20
> =B8=AC=B6=C7=AB=BE*\=A2=B8 4=DEr =DE=B48 =
z=CBRy=AA=DC?s=DE=BE*.=B2s,=B6)=E0=B1=ABp=C3 =A9r =
=E0:r=E2=9D=E4^=B2<=ABq=EB j=D6>j=C7=AC f=A2"
> > =DC?+=DE=B0=F9^j=C7=AF =C8=AD =
=F0=B0y=BB"=B5=E8m=B6Y=FF=C3"=A5=CA+f=F8ms_=DF=A2=BB=A6?=D9Y=A2=B6=9Dv+b=
=A2v=A5 w=E8=AEf=AD=20
> =
?=E8=AD=CA'=B5=A7-)=E6oe...&=ACjj+?=ABlj=C6=A4=A2*\=A2=B8(=AF=CE;=E7O}=EF=
M =C6=DEw15=3D=3D
>=20
> --------------------------------------------------------------
> -------------------
> Technet Mail List provided as a free service by IPC using=20
> LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with=20
> following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to=20
> [log in to unmask]: SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail=20
> to [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources=20
> & Databases > E-mail Archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm=20
> for additional
> information, or contact Keach Sasamori at [log in to unmask] or=20
> 847-509-9700 ext.5315
> --------------------------------------------------------------
> -------------------
>=20
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Date: Wed, 27 Mar 2002 06:25:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Thin Laminates with low dielectric constant..
X-To: [log in to unmask]
Steve,
The Gore material works well. As we've discussed before, and as I indicated
in Marks questions, this is, currently, a highly specialized part of the MLB
world. I know you must do what you need and have selected one or more
qualified suppliers with many more lurking in the wings. The big caustion,
as you already know, is those lurking having transitioned from more common
board types to hi-rel types.
Gore presents its lamination press cycles to get full "cure." This is a two
stage press cycle (A and B( and a critical cool down cycle. The cycles are
similar to other "hi-rel" MLB requirements as polyimide and GTEK. The
"ordinary" fab folks are very happy with a much simpler cycle going to full
pressure and temperature in one big move for about 90 minutes and POP, it's
out of there and enjoyed by all commercial folks.
As for the thin core/preg stuff, I outlined that in my response to Mark
below. No matter, we must continue pushing the envelope in all we do, so why
not here.
You live the good life Steve, according to:
The MoonMan
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Date: Wed, 27 Mar 2002 07:08:36 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: another materials question
X-To: [log in to unmask]
Mark,
Good study and good questions though I wrote a much better reply before but
it didn't take because of my ignorance in taking too much time the first
time. So, here goes again.
Mark: I'm learning about laminate materials and read with interest several
recent tecnet emails on the subject. I'd like to submit a question about a
particular construction that is a challenge with respect to registration.
Earl: Wish I simply copy what I wrote earlier. Registration, as all
specified requirements, suffers when bad design choices are made concerning
material selections and MLB constructions. You already know that.
Mark: The construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The construction
is balanced with respect to copper weights, glass styles, core thicknesses,
and prepreg openings.
Earl: Unless selecting and using relatively exotic materials, you must stay
away from very thin core/preg materials for several reasons. If you're
serious about making your own capacitance cores you must consider foil
choices as not ED copper unless tooth faicing out. Of course, there is a
patent issues as well though I still don't know why. You will need to use
rolled copper unless as stated above with ED. Again, because the thin
core/pregs are so resin rich, you face dimensional issues both in the press
and in product significantly reducing yelds mostly because of
misregistration issues.
Mark: What I am observing with this part is variation in how much certain
cores shrink, lot to lot, and variation that I would describe as a shift or
possibly a rotation in some of the internal layers.
Earl: Don't know all what you mean by shrinkage but core variability should
not be an as received issue. It is when married with very thin, resin rich
stuff as you describe (106 and 1080). These glass styles are so juicy they
slip and slide in the press and books therein. I have images depicting
relamination dynamics and, if you wish, I'll ask Steve Gregory to post them.
There is so much more to this, but the general idea, unless pushing the
envelope like Steve, you should carefully consider your options as design
compromises faced every day by GOOD designers and fabricators.
I wanted to write more, and did before this, but time prohibits.
Best wishes,
Earl
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Date: Wed, 27 Mar 2002 08:38:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: another materials question
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_000C_01C1D56A.D6931E60"
This is a multi-part message in MIME format.
------=_NextPart_000_000C_01C1D56A.D6931E60
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Mark,
You should not assume that poor yields are a result of material =
shrinkage.
A good board fabrication shop should be able to predict how much =
shrinkage
occurs during normal fabrication of one's laminate. Yes shrinkage does =
vary
from supplier to supplier, but it should be consistent. For instance we =
here
at AIT use a ton of .005 1/1 cores and we will compensate(scale) the =
image
so that by the time the board is complete it will be at 1:1. This may =
mean
that we start a job some .015-.03 over 1:1 in the beginning.
Tony Steinke
----- Original Message -----=20
From: [log in to unmask]
To: [log in to unmask]
Sent: Tuesday, March 26, 2002 10:04 PM
Subject: [TN] another materials question
I'm learning about laminate materials and read with interest several =
recent tecnet emails on the subject.=20
I'd like to submit a question about a particular construction that is =
a challenge with respect to registration.=20
The construction is all 2 core and 3 core. The prepregs are 1-106 and =
1-1080, which I have learned are described as resin rich. The =
construction is balanced with respect to copper weights, glass styles, =
core thicknesses, and prepreg openings.=20
What I am observing with this part is variation in how much certain =
cores shrink, lot to lot,=20
and variation that I would describe as a shift or possibly a rotation =
in some of the internal layers. =20
Am I correct in assuming that these thin cores and these particular =
prepregs will contribute to lower yields due to misregistration? If =
anyone would care to offer up ideas on how to tackle the registration =
challenge that I am observing on this kind of construction, I would =
appreciate hearing your ideas.=20
Mark J.=20
------=_NextPart_000_000C_01C1D56A.D6931E60
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#fff8e0>
<DIV><FONT face=3DArial size=3D2>Mark,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>You should not assume that poor yields =
are a result=20
of material shrinkage.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>A good board fabrication shop should be =
able to=20
predict how much shrinkage</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>occurs during normal fabrication of =
one's laminate.=20
Yes shrinkage does vary</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>from supplier to supplier, but it =
should be=20
consistent. For instance we here</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>at AIT use a ton of .005 1/1 cores and =
we will=20
compensate(scale) the image</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>so that by the time the board is =
complete it will=20
be at 1:1. This may mean</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>that we start a job some .015-.03 over =
1:1 in the=20
beginning.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Tony Steinke</FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, March 26, 2002 =
10:04=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] another materials =
question</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>I'm =
learning about=20
laminate materials and read with interest several recent tecnet emails =
on the=20
subject. <BR>I'd like to submit a question about a particular =
construction=20
that is a challenge with respect to registration. <BR><BR>The =
construction is=20
all 2 core and 3 core. The prepregs are 1-106 and 1-1080, which =
I have=20
learned are described as resin rich. The construction is =
balanced=20
with respect to copper weights, glass styles, core thicknesses, and =
prepreg=20
openings. <BR><BR>What I am observing with this part is variation in =
how much=20
certain cores shrink, lot to lot, <BR>and variation that I would =
describe as a=20
shift or possibly a rotation in some of the internal layers. =
<BR><BR>Am=20
I correct in assuming that these thin cores and these particular =
prepregs will=20
contribute to lower yields due to misregistration? If =
anyone would=20
care to offer up ideas on how to tackle the registration challenge =
that I am=20
observing on this kind of construction, I would appreciate hearing =
your ideas.=20
<BR><BR>Mark J.</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_000C_01C1D56A.D6931E60--
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Date: Wed, 27 Mar 2002 08:48:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: ICT
X-To: DUTTON Phil <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Barry,
If your board is highly populated, and test point space is at a premium, you
can go do to a .035 square pad on .070 centers.
But you need a very good fixture house.
Good luck,
Kerry
-----Original Message-----
From: DUTTON Phil [mailto:[log in to unmask]]
Sent: Tuesday, March 26, 2002 7:33 PM
To: [log in to unmask]
Subject: Re: [TN] ICT
Hello Barry,
IPC-2221 3.5 has some good info on testing and In Circuit Testing design
requirements.
Can be quite involved, and the circuit design needs to consider the test
requirements as well. Test probe lands are typically 0.040" and pitched at
0.100" centres for bed-of-nails type test fixtures. Different types/sizes of
probe pins are available.
Good idea to talk to the people who will be testing your boards very early.
Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer
-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Wednesday, 27 March 2002 09:03
To: [log in to unmask]
Subject: [TN] ICT
G'day
Was asked if I could come up with some information on ICT.
Where can I find if any on standards that govern ICT "if any" or
how to's on fixturing etc.
Barry.
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Date: Wed, 27 Mar 2002 08:19:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Hafften <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Hafften <[log in to unmask]>
Subject: Imaging Clean Rooms
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We are in the process of evaluating our clean room for inner and outer layer
circuit imaging. I am interested in finding out more information on the use
of clean rooms for printed circuit processing, particularly imaging. This
would include not only clean room requirements for imaging .003" lines but
also methods to achieve the required level of cleanliness. There seems to
be alot of information for processing microelectronics but not for printed
circuits. Thanks in advance for any help.
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Date: Wed, 27 Mar 2002 07:08:22 -0800
Reply-To: Leo Roos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leo Roos <[log in to unmask]>
Subject: Re: Imaging Clean Rooms
X-To: Ken Hafften <[log in to unmask]>
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Some years ago PCFab had a series of articles in the same issue addressing
clean rooms. Major article was written by Bob Almond of Dupont. It provided
a great deal of information that we used in the building of our own clean
rooms. You might also try Dr. Karl Dietz ant Dupont, located at RTP, NC.
Leo Roos
----- Original Message -----
From: "Ken Hafften" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 27, 2002 6:19 AM
Subject: [TN] Imaging Clean Rooms
> We are in the process of evaluating our clean room for inner and outer
layer
> circuit imaging. I am interested in finding out more information on the
use
> of clean rooms for printed circuit processing, particularly imaging. This
> would include not only clean room requirements for imaging .003" lines but
> also methods to achieve the required level of cleanliness. There seems to
> be alot of information for processing microelectronics but not for printed
> circuits. Thanks in advance for any help.
>
> --------------------------------------------------------------------------
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Date: Wed, 27 Mar 2002 09:05:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: another materials question
X-To: [log in to unmask]
Outstanding Tony. Your statistical database must be extensive.
Earl
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Date: Wed, 27 Mar 2002 10:11:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: solder mask tape dots
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Here is another question for all you gurus.
We have a hand build, through hole circuit board that has 8 locations =
that must be free of solder for the next level of assembly. So far I =
can only find solder mask tape dots at Contact East. Are there any other =
suppliers out there? Our terminal measures 0.28 inch diameter, so a =
0.3" pad might be just the thing.
Thanks in advance,
Phil
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Date: Wed, 27 Mar 2002 15:15:17 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: another materials question
X-To: [log in to unmask]
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boundary="----=_NextPartTM-000-55ad74b0-4191-11d6-9bf6-00508bf7df76"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------=_NextPartTM-000-55ad74b0-4191-11d6-9bf6-00508bf7df76
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1D5A2.33A19410"
------_=_NextPart_001_01C1D5A2.33A19410
Content-Type: text/plain;
charset="iso-8859-1"
Hi Mark,
You should be able to dial this job in like any other but it may take an
iterative process. Thin core shouldn't translate into always having lower
yields - it might require tweaking the artwork comp. factors. Thinner
materials do like to shrink up (relax) once you etch the copper off.
Good registration requires understanding what the materials are doing
through the imaging to lamination processes. I'm stronger in the lam
department than artwork area but somebody else can cover for me.
If you really do have excessive core shrinkage (lot to lot) then I'd get
your lam supplier in there double quick to explain what's going on in their
process. Have you verified that your Artwork, Imaging & Lamination process
is in control?
Artwork - temp. & humidity within spec., best available artwork comp.
factors per sheet.
Imaging - Artwork & core stabilized, job running on one imaging unit
Lamination - Lamin. Pins and Bushings not overly worn, PEP data consistent
It sounds like you are having random registration problems - is that true on
all your layers or only some? Can you describe the misregistration better?
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask] <mailto:[log in to unmask]>
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, March 27, 2002 1:05 AM
To: [log in to unmask]
Subject: [TN] another materials question
I'm learning about laminate materials and read with interest several recent
tecnet emails on the subject.
I'd like to submit a question about a particular construction that is a
challenge with respect to registration.
The construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The construction
is balanced with respect to copper weights, glass styles, core thicknesses,
and prepreg openings.
What I am observing with this part is variation in how much certain cores
shrink, lot to lot,
and variation that I would describe as a shift or possibly a rotation in
some of the internal layers.
Am I correct in assuming that these thin cores and these particular prepregs
will contribute to lower yields due to misregistration? If anyone would
care to offer up ideas on how to tackle the registration challenge that I am
observing on this kind of construction, I would appreciate hearing your
ideas.
Mark J.
------_=_NextPart_001_01C1D5A2.33A19410
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Hi
Mark,</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>You should be able to
dial this job in like any other but it may take an iterative process. Thin
core shouldn't translate into always having lower yields - it might require
tweaking the artwork comp. factors. Thinner materials do like to shrink up
(relax) once you etch the copper off.</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Good registration
requires understanding what the materials are doing through
the imaging to lamination processes. I'm stronger in the lam
department than artwork area but somebody else can cover for
me. </FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002> <FONT color=#0000ff>If you really do
have excessive core shrinkage (lot to lot) then I'd get your lam supplier
in there double quick to explain what's going on in their process.
Have you verified that your Artwork, Imaging & Lamination process
is in control? </FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Artwork - temp. &
humidity within spec., best available artwork comp. factors per
sheet.</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Imaging - Artwork &
core stabilized, job running on one imaging unit</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Lamination - Lamin. Pins
and Bushings not overly worn, PEP data consistent</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>It sounds like you
are having random registration problems - is that true on all your
layers or only some? Can you describe the misregistration
better?</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT color=#0000ff></FONT><BR><FONT
face=Verdana>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</FONT> <BR><FONT
face=Verdana>Hans M. Hinners</FONT> <BR><FONT face=Verdana>Electronics
Engineer</FONT> <BR><FONT face=Verdana>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)</FONT> <BR><FONT face=Verdana>226 Cochran Street</FONT> <BR><FONT
face=Verdana>Robins AFB GA 31098-1622</FONT> </DIV>
<DIV>
<P><FONT face=Verdana><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A></FONT>
</P>
<P><FONT face=Verdana>Com: (478) 926 - 5224</FONT> <BR><FONT
face=Verdana>Fax: (478) 926 - 4911</FONT> <BR><FONT face=Arial
size=2>DSN Prefix: 468</FONT> </P></SPAN></DIV>
<DIV><SPAN class=109463214-27032002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, March 27, 2002 1:05
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] another materials
question<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>I'm
learning about laminate materials and read with interest several recent tecnet
emails on the subject. <BR>I'd like to submit a question about a particular
construction that is a challenge with respect to registration. <BR><BR>The
construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The
construction is balanced with respect to copper weights, glass styles, core
thicknesses, and prepreg openings. <BR><BR>What I am observing with this part
is variation in how much certain cores shrink, lot to lot, <BR>and variation
that I would describe as a shift or possibly a rotation in some of the
internal layers. <BR><BR>Am I correct in assuming that these thin cores
and these particular prepregs will contribute to lower yields due to
misregistration? If anyone would care to offer up ideas on how to
tackle the registration challenge that I am observing on this kind of
construction, I would appreciate hearing your ideas. <BR><BR>Mark J.</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 27 Mar 2002 10:16:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Thin Laminates with low dielectric constant..
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Steve,
Have you thought of using Kapton (adhesiveless -offcourse) to build the brd with. THis is very proven technology (rigid-flex). Pricy, but can't imagine it to be much more than SpeedBoard.
We have build brds with Kapton to provide thin brds w/ high layer count. Benefits:-
1) Er of 3.2-3.6.
2) Can use 2 mil thick material.. 2 mil thick has been used in rigid-flex for years.
Call offline if you want to discuss further.
Rush
818.768.3919
www.accueng.com
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Date: Wed, 27 Mar 2002 18:29:48 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Volkmar Huss <[log in to unmask]>
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Bruno
As they say in the country where I used to live, "Groezi wohl" to kalt
Hamburg. Yes, I agree that outside consultancy can help and probably be
cheaper in the long run, provided that Volkmar has researched the
problem sufficiently to be able to define the terms of reference. If he
leaves this open-ended, then it will cost zillions and may not get
optimum results.
My experience as a consultant is that most clients approach me saying
that they want to change from x cleaning method to y cleaning method or
z not to clean at all, without having a clue what is involved. It
typically doubles the cost of the consultancy if they have not
previously defined at least a baseline, because the act of definition
gives them a much clearer mind and how to go about it. Another stumbling
block is that, prior to visiting the site, I'm sometimes misinformed as
to things like available equipment, end use conditions etc. which means
that my preparation is often of limited use (I minimalise preparation,
now, for that reason).
Greetings from a cold and sunny Washington DC (back to the warmth of
Cyprus by Friday!).
Brian
Volkmar Huss wrote:
>
> Hi TechNetters,
>
> we are working on defining our "No Clean" soldering process. The
> solder-paste and flux manufacturers certify the "No Clean" capability of
>
> their products to some extend, but what is the definition of "No Clean"?
>
> And I don't mean the statement, that only inert residues of flux and
> solder-paste additives remain on the board.
> Are there any standards that can used as a reference?
> How do you measure the:
> "No Clean" capability of solder paste, flux and tubular solder with flux
>
> core?
> "No Clean" quality of printed board assemblies?
> "No Clean" quality of printed board assemblies onto which devices have
> been hand-soldered?
> and all of this for prototype and series production?
>
> I have gleaned some insights from the TechNet archives, but any
> additional input is very welcome.
>
> Best regards
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> --
> Best regards / Mit freundlichen Grüßen
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> Mç!ëLj)K Ëi®‹âuçZ±§ëyë ®øœy¼ˆ<+¬ x!$Ò uñÔèº{.nÇ+‰·¬zwZ™ë,j ² M! TƒÂ9 ° Ø_¢YhÂ)àµìm {ax ƒ`Ó“¶ ¬¹¸Þr×âzWR cN TÞr Þµ:-zjhªâ—(Z–×^–+Þ¯* Mç!ëlzw^™¨¥¶‚â²Û ®ø©r àHDÓyÈgzÓN0 N Þqè¯xãD™¨¥ x)z·Zʇږ[azš,¶Ë צj)m ¸¬¶Ç«¾*\¢¸ 4Þr Þ´8 zËRyªÜ†šÞ¾*.²š,¶)౫pà ©r à:râä^²‹«që jÖ›jǬ f¢”
> ܆+Þ°ù^jǯ È ð°y»"µèm¶ŸÿÃ"¥Ê+ƒømš_ߢ»¦†ÙŸ¢¶v+b¢v¥ wè®f ‰èÊ'µ§-)朅&¬jj+‰«ljƤ¢*\¢¸(¯Î;çO}ïM ÆÞw15==
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=========================================================================
Date: Wed, 27 Mar 2002 11:55:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: solder mask tape dots
MIME-Version: 1.0
Content-Type: text/plain
What about peelable solder mask Phil?
Regards,
Ioan
> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Wednesday, March 27, 2002 10:12 AM
> To: [log in to unmask]
> Subject: [TN] solder mask tape dots
>
> Here is another question for all you gurus.
>
> We have a hand build, through hole circuit board that has 8 locations that
> must be free of solder for the next level of assembly. So far I can only
> find solder mask tape dots at Contact East. Are there any other suppliers
> out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might
> be just the thing.
>
> Thanks in advance,
>
> Phil
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> ext.5315
> --------------------------------------------------------------------------
> -------
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Date: Wed, 27 Mar 2002 12:12:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Howard Watson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Re: Double Sided Reflow Flux and surface tension
X-To: "Edward S. Wheeler" <[log in to unmask]>
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Ed,
I can't answer your questions regarding the OA flux and BGA's, but I can
help with your other questions:
"Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?" Yes, as stated in previous TechNet threads on the subject, the "rule of
thumb" formula is the weight of the component in grams / Total pad mating
area in square inches. The resulting value in grams per sq. in. must be
less than 30.
"Does anybody use adhesives to stake heavy parts on the first pass?" No I don't, but it shouldn't cause you any worries. There are issues with thermal balance and back to back components that
you will need to investigate to obtain the proper reflow.
"Does anybody have a solid rule of thumb for pin-in-paste apertures? On
our
first try we used an 8 mil step up and had the aperture the same size as
outer edge of the PTH. Would an oversize print work better?" The key is to get a sufficient amount of solder fill in the hole and to
provide for good fillets. A simple formula to use for paste required is:
Vp = [Vh - Vl]x Fh x Sp ,where:
Vp = The "target" volume of paste
Vh = Volume of the hole (self explanatory)
Vl = Volume of the lead (again, self explanatory)
Fh = Through hole fill percentage (This depends on your own needs, ie:IPC
class I,II,II)
Sp = Paste shrink factor (depends on your paste, I use 51%)
I have used this formula and have achieved great success reflowing through
hole parts. I have overprinted the pads out of necessity to get the
desired volume of paste, up to a .22" aperture, and the paste reflowed
into the barrel, creating good top and bottom side fillets. The amount of
overprint is dictated by the paste volume formula, and also by the PCB
layout of nearby SMT components, the pitch of the device,vias, or other
keep out areas. I created a spreadsheet that helps me design the
apertures based on the above formula, and I can email this to you if you
are interested. IPC-7525 contains some very useful guidelines for
"Intrusive Reflow". Their formula is more detailed, but may be overkill.
I hope this is of some help. Good luck!
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
"Edward S. Wheeler" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
03/26/02 01:14 PM
Please respond to "TechNet E-Mail Forum."; Please respond to "Edward S.
Wheeler"
To: [log in to unmask]
cc:
Subject: [TN] Double Sided Reflow Flux and surface tension
Hello Tech-Net users! I am new to the group here, and would like your
assistance on a couple of matters concerning a double sided reflow process
we are undertaking. We are new to this process, so we would appreciate any
expertise on the matter.
We are using an OA type solder paste, and like to wash our boards within 2
hours, 4 being the maximum in house limit. To perform our double sided
reflow process in mass production, we may want to run all day on one side
and do the other side the next. My question is... does any of the residual
flux material aid the second reflow process, or can we wash it off before
the second reflow and get as good of results? I am concerned that the
solder joint may have an outer layer of oxidation or graininess due to the
lack of flux once it reflows again. Is there any flux left over that is
active, or is it simply the remainder of the carrier?
What luck are people having with BGAs populated on the bottom side? Is
there more of a concern with warp on the second pass?
Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?
Does anybody use adhesives to stake heavy parts on the first pass?
Does anybody have a solid rule of thumb for pin-in-paste apertures? On our
first try we used an 8 mil step up and had the aperture the same size as
outer edge of the PTH. Would an oversize print work better?
Thanks in advance for any help.
Ed
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<br><font size=2 face="sans-serif">Ed,</font>
<br>
<br><font size=2 face="sans-serif">I can't answer your questions regarding the OA flux and BGA's, but I can help with your other questions:</font>
<br>
<br><font size=2 face="Courier New"><i>"Is there a rule of thumb for the pad surface area / part weight ratio to<br>
maintain enough surface tension to correctly hold the part?"</i> Yes, as stated in previous TechNet threads on the subject, the "rule of thumb" formula is the weight of the component in grams / Total pad mating area in square inches. The resulting value in grams per sq. in. must be less than 30.<br>
<br>
<i>"Does anybody use adhesives to stake heavy parts on the first pass?" </i>No I don't, but it shouldn't cause you any worries<i>.</i> There are issues with thermal balance and back to back components that you will need to investigate to obtain the proper reflow.<br>
<br>
<i>"Does anybody have a solid rule of thumb for pin-in-paste apertures? On our<br>
first try we used an 8 mil step up and had the aperture the same size as<br>
outer edge of the PTH. Would an oversize print work better?" </i>The key is to get a sufficient amount of solder fill in the hole and to provide for good fillets. A simple formula to use for paste required is: V<sub>p</sub> = [V<sub>h </sub>- V<sub>l</sub>]x F<sub>h</sub> x S<sub>p</sub> ,where:</font>
<br><font size=2 face="Courier New">V<sub>p</sub> = The "target" volume of paste</font>
<br><font size=2 face="Courier New">V<sub>h</sub> = Volume of the hole (self explanatory)</font>
<br><font size=2 face="Courier New">V<sub>l</sub> = Volume of the lead (again, self explanatory)</font>
<br><font size=2 face="Courier New">F<sub>h</sub> = Through hole fill percentage (This depends on your own needs, ie:IPC class I,II,II)</font>
<br><font size=2 face="Courier New">S<sub>p</sub> = Paste shrink factor (depends on your paste, I use 51%)</font>
<br><font size=2 face="Courier New">I have used this formula and have achieved great success reflowing through hole parts. I have overprinted the pads out of necessity to get the desired volume of paste, up to a .22" aperture, and the paste reflowed into the barrel, creating good top and bottom side fillets. The amount of overprint is dictated by the paste volume formula, and also by the PCB layout of nearby SMT components, the pitch of the device,vias, or other keep out areas. I created a spreadsheet that helps me design the apertures based on the above formula, and I can email this to you if you are interested. IPC-7525 contains some very useful guidelines for "Intrusive Reflow". Their formula is more detailed, but may be overkill. I hope this is of some help. Good luck!</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>"Edward S. Wheeler" <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">03/26/02 01:14 PM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."; Please respond to "Edward S. Wheeler"</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: [TN] Double Sided Reflow Flux and surface tension</font></table>
<br>
<br>
<br><font size=2 face="Courier New">Hello Tech-Net users! I am new to the group here, and would like your<br>
assistance on a couple of matters concerning a double sided reflow process<br>
we are undertaking. We are new to this process, so we would appreciate any<br>
expertise on the matter.<br>
<br>
We are using an OA type solder paste, and like to wash our boards within 2<br>
hours, 4 being the maximum in house limit. To perform our double sided<br>
reflow process in mass production, we may want to run all day on one side<br>
and do the other side the next. My question is... does any of the residual<br>
flux material aid the second reflow process, or can we wash it off before<br>
the second reflow and get as good of results? I am concerned that the<br>
solder joint may have an outer layer of oxidation or graininess due to the<br>
lack of flux once it reflows again. Is there any flux left over that is<br>
active, or is it simply the remainder of the carrier?<br>
<br>
What luck are people having with BGAs populated on the bottom side? Is<br>
there more of a concern with warp on the second pass?<br>
<br>
Is there a rule of thumb for the pad surface area / part weight ratio to<br>
maintain enough surface tension to correctly hold the part?<br>
<br>
Does anybody use adhesives to stake heavy parts on the first pass?<br>
<br>
Does anybody have a solid rule of thumb for pin-in-paste apertures? On our<br>
first try we used an 8 mil step up and had the aperture the same size as<br>
outer edge of the PTH. Would an oversize print work better?<br>
<br>
Thanks in advance for any help.<br>
<br>
Ed<br>
<br>
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<br>
<br>
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=========================================================================
Date: Wed, 27 Mar 2002 12:23:16 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gary Bremer <[log in to unmask]>
Subject: New Laminate Material
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Gentelmen,
Does anyone have information on carbon-core Printed Wiring
Boards? Who makes this material and how easy is it to work with?
Gary Bremer
Manufacturing Engineer
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Date: Wed, 27 Mar 2002 12:41:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Double Sided Reflow Flux and surface tension
X-To: Howard Watson <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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A question regarding the "total pad mating area" in the formula below. Does
one take into consideration only the area where the bottom of the lead
contacts the pad, or the entire pad area? And, is the contact area of the
bottom of the lead and the contact area of the top of the pad in contact
with the lead added together to get the total contact area for that lead?
Hope this question makes sense!
Bob
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: Wednesday, March 27, 2002 12:12 PM
To: [log in to unmask]
Subject: Re: [TN] Double Sided Reflow Flux and surface tension
Ed,
I can't answer your questions regarding the OA flux and BGA's, but I can
help with your other questions:
"Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?" Yes, as
stated in previous TechNet threads on the subject, the "rule of thumb"
formula is the weight of the component in grams / Total pad mating area in
square inches. The resulting value in grams per sq. in. must be less than
30.
------=_NextPart_000_000E_01C1D58C.B766F440
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4913.1100" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D370093417-27032002>A =
question regarding=20
the "total pad mating area" in the formula below. Does one take into=20
consideration only the area where the bottom of the lead contacts =
the pad,=20
or the entire pad area? And, is the contact area of the bottom of =
the lead=20
and the contact area of the top of the pad in contact with the lead =
added=20
together to get the total contact area for that lead? Hope this question =
makes=20
sense!</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<P><FONT size=3D2>Bob<BR></FONT></P>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Howard =
Watson<BR><B>Sent:</B>=20
Wednesday, March 27, 2002 12:12 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Double Sided Reflow Flux =
and=20
surface tension<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif=20
size=3D2>Ed,</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>I can't =
answer your=20
questions regarding the OA flux and BGA's, but I can help with your =
other=20
questions:</FONT> <BR><BR><FONT face=3D"Courier New" size=3D2><I>"Is =
there a rule=20
of thumb for the pad surface area / part weight ratio to<BR>maintain =
enough=20
surface tension to correctly hold the part?"</I> Yes, as stated =
in=20
previous TechNet threads on the subject, the "rule of thumb" formula =
is the=20
weight of the component in grams / Total pad mating area in square =
inches.=20
The resulting value in grams per sq. in. must be less than=20
30.<BR></FONT></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 27 Mar 2002 10:48:36 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: ICT
X-To: "McMullen, Kerry" <[log in to unmask]>
MIME-Version: 1.0
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Thank you all for your assistance.
Barry.
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Wednesday, March 27, 2002 6:48 AM
To: [log in to unmask]
Subject: Re: [TN] ICT
Hi Barry,
If your board is highly populated, and test point space is at a premium, you
can go do to a .035 square pad on .070 centers.
But you need a very good fixture house.
Good luck,
Kerry
-----Original Message-----
From: DUTTON Phil [mailto:[log in to unmask]]
Sent: Tuesday, March 26, 2002 7:33 PM
To: [log in to unmask]
Subject: Re: [TN] ICT
Hello Barry,
IPC-2221 3.5 has some good info on testing and In Circuit Testing design
requirements.
Can be quite involved, and the circuit design needs to consider the test
requirements as well. Test probe lands are typically 0.040" and pitched at
0.100" centres for bed-of-nails type test fixtures. Different types/sizes of
probe pins are available.
Good idea to talk to the people who will be testing your boards very early.
Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer
-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Wednesday, 27 March 2002 09:03
To: [log in to unmask]
Subject: [TN] ICT
G'day
Was asked if I could come up with some information on ICT.
Where can I find if any on standards that govern ICT "if any" or
how to's on fixturing etc.
Barry.
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Date: Wed, 27 Mar 2002 13:26:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: solder mask tape dots
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Ioan,
That would be a solution, but that requires my assemblers to wait for it =
to cure. If time wasn't an issue that would be fine as we have that in =
stock. As a fallback I may use some of the Kapton wave solder masking =
tape we have in house. The only problem is this will cover too much =
space, or my assemblers will spend way to much time trying to make the =
tape fit.
Thanks for the thought.
Phil
-----Original Message-----
From: Tempea, Ioan [mailto:[log in to unmask]]
Sent: Wednesday, March 27, 2002 11:55 AM
To: [log in to unmask]
Subject: Re: [TN] solder mask tape dots
What about peelable solder mask Phil?
Regards,
Ioan
> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Wednesday, March 27, 2002 10:12 AM
> To: [log in to unmask]
> Subject: [TN] solder mask tape dots
>
> Here is another question for all you gurus.
>
> We have a hand build, through hole circuit board that has 8 locations =
that
> must be free of solder for the next level of assembly. So far I can =
only
> find solder mask tape dots at Contact East. Are there any other =
suppliers
> out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad =
might
> be just the thing.
>
> Thanks in advance,
>
> Phil
>
> =
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Date: Wed, 27 Mar 2002 13:29:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: solder mask tape dots
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Phil,
Check this site for solder plugs and other types of boots and maskant
products: http://www.kinnarney.com/
I've used these folks for a long time and have had great success.
Steve
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
We have a hand build, through hole circuit board that has 8 locations that
must be free of solder for the next level of assembly. So far I can only
find solder mask tape dots at Contact East. Are there any other suppliers
out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might be
just the thing.
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Date: Wed, 27 Mar 2002 15:12:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Double Sided Reflow Flux and surface tension
X-To: bbarr <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0050_01C1D5A1.D27DDF40"
This is a multi-part message in MIME format.
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charset="iso-8859-1"
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The formula is conservative and assumes the lead is completely on the land.
Surface tension on the wetted sides and heel of leaded devices add to the
forces to that in cases where the leads occupy about 85% of the land pattern
it is okay to use the land pattern in the formula. If the land patterns are
unusually large you might have trouble. Then, use the surface area of the
component lead. For, BGAs use the land pattern.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
Sent: Wednesday, March 27, 2002 12:41 PM
To: [log in to unmask]
Subject: Re: [TN] Double Sided Reflow Flux and surface tension
A question regarding the "total pad mating area" in the formula below.
Does one take into consideration only the area where the bottom of the lead
contacts the pad, or the entire pad area? And, is the contact area of the
bottom of the lead and the contact area of the top of the pad in contact
with the lead added together to get the total contact area for that lead?
Hope this question makes sense!
Bob
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: Wednesday, March 27, 2002 12:12 PM
To: [log in to unmask]
Subject: Re: [TN] Double Sided Reflow Flux and surface tension
Ed,
I can't answer your questions regarding the OA flux and BGA's, but I can
help with your other questions:
"Is there a rule of thumb for the pad surface area / part weight ratio
to
maintain enough surface tension to correctly hold the part?" Yes, as
stated in previous TechNet threads on the subject, the "rule of thumb"
formula is the weight of the component in grams / Total pad mating area in
square inches. The resulting value in grams per sq. in. must be less than
30.
------=_NextPart_000_0050_01C1D5A1.D27DDF40
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D258080520-27032002>The=20
formula is conservative and assumes the lead is completely on the land. =
Surface=20
tension on the wetted sides and heel of leaded devices add to the forces =
to that=20
in cases where the leads occupy about 85% of the land pattern it is okay =
to use=20
the land pattern in the formula. If the land patterns are unusually =
large=20
you might have trouble. Then, use the surface area of the component =
lead. For, =20
BGAs use the land pattern. </SPAN></FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> bbarr<BR><B>Sent:</B> =
Wednesday,=20
March 27, 2002 12:41 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> Re:=20
[TN] Double Sided Reflow Flux and surface tension<BR><BR></DIV></FONT>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D370093417-27032002>A =
question=20
regarding the "total pad mating area" in the formula below. Does one =
take into=20
consideration only the area where the bottom of the lead contacts =
the=20
pad, or the entire pad area? And, is the contact area of the bottom of =
the lead and the contact area of the top of the pad in contact =
with the=20
lead added together to get the total contact area for that lead? Hope =
this=20
question makes sense!</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<P><FONT size=3D2>Bob<BR></FONT></P>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
PADDING-LEFT: 5px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Howard =
Watson<BR><B>Sent:</B>=20
Wednesday, March 27, 2002 12:12 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Double Sided Reflow Flux =
and=20
surface tension<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif=20
size=3D2>Ed,</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>I can't =
answer your=20
questions regarding the OA flux and BGA's, but I can help with your =
other=20
questions:</FONT> <BR><BR><FONT face=3D"Courier New" size=3D2><I>"Is =
there a=20
rule of thumb for the pad surface area / part weight ratio =
to<BR>maintain=20
enough surface tension to correctly hold the part?"</I> Yes, =
as stated=20
in previous TechNet threads on the subject, the "rule of thumb" =
formula is=20
the weight of the component in grams / Total pad mating area in =
square=20
inches. The resulting value in grams per sq. in. must be less =
than=20
30.<BR></FONT></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0050_01C1D5A1.D27DDF40--
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Date: Wed, 27 Mar 2002 12:05:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Thorup, John" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Thorup, John" <[log in to unmask]>
Subject: Re: solder mask tape dots
X-To: "Sauer, Steven T." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
We use the "solder wave disks" from Shercon. Basically it's a roll of dots
of high temp masking tape. Among others there are .250 and .375 dia. They
work well for us and don't leave any goop. We buy them thru Com-Kyl.
> -----Original Message-----
> From: Sauer, Steven T. [SMTP:[log in to unmask]]
> Sent: Wednesday, March 27, 2002 10:29 AM
> To: [log in to unmask]
> Subject: Re: [TN] solder mask tape dots
>
> Phil,
> Check this site for solder plugs and other types of boots and maskant
> products: http://www.kinnarney.com/
> I've used these folks for a long time and have had great success.
>
> Steve
>
> -----Original Message-----
> From: Phil Nutting [mailto:[log in to unmask]]
>
> We have a hand build, through hole circuit board that has 8 locations that
> must be free of solder for the next level of assembly. So far I can only
> find solder mask tape dots at Contact East. Are there any other suppliers
> out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might
> be
> just the thing.
>
> --------------------------------------------------------------------------
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Date: Wed, 27 Mar 2002 16:40:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: solder mask tape dots
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Phil,
One more solution - UV curable spotmask, made by several of the peelable
and/or water-soluble spot mask suppliers. Available at Contact East and
other distributors.
Al Kreplick
Sr. Mfg. Eng.
Teradyne, Inc.
500 Riverpark Drive
North Reading, MA 01864
978-370-1726
(Embedded
image moved TechNet <[log in to unmask]>
to file: 03/27/2002 01:26 PM
pic31591.pcx)
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Phil Nutting <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] solder mask tape dots
Ioan,
That would be a solution, but that requires my assemblers to wait for it to
cure. If time wasn't an issue that would be fine as we have that in stock.
As a fallback I may use some of the Kapton wave solder masking tape we have
in house. The only problem is this will cover too much space, or my
assemblers will spend way to much time trying to make the tape fit.
Thanks for the thought.
Phil
-----Original Message-----
From: Tempea, Ioan [mailto:[log in to unmask]]
Sent: Wednesday, March 27, 2002 11:55 AM
To: [log in to unmask]
Subject: Re: [TN] solder mask tape dots
What about peelable solder mask Phil?
Regards,
Ioan
> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Wednesday, March 27, 2002 10:12 AM
> To: [log in to unmask]
> Subject: [TN] solder mask tape dots
>
> Here is another question for all you gurus.
>
> We have a hand build, through hole circuit board that has 8 locations
that
> must be free of solder for the next level of assembly. So far I can only
> find solder mask tape dots at Contact East. Are there any other suppliers
> out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might
> be just the thing.
>
> Thanks in advance,
>
> Phil
>
>
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Date: Wed, 27 Mar 2002 16:40:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Conformal Coating BGA's
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Peter! You have me confused (which is a normal state for me if I don't
have a Coke in my hand). Collins has been using BGAs in avionics use
environments, not underfilled, with acrylic conformal coating very
successfully for a couple of years. What was the reason/rationale for using
BGAs with underfill? Was is an issue with solder joint thermal cycle
fatigue for a given use environment? Corrosion? Customer requirements?
Residual flux issues? Sheer terror of the unknown?
Dave Hillman
Rockwell Collins
[log in to unmask]
[log in to unmask]@ipc.org> on 03/26/2002 07:48:52 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to [log in to unmask]
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Conformal Coating BGA's
Hi, Bruce,
We apply Humiseal acrylic coating to boards that fit your description and
application precisely, except that we do underfill the BGA's with a
reworkable epoxy, applied after assembly. The only exception was for the
case of two boards destined for temperature cycling measurement, for which
we couldn't get a supply of underfill material at the time. We substituted
thinned Humiseal as the boards would not be flying, as we were concerned
about entrapped air and also no suuport for the BGA joints. Humiseal is not
a proper substitute for the specialised proper epoxy, but was sufficient
for our particular purpose.
The main issue as I see it would be moisture and other contaminants in the
entrapped air, but I have no first hand data to help you decide if that
causes problems or not.
Good luck
Peter
"Misner,
Bruce" To: [log in to unmask]
<Bruce_Misner cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
@ATK.COM> Aero/ST Group)
Sent by: Subject: [TN] Conformal
Coating BGA's
TechNet
<[log in to unmask]
ORG>
03/20/02
03:48 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Misner,
Bruce"
My question of the day: Is anyone conformal coating (not parylene) plastic
BGA's on FR-4 in Hi-Rel applications (aircraft; -20 to +71C ambient
operating temperature requirement) without benefit of an underfil? If yes,
has entrapped air been a major issue? Anyone care to comment on this
approach?
Regards,
Bruce Misner
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Date: Wed, 27 Mar 2002 18:37:53 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: solder mask tape dots
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_90.23777ee9.29d3b1d1_boundary"
--part1_90.23777ee9.29d3b1d1_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Phil!
Here's another suggestion to add to the answers you've received, reusable
tapered plugs. Check out:
http://www.echosupply.com/catalog_pdf/echo6.pdf
-Steve Gregory-
> Here is another question for all you gurus.
>
> We have a hand build, through hole circuit board that has 8 locations that
> must be free of solder for the next level of assembly. So far I can only
> find solder mask tape dots at Contact East. Are there any other suppliers
> out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might
> be just the thing.
>
> Thanks in advance,
>
> Phil
>
--part1_90.23777ee9.29d3b1d1_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Phil!<BR>
<BR>
Here's another suggestion to add to the answers you've received, reusable tapered plugs. Check out:<BR>
<BR>
http://www.echosupply.com/catalog_pdf/echo6.pdf<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Here is another question for all you gurus.<BR>
<BR>
We have a hand build, through hole circuit board that has 8 locations that must be free of solder for the next level of assembly. So far I can only find solder mask tape dots at Contact East. Are there any other suppliers out there? Our terminal measures 0.28 inch diameter, so a 0.3" pad might be just the thing.<BR>
<BR>
Thanks in advance,<BR>
<BR>
Phil<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_90.23777ee9.29d3b1d1_boundary--
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Date: Wed, 27 Mar 2002 18:54:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: solder mask tape dots
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Humiseal makes tape dots that are designed for coating masking, but I have
used them at wave in the past. You might try to get a sample from them to
test.
Jon Moore
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=========================================================================
Date: Wed, 27 Mar 2002 18:35:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
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Contact Information:
Joe Dudeck, IPC Communications Manager
847-790-5371
For Immediate Release
IPC AND ITS MEMBERS CLAIM VICTORY
NORTHBROOK, Ill., March 15, 2002--IPC-Association Connecting Electronics =
Industries=AE has announced a victory in its efforts to pass a realistic =
depreciation bill for the electronics assembly and printed circuit board =
industries.
The U.S. Congress and the Bush Administration recently reached an =
agreement to pass an economic stimulus package that includes a significant =
accelerated depreciation provision for the electronic interconnection =
industry and other U.S. manufacturers. This realistic depreciation issue =
has been a cornerstone of IPC's Government Relations policy for more than =
seven years. The bipartisan effort received support from nearly every =
congressman and senator IPC contacted to support the bill.
"This is a great victory for IPC, its Board and its dedicated members," =
said IPC President Denny McGuirk. "I congratulate and thank all those =
individuals, especially those that serve on our Government Relations =
committee, who have given their time and energy to attend past Capitol =
Hill Day events, write letters and host plant tours on this very important =
issue."
The "Job Creation and Worker Assistance Act of 2002," which was signed =
into law by President Bush on March 9, contains a 30 percent accelerated =
depreciation benefit over the next three years that will spur investment =
in state-of-the-art manufacturing equipment and assist in the recovery of =
the PCB and EMS industry. The applicable time period for equipment =
covered under the new law is property that was acquired after September =
10, 2001, and before September 11, 2004.
"The passing of this bill is timely for our industry and our national =
economy," added McGuirk. "With IPC Printed Circuits Expo=AE 2002 just =
around the corner, the 30 percent accelerated depreciation benefit will =
likely impact many attendees' purchasing decisions in a positive way."
For more information, contact John Kania, IPC's director of Government =
Relations, at [log in to unmask] or 202-962-0460.
About IPC
IPC is a U.S.-based trade association dedicated to the competitive =
excellence and financial success of its more than 2,600 member companies =
which represent all facets of the electronic interconnection industry, =
including design, printed wiring board manufacturing and electronics =
assembly. As a member-driven organization and leading source for industry =
standards, training, market research and public policy advocacy, IPC =
supports programs to meet the needs of a $44 billion U.S. industry =
employing more than 400,000 people.
//30//
NR02056AccDepSupport
--=_B9E42A2A.9FFE9FBF
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Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px"><FONT=20
face=3D"Times New Roman" size=3D3>
<DIV><STRONG>Contact Information:</STRONG><BR>Joe Dudeck, IPC Communication=
s=20
Manager<BR>847-790-5371</DIV>
<DIV> </DIV>
<DIV><FONT size=3D4><STRONG>For Immediate Release</STRONG></FONT></DIV>
<DIV> </DIV>
<DIV align=3Dcenter><FONT size=3D5><STRONG><U>IPC AND ITS MEMBERS CLAIM=20
VICTORY</U></STRONG></FONT></DIV>
<DIV> </DIV>
<DIV><STRONG>NORTHBROOK, Ill., March 15, 2002</STRONG>--IPC-Association=20
Connecting Electronics Industries=AE has announced a victory in its =
efforts to=20
pass a realistic depreciation bill for the electronics assembly and =
printed=20
circuit board industries.</DIV>
<DIV><BR>The U.S. Congress and the Bush Administration recently reached =
an=20
agreement to pass an economic stimulus package that includes a significant=
=20
accelerated depreciation provision for the electronic interconnection =
industry=20
and other U.S. manufacturers. This realistic depreciation issue has =
been a=20
cornerstone of IPC's Government Relations policy for more than seven=20
years. The bipartisan effort received support from nearly every=20
congressman and senator IPC contacted to support the bill.</DIV>
<DIV> </DIV>
<DIV>"This is a great victory for IPC, its Board and its dedicated =
members,"=20
said IPC President Denny McGuirk. "I congratulate and thank all =
those=20
individuals, especially those that serve on our Government Relations =
committee,=20
who have given their time and energy to attend past Capitol Hill Day =
events,=20
write letters and host plant tours on this very important issue."</DIV>
<DIV><BR>The "Job Creation and Worker Assistance Act of 2002," which was =
signed=20
into law by President Bush on March 9, contains a 30 percent accelerated=20=
depreciation benefit over the next three years that will spur investment =
in=20
state-of-the-art manufacturing equipment and assist in the recovery of the =
PCB=20
and EMS industry. The applicable time period for equipment covered =
under=20
the new law is property that was acquired after September 10, 2001, and =
before=20
September 11, 2004.</DIV>
<DIV> </DIV>
<DIV>"The passing of this bill is timely for our industry and our =
national=20
economy," added McGuirk. "With IPC Printed Circuits Expo=AE 2002 =
just around=20
the corner, the 30 percent accelerated depreciation benefit will likely =
impact=20
many attendees' purchasing decisions in a positive way."</DIV>
<DIV> </DIV>
<DIV>For more information, contact John Kania, IPC's director of Government=
=20
Relations, at <A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or=20
202-962-0460.</DIV>
<DIV> </DIV>
<DIV><STRONG><U>About IPC</U></STRONG><BR>IPC is a U.S.-based trade =
association=20
dedicated to the competitive excellence and financial success of its more =
than=20
2,600 member companies which represent all facets of the electronic=20
interconnection industry, including design, printed wiring=20
board manufacturing and electronics assembly. As a member-driven=
=20
organization and leading source for industry standards, training, =
market=20
research and public policy advocacy, IPC supports programs to meet the =
needs of=20
a $44 billion U.S. industry employing more than 400,000 people.<BR></DIV>
<DIV align=3Dcenter>//30//</DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>NR02056AccDepSupport</FONT></DIV></FONT></BODY></HTML>
--=_B9E42A2A.9FFE9FBF--
---------------------------------------------------------------------------------
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To unsubscribe, send a message to [log in to unmask] with following text in
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=========================================================================
Date: Wed, 27 Mar 2002 21:57:10 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_96.2406ad14.29d3e086_boundary"
--part1_96.2406ad14.29d3e086_boundary
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All I can say is; OUTSTANDING!! Although I must admit, I've not been involve=
d=20
intimately with this issue, just been watching from a far.
I've got a question though, I looked at the bill from links that I searched=20
about the bill, and it seems to me, that any money that you spend that is=20
considered a capital cost (for example, $49,000 for a circuitcam software=20
suite for our pick-n-place stuff) can be rolled into this tax break...am I=20
correct in my assumption?
I'm pretty sure our bean counters aren't aware about this news, but we have=20
spent some money on stuff that we capitalized recently...since 9/11.
Also, one last question, there isn't any differentiation if the money was=20
spent on new equipment, or used, is there?
PLEASE, PLEASE ya'll, don't think that this stuff is what I worry about, I=20
just thought I could pass on some good information to our financial staff=20
that they may not be aware of...I'm not a "Bean Counter"...hehehe.
-Steve Gregory-
> Contact Information:
> Joe Dudeck, IPC Communications Manager
> 847-790-5371
> =20
> For Immediate Release
> =20
> IPC AND ITS MEMBERS CLAIM VICTORY
> =20
> NORTHBROOK, Ill., March 15, 2002--IPC-Association Connecting Electronics=20
> Industries=AE has announced a victory in its efforts to pass a realistic=20
> depreciation bill for the electronics assembly and printed circuit board=20
> industries.
>=20
> The U.S. Congress and the Bush Administration recently reached an agreemen=
t=20
> to pass an economic stimulus package that includes a significant=20
> accelerated depreciation provision for the electronic interconnection=20
> industry and other U.S. manufacturers. This realistic depreciation issue=20
> has been a cornerstone of IPC's Government Relations policy for more than=20
> seven years. The bipartisan effort received support from nearly every=20
> congressman and senator IPC contacted to support the bill.
> =20
> "This is a great victory for IPC, its Board and its dedicated members,"=20
> said IPC President Denny McGuirk. "I congratulate and thank all those=20
> individuals, especially those that serve on our Government Relations=20
> committee, who have given their time and energy to attend past Capitol Hil=
l=20
> Day events, write letters and host plant tours on this very important=20
> issue."
>=20
> The "Job Creation and Worker Assistance Act of 2002," which was signed int=
o=20
> law by President Bush on March 9, contains a 30 percent accelerated=20
> depreciation benefit over the next three years that will spur investment i=
n=20
> state-of-the-art manufacturing equipment and assist in the recovery of the=
=20
> PCB and EMS industry. The applicable time period for equipment covered=20
> under the new law is property that was acquired after September 10, 2001,=20
> and before September 11, 2004.
> =20
> "The passing of this bill is timely for our industry and our national=20
> economy," added McGuirk. "With IPC Printed Circuits Expo=AE 2002 just aro=
und=20
> the corner, the 30 percent accelerated depreciation benefit will likely=20
> impact many attendees' purchasing decisions in a positive way."
> =20
> For more information, contact John Kania, IPC's director of Government=20
> Relations, at <A HREF=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 202-=
962-0460.
> =20
> About IPC
> IPC is a U.S.-based trade association dedicated to the competitive=20
> excellence and financial success of its more than 2,600 member companies=20
> which represent all facets of the electronic interconnection industry,=20
> including design, printed wiring board manufacturing and electronics=20
> assembly. As a member-driven organization and leading source for industry=
=20
> standards, training, market research and public policy advocacy, IPC=20
> supports programs to meet the needs of a $44 billion U.S. industry=20
> employing more than 400,000 people.
>=20
> //30//
> =20
> NR02056AccDepSupport
>=20
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<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=
=3D"Arial" LANG=3D"0">All I can say is; OUTSTANDING!! Although I must admit,=
I've not been involved intimately with this issue, just been watching from=20=
a far.<BR>
<BR>
I've got a question though, I looked at the bill from links that I searched=20=
about the bill, and it seems to me, that any money that you spend that is co=
nsidered a capital cost (for example, $49,000 for a circuitcam software suit=
e for our pick-n-place stuff) can be rolled into this tax break...am I corre=
ct in my assumption?<BR>
<BR>
I'm pretty sure our bean counters aren't aware about this news, but we have=20=
spent some money on stuff that we capitalized recently...since 9/11.<BR>
<BR>
Also, one last question, there isn't any differentiation if the money was sp=
ent on new equipment, or used, is there?<BR>
<BR>
PLEASE, PLEASE ya'll, don't think that this stuff is what I worry about, I j=
ust thought I could pass on some good information to our financial staff tha=
t they may not be aware of...I'm not a "Bean Counter"...hehehe.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=3D3=
FAMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"><BLOCKQUOTE TYPE=3DCIT=
E style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0=
px; PADDING-LEFT: 5px"><B>Contact Information:</B><BR>
Joe Dudeck, IPC Communications Manager<BR>
847-790-5371<BR>
<BR>
</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=3D4=
FAMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"><B>For Immediate Relea=
se</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=
=3D3 FAMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"></B><BR>
<BR>
</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=3D5=
FAMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"><B><U>IPC AND ITS MEMB=
ERS CLAIM VICTORY</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR:=20=
#ffffff" SIZE=3D3 FAMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"></B><=
/U><BR>
<BR>
<B>NORTHBROOK, Ill., March 15, 2002</B>--IPC-Association Connecting Electron=
ics Industries=AE has announced a victory in its efforts to pass a realistic=
depreciation bill for the electronics assembly and printed circuit board in=
dustries.<BR>
<BR>
The U.S. Congress and the Bush Administration recently reached an agreement=20=
to pass an economic stimulus package that includes a significant accelerated=
depreciation provision for the electronic interconnection industry and othe=
r U.S. manufacturers. This realistic depreciation issue has been a cor=
nerstone of IPC's Government Relations policy for more than seven years.&nbs=
p; The bipartisan effort received support from nearly every congressman and=20=
senator IPC contacted to support the bill.<BR>
<BR>
"This is a great victory for IPC, its Board and its dedicated members," said=
IPC President Denny McGuirk. "I congratulate and thank all those indi=
viduals, especially those that serve on our Government Relations committee,=20=
who have given their time and energy to attend past Capitol Hill Day events,=
write letters and host plant tours on this very important issue."<BR>
<BR>
The "Job Creation and Worker Assistance Act of 2002," which was signed into=20=
law by President Bush on March 9, contains a 30 percent accelerated deprecia=
tion benefit over the next three years that will spur investment in state-of=
-the-art manufacturing equipment and assist in the recovery of the PCB and E=
MS industry. The applicable time period for equipment covered under th=
e new law is property that was acquired after September 10, 2001, and before=
September 11, 2004.<BR>
<BR>
"The passing of this bill is timely for our industry and our national econom=
y," added McGuirk. "With IPC Printed Circuits Expo=AE 2002 just around=
the corner, the 30 percent accelerated depreciation benefit will likely imp=
act many attendees' purchasing decisions in a positive way."<BR>
<BR>
For more information, contact John Kania, IPC's director of Government Relat=
ions, at <A HREF=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 202-962-046=
0.<BR>
<BR>
<B><U>About IPC</B></U><BR>
IPC is a U.S.-based trade association dedicated to the competitive excellenc=
e and financial success of its more than 2,600 member companies which repres=
ent all facets of the electronic interconnection industry, including design,=
printed wiring board manufacturing and electronics assembly. As a mem=
ber-driven organization and leading source for industry standards, training,=
market research and public policy advocacy, IPC supports programs to meet t=
he needs of a $44 billion U.S. industry employing more than 400,000 people.<=
BR>
<BR>
//30//<BR>
<BR>
</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=3D1=
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AMILY=3D"SERIF" FACE=3D"Times New Roman" LANG=3D"0"><BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR=3D"#000000" style=3D"BACKGROUND-COLOR: #ffffff" SIZE=3D2=
FAMILY=3D"SANSSERIF" FACE=3D"Arial" LANG=3D"0"><BR>
</FONT></HTML>
--part1_96.2406ad14.29d3e086_boundary--
---------------------------------------------------------------------------------
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To unsubscribe, send a message to [log in to unmask] with following text in
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Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
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=========================================================================
Date: Thu, 28 Mar 2002 11:29:20 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
kevinyeah <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: kevinyeah <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: "[log in to unmask]" <[log in to unmask]>
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ICAgICAgIGtldmlueWVhaA0KICAgICAgICAgICAgICAga2V2aW55ZWFoQHNvaHUuY29tDQoJCQkJ
CTIwMDItMDMtMjggDQo=
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Date: Thu, 28 Mar 2002 14:06:59 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: MIL-C-28809 Replacement/supersede
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Understand that MIL-C-28809 has been cancelled. However, there are two
tables indicates in this mil-spec on the max. number allowed permitted
for plated-thorugh hole repair and circuit repair. Can someone point to
me where else can I find similar tables for repair under IPC standards?
Thank you very much in advance - Wee Mei.
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Date: Thu, 28 Mar 2002 09:33:29 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Double Sided Reflow Flux and surface tension
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Hi Edward,
An answer to your question about using adhesives: yes, when there are =
heavy components going through "inverted reflow" we apply a few gluedots =
to the corners of these parts. We use the same Hereaus glue that we use =
for wave soldering of smd's, it is applied after soldering and cleaning of =
the first side.=20
Instead of using an additional curing step we let the adhesive harden in =
the preheat-zones of the reflow oven, so that it is cured before the =
solder melts.
It works, but I still see it as a makeshift for badly designed boards, and =
it should not be standard practice.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> "Edward S. Wheeler" <[log in to unmask]> 03/26 9:14 pm >>>
Hello Tech-Net users! I am new to the group here, and would like your
assistance on a couple of matters concerning a double sided reflow process
we are undertaking. We are new to this process, so we would appreciate any
expertise on the matter.
We are using an OA type solder paste, and like to wash our boards within 2
hours, 4 being the maximum in house limit. To perform our double sided
reflow process in mass production, we may want to run all day on one side
and do the other side the next. My question is... does any of the residual
flux material aid the second reflow process, or can we wash it off before
the second reflow and get as good of results? I am concerned that the
solder joint may have an outer layer of oxidation or graininess due to the
lack of flux once it reflows again. Is there any flux left over that is
active, or is it simply the remainder of the carrier?
What luck are people having with BGAs populated on the bottom side? Is
there more of a concern with warp on the second pass?
Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?
Does anybody use adhesives to stake heavy parts on the first pass?
Does anybody have a solid rule of thumb for pin-in-paste apertures? On our
first try we used an 8 mil step up and had the aperture the same size as
outer edge of the PTH. Would an oversize print work better?
Thanks in advance for any help.
Ed
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Date: Thu, 28 Mar 2002 06:05:33 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: [log in to unmask]
I completely agree with the following:
IHRlbXBvcmFyaWx5IGhhbHQgZGVsaXZlcnkgb2YgVGVjaG5ldCBzZW5kIGUtbWFpbCB0byBMaXN0
c2VydkBpcGMub3JnOiBTRVQgVGVjaG5ldCBOT01BSUwNCj5UbyByZWNlaXZlIE9ORSBtYWlsaW5n
IHBlciBkYXkgb2YgYWxsIHRoZSBwb3N0czogc2VuZCBlLW1haWwgdG8gTGlzdHNlcnZAaXBjLm9y
ZzogU0VUIFRlY2huZXQgRGlnZXN0DQo+U2VhcmNo
However, Vinit sent me some really ugly photos showing the condition. Out of
respect for his privacy and sorrow, I won't even attempt posting them unless
he wishes. Never seen anything so ugly.
MoonMan
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Date: Thu, 28 Mar 2002 07:47:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: MIL-C-28809 Replacement/supersede
X-To: fullname <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Wee Mei,
To my knowledge, the information that you are looking for does not exist in
a replacement military specification nor other industry association
documents.
On one hand, the information contained in MIL-C-28809 was considered
requirements for "standard" repair/modification. Repair and modifications
that did not fall within these requirements, "non-standard", were turned
over to a Material Review Board (MRB) and dependent on contractual
requirements may have included customer review and approval/disapproval.
With today's technology and the ever changing end use environments,
"standard" repairs should be reviewed by a MRB for issues related to
quality, performance, reliability and maintainability of the deliverable
product. The guidance information contained in MIL-C-28809 can be used to
develop criteria for use by a MRB or better yet, used to develop an in-house
procedure for standard repairs that defines specifics for your products.
IPC-7721 (supercedes IPC-R-700) is widely accepted and used for repair and
modification of electronic assemblies, but it does not contain "maximum
allowable" criteria.
Steve Sauer
-----Original Message-----
From: fullname [mailto:[log in to unmask]]
Understand that MIL-C-28809 has been cancelled. However, there are two
tables indicates in this mil-spec on the max. number allowed permitted
for plated-thorugh hole repair and circuit repair. Can someone point to
me where else can I find similar tables for repair under IPC standards?
---------------------------------------------------------------------------------
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Date: Thu, 28 Mar 2002 08:44:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: MSD tracking
MIME-Version: 1.0
Content-Type: text/plain
Hi Technos,
for me it's payback time. We always ask our customers to supply the Moisture
Sensitive Devices in controlled conditions, you know, sealed bags,
desiccant, humidity indicators. In turn, they started asking us how do we
control the MSDs on the floor.
Right now, we do tracking sheets, a system very close to the one the Moonman
presents in his procedure.
I badly need your input on the following:
- what is the trend in the industry, more companies using the manual system,
like we do, with tracking sheets, or more companies using high-tech systems
like Cogiscan?
- does anybody use the MRP system to log tracking data?
Thanks,
Ioan
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Date: Thu, 28 Mar 2002 07:50:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
Mime-Version: 1.0
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I agree with Steve I have already forwarded it to the bean counters. =
Which now I can look into another experiment I have always wanted to =
watch, How fast can a bean counter move when saving is at stake.....HEHEHEH=
EHEHE
Kathy=20
--=_4F12DDA7.E786EB29
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<META content="MSHTML 6.00.2713.1100" name=GENERATOR></HEAD>
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<DIV>I agree with Steve I have already forwarded it to the bean counters.
Which now I can look into another experiment I have always wanted to watch, How
fast can a bean counter move when saving is at stake.....HEHEHEHEHEHE</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 28 Mar 2002 09:32:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Francois Monette <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Double Sided Reflow Flux and surface tension
X-cc: [log in to unmask]
MIME-version: 1.0
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Ed,
One very important consideration for double-side reflow that many people
overlook is the additional control required for moisture sensitive
components.
As you are probably aware, most PBGAs are classified as moisture sensitive
and as such they have a limited floor life prior to reflow. When you run a
double-side reflow process, it is important to understand that the floor
life clock is not reset by the first reflow. In other words, the components
that are assembled on the first side will continue to absorb moisture after
being assembled and before the second reflow. This means that you need some
method to keep track of the remaining floor life of components on partially
assembled board between the first and second reflow.
Ref : J-STD-033, Section 8.4.4. "If more than one reflow pass is used, care
must be taken to ensure that no moisture sensitive components, mounted or
unmounted, have exceeded their floor life prior to the final pass."
Let me know if you need more information on this subject.
Francois Monette
Cogiscan Inc.
Tel : 450-534-2644
Fax : 450-534-0092
E-mail : [log in to unmask]
www.cogiscan.com
"Edward S. Wheeler" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
03/26/02 01:14 PM
Please respond to "TechNet E-Mail Forum."; Please respond to "Edward S.
Wheeler"
To: [log in to unmask]
cc:
Subject: [TN] Double Sided Reflow Flux and surface tension
Hello Tech-Net users! I am new to the group here, and would like your
assistance on a couple of matters concerning a double sided reflow process
we are undertaking. We are new to this process, so we would appreciate any
expertise on the matter.
We are using an OA type solder paste, and like to wash our boards within 2
hours, 4 being the maximum in house limit. To perform our double sided
reflow process in mass production, we may want to run all day on one side
and do the other side the next. My question is... does any of the residual
flux material aid the second reflow process, or can we wash it off before
the second reflow and get as good of results? I am concerned that the
solder joint may have an outer layer of oxidation or graininess due to the
lack of flux once it reflows again. Is there any flux left over that is
active, or is it simply the remainder of the carrier?
What luck are people having with BGAs populated on the bottom side? Is
there more of a concern with warp on the second pass?
Is there a rule of thumb for the pad surface area / part weight ratio to
maintain enough surface tension to correctly hold the part?
Does anybody use adhesives to stake heavy parts on the first pass?
Does anybody have a solid rule of thumb for pin-in-paste apertures? On our
first try we used an 8 mil step up and had the aperture the same size as
outer edge of the PTH. Would an oversize print work better?
Thanks in advance for any help.
Ed
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=========================================================================
Date: Thu, 28 Mar 2002 09:54:37 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MSD tracking
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_4b.1ab75487.29d488ad_boundary"
--part1_4b.1ab75487.29d488ad_boundary
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Ioan -
The sad fact of the matter is that most companies do not track MSD at all.
The industry is slowly becoming aware of the issue and proper procedures.
Soon MSD will have the "stature" of concern in the industry that ESD has.
When we do Process Audits, MSD "awareness" and tracking is a key category.
Of the companies that do track, the majority seem to be using a traveller
system. However, these are prone to "human" error (just as inspection
logging in AQl methodology). In my opinion, the Cogiscan system is the way
to go. It is relatively new, though, so there are limited installations.
But where they have gone in, it makes MSD tracking as "idiot proof" as
possible.
Bear in mind that MSD tracking becomes even more difficult with double-sided
assemblies (if MSDs are on the first side). I am aware of a at least one
Cogiscan installation at an automobile electronics manufacturer in which
their method of electronic tracking saved the day.
In terms of ROI, the Cogiscan system is very economical. I suggest you look
into it.
My colleagues and I at ITM are advocates of MSD awareness. We are currently
looking into whether the IC manufacturers have any idea how many of their
components were returned as "bad" when, in fact, they were done in by
improper MSD handling.
Think dry!
Phil Zarrow
ITM Consulting
Durham, NH USA
www.ITM-SMT.com
T: (603) 868-1754
F: (603) 868-3623
EM:[log in to unmask]
--part1_4b.1ab75487.29d488ad_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Ioan - <BR>
The sad fact of the matter is that most companies do not track MSD at all. The industry is slowly becoming aware of the issue and proper procedures. Soon MSD will have the "stature" of concern in the industry that ESD has. <BR>
When we do Process Audits, MSD "awareness" and tracking is a key category. Of the companies that do track, the majority seem to be using a traveller system. However, these are prone to "human" error (just as inspection logging in AQl methodology). In my opinion, the Cogiscan system is the way to go. It is relatively new, though, so there are limited installations. But where they have gone in, it makes MSD tracking as "idiot proof" as possible.<BR>
Bear in mind that MSD tracking becomes even more difficult with double-sided assemblies (if MSDs are on the first side). I am aware of a at least one Cogiscan installation at an automobile electronics manufacturer in which their method of electronic tracking saved the day. <BR>
In terms of ROI, the Cogiscan system is very economical. I suggest you look into it.<BR>
My colleagues and I at ITM are advocates of MSD awareness. We are currently looking into whether the IC manufacturers have any idea how many of their components were returned as "bad" when, in fact, they were done in by improper MSD handling.<BR>
<BR>
Think dry!<BR>
<BR>
Phil Zarrow<BR>
<BR>
<B>ITM Consulting <BR>
Durham, NH USA<BR>
www.ITM-SMT.com<BR>
T: (603) 868-1754<BR>
F: (603) 868-3623<BR>
EM:[log in to unmask]</B></FONT></HTML>
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Date: Thu, 28 Mar 2002 09:29:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Carlile <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Carlile <[log in to unmask]>
Subject: Heatsink wanted
I am currently looking for 2 heatsinks:
(1) Approximately 3/4" x 3/4" that is an adhesive tape mount
(2) Approximately 1.575" x 1.575" (40mm x 40mm)that is an adhesive mount
type with a fan attached
Since these are for BGAs, a clip mounting is not acceptable.
Does anybody know where I can find these? I am trying to avoid mom & pop
type shops. Surely a major manufacturer has to make this and distributors
stock it.
Can anybody point me in the right direction???
Thanks!
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Date: Thu, 28 Mar 2002 10:32:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Howard Watson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Re: IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
X-To: Kathy Kuhlow <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="=_mixed 00551DC887256B8A_="
--=_mixed 00551DC887256B8A_=
Content-Type: multipart/alternative; boundary="=_alternative 00551DC887256B8A_="
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Content-Type: text/plain; charset="us-ascii"
I also forwarded this to our financial folks, because frankly I don't know
what its impact is to my company. I am making a $147k capital purchase
now, so what is the bottom line benefit to my company? Any ideas?
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
Kathy Kuhlow <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
03/28/02 06:50 AM
Please respond to "TechNet E-Mail Forum."; Please respond to Kathy Kuhlow
To: [log in to unmask]
cc:
Subject: Re: [TN] IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
I agree with Steve I have already forwarded it to the bean counters. Which
now I can look into another experiment I have always wanted to watch, How
fast can a bean counter move when saving is at stake.....HEHEHEHEHEHE
Kathy
--=_alternative 00551DC887256B8A_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">I also forwarded this to our financial folks, because frankly I don't know what its impact is to my company. I am making a $147k capital purchase now, so what is the bottom line benefit to my company? Any ideas?</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>Kathy Kuhlow <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">03/28/02 06:50 AM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."; Please respond to Kathy Kuhlow</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: Re: [TN] IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY</font></table>
<br>
<br>
<br><font size=2 face="Courier New">I agree with Steve I have already forwarded it to the bean counters. Which now I can look into another experiment I have always wanted to watch, How fast can a bean counter move when saving is at stake.....HEHEHEHEHEHE<br>
<br>
Kathy <br>
</font>
<br>
<br>
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--=_mixed 00551DC887256B8A_=
Content-Type: text/html; name="TEXT.htm"
Content-Disposition: attachment; filename="TEXT.htm"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2713.1100" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I agree with Steve I have already forwarded it to the bean counters.&n=
bsp;
Which now I can look into another experiment I have always wanted to watch,=
How
fast can a bean counter move when saving is at stake.....HEHEHEHEHEHE</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_mixed 00551DC887256B8A_=--
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Date: Thu, 28 Mar 2002 09:59:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Adrian Hanks." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Adrian Hanks." <[log in to unmask]>
Subject: BGA Double Drop
Hi Technetters,
Can anyone help me?
We are curently running some BGA'S through reflow, and on inspecting them
through our Ersascope BGA inspection system have measured there is a ball
drop of around 30% from original ball size. The actual ball formation looks
very "border line" as in, has it single or double dropped. Does anyone know
the guidlines for such a drop? Is 30% the bottom end tolerance and if so
should I be looking at a drop of + 30% to insure a good looking sound joint
on the BGA.
Many thanks in advance,
Adrian Hanks.
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Date: Thu, 28 Mar 2002 11:25:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: BGA Double Drop
X-To: "Adrian Hanks." <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Adrian, I have a few questions, then if they are consistent with what we
have seen, we can discuss this further. Is the "drop" from the original
size due to the fact the chip is warped and pulled the ball up into a
column? Are they located in the corners and edges mostly? Is this a plastic
BGA? Are you inspecting for solder paste in the BGA areas? Are you losing
solder down your vias by way of a short trace?
Ed
At 09:59 AM 3/28/2002 -0600, you wrote:
>Hi Technetters,
>
>Can anyone help me?
>
>We are curently running some BGA'S through reflow, and on inspecting them
>through our Ersascope BGA inspection system have measured there is a ball
>drop of around 30% from original ball size. The actual ball formation looks
>very "border line" as in, has it single or double dropped. Does anyone know
>the guidlines for such a drop? Is 30% the bottom end tolerance and if so
>should I be looking at a drop of + 30% to insure a good looking sound joint
>on the BGA.
>
>Many thanks in advance,
>
>Adrian Hanks.
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
>
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Date: Thu, 28 Mar 2002 11:41:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: MSD tracking
MIME-Version: 1.0
Content-Type: text/plain
Thanks Phil,
although I don't really agree with dry thinking right now, when Easter has
to be celebrated.
Ioan
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, March 28, 2002 9:55 AM
> To: [log in to unmask]
> Subject: Re: [TN] MSD tracking
>
> Ioan -
> The sad fact of the matter is that most companies do not track MSD at all.
> The industry is slowly becoming aware of the issue and proper procedures.
> Soon MSD will have the "stature" of concern in the industry that ESD has.
>
> When we do Process Audits, MSD "awareness" and tracking is a key category.
> Of the companies that do track, the majority seem to be using a traveller
> system. However, these are prone to "human" error (just as inspection
> logging in AQl methodology). In my opinion, the Cogiscan system is the
> way to go. It is relatively new, though, so there are limited
> installations. But where they have gone in, it makes MSD tracking as
> "idiot proof" as possible.
> Bear in mind that MSD tracking becomes even more difficult with
> double-sided assemblies (if MSDs are on the first side). I am aware of a
> at least one Cogiscan installation at an automobile electronics
> manufacturer in which their method of electronic tracking saved the day.
>
> In terms of ROI, the Cogiscan system is very economical. I suggest you
> look into it.
> My colleagues and I at ITM are advocates of MSD awareness. We are
> currently looking into whether the IC manufacturers have any idea how many
> of their components were returned as "bad" when, in fact, they were done
> in by improper MSD handling.
>
> Think dry!
>
> Phil Zarrow
>
> ITM Consulting
> Durham, NH USA
> www.ITM-SMT.com
> T: (603) 868-1754
> F: (603) 868-3623
> EM:[log in to unmask]
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Date: Thu, 28 Mar 2002 11:42:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA Double Drop
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_95.19f590d1.29d4a200_boundary"
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Hi Adrian!
Is this part a Texas Instrument part that has a big metal heat slug in the
top? I've seen this happen with that part because of the weight of the heat
slug...the balls
look kinda "squished" too...
-Steve Gregory-
> Hi Technetters,
>
> Can anyone help me?
>
> We are curently running some BGA'S through reflow, and on inspecting them
> through our Ersascope BGA inspection system have measured there is a ball
> drop of around 30% from original ball size. The actual ball formation looks
> very "border line" as in, has it single or double dropped. Does anyone know
> the guidlines for such a drop? Is 30% the bottom end tolerance and if so
> should I be looking at a drop of + 30% to insure a good looking sound joint
> on the BGA.
>
> Many thanks in advance,
>
> Adrian Hanks.
>
--part1_95.19f590d1.29d4a200_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Adrian!
<BR>
<BR>Is this part a Texas Instrument part that has a big metal heat slug in the top? I've seen this happen with that part because of the weight of the heat slug...the balls
<BR>look kinda "squished" too...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Technetters,
<BR>
<BR>Can anyone help me?
<BR>
<BR>We are curently running some BGA'S through reflow, and on inspecting them
<BR>through our Ersascope BGA inspection system have measured there is a ball
<BR>drop of around 30% from original ball size. The actual ball formation looks
<BR>very "border line" as in, has it single or double dropped. Does anyone know
<BR>the guidlines for such a drop? Is 30% the bottom end tolerance and if so
<BR>should I be looking at a drop of + 30% to insure a good looking sound joint
<BR>on the BGA.
<BR>
<BR>Many thanks in advance,
<BR>
<BR>Adrian Hanks.
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_95.19f590d1.29d4a200_boundary--
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Date: Thu, 28 Mar 2002 09:00:21 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: standard package dimensions
MIME-version: 1.0
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This is a multi-part message in MIME format.
--Boundary_(ID_U/esmW0BpRhdtJ7Nwt57Uw)
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
Does anyone know of a web site that gives standard dimensions for QFP, PLCC, etc.?
We have a couple of new products coming out and I need to find shipping tubes, hopefully off the shelf.
The parts are .175" X .175" X .066", .190" X .220" X .065, and .276" X .378" X .092.
Thanks,
Dan
--Boundary_(ID_U/esmW0BpRhdtJ7Nwt57Uw)
Content-type: text/html; charset=iso-8859-1
Content-transfer-encoding: 7BIT
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Does anyone know of a web site that gives standard
dimensions for QFP, PLCC, etc.?</FONT></DIV>
<DIV><FONT face=Arial size=2>We have a couple of new products coming out and I
need to find shipping tubes, hopefully off the shelf.</FONT></DIV>
<DIV><FONT face=Arial size=2>The parts are .175" X .175" X .066", .190" X .220"
X .065, and .276" X .378" X .092.</FONT></DIV>
<DIV><FONT face=Arial size=2>Thanks,</FONT></DIV>
<DIV><FONT face=Arial size=2>Dan</FONT></DIV></BODY></HTML>
--Boundary_(ID_U/esmW0BpRhdtJ7Nwt57Uw)--
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Date: Thu, 28 Mar 2002 12:02:23 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: IPC News Release--IPC AND ITS MEMBERS CLAIM VICTORY
MIME-Version: 1.0
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boundary="part1_49.1ad0e868.29d4a69f_boundary"
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Hi Howard!
I found a link that has the whole bill in a *.PDF file. Go to:
http://thomas.loc.gov/cgi-bin/bdquery/z?d107:H.R.3090:
Then click on the PDF link...
I think I found the answer to my question about software, I think you can
depreciate that too...I just need to read section 167(f)(1)(B) to see if
CircuitCam falls under that description...
-Steve Gregory-
> I also forwarded this to our financial folks, because frankly I don't know
> what its impact is to my company. I am making a $147k capital purchase
> now, so what is the bottom line benefit to my company? Any ideas?
>
> Howard Watson
> Manufacturing Engineer
> AMETEK/Dixson
>
--part1_49.1ad0e868.29d4a69f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Howard!
<BR>
<BR>I found a link that has the whole bill in a *.PDF file. Go to:
<BR>
<BR>http://thomas.loc.gov/cgi-bin/bdquery/z?d107:H.R.3090:
<BR>
<BR>Then click on the </FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><U>PDF</FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></U> link...
<BR>
<BR>I think I found the answer to my question about software, I think you can depreciate that too...I just need to read section 167(f)(1)(B) to see if CircuitCam falls under that description...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I also forwarded this to our financial folks, because frankly I don't know what its impact is to my company. I am making a $147k capital purchase now, so what is the bottom line benefit to my company? Any ideas?
<BR>
<BR>Howard Watson
<BR>Manufacturing Engineer
<BR>AMETEK/Dixson
<BR></BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
--part1_49.1ad0e868.29d4a69f_boundary--
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Date: Thu, 28 Mar 2002 10:58:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Heatsink wanted
X-To: Ken Carlile <[log in to unmask]>
Carlile, you aninmal, the following are but a few I use daily. Knowing you,
I'm sure you'll look at the second one first. I did.
http://www.accelindustrial.com/single2.html
http://www.usa-assmann.com/
http://www.serteksales.com/page7.html
http://www.surplusales.com/Heatsinks/HeatSink-1.html
http://www.chtechnology.com/customfr.htm
http://www.jdf.dk/menukole.htm
http:[log in to unmask]
http://www.micforg.co.jp/
http://www.qats.com/html/products.html
http://www.darrahelectric.com/
http://www.melcor.com/
http://www.wakefield.com/
http://www.thermalloy.com/
http://www.heatsink.com/bhs.html
Wakefield and Thermalloy are most famous.
MoonMan
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Date: Thu, 28 Mar 2002 11:08:10 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal coating: high humidity environment.
What is the name of the book that you referenced? Is it CLEANING AND
CONTAMINATION OF ELECTRONICS COMPONENTS AND ASSEMBLIES ?
Thanks,
Jason
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Date: Thu, 28 Mar 2002 09:32:41 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Debbie Goodwin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Debbie Goodwin <[log in to unmask]>
Subject: Re: standard package dimensions
X-To: "Dan R. Johnson" <[log in to unmask]>
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Hi Dan,
Our catalog of "Dummy" components contains most of this information as does
our website www.practicalcomponents.com <http://www.practicalcomponents.com>
Please contact me off line if you would like a hardcopy catalog sent to you.
We may also be able to help you with empty tubes/trays.
Sincerely,
Debbie Goodwin
Account Representative
10867 Portal Dr
Los Alamitos, CA 90720
Phone = (714) 252-0010
Fax = (714) 252-0026
PLEASE NOTE - Effective Immediately New e-mail address is:
[log in to unmask]
__________________________________________________
This message is intended for the use of the individual entity to which it is
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is not the intended recipient, or the employee or agent responsible for
delivering the message to the intended recipient, you are hereby notified
that any dissemination, distribution or copying of this communication is
strictly prohibited. If you have received this communication in error,
please notify us immediately by calling
714.252.0010 or returning the original message to us. Thank You.
-----Original Message-----
From: Dan R. Johnson [mailto:[log in to unmask]]
Sent: Thursday, March 28, 2002 9:00 AM
To: [log in to unmask]
Subject: [TN] standard package dimensions
Does anyone know of a web site that gives standard dimensions for QFP, PLCC,
etc.?
We have a couple of new products coming out and I need to find shipping
tubes, hopefully off the shelf.
The parts are .175" X .175" X .066", .190" X .220" X .065, and .276" X .378"
X .092.
Thanks,
Dan
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<DIV><FONT face=Arial size=2><SPAN class=260234517-28032002>Hi
Dan,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=260234517-28032002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=260234517-28032002>Our catalog of
"Dummy" components contains most of this information as does our website <FONT
color=#000000><A
href="http://www.practicalcomponents.com">www.practicalcomponents.com</A></FONT></SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=260234517-28032002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=260234517-28032002>Please contact me
off line if you would like a hardcopy catalog sent to you.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=260234517-28032002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=260234517-28032002>We may also be able
to help you with empty tubes/trays.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=260234517-28032002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN
class=260234517-28032002>Sincerely,</SPAN></FONT></DIV>
<P><FONT face=Arial size=2>Debbie Goodwin</FONT> <BR><FONT face=Arial
size=2>Account Representative</FONT> <BR><FONT face=Arial size=2>10867 Portal
Dr</FONT> <BR><FONT face=Arial size=2>Los Alamitos, CA 90720</FONT> <BR><FONT
face=Arial size=2>Phone = (714) 252-0010 </FONT><BR><FONT face=Arial size=2>Fax
= (714) 252-0026</FONT> <BR><FONT face=Arial size=2>PLEASE NOTE - Effective
Immediately New e-mail address is: [log in to unmask]</FONT>
<BR><FONT face=Arial
size=2>__________________________________________________</FONT> <BR><FONT
face=Arial size=1>This message is intended for the use of the individual entity
to which it is addressed and may contain information that is privileged,
confidential and exempt from disclosure under applicable law. If the
reader of this message is not the intended recipient, or the employee or agent
responsible for delivering the message to the intended recipient, you are hereby
notified that any dissemination, distribution or copying of this communication
is strictly prohibited. If you have received this communication in error,
please notify us immediately by calling </FONT></P>
<P><FONT face=Arial size=1>714.252.0010 or returning the original message to
us. Thank You.</FONT> </P>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Dan R. Johnson
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, March 28, 2002 9:00
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] standard package
dimensions<BR><BR></DIV></FONT>
<DIV><FONT face=Arial size=2>Does anyone know of a web site that gives
standard dimensions for QFP, PLCC, etc.?</FONT></DIV>
<DIV><FONT face=Arial size=2>We have a couple of new products coming out and I
need to find shipping tubes, hopefully off the shelf.</FONT></DIV>
<DIV><FONT face=Arial size=2>The parts are .175" X .175" X .066", .190" X
.220" X .065, and .276" X .378" X .092.</FONT></DIV>
<DIV><FONT face=Arial size=2>Thanks,</FONT></DIV>
<DIV><FONT face=Arial size=2>Dan</FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Mar 2002 10:45:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Board Panelization
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Good day folks.
If a guy who has never been involved in board panelizations wanted to get in
and really
learn the how too's. Where and how would I go about this?
Thanks to all for your undying commitment to a better Industry by the way.
Barry.
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Date: Thu, 28 Mar 2002 09:44:27 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brummer Chuck <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brummer Chuck <[log in to unmask]>
Subject: Re: another materials question
X-To: "[log in to unmask]" <[log in to unmask]>
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Mark,
A rule of thumb is that the greater the resin content the worse the
dimensional stability. Lighter glass will also have different thread counts
in each direction.
Chuck Brummer
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, March 26, 2002 10:05 PM
To: [log in to unmask]
Subject: [TN] another materials question
I'm learning about laminate materials and read with interest several recent
tecnet emails on the subject.
I'd like to submit a question about a particular construction that is a
challenge with respect to registration.
The construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The construction
is balanced with respect to copper weights, glass styles, core thicknesses,
and prepreg openings.
What I am observing with this part is variation in how much certain cores
shrink, lot to lot,
and variation that I would describe as a shift or possibly a rotation in
some of the internal layers.
Am I correct in assuming that these thin cores and these particular prepregs
will contribute to lower yields due to misregistration? If anyone would
care to offer up ideas on how to tackle the registration challenge that I am
observing on this kind of construction, I would appreciate hearing your
ideas.
Mark J.
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<DIV><SPAN class=710505317-28032002><FONT face=Arial color=#0000ff
size=2>Mark,</FONT></SPAN></DIV>
<DIV><SPAN class=710505317-28032002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=710505317-28032002><FONT face=Arial color=#0000ff size=2>A rule
of thumb is that the greater the resin content the worse the dimensional
stability. Lighter glass will also have different thread counts in each
direction. </FONT></SPAN></DIV>
<DIV><SPAN class=710505317-28032002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=710505317-28032002><FONT face=Arial color=#0000ff size=2>Chuck
Brummer</FONT></SPAN></DIV>
<DIV><SPAN class=710505317-28032002></SPAN> </DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, March 26, 2002 10:05
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] another materials
question<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>I'm
learning about laminate materials and read with interest several recent tecnet
emails on the subject. <BR>I'd like to submit a question about a particular
construction that is a challenge with respect to registration. <BR><BR>The
construction is all 2 core and 3 core. The prepregs are 1-106 and
1-1080, which I have learned are described as resin rich. The
construction is balanced with respect to copper weights, glass styles, core
thicknesses, and prepreg openings. <BR><BR>What I am observing with this part
is variation in how much certain cores shrink, lot to lot, <BR>and variation
that I would describe as a shift or possibly a rotation in some of the
internal layers. <BR><BR>Am I correct in assuming that these thin cores
and these particular prepregs will contribute to lower yields due to
misregistration? If anyone would care to offer up ideas on how to
tackle the registration challenge that I am observing on this kind of
construction, I would appreciate hearing your ideas. <BR><BR>Mark J.</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Mar 2002 09:47:25 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brummer Chuck <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brummer Chuck <[log in to unmask]>
Subject: Re: Imaging Clean Rooms
X-To: Ken Hafften <[log in to unmask]>
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IPC has a guide for cleanrooms. TA-724. Look that up.
Chuck Brummer
Acuson
-----Original Message-----
From: Ken Hafften [mailto:[log in to unmask]]
Sent: Wednesday, March 27, 2002 6:19 AM
To: [log in to unmask]
Subject: [TN] Imaging Clean Rooms
We are in the process of evaluating our clean room for inner and outer layer
circuit imaging. I am interested in finding out more information on the use
of clean rooms for printed circuit processing, particularly imaging. This
would include not only clean room requirements for imaging .003" lines but
also methods to achieve the required level of cleanliness. There seems to
be alot of information for processing microelectronics but not for printed
circuits. Thanks in advance for any help.
----------------------------------------------------------------------------
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<TITLE>RE: [TN] Imaging Clean Rooms</TITLE>
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<P><FONT SIZE=3D2>IPC has a guide for cleanrooms. TA-724. =
Look that up.</FONT>
<BR><FONT SIZE=3D2>Chuck Brummer</FONT>
<BR><FONT SIZE=3D2>Acuson</FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Ken Hafften [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<=
/FONT>
<BR><FONT SIZE=3D2>Sent: Wednesday, March 27, 2002 6:19 AM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Imaging Clean Rooms</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>We are in the process of evaluating our clean room =
for inner and outer layer</FONT>
<BR><FONT SIZE=3D2>circuit imaging. I am interested in finding =
out more information on the use</FONT>
<BR><FONT SIZE=3D2>of clean rooms for printed circuit processing, =
particularly imaging. This</FONT>
<BR><FONT SIZE=3D2>would include not only clean room requirements for =
imaging .003" lines but</FONT>
<BR><FONT SIZE=3D2>also methods to achieve the required level of =
cleanliness. There seems to</FONT>
<BR><FONT SIZE=3D2>be alot of information for processing =
microelectronics but not for printed</FONT>
<BR><FONT SIZE=3D2>circuits. Thanks in advance for any =
help.</FONT>
</P>
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Date: Thu, 28 Mar 2002 13:13:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charlie McMahon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charlie McMahon <[log in to unmask]>
Subject: Re: Board Panelization
X-To: Barry Gallegos <[log in to unmask]>
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Barry:
This is an issue close to my heart....
When panel choices are on the table, I have found there are no standard
methodologies that fit all.
The primary reason is due to costing drivers at the board fabricator and
placment/productivity constraints at the assembler
Therefore, the way to handle this challenge in my view is to provide the
individual board size to the fabricator for their review and
advisory as to #-up and breakaway methods. Pricing will follow.
Upon receipt of this information, submit same to the assembly folks for
ratification and or revision. Pricing will follow as well.
Both fabricator and assembler need to work together with you to attain
the most cost effective panel strategy for you,
the client, to meet your pricing goals.
Yes, this takes more effort....it need be done but once. However the
benefits in yield, productivity, cost and ultimately
higher margins to you, the client, can be enhanced.
Just a suggestion.
Charlie McMahon
Barry Gallegos wrote:
>Good day folks.
>If a guy who has never been involved in board panelizations wanted to get in
>and really
>learn the how too's. Where and how would I go about this?
>
>Thanks to all for your undying commitment to a better Industry by the way.
>
>Barry.
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
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Date: Thu, 28 Mar 2002 18:25:08 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: solder mask tape dots
X-To: Phil Nutting <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Yup - we are and you can try HumiSeal
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> Sent: 27 March 2002 15:12
> To: [log in to unmask]
> Subject: [TN] solder mask tape dots
>
>
> Here is another question for all you gurus.
>
> We have a hand build, through hole circuit board that has 8
> locations that must be free of solder for the next level of
> assembly. So far I can only find solder mask tape dots at
> Contact East. Are there any other suppliers out there? Our
> terminal measures 0.28 inch diameter, so a 0.3" pad might be just
> the thing.
>
> Thanks in advance,
>
> Phil
>
> ------------------------------------------------------------------
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>
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Date: Thu, 28 Mar 2002 18:25:05 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
X-To: Volkmar Huss <[log in to unmask]>
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Volkmar
As the Chairman of a new IEC committee to produce a "Process
Characterisation" specification, I can very probably help you.
That's the good news! The bad news is that we only have the spec in draft -
however, if you wish, I will try to send you something to consider but I
will have to send this off-line.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Volkmar Huss
> Sent: 26 March 2002 14:37
> To: [log in to unmask]
> Subject: [TN] Measuring "No Clean" process quality
>
>
> Hi TechNetters,
>
> we are working on defining our "No Clean" soldering process. The
> solder-paste and flux manufacturers certify the "No Clean" capability of
>
> their products to some extend, but what is the definition of "No Clean"?
>
> And I don't mean the statement, that only inert residues of flux and
> solder-paste additives remain on the board.
> Are there any standards that can used as a reference?
> How do you measure the:
> "No Clean" capability of solder paste, flux and tubular solder with flux
>
> core?
> "No Clean" quality of printed board assemblies?
> "No Clean" quality of printed board assemblies onto which devices have
> been hand-soldered?
> and all of this for prototype and series production?
>
> I have gleaned some insights from the TechNet archives, but any
> additional input is very welcome.
>
> Best regards
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> --
> Best regards / Mit freundlichen Grüßen
>
> Volkmar Huß
>
> Engineering Electronic Circuit Boards
> Aufbau- und Verbindungstechnik
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
> DRÄGER ELECTRONICS
>
> Draeger Electronics GmbH
> Moislinger Allee 53-55
> D-23558 Lübeck
>
> Tel: +49-451-882-3998
> Fax: +49-451-882-4365
> mailto:[log in to unmask]
> Website http://www.draeger.com/de/EL
> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
>
>
> ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿý7œ†w
> 1¨¥.+-¦º/‰×jÆŸç¬z»âqæò
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>
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Date: Thu, 28 Mar 2002 14:00:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Maddox, Allen T" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Maddox, Allen T" <[log in to unmask]>
Subject: Re: standard package dimensions
X-To: "Dan R. Johnson" <[log in to unmask]>
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Try here:
http://www.jedec.org/download/default.cfm
<http://www.jedec.org/download/default.cfm>
Allen M.
-----Original Message-----
From: Dan R. Johnson [mailto:[log in to unmask]]
Sent: Thursday, March 28, 2002 12:00 PM
To: [log in to unmask]
Subject: [TN] standard package dimensions
Does anyone know of a web site that gives standard dimensions for QFP, PLCC,
etc.?
We have a couple of new products coming out and I need to find shipping
tubes, hopefully off the shelf.
The parts are .175" X .175" X .066", .190" X .220" X .065, and .276" X .378"
X .092.
Thanks,
Dan
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Date: Thu, 28 Mar 2002 14:31:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: standard package dimensions
X-To: "Dan R. Johnson" <[log in to unmask]>
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------_=_NextPart_001_01C1D68F.2A8A744E
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Try
www.toplinedummy.com <http://www.toplinedummy.com>
shahed
-----Original Message-----
From: Dan R. Johnson [mailto:[log in to unmask]]
Sent: Thursday, March 28, 2002 12:00 PM
To: [log in to unmask]
Subject: [TN] standard package dimensions
Does anyone know of a web site that gives standard dimensions for QFP, PLCC,
etc.?
We have a couple of new products coming out and I need to find shipping
tubes, hopefully off the shelf.
The parts are .175" X .175" X .066", .190" X .220" X .065, and .276" X .378"
X .092.
Thanks,
Dan
------_=_NextPart_001_01C1D68F.2A8A744E
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><SPAN class=033573819-28032002><FONT face="Courier New"
color=#0000ff>Try</FONT></SPAN></DIV>
<DIV><SPAN class=033573819-28032002><FONT face="Courier New" color=#0000ff><A
href="http://www.toplinedummy.com">www.toplinedummy.com</A></FONT></SPAN></DIV>
<DIV> </DIV><SPAN class=033573819-28032002></SPAN><FONT
face="Courier New"><FONT color=#0000ff>shahed<SPAN
class=033573819-28032002></SPAN></FONT></FONT><BR><BR>
<P align=left><FONT face=AvantGarde> </FONT><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Dan R. Johnson
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, March 28, 2002 12:00
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] standard package
dimensions<BR><BR></FONT></P>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV><FONT face=Arial size=2>Does anyone know of a web site that gives
standard dimensions for QFP, PLCC, etc.?</FONT></DIV>
<DIV><FONT face=Arial size=2>We have a couple of new products coming out and I
need to find shipping tubes, hopefully off the shelf.</FONT></DIV>
<DIV><FONT face=Arial size=2>The parts are .175" X .175" X .066", .190" X
.220" X .065, and .276" X .378" X .092.</FONT></DIV>
<DIV><FONT face=Arial size=2>Thanks,</FONT></DIV>
<DIV><FONT face=Arial size=2>Dan</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1D68F.2A8A744E--
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Date: Thu, 28 Mar 2002 15:51:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Flex circuit design guidelines
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Hello Technet:
I'm looking for some design guidelines for a flex circuit. What factors
should be considered when designing a circuit used for continued flexing?
Foil thickness, bend radius, etc. I know that IPC 2223 has this info, but I
don't have a copy yet and need this information ASAP. Any information will
be helpful.
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 28 Mar 2002 16:20:19 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flex circuit design guidelines
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Hi Jim!
Here's a couple of links that might be helpful:
http://www.minco.com/pdf/aa24.pdf
http://www.allflexinc.com/desi.shtml
-Steve Gregory-
> Hello Technet:
> I'm looking for some design guidelines for a flex circuit. What factors
> should be considered when designing a circuit used for continued flexing?
> Foil thickness, bend radius, etc. I know that IPC 2223 has this info, but I
> don't have a copy yet and need this information ASAP. Any information will
> be helpful.
>
> Thanks,
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
--part1_102.12d97df1.29d4e313_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jim!
<BR>
<BR>Here's a couple of links that might be helpful:
<BR>
<BR>http://www.minco.com/pdf/aa24.pdf
<BR>http://www.allflexinc.com/desi.shtml
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello Technet:
<BR>I'm looking for some design guidelines for a flex circuit. What factors
<BR>should be considered when designing a circuit used for continued flexing?
<BR>Foil thickness, bend radius, etc. I know that IPC 2223 has this info, but I
<BR>don't have a copy yet and need this information ASAP. Any information will
<BR>be helpful.
<BR>
<BR>Thanks,
<BR>Jim Marsico
<BR>Senior Engineer
<BR>Production Engineering
<BR>EDO Electronics Systems Group
<BR>[log in to unmask] <mailto:[log in to unmask]>
<BR>631-595-5879
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_102.12d97df1.29d4e313_boundary--
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Date: Thu, 28 Mar 2002 16:59:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: Flex circuit design guidelines
MIME-Version: 1.0
Content-Type: text/plain
Hi Jim,
check http:\\www.mflex.com. They have a design manual. Just got my free copy
on CD.
Regards,
Ioan
> -----Original Message-----
> From: Marsico, James [SMTP:[log in to unmask]]
> Sent: Thursday, March 28, 2002 3:52 PM
> To: [log in to unmask]
> Subject: [TN] Flex circuit design guidelines
>
> Hello Technet:
> I'm looking for some design guidelines for a flex circuit. What factors
> should be considered when designing a circuit used for continued flexing?
> Foil thickness, bend radius, etc. I know that IPC 2223 has this info, but
> I
> don't have a copy yet and need this information ASAP. Any information
> will
> be helpful.
>
> Thanks,
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
> -------
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Date: Thu, 28 Mar 2002 23:13:30 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Board Panelization
X-To: Barry Gallegos <[log in to unmask]>
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Hi Barry,
One of the most important things to keep in mind when designing a =
panelization is how good your panel fits in the pcb-suppliers production =
panel, as this determines how efficient the material is used, and thus =
the price. With programs like KwickFit (www.micromeg.com, trial version =
available) it is easily demonstrated how large the differences can be.=20
The main problem I see is that as for an assembly guy it's hard to tell =
where the breakaway-tabs should be, as you need to inspect all the board =
layers (you'll want no tab where there's tracks close to it) which may =
take lots time. However, leaving it to the pcb vendor sometimes results =
in unpleasant surprises. I'd like to hear how other deal with this..... =
=20
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: Barry Gallegos=20
To: [log in to unmask]
Sent: Thursday, March 28, 2002 6:45 PM
Subject: [TN] Board Panelization
Good day folks.
If a guy who has never been involved in board panelizations wanted to =
get in
and really
learn the how too's. Where and how would I go about this?
Thanks to all for your undying commitment to a better Industry by the =
way.
Barry.
=
-------------------------------------------------------------------------=
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1.8d
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in
the BODY (NOT the subject field): SIGNOFF Technet
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[log in to unmask]: SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & =
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Please visit IPC web site http://www.ipc.org/html/forum.htm for =
additional
information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700 ext.5315
=
-------------------------------------------------------------------------=
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>Hi Barry,</DIV>
<DIV> </DIV>
<DIV>One of the most important things to keep in mind when designing a=20
panelization is how good your panel fits in the pcb-suppliers production =
panel,=20
as this determines how efficient the material is used, and =
thus the=20
price. With programs like KwickFit (<A=20
href=3D"http://www.micromeg.com">www.micromeg.com</A>, trial version=20
available) it is easily demonstrated how large the differences =
can=20
be. </DIV>
<DIV>The main problem I see is that as for an assembly guy it's hard to =
tell=20
where the breakaway-tabs should be, as you need to inspect all the board =
layers=20
(you'll want no tab where there's tracks close to it) which may take =
lots=20
time. However, leaving it to the pcb vendor sometimes results in =
unpleasant=20
surprises. I'd like to hear how other deal with=20
this..... </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV>http://<A href=3D"http://www.smtinfo.net">www.smtinfo.net</A></DIV>
<DIV> </DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial"><FONT face=3DVerdana =
size=3D3></FONT> </DIV>
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">Barry Gallegos</A> =
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 28, 2002 =
6:45=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Board =
Panelization</DIV>
<DIV><BR></DIV>Good day folks.<BR>If a guy who has never been involved =
in=20
board panelizations wanted to get in<BR>and really<BR>learn the how =
too's.=20
Where and how would I go about this?<BR><BR>Thanks to all for your =
undying=20
commitment to a better Industry by the=20
=
way.<BR><BR>Barry.<BR><BR>-----------------------------------------------=
----------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
text=20
in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To =
temporarily halt=20
delivery of Technet send e-mail to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet =
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Date: Thu, 28 Mar 2002 14:22:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
peter lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: LPI solder mask
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Does anyone know what the difference is between
Probimer 52 and Probimer 77 solder mask?
In particular, I would like more info. on the impact
of switching from 52 to 77 has on the manufacturing
process. i.e. Implications and impact on reflow,
conformal coating compatibility etc.
Rgds,
Peter
__________________________________________________
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Date: Thu, 28 Mar 2002 14:33:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Self life PC Boards
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello Technet,
Can someone tell me the shelf life of PC boards with HASL and immersion gold
finish?
Thanks,
Patrick
This e-mail may contain SEL confidential information. The opinions expressed
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Date: Thu, 28 Mar 2002 17:06:08 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Conformal Coating BGA's
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Peter! Cool, now your underfill rationale falls into place, especially
since you were reacting to a less-than-robust design. I have test boards in
the thermal cycle chamber right now in an attempt to understand just how
much of an "improvement" the underfill operation adds to the solder joint
thermal cycle fatigue life. And yes, underfill adds an extra processing
step thus increasing time and cost. If the underfill operation doesn't
result in a value added benefit for our use environments then it most
definitely won't be a suggested process addition. The EMMA project has
published an extensive data set on the impact of vibration on area array
components (BGA, CSP, FC) which might be useful to you. Contact Lee
Whiteman for access to the data ([log in to unmask]).
Dave
[log in to unmask] on 03/27/2002 06:22:10 PM
To: <[log in to unmask]>
cc:
Subject: Re: [TN] Conformal Coating BGA's
Hi, Dave,
Got a Coke to hand? OK. Reason for underfilling BGA's was that the first
BGA boards we had were designed and assembled for us by a s/c. The first
time we put them near any form of vibration, and it was gentle, they
failed. Investigation followed, and I learned more about BGA's, ENIG boards
and the poor manufacturing quality of whoever assembled the things.
I had a couple more boards assembled myself, full of sheer terror, as you
correctly guessed, of the ENIG and BGA horror stories I'd heard about, and
heard about what Underfills were supposed to do. So I opted to use it,
partly to fillin the air gap but mostly to add support to the solder joints
against creep fatigue.
I do know, though, that many high reliability appliactions do not underfill
their BGA's, but they've maybe had more money, resources, time and
experience to prove it isn't necessary with the processes they use. If I
could be confident enough, I wouldn't use it either - it's one more process
to take time and cost, right?
Peter
<ddhillma@rockwellco
llins.com> To: [log in to unmask],
DUNCAN Peter/Asst Prin
Engr/ST Aero/ST Group@ST
Domain
03/28/02 06:40 AM cc:
Subject: Re: [TN]
Conformal Coating BGA's
Hi Peter! You have me confused (which is a normal state for me if I don't
have a Coke in my hand). Collins has been using BGAs in avionics use
environments, not underfilled, with acrylic conformal coating very
successfully for a couple of years. What was the reason/rationale for using
BGAs with underfill? Was is an issue with solder joint thermal cycle
fatigue for a given use environment? Corrosion? Customer requirements?
Residual flux issues? Sheer terror of the unknown?
Dave Hillman
Rockwell Collins
[log in to unmask]
[log in to unmask]@ipc.org> on 03/26/2002 07:48:52 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to [log in to unmask]
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Conformal Coating BGA's
Hi, Bruce,
We apply Humiseal acrylic coating to boards that fit your description and
application precisely, except that we do underfill the BGA's with a
reworkable epoxy, applied after assembly. The only exception was for the
case of two boards destined for temperature cycling measurement, for which
we couldn't get a supply of underfill material at the time. We substituted
thinned Humiseal as the boards would not be flying, as we were concerned
about entrapped air and also no suuport for the BGA joints. Humiseal is not
a proper substitute for the specialised proper epoxy, but was sufficient
for our particular purpose.
The main issue as I see it would be moisture and other contaminants in the
entrapped air, but I have no first hand data to help you decide if that
causes problems or not.
Good luck
Peter
"Misner,
Bruce" To: [log in to unmask]
<Bruce_Misner cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
@ATK.COM> Aero/ST Group)
Sent by: Subject: [TN] Conformal
Coating BGA's
TechNet
<[log in to unmask]
ORG>
03/20/02
03:48 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Misner,
Bruce"
My question of the day: Is anyone conformal coating (not parylene) plastic
BGA's on FR-4 in Hi-Rel applications (aircraft; -20 to +71C ambient
operating temperature requirement) without benefit of an underfil? If yes,
has entrapped air been a major issue? Anyone care to comment on this
approach?
Regards,
Bruce Misner
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=========================================================================
Date: Thu, 28 Mar 2002 17:22:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brad Mecham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Mecham <[log in to unmask]>
Subject: SMT Ceramic Resonators
Does someone know if there is an IPC standard for a SMT Ceramic Resonators
which has Castellated Terminations? Does IPC require a good Castellated
fillet on both sides of the part even though the pad is continuos?
On the middle pad we are getting good wetting on one of the Castellated
terminals. However the other side does not have a good fillet. I feel
that since the part has a pad all the way underneath itself, that a good
Castellated terminal one side means that the bottom pad is also soldered.
I guess the question I am asking is, according to IPC do Castellated
Terminations (section 12.2.4 of IPC-A-610 C) only apply to Leadless Chip
Carriers or any part that has a castellated terminal. Any help on this
would be greatly appreciated.
Thanks,
Brad Mecham
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=========================================================================
Date: Thu, 28 Mar 2002 21:43:10 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: Conformal Coating BGA's
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Dave,
Just curious on this one. When you apply Humiseal to a board with BGA's
with no underfill, I take that to mean the coating just bridges the gap
between part and board around the perimeter of the BGA without wicking
underneath very far. This traps air under the BGA. Obviously this works
fine, as you have been using it in avionics for some time and that is a
tough environment. My naive question is why doesn't the coating around the
BGA perimeter blow out when the trapped air under the BGA heats up due to
power dissipation in the BGA itself? If it was going to happen at all, your
application is possibly a worst case with the combination of high ambient
temperature and low ambient pressure.
I would also be interested to know the results of your test to see how the
underfill affects the failure rate due to temperature cycling. Since
neither the underfill nor the conformal coating will really keep moisture
out, it would be nice to know if there are any real benefits conferred by
this extra processing step.
Seth Goodman
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dave Hillman
Sent: Thursday, March 28, 2002 5:06 PM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating BGA's
Hi Peter! Cool, now your underfill rationale falls into place, especially
since you were reacting to a less-than-robust design. I have test boards in
the thermal cycle chamber right now in an attempt to understand just how
much of an "improvement" the underfill operation adds to the solder joint
thermal cycle fatigue life. And yes, underfill adds an extra processing
step thus increasing time and cost. If the underfill operation doesn't
result in a value added benefit for our use environments then it most
definitely won't be a suggested process addition. The EMMA project has
published an extensive data set on the impact of vibration on area array
components (BGA, CSP, FC) which might be useful to you. Contact Lee
Whiteman for access to the data ([log in to unmask]).
Dave
[log in to unmask] on 03/27/2002 06:22:10 PM
To: <[log in to unmask]>
cc:
Subject: Re: [TN] Conformal Coating BGA's
Hi, Dave,
Got a Coke to hand? OK. Reason for underfilling BGA's was that the first
BGA boards we had were designed and assembled for us by a s/c. The first
time we put them near any form of vibration, and it was gentle, they
failed. Investigation followed, and I learned more about BGA's, ENIG boards
and the poor manufacturing quality of whoever assembled the things.
I had a couple more boards assembled myself, full of sheer terror, as you
correctly guessed, of the ENIG and BGA horror stories I'd heard about, and
heard about what Underfills were supposed to do. So I opted to use it,
partly to fillin the air gap but mostly to add support to the solder joints
against creep fatigue.
I do know, though, that many high reliability appliactions do not underfill
their BGA's, but they've maybe had more money, resources, time and
experience to prove it isn't necessary with the processes they use. If I
could be confident enough, I wouldn't use it either - it's one more process
to take time and cost, right?
Peter
<ddhillma@rockwellco
llins.com> To: [log in to unmask],
DUNCAN Peter/Asst Prin
Engr/ST Aero/ST Group@ST
Domain
03/28/02 06:40 AM cc:
Subject: Re: [TN]
Conformal Coating BGA's
Hi Peter! You have me confused (which is a normal state for me if I don't
have a Coke in my hand). Collins has been using BGAs in avionics use
environments, not underfilled, with acrylic conformal coating very
successfully for a couple of years. What was the reason/rationale for using
BGAs with underfill? Was is an issue with solder joint thermal cycle
fatigue for a given use environment? Corrosion? Customer requirements?
Residual flux issues? Sheer terror of the unknown?
Dave Hillman
Rockwell Collins
[log in to unmask]
[log in to unmask]@ipc.org> on 03/26/2002 07:48:52 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to [log in to unmask]
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Conformal Coating BGA's
Hi, Bruce,
We apply Humiseal acrylic coating to boards that fit your description and
application precisely, except that we do underfill the BGA's with a
reworkable epoxy, applied after assembly. The only exception was for the
case of two boards destined for temperature cycling measurement, for which
we couldn't get a supply of underfill material at the time. We substituted
thinned Humiseal as the boards would not be flying, as we were concerned
about entrapped air and also no suuport for the BGA joints. Humiseal is not
a proper substitute for the specialised proper epoxy, but was sufficient
for our particular purpose.
The main issue as I see it would be moisture and other contaminants in the
entrapped air, but I have no first hand data to help you decide if that
causes problems or not.
Good luck
Peter
"Misner,
Bruce" To: [log in to unmask]
<Bruce_Misner cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
@ATK.COM> Aero/ST Group)
Sent by: Subject: [TN] Conformal
Coating BGA's
TechNet
<[log in to unmask]
ORG>
03/20/02
03:48 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Misner,
Bruce"
My question of the day: Is anyone conformal coating (not parylene) plastic
BGA's on FR-4 in Hi-Rel applications (aircraft; -20 to +71C ambient
operating temperature requirement) without benefit of an underfil? If yes,
has entrapped air been a major issue? Anyone care to comment on this
approach?
Regards,
Bruce Misner
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=========================================================================
Date: Fri, 29 Mar 2002 11:08:46 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Vinit Verma <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Vinit Verma <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Earl,
Thanks for your "condolences". I would'nt mind your posting the photographs!
Rather it might enable somebody else too to give some insight!!
Where would you post them anyway?? Steve's site?
Regards
Vinit
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, March 28, 2002 5:36 PM
To: [log in to unmask]
Subject: Re: [TN] Blistering in PCBs
I completely agree with the following:
IHRlbXBvcmFyaWx5IGhhbHQgZGVsaXZlcnkgb2YgVGVjaG5ldCBzZW5kIGUtbWFpbCB0byBMaXN0
c2VydkBpcGMub3JnOiBTRVQgVGVjaG5ldCBOT01BSUwNCj5UbyByZWNlaXZlIE9ORSBtYWlsaW5n
IHBlciBkYXkgb2YgYWxsIHRoZSBwb3N0czogc2VuZCBlLW1haWwgdG8gTGlzdHNlcnZAaXBjLm9y
ZzogU0VUIFRlY2huZXQgRGlnZXN0DQo+U2VhcmNo
However, Vinit sent me some really ugly photos showing the condition. Out of
respect for his privacy and sorrow, I won't even attempt posting them unless
he wishes. Never seen anything so ugly.
MoonMan
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=========================================================================
Date: Fri, 29 Mar 2002 08:18:47 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Conformal coating: high humidity environment.
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
This seems to be out of context, but I think that this was referred to
in the original thread
Brian
[log in to unmask] wrote:
>
> What is the name of the book that you referenced? Is it CLEANING AND
> CONTAMINATION OF ELECTRONICS COMPONENTS AND ASSEMBLIES ?
>
> Thanks,
> Jason
>
> ---------------------------------------------------------------------------------
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Date: Fri, 29 Mar 2002 06:49:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: Vinit Verma <[log in to unmask]>
Vinit,
Ok, here we go. Never seen nothin' like these before. Oh well, maybe once
when I was a "young gun" process engineer at Xerox. That's another story
I'll not bore anyone with now.
Concerning the pics, it is obvious there is delam everywhere but maybe the
edges. Vinitdelam3's discoloration also is delamination, not solder mask
related.
Someone else take shots at this and Vinit's supplier. This shop shoundn't
exist unless they just lost it all on his boards ONE PING ONLY PLEASE.
A pleasure to serve Vinit. Don't often get to see how bad something can be
besides a train wreck.
MoonMan
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Date: Fri, 29 Mar 2002 09:13:26 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flex circuit design guidelines
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hello Jim,
Quick thought for flex...
Use .002 1/1 or half over half adhesiveless
Use .001 cover coat (Polyimide Kapton)
Termination of cover coat .025-.075 at rigid junction requires this area to
be via free for .10 inch... thats a tuff one I know
Traces only perpendicularly transition rigid flex
Traces only perpendicularly transition rigid flex
Relieved planes in flex are very nice for flexing
No adhesive between flex pairs
Either epoxy or poly rigid works
complex flex will require preheat and a fixture after assembly for shape
forming
If your doing FR4 flex things are different
I love flex
Boston Brad
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Date: Fri, 29 Mar 2002 09:32:55 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Blistering in PCBs
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Hey Earl
Where can I see these photos? Don't see them on Steve's site.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, March 29, 2002 6:49 AM
To: [log in to unmask]
Subject: Re: [TN] Blistering in PCBs
Vinit,
Ok, here we go. Never seen nothin' like these before. Oh well, maybe once
when I was a "young gun" process engineer at Xerox. That's another story
I'll not bore anyone with now.
Concerning the pics, it is obvious there is delam everywhere but maybe the
edges. Vinitdelam3's discoloration also is delamination, not solder mask
related.
Someone else take shots at this and Vinit's supplier. This shop shoundn't
exist unless they just lost it all on his boards ONE PING ONLY PLEASE.
A pleasure to serve Vinit. Don't often get to see how bad something can be
besides a train wreck.
MoonMan
---------------------------------------------------------------------------------
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Date: Fri, 29 Mar 2002 10:48:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: solder paste registration
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0053_01C1D70F.448172A0"
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------=_NextPart_000_0053_01C1D70F.448172A0
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Ladies and Gentlemen,
We are having a major problem with an assembly house with registering
the solder paste to surface mount features prior to pick and place. They
are claiming that the boards are growing/shrinking some 15-20 mils.
We have done extensive measuring on unpopulated boards in-house
and cannot see more than 3-5 mils misregistration. The panel size
is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
throughout the panel. Overall thickness .080. Is it possible that the =
mesh
screen that they are using can expand/contract over time? has anyone
heard of this experienced this situation before. Any information would =
be
greatly appreciated.
Thanks
Tony Steinke
AIT-Atlanta
------=_NextPart_000_0053_01C1D70F.448172A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#fff8e0>
<DIV><FONT face=3DArial size=3D2>Ladies and Gentlemen,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>We are having a major problem with an =
assembly=20
house with registering</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>the solder paste to surface mount =
features prior to=20
pick and place. They</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>are claiming that the boards are =
growing/shrinking=20
some 15-20 mils.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>We have done extensive measuring on =
unpopulated=20
boards in-house</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>and cannot see more than 3-5 mils =
misregistration.=20
The panel size</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>is approximately 14.00 x 16.00 inches, =
20-24 mil=20
pitch, and 15 BGA's</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>throughout the panel. Overall thickness =
.080. Is it=20
possible that the mesh</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>screen that they are using can =
expand/contract over=20
time? has anyone</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>heard of this experienced this =
situation before.=20
Any information would be</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>greatly appreciated.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Tony Steinke</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>AIT-Atlanta</FONT></DIV></BODY></HTML>
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Date: Fri, 29 Mar 2002 11:08:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: solder paste registration
X-To: tony steinke <[log in to unmask]>
MIME-Version: 1.0
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I have seen 3-5 mils with our boards. Nothing more. What material are they
using for the stencil and the board?
-----Original Message-----
From: tony steinke [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 1:49 PM
To: [log in to unmask]
Subject: [TN] solder paste registration
Ladies and Gentlemen,
We are having a major problem with an assembly house with registering
the solder paste to surface mount features prior to pick and place. They
are claiming that the boards are growing/shrinking some 15-20 mils.
We have done extensive measuring on unpopulated boards in-house
and cannot see more than 3-5 mils misregistration. The panel size
is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
throughout the panel. Overall thickness .080. Is it possible that the mesh
screen that they are using can expand/contract over time? has anyone
heard of this experienced this situation before. Any information would be
greatly appreciated.
Thanks
Tony Steinke
AIT-Atlanta
------_=_NextPart_001_01C1D73B.FA2DC370
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=#fff8e0>
<DIV><SPAN class=006001516-29032002><FONT face=Arial color=#0000ff size=2>I have
seen 3-5 mils with our boards. Nothing more. What material are they
using for the stencil and the board?</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> tony steinke
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, March 29, 2002 1:49
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] solder paste
registration<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Ladies and Gentlemen,</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>We are having a major problem with an assembly
house with registering</FONT></DIV>
<DIV><FONT face=Arial size=2>the solder paste to surface mount features prior
to pick and place. They</FONT></DIV>
<DIV><FONT face=Arial size=2>are claiming that the boards are
growing/shrinking some 15-20 mils.</FONT></DIV>
<DIV><FONT face=Arial size=2>We have done extensive measuring on unpopulated
boards in-house</FONT></DIV>
<DIV><FONT face=Arial size=2>and cannot see more than 3-5 mils
misregistration. The panel size</FONT></DIV>
<DIV><FONT face=Arial size=2>is approximately 14.00 x 16.00 inches, 20-24 mil
pitch, and 15 BGA's</FONT></DIV>
<DIV><FONT face=Arial size=2>throughout the panel. Overall thickness .080. Is
it possible that the mesh</FONT></DIV>
<DIV><FONT face=Arial size=2>screen that they are using can expand/contract
over time? has anyone</FONT></DIV>
<DIV><FONT face=Arial size=2>heard of this experienced this situation before.
Any information would be</FONT></DIV>
<DIV><FONT face=Arial size=2>greatly appreciated.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Thanks</FONT></DIV>
<DIV><FONT face=Arial size=2>Tony Steinke</FONT></DIV>
<DIV><FONT face=Arial size=2>AIT-Atlanta</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1D73B.FA2DC370--
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Date: Fri, 29 Mar 2002 11:18:52 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Blistering in PCBs
MIME-Version: 1.0
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boundary="part1_59.19574e84.29d5edec_boundary"
--part1_59.19574e84.29d5edec_boundary
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Don and Everybody!
The pic's are now up! Go to: http://www.stevezeva.homestead.com
I gotta say, those are some UGLY boards!
-Steve Gregory-
> Hey Earl
>
> Where can I see these photos? Don't see them on Steve's site.
>
> Don Vischulis
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: Friday, March 29, 2002 6:49 AM
> To: [log in to unmask]
> Subject: Re: [TN] Blistering in PCBs
>
>
> Vinit,
>
> Ok, here we go. Never seen nothin' like these before. Oh well, maybe once
> when I was a "young gun" process engineer at Xerox. That's another story
> I'll not bore anyone with now.
>
> Concerning the pics, it is obvious there is delam everywhere but maybe the
> edges. Vinitdelam3's discoloration also is delamination, not solder mask
> related.
>
> Someone else take shots at this and Vinit's supplier. This shop shoundn't
> exist unless they just lost it all on his boards ONE PING ONLY PLEASE.
>
> A pleasure to serve Vinit. Don't often get to see how bad something can be
> besides a train wreck.
>
> MoonMan
>
--part1_59.19574e84.29d5edec_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Don and Everybody!<BR>
<BR>
The pic's are now up! Go to: http://www.stevezeva.homestead.com<BR>
<BR>
I gotta say, those are some UGLY boards!<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hey Earl<BR>
<BR>
Where can I see these photos? Don't see them on Steve's site.<BR>
<BR>
Don Vischulis<BR>
<BR>
-----Original Message-----<BR>
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon<BR>
Sent: Friday, March 29, 2002 6:49 AM<BR>
To: [log in to unmask]<BR>
Subject: Re: [TN] Blistering in PCBs<BR>
<BR>
<BR>
Vinit,<BR>
<BR>
Ok, here we go. Never seen nothin' like these before. Oh well, maybe once<BR>
when I was a "young gun" process engineer at Xerox. That's another story<BR>
I'll not bore anyone with now.<BR>
<BR>
Concerning the pics, it is obvious there is delam everywhere but maybe the<BR>
edges. Vinitdelam3's discoloration also is delamination, not solder mask<BR>
related.<BR>
<BR>
Someone else take shots at this and Vinit's supplier. This shop shoundn't<BR>
exist unless they just lost it all on his boards ONE PING ONLY PLEASE.<BR>
<BR>
A pleasure to serve Vinit. Don't often get to see how bad something can be<BR>
besides a train wreck.<BR>
<BR>
MoonMan<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Fri, 29 Mar 2002 11:47:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: solder paste registration
X-To: tony steinke <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/html; charset="us-ascii"
<html>
We have only seen stretch on our stencils cause a problem when they are
old and very used. At this point it is best to purchase a new stencil, as
it will pay for itself with reduced defects almost immediately. It may be
worth while to see how the board is fixtured, as it can sometimes shift
during the print cycle from time to time and cause problems. <br><br>
Hope some of this is useful.<br><br>
Ed<br><br>
<br><br>
<br>
At 10:48 AM 3/29/2002 -0800, you wrote:<br>
<blockquote type=cite class=cite cite><font face="arial" size=2>Ladies
and Gentlemen,</font><br>
<br>
<font face="arial" size=2>We are having a major problem with an assembly
house with registering</font><br>
<font face="arial" size=2>the solder paste to surface mount features
prior to pick and place. They</font><br>
<font face="arial" size=2>are claiming that the boards are
growing/shrinking some 15-20 mils.</font><br>
<font face="arial" size=2>We have done extensive measuring on unpopulated
boards in-house</font><br>
<font face="arial" size=2>and cannot see more than 3-5 mils
misregistration. The panel size</font><br>
<font face="arial" size=2>is approximately 14.00 x 16.00 inches, 20-24
mil pitch, and 15 BGA's</font><br>
<font face="arial" size=2>throughout the panel. Overall thickness .080.
Is it possible that the mesh</font><br>
<font face="arial" size=2>screen that they are using can expand/contract
over time? has anyone</font><br>
<font face="arial" size=2>heard of this experienced this situation
before. Any information would be</font><br>
<font face="arial" size=2>greatly appreciated.</font><br>
<br>
<font face="arial" size=2>Thanks</font><br>
<font face="arial" size=2>Tony Steinke</font><br>
<font face="arial" size=2>AIT-Atlanta</font></blockquote><br>
</html>
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Date: Fri, 29 Mar 2002 19:01:59 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: solder paste registration
X-To: tony steinke <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Tony
You don't say what type of screen is being used. If it's a
nylon/polyester one, then I'd say you're in deep trouble. If it's a
stainless steel one, it can still stretch as the squeegee distorts it.
You really should use a stencil.
Brian
> tony steinke wrote:
>
> Ladies and Gentlemen,
>
> We are having a major problem with an assembly house with registering
> the solder paste to surface mount features prior to pick and place.
> They
> are claiming that the boards are growing/shrinking some 15-20 mils.
> We have done extensive measuring on unpopulated boards in-house
> and cannot see more than 3-5 mils misregistration. The panel size
> is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
> throughout the panel. Overall thickness .080. Is it possible that the
> mesh
> screen that they are using can expand/contract over time? has anyone
> heard of this experienced this situation before. Any information would
> be
> greatly appreciated.
>
> Thanks
> Tony Steinke
> AIT-Atlanta
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=========================================================================
Date: Fri, 29 Mar 2002 11:06:21 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jorge Santana <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Santana <[log in to unmask]>
Subject: Underwater application
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi
We need found out a way to keep the board working in a underwater
environment, there is possibilities of occasional flood inside the box
enclosure and the board has to survive, the water came from rain.
Folks from automotive world " under hood applications" have this
experience since cars are subject to flood also.
What kind of material is used ? What recommended thickness ?
We are thinking about RTV Elastomeric Conformal Coating.
It is not necessary to say that the solution should be not expensive and
effective.
Thanks
Jorge Santana
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Date: Fri, 29 Mar 2002 12:15:04 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: solder paste registration
MIME-Version: 1.0
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Hey Folks,
The solder paste is being applied with a stencil. Thanks for all the info.
Tony steinke
----- Original Message -----
From: Brian Ellis <[log in to unmask]>
To: TechNet E-Mail Forum. <[log in to unmask]>; tony steinke
<[log in to unmask]>
Sent: Friday, March 29, 2002 9:01 AM
Subject: Re: [TN] solder paste registration
> Tony
>
> You don't say what type of screen is being used. If it's a
> nylon/polyester one, then I'd say you're in deep trouble. If it's a
> stainless steel one, it can still stretch as the squeegee distorts it.
> You really should use a stencil.
>
> Brian
>
> > tony steinke wrote:
> >
> > Ladies and Gentlemen,
> >
> > We are having a major problem with an assembly house with registering
> > the solder paste to surface mount features prior to pick and place.
> > They
> > are claiming that the boards are growing/shrinking some 15-20 mils.
> > We have done extensive measuring on unpopulated boards in-house
> > and cannot see more than 3-5 mils misregistration. The panel size
> > is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
> > throughout the panel. Overall thickness .080. Is it possible that the
> > mesh
> > screen that they are using can expand/contract over time? has anyone
> > heard of this experienced this situation before. Any information would
> > be
> > greatly appreciated.
> >
> > Thanks
> > Tony Steinke
> > AIT-Atlanta
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Date: Fri, 29 Mar 2002 09:30:28 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Underwater application
X-To: [log in to unmask]
MIME-Version: 1.0
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hi,
i know, i know...here i go again with parylene. but it will work.
phil
-----Original Message-----
From: Jorge Santana [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 9:06 AM
To: [log in to unmask]
Subject: [TN] Underwater application
Hi
We need found out a way to keep the board working in a underwater
environment, there is possibilities of occasional flood inside the box
enclosure and the board has to survive, the water came from rain.
Folks from automotive world " under hood applications" have this
experience since cars are subject to flood also.
What kind of material is used ? What recommended thickness ?
We are thinking about RTV Elastomeric Conformal Coating.
It is not necessary to say that the solution should be not expensive and
effective.
Thanks
Jorge Santana
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Date: Fri, 29 Mar 2002 11:45:37 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: solder paste registration
X-To: [log in to unmask]
Tony,
You know the stencil is not the first concern. The board may be very
different than the foil as it too moves though the stencil is pretty set in
concrete upon receipt. Always see no green when the stencil is ready for
printing.
Earl
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Date: Fri, 29 Mar 2002 12:54:37 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: solder paste registration
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_141.bfb2ba6.29d6045d_boundary"
--part1_141.bfb2ba6.29d6045d_boundary
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Hi Tony!
How old is the stencil? I think for it to stretch it would have to quite old
and have been used to print thousands of boards...stainless steel (which is
the standard) doesn't stretch that much...
What it could be is that the tension of the stencil within the frame is not
what it should be, and along with high squeegee pressure, is pulling the
stencil off registration in the direction of the print stroke. I've seen that
happen even with a fairly new stencil when there has been to much squeegee
pressure set in the printer program...
I can just about bet it has something to do with either machine set-up, or a
loose stencil...and NOT the board.
-Steve Gregory-
> Ladies and Gentlemen,
>
> We are having a major problem with an assembly house with registering
> the solder paste to surface mount features prior to pick and place. They
> are claiming that the boards are growing/shrinking some 15-20 mils.
> We have done extensive measuring on unpopulated boards in-house
> and cannot see more than 3-5 mils misregistration. The panel size
> is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
> throughout the panel. Overall thickness .080. Is it possible that the mesh
> screen that they are using can expand/contract over time? has anyone
> heard of this experienced this situation before. Any information would be
> greatly appreciated.
>
> Thanks
> Tony Steinke
> AIT-Atlanta
>
--part1_141.bfb2ba6.29d6045d_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#fff8e0"><FONT SIZE=2>Hi Tony!<BR>
<BR>
How old is the stencil? I think for it to stretch it would have to quite old and have been used to print thousands of boards...stainless steel (which is the standard) doesn't stretch that much...<BR>
<BR>
What it could be is that the tension of the stencil within the frame is not what it should be, and along with high squeegee pressure, is pulling the stencil off registration in the direction of the print stroke. I've seen that happen even with a fairly new stencil when there has been to much squeegee pressure set in the printer program...<BR>
<BR>
I can just about bet it has something to do with either machine set-up, or a loose stencil...and NOT the board.<BR>
<BR>
-Steve Gregory- <BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Ladies and Gentlemen,</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">We are having a major problem with an assembly house with registering</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">the solder paste to surface mount features prior to pick and place. They</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">are claiming that the boards are growing/shrinking some 15-20 mils.</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">We have done extensive measuring on unpopulated boards in-house</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">and cannot see more than 3-5 mils misregistration. The panel size</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">throughout the panel. Overall thickness .080. Is it possible that the mesh</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">screen that they are using can expand/contract over time? has anyone</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">heard of this experienced this situation before. Any information would be</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">greatly appreciated.</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Thanks</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Tony Steinke</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">AIT-Atlanta</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #fff8e0" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT></HTML>
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Date: Fri, 29 Mar 2002 09:59:27 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jindra, Larry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jindra, Larry" <[log in to unmask]>
Subject: Solder Ball Wrinkles
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
We have a lot of BGA packages from a custom package house with a "wrinkled" appearance to the ball surface, most pronounced on top of the ball, where they will interface with the PCB. These packages are prone to shorting.
Does anyone out there have an idea of what might cause that "wrinkled" appearance, and why it might make the package succeptible to shorting?
Larry Jindra
Mfg Engr Group Lead
TRW Radio Systems
[log in to unmask]
w) 858-592-3424
f) 858-592-3940
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Date: Fri, 29 Mar 2002 11:04:28 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: solder paste registration
X-To: "Edward S. Wheeler" <[log in to unmask]>
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This sounds almost like the mesh that holds the
stencil in the frame is becoming weak and stretched
allowing for extensive movement of the stencil during
the printing operation. IMHO.
Barry.
-----Original Message-----
From: Edward S. Wheeler [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 9:48 AM
To: [log in to unmask]
Subject: Re: [TN] solder paste registration
We have only seen stretch on our stencils cause a problem when they are old
and very used. At this point it is best to purchase a new stencil, as it
will pay for itself with reduced defects almost immediately. It may be worth
while to see how the board is fixtured, as it can sometimes shift during the
print cycle from time to time and cause problems.
Hope some of this is useful.
Ed
At 10:48 AM 3/29/2002 -0800, you wrote:
Ladies and Gentlemen,
We are having a major problem with an assembly house with registering
the solder paste to surface mount features prior to pick and place. They
are claiming that the boards are growing/shrinking some 15-20 mils.
We have done extensive measuring on unpopulated boards in-house
and cannot see more than 3-5 mils misregistration. The panel size
is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
throughout the panel. Overall thickness .080. Is it possible that the mesh
screen that they are using can expand/contract over time? has anyone
heard of this experienced this situation before. Any information would be
greatly appreciated.
Thanks
Tony Steinke
AIT-Atlanta
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<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff size=2>This
sounds almost like the mesh that holds the</FONT></SPAN></DIV>
<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff
size=2>stencil in the frame is becoming weak and stretched</FONT></SPAN></DIV>
<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff
size=2>allowing for extensive movement of the stencil during</FONT></SPAN></DIV>
<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff size=2>the
printing operation. IMHO.</FONT></SPAN></DIV>
<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=980580218-29032002><FONT face=Arial color=#0000ff
size=2>Barry.</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Edward S. Wheeler
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, March 29, 2002 9:48
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] solder paste
registration<BR><BR></FONT></DIV>We have only seen stretch on our stencils
cause a problem when they are old and very used. At this point it is best to
purchase a new stencil, as it will pay for itself with reduced defects almost
immediately. It may be worth while to see how the board is fixtured, as it can
sometimes shift during the print cycle from time to time and cause problems.
<BR><BR>Hope some of this is useful.<BR><BR>Ed<BR><BR><BR><BR><BR>At 10:48 AM
3/29/2002 -0800, you wrote:<BR>
<BLOCKQUOTE class=cite cite="" type="cite"><FONT face=arial size=2>Ladies
and Gentlemen,</FONT><BR> <BR><FONT face=arial size=2>We are having a
major problem with an assembly house with registering</FONT><BR><FONT
face=arial size=2>the solder paste to surface mount features prior to pick
and place. They</FONT><BR><FONT face=arial size=2>are claiming that the
boards are growing/shrinking some 15-20 mils.</FONT><BR><FONT face=arial
size=2>We have done extensive measuring on unpopulated boards
in-house</FONT><BR><FONT face=arial size=2>and cannot see more than 3-5 mils
misregistration. The panel size</FONT><BR><FONT face=arial size=2>is
approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15
BGA's</FONT><BR><FONT face=arial size=2>throughout the panel. Overall
thickness .080. Is it possible that the mesh</FONT><BR><FONT face=arial
size=2>screen that they are using can expand/contract over time? has
anyone</FONT><BR><FONT face=arial size=2>heard of this experienced this
situation before. Any information would be</FONT><BR><FONT face=arial
size=2>greatly appreciated.</FONT><BR> <BR><FONT face=arial
size=2>Thanks</FONT><BR><FONT face=arial size=2>Tony Steinke</FONT><BR><FONT
face=arial
size=2>AIT-Atlanta</FONT></BLOCKQUOTE><BR>---------------------------------------------------------------------------------
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Date: Fri, 29 Mar 2002 13:16:21 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: COD/BOD
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A general inquiry.
Who/how many among our PCB Bare Board Fabricators are concerned over BOD/COD
of their waste water?
Are you doing special treatment, or making special choices in
chemistry/process, to deal with that issue?
Rudy Sedlak
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Date: Fri, 29 Mar 2002 13:22:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Solder Ball Wrinkles
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Hi Larry!
The "wrinkled" appearance is not all that unusual, and according to this file
below, is not a defect unless it is extreme. Go to:
http://www.cooksonsemi.com/pdfs/BGASolderBumpQual.pdf
The fact that you are experiencing a lot of shorts, IMHO points somewhere
else than wrinkled surfaces on the spheres...I would think if anything,
wrinkled surfaces of the spheres would cause voiding problems...
My 2-cents..
-Steve Gregory-
> We have a lot of BGA packages from a custom package house with a "wrinkled"
> appearance to the ball surface, most pronounced on top of the ball, where
> they will interface with the PCB. These packages are prone to shorting.
>
> Does anyone out there have an idea of what might cause that "wrinkled"
> appearance, and why it might make the package succeptible to shorting?
>
>
> Larry Jindra
> Mfg Engr Group Lead
> TRW Radio Systems
> [log in to unmask]
> w) 858-592-3424
> f) 858-592-3940
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Larry!<BR>
<BR>
The "wrinkled" appearance is not all that unusual, and according to this file below, is not a defect unless it is extreme. Go to:<BR>
<BR>
http://www.cooksonsemi.com/pdfs/BGASolderBumpQual.pdf<BR>
<BR>
The fact that you are experiencing a lot of shorts, IMHO points somewhere else than wrinkled surfaces on the spheres...I would think if anything, wrinkled surfaces of the spheres would cause voiding problems...<BR>
<BR>
My 2-cents..<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">We have a lot of BGA packages from a custom package house with a "wrinkled" appearance to the ball surface, most pronounced on top of the ball, where they will interface with the PCB. These packages are prone to shorting.<BR>
<BR>
Does anyone out there have an idea of what might cause that "wrinkled" appearance, and why it might make the package succeptible to shorting?<BR>
<BR>
<BR>
Larry Jindra<BR>
Mfg Engr Group Lead<BR>
TRW Radio Systems<BR>
[log in to unmask]<BR>
w) 858-592-3424<BR>
f) 858-592-3940<BR>
</BLOCKQUOTE><BR>
<BR>
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Date: Fri, 29 Mar 2002 13:37:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: Solder Ball Wrinkles
X-To: "Jindra, Larry" <[log in to unmask]>
In-Reply-To: <[log in to unmask] >
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We have noticed that on BGA devices that undergo warp during the reflow
cycle (shadow moire results showed the parts would warp up at the ends,
then down, then up) can cause this if the joint is moving during the
transition back to solid. The joint looks similar to wrinkled tin foil.
When we have parts that don't warp with all of the same parameters, the
joint is smooth and shiny.
Our main failure with these warping parts has been a head in pillow open.
Ed
At 09:59 AM 3/29/2002 -0800, you wrote:
>We have a lot of BGA packages from a custom package house with a
>"wrinkled" appearance to the ball surface, most pronounced on top of the
>ball, where they will interface with the PCB. These packages are prone to
>shorting.
>
>Does anyone out there have an idea of what might cause that "wrinkled"
>appearance, and why it might make the package succeptible to shorting?
>
>
>Larry Jindra
>Mfg Engr Group Lead
>TRW Radio Systems
>[log in to unmask]
>w) 858-592-3424
>f) 858-592-3940
>
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Date: Fri, 29 Mar 2002 19:53:48 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: solder paste registration
X-To: tony steinke <[log in to unmask]>
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Perhaps the assembler is using only 2 fiducials on their printer ? Then =
the deviation can be partly due to the board, with the remainder =
resulting from the fact that a 2 fiducial cannot compensate for rotation =
in the machine.=20
Daan Terstegge
http://www.smtinfo.net
=20
----- Original Message -----=20
From: tony steinke=20
To: [log in to unmask]
Sent: Friday, March 29, 2002 9:15 PM
Subject: Re: [TN] solder paste registration
Hey Folks,
The solder paste is being applied with a stencil. Thanks for all the =
info.
Tony steinke
----- Original Message -----
From: Brian Ellis <[log in to unmask]>
To: TechNet E-Mail Forum. <[log in to unmask]>; tony steinke
<[log in to unmask]>
Sent: Friday, March 29, 2002 9:01 AM
Subject: Re: [TN] solder paste registration
> Tony
>
> You don't say what type of screen is being used. If it's a
> nylon/polyester one, then I'd say you're in deep trouble. If it's a
> stainless steel one, it can still stretch as the squeegee distorts =
it.
> You really should use a stencil.
>
> Brian
>
> > tony steinke wrote:
> >
> > Ladies and Gentlemen,
> >
> > We are having a major problem with an assembly house with =
registering
> > the solder paste to surface mount features prior to pick and =
place.
> > They
> > are claiming that the boards are growing/shrinking some 15-20 =
mils.
> > We have done extensive measuring on unpopulated boards in-house
> > and cannot see more than 3-5 mils misregistration. The panel size
> > is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 =
BGA's
> > throughout the panel. Overall thickness .080. Is it possible that =
the
> > mesh
> > screen that they are using can expand/contract over time? has =
anyone
> > heard of this experienced this situation before. Any information =
would
> > be
> > greatly appreciated.
> >
> > Thanks
> > Tony Steinke
> > AIT-Atlanta
=
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<DIV>Perhaps the assembler is using only 2 fiducials on their printer =
? =20
Then the deviation can be partly due to the board, with the remainder =
resulting=20
from the fact that a 2 fiducial cannot compensate for rotation in the=20
machine. </DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">tony=20
steinke</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, March 29, 2002 =
9:15=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] solder paste=20
registration</DIV>
<DIV><BR></DIV>Hey Folks,<BR>The solder paste is being applied with a =
stencil.=20
Thanks for all the info.<BR>Tony steinke<BR>----- Original Message=20
-----<BR>From: Brian Ellis <<A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR>=
To:=20
TechNet E-Mail Forum. <<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>>; tony =
steinke<BR><<A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>>=
<BR>Sent:=20
Friday, March 29, 2002 9:01 AM<BR>Subject: Re: [TN] solder paste=20
registration<BR><BR><BR>> Tony<BR>><BR>> You don't say what =
type of=20
screen is being used. If it's a<BR>> nylon/polyester one, then I'd =
say=20
you're in deep trouble. If it's a<BR>> stainless steel one, it can =
still=20
stretch as the squeegee distorts it.<BR>> You really should use a=20
stencil.<BR>><BR>> Brian<BR>><BR>> > tony steinke=20
wrote:<BR>> ><BR>> > Ladies and Gentlemen,<BR>> =
><BR>>=20
> We are having a major problem with an assembly house with=20
registering<BR>> > the solder paste to surface mount features =
prior to=20
pick and place.<BR>> > They<BR>> > are claiming that the =
boards=20
are growing/shrinking some 15-20 mils.<BR>> > We have done =
extensive=20
measuring on unpopulated boards in-house<BR>> > and cannot see =
more than=20
3-5 mils misregistration. The panel size<BR>> > is approximately =
14.00 x=20
16.00 inches, 20-24 mil pitch, and 15 BGA's<BR>> > throughout =
the panel.=20
Overall thickness .080. Is it possible that the<BR>> > =
mesh<BR>> >=20
screen that they are using can expand/contract over time? has =
anyone<BR>>=20
> heard of this experienced this situation before. Any information=20
would<BR>> > be<BR>> > greatly appreciated.<BR>> =
><BR>>=20
> Thanks<BR>> > Tony Steinke<BR>> >=20
=
AIT-Atlanta<BR><BR>------------------------------------------------------=
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Date: Fri, 29 Mar 2002 13:22:56 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: solder paste registration
X-To: [log in to unmask]
Ah ha ha ha,
Steve,
Agree it's most likely to do with the stencil and its surrounding retainer
or age of both. However, I've seen many times it WAS the board.
Earl Moon
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Date: Fri, 29 Mar 2002 13:41:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: solder paste registration
X-To: [log in to unmask]
Tony,
This is a subject always needing attention, in my not so humble opinion but
objective study and observation. As Daan said, fids can be off. This also
means other pads can be off on boards especially multiple ups. The Gerber is
one thing to a board going through all "normal" process and quite another to
stencils with very high dimensional stability.
Anyway, matching the stencil to the board pads/fids is easily done on the
printer. Also, printing a miylar over the panels before committing to
production works as well - ESD safe material of course.
Love those DEKS as you can press F2, I think, and have the rising table rise
so solder paste can be applied. At this time you can observe stencil to pad
registration so you only see metal instead of green as the board.
Hell, you folks all know this,
MoonMan
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Date: Fri, 29 Mar 2002 13:55:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jorge Santana <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Santana <[log in to unmask]>
Subject: Re: solder paste registration
X-To: tony steinke <[log in to unmask]>
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Tony
This is easy to see in the screen printer machine, just load the board and
do the align without printing ( most of screen printers has this
capabilities ) , go into the machine and see if all stencil apertures are
aligned with the board pads, from there you have the final conclusion ...
Jorge Santana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of tony steinke
Sent: Friday, March 29, 2002 12:49 PM
To: [log in to unmask]
Subject: [TN] solder paste registration
Ladies and Gentlemen,
We are having a major problem with an assembly house with registering
the solder paste to surface mount features prior to pick and place. They
are claiming that the boards are growing/shrinking some 15-20 mils.
We have done extensive measuring on unpopulated boards in-house
and cannot see more than 3-5 mils misregistration. The panel size
is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's
throughout the panel. Overall thickness .080. Is it possible that the mesh
screen that they are using can expand/contract over time? has anyone
heard of this experienced this situation before. Any information would be
greatly appreciated.
Thanks
Tony Steinke
AIT-Atlanta
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<BODY bgColor=3D#fff8e0>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2> Tony</FONT></SPAN></DIV>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2> =20
This is easy to see in the screen printer machine, just load the board=20
and do the align without printing ( most of screen printers has =
this=20
capabilities ) , go into the machine and see if all stencil apertures =
are=20
aligned with the board pads, from there you have the final conclusion=20
...</FONT></SPAN></DIV>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2>Jorge=20
Santana</FONT></SPAN></DIV>
<DIV><SPAN class=3D610225119-29032002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>tony =
steinke<BR><B>Sent:</B>=20
Friday, March 29, 2002 12:49 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] solder paste=20
registration<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Ladies and Gentlemen,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>We are having a major problem with an =
assembly=20
house with registering</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>the solder paste to surface mount =
features prior=20
to pick and place. They</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>are claiming that the boards are=20
growing/shrinking some 15-20 mils.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>We have done extensive measuring on =
unpopulated=20
boards in-house</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>and cannot see more than 3-5 mils=20
misregistration. The panel size</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>is approximately 14.00 x 16.00 =
inches, 20-24 mil=20
pitch, and 15 BGA's</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>throughout the panel. Overall =
thickness .080. Is=20
it possible that the mesh</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>screen that they are using can =
expand/contract=20
over time? has anyone</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>heard of this experienced this =
situation before.=20
Any information would be</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>greatly appreciated.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Tony Steinke</FONT></DIV>
<DIV><FONT face=3DArial =
size=3D2>AIT-Atlanta</FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 29 Mar 2002 15:31:09 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Underwater application
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I would recommend an acrylic as my first choice, probably coated twice.
Jon Moore
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Date: Fri, 29 Mar 2002 15:31:55 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Underwater application
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In a message dated 3/29/2002 12:35:04 PM US Eastern Standard Time,
[log in to unmask] writes:
<< i know, i know...here i go again with parylene. but it will work. >>
I agree Phil, but he did say cost was a factor.
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Date: Fri, 29 Mar 2002 15:49:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Afri Singh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Afri Singh <[log in to unmask]>
Subject: Re: Tiny black spots on copper foil surface
MIME-Version: 1.0
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how about some dust or carbon from the scrubber -- drier section
Do you have filters on your drier ?
or pieces of rubber from the rollers breaking off
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Friday, March 22, 2002 9:54 AM
To: [log in to unmask]
Subject: Re: [TN] Tiny black spots on copper foil surface
Or somebody sneezed.
You might try to recreate the spots by flicking some water on the panel.
It could also be algae growing in the tanks.
When I hear black spots on copper I think tarnish.
Hans
-----Original Message-----
From: JaMi Smith [mailto:[log in to unmask]]
Sent: Thursday, March 21, 2002 2:57 PM
To: [log in to unmask]
Subject: Re: [TN] Tiny black spots on copper foil surface
Shirley,
Sounds like it might be very very small pin holes in your resist that is
letting in a microscopic amount of etchant.
JaMi Smith
-----Original Message-----
From: Shirley Xiao [mailto:[log in to unmask]]
Sent: Wednesday, March 20, 2002 11:14 PM
To: [log in to unmask]
Subject: [TN] Tiny black spots on copper foil surface
Dear All:
We encountered a problem after develop, etch & strip.
Lots of tiny black spots were found on copper surface.
We are sure that these tiny black spots are not
oxidization.They can not be removed by acetone but is
removable by micro etch.Before get result by EDX
element analysis, I wish anyone have similar
experience can share some information with me.
__________________________________________________
Do You Yahoo!?
Yahoo! Movies - coverage of the 74th Academy Awards(r)
http://movies.yahoo.com/
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Date: Fri, 29 Mar 2002 16:13:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solder Ball Wrinkles
X-To: "Jindra, Larry" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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As I read your message, we are not talking about BGAs that were mounted on
boards. These are the packages before they were installed? It this true?
Yes, I would be worried. Sound like something was wrong in the solder ball
attach process. I am not very familiar with commercial methods. Reballing
processes that produce wrinkled balls can be caused by excessive heat and
excessive convection.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jindra, Larry
> Sent: Friday, March 29, 2002 12:59 PM
> To: [log in to unmask]
> Subject: [TN] Solder Ball Wrinkles
>
>
> We have a lot of BGA packages from a custom package house with a
> "wrinkled" appearance to the ball surface, most pronounced on top
> of the ball, where they will interface with the PCB. These
> packages are prone to shorting.
>
> Does anyone out there have an idea of what might cause that
> "wrinkled" appearance, and why it might make the package
> succeptible to shorting?
>
>
> Larry Jindra
> Mfg Engr Group Lead
> TRW Radio Systems
> [log in to unmask]
> w) 858-592-3424
> f) 858-592-3940
>
> ------------------------------------------------------------------
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Date: Fri, 29 Mar 2002 16:35:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chris Almeras <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chris Almeras <[log in to unmask]>
Subject: Re: Underwater application
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Is there any other environmental issues this assembly faces besides the =
moisture?(I.E. temperature,vibration, etc....) If there are no other =
concerns, I would consider an acrylic, possibly Humiseal 1B73 or 1B31. =
We do have an assembly that is encapsulated with Shin-Etsu KE109E. The =
customer puts it through a test where it has to work while submerged for =
a certain amount of time during heavy vibration. It is not a real =
expensive option, but it is not as cheap as the acrylic option.
Chris Almeras
-----Original Message-----
From: Jorge Santana [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 12:06 PM
To: [log in to unmask]
Subject: [TN] Underwater application
Hi
We need found out a way to keep the board working in a underwater
environment, there is possibilities of occasional flood inside the box
enclosure and the board has to survive, the water came from rain.
Folks from automotive world " under hood applications" have this
experience since cars are subject to flood also.
What kind of material is used ? What recommended thickness ?
We are thinking about RTV Elastomeric Conformal Coating.
It is not necessary to say that the solution should be not expensive =
and
effective.
Thanks
Jorge Santana
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Date: Fri, 29 Mar 2002 14:19:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jindra, Larry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jindra, Larry" <[log in to unmask]>
Subject: Re: Solder Ball Wrinkles
X-To: [log in to unmask]
MIME-Version: 1.0
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True, I was talking about appearance of the BGAs prior to mounting.
We just did a blind installation test with the same packages from an earlier lot that did not exhibit "wrinkles." The result show a significantly greater voiding joints from the "wrinkled" BGAs, given the same paste, place and reflow processing parameters. Given that the same things that cause voiding can cause shorting, we have a process problem that appears to be caused by a supplier process.
The packaging vendor claims the bad balls saw a normal process. I need to tell them we suspect they are .....
Larry Jindra
Mfg Engr Group Lead
TRW Radio Systems
[log in to unmask]
w) 858-592-3424
f) 858-592-3940
-----Original Message-----
From: Guy Ramsey [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 1:13 PM
To: TechNet E-Mail Forum.; Jindra, Larry
Subject: RE: [TN] Solder Ball Wrinkles
As I read your message, we are not talking about BGAs that were mounted on
boards. These are the packages before they were installed? It this true?
Yes, I would be worried. Sound like something was wrong in the solder ball
attach process. I am not very familiar with commercial methods. Reballing
processes that produce wrinkled balls can be caused by excessive heat and
excessive convection.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jindra, Larry
> Sent: Friday, March 29, 2002 12:59 PM
> To: [log in to unmask]
> Subject: [TN] Solder Ball Wrinkles
>
>
> We have a lot of BGA packages from a custom package house with a
> "wrinkled" appearance to the ball surface, most pronounced on top
> of the ball, where they will interface with the PCB. These
> packages are prone to shorting.
>
> Does anyone out there have an idea of what might cause that
> "wrinkled" appearance, and why it might make the package
> succeptible to shorting?
>
>
> Larry Jindra
> Mfg Engr Group Lead
> TRW Radio Systems
> [log in to unmask]
> w) 858-592-3424
> f) 858-592-3940
>
> ------------------------------------------------------------------
> ---------------
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>
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Date: Fri, 29 Mar 2002 17:11:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: solder paste registration
X-To: [log in to unmask]
Right on Right on and as a plus, print a mylar on top of the pads and
determine if acceptable. What is it? - 25% misaligned for fine pitch and 35
for all else? Who has this answer? IPC? But it works well for most with a
little fudge factor but not without verification before commiting to
production of any amount.
MoonMan
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Date: Fri, 29 Mar 2002 15:26:11 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
JaMi Smith <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: JaMi Smith <[log in to unmask]>
Subject: Re: Blistering in PCBs - A possible answer
X-cc: [log in to unmask]
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Vinit and the group -
=20
I have seen this before -
=20
Apologies up front for the long post -
=20
I am assuming that we are talking about the last four photos at the
webpage stevezeva.homestead.com, which are labeled Bad Board, Bad Board
2, Bad Board 3, and Bad Board 4.
=20
If so then here is my take as relates to the "raised vias" shown in Bad
Board 2 and Bad Board 4, and this may be the key to understanding the
related problems.
=20
About 12 to 13 years ago, I came on board at Datatape., in Pasadena
California, as a Sr. Designer. Although my work background had been
primarily as a PCB Designer working my way up to become a Sr. Design
Engineer for TRW, at Datatape, I was hired into the Electrical
Engineering Department as a troubleshooter primarily because while not
degreed, I have a broad background in Electronics, and hence because of
by cross disciplines I could communicate not only to Engineering, but
also to folks in Design and Drafting , as well as those in
Manufacturing.
=20
My first crisis was an overdue Military Contract VME Style Backplane for
16 Cards with 3 96 Pin Connectors each, that was 11 layers at .238"
thick due to impedance requirements for ECL Logic.
=20
Yes, you read correctly, almost =BC inch.
=20
Well the first batch from the first PCB supplier in Monrovia California,
ended up with massive shorts of almost all of the holes, to almost all
of the supply lines and ground. To make a long story short, this was due
to the fab house using the same feeds and speeds and drill changes on
that board as they would have on a 1/8 inch thick board, which, needless
to say dulled the drills immediately and ended up snagging most if not
all of the internal pads and ripping them out, which in turn caused all
of the material in each hole to be ripped out also, leaving all (or
most) of the holes with a clean entry and exit (due to aluminum backing
sheets), but a large caveran inside each hole which exposed all of the
edges of the clearance holes in the 5 power and ground planes, and
plated everything into one massive short.
=20
Well I finally convinced the fab shop as to exactly what they had done
wrong and then had to convince them that they really could make the
boards properly after all, and I had them contact their Excellon Rep
(for help with drilling feeds and speeds and drill life for a =BC inch
board), and made some minor adjustments to hole sizes and allowed them
to remove unused pads from the internal layers. Then I just sat back and
waited for the next turn of the board. I new that we had failed when the
shop foreman failed to call me back after an ohmmeter check after final
etch, and when I called them I was told he had gone down the street
cursing and screaming to a local bar. This time the holes were
beautiful, but the layer to layer registration was off since they didn't
use pins and just threw the whole large stack up into the laminating
press with only a few "hot glue" spot bonds to hold everything together.
That's like an In 'n Out Double Double Hambuger with extra mayo, extra
cheese, extra tomato, and extra onions, when you try to mash it down to
get in into the wrapper, everything shifts!
=20
This left me to find someone who could make the boards properly and
quickly. I went to 2 different shops with the same order, one shop in
Huntington Beach California for 3 boards 1 week @ $13K each, and the
other shop in Florida for 3 boards 1 week @ $1K each. Major difference
in price, but Florida was a backup anyway, which I had located after we
contracted with the other guy, and we needed the boards done right three
weeks ago by then, so that was a small price for insurance.
=20
The supplier in Huntington Beach, who used an autoclave, delivered
perfect boards on time and went out and bought a new car off of that job
(or so he told me). However the supplier in Florida delivered 3 boards
that had all of the holes (small holes) and vias in the board raised and
looking exactly like the photos on the website, labeled "raised vias".
=20
This is what I found:
=20
The first thing that I noticed was that a surprising number of the holes
had some peculiar "black flakes" in them which you could see when
looking into the hole with a lupe. While I did not have any fancy "bore
scope" or other tool other than a lupe, to examine the hole with, I came
to the conclusion that these "flakes" were actually protruding from (or
stuck into) the wall of the PTH. It almost looked like there was a 2 mil
thick layer of graphite or carbon that was in the middle of the board
that hat chipped in some holes and left a flake protruding from the PTH
wall.
=20
My initial conclusion was that the boards were bad and I wanted to
reject them, but I had to either find a reason to reject them or eat the
$3K, which by then was a small piece of change anyway.
=20
I used an ohmmeter to check a few of the worst looking holes, but they
showed continuity. Nonetheless, I knew they were bad. I called the
Company who had done the Mil Continuity Certification, which was
different than the supplier, and he assured me that the boards were
checked and all passed, but that no, he did not remember any "raised
vias" as I had described them to him.
=20
That description, by the way was essentially this: When you held the
board up to a light source so that you could see the light reflected off
of the surface of the board, you could see that board surface
surrounding virtually each and every via was raised above the normal
flat surface of the board, and that the groups of 96 holes at each
connector location were also raised. It looked like a little island
sticking up out of a calm sea, and while I never measured the height of
the rise, it was visually very noticeable, similar to those shown in
photo Bare Board 2.
=20
Well, I didn't know what to do to prove that the boards were bad, since
I didn't want to pay for them I couldn't very well section one of the
boards and then try to send it back, and the test coupons had not been
properly masked so the top and bottom layers as well as all plating from
the holes had been etched away, and then they were separated from the
boards and so they did not exhibit any of the problems.
=20
I finally got some aluminum foil, Reynolds Wrap if I remember, and made
a large pad that I could hook to one of the test leads of the ohmmeter,
and use as a massive "contact" to contact all of the bottom pads on the
board in an area that I wanted to check. I then set about checking the
continuity of each and every hole of each connector (over 4600 holes),
as well as all of the vias (several hundred additional holes as vias). I
checked for continuity from the pad (annular ring) on the top side of
the hole to the pad on the bottom side of the hole, of each and every
hole. I wasn't doing a net list check, all I was doing was checking each
hole for top to bottom continuity.
=20
I was about to give up when I found my first hole with an "open", and
when I checked the hole with the lupe, I expected to see flakes, but saw
instead a beautiful hole, and couldn't even tell visually that there was
a break in the wall since it looked so smooth.
=20
I ultimately found that that board had a total of 8 holes that exhibited
an open from top to bottom. 4 of the holes were unused electrically
speaking, but the remaining 4 were active holes that were supposed to go
to other places, of which all were connected to the proper place by at
least one of the pads (either top or bottom (but not both)), but at
least one of the holes did occur in the middle of a net connection which
did in fact cause the net to be broken in the middle. This was enough to
reject the board for failure to exhibit the same continuity as the other
2 boards that it was checked against for the Mil Certification.
=20
I started asking questions of the Florida supplier and I finally came up
with what I believed to be the answer, and when I explained it to the
guys in Florida, they concurred with my evaluation, and although they
said they themselves would section the boards, they never got back to me
with any contradictory findings.
=20
The supplier in Florida took every precaution and was very careful every
step of the way, and in fact had produced perfect boards (with the
exception of the Test Coupons), right up to the very last step, which
was the only uncontrolled step in their entire process.
=20
After they had gone down the street to get the boards Mil Certified for
Continuity at another vendor, they gave them to their "touch up girl" to
do a very small amount of touch up of scratches and voids in the solder
mask before shipping. When she was finished with her touch up, she put
the boards into her uncontrolled oven which she only used to cure the
"touch up jobs".
=20
Well, my take on it was that the oven was hotter than it should have
been, and that the boards expanded very rapidly, and also expanded by a
large amount, such that every single small hole in the board had its
plated thru wall stretched so far that many of the walls actually broke
apart, some with a clean break, and some with a jagged break, and some,
probably most, just stretched.
=20
Next in the process, the boards were taken out of the oven and simply
allowed to cool by themselves in a rack. This is when the stretched and
broken hole and via walls now stood up in protest, and simply would not
return to their original dimensions. I believe that a major part of this
was due to the fact that when the holes with jagged breaks in their
walls tried to contract, the 2 halves of the barrel just mashed into
each other, which, among other things produced the little "black flakes"
that I saw in many of the holes, which were actually broken pieces of
the plated wall of the hole. The reason that most of them looked "black"
is that I was seeing the outer side of the hole wall.=20
=20
As it turned out, the 8 discontinuities that I found in the one board
that I tested, all exhibited exceptionally clean walls in the hole, and
I concluded that these 8 holes broke so cleanly that when the board
material in adjacent holes around them failed to return to the original
dimension, these 8 hole walls simply did not re-engage their
counterparts, and hence showed up as an open to the ohmmeter.
=20
While I am sure that there are some additional factors which lead to
this catastrophic damage to the board besides the massive thermal shock
and massive expansion of the board, I could only put my finger on one in
particular that I believe contributed to the problem. I believe that a
primary contributor was the "reduced reproducibility" ratio of the .238"
board thickness to the .039" dia hole used for the connectors, which I
am sure produced a very thin wall (barrel) in the middle of the hole,
and while I know that 039" is not a very small hole, it is comparable to
a .010" hole in a .060 board of today.
=20
I believe that my experience as described above will account for the
"raised vias" in the pictures on the website, which I believe were
caused by thermal expansion of the PC Board at some point in the final
manufacturing process, where the holes and vias were "stretched" so far
out of shape (dimensionally) that they refused to return to their
original "pre-expansion dimension".
=20
I would stress that I do not believe that the hole walls would have to
be stretched to the point of breakage as did happen in the case I
described above, so there may be no evidence of the "flakes" that I saw
in the holes of the above example. I believe that the holes could
stretch without breaking, especially if there was thicker plating than
experienced in my example above, and still refuse to return to their
original dimension, and therefore leave an otherwise perfect looking
wall behind with no signs of the thermal expansion other than being
raised.
=20
The one thing that I saw as a big problem in the whole episode as
described above that has scared the heck out of me ever since, and which
is why I will not allow a test coupon to be separated prior to delivery
of the board to me, is the fact that most of this type of damage occurs
to the board after all of its primary inspection, you know, the
continuity check, the QA inspection, and the visual inspection, since
touch up is usually the last thing that happens before it gets sent out
the door, and usually it is not even looked at by the person who did the
touch up once the board dried, which explains how an otherwise good
supplier can ship such a #4(&!\%* product. (pardon my ascii).
=20
I am very confident that this explains the "raised vias", and I am sure
that when this scenario is taken into account, it will go a long way
towards explaining the remaining problems with the boards.
=20
JaMi Smith
Optical Crossing Inc.
=20
=20
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]=20
Sent: Friday, March 29, 2002 8:19 AM
To: [log in to unmask]
Subject: Re: [TN] Blistering in PCBs
=20
Don and Everybody!
The pic's are now up! Go to: http://www.stevezeva.homestead.com
I gotta say, those are some UGLY boards!
-Steve Gregory-
Hey Earl
Where can I see these photos? Don't see them on Steve's site.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, March 29, 2002 6:49 AM
To: [log in to unmask]
Subject: Re: [TN] Blistering in PCBs
Vinit,
Ok, here we go. Never seen nothin' like these before. Oh well, maybe
once
when I was a "young gun" process engineer at Xerox. That's another story
I'll not bore anyone with now.
Concerning the pics, it is obvious there is delam everywhere but maybe
the
edges. Vinitdelam3's discoloration also is delamination, not solder mask
related.
Someone else take shots at this and Vinit's supplier. This shop
shoundn't
exist unless they just lost it all on his boards ONE PING ONLY PLEASE.
A pleasure to serve Vinit. Don't often get to see how bad something can
be
besides a train wreck.
MoonMan
=20
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Date: Fri, 29 Mar 2002 17:36:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Underwater application
X-To: Chris Almeras <[log in to unmask]>
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Cris,
NO to 1B31!! The Tg is about 15 degrees C and it is easily softened by hydrocarbons.
IB73 is some what better with a Tg around 43 degrees C but it will not with stand exposure to hydrocarbons.
The unit will be exposed "external" environmental conditions besides "dirty" water. The build up of these
contaminants will pose serious issues when combined with moisture.
Either you use Parylene or "seal" the product. Anything else will result in shortened product life.
The question is how long is the warranty period for this product???
David A. Douthit
Manager
LoCan LLC
Chris Almeras wrote:
> Is there any other environmental issues this assembly faces besides the moisture?(I.E. temperature,vibration, etc....) If there are no other concerns, I would consider an acrylic, possibly Humiseal 1B73 or 1B31. We do have an assembly that is encapsulated with Shin-Etsu KE109E. The customer puts it through a test where it has to work while submerged for a certain amount of time during heavy vibration. It is not a real expensive option, but it is not as cheap as the acrylic option.
>
> Chris Almeras
>
> -----Original Message-----
> From: Jorge Santana [mailto:[log in to unmask]]
> Sent: Friday, March 29, 2002 12:06 PM
> To: [log in to unmask]
> Subject: [TN] Underwater application
>
> Hi
>
> We need found out a way to keep the board working in a underwater
> environment, there is possibilities of occasional flood inside the box
> enclosure and the board has to survive, the water came from rain.
> Folks from automotive world " under hood applications" have this
> experience since cars are subject to flood also.
>
> What kind of material is used ? What recommended thickness ?
>
> We are thinking about RTV Elastomeric Conformal Coating.
> It is not necessary to say that the solution should be not expensive and
> effective.
>
> Thanks
> Jorge Santana
>
> ---------------------------------------------------------------------------------
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>
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Date: Fri, 29 Mar 2002 17:38:45 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Underwater application
X-To: [log in to unmask]
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Jon,
Don't fall into the 'trying to save money no matter how much it costs' trap.
David a. Douthit
Manager
LoCan LLC
[log in to unmask] wrote:
> In a message dated 3/29/2002 12:35:04 PM US Eastern Standard Time,
> [log in to unmask] writes:
>
> << i know, i know...here i go again with parylene. but it will work. >>
>
> I agree Phil, but he did say cost was a factor.
>
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Date: Sat, 30 Mar 2002 00:38:16 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Underwater application
X-To: Jorge Santana <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Jorge
To my knowledge there is nothing that will do this job long-term.
You can try Paralene - Silicone - Acrylics - Urethanes etc., but underwater?
Not in my experience.
Occasional flood? What about the connector and other uncoated items? And
what quality the rain water - acid rain?
Better to have a drain hole in the box to let it out, then you can probably
successfully use any of the above as you prefer - but keeping in mind the
pro's and con's of each.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jorge Santana
> Sent: 29 March 2002 17:06
> To: [log in to unmask]
> Subject: [TN] Underwater application
>
>
> Hi
>
> We need found out a way to keep the board working in a underwater
> environment, there is possibilities of occasional flood inside the box
> enclosure and the board has to survive, the water came from rain.
> Folks from automotive world " under hood applications" have this
> experience since cars are subject to flood also.
>
> What kind of material is used ? What recommended thickness ?
>
> We are thinking about RTV Elastomeric Conformal Coating.
> It is not necessary to say that the solution should be not
> expensive and
> effective.
>
> Thanks
> Jorge Santana
>
> ------------------------------------------------------------------
> ---------------
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>
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Date: Sat, 30 Mar 2002 10:07:31 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
don_well <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: don_well <[log in to unmask]>
Subject: Re: Measuring "No Clean" process quality
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Date: Sat, 30 Mar 2002 10:23:20 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
don_well <[log in to unmask]>
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PC9CT0RZPjwvSFRNTD4NCg==
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Date: Sat, 30 Mar 2002 11:00:00 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: solder paste registration
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To all,
Thanks everyone for the excellent responses pertaining to the solder =
paste
registration. The company had the stencil sent out for evaluation, and =
it
was discovered that it was in fact out by as much as .010 in the X =
axis(long direction). We have approximately 20-25 "local" fiducials on =
the board itself.
Anyway, I am off to Minot, ND Monday morning for a follow up. The high =
temp
there for Monday is a blistering 21 degrees. And to think I just put =
planted tomatoes
in Atlanta. Also I will be sure to show the engineers the Technet =
website.
Thanks again,
Tony Steinke
----- Original Message -----=20
From: D.Terstegge=20
To: TechNet E-Mail Forum. ; tony steinke=20
Sent: Friday, March 29, 2002 10:53 AM
Subject: Re: Re: [TN] solder paste registration
Perhaps the assembler is using only 2 fiducials on their printer ? =
Then the deviation can be partly due to the board, with the remainder =
resulting from the fact that a 2 fiducial cannot compensate for rotation =
in the machine.=20
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: tony steinke=20
To: [log in to unmask]
Sent: Friday, March 29, 2002 9:15 PM
Subject: Re: [TN] solder paste registration
Hey Folks,
The solder paste is being applied with a stencil. Thanks for all the =
info.
Tony steinke
----- Original Message -----
From: Brian Ellis <[log in to unmask]>
To: TechNet E-Mail Forum. <[log in to unmask]>; tony steinke
<[log in to unmask]>
Sent: Friday, March 29, 2002 9:01 AM
Subject: Re: [TN] solder paste registration
> Tony
>
> You don't say what type of screen is being used. If it's a
> nylon/polyester one, then I'd say you're in deep trouble. If it's =
a
> stainless steel one, it can still stretch as the squeegee distorts =
it.
> You really should use a stencil.
>
> Brian
>
> > tony steinke wrote:
> >
> > Ladies and Gentlemen,
> >
> > We are having a major problem with an assembly house with =
registering
> > the solder paste to surface mount features prior to pick and =
place.
> > They
> > are claiming that the boards are growing/shrinking some 15-20 =
mils.
> > We have done extensive measuring on unpopulated boards in-house
> > and cannot see more than 3-5 mils misregistration. The panel =
size
> > is approximately 14.00 x 16.00 inches, 20-24 mil pitch, and 15 =
BGA's
> > throughout the panel. Overall thickness .080. Is it possible =
that the
> > mesh
> > screen that they are using can expand/contract over time? has =
anyone
> > heard of this experienced this situation before. Any information =
would
> > be
> > greatly appreciated.
> >
> > Thanks
> > Tony Steinke
> > AIT-Atlanta
=
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<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>To all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks everyone for the excellent =
responses=20
pertaining to the solder paste</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>registration. The company had the =
stencil sent out=20
for evaluation, and it</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>was discovered that it was in fact out =
by as much=20
as .010 in the X axis(long direction). We have approximately 20-25 =
"local"=20
fiducials on the board itself.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Anyway, I am off to Minot, ND Monday =
morning for a=20
follow up. The high temp</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>there for Monday is a blistering 21 =
degrees. And to=20
think I just put planted tomatoes</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>in Atlanta. Also I will be sure to show =
the=20
engineers the Technet website.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Thanks again,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Tony Steinke</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">D.Terstegge</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">TechNet E-Mail Forum.</A> ; <A=20
[log in to unmask] =
href=3D"mailto:[log in to unmask]">tony=20
steinke</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, March 29, 2002 =
10:53=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: Re: [TN] solder =
paste=20
registration</DIV>
<DIV><BR></DIV>
<DIV>Perhaps the assembler is using only 2 fiducials on their printer =
? =20
Then the deviation can be partly due to the board, with the remainder=20
resulting from the fact that a 2 fiducial cannot compensate for =
rotation in=20
the machine. </DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A =
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">tony steinke</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, March 29, 2002 =
9:15=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] solder =
paste=20
registration</DIV>
<DIV><BR></DIV>Hey Folks,<BR>The solder paste is being applied with =
a=20
stencil. Thanks for all the info.<BR>Tony steinke<BR>----- Original =
Message=20
-----<BR>From: Brian Ellis <<A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR>=
To:=20
TechNet E-Mail Forum. <<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>>; tony=20
steinke<BR><<A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>>=
<BR>Sent:=20
Friday, March 29, 2002 9:01 AM<BR>Subject: Re: [TN] solder paste=20
registration<BR><BR><BR>> Tony<BR>><BR>> You don't say what =
type of=20
screen is being used. If it's a<BR>> nylon/polyester one, then =
I'd say=20
you're in deep trouble. If it's a<BR>> stainless steel one, it =
can still=20
stretch as the squeegee distorts it.<BR>> You really should use a =
stencil.<BR>><BR>> Brian<BR>><BR>> > tony steinke=20
wrote:<BR>> ><BR>> > Ladies and Gentlemen,<BR>> =
><BR>>=20
> We are having a major problem with an assembly house with=20
registering<BR>> > the solder paste to surface mount features =
prior to=20
pick and place.<BR>> > They<BR>> > are claiming that the =
boards=20
are growing/shrinking some 15-20 mils.<BR>> > We have done =
extensive=20
measuring on unpopulated boards in-house<BR>> > and cannot see =
more=20
than 3-5 mils misregistration. The panel size<BR>> > is =
approximately=20
14.00 x 16.00 inches, 20-24 mil pitch, and 15 BGA's<BR>> > =
throughout=20
the panel. Overall thickness .080. Is it possible that the<BR>> =
>=20
mesh<BR>> > screen that they are using can expand/contract =
over time?=20
has anyone<BR>> > heard of this experienced this situation =
before. Any=20
information would<BR>> > be<BR>> > greatly =
appreciated.<BR>>=20
><BR>> > Thanks<BR>> > Tony Steinke<BR>> >=20
=
AIT-Atlanta<BR><BR>------------------------------------------------------=
---------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
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Date: Sat, 30 Mar 2002 11:22:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Flex circuit design guidelines
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Hi Jim,
Actually, IPC-2223 does not have the design guidelines for a flex circuit for
continued flexing; for that you need to go to IPC-D-330, Section 6.2.1.2
"Flexibility Considerations in the Design of Flexible Printed Wiring." Also,
IPC-TP-652 and IPC-TR-484 would be good references.
Factors that need to be considered are bend radius, distance from neutral
plane, ductility, tensile strength, modulus of elasticity.
Werner Engelmaier
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Date: Sat, 30 Mar 2002 17:51:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bogert <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: White residue on LPI Solder Mask coated (and incompletely cured)
PWAs, Is it a technical concern?
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3/30/002
Folks, we have an OEM who purchased FR-4 printed wiring boards from a =
MIL-P-55110 qualified board manufacturer. The OEM wave soldered the =
PWAs using HF1189A water washable, organic flux and cleaned the =
assemblies using DI water in an in-line cleaning process. Subsequent =
Omegameter 600 ionic cleanliness testing passed. However, almost all of =
the solder side of the PWAs exhibited white residue. Basically it looks =
like a water mark. While you can remove the residue using abrasion, such =
as by a pencil erasure, it comes back, even after several subsequent =
baking operatioins and additional in-line cleaning. The OEM sent out =
samples for outside chemical evaluation and found minute traces of =
carbon. The OEM traced the problem to incomplete curing of the LPI =
solder mask. The white residue only appears on the solder side of the =
PWA. There is no evidence of the residue on the component side of the =
assembly.
The OEM proposes that a sample assembly be sent out for SIR testing, and =
that if the test passes, they will request us to accept the condition as =
is. My concern is that over time in a humid environment, we may =
experience leakage current paths that cound cause operasting failures. =
The OEM has 20 PWAs that are part of the lot. However, only 6 =
experience this condition. It appears that I should reject all PWAs =
that show evidence of the white residue. I am concerned with the =
presence of carbon, even in trace amounts. The OEM noted that almost =
everything will show traces of carbon, so not to worry.
Bottom line is, is there any technical concern if the white residue is =
present? Any input on this topic wo\uld be appreciated.=20
------=_NextPart_000_0165_01C1D813.809967C0
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charset="iso-8859-1"
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>3/30/002</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Folks, we have an OEM who purchased =
FR-4 printed=20
wiring boards from a MIL-P-55110 qualified board manufacturer. The =
OEM=20
wave soldered the PWAs using HF1189A water washable, organic flux =
and=20
cleaned the assemblies using DI water in an in-line cleaning =
process. =20
Subsequent Omegameter 600 ionic cleanliness testing passed. =
However,=20
almost all of the solder side of the PWAs exhibited white residue. =
Basically it looks like a water mark. While you can remove the =
residue=20
using abrasion, such as by a pencil erasure, it comes back, even =
after=20
several subsequent baking operatioins and additional in-line=20
cleaning. The OEM sent out samples for outside chemical =
evaluation=20
and found minute traces of carbon. The OEM traced the =
problem to=20
incomplete curing of the LPI solder mask. The white residue only =
appears=20
on the solder side of the PWA. There is no evidence of the residue =
on the=20
component side of the assembly.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>The OEM proposes that a sample assembly =
be sent out=20
for SIR testing, and that if the test passes, they will request us to =
accept the=20
condition as is. My concern is that over time in a humid =
environment,=20
we may experience leakage current paths that cound cause operasting =
failures. The OEM has 20 PWAs that are part of the lot. =
However,=20
only 6 experience this condition. It appears that I should =
reject all=20
PWAs that show evidence of the white residue. I am concerned with =
the=20
presence of carbon, even in trace amounts. The OEM noted that =
almost=20
everything will show traces of carbon, so not to worry.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Bottom line is, is there any technical =
concern if=20
the white residue is present? Any input on this topic wo\uld be=20
appreciated.</FONT> </DIV></BODY></HTML>
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Date: Sat, 30 Mar 2002 17:01:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: White residue on LPI Solder Mask coated (and
incompletelycured)PWAs, Is it a technical concern?
X-To: Bogert <[log in to unmask]>
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--------------DFE1D64DE18DFB0B0EA98312
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Bogart (luv the name!),
How long is the warranty period?
What sort of liability issues are possible?
If you are in "harsh" environments are you conformal coating the boards?
Won't the OEM pay for operational/functional testing in simulated
environments?
There is always a possibility of "leakage" currents and or
electrochemical migration.
Only operational/functional testing will inform you if the product will
work!
Are you the one who must "sign off" the release/ok to ship paper work?
(Whose neck is in the noose?)
David A. Douthit
Manager
LoCan LLC
Bogert wrote:
> 3/30/002 Folks, we have an OEM who purchased FR-4 printed wiring
> boards from a MIL-P-55110 qualified board manufacturer. The OEM wave
> soldered the PWAs using HF1189A water washable, organic flux and
> cleaned the assemblies using DI water in an in-line cleaning process.
> Subsequent Omegameter 600 ionic cleanliness testing passed. However,
> almost all of the solder side of the PWAs exhibited white residue.
> Basically it looks like a water mark. While you can remove the residue
> using abrasion, such as by a pencil erasure, it comes back, even after
> several subsequent baking operatioins and additional in-line
> cleaning. The OEM sent out samples for outside chemical evaluation
> and found minute traces of carbon. The OEM traced the problem to
> incomplete curing of the LPI solder mask. The white residue only
> appears on the solder side of the PWA. There is no evidence of the
> residue on the component side of the assembly. The OEM proposes that a
> sample assembly be sent out for SIR testing, and that if the test
> passes, they will request us to accept the condition as is. My
> concern is that over time in a humid environment, we may experience
> leakage current paths that cound cause operasting failures. The OEM
> has 20 PWAs that are part of the lot. However, only 6 experience this
> condition. It appears that I should reject all PWAs that show
> evidence of the white residue. I am concerned with the presence of
> carbon, even in trace amounts. The OEM noted that almost everything
> will show traces of carbon, so not to worry. Bottom line is, is there
> any technical concern if the white residue is present? Any input on
> this topic wo\uld be appreciated.
--------------DFE1D64DE18DFB0B0EA98312
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Bogart (luv the name!),
<p>How long is the warranty period?
<br>What sort of liability issues are possible?
<br>If you are in "harsh" environments are you conformal coating the boards?
<br>Won't the OEM pay for operational/functional testing in simulated environments?
<p>There is always a possibility of "leakage" currents and or electrochemical
migration.
<br>Only operational/functional testing will inform you if the product
will work!
<p>Are you the one who must "sign off" the release/ok to ship paper work?
<br>(Whose neck is in the noose?)
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Bogert wrote:
<blockquote TYPE=CITE><style></style>
<font face="Arial"><font size=-1>3/30/002</font></font> <font face="Arial"><font size=-1>Folks,
we have an OEM who purchased FR-4 printed wiring boards from a MIL-P-55110
qualified board manufacturer. The OEM wave soldered the PWAs using
HF1189A water washable, organic flux and cleaned the assemblies using DI
water in an in-line cleaning process. Subsequent Omegameter 600 ionic
cleanliness testing passed. However, almost all of the solder side
of the PWAs exhibited white residue. Basically it looks like a water
mark. While you can remove the residue using abrasion, such as by a pencil
erasure, it comes back, even after several subsequent baking operatioins
and additional in-line cleaning. The OEM sent out samples for outside
chemical evaluation and found minute traces of carbon. The OEM traced
the problem to incomplete curing of the LPI solder mask. The white
residue only appears on the solder side of the PWA. There is no evidence
of the residue on the component side of the assembly.</font></font> <font face="Arial"><font size=-1>The
OEM proposes that a sample assembly be sent out for SIR testing, and that
if the test passes, they will request us to accept the condition as is.
My concern is that over time in a humid environment, we may experience
leakage current paths that cound cause operasting failures. The OEM
has 20 PWAs that are part of the lot. However, only 6 experience
this condition. It appears that I should reject all PWAs that show
evidence of the white residue. I am concerned with the presence of
carbon, even in trace amounts. The OEM noted that almost everything
will show traces of carbon, so not to worry.</font></font> <font face="Arial"><font size=-1>Bottom
line is, is there any technical concern if the white residue is present?
Any input on this topic wo\uld be appreciated.</font></font></blockquote>
</body>
</html>
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Date: Sun, 31 Mar 2002 10:15:11 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Blistering in PCBs
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Steve,
Really very ugly boards.
To my opinion the clue is on the first picture : blisters on =
non-drilled
area.It mean completly failure of the board.
You may call it "blisters".To my opinion this is delamination.
For sure reliability of those boards is zero.
Cross section of the should show it.
If I am right, the list of possible reasons is very long starting from =
raw
materials , pressing procedures , HASL procedures ending with soldering
foults.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: =E5 =EE=F8=F5 29 2002 18:19
> To: [log in to unmask]
> Subject: Re: [TN] Blistering in PCBs
>=20
> Don and Everybody!
>=20
> The pic's are now up! Go to: http://www.stevezeva.homestead.com
>=20
> I gotta say, those are some UGLY boards!
>=20
> -Steve Gregory-
>=20
>=20
>=20
>=20
> Hey Earl
> =09
> Where can I see these photos? Don't see them on Steve's site.
> =09
> Don Vischulis
> =09
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: Friday, March 29, 2002 6:49 AM
> To: [log in to unmask]
> Subject: Re: [TN] Blistering in PCBs
> =09
> =09
> Vinit,
> =09
> Ok, here we go. Never seen nothin' like these before. Oh well, maybe
> once
> when I was a "young gun" process engineer at Xerox. That's another
> story
> I'll not bore anyone with now.
> =09
> Concerning the pics, it is obvious there is delam everywhere but
> maybe the
> edges. Vinitdelam3's discoloration also is delamination, not solder
> mask
> related.
> =09
> Someone else take shots at this and Vinit's supplier. This shop
> shoundn't
> exist unless they just lost it all on his boards ONE PING ONLY
> PLEASE.
> =09
> A pleasure to serve Vinit. Don't often get to see how bad something
> can be
> besides a train wreck.
> =09
> MoonMan
> =09
>=20
>=20
>=20
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Date: Sun, 31 Mar 2002 11:21:17 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: White residue on LPI Solder Mask coated (and
incompletelycured)PWAs, Is it a technical concern?
X-To: Bogert <[log in to unmask]>
MIME-Version: 1.0
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If this were a hi-rel application, I would be very worried. An
improperly cured coating is potentially dangerous and I would want to
know more about what would appear to be an astoichiometric chemistry and
the free components.
The white "residue" is probably a very fine alumina added to the mask to
give it the desired rheological properties (and to reduce the cost). It
has a refractive index close to that of the mask resin, so is normally
invisible. When the mask surface is eroded by solubilisation in water or
by evaporation of an unreacted component, a small quantity will be laid
bare, becoming visible. If this is the case, the alumina itself is
harmless, but unreacted chemicals will always be present.
It would seem your board supplier is trying to weasel out of his
responsibility for producing faulty goods.
Without being certain, I thought that MIL-P-55110 went out of being
several years ago. Unfortunately, I was unable to check it as Assist is
offline just now. I suggest you check with
http://astimage.daps.dla.mil/quicksearch/ to find the current situation.
In any case, it was a specification for bare printed circuits, not a
qualification procedure for suppliers.
IMHO
Brian
> Bogert wrote:
>
> 3/30/002
>
> Folks, we have an OEM who purchased FR-4 printed wiring boards from a
> MIL-P-55110 qualified board manufacturer. The OEM wave soldered
> the PWAs using HF1189A water washable, organic flux and cleaned the
> assemblies using DI water in an in-line cleaning process. Subsequent
> Omegameter 600 ionic cleanliness testing passed. However, almost all
> of the solder side of the PWAs exhibited white residue. Basically it
> looks like a water mark. While you can remove the residue
> using abrasion, such as by a pencil erasure, it comes back, even after
> several subsequent baking operatioins and additional in-line
> cleaning. The OEM sent out samples for outside chemical evaluation
> and found minute traces of carbon. The OEM traced the problem to
> incomplete curing of the LPI solder mask. The white residue only
> appears on the solder side of the PWA. There is no evidence of the
> residue on the component side of the assembly.
>
> The OEM proposes that a sample assembly be sent out for SIR testing,
> and that if the test passes, they will request us to accept the
> condition as is. My concern is that over time in a humid environment,
> we may experience leakage current paths that cound cause operasting
> failures. The OEM has 20 PWAs that are part of the lot. However,
> only 6 experience this condition. It appears that I should reject all
> PWAs that show evidence of the white residue. I am concerned with the
> presence of carbon, even in trace amounts. The OEM noted that almost
> everything will show traces of carbon, so not to worry.
>
> Bottom line is, is there any technical concern if the white residue is
> present? Any input on this topic wo\uld be appreciated.
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Date: Mon, 1 Apr 2002 09:26:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
don_well <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: don_well <[log in to unmask]>
Subject: Rework RF amplifier boards
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Date: Mon, 1 Apr 2002 13:57:01 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Re: MIL-C-28809 Replacement/supersede
X-To: "Sauer, Steven T." <[log in to unmask]>
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Thanks Steve.
I have a few questions :
1. What then is classified as "standard" and what is "non-standard"?
2. Who is the Material Review Board (MRB)?
3. Since MIL-C-28809 no longer exist, are we allow to or can we develop an in-house workmanship, making
referral to an aboselete standard?
Regards - Wee Mei
"Sauer, Steven T." wrote:
> Hello Wee Mei,
> To my knowledge, the information that you are looking for does not exist in
> a replacement military specification nor other industry association
> documents.
> On one hand, the information contained in MIL-C-28809 was considered
> requirements for "standard" repair/modification. Repair and modifications
> that did not fall within these requirements, "non-standard", were turned
> over to a Material Review Board (MRB) and dependent on contractual
> requirements may have included customer review and approval/disapproval.
> With today's technology and the ever changing end use environments,
> "standard" repairs should be reviewed by a MRB for issues related to
> quality, performance, reliability and maintainability of the deliverable
> product. The guidance information contained in MIL-C-28809 can be used to
> develop criteria for use by a MRB or better yet, used to develop an in-house
> procedure for standard repairs that defines specifics for your products.
> IPC-7721 (supercedes IPC-R-700) is widely accepted and used for repair and
> modification of electronic assemblies, but it does not contain "maximum
> allowable" criteria.
>
> Steve Sauer
>
> -----Original Message-----
> From: fullname [mailto:[log in to unmask]]
> Understand that MIL-C-28809 has been cancelled. However, there are two
> tables indicates in this mil-spec on the max. number allowed permitted
> for plated-thorugh hole repair and circuit repair. Can someone point to
> me where else can I find similar tables for repair under IPC standards?
>
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