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Date: Sun, 10 Feb 2002 10:35:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Different CTE materials, what is the safe tolerance ?
Folks,
I hope you all aren't getting too tired of this. I am. I spent the morning
hours cutting and filing the images you may see on Steve's site. Damn near
lost a thumb this time.
My last message I thought was to Steve only. However, if Steve is so kind as
to post these images, the pics will show as indicated in text what I found,
but don't know the exact meaning of yet, you will see some more interesting
things. As an example, for those never having seen what fiber glass "cloth"
like, the images show it.
Sure wish Werner well with grandkiddies, but I need some more help. Maybe
Dave Hillman has some more educated ideas since I sent him my first report
from fellow Rockwell types. Also, I still await Joe Felstad's comments about
the chip attachment, its method, and the lack of an apparent
"compliant/flex" layer as he helped develop at Tessera.
MoonMan
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Date: Sun, 10 Feb 2002 13:03:22 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Different CTE materials, what is the safe tolerance ?
X-To: [log in to unmask], [log in to unmask]
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Hi Steve,
In a message dated 02/09/2002 20:53:56, [log in to unmask] writes:
>One other question that I'll throw-out there, is why in the hell do companies
>like Texas Instruments put components on the market that can't be assembled
>with standard processes?
The component suppliers have all conspired to make sure consultants are not
short of work.
Seriously though, it is a sad fact that component suppliers, with very few
notable exceptions are a part of the problem and have a serious
throw-it-over-the-wall attitude.
It started with LLCCCs, followed by plastic components with Alloy 42
leadframes and leads (TSOP, SOT), SBGAs, CBGAs, ....you name it.
Werner Engelmaier
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Date: Sun, 10 Feb 2002 13:03:23 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Different CTE materials, what is the safe tolerance ?
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Earl, the MoonMan,
First, I have problems accessing Steve's website--please send me the pics
directly.
Second,
>Thermally asymetric? Does this mean in the Z axis as a primary function of
>the Al heat sink and the Silicon chip placed on a BT substrate, or?
A: What it means is that the various layers [overmold, die, die attach,
interposer, package substrate] are made of different materials all having
different CTEs and modulii of elasticity. By proper variation of the
thicknesses of these materials one can achieve a thermally balanced [or at
least nearly balanced] design where the various layers will thermally
expand/contract without significantly warping [of course there are shear
forces between these layers] the package--with a metal heat spreader this
becomes essentially impossible with the heat spreader on the outside.
Third, the die attach on thin BGAs is typically some polyimide-based adhesive.
Fourth,
>Sure wish Werner well with grandkiddies, but I need some more help. Maybe
>Dave Hillman has some more educated ideas since I sent him my first report
>from fellow Rockwell types. Also, I still await Joe Felstad's comments about
>the chip attachment, its method, and the lack of an apparent
>"compliant/flex" layer as he helped develop at Tessera.
A: The "compliant/flex" interposer layer of the Tessera patents is needed
most for CSPs and thin BGAs with a thin package substrate not including woven
glass-fiber reinforcement and prevents the large die/PCB expansion mismatch
from loading the SJs [the failures would occur at the die corners]--the large
die/PCB expansion mismatch is accommodated in the "compliant/flex" interposer
layer(s) [in some designs to the extent that the copper traces broke]. The
BLR of the larger BGA packages depends on the much thicker woven glass-fiber
reinforced BT to be stiff enough to shield the solder joints from the much
larger die/PCB CTE-mismatch. This works particularly well for packages much
larger than the die [it is the package corner SJs that fail first] and those
with SJ arrays depopulated under the die.
I hope this helps--you do need to get out of your cave more often--there is a
whole world out here
Werner Engelmaier
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Date: Sun, 10 Feb 2002 13:20:34 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Different CTE materials, what is the safe tolerance ?
X-To: [log in to unmask]
Sure Werner,
I get out of mine once and awhile and look what happens. You keep one close
eye on the kiddies and another, on Sunday at that, on the MoonMan's rants.
Ok, I got it. It's as I envisioned and can see clearly now - all popsicles
in my way. It's not a bright sun shiney day however.
Like big Steve, I keep seeing red as the kind folks, as TI, keep shoving it
to us. I'm just trying to get someone like Steve to build these damn boards
with these damn components. If he, or someone like him, can't do it, their
reputations, like mine for hiring him, is shot to hell.
Been down just about every LCCCC, CCGA, BGA, and all the rest, as alloy 42,
and did reasonably well. This time, I and my client are stuck, as there
seems not alternative because no alternate DSP exists.
I'm sending the pictures directly to you. Hope your grandchildren learn to
love this stuff as much as their grandfather. They're going to need to just
to survive in the "new world" especially without lead in their diets and
solder joints.
MoonCaveMan staying out way too long.
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Date: Sun, 10 Feb 2002 15:25:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB Question - Final Analysis is complete
MIME-Version: 1.0
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Hi Kathy,
you did not send me any of the X-sections--could you?
Werner Engelmaier
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Date: Sun, 10 Feb 2002 21:57:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
YH Koh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: YH Koh <[log in to unmask]>
Subject: Plating Audit Template
Dear All,
I am looking for a command audit template that can address the plating
capability of a PCB maker. The reasons are to compare and rate a few PCB
suppliers to identify if they are matching the world class requirements.
I am not sure if there is a command plating template that will cover:
1. Plating machinery
2. Plating technology
3. Process control system - in process and outgoing etc.
4. Chemistry
5. Plating capability like thickness,minuimum platable vias etc.
Thank you.
Regards,
YH Koh
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Date: Mon, 11 Feb 2002 12:24:59 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Atkinson, Neil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Flux Testing using Titration
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
We are currently buying titration kits from a solder / flux supplier. Does
anyone out there buy the chemicals to do this from a standard chemical
supplier (cheaper?) and if so which chemicals do I need, in what
concentrations etc and can I just follow the same procedure and use the flux
manufacturer's titration curves?
Thanks,
Neil
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Date: Mon, 11 Feb 2002 06:35:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: PRESENTING THE BAD NEWS
Folks,
For those caring, my final summary of this thing is as has been stated. As
Werner puts it, the first thing bad is the asymetric device construction.
This means coplanarity is compromised because of the aluminum heat sink atop
the part and attached directly to the hot Silicon part. This causes the PCB
substrate to warp.
The second issue points to the reason Tessera is successful. They used a
compliant flex layer to ensure CTE matchibng characteristics are not
compromised as in the case of the TI device wheren its die is directly
attachd to the PCB substrate.
Therefore, two failure mechanisms are at work. Each or both are capable of
effecting poor initial quality solder joints and negatively impact long term
reliability.
Thanks all on and off line,
Earl Moon
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Date: Mon, 11 Feb 2002 06:54:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: PRESENTING POSSIBLE GOOD NEWS
I'm sure everyone else on the planet is aware of the following:
Tessera Technologies and Texas Instruments Settle Patent Infringement Disputes
TI Takes Tessera Patent License for TI?s MicroStar? BGA Technology
Editorial Contacts:
Molly Taylor
The Hoffman Agency, for Tessera
(408) 975-3067
[log in to unmask]
San Jose, Calif. - January 7, 2002 - Tessera Technologies announced today
that it has reached settlement with Texas Instruments, Inc. (NYSE:TXN) of
pending litigation between the companies relating to CSP technology. The
settlement will result in the dismissal of patent infringement claims and
related issues in U.S. District Courts in Oakland, CA and Marshall, TX.
Under the terms of the settlement, the parties will release each other from
all pending claims and counterclaims. TI will make a one-time payment to
Tessera. The settlement includes a royalty-bearing license that covers TI's
MicroStar? family of FBGA packages. The MicroStar package is primarily used
to package TI's flagship DSP technology used in OEM products, such as mobile
phones, MP3 players and personal digital assistants. The remaining terms of
the settlement are confidential.
?Tessera is pleased that it has been able to reach an agreement with Texas
Instruments?. said Chris Pickett, senior vice president, licensing business
and general counsel, Tessera. ?We look forward to building a positive
business relationship with TI as we move forward.?
This will do it for me. Now, most of the problems I faced before will be
resolved, qualified to the extent all else is acceptable. Also, I will now
contact TI directly concerning their MicroStar package and see when our 6302
DSP will be available, if not already.
Earl Moon
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Date: Mon, 11 Feb 2002 09:06:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bartkowaik Christine <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bartkowaik Christine <[log in to unmask]>
Subject: No Clean Process
MIME-Version: 1.0
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I would like leads to recent NO CLEAN articles, "white" papers or books.
Thanks, Chris
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Date: Mon, 11 Feb 2002 09:55:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
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From: Bev Christian <[log in to unmask]>
Subject: Re: Flux Testing using Titration
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Neil,
It depends on who you ask. If you are talking about the quick and dirty
at-the-wave-solder-machine titrations, I doubt they will recommend you use
anything but their kits. But if you are going to do it in a lab with proper
equipment, trained personnel, you may be able to nicely ask them for their
lab procedure on how they do it. Some of them will give it to you, and some
won't.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Atkinson, Neil [mailto:[log in to unmask]]
Sent: February 11, 2002 7:25 AM
To: [log in to unmask]
Subject: [TN] Flux Testing using Titration
We are currently buying titration kits from a solder / flux supplier. Does
anyone out there buy the chemicals to do this from a standard chemical
supplier (cheaper?) and if so which chemicals do I need, in what
concentrations etc and can I just follow the same procedure and use the flux
manufacturer's titration curves?
Thanks,
Neil
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Date: Mon, 11 Feb 2002 07:09:40 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re:
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
this reminds me of old saw which goes something like:
if you put a teaspoon of dreck in a barrel of fine wine, you'll end up with a barrel of dreck. on the other hand if you put a teaspoon of fine wine in a barrel of dreck, you won't end up with a barrel of fine wine.
phil
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, February 07, 2002 4:15 PM
To: [log in to unmask]
Subject: Re: [TN]
You'll just ruin a lot of nice new paste. It's like having hot water, and
cold water that used to be hot - mix the two and you get warm water. The
cold one is hotter than it was (rejuvinated a bit, if you like, but not
completely) while the hot water is much cooler (rapidly aged).
Peter
Surface Mount
<smt@Q-TRONIC To: [log in to unmask]
S.NET> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN]
<[log in to unmask]
ORG>
02/08/02
04:48 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Surface Mount
Hello,
I work for a small PCB Manufacturing plant in Michigan. I am somewhat
new to the buisness, and my co-workers have been giving me info about
solder
paste, but there seems to be some questions about solder paste use
We use Kester R562 solder paste. One of the things they are telling me is
mixing new solder paste with old solder paste will rejuvinate the old
paste.
Is this true, or will it just ruin the new paste.
Art Hampton
[This e-mail is confidential and may also be privileged. If you are not the
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Date: Mon, 11 Feb 2002 10:32:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flux Testing using Titration
MIME-Version: 1.0
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If you vendor will not give you a procedure..
Send me (off-line) your current procedure...
and I will work up a method, and send it to you.
Key issues needed to do this are:
Name of indicator...is flux water based, and do you add water during testing?
Rudy Sedlak ([log in to unmask])
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Date: Mon, 11 Feb 2002 10:32:47 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No Clean Process
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Chris,
Here are a few links that are pretty good:
http://www.pprc.org/pprc/p2tech/noclean/nointro.html
http://www.epa.gov/ozone/title6/snap/icel/noclean1.pdf
http://www.epa.gov/ozone/title6/snap/icel/noclean2.pdf
-Steve Gregory-
> I would like leads to recent NO CLEAN articles, "white" papers or books.
> Thanks, Chris
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Chris,
<BR>
<BR>Here are a few links that are pretty good:
<BR>
<BR>http://www.pprc.org/pprc/p2tech/noclean/nointro.html
<BR>http://www.epa.gov/ozone/title6/snap/icel/noclean1.pdf
<BR>http://www.epa.gov/ozone/title6/snap/icel/noclean2.pdf
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I would like leads to recent NO CLEAN articles, "white" papers or books.
<BR>Thanks, Chris
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Mon, 11 Feb 2002 10:49:50 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Re: Plating Audit Template
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Mr. Koh:
If I may speak openly for all my beleaguered collegues/customers, as they
would be afraid to discuss this openly with Motorola...
The most important characteristics of potential plating quality really cannot
be measured in any programmable way, save by looking at results.
It takes great understanding and intelligence to set up and run a plating
process in the modern PCB facility, and no amount of ISO standardization can
monitor that.
You will certainly get vast amounts of data about "control" of plating
systems, but at the end of the day, it is only slightly above a "black art",
and the most important aspects, design of the tanks, and fluid flow, are not
understandable to outside audit teams. Further, issues like plating rate,
anode placement, etc. can change with every job.
You can run test coupons with every load, but it will not tell you if the PCB
is being plated correctly.
Look at results on the PCB...that is the only real truth....the rest is
largely window dressing, and often expensive and difficult to obtain window
dressing.
Rudy Sedlak
RD Chemical Company
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Date: Mon, 11 Feb 2002 08:32:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dyane White <[log in to unmask]>
Subject: Re: Upside down chip resistors
X-To: Mel Parrish <[log in to unmask]>
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The entrapment of chemical process chemistries is an issue because material can become entrapped in the kerf. If the component in upside down it cannot be cleaned. The rev C version of the IPC 610 does call this a process indicator so for that reason I
guess it has become a non isuue.
Dyane White
Process/Technical Trainer
Philips Ultrasound
Mel Parrish
<mparrish@SOLDERIN To: [log in to unmask]
GTECH.COM> cc: (bcc: Dyane White/ATL-BTL/MS/PHILIPS)
Sent by: TechNet Subject: Re: [TN] Upside down chip resistors
<[log in to unmask]>
Classification:
02/08/02 05:22 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Mel
Parrish
Agree with MoonMan, but for discussion, this criteria was included in the
standards some time ago and was a carry over from the Mil Specs. The testing
was accomplished then to determine if there was justification to consider
orientation of these components. The tests for a particular program proved
that there was a very significant increase in component operational life if
the component was face up.
We didn't look at the "why" although there was speculation concerning
entrapment of process chemistries, or thermal issues for the film close to
the board.
IPC-A-610C calls this a Process Indicator for Class 2 and 3 which wouldn't
support rework. If the long term reliability of the component was a
concern, you might look at effective methods to correct it (not point to
point soldering). Best option is to orient up if it by process if required.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, February 08, 2002 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Upside down chip resistors
The less rework, the better. When replacing or reworking any chip device,
using hand soldering techniques, chances are damage will ensue.
MoonMan
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Date: Mon, 11 Feb 2002 11:57:30 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: timeline-Gantt chart
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Anyone have a sample timeline for ISO implementation.
Been looking for this for days, still no luck. Thanks.
Joseph Spicuzza
Quality Assurance Manager
Advanced Interconnect Products Division
Compunetics, Inc.
PH: 412 858-6166
FX: 412 373-8060
[log in to unmask]
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Date: Mon, 11 Feb 2002 17:30:53 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Flux Testing using Titration
X-To: Bev Christian <[log in to unmask]>
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I think the flux guys would claim, with justification in some cases, that
their "at the point of use" kits are designed for a non chemist to be able
to use reliably. Conversely if you have a lab with proper chemists in it,
then they will be most likely able to do the titration anyway.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Monday, February 11, 2002 2:55 PM
To: [log in to unmask]
Subject: Re: [TN] Flux Testing using Titration
Neil,
It depends on who you ask. If you are talking about the quick and dirty
at-the-wave-solder-machine titrations, I doubt they will recommend you use
anything but their kits. But if you are going to do it in a lab with proper
equipment, trained personnel, you may be able to nicely ask them for their
lab procedure on how they do it. Some of them will give it to you, and some
won't.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Atkinson, Neil [mailto:[log in to unmask]]
Sent: February 11, 2002 7:25 AM
To: [log in to unmask]
Subject: [TN] Flux Testing using Titration
We are currently buying titration kits from a solder / flux supplier. Does
anyone out there buy the chemicals to do this from a standard chemical
supplier (cheaper?) and if so which chemicals do I need, in what
concentrations etc and can I just follow the same procedure and use the flux
manufacturer's titration curves?
Thanks,
Neil
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Date: Mon, 11 Feb 2002 19:06:25 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: No Clean Process
X-To: Bartkowaik Christine <[log in to unmask]>
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Hi Chris,
When you go to my page www.smtinfo.net/smtlinks.html you'll see a =
sections "search articles database" somewhere at the top. A search on =
"no-clean flux" or "low residue" or thinkgs like that should give you =
quite a few links. Because my search engine searches in a database of =
technical articles (about 350 now) the results should be more relevant =
than with the normal searchengines.
Hope this doesn't sound like advertising, just trying to help.....
Daan=20
----- Original Message -----=20
From: Bartkowaik Christine=20
To: [log in to unmask]
Sent: Monday, February 11, 2002 3:06 PM
Subject: [TN] No Clean Process
I would like leads to recent NO CLEAN articles, "white" papers or =
books.
Thanks, Chris
=
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>Hi Chris,</DIV>
<DIV> </DIV>
<DIV>When you go to my page <A=20
href=3D"http://www.smtinfo.net/smtlinks.html">www.smtinfo.net/smtlinks.ht=
ml</A>=20
you'll see a sections "search articles database" somewhere at the top. A =
search=20
on "no-clean flux" or "low residue" or thinkgs like that should give you =
quite a=20
few links. Because my search engine searches in a database of technical =
articles=20
(about 350 now) the results should be more relevant than with the =
normal=20
searchengines.</DIV>
<DIV>Hope this doesn't sound like advertising, just trying to =
help.....</DIV>
<DIV> </DIV>
<DIV>Daan </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">Bartkowaik=20
Christine</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, February 11, 2002 =
3:06=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] No Clean =
Process</DIV>
<DIV><BR></DIV>I would like leads to recent NO CLEAN articles, "white" =
papers=20
or books.<BR>Thanks,=20
=
Chris<BR><BR>------------------------------------------------------------=
---------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
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NOMAIL<BR>To=20
receive ONE mailing per day of all the posts: send e-mail to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
Digest<BR>Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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Date: Mon, 11 Feb 2002 12:26:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: No Clean Process
X-To: [log in to unmask]
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Doesn't sound like "run-of-the-mill" advertsiing to me Daan,
your research and technical knowledge are, in my mind, invaluable to this =
forum. Keep up the good work!
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
>>> [log in to unmask] 02/11/02 12:06PM >>>
Hi Chris,
When you go to my page www.smtinfo.net/smtlinks.html you'll see a sections =
"search articles database" somewhere at the top. A search on "no-clean =
flux" or "low residue" or thinkgs like that should give you quite a few =
links. Because my search engine searches in a database of technical =
articles (about 350 now) the results should be more relevant than with the =
normal searchengines.
Hope this doesn't sound like advertising, just trying to help.....
Daan=20
----- Original Message -----=20
From: Bartkowaik Christine=20
To: [log in to unmask]
Sent: Monday, February 11, 2002 3:06 PM
Subject: [TN] No Clean Process
I would like leads to recent NO CLEAN articles, "white" papers or books.
Thanks, Chris
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Date: Mon, 11 Feb 2002 20:10:10 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Ceramic CSP's and BGA's in general
X-To: Earl Moon <[log in to unmask]>
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Hi Earl,
About CBGA's, I just uploaded a very interesting document called =
"Ceramic Ball Grid Array Assembly Reliability in Military Applications" =
to www.smtinfo.net/docs/bga_80775_c.pdf It's about the assembly process =
with Kyocera's dimpled CBGA, with SnPbBi solderballs (melting point =
close to eutectic solder). Really good stuff, including results of =
reliability studies.
Best regards,
Daan
----- Original Message -----=20
From: Earl Moon=20
To: [log in to unmask]
Sent: Thursday, February 07, 2002 9:41 PM
Subject: [TN] Ceramic CSP's and BGA's in general
Kind folks of the IPC TechNet and those not so but well informed =
concering
the subject issue - for me.
I have gone back and re-read all the articles and papers concerning =
ceramic
packages, but for CCGA's. I am, as some of you in the past, about the =
great
CTE mismatch between ceramic, silicon, and MLB's without constraining =
or
tailoring core materials.
My "frinds" at TI and IBM have been the primary players in this game. =
TI's
approach to solder balls is using eutectic types - I belive though not
certain in every instance. IBM talks to hard balls (90% lead) instead =
- in
most cases as I again believe.
I like the hard ball approach because no collapse, of course, is =
effected
during reflow. Therefore, more hot air is allowed to "circulate" under =
and
between the balls effecting a better solder joint consistently.
I am hopeful, some of you can shed some light with positive =
experiences with
the aformentiond parts and their solder joint acceptable initially, =
and long
term reliability. Realizing we have gone down this pass a few times, I =
hope
there is some "new" information besides the great stuff the two =
companies in
question provide.
As a lover of CCGA's, past and present, by IBM, I wish these parts =
could use
this technology. It works first and always.
Beyond this, I am hoping TI, as a major DSP device supplier, proves =
its
plastic BGA (super BGA or perimeter BGA - whichever) does the job. It =
is
said they are packaging four chips in this package style making it =
lower
cost and certainly more reliable due to the CTE issue.
Any input appreciated,
MoonMan
=
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<DIV>Hi Earl,</DIV>
<DIV> </DIV>
<DIV>About CBGA's, I just uploaded a very interesting document called =
"Ceramic=20
Ball Grid Array Assembly Reliability in =
Military Applications" to <A=20
href=3D"http://www.smtinfo.net/docs/bga_80775_c.pdf">www.smtinfo.net/docs=
/bga_80775_c.pdf</A> =20
It's about the assembly process with Kyocera's dimpled CBGA, with SnPbBi =
solderballs (melting point close to eutectic solder). Really good stuff, =
including results of reliability studies.</DIV>
<DIV> </DIV>
<DIV>Best regards,</DIV>
<DIV> </DIV>
<DIV>Daan</DIV>
<DIV> </DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, February 07, =
2002 9:41=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Ceramic CSP's and =
BGA's in=20
general</DIV>
<DIV><BR></DIV>Kind folks of the IPC TechNet and those not so but well =
informed concering<BR>the subject issue - for me.<BR><BR>I have gone =
back and=20
re-read all the articles and papers concerning ceramic<BR>packages, =
but for=20
CCGA's. I am, as some of you in the past, about the great<BR>CTE =
mismatch=20
between ceramic, silicon, and MLB's without constraining =
or<BR>tailoring core=20
materials.<BR><BR>My "frinds" at TI and IBM have been the primary =
players in=20
this game. TI's<BR>approach to solder balls is using eutectic types - =
I belive=20
though not<BR>certain in every instance. IBM talks to hard balls (90% =
lead)=20
instead - in<BR>most cases as I again believe.<BR><BR>I like the hard =
ball=20
approach because no collapse, of course, is effected<BR>during reflow. =
Therefore, more hot air is allowed to "circulate" under and<BR>between =
the=20
balls effecting a better solder joint consistently.<BR><BR>I am =
hopeful, some=20
of you can shed some light with positive experiences with<BR>the =
aformentiond=20
parts and their solder joint acceptable initially, and long<BR>term=20
reliability. Realizing we have gone down this pass a few times, I=20
hope<BR>there is some "new" information besides the great stuff the =
two=20
companies in<BR>question provide.<BR><BR>As a lover of CCGA's, past =
and=20
present, by IBM, I wish these parts could use<BR>this technology. It =
works=20
first and always.<BR><BR>Beyond this, I am hoping TI, as a major DSP =
device=20
supplier, proves its<BR>plastic BGA (super BGA or perimeter BGA - =
whichever)=20
does the job. It is<BR>said they are packaging four chips in this =
package=20
style making it lower<BR>cost and certainly more reliable due to the =
CTE=20
issue.<BR><BR>Any input=20
=
appreciated,<BR><BR>MoonMan<BR><BR>--------------------------------------=
-------------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
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Date: Mon, 11 Feb 2002 14:27:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bartkowaik Christine <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bartkowaik Christine <[log in to unmask]>
Subject: Re: No Clean Process
X-To: [log in to unmask]
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Steve: These articles look very helpful thanks for the support.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, February 11, 2002 10:33 AM
To: [log in to unmask]
Subject: Re: [TN] No Clean Process
Chris,
Here are a few links that are pretty good:
http://www.pprc.org/pprc/p2tech/noclean/nointro.html
http://www.epa.gov/ozone/title6/snap/icel/noclean1.pdf
http://www.epa.gov/ozone/title6/snap/icel/noclean2.pdf
-Steve Gregory-
I would like leads to recent NO CLEAN articles, "white" papers or books.
Thanks, Chris
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<DIV><SPAN class=260082019-11022002><FONT face=Arial color=#0000ff
size=2>Steve: These articles look very helpful thanks for the
support.</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, February 11, 2002 10:33
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] No Clean
Process<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Chris,
<BR><BR>Here are a few links that are pretty good:
<BR><BR>http://www.pprc.org/pprc/p2tech/noclean/nointro.html
<BR>http://www.epa.gov/ozone/title6/snap/icel/noclean1.pdf
<BR>http://www.epa.gov/ozone/title6/snap/icel/noclean2.pdf <BR><BR>-Steve
Gregory- <BR><BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">I would like leads to recent NO CLEAN articles, "white" papers
or books. <BR>Thanks, Chris <BR></FONT><FONT lang=0 face=Arial color=#000000
size=3 FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0 face=Arial
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Date: Mon, 11 Feb 2002 14:51:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Moses <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Moses <[log in to unmask]>
Subject: Re: Upside down chip resistors
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If the IPC 610 labels it as a process indicator then it is not truly a =
defect correct? Therefore it does not need rework, but does require =
process improvement. =20
By the way, thanks for all of your responses regarding the upside down =
chip resistors. =20
John Moses
>>> [log in to unmask] 02/11/02 11:32AM >>>
The entrapment of chemical process chemistries is an issue because =
material can become entrapped in the kerf. If the component in upside =
down it cannot be cleaned. The rev C version of the IPC 610 does call =
this a process indicator so for that reason I
guess it has become a non isuue.
Dyane White
Process/Technical Trainer
Philips Ultrasound
Mel Parrish
<mparrish@SOLDERIN To: [log in to unmask]
GTECH.COM> cc: (bcc: Dyane =
White/ATL-BTL/MS/PHILIPS)
Sent by: TechNet Subject: Re: [TN] Upside =
down chip resistors
<[log in to unmask]>
Classification:
02/08/02 05:22 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Mel
Parrish
Agree with MoonMan, but for discussion, this criteria was included in the
standards some time ago and was a carry over from the Mil Specs. The =
testing
was accomplished then to determine if there was justification to consider
orientation of these components. The tests for a particular program proved
that there was a very significant increase in component operational life =
if
the component was face up.
We didn't look at the "why" although there was speculation concerning
entrapment of process chemistries, or thermal issues for the film close to
the board.
IPC-A-610C calls this a Process Indicator for Class 2 and 3 which wouldn't
support rework. If the long term reliability of the component was a
concern, you might look at effective methods to correct it (not point to
point soldering). Best option is to orient up if it by process if =
required.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, February 08, 2002 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Upside down chip resistors
The less rework, the better. When replacing or reworking any chip device,
using hand soldering techniques, chances are damage will ensue.
MoonMan
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Date: Mon, 11 Feb 2002 15:03:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: Upside down chip resistors
X-To: John Moses <[log in to unmask]>
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If i remember why the IPC group made it a process indicator for class 2 and
3 is because you could not always be certain of the orientation of the
component during pick and place. Some of the new bulk feeders for chips
could orient the component for placement either way. This did have some
debate and the consense was that this should be considered a process
indicator.
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Date: Mon, 11 Feb 2002 12:53:46 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bob Perkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Perkins <[log in to unmask]>
Subject: FW: Moisture Sensitive Devices
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Hi all,
Regarding moisture sensitive devices, all the levels I see are in respect
to <= 30c 60%RH. The time specified for these levels are clear but what
if I am dealing with 30%RH. Is there a sliding scale that is applied to
this level of humidity or do I strickly go with the times given at 60%RH..
ex. The level 5 component has 48 hours, would that be 96 hours on my
production floor if I'm at 30% RH ?
Thanks
Bob P
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<DIV><SPAN class=744051118-11022002>Hi all,</SPAN></DIV>
<DIV><SPAN class=744051118-11022002><SPAN class=402424220-11022002><FONT
color=#0000ff face=Arial size=2> </FONT></SPAN></SPAN></DIV>
<DIV><SPAN class=744051118-11022002><SPAN
class=402424220-11022002> </SPAN>Regarding moisture sensitive
devices, all the levels I see are in respect to<SPAN
class=339012919-11022002> <SPAN
class=402424220-11022002> <= </SPAN> </SPAN>30c<SPAN
class=402424220-11022002> 6</SPAN>0%RH. The time specified for
these levels are clear but what if I am dealing with 30%RH. Is
there a sliding scale that is applied to this level of humidity or do I
s<SPAN class=402424220-11022002><FONT color=#0000ff face=Arial size=2><FONT
color=#000000 face="Times New Roman"
size=3>trickly go</FONT></FONT></SPAN> with the times given at 60%RH..
ex. The level 5 component has 48 hours, would that be 96 hours on my
production floor<SPAN class=339012919-11022002> if I'm at 30%
RH </SPAN>? </SPAN></DIV>
<DIV><SPAN class=744051118-11022002></SPAN> </DIV>
<DIV><SPAN class=744051118-11022002><SPAN class=402424220-11022002><FONT
color=#0000ff face=Arial size=2><FONT color=#000000 face="Times New Roman"
size=3>Thanks</FONT></FONT></SPAN></SPAN></DIV>
<DIV><SPAN class=744051118-11022002>Bob <FONT color=#0000ff face=Arial
size=2><SPAN class=402424220-11022002> <FONT color=#000000
face="Times New Roman" size=3>P</FONT></SPAN></FONT></SPAN><SPAN
class=744051118-11022002><FONT color=#0000ff face=Arial size=2><SPAN
class=402424220-11022002> </SPAN></FONT></SPAN></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 11 Feb 2002 17:22:32 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Here is the board buyers opportunity
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Ladies and Gentlemen of the Technet (and you too Steve... :-)
I need you to put me to the test...., he said, opening himself up to he knows
not what...
Imagine, if you would, that someone had the temerity to announce the arrival
of the worlds greatest innerlayer oxide....it did everything, created only
purest water as an effluent, and was free...
Well, maybe not quite that good...
What tests would you ask this vendor to pass before accepting it on your most
hallowed of boards? (Besides the obvious minimum vendor sanity
requirements....)
My pencil is poised.....solder pot heating, and I am scared...
Rudy Sedlak
RD Chemical Company
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Date: Mon, 11 Feb 2002 17:56:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kane, Joseph" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kane, Joseph" <[log in to unmask]>
Subject: Re: FW: Moisture Sensitive Devices
X-To: Bob Perkins <[log in to unmask]>
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J-STD-033 has the "derating" tables you're looking for.
-----Original Message-----
From: Bob Perkins [mailto:[log in to unmask]]
Sent: Monday, February 11, 2002 3:54 PM
To: [log in to unmask]
Subject: [TN] FW: Moisture Sensitive Devices
Hi all,
Regarding moisture sensitive devices, all the levels I see are in respect
to <= 30c 60%RH. The time specified for these levels are clear but what
if I am dealing with 30%RH. Is there a sliding scale that is applied to
this level of humidity or do I strickly go with the times given at 60%RH..
ex. The level 5 component has 48 hours, would that be 96 hours on my
production floor if I'm at 30% RH ?
Thanks
Bob P
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<DIV><SPAN class=874095722-11022002><FONT face=Arial color=#0000ff
size=2>J-STD-033 has the "derating" tables you're looking
for.</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Bob Perkins
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, February 11, 2002
3:54 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] FW: Moisture
Sensitive Devices<BR><BR></FONT></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV><SPAN class=744051118-11022002>Hi all,</SPAN></DIV>
<DIV><SPAN class=744051118-11022002><SPAN class=402424220-11022002><FONT
face=Arial color=#0000ff size=2></FONT></SPAN></SPAN> </DIV>
<DIV><SPAN class=744051118-11022002><SPAN
class=402424220-11022002> </SPAN>Regarding moisture sensitive
devices, all the levels I see are in respect to<SPAN
class=339012919-11022002> <SPAN
class=402424220-11022002> <= </SPAN> </SPAN>30c<SPAN
class=402424220-11022002> 6</SPAN>0%RH. The time specified for
these levels are clear but what if I am dealing with 30%RH. Is
there a sliding scale that is applied to this level of humidity or do I
s<SPAN class=402424220-11022002><FONT face=Arial color=#0000ff size=2><FONT
face="Times New Roman" color=#000000
size=3>trickly go</FONT></FONT></SPAN> with the times given at 60%RH..
ex. The level 5 component has 48 hours, would that be 96 hours on my
production floor<SPAN class=339012919-11022002> if I'm at 30%
RH </SPAN>? </SPAN></DIV>
<DIV><SPAN class=744051118-11022002></SPAN> </DIV>
<DIV><SPAN class=744051118-11022002><SPAN class=402424220-11022002><FONT
face=Arial color=#0000ff size=2><FONT face="Times New Roman" color=#000000
size=3>Thanks</FONT></FONT></SPAN></SPAN></DIV>
<DIV><SPAN class=744051118-11022002>Bob <FONT face=Arial color=#0000ff
size=2><SPAN class=402424220-11022002> <FONT face="Times New Roman"
color=#000000 size=3>P</FONT></SPAN></FONT></SPAN><SPAN
class=744051118-11022002><FONT face=Arial color=#0000ff size=2><SPAN
class=402424220-11022002> </SPAN></FONT></SPAN></DIV></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 11 Feb 2002 18:05:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Source for solder
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All
I am looking for a source for a solder named Motorola "J" solder.
Composition is
Sn65Ag25Sb10. I have scanned several company's product and they have do not
have it listed. If you have any leads let me know.
Phil Hiinton
[log in to unmask]
520-745-1013
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>All
<BR>
<BR>I am looking for a source for a solder named Motorola "J" solder. Composition is
<BR>Sn65Ag25Sb10. I have scanned several company's product and they have do not have it listed. If you have any leads let me know.
<BR>
<BR>Phil Hiinton
<BR>[log in to unmask]
<BR>520-745-1013 </FONT></HTML>
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Date: Mon, 11 Feb 2002 18:15:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
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From: tony steinke <[log in to unmask]>
Subject: Re: Source for solder
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Try Norm Volle at [log in to unmask]
----- Original Message -----=20
From: [log in to unmask]
To: [log in to unmask]
Sent: Monday, February 11, 2002 3:05 PM
Subject: [TN] Source for solder
All=20
I am looking for a source for a solder named Motorola "J" solder. =
Composition is=20
Sn65Ag25Sb10. I have scanned several company's product and they have =
do not have it listed. If you have any leads let me know. =20
Phil Hiinton=20
[log in to unmask]
520-745-1013 =20
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style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
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<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, February 11, 2002 =
3:05=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Source for =
solder</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>All =
<BR><BR>I am=20
looking for a source for a solder named Motorola "J" solder. =
Composition=20
is <BR>Sn65Ag25Sb10. I have scanned several company's product =
and they=20
have do not have it listed. If you have any leads let me know. =
=20
<BR><BR>Phil Hiinton <BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <BR>520-745-1013 =
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Date: Mon, 11 Feb 2002 15:31:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
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Date: Mon, 11 Feb 2002 17:04:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Solder spikes in wave soldering
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Hello,
What are the possible causes for solder spikes in wave soldering TH
components. How would one trouble shoot such a defect?
Rgds,
Peter
_________________________________________________________
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Date: Mon, 11 Feb 2002 21:15:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: timeline-Gantt chart
X-To: Joseph Spicuzza <[log in to unmask]>
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http://www.questanalytical.com/ISO9000/FAQ/How_Long_Will_it_Take.htm
http://www.school-for-champions.com/iso9000/isosteps.htm
http://vig.pearsoned.com/samplechapter/0130620467.pdf
----- Original Message -----
From: "Joseph Spicuzza" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, February 11, 2002 8:57 AM
Subject: [TN] timeline-Gantt chart
> Anyone have a sample timeline for ISO implementation.
> Been looking for this for days, still no luck. Thanks.
>
> Joseph Spicuzza
> Quality Assurance Manager
> Advanced Interconnect Products Division
> Compunetics, Inc.
> PH: 412 858-6166
> FX: 412 373-8060
> [log in to unmask]
>
> --------------------------------------------------------------------------
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Date: Mon, 11 Feb 2002 21:27:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dennis Fritz <[log in to unmask]>
Subject: Re: Plating Audit Template
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I have reprinted a recent posting from Conductor Analysis Technologies of
Albuquerque, New Mexico. They are in the business of analyzing test boards
from various board fabricators to determine capability. One of the criteria
from their analysis is microvias, and I think they can infer plating
uniformity from conductor thickness uniformity across a panel. They may have
Motorola available information already - I do not know if Motorola has asked
them to audit various board shops already.
The IPC-PCQR2 Committee also mentioned below is in the process of
standardizing test vehicles for capability of board fabrication shops around
the world. That committee has data on 15 shops so far, and is on the way to
30 data points by the time of IPC Expo at the end of March. Plating, and
especially microvia plating, is part of the capability vehicle.
Suggest you contact CAT about capabilities to qualify the plating at your
fabricators.
Denny Fritz
MacDermid
*****************************
Subj: Between The Conductors and CAT News Notes
Date: 1/7/02 7:04:32 PM Eastern Standard Time
From: [log in to unmask] (Timothy A. Estes)
To: [log in to unmask]
Between The Conductors
The current issue of Between the Conductors, a monthly technical publication
from Conductor Analysis Technologies, Inc., is now available at
www.cat-test.info <http://www.cat-test.info/> under the BTC link.
Title: The Impact of Copper Thickness on Quality - Part 2
Description: A discussion of the impact copper thickness on via quality and
reliability.
CAT News Notes
IPC-PCQR2 Free Seminar at APEX 2002
Date: January 22, 2002
Time: 3:15-6:15PM
Location: San Diego Convention Center
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Date: Mon, 11 Feb 2002 21:55:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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Hi Rudy
My favorite torture test is to run portions of a board through the 7 day
Moisture/Insulation Resistance test 95RH with cycling temperature and then
throw the coupons on a solder pot and section.
If it sticks together after that - and many do - it should take anything an
assembler or use environment could give.
Susan Mansilla
Robisan Lab
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Date: Tue, 12 Feb 2002 07:23:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solder spikes in wave soldering
X-To: Peter Lee <[log in to unmask]>
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First rule out solderability problems with the board or components. Is this
anomoly assoicated with one board or many boards, one component or many
components? Poor design can promote peaks.
Then, is this a new problem or a chronic problem? Many machine settings can
encourage formation of peaks. Preheat (both too high or too low) solder
temp too low, conveyor too fast, Solder contamination, flux contamination?
Insufficient flux. (spec gravity too low or foam head skips). Hope this
helps.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Lee
> Sent: Monday, February 11, 2002 8:04 PM
> To: [log in to unmask]
> Subject: [TN] Solder spikes in wave soldering
>
>
> Hello,
>
> What are the possible causes for solder spikes in wave soldering TH
> components. How would one trouble shoot such a defect?
>
>
> Rgds,
> Peter
>
>
>
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
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Date: Tue, 12 Feb 2002 08:20:02 -0500
Reply-To: [log in to unmask]
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From: Chris Christian <[log in to unmask]>
Subject: Re: Source for solder
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Indium Corporation of America has manufactured this alloy for many years
under the Indalloy#209 name.
Christine A. Christian
Sales Manager - Canada
Indium Corporation of America
Ph: +1 315 853-4900 X7572
Fx: +1 315 853-1000
Mobile: +1 315 796-0627
[log in to unmask]
www.indium.com
www.pb-free.com or www.SMQ230.com
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Monday, February 11, 2002 6:06 PM
To: [log in to unmask]
Subject: [TN] Source for solder
All
I am looking for a source for a solder named Motorola "J" solder.
Composition is
Sn65Ag25Sb10. I have scanned several company's product and they have do
not have it listed. If you have any leads let me know.
Phil Hiinton
[log in to unmask]
520-745-1013
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<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D670081913-12022002>Indium=20
Corporation of America has manufactured this alloy for many years under =
the=20
Indalloy#209 name.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D670081913-12022002></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D670081913-12022002>
<P><FONT size=3D2>Christine A. Christian<BR>Sales Manager - =
Canada<BR>Indium=20
Corporation of America<BR>Ph: +1 315 853-4900 X7572<BR>Fx: =
+1 315=20
853-1000<BR>Mobile: +1 315=20
796-0627<BR>[log in to unmask]<BR><BR>www.indium.com<BR>www.pb-free.co=
m or=20
www.SMQ230.com<BR>[log in to unmask]<BR><BR> </FONT> =
</P></SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Monday, February 11, 2002 6:06 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Source for=20
solder<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>All=20
<BR><BR>I am looking for a source for a solder named Motorola "J" =
solder.=20
Composition is <BR>Sn65Ag25Sb10. I have scanned several =
company's=20
product and they have do not have it listed. If you have any =
leads let=20
me know. <BR><BR>Phil Hiinton <BR>[log in to unmask] =
<BR>520-745-1013=20
</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Tue, 12 Feb 2002 07:32:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Here is the board buyers opportunity
MIME-Version: 1.0
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Susan Mansilla suggests:
My favorite torture test is to run portions of a board through the 7 day
Moisture/Insulation Resistance test 95RH with cycling temperature and then
throw the coupons on a solder pot and section.
Doug Pauls, well into his second Diet Dew of the day, adds:
I can imagine Susan cackling evilly as she throws the coupon on the molten
solder. What fun, but what a wimpy test. If you REALLY want to torture a
board, do the 7 day moisture test, immerse the coupon in liquid nitrogen
for 20 minutes, THEN throw it on the solder pot. Be sure to wear safety
goggles and avoid the flying shards of laminate. Now THAT's torturing the
board.
Doug Pauls
In the land of the absurd, I am royalty.
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Date: Tue, 12 Feb 2002 07:43:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Here is the board buyers opportunity
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Rudy,
One of the things I saw whilst at CSL was that we would sometimes see
corrosion on inner layer traces when they were placed very close to the
edge of a board. If the panels had been scored rather than routed, as was
the case, the mechanical flexing would open the edge of the laminate, or
the rough edge would allow moisture ingress, such that the inner layers
could corrode. So one thing I would look at would be the flexibility of
the oxide. I would also look at how well oxide coated inner traces, placed
near the edge of the board, resisted corrosion. If you are convinced that
the vendor has adequate inner layer cleanliness before lamination, then you
might want to use some external contaminant source, such as salt spray/fog
testing or some of the mixed flowing gas tests done at UL. Susan Mansilla
had a good test and would be dramatically faster and easier than the tests
I suggest, but probably would not address the corrosion issues.
The whole point of the inner layer oxide is protect the metal.
a. Does the oxide interfere with good plating in vias?
b. Does the oxide have sufficient flexibility to protect the metal in high
G or high shock environments?
c. Does the oxide have sufficient chemical resistance to protect the metal
against corrosive elements?
Doug Pauls
Rockwell Collins
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Date: Tue, 12 Feb 2002 08:02:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No Clean Process
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Christine,
In addition to the other suggestions you have had, let me suggest that you
get the Proceedings of IPC's First and Second Annual Conferences on No
Clean, held in 1993 and 1994. While some of that information is outdated
now, the approaches that many of the companies used to transition from
cleaning-based assembly processes to no-clean processes are still valid and
applicable today.
Doug Pauls
Rockwell Collins
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Date: Tue, 12 Feb 2002 09:41:47 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Black Nickle IN ENIG Article
MIME-Version: 1.0
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Clipped from the referenced PCFab site
http://www.pcfab.com/db_area/archive/2002/0202/toc.html ]
"A Key Failure Mode Resulting in Interfacial Fracture of Soldered ENIG
Surfaces" Ken Crouse and Don Cullen, PCFab, Feb 2002, V 25, No 2, p. 22-32
"Black-line nickel, a low-level defect of electroless nickel immersion gold,
goes undetected prior to assembly yet results in improperly formed solder
joints, causing opens. Here's how the phenomenon - often associated with
soldermask - occurs, and how to prevent it."
Dave Fish
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Date: Tue, 12 Feb 2002 11:50:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Here is the board buyers opportunity
MIME-Version: 1.0
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Doug,
I hope no one takes you literally - like the people who believed Dean Martin
when he said they could enter his "contest" by sending in the top of their
television set! He got, I think, somewhere between 8 and 12. Not believing
people could be that stupid, he had another "contest" and asked them to send
in the back of their piano. He got three.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: February 12, 2002 8:32 AM
To: [log in to unmask]
Subject: Re: [TN] Here is the board buyers opportunity
Susan Mansilla suggests:
My favorite torture test is to run portions of a board through the 7 day
Moisture/Insulation Resistance test 95RH with cycling temperature and then
throw the coupons on a solder pot and section.
Doug Pauls, well into his second Diet Dew of the day, adds:
I can imagine Susan cackling evilly as she throws the coupon on the molten
solder. What fun, but what a wimpy test. If you REALLY want to torture a
board, do the 7 day moisture test, immerse the coupon in liquid nitrogen
for 20 minutes, THEN throw it on the solder pot. Be sure to wear safety
goggles and avoid the flying shards of laminate. Now THAT's torturing the
board.
Doug Pauls
In the land of the absurd, I am royalty.
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Date: Tue, 12 Feb 2002 09:58:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Ochenas, Tom" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Ochenas, Tom" <[log in to unmask]>
Subject: requalification of expired flux-core solder
MIME-Version: 1.0
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This message is in MIME format. Since your mail reader does not understand
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Does anyone know of a method/standard for requalifying expired flux core
solder wire (62/36/2)?
The simpler the better...
Thanks In Advance,
Tom Ochenas
Process Engineering
Maxtek Components Corporation
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<P><FONT SIZE=2 FACE="Arial">Does anyone know of a method/standard for requalifying expired flux core solder wire (62/36/2)? </FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">The simpler the better...</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Thanks In Advance,</FONT>
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<P><FONT SIZE=2 FACE="Arial">Tom Ochenas</FONT>
<BR><FONT SIZE=2 FACE="Arial">Process Engineering</FONT>
<BR><FONT SIZE=2 FACE="Arial">Maxtek Components Corporation</FONT>
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Date: Tue, 12 Feb 2002 12:40:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Here is the board buyers opportunity
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Yah, Bev raises a good point. There might be a few out there who don't
recognize the ravings of an industry lunatic hyped up on caffeine for what
it truly is.
Soooooo, lets be clear, taking a material from -321F to 500F in an instant,
a thermal shock of 821F, is more than almost any polymeric material (or
most ceramics) could possibly handle, and so should NOT be done.
Unless of course you are looking for new and fun ways to destroy something,
or doing research in projectile motion, or have some LN2 you want to use
up........
Doug Pauls
The Count of Caffeine
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Date: Tue, 12 Feb 2002 14:54:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: High Frequency Effects
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi TechNet,
Last year the Class II requirements for solder fillet height on resistors
and capacitors was changed from requiring a fillet 1/4 way up the
termination (or 0.5 mm) to only requiring adequate wetting and evidence of a
good solder joint. As a result we are accepting a lot of solder joints that
were previously rejected and of course this concerns many. In particular
there seems to be the feeling among some that if they touch up a joint that
meets the new requirement but does not have much fillet height, then a
circuit pack can be made to pass test. They are proposing that in high
frequency applications (2.5 gigabits per second and above), the additional
solder volume is sufficient to improve the signal. Admittedly I am way out
of my league here, but I am skeptical and feel that the handling of the pack
and removal and insertion of fiber optics may be the actual cause of
acceptance. My question to the TechNet is whether it is possible to improve
performance for high speed signals if you add solder volume to a secure
connection? As always the input from this group is appreciated.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
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Date: Tue, 12 Feb 2002 14:16:53 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Yacovitch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Yacovitch <[log in to unmask]>
Subject: Re: BGAs on alternative finishes
X-To: [log in to unmask]
Steve,
IBM was the first to produce and deploy bare (exposed) copper into usage
amongst their products and customers/recipients of such. This is "old" news
and there are tons of quality data puhlished on bare copper reliability.
Most from IBM itself. One just need look. You'll get all the information
(bullets) you wll need to defend such.
Bill Y.
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Date: Tue, 12 Feb 2002 14:42:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Yacovitch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Yacovitch <[log in to unmask]>
Subject: Re: BGAs on alternative finishes
X-To: [log in to unmask]
Alan,
Boston Brad did a admirable job of explaining alternate surface finishes
and compatability. Especially from the PWB fabricators perspective.
From a specifier, and user, perspective which is where I am soming from I
can tell you the following:
- HASL is no longer a consideration and hasn't been since about 1992 when
it started showing it's ugly side in support of BGA flatness requirements.
The process lends itself to too much variation and operator intervention.
- OSP is a very good alternative, but along with it comes storage, shelf
life, and handling issues. Not to mention the customer perception of bare
copper. We have and still do use OSP's on a large portion of our products.
- ENIG (Electroless Nickel/Immersion Gold) otherwise known as eNi/iAu has
been the recent change in surface finish from OSP's in support of our newer
packaging technology requirements. Be forewarned however that the source
needs to have a robust and well controlled process with experience in this
finish. The Gold is self limiting and therefore is not the isse. It is the
plating of the nickel that can cause issues. Early on, "Black Pad" was the
nasty phrase and much to-do and research was embarked upon for root cause.
This issue is basically non-existant given a well controlled fabrication
process.
- ENIS (Electroless Nickel/Immersion Silver) is probably the next best
alternate surface finish. Note that Boston Brad responded about Immersion
Silver plated directly to Copper, removing the Nickel influence. I do not
have any experience with this, but I question the flatness without the
Nickel.
- Immersion Tin (White Tin) is also gaining ground.
I suggest you get a copy of the CCAMTF (Circuit Card Assembly Materials
Task Force) Phase 1 and 2 evaluations of Alternate Surface Finishes. This
membership includes 22 organizations and 35 individuals. Their two basic
goals are: 1) evaluate alternatives to fused tin-lead PWB surface finishes
and 2) develop guidelines for conformal coating usage. I believe that this
report will help you tremendously.
That's my three cents. Hope I was of some help.
Bill Y.
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Date: Tue, 12 Feb 2002 14:14:22 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Tue, 12 Feb 2002 15:11:39 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Rich, Barbara J" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Rich, Barbara J" <[log in to unmask]>
Subject: bga's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Does anyone have information on reliability issues that have been caused by
wave soldering a board that has BGA's without a fixture. Any information
will be helpful.
Thanks,
Barb Rich
Sr. Eng.Asst./Seritrack Support
Phone 303-661-8956
pgr.303.649.8366
INFORMATION made POWERFUL
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Date: Tue, 12 Feb 2002 18:25:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Hiteshew, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Hiteshew, Michael" <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
X-To: Rick Thompson <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain
Content-transfer-encoding: 7BIT
Rick,
What about the "old standby" RTV (Room Temperature Vulcanizing
silicone adhesive)? We use it all the time for just the applications you
stated. A good general purpose product is TSE392-C, available from GE
Silicones. Also, don't be afraid of seat-of-the-pants solutions. A piece of
22 awg solid copper tinned wire makes a great hold-down strap when mounted
across a component. Plus, it's easy to install. No trimming of insulation or
wire tinning required. Provide two holes (centered on the component and
located just beyond the max size of the part), solder in one side, thread
though the other hole and pull tight, then solder that side. Cheap and
effective. Great for a securing a component against shock. Used in tandem
with RTV (which has great vibration damping characteristics) it makes an
affordable and effective solution.
Michael Hiteshew
Lockheed Martin NE&SS Marine Systems
410-682-1259
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, February 12, 2002 5:14 PM
To: [log in to unmask]
Subject: [TN] Adhesive Recommendations?
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Wed, 13 Feb 2002 07:30:29 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: BGAs on alternative finishes
X-To: Bill Yacovitch <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi Bill,
Pls advice how the copy of of those evaluations.
best regards
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Bill Yacovitch [SMTP:[log in to unmask]]
> Sent: =E2 =F4=E1=F8=E5=E0=F8 12 2002 22:43
> To: [log in to unmask]
> Subject: Re: [TN] BGAs on alternative finishes
>=20
> Alan,
> I suggest you get a copy of the CCAMTF (Circuit Card Assembly =
Materials
> Task Force) Phase 1 and 2 evaluations of Alternate Surface Finishes. =
This
> membership includes 22 organizations and 35 individuals. Their two =
basic
> goals are: 1) evaluate alternatives to fused tin-lead PWB surface =
finishes
> and 2) develop guidelines for conformal coating usage. I believe that =
this
> report will help you tremendously.
>=20
> That's my three cents. Hope I was of some help.
>=20
> Bill Y.
>=20
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Date: Wed, 13 Feb 2002 09:33:41 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: requalification of expired flux-core solder
X-To: "Ochenas, Tom" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
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I didn't realise that cored solder had a sell-by or best-before date. I
found a reel of RA-flux cored solder that was at least 25 years old, a
few months ago. Other than the fact that the metal was somewhat
matte-looking, it looked OK, smelled OK and worked perfectly. I'm also
using at home a 10-year old reel of 1.5% (less than normal) rosin-cored
to DIN F-SW32 (halogen-free) and it works OK, within the limitations of
its characteristics.
I guess that if it tins some lightly tarnished copper with a soldering
iron at 300°C (which both above did/do), then you can use it!
Brian
> "Ochenas, Tom" wrote:
>
> Does anyone know of a method/standard for requalifying expired flux
> core solder wire (62/36/2)?
>
> The simpler the better...
>
> Thanks In Advance,
>
> Tom Ochenas
> Process Engineering
> Maxtek Components Corporation
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Date: Wed, 13 Feb 2002 08:21:18 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: bga's
X-To: "Rich, Barbara J" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Barbara,
I have information------don't do it.
A while ago I was faced with expensive boards that were failing bench test.
We could get them going temporarily by placing a finger on the bga
components. Since that firm didn't supply a test engineer's finger with
every product, the onus was on me to sort it.
Having measured the temperature underneath the bga during bottom side wave
soldering at about 180 Celsius I decided that we either mask the bga vias
comprehensively with peelable mask and use a jig or go double sided reflow.
In this particular case DSR was the answer with a few pin-in-holes thrown
in. The problem went away.
Hope this helps
Regards
Eric Dawson
> -----Original Message-----
> From: Rich, Barbara J [SMTP:[log in to unmask]]
> Sent: Tuesday, February 12, 2002 10:12 PM
> To: [log in to unmask]
> Subject: [TN] bga's
>
> Does anyone have information on reliability issues that have been caused
> by
> wave soldering a board that has BGA's without a fixture. Any information
> will be helpful.
>
> Thanks,
> Barb Rich
> Sr. Eng.Asst./Seritrack Support
> Phone 303-661-8956
> pgr.303.649.8366
> INFORMATION made POWERFUL
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
> -------
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Date: Wed, 13 Feb 2002 07:48:31 +0000
Reply-To: Roger Bilham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Bilham <[log in to unmask]>
Subject: Re: requalification of expired flux-core solder
In-Reply-To: <48359946794DD511BA3A00508BA5563F0ECE1A@MERCURY>
MIME-Version: 1.0
As a follow-up question, has anyone ever come across flux cored wire
which has become functionally defective through age? Provided that the
temperature isn't excessive and the outer layers of the wire are
protected from surface oxidation, cored wire should last almost
indefinitley, shouldn't it?
Roger Bilham
In article <48359946794DD511BA3A00508BA5563F0ECE1A@MERCURY>, Ochenas,
Tom <[log in to unmask]> writes
>
> Does anyone know of a method/standard for requalifying expired flux
> core solder wire (62/36/2)?
>
> The simpler the better...
>
> Thanks In Advance,
>
> Tom Ochenas
> Process Engineering
> Maxtek Components Corporation
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Wed, 13 Feb 2002 08:14:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
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Rick,
Way back in the very early seventies when I was working on research =
payloads for rockets we used (Dow Corning? GE?) 3140 and 3144 RTV. Now =
thirty years later we use Dow Corning RTV 737. It has good electrical =
characteristics, good moisture resistance and sticks like crazy. We buy =
it in 3 oz. tubes and 10.1 oz "caulking cartridges". For ease of =
dispensing we transfer from the 10.1 oz cartridge into 30cc syringes and =
then use 0.063" tip for fine application dispensing. The dispenser is =
air operated and the assemblers love it after having to fight with the =
half empty "tub caulk" size tube for years.
For instant gratification there are several clear RTV products available =
at the local hardware store that are used for general bonding and =
sealing. Like replacing those tiles in the bathroom that have come =
loose.
It isn't high tech but it has worked for many years.
Phil Nutting
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, February 12, 2002 5:14 PM
To: [log in to unmask]
Subject: [TN] Adhesive Recommendations?
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
-------------------------------------------------------------------------=
--------
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in
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> E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 =
ext.5315
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--------
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=========================================================================
Date: Wed, 13 Feb 2002 08:54:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Use caution if you buy a general purpose RTV at a hardware store. Many of
those products will be corrosive to electronics. If it smells like vinegar
when it cures it is no good for electronics. You must use an electronic
grade of RTV on boards. We use Dow Corning 3145 all the time for staking
with excellent results. We too transfer it to a syringe and use an EFD
dispenser.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> Sent: Wednesday, February 13, 2002 8:15 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
> For instant gratification there are several clear RTV products
> available at the local hardware store that are used for general
> bonding and sealing. Like replacing those tiles in the bathroom
> that have come loose.
>
> It isn't high tech but it has worked for many years.
---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 13 Feb 2002 09:20:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: requalification of expired flux-core solder
X-To: Roger Bilham <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Roger,
Yes, that is what I expect and that is what Brian Ellis has been able to
show through his own experience. If you want to be really, really
conservative, chop off the first 10 centimeters or so.
Also, what gives? I went to reply and it only put in Roger's e-mail address
and not Technet! Anybody else have this happen?
Bev Christian
Research in Motion
-----Original Message-----
From: Roger Bilham [mailto:[log in to unmask]]
Sent: February 13, 2002 2:49 AM
To: [log in to unmask]
Subject: Re: [TN] requalification of expired flux-core solder
As a follow-up question, has anyone ever come across flux cored wire
which has become functionally defective through age? Provided that the
temperature isn't excessive and the outer layers of the wire are
protected from surface oxidation, cored wire should last almost
indefinitley, shouldn't it?
Roger Bilham
In article <48359946794DD511BA3A00508BA5563F0ECE1A@MERCURY>, Ochenas,
Tom <[log in to unmask]> writes
>
> Does anyone know of a method/standard for requalifying expired flux
> core solder wire (62/36/2)?
>
> The simpler the better...
>
> Thanks In Advance,
>
> Tom Ochenas
> Process Engineering
> Maxtek Components Corporation
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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=========================================================================
Date: Wed, 13 Feb 2002 09:23:10 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_51.1906301f.299bd0ce_boundary"
--part1_51.1906301f.299bd0ce_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Rick!
We've got a board here that has some HUGE caps (3.25" tall. 1.25" diameter)
that we stake down to the board and to each other. Go to:
http://www.stevezeva.homestead.com and look at Big Blue Caps.
We use Dow Corning 732....works great for us.
-Steve Gregory-
> We have an application where we need to secure some vertically mounted
> radial electrolytic caps and a few other higher profile items to make
> them resistant to shock, impact and vibration (amusement park
> application). I've contacted Loctite and 3M for recommendations but the
> ones I've gotten have several week lead times, minimum buys due to
> special order, etc. Since we don't know if the products will work, we
> didn't want to buy minimum quantities of materials we can't return.
>
> Does anyone have any recommendations for standard products you may have
> used in similar situations? I realize I can get samples from the mfgs.
> Noted but I was hoping to shorten the lead time if I can find off the
> shelf products that may do the job.
>
> Thanks for your inputs.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
--part1_51.1906301f.299bd0ce_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Rick!
<BR>
<BR>We've got a board here that has some HUGE caps (3.25" tall. 1.25" diameter) that we stake down to the board and to each other. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com and look at Big Blue Caps.
<BR>
<BR>We use Dow Corning 732....works great for us.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">We have an application where we need to secure some vertically mounted
<BR>radial electrolytic caps and a few other higher profile items to make
<BR>them resistant to shock, impact and vibration (amusement park
<BR>application). I've contacted Loctite and 3M for recommendations but the
<BR>ones I've gotten have several week lead times, minimum buys due to
<BR>special order, etc. Since we don't know if the products will work, we
<BR>didn't want to buy minimum quantities of materials we can't return.
<BR>
<BR>Does anyone have any recommendations for standard products you may have
<BR>used in similar situations? I realize I can get samples from the mfgs.
<BR>Noted but I was hoping to shorten the lead time if I can find off the
<BR>shelf products that may do the job.
<BR>
<BR>Thanks for your inputs.
<BR>
<BR>
<BR>Rick Thompson
<BR>Ventura Electronics Assembly
<BR>2655 Park Center Dr.
<BR>Simi Valley, CA 93065
<BR>
<BR>+1 (805) 584-9858 x-304 voice
<BR>+1 (805) 584-1529 fax
<BR>[log in to unmask]
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_51.1906301f.299bd0ce_boundary--
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=========================================================================
Date: Wed, 13 Feb 2002 09:33:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Bob,
Oops, good point! That was one of the reasons we switched from GE =
RTV108 to Dow Corning 737 because 737 is a neutral cure and doesn't use =
acetic acid (that stinky foot smell) to cure. The acetic acid can do =
nasty things to bare copper during the cure cycle.
Let me retract my hardware store suggestion!
Phil
-----Original Message-----
From: bbarr [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 8:54 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
Use caution if you buy a general purpose RTV at a hardware store. Many =
of
those products will be corrosive to electronics. If it smells like =
vinegar
when it cures it is no good for electronics. You must use an electronic
grade of RTV on boards. We use Dow Corning 3145 all the time for staking
with excellent results. We too transfer it to a syringe and use an EFD
dispenser.
Bob
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> Sent: Wednesday, February 13, 2002 8:15 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
> For instant gratification there are several clear RTV products
> available at the local hardware store that are used for general
> bonding and sealing. Like replacing those tiles in the bathroom
> that have come loose.
>
> It isn't high tech but it has worked for many years.
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Date: Wed, 13 Feb 2002 10:08:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jerry Mosur <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jerry Mosur <[log in to unmask]>
Subject: Reflow Process
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello,
As a part of our preparations to set up an internal SMD line, I would like
to get your opinion on the following topic.
What are the problems, if any, associated with reflowing the double sided
SMT board using solder paste with different melting points for top and
bottom.
Is this a fairly common process?
If not what would you recommend as a best assembly process for double sided
SMT boards?
Thanks in advance,
Jerry
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Date: Wed, 13 Feb 2002 15:06:04 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: requalification of expired flux-core solder
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Tom,
I ran into this problem a few years ago - check the list archives. As I
recall, the consensus was the flux core was protected by the solder and
shouldn't expire. A down & dirty test could be to compare basic
solderability for the expired with in date flux-core wire. If the stuff
still wets, passes a pull test and can't be distinguished from in date
solder then you could "requalify" it. I'd be interested to hear what one of
the solder manufacturer's has to say about a requal procedure. It might be
more of a marketing tool, such as the "best used by" date on soda cans.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Roger Bilham [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 2:49 AM
To: [log in to unmask]
Subject: Re: [TN] requalification of expired flux-core solder
As a follow-up question, has anyone ever come across flux cored wire
which has become functionally defective through age? Provided that the
temperature isn't excessive and the outer layers of the wire are
protected from surface oxidation, cored wire should last almost
indefinitley, shouldn't it?
Roger Bilham
In article <48359946794DD511BA3A00508BA5563F0ECE1A@MERCURY>, Ochenas,
Tom <[log in to unmask]> writes
>
> Does anyone know of a method/standard for requalifying expired flux
> core solder wire (62/36/2)?
>
> The simpler the better...
>
> Thanks In Advance,
>
> Tom Ochenas
> Process Engineering
> Maxtek Components Corporation
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Wed, 13 Feb 2002 07:56:47 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bob Perkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Perkins <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
X-To: Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Rick
We are using the Dow 3145 RTV for a vibration protection application, I
know we are in an over stock situatiion right now, with an Expiry is
5/13/02. If you are interested we could have this out to you right away for
a very good price.
Bob Perkins
Aimtronics - Delta
SMT Process Engineering
[log in to unmask]
604-940-5788
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, February 12, 2002 2:14 PM
To: [log in to unmask]
Subject: [TN] Adhesive Recommendations?
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Wed, 13 Feb 2002 07:57:28 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bob Perkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Perkins <[log in to unmask]>
Subject: Recall: [TN] Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: text/plain
Bob Perkins would like to recall the message, "[TN] Adhesive
Recommendations?".
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Date: Wed, 13 Feb 2002 07:58:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chuck Brummer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Here is the board buyers opportunity
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Doug,
I thought the purpose of inner layer oxide was to increase the bond between the copper and the epoxy.
The epoxy itself should protect the copper from corosion. Have I been wrong all these years. Why did I
do all those bond tests on oxides with different crystal structures?
Chuck Brummer
[log in to unmask] wrote:
> Rudy,
> One of the things I saw whilst at CSL was that we would sometimes see
> corrosion on inner layer traces when they were placed very close to the
> edge of a board. If the panels had been scored rather than routed, as was
> the case, the mechanical flexing would open the edge of the laminate, or
> the rough edge would allow moisture ingress, such that the inner layers
> could corrode. So one thing I would look at would be the flexibility of
> the oxide. I would also look at how well oxide coated inner traces, placed
> near the edge of the board, resisted corrosion. If you are convinced that
> the vendor has adequate inner layer cleanliness before lamination, then you
> might want to use some external contaminant source, such as salt spray/fog
> testing or some of the mixed flowing gas tests done at UL. Susan Mansilla
> had a good test and would be dramatically faster and easier than the tests
> I suggest, but probably would not address the corrosion issues.
>
> The whole point of the inner layer oxide is protect the metal.
> a. Does the oxide interfere with good plating in vias?
> b. Does the oxide have sufficient flexibility to protect the metal in high
> G or high shock environments?
> c. Does the oxide have sufficient chemical resistance to protect the metal
> against corrosive elements?
>
> Doug Pauls
> Rockwell Collins
>
> ---------------------------------------------------------------------------------
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Date: Wed, 13 Feb 2002 11:02:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
X-To: bbarr <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I wondered if anyone was going to caution the group on this fact. I have
seen RTV damage the printed circuit right through solder mask.
The other thing I have observed is that it isn't that good at absorbing
shock. If you hit it hard it can simply tear or worse bounce and actually
return energy to the component.
I think in the context originally described in this thread, used in
conjunction with a wire hold down, it may be okay.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> Sent: Wednesday, February 13, 2002 8:54 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
>
> Use caution if you buy a general purpose RTV at a hardware store. Many of
> those products will be corrosive to electronics. If it smells like vinegar
> when it cures it is no good for electronics. You must use an electronic
> grade of RTV on boards. We use Dow Corning 3145 all the time for staking
> with excellent results. We too transfer it to a syringe and use an EFD
> dispenser.
>
> Bob
>
> =======================
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> > Sent: Wednesday, February 13, 2002 8:15 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations?
>
> >
> > For instant gratification there are several clear RTV products
> > available at the local hardware store that are used for general
> > bonding and sealing. Like replacing those tiles in the bathroom
> > that have come loose.
> >
> > It isn't high tech but it has worked for many years.
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>
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Date: Wed, 13 Feb 2002 10:01:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Adhesive Recommendations?
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
I'll weigh in on this issue since I've been wrestling with it quite a bit
in recent weeks.
The DC3140 silicone needs a primer to get the full adhesion on the data
sheets. It is a self leveling material so expect it to flow away from
where you put it. The DC3145 material is thicker (stays put) and needs no
primer. Both of these materials evolve alcohol when they cure, as opposed
to acetic acid. The silicones that evolve acetic acid are not suitable for
electronics.
Both of these materials are moisture cure materials. The thicker the
material, the longer it takes to cure. It also cures from the outside in,
so the surface skins over first. Cured silicone resists moisture flowing
through it, so it takes progressively longer to cure the farthest portions
of the silicone mass. For thicknesses in the 0-0.2" range, figure on 24
hours of ambient cure time at a minimum. You can accelerated the cure
using a humidity chamber, but you can sometimes get bubbles forming in the
silicone mass when the alcohol cannot get through the skinned over surface.
Consequently, you have a silicone mass that has lower tensile strength and
lower dielectric properties. We used these materials on some of our RF
components and the bubbles in the silicone lead to arcing and corona in
high power applications.
Because of the long cure times, we are currently investigating thermally
cured epoxy and urethane materials that cure in 30 - 60 minutes and which
don't have the incompatibilities with acrylic conformal coat that silicones
do.
Doug Pauls
Rockwell Collins
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Date: Wed, 13 Feb 2002 08:20:18 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dyane White <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
X-To: Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Rick,
Our company uses hot melt glue with glue guns and glue sticks. Works great!
Rick Thompson
<rthompson@VENTURAELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: Dyane White/ATL-BTL/MS/PHILIPS)
Sent by: TechNet Subject: [TN] Adhesive Recommendations?
<[log in to unmask]>
Classification:
02/12/02 02:14 PM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Wed, 13 Feb 2002 11:20:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bartkowaik Christine <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bartkowaik Christine <[log in to unmask]>
Subject: Re: Reflow Process
X-To: Jerry Mosur <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jerry:
I use the same paste and profile to build double-sided boards with no
problems.
The side with the "lighter" componets is built first.
Chris
-----Original Message-----
From: Jerry Mosur [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 10:09 AM
To: [log in to unmask]
Subject: [TN] Reflow Process
Hello,
As a part of our preparations to set up an internal SMD line, I would like
to get your opinion on the following topic.
What are the problems, if any, associated with reflowing the double sided
SMT board using solder paste with different melting points for top and
bottom.
Is this a fairly common process?
If not what would you recommend as a best assembly process for double sided
SMT boards?
Thanks in advance,
Jerry
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Date: Wed, 13 Feb 2002 11:52:31 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Chris Christian <[log in to unmask]>
Subject: Re: Reflow Process
X-To: Jerry Mosur <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi,
In the early days of SMT, many people tried lower melting point temp solders
on the second side. It is common practice now to use the Sn/Pb eutectic on
both sides relying on surface tension to hold the components. I personally
do not know of anyone using 2 different melting point solders on
double-sided boards these days. In order to attain lower melting points,
one must use a bismuth-containing alloy. Customers were not happy with the
less than shiny joints.
Chris Christian
Indium Corporation of America
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Wednesday, February 13, 2002 10:09 AM
To: [log in to unmask]
Subject: [TN] Reflow Process
Hello,
As a part of our preparations to set up an internal SMD line, I would like
to get your opinion on the following topic.
What are the problems, if any, associated with reflowing the double sided
SMT board using solder paste with different melting points for top and
bottom.
Is this a fairly common process?
If not what would you recommend as a best assembly process for double sided
SMT boards?
Thanks in advance,
Jerry
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Date: Wed, 13 Feb 2002 08:57:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Ochenas, Tom" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Ochenas, Tom" <[log in to unmask]>
Subject: Re: requalification of expired flux-core solder
MIME-Version: 1.0
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Profuse thanks to all who replied to my query; your input was extremely
helpful!
The brain power that is accessible through TechNet is truly awesome...
Best Regards,
Tom Ochenas
------_=_NextPart_001_01C1B4AF.7753C660
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<TITLE>RE: [TN] requalification of expired flux-core solder</TITLE>
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<P><FONT SIZE=2>Profuse thanks to all who replied to my query; your input was extremely helpful!</FONT>
</P>
<P><FONT SIZE=2>The brain power that is accessible through TechNet is truly awesome...</FONT>
</P>
<P><FONT SIZE=2>Best Regards,</FONT>
<BR><FONT SIZE=2>Tom Ochenas</FONT>
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Date: Wed, 13 Feb 2002 09:16:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Miguel Vallejo <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Miguel Vallejo <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
To expand a bit in the transfering-to-the-syrenge technique, we fill and
re-fill the syringe through the tip of the syringe--rather than from the
top--to keep air bubbles out of the cylinder, thus minimizing turn-over of
syringes due to dried out left over, and maximizing the working life of the
RTV in the syringe:
1. using a caulking cartridge and gun, cut off the tip of the cartridge so
that the opening is slightly smaller than the nipple of the syringe(the
piece that goes inside the needle).
2. With the piston in the bottom of the cylinder, insert the nipple of the
syringe to the tip of the cartridge.
3. While holding the syringe with one hand, actuate the caulking gun to
release the RTV. The RTV will push up the piston as it fills the cylinder.
4. If any air is trapped between the RTV and the piston, it can be purged by
pushing the piston down while the exit of the syringe is shut (as
recommended by some air dispensing units).
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 6:33 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
Bob,
Oops, good point! That was one of the reasons we switched from GE RTV108 to
Dow Corning 737 because 737 is a neutral cure and doesn't use acetic acid
(that stinky foot smell) to cure. The acetic acid can do nasty things to
bare copper during the cure cycle.
Let me retract my hardware store suggestion!
Phil
-----Original Message-----
From: bbarr [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 8:54 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
Use caution if you buy a general purpose RTV at a hardware store. Many of
those products will be corrosive to electronics. If it smells like vinegar
when it cures it is no good for electronics. You must use an electronic
grade of RTV on boards. We use Dow Corning 3145 all the time for staking
with excellent results. We too transfer it to a syringe and use an EFD
dispenser.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> Sent: Wednesday, February 13, 2002 8:15 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
> For instant gratification there are several clear RTV products
> available at the local hardware store that are used for general
> bonding and sealing. Like replacing those tiles in the bathroom
> that have come loose.
>
> It isn't high tech but it has worked for many years.
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Date: Wed, 13 Feb 2002 10:28:31 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Reflow Process
X-To: Jerry Mosur <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative; boundary="=_alternative 005FDDFE87256B5F_="
This is a multipart message in MIME format.
--=_alternative 005FDDFE87256B5F_=
Content-Type: text/plain; charset="us-ascii"
Jerry,
Check out this article http://www.aimsolder.com/techarticles/reflow.htm ,which describes "step soldering" and may answer some of what you are
inquiring about.
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
Jerry Mosur <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
02/13/02 08:08 AM
Please respond to "TechNet E-Mail Forum."; Please respond to Jerry Mosur
To: [log in to unmask]
cc:
Subject: [TN] Reflow Process
Hello,
As a part of our preparations to set up an internal SMD line, I would like
to get your opinion on the following topic.
What are the problems, if any, associated with reflowing the double sided
SMT board using solder paste with different melting points for top and
bottom.
Is this a fairly common process?
If not what would you recommend as a best assembly process for double
sided
SMT boards?
Thanks in advance,
Jerry
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Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Jerry,</font>
<br>
<br><font size=2 face="sans-serif">Check out this article </font><a><font size=2 color=blue face="sans-serif">http://www.aimsolder.com/techarticles/reflow.htm</font></a><font size=2 face="sans-serif"> ,which describes "step soldering" and may answer some of what you are inquiring about.</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>Jerry Mosur <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">02/13/02 08:08 AM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."; Please respond to Jerry Mosur</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: [TN] Reflow Process</font></table>
<br>
<br>
<br><font size=2 face="Courier New">Hello,<br>
<br>
As a part of our preparations to set up an internal SMD line, I would like<br>
to get your opinion on the following topic.<br>
What are the problems, if any, associated with reflowing the double sided<br>
SMT board using solder paste with different melting points for top and<br>
bottom.<br>
Is this a fairly common process?<br>
If not what would you recommend as a best assembly process for double sided<br>
SMT boards?<br>
<br>
<br>
Thanks in advance,<br>
<br>
Jerry<br>
<br>
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Date: Wed, 13 Feb 2002 12:31:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Raymond <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Inspecting Wavesoldered bottom-side SMD joints
Hi all,
I'm using a wave solder system with a hot air knife... the knife
reduces solder shorts just fine, however, the inspectors are finding "more"
insufficient solder joints. I've read articles _somewhere_, that when
using a hot air knife system, the joints will tend to look different and
that inspectors will need to be retrained as to what to look for. Can
anyone point me to a source of information??
Thanks, Bill...
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Date: Wed, 13 Feb 2002 12:44:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Some more free stuff on Seth's ftp site
Folks,
I posted some more stuff mostly as presentations on Seth's site
(ftp.GoodmanAssociates.com). Just log on anonomously and take what you will.
Ioan, your push to pull Lean presentation is there as well.
Also want to mention TI, myself, and other members of our little group, had
a fruitful discussion about our about to end flip chip DSP assembly and
quality issues. Two more weeks and will have proof one way or another. I'll
keep you all posted.
MoonMan
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Date: Wed, 13 Feb 2002 14:15:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Assembled Backplane Testing Definitions / Specifications
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Technetters,
Does anyone know of any specifications that define the electrical testing
levels for an assembled backplane?
What I have always used as a definition is:
Level 1. Top Side Pin to Bottom Side hole continuity is tested.
Level 2. Level 1 plus Pin to Pin continuity is tested.
Level 3. Level 2 plus all components are tested for correct values
Level 4. Level 2 and 3 plus all active devices (IC's, etc.) are tested.
I have looked in the IPC bookstore and did not see anything (probably
looking in the wrong spot).
Would appreciate any and all comments.
Thanks,
Kerry
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Date: Wed, 13 Feb 2002 15:10:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Some more free stuff on Seth's ftp site
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Consider posting these files in a zip format
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 13, 2002 10:44 AM
Subject: [TN] Some more free stuff on Seth's ftp site
> Folks,
>
> I posted some more stuff mostly as presentations on Seth's site
> (ftp.GoodmanAssociates.com). Just log on anonomously and take what you
will.
>
> Ioan, your push to pull Lean presentation is there as well.
>
>
> Also want to mention TI, myself, and other members of our little group,
had
> a fruitful discussion about our about to end flip chip DSP assembly and
> quality issues. Two more weeks and will have proof one way or another.
I'll
> keep you all posted.
>
> MoonMan
>
> --------------------------------------------------------------------------
-------
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SET Technet NOMAIL
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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Date: Wed, 13 Feb 2002 14:15:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Carl Ray <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl Ray <[log in to unmask]>
Subject: Preferred Probes for No Clean Processes
X-To: test techcouncil <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I need some feedback as to what types of test probes are preferred for
No Clean Processes? Need to know for probing vias, pads and test points.
Also product that has been wave soldered and double sided reflow.
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Date: Wed, 13 Feb 2002 14:43:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Some more free stuff on Seth's ftp site
X-To: [log in to unmask]
Dave,
Though I responded off line, I should have explained here the files don't
compress much more as most of the stuff is .jpg already. 4% is about it. I
hope this doesn't inconvenience folks too much.
Also, the presentations are a bit vague without a presenter. I'm not in need
of a vacation from my contract yet but, when I am, I'll accept anyone's kind
offer to give them one and all - free of charge but for expenses.
Please note, this in no way is a solicitation. I just like doing it but am
very poor, as a cave dwelling type, and don't want to hole up in a swank,
palacial place out of my pocket.
MoonMan
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Date: Wed, 13 Feb 2002 14:42:47 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Foote, Jeffery" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Foote, Jeffery" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Anyone,
I am looking for some information regarding the preparation of copper foil
for adhesion to internal laminate layers in the construction of PWBs. I am
presently experiencing delamination of the copper from the laminate prepreg
on an internal layer after IR reflow exposure. EDS of the delaminated
surfaces showed localized, high-concentration of sulfur and tin on the
copper surface. What types of chemistry or processes are used for the
preparation of the copper surface before bonding to the laminate. The
delamination is occurring between the electroplated copper and the laminate.
Best Regards
Jeff Foote
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Date: Wed, 13 Feb 2002 18:33:18 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Delamination
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 2/13/02 2:58:07 PM Pacific Standard Time, [log in to unmask]
writes:
<< I am looking for some information regarding the preparation of copper foil
for adhesion to internal laminate layers in the construction of PWBs. I am
presently experiencing delamination of the copper from the laminate prepreg
on an internal layer after IR reflow exposure. EDS of the delaminated
surfaces showed localized, high-concentration of sulfur and tin on the
copper surface >>
Jeff: I assume that this delamination is occuring adjacent to drilled holes?
These are not buried via boards are they?
Rudy Sedlak
RD Chemical Company
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Date: Wed, 13 Feb 2002 17:52:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: 0201 Report available; proceeds to charity
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: multipart/alternative; boundary="=_E7BABC25.90F19636"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_E7BABC25.90F19636
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
The review below was prepared by SMTA and covers an informative report on =
use of 0201 components. International purchasers can contact Bob at his =
address below; North American purchasers contact SMTA at 952-920-7682.
We extend a special thanks to Bob Willis, Electronic Presentation =
Services, the SMART Group, and all contributors to the report for this =
effort.
Cordially
Jack
>>> "Bob Willis" <[log in to unmask]> 02/13/02 02:05PM >>>
Jack and feedback on the 0201 Charity report and any coverage IPC can give =
it. As I said before the money is going to the Red Cross September 11th =
Appeal. I know you passed the email on for comment but I did not see =
response.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
0201 Chip Component Design, Assembly and Soldering Guide
SMART Group (UK)
The continued need for miniaturization at component and board level =
assembly has seen the move to 0201 chip components. Consideration is also =
being given to the design and manufacture of the next level of chip =
component. This report is one of the SMART Group Charity Reports produced =
due to the need for practical information. They have covered the existing =
material in the industry, including reports of current projects and recent =
seminars on the subject.
The 0201 report contents include 0201 Chip Component Trends, Printed Board =
Layout, Solder Paste Stencil, Design of Apertures and Recommendations, =
Printing Solder Paste, Component Placement, Component Packaging, Reflow =
Soldering, Effects of Nitrogen, Temperature Profiling Boards, Visual =
Inspection, X-Ray Images, Process Defects, Rework and Repair, Existing =
Process Trial Results, and an 0201 Technical Bibliography. Authors include =
Angus Westwater, ROHM; Peter Grundy, Siemens PLC; Malcolm Warwick, =
Loctite/Multicore; Bruce Seaton, Speedline Technologies; Simon Hawkins, OK =
Industries; and Bob Willis, Electronic Presentations Services.
The full report is over 50 pages long including pictures and diagrams and =
is provided on CD-ROM. The CD also includes an 0201 processing specific =
photo album of components, printing, reflowed joints, x-ray examples and =
defective joints. This makes an ideal resource for training engineers. The =
photographs may be used royalty free. A further feature is a number of =
video clips showing reflow of 0201, component movement/lifting and =
tombstoning. There are also clips showing 0201 rework which can be =
incorporated into PowerPoint presentations and used in seminar presentation=
s and training workshops.
The SMART Group, its committee and members would like to offer the money =
raised from the sale of this report to support those affected by the =
events on 11th, September 2001, in the USA. All proceeds will go to the =
Salvation Army September 11 Fund. 50 pages, 2002, SMART Group.
--=_E7BABC25.90F19636
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1></FONT>The review below was prepared by SMTA and =
covers an=20
informative report on use of 0201 components. International purchasers =
can=20
contact Bob at his address below; North American purchasers contact SMTA =
at=20
952-920-7682.</DIV>
<DIV> </DIV>
<DIV>We extend a special thanks to Bob Willis, Electronic Presentation=20
Services, the SMART Group, and all contributors to the report for =
this=20
effort.</DIV>
<DIV> </DIV>
<DIV>Cordially</DIV>
<DIV>Jack<BR><BR>>>> "Bob Willis" <[log in to unmask]> =
02/13/02=20
02:05PM >>><BR></DIV>
<DIV><FONT face=3DArial size=3D2>Jack and feedback on the 0201 Charity =
report and=20
any coverage IPC can give it. As I said before the money is going to the =
Red=20
Cross September 11th Appeal. I know you passed the email on for comment =
but I=20
did not see response.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Bob Willis<BR>Electronic Presentation =
Services<BR>2=20
Fourth Ave, Chelmsford, Essex, CM1 4HA England<BR><A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245=20
351502 Fax: (44) 01245 496123</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>0201 Chip Component Design, Assembly and Soldering Guide<BR>SMART =
Group=20
(UK)</DIV>
<DIV> </DIV>
<DIV><BR>The continued need for miniaturization at component and board =
level=20
assembly has seen the move to 0201 chip components. Consideration is also =
being=20
given to the design and manufacture of the next level of chip component. =
This=20
report is one of the SMART Group Charity Reports produced due to the need =
for=20
practical information. They have covered the existing material in the =
industry,=20
including reports of current projects and recent seminars on the subject.</=
DIV>
<DIV><BR>The 0201 report contents include 0201 Chip Component Trends, =
Printed=20
Board Layout, Solder Paste Stencil, Design of Apertures and Recommendations=
,=20
Printing Solder Paste, Component Placement, Component Packaging, Reflow=20
Soldering, Effects of Nitrogen, Temperature Profiling Boards, Visual =
Inspection,=20
X-Ray Images, Process Defects, Rework and Repair, Existing Process =
Trial=20
Results, and an 0201 Technical Bibliography. Authors include Angus =
Westwater,=20
ROHM; Peter Grundy, Siemens PLC; Malcolm Warwick, Loctite/Multicore; =
Bruce=20
Seaton, Speedline Technologies; Simon Hawkins, OK Industries; and Bob =
Willis,=20
Electronic Presentations Services.</DIV>
<DIV><BR>The full report is over 50 pages long including pictures and =
diagrams=20
and is provided on CD-ROM. The CD also includes an 0201 processing =
specific=20
photo album of components, printing, reflowed joints, x-ray examples =
and=20
defective joints. This makes an ideal resource for training engineers. =
The=20
photographs may be used royalty free. A further feature is a number of =
video=20
clips showing reflow of 0201, component movement/lifting and tombstoning. =
There=20
are also clips showing 0201 rework which can be incorporated into =
PowerPoint=20
presentations and used in seminar presentations and training workshops.</DI=
V>
<DIV><BR>The SMART Group, its committee and members would like to offer =
the=20
money raised from the sale of this report to support those affected by =
the=20
events on 11th, September 2001, in the USA. All proceeds will go to the=20
Salvation Army September 11 Fund. 50 pages, 2002, SMART=20
Group.</DIV></BODY></HTML>
--=_E7BABC25.90F19636--
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Date: Thu, 14 Feb 2002 08:35:24 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Upside down chip resistors
X-To: Mel Parrish <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Mell,
I'll throw a little fat into your new fire with few discussion questions:
Was the "Right way up vs. wrong way up reliability testing" carried out by
assembling virgin components the right way up and the wrong way up
intentionally and . i.e. the test pieces were not re-worked to produce the
test orientations?
If the answer to the above is Yes, the results are interesting and should
be noted - fit the resistors the right way up first time for maximum
reliability.
However, are there any similar, comparative test results of long term
reliability for components that are fitted the right way up only after they
were re-worked to make them the right way up? Are they still more reliable
than if they were left the wrong way up and undisturbed?
Peter
Mel Parrish
<mparrish@SOLDERIN To: [log in to unmask]
GTECH.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Upside down chip resistors
02/09/02 09:22 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Mel
Parrish
Agree with MoonMan, but for discussion, this criteria was included in the
standards some time ago and was a carry over from the Mil Specs. The
testing
was accomplished then to determine if there was justification to consider
orientation of these components. The tests for a particular program proved
that there was a very significant increase in component operational life if
the component was face up.
We didn't look at the "why" although there was speculation concerning
entrapment of process chemistries, or thermal issues for the film close to
the board.
IPC-A-610C calls this a Process Indicator for Class 2 and 3 which wouldn't
support rework. If the long term reliability of the component was a
concern, you might look at effective methods to correct it (not point to
point soldering). Best option is to orient up if it by process if
required.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, February 08, 2002 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Upside down chip resistors
The less rework, the better. When replacing or reworking any chip device,
using hand soldering techniques, chances are damage will ensue.
MoonMan
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Date: Thu, 14 Feb 2002 08:45:03 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Pull strength on soldered clip
X-To: Peter Lee <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Peter,
If you have the space to do it, I would suggest increasing the pad size to
about 0.265" square, or, if not, reducing the clip contact area
correspondingly so that you can obtain heel, toe and side solder fillets.
Without these, you are producing stress concentration points that will in
turn cause low peel strength.
Peter
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Pull strength on soldered clip
<[log in to unmask]
ORG>
02/09/02
04:17 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Peter Lee
Hello,
I ran into an application requiring SMT reflow soldering of a small
copper clip to a pad. The resulting solder joint was so weak that a
slight pull on the overhanging lip will rip off the entire clip from the
pad. I examined the mating surfaces afterwards and both were still
solderable.
The 0.005" thick clip has a flat 1/4"x1/4" surface which was placed
right on top of the pad with the same size. Stencil aperture is 1:1 and
both the pad and clip have good solderability (before and after). The
rest of the components on the boards are soldered well. I like to know
if there is a way to determine how much pull strength should I expect
with such design? In order to strengthen the solder joint, does it make
sense to increase the size of the pad to ensure wetting on the edge and
force excess solder to flow on top of the clip?
Any advice is appreciated.
Rgds,
Peter
_________________________________________________________
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Date: Thu, 14 Feb 2002 06:27:33 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Prasad An <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Prasad An <[log in to unmask]>
Subject: Re: Flux Testing using Titration
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Rudy
We are using Cookson make No clean flux RF-800.Currently we are measuring
the specific gravity of the flux using Density meter.But I would like to
measure thru the titration method.Sujjest me the procedure for using the
titration method.
A.N.Prasad
Flextronics Technologies (I) Ltd.,
Bangalore, India
email:[log in to unmask]
* Flextronics Internal Use *
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, February 11, 2002 9:02 PM
To: [log in to unmask]
Subject: Re: [TN] Flux Testing using Titration
If you vendor will not give you a procedure..
Send me (off-line) your current procedure...
and I will work up a method, and send it to you.
Key issues needed to do this are:
Name of indicator...is flux water based, and do you add water during
testing?
Rudy Sedlak ([log in to unmask])
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Date: Thu, 14 Feb 2002 09:49:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Adhesive Recommendations?
X-To: Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Rick,
I've recommended Eccobond 45 to a number of people for securing components
to substrates for use in hostile environments. In my last company it was
used in military radars where 15g accecerations and very high vibration
levels were breaking not-a-few component leads. The Eccobond proved to be a
successful solution. Don't know about lead times or MOQ's though.
Peter
Rick Thompson
<rthompson@VENTURAELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Adhesive Recommendations?
02/13/02 06:14 AM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Thu, 14 Feb 2002 10:25:53 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Adhesive Recommendations? Silicon??
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, All,
I'm still trying to reconcile all the continued use of silicon adhesives
(as recommended by several learned members of this forum) with all the
learned discussion about how terrible it is to put silicon anywhere near
boards because of contamination issues. Is anyone prepared to put his/her
neck on the line and try for a definitive statement on this issue - is
silicon on boards good, OK or bad? If it's bad, why are so many still doing
it? Is it Force Majeur, are there no alternatives, or is there a mysterious
land out there where the use of silicon is not detrimental and the benefits
are worth having? Which land is this?
Peter
Phil Nutting
<PNutting@KAISERSY To: [log in to unmask]
STEMS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Adhesive Recommendations?
02/13/02 09:14 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Phil
Nutting
Rick,
Way back in the very early seventies when I was working on research
payloads for rockets we used (Dow Corning? GE?) 3140 and 3144 RTV. Now
thirty years later we use Dow Corning RTV 737. It has good electrical
characteristics, good moisture resistance and sticks like crazy. We buy it
in 3 oz. tubes and 10.1 oz "caulking cartridges". For ease of dispensing
we transfer from the 10.1 oz cartridge into 30cc syringes and then use
0.063" tip for fine application dispensing. The dispenser is air operated
and the assemblers love it after having to fight with the half empty "tub
caulk" size tube for years.
For instant gratification there are several clear RTV products available at
the local hardware store that are used for general bonding and sealing.
Like replacing those tiles in the bathroom that have come loose.
It isn't high tech but it has worked for many years.
Phil Nutting
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, February 12, 2002 5:14 PM
To: [log in to unmask]
Subject: [TN] Adhesive Recommendations?
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Thu, 14 Feb 2002 07:36:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I can recall a recent program we ran here where a large radial leaded cap
that was bonded to a circuit board with RTV 3140 had broken leads after
going through qualification vibe. So I can second Guy Ramsey's observation
about components bouncing. We ended up changing to a soft epoxy with a low
CTE and the bonded parts survived quite nicely. We were quite surprised at
the difference in characteristics when we vibe tested fully instrumented
components with different bonding materials and applications. We found that
the soft epoxy worked the best. Please note that our performance
requirements superceded any priority that related to the time to prepare,
apply and cure the epoxy. So, I'm not suggesting that this method is fast
and easy, it's probably the opposite.
Bill Kasprzak
Moog Inc. Manufacturing Engineering, Electronics
> -----Original Message-----
> From: Guy Ramsey [SMTP:[log in to unmask]]
> Sent: Wednesday, February 13, 2002 11:02 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
> I wondered if anyone was going to caution the group on this fact. I have
> seen RTV damage the printed circuit right through solder mask.
>
> The other thing I have observed is that it isn't that good at absorbing
> shock. If you hit it hard it can simply tear or worse bounce and actually
> return energy to the component.
>
> I think in the context originally described in this thread, used in
> conjunction with a wire hold down, it may be okay.
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> > Sent: Wednesday, February 13, 2002 8:54 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations?
> >
> >
> > Use caution if you buy a general purpose RTV at a hardware store. Many
> of
> > those products will be corrosive to electronics. If it smells like
> vinegar
> > when it cures it is no good for electronics. You must use an electronic
> > grade of RTV on boards. We use Dow Corning 3145 all the time for staking
> > with excellent results. We too transfer it to a syringe and use an EFD
> > dispenser.
> >
> > Bob
> >
> > =======================
> > Robert Barr
> > Manufacturing Engineering
> > Formation, Inc.
> > Voice: 856-234-5020 x3035
> > Fax: 856-234-6679
> >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> > > Sent: Wednesday, February 13, 2002 8:15 AM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] Adhesive Recommendations?
> >
> > >
> > > For instant gratification there are several clear RTV products
> > > available at the local hardware store that are used for general
> > > bonding and sealing. Like replacing those tiles in the bathroom
> > > that have come loose.
> > >
> > > It isn't high tech but it has worked for many years.
> >
> > ------------------------------------------------------------------
> > ---------------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
> in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> > Search previous postings at: www.ipc.org > On-Line Resources &
> > Databases > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > ------------------------------------------------------------------
> > ---------------
> >
>
> --------------------------------------------------------------------------
> -------
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Date: Thu, 14 Feb 2002 07:51:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Adhesive Recommendations? Silicon??
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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The answer to your question is.......it depends. (How's that for not
sticking my neck out?) As long as you use electronic grade silicone (RTV) as
I mentioned in my previous post, then there is nothing in the material that
will harm your board. Heck, when I was involved in building high voltage
power supplies for military applications we potted the entire board in
silicone to prevent coronal discharge (also known as lightning.) Silicone
conformal coating is actually quite popular for certain applications.
However, what I think you are referring to as far as contamination is when a
board has to be conformal coated or potted with another material. In that
situation, any silicone on the board will prevent adhesion of the coating so
one must be very conscience of contamination issues. So, like most things in
life, there is no absolute here. It all depends on your requirements,
compatibility to the rest of the process and your individual process
controls.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of
> [log in to unmask]
> Sent: Wednesday, February 13, 2002 9:26 PM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations? Silicon??
>
>
> Hi, All,
>
> I'm still trying to reconcile all the continued use of silicon adhesives
> (as recommended by several learned members of this forum) with all the
> learned discussion about how terrible it is to put silicon anywhere near
> boards because of contamination issues. Is anyone prepared to put his/her
> neck on the line and try for a definitive statement on this issue - is
> silicon on boards good, OK or bad? If it's bad, why are so many
> still doing
> it? Is it Force Majeur, are there no alternatives, or is there a
> mysterious
> land out there where the use of silicon is not detrimental and
> the benefits
> are worth having? Which land is this?
>
> Peter
>
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=========================================================================
Date: Thu, 14 Feb 2002 08:40:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Management forum?
MIME-Version: 1.0
Content-Type: text/plain
Hi,
following the largely appreciated effort from the Moonman to distribute some
knowledge to the masses, I started wondering if there is any on-line
management forum, preferably applied to the electronics industry. Nothing of
the kind with IPC, unfortunately. Any leads?
Thanks Moonman,
thanks everybody,
Ioan
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Date: Thu, 14 Feb 2002 08:44:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Standards for testing
MIME-Version: 1.0
Content-Type: text/plain
Hi again,
is there any IPC standard, or any standard, covering ICT, functional and
system testing?
What I'm looking for are some guidelines on:
* how to decide what tests are necessary according to the end usage
* sampling vs. 100% testing
* burn-in or environmental tests needed or not
Thank you,
Ioan
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Date: Thu, 14 Feb 2002 13:58:04 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Adhesive Recommendations? Silicon??
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I think the contamination issue is with silicon grease not adhesive or potting compound.
There used to be a legend that the grease would 'migrate' into switches etc where it would cause open
circuits and be impossible to clean.
I'd be interested to know if anyone ever experienced this.
Regards,
[log in to unmask] wrote:
> The answer to your question is.......it depends. (How's that for not
> sticking my neck out?) As long as you use electronic grade silicone (RTV) as
> I mentioned in my previous post, then there is nothing in the material that
> will harm your board. Heck, when I was involved in building high voltage
> power supplies for military applications we potted the entire board in
> silicone to prevent coronal discharge (also known as lightning.) Silicone
> conformal coating is actually quite popular for certain applications.
> However, what I think you are referring to as far as contamination is when a
> board has to be conformal coated or potted with another material. In that
> situation, any silicone on the board will prevent adhesion of the coating so
> one must be very conscience of contamination issues. So, like most things in
> life, there is no absolute here. It all depends on your requirements,
> compatibility to the rest of the process and your individual process
> controls.
>
> Bob
>
> =======================
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of
> > [log in to unmask]
> > Sent: Wednesday, February 13, 2002 9:26 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations? Silicon??
> >
> >
> > Hi, All,
> >
> > I'm still trying to reconcile all the continued use of silicon adhesives
> > (as recommended by several learned members of this forum) with all the
> > learned discussion about how terrible it is to put silicon anywhere near
> > boards because of contamination issues. Is anyone prepared to put his/her
> > neck on the line and try for a definitive statement on this issue - is
> > silicon on boards good, OK or bad? If it's bad, why are so many
> > still doing
> > it? Is it Force Majeur, are there no alternatives, or is there a
> > mysterious
> > land out there where the use of silicon is not detrimental and
> > the benefits
> > are worth having? Which land is this?
> >
> > Peter
> >
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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=========================================================================
Date: Thu, 14 Feb 2002 08:06:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Vacuolar porosity under leads
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
I have a question regarding vacuolar porosity under leads.=20
A potential customer has forwarded me some CAD data and will send me some =
boards for me to inspect using our 5DX X-ray. His concerns are that during =
reflow, the flux attempts to outgas and stops just short of total =
outgassing when the joint solidifies. This situation then forms "pockets" =
in the joint in the lead/pad interconnect.=20
My question is this - Has anyone done any studies regarding this phenomena =
and if so, does this affect the integrity of the joint? My belief has =
always been that the structure and formation of the heel portion of the =
joint comprises the actual integrity of the joint and the toe fillet (or =
lack thereof) does not play into the lifespan (or strength) of the joint. =
Therefore, the lead/pad interconnect would also not be the main point of =
contention.
In Alabama, we had some components (QFP48) that had a ground lug on the =
bottom part of the package that was soldered to a pad directly beneath. =
The lug was approximately 1mm by 1mm and the pad was approximately 7/10mm =
by 7/10mm. In this case, the porosity dilemma was evident. We would see, =
through 3D laminography, that large voids were formed, causing roughly a =
40% or so decrease in actual solder interconnect area. Some playing around =
with the reflow profile displayed better results, but never resolved the =
issue.=20
Any thoughts/comments would be greatly appreciated.
Thanks,
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
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=========================================================================
Date: Thu, 14 Feb 2002 09:10:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Preferred Probes for No Clean Processes
X-To: Carl Ray <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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There are no prefered test probes for NC fluxes. Through experimentation,
you can determine proper probes for the characteristics of the flux you use.
When considering test requirements in your flux qualification process, you
can choose between fluxes with residues that are soft/brittle, slick/sticky,
etc.
Test machine operators:
. Think NC flux residues are a pain in the gluteus maximus.
. Change probes (from a collection of different tip types: crown,
straight point, diamond) to select (tailor) the correct probe for the probe
location.
. Dry scrub probe tips with a wire brush (like Techni-Tool 872M1034, but
with longer rows of bristles) when a fixture begins to act-up.
. Inspect the probe side surfaces for "black corrosion" [from the
flux???] that prevents good contact. The probe manufacturer recommends a
change-out schedule ... 50k hits or something like that.
Dave Fish
----- Original Message -----
From: "Carl Ray" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 13, 2002 12:15 PM
Subject: [TN] Preferred Probes for No Clean Processes
> I need some feedback as to what types of test probes are preferred for
> No Clean Processes? Need to know for probing vias, pads and test points.
> Also product that has been wave soldered and double sided reflow.
>
> --------------------------------------------------------------------------
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additional
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> --------------------------------------------------------------------------
-------
>
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Date: Thu, 14 Feb 2002 15:28:35 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Zweigart, Siegmund" <[log in to unmask]>
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Subject: Class 1 to 3
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Hello
Is it possible to find the definition of class1 2 and 3 in the internet?
Thanks
Siggi
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Date: Thu, 14 Feb 2002 08:23:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
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From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Management forum?
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What a wonderful idea, a management forum. Considering most of the items =
we deal with day to day has to have upper buy in. We do need those =
individuals to champion most programs. Especially with the push from ISO =
to have the senior level much more involved and really guide an organizatio=
n.
Kathy=20
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<DIV>What a wonderful idea, a management forum. Considering most of the
items we deal with day to day has to have upper buy in. We do
need those individuals to champion most programs. Especially with
the push from ISO to have the senior level much more involved and really guide
an organization.</DIV>
<DIV> </DIV>
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Date: Thu, 14 Feb 2002 08:28:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
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Subject: Re: Adhesive Recommendations? Silicon??
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Peter Duncan stirs the pot with:
I'm still trying to reconcile all the continued use of silicon adhesives
(as recommended by several learned members of this forum) with all the
learned discussion about how terrible it is to put silicon anywhere near
boards because of contamination issues. Is anyone prepared to put his/her
neck on the line and try for a definitive statement on this issue - is
silicon on boards good, OK or bad? If it's bad, why are so many still doing
it? Is it Force Majeur, are there no alternatives, or is there a mysterious
land out there where the use of silicon is not detrimental and the benefits
are worth having? Which land is this?
**Doug Pauls, never one to turn down a challenge, responds:
So Peter, you want someone to make a definitive statement that any single
material is absolutely good, or absolutely bad, for all applications for
all products for all end use environments. I don't think that could be
said of any material. Every material has engineering tradeoffs. Take gold
for example. Excellent for RF. Plates well. Nearly corrosion proof.
BUT, a soft metal, can cause solder joint embrittlement and is damned
expensive.
So look at silicones. From what has been said in recent days, do we say
they should never be used in electronics? I'm sure that the good folks at
Dow Chemical and GE would beg to differ. Like any material, you have to be
aware of the material properties and weigh the pros and cons. Do the
advantages of a material outweigh the disadvantages? Is the benefit worth
the pain?
Rockwell has been using silicone adhesives for several years and we build
very high reliability stuff. When our stuff fails, airplanes fly into the
sides of mountains, so we take reliability VERY seriously. If it is a
plane, it has some of our equipment on it somewhere and since I fly alot, I
REALLY take the issue to heart.
We are trying to get away from using silicone adhesives for two reasons:
(1) most of our customers don't want silicone adhesives on the product
because they outgas. The outgas products can tend to cross-contaminate
other hardware, especially switches and relays which can develop open
circuits. So our customers, especially the Europeans, want us to minimize
or eliminate silicones soon. (2) the stuff causes problems in our
manufacturing flow. The silicones can cross contaminate wash solutions, it
takes a long time to cure them fully (24+hours), especially in thick cross
sections (3-5 days), and acrylic conformal coat does not stick to
silicones. That is why we have been looking at thermally cured epoxies and
urethanes lately.
You ask if there are no alternatives and why are we still using this stuff.
Rockwell Collins makes thousands of different products, all with a drawing.
To change from a silicone material to anything else is a HUGE undertaking.
Our products were qualified using silicones. Many of the products were
designed around the properties of the silicones. To change from a silicone
to an epoxy or urethane means that we would have to change thousands of
drawings. A single process initiative, or some form of blanket change, is
not really an option because each product needs to be reviewed by the
design engineer (some of whom are no longer living) to see if the new
material properties change the intended function or reliability. That's a
few thousand reviews and that ain't cheap. So, to answer your question
about why we use them, it is too painful to change, or we have to be able
to show that the reliability and cost savings are sufficient to go through
that change. I have yet to see a large company with diverse product lines
and high reliability requirements implement such changes without a major
investment.
But, if you are making products where outgassing is not a concern, or you
don't conformal coat, the silicones may be just fine. You don't need an
oven to cure them and they get to at least a tack free state in under an
hour and you can keep processing them while they cure.
There are ALWAYS alternative materials. The organic material field is very
diverse. You just have to make the determination of the engineering
tradeoffs with each material and then determine if the benefits of change
outweigh the pain of change.
As to the land where silicones have only advantages and no disadvantages, I
suggest either Oz, second star on the right and straight on till morning,
or the marketing department of a large company in Midland, Michigan.
Doug Pauls
Rockwell Collins
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Date: Thu, 14 Feb 2002 07:23:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Vapor Phase Soldering ReVisited!
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Dear TechNetters,
While attending the last APEX show, I was surprised to find vapor phase
soldering equipment essentially non-existent. At least the high end,
conveyorized machines were not to be found. The equipment being peddled for
no-lead SMT soldering is pretty much 'improved' convection reflow stuff.
With our convection reflow oven we have to run about 40 C. above melt point
to reliably solder our more difficult high layer count boards with large
BGA's (about 30% of our business). If we built these with 'no-lead'
processing (which may be required soon) I expect the boards would be
approaching 250 C., which our organic boards and parts would not tolerate.
It seems to me, in-line vapor phase soldering with a smooth transition into
the vapor chamber, would offer many advantages. If we could find a thermal
liquid with a boiling point of 225 or 230 C., we may be able to solder
'no-lead' pastes with only a 10 or 15 C. delta and not worry about melting
down parts. Also we would be in an easily controlled inert atmosphere to
reduce oxidation.
Am I missing something in this analysis that is obvious to everyone else?
Help? Where have all the vapor phase machines gone?
Jim Kittel
L-3 Communications
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Date: Thu, 14 Feb 2002 09:33:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward H. Uslar" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward H. Uslar" <[log in to unmask]>
Subject: Adhesive
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We are building a fixture for a customer that requires bonding two pieces of
.059 polyimide together. This fixture will be use to hold assembled boards
for the reflow operation in the oven. They will be used many times so the
adhesive needs to with stand the many temperature cycles. A screen printable
adhesive would be ideal. Thanks for your help.
Ed
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Date: Thu, 14 Feb 2002 09:47:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Adhesive Recommendations? Silicon??
X-To: Eric Christison <[log in to unmask]>
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You are correct in that silicon grease causes the same contamination issues
as other silicone based products. Handled incorrectly, silicone can be a
problem whether it is in heatsink grease, adhesives or potting compounds. I
don't know specifically about the switch issue you mentioned, but I do know
heatsink grease has a justly deserved reputation of having prolific
reproductive capacity. Having worked with it for many years I can tell you
it just seems to go everywhere despite one's best intentions otherwise.
Thank goodness for the invention of silicone pads.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Christison
> Sent: Thursday, February 14, 2002 8:58 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations? Silicon??
>
>
> I think the contamination issue is with silicon grease not
> adhesive or potting compound.
>
> There used to be a legend that the grease would 'migrate' into
> switches etc where it would cause open
> circuits and be impossible to clean.
>
> I'd be interested to know if anyone ever experienced this.
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Date: Thu, 14 Feb 2002 09:30:53 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Moses <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Moses <[log in to unmask]>
Subject: Re: Reflow Process
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Hi,
I have found that with most components it is not necessary to use two =
different melt temp solders for double sided reflow. The surface tension =
keeps the bottom components in place unless you have some unusually heavy =
components. Connectors can sometimes be a problem.
John
>>> [log in to unmask] 02/13/02 10:08AM >>>
Hello,
As a part of our preparations to set up an internal SMD line, I would like
to get your opinion on the following topic.
What are the problems, if any, associated with reflowing the double sided
SMT board using solder paste with different melting points for top and
bottom.
Is this a fairly common process?
If not what would you recommend as a best assembly process for double =
sided
SMT boards?
Thanks in advance,
Jerry
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Date: Thu, 14 Feb 2002 10:12:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Hey Jim. Take a look at the February 2002 issue of Assembly magazine. It has
a two page article on this very subject. If you don't subscribe you may be
able to find it at www.assemblymag.com . If not, contact me off-forum and I
can fax you a copy.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jim Kittel
> Sent: Thursday, February 14, 2002 9:24 AM
> To: [log in to unmask]
> Subject: [TN] Vapor Phase Soldering ReVisited!
>
>
> Dear TechNetters,
> While attending the last APEX show, I was surprised to find vapor phase
> soldering equipment essentially non-existent. At least the high end,
> conveyorized machines were not to be found. The equipment being
> peddled for
> no-lead SMT soldering is pretty much 'improved' convection reflow stuff.
> With our convection reflow oven we have to run about 40 C. above
> melt point
> to reliably solder our more difficult high layer count boards with large
> BGA's (about 30% of our business). If we built these with 'no-lead'
> processing (which may be required soon) I expect the boards would be
> approaching 250 C., which our organic boards and parts would not
> tolerate.
> It seems to me, in-line vapor phase soldering with a smooth
> transition into
> the vapor chamber, would offer many advantages. If we could find
> a thermal
> liquid with a boiling point of 225 or 230 C., we may be able to solder
> 'no-lead' pastes with only a 10 or 15 C. delta and not worry about melting
> down parts. Also we would be in an easily controlled inert atmosphere to
> reduce oxidation.
> Am I missing something in this analysis that is obvious to everyone else?
> Help? Where have all the vapor phase machines gone?
> Jim Kittel
> L-3 Communications
>
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Date: Thu, 14 Feb 2002 10:18:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charlie Pitarys <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charlie Pitarys <[log in to unmask]>
Subject: Re: Adhesive Recommendations? Silicon??
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Hi Rick,
You may want to investigate VHB tape from 3M
It is used to secure components in cell tower antennas, used in automotive
applications, even used to secure the vinyl covering over wood on high end
home windows and these guys threw it into an environmental chamber for 2
months to qualify it Also it is impervious to any cleaning chemistry that I
threw at it.
Always ask for samples I believe they will oblige
Good luck
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, February 12, 2002 5:14 PM
To: [log in to unmask]
Subject: [TN] Adhesive Recommendations?
We have an application where we need to secure some vertically mounted
radial electrolytic caps and a few other higher profile items to make
them resistant to shock, impact and vibration (amusement park
application). I've contacted Loctite and 3M for recommendations but the
ones I've gotten have several week lead times, minimum buys due to
special order, etc. Since we don't know if the products will work, we
didn't want to buy minimum quantities of materials we can't return.
Does anyone have any recommendations for standard products you may have
used in similar situations? I realize I can get samples from the mfgs.
Noted but I was hoping to shorten the lead time if I can find off the
shelf products that may do the job.
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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<TITLE>RE: [TN] Adhesive Recommendations? Silicon??</TITLE>
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<P><FONT SIZE=3D2>Hi Rick,</FONT>
<BR><FONT SIZE=3D2>You may want to investigate VHB tape from 3M</FONT>
</P>
<P><FONT SIZE=3D2>It is used to secure components in cell tower =
antennas, used in automotive applications, even used to secure the =
vinyl covering over wood on high end home windows and these guys threw =
it into an environmental chamber for 2 months to qualify it Also it is =
impervious to any cleaning chemistry that I threw at it.</FONT></P>
<P><FONT SIZE=3D2>Always ask for samples I believe they will =
oblige</FONT>
</P>
<P><FONT SIZE=3D2>Good luck</FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Rick Thompson [<A =
HREF=3D"mailto:[log in to unmask]">mailto:rthompson@VENTUR=
AELECTRONICS.COM</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Tuesday, February 12, 2002 5:14 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Adhesive Recommendations?</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>We have an application where we need to secure some =
vertically mounted</FONT>
<BR><FONT SIZE=3D2>radial electrolytic caps and a few other higher =
profile items to make</FONT>
<BR><FONT SIZE=3D2>them resistant to shock, impact and vibration =
(amusement park</FONT>
<BR><FONT SIZE=3D2>application). I've contacted Loctite and 3M =
for recommendations but the</FONT>
<BR><FONT SIZE=3D2>ones I've gotten have several week lead times, =
minimum buys due to</FONT>
<BR><FONT SIZE=3D2>special order, etc. Since we don't know if the =
products will work, we</FONT>
<BR><FONT SIZE=3D2>didn't want to buy minimum quantities of materials =
we can't return.</FONT>
</P>
<P><FONT SIZE=3D2>Does anyone have any recommendations for standard =
products you may have</FONT>
<BR><FONT SIZE=3D2>used in similar situations? I realize I can =
get samples from the mfgs.</FONT>
<BR><FONT SIZE=3D2>Noted but I was hoping to shorten the lead time if I =
can find off the</FONT>
<BR><FONT SIZE=3D2>shelf products that may do the job.</FONT>
</P>
<P><FONT SIZE=3D2>Thanks for your inputs.</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>Rick Thompson</FONT>
<BR><FONT SIZE=3D2>Ventura Electronics Assembly</FONT>
<BR><FONT SIZE=3D2>2655 Park Center Dr.</FONT>
<BR><FONT SIZE=3D2>Simi Valley, CA 93065</FONT>
</P>
<P><FONT SIZE=3D2>+1 (805) 584-9858 x-304 =
voice</FONT>
<BR><FONT SIZE=3D2>+1 (805) 584-1529 fax</FONT>
<BR><FONT SIZE=3D2>[log in to unmask]</FONT>
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Date: Thu, 14 Feb 2002 10:23:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Adhesive Recommendations? Silicon??
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Thanks Doug! Another knowledge nugget that can be filed away.
Phil Nutting
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 9:28 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations? Silicon??
Peter Duncan stirs the pot with:
I'm still trying to reconcile all the continued use of silicon adhesives
(as recommended by several learned members of this forum) with all the
learned discussion about how terrible it is to put silicon anywhere near
boards because of contamination issues. Is anyone prepared to put =
his/her
neck on the line and try for a definitive statement on this issue - is
silicon on boards good, OK or bad? If it's bad, why are so many still =
doing
it? Is it Force Majeur, are there no alternatives, or is there a =
mysterious
land out there where the use of silicon is not detrimental and the =
benefits
are worth having? Which land is this?
**Doug Pauls, never one to turn down a challenge, responds:
So Peter, you want someone to make a definitive statement that any =
single
material is absolutely good, or absolutely bad, for all applications for
all products for all end use environments. I don't think that could be
said of any material. Every material has engineering tradeoffs. Take =
gold
for example. Excellent for RF. Plates well. Nearly corrosion proof.
BUT, a soft metal, can cause solder joint embrittlement and is damned
expensive.
So look at silicones. From what has been said in recent days, do we say
they should never be used in electronics? I'm sure that the good folks =
at
Dow Chemical and GE would beg to differ. Like any material, you have to =
be
aware of the material properties and weigh the pros and cons. Do the
advantages of a material outweigh the disadvantages? Is the benefit =
worth
the pain?
Rockwell has been using silicone adhesives for several years and we =
build
very high reliability stuff. When our stuff fails, airplanes fly into =
the
sides of mountains, so we take reliability VERY seriously. If it is a
plane, it has some of our equipment on it somewhere and since I fly =
alot, I
REALLY take the issue to heart.
We are trying to get away from using silicone adhesives for two reasons:
(1) most of our customers don't want silicone adhesives on the product
because they outgas. The outgas products can tend to cross-contaminate
other hardware, especially switches and relays which can develop open
circuits. So our customers, especially the Europeans, want us to =
minimize
or eliminate silicones soon. (2) the stuff causes problems in our
manufacturing flow. The silicones can cross contaminate wash solutions, =
it
takes a long time to cure them fully (24+hours), especially in thick =
cross
sections (3-5 days), and acrylic conformal coat does not stick to
silicones. That is why we have been looking at thermally cured epoxies =
and
urethanes lately.
You ask if there are no alternatives and why are we still using this =
stuff.
Rockwell Collins makes thousands of different products, all with a =
drawing.
To change from a silicone material to anything else is a HUGE =
undertaking.
Our products were qualified using silicones. Many of the products were
designed around the properties of the silicones. To change from a =
silicone
to an epoxy or urethane means that we would have to change thousands of
drawings. A single process initiative, or some form of blanket change, =
is
not really an option because each product needs to be reviewed by the
design engineer (some of whom are no longer living) to see if the new
material properties change the intended function or reliability. That's =
a
few thousand reviews and that ain't cheap. So, to answer your question
about why we use them, it is too painful to change, or we have to be =
able
to show that the reliability and cost savings are sufficient to go =
through
that change. I have yet to see a large company with diverse product =
lines
and high reliability requirements implement such changes without a major
investment.
But, if you are making products where outgassing is not a concern, or =
you
don't conformal coat, the silicones may be just fine. You don't need =
an
oven to cure them and they get to at least a tack free state in under an
hour and you can keep processing them while they cure.
There are ALWAYS alternative materials. The organic material field is =
very
diverse. You just have to make the determination of the engineering
tradeoffs with each material and then determine if the benefits of =
change
outweigh the pain of change.
As to the land where silicones have only advantages and no =
disadvantages, I
suggest either Oz, second star on the right and straight on till =
morning,
or the marketing department of a large company in Midland, Michigan.
Doug Pauls
Rockwell Collins
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Date: Thu, 14 Feb 2002 07:25:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Adhesive
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
not a lot of details to go on. you might look at the offerings of cytec. they make, among other things, structural film adhesives. you should find a product that will do the job for you.
phil
-----Original Message-----
From: Edward H. Uslar [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 6:34 AM
To: [log in to unmask]
Subject: [TN] Adhesive
We are building a fixture for a customer that requires bonding two pieces of
.059 polyimide together. This fixture will be use to hold assembled boards
for the reflow operation in the oven. They will be used many times so the
adhesive needs to with stand the many temperature cycles. A screen printable
adhesive would be ideal. Thanks for your help.
Ed
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Date: Thu, 14 Feb 2002 07:33:08 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank L Norman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank L Norman <[log in to unmask]>
Subject: Reflow heater zones, how many?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi All,
Can a reflow oven with four heater zones be used to reflow BGA and
0402-0805 chips? And, what is the general school of thought on the subject
of reflow oven heater zones needed to reflow the various technologies?
Frank
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Date: Thu, 14 Feb 2002 09:39:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Management forum?
X-To: [log in to unmask]
Ioan,
You are welcome and thanks for your help on a continuing basis. For lean,
the following is interesting from time to time: http://www.nwlean.net/ but I
think you know this. Can't remember all the folks who put me on to this well
over a year ago.
Earl
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Date: Thu, 14 Feb 2002 10:49:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Vacuolar porosity under leads
X-To: Jason Gregory <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Great question. I have observed voids in fillets on components other than
BGAs as well. We have not studied them. Werner?
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jason Gregory
> Sent: Thursday, February 14, 2002 9:06 AM
> To: [log in to unmask]
> Subject: [TN] Vacuolar porosity under leads
>
>
> I have a question regarding vacuolar porosity under leads.
> A potential customer has forwarded me some CAD data and will send
> me some boards for me to inspect using our 5DX X-ray. His
> concerns are that during reflow, the flux attempts to outgas and
> stops just short of total outgassing when the joint solidifies.
> This situation then forms "pockets" in the joint in the lead/pad
> interconnect.
> My question is this - Has anyone done any studies regarding this
> phenomena and if so, does this affect the integrity of the joint?
> My belief has always been that the structure and formation of the
> heel portion of the joint comprises the actual integrity of the
> joint and the toe fillet (or lack thereof) does not play into the
> lifespan (or strength) of the joint. Therefore, the lead/pad
> interconnect would also not be the main point of contention.
> In Alabama, we had some components (QFP48) that had a ground lug
> on the bottom part of the package that was soldered to a pad
> directly beneath. The lug was approximately 1mm by 1mm and the
> pad was approximately 7/10mm by 7/10mm. In this case, the
> porosity dilemma was evident. We would see, through 3D
> laminography, that large voids were formed, causing roughly a 40%
> or so decrease in actual solder interconnect area. Some playing
> around with the reflow profile displayed better results, but
> never resolved the issue.
> Any thoughts/comments would be greatly appreciated.
>
> Thanks,
>
>
> Jason Gregory
> Software Specialist
> Sanmina-SCI - Tech Center Austin
> 15508 Bratton Lane
> Austin, Tx. 78728
> (512)246-5648
> [log in to unmask]
>
> ------------------------------------------------------------------
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Date: Thu, 14 Feb 2002 09:47:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Management forum?
X-To: [log in to unmask]
Kathy,
Exactomundo! Unfortunately, upper management types often have their own
forum based on their MBA training requiring primary focus to be on the
bottom line often with little attention, or often care, to use at the
bottom. We just had a conversation this morning concerning this issue and
pointed clearly at some very large corporate failings due to too much focus
on the bottom line and stock values, instead the product supporting them to
that point.
Fortunately, I am currently working in a small 40 or so person company with
great cash flow, great folks, and great management (that gets in my face
about three times a day but that's alright because we do share our views
concerning the company's direction). Problem is, management is no where
capable or has the time to entertain a quality system with which to grow.
This will change, and I will be the driver once we get some quality product
in and out the door withing the next few weeks. It, and the DFM/CE efforts
used so far and the rules imposed by it, will serve as models for all other
activities here.
Enjoy,
MoonDFMMan
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Date: Thu, 14 Feb 2002 09:49:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Vapor Phase Soldering ReVisited!
X-To: Jim Kittel <[log in to unmask]>
Jim and all,
What's the status of the "new" condensation process technology?
MoonMan
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Date: Thu, 14 Feb 2002 09:52:58 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Reflow heater zones, how many?
X-To: [log in to unmask]
Give me as many as I can get. I'm a dedicated BTU freak forever. For some
recent stuff, as I've been describing, it was not possible to acheive
success with the 6 zone Heller. Couldn't get the recommended and proven, by
Kerry, profile to even come close for my boards.
MoonMan
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Date: Thu, 14 Feb 2002 18:00:49 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Vapor Phase Soldering ReVisited!
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Jim
VPS or condensation soldering is, indeed, a good theoretical process
with, as you imply, its main advantage being asymptotic, so component
cooking becomes more difficult.
There are fluids available up to about 260°C, so that is not the
problem. The main problems are
a) the fluids are damned expensive
b) with much fluid vapour trapped under components, such as BGAs, the
losses (emissions) are not inconsiderable
c) the fluids, along with SF6, are amongst the worst "global warmers"
known to man, with an atmosperic residence time in the thousands of
years. The GWP of these fluids is about 10,000, that is that if you lose
just 2 kg in a year, this is equivalent to all the CO2 a medium car will
emit in all its lifetime. Apart from that, do you wish to have some
chemical you use floating around in the atmosphere for the next several
millennia, not knowing what is going to happen to it in the end?
Regarding equipment, the last machine I saw was of German manufacture (I
know they were built up to a year or two ago and they may still be). It
was a batch machine but, IMHO, it was not especially well designed to
minimise emissions.
Brian
Jim Kittel wrote:
>
> Dear TechNetters,
> While attending the last APEX show, I was surprised to find vapor phase
> soldering equipment essentially non-existent. At least the high end,
> conveyorized machines were not to be found. The equipment being peddled for
> no-lead SMT soldering is pretty much 'improved' convection reflow stuff.
> With our convection reflow oven we have to run about 40 C. above melt point
> to reliably solder our more difficult high layer count boards with large
> BGA's (about 30% of our business). If we built these with 'no-lead'
> processing (which may be required soon) I expect the boards would be
> approaching 250 C., which our organic boards and parts would not tolerate.
> It seems to me, in-line vapor phase soldering with a smooth transition into
> the vapor chamber, would offer many advantages. If we could find a thermal
> liquid with a boiling point of 225 or 230 C., we may be able to solder
> 'no-lead' pastes with only a 10 or 15 C. delta and not worry about melting
> down parts. Also we would be in an easily controlled inert atmosphere to
> reduce oxidation.
> Am I missing something in this analysis that is obvious to everyone else?
> Help? Where have all the vapor phase machines gone?
> Jim Kittel
> L-3 Communications
>
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Date: Thu, 14 Feb 2002 08:18:01 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Foote, Jeffery" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Foote, Jeffery" <[log in to unmask]>
Subject: Re: Delamination
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Rudy, You are correct the boards do not have buried vias, but the
delamination does not necessarily locate adjacent to a hole. Tests on bare
boards showed that they do occur primarily at one end of the PWB on layer 5
of 8. The delaminations occur on the "sawtooth" side of the copper.
Additionally, examination through the laminate on the secondary side (layer
8) revealed black patchy areas over large land patterns or ground planes on
layer 7. These also occur on the sawtooth side of the copper. Although
these areas have not delaminated, I have confirmed that the laminate resin
does not bond to these areas and EDS showed the same presence of sulfur and
tin that was observed on the delaminated surfaces. Do you know what
chemical preparation the sawtooth side of the copper is exposed to in order
to improve adhesion?
Thanks Rudy for your time.
Best Regards,
Jeff
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, February 13, 2002 3:33 PM
To: [log in to unmask]
Subject: [TN] Delamination
In a message dated 2/13/02 2:58:07 PM Pacific Standard Time,
[log in to unmask]
writes:
<< I am looking for some information regarding the preparation of copper
foil
for adhesion to internal laminate layers in the construction of PWBs. I am
presently experiencing delamination of the copper from the laminate prepreg
on an internal layer after IR reflow exposure. EDS of the delaminated
surfaces showed localized, high-concentration of sulfur and tin on the
copper surface >>
Jeff: I assume that this delamination is occuring adjacent to drilled
holes?
These are not buried via boards are they?
Rudy Sedlak
RD Chemical Company
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Date: Thu, 14 Feb 2002 09:18:21 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Adhesive Recommendations? Silicon??
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Doug,
Well stated.We use DC 3145 for all legacy and momentum products for the
exact reasons you described:tons of test data;Qual data; and years of
trouble free flight use.We have since developed an epoxy adhesive,which is
more in line with today's DFM practices.We also had some failures with the
RTV at higher G levels of vibration.
We had to do a lot of testing and Qual work,because a lot of the bigger
adhesive manufacturers make more money selling to the commodity market and
don't want to bo bothered meeting and testing to our more stringent
requirements.
Properly chosen RTV's meet those requirements and are reworkable,but impose
certain restrictions and complications to the manufacturing process.Some
epoxies meet these requirements, but are potentially less reworkable.
It is imperative that you understand the enviroment of use and the
compatiability of the materials and processes.Is the assembly to be
Conformal Coated?Is the material amine free and is the by-products of the
cure process a potential source of corrosion,contamination or an electrical
migration initiator?
PS:I owe you two Mountain Dews now.
Dewey
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, February 14, 2002 7:28 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations? Silicon??
>
> Peter Duncan stirs the pot with:
>
> I'm still trying to reconcile all the continued use of silicon adhesives
> (as recommended by several learned members of this forum) with all the
> learned discussion about how terrible it is to put silicon anywhere near
> boards because of contamination issues. Is anyone prepared to put his/her
> neck on the line and try for a definitive statement on this issue - is
> silicon on boards good, OK or bad? If it's bad, why are so many still
> doing
> it? Is it Force Majeur, are there no alternatives, or is there a
> mysterious
> land out there where the use of silicon is not detrimental and the
> benefits
> are worth having? Which land is this?
>
> **Doug Pauls, never one to turn down a challenge, responds:
>
> So Peter, you want someone to make a definitive statement that any single
> material is absolutely good, or absolutely bad, for all applications for
> all products for all end use environments. I don't think that could be
> said of any material. Every material has engineering tradeoffs. Take
> gold
> for example. Excellent for RF. Plates well. Nearly corrosion proof.
> BUT, a soft metal, can cause solder joint embrittlement and is damned
> expensive.
>
> So look at silicones. From what has been said in recent days, do we say
> they should never be used in electronics? I'm sure that the good folks at
> Dow Chemical and GE would beg to differ. Like any material, you have to
> be
> aware of the material properties and weigh the pros and cons. Do the
> advantages of a material outweigh the disadvantages? Is the benefit worth
> the pain?
>
> Rockwell has been using silicone adhesives for several years and we build
> very high reliability stuff. When our stuff fails, airplanes fly into the
> sides of mountains, so we take reliability VERY seriously. If it is a
> plane, it has some of our equipment on it somewhere and since I fly alot,
> I
> REALLY take the issue to heart.
>
> We are trying to get away from using silicone adhesives for two reasons:
> (1) most of our customers don't want silicone adhesives on the product
> because they outgas. The outgas products can tend to cross-contaminate
> other hardware, especially switches and relays which can develop open
> circuits. So our customers, especially the Europeans, want us to
> minimize
> or eliminate silicones soon. (2) the stuff causes problems in our
> manufacturing flow. The silicones can cross contaminate wash solutions,
> it
> takes a long time to cure them fully (24+hours), especially in thick cross
> sections (3-5 days), and acrylic conformal coat does not stick to
> silicones. That is why we have been looking at thermally cured epoxies
> and
> urethanes lately.
>
> You ask if there are no alternatives and why are we still using this
> stuff.
> Rockwell Collins makes thousands of different products, all with a
> drawing.
> To change from a silicone material to anything else is a HUGE undertaking.
> Our products were qualified using silicones. Many of the products were
> designed around the properties of the silicones. To change from a
> silicone
> to an epoxy or urethane means that we would have to change thousands of
> drawings. A single process initiative, or some form of blanket change, is
> not really an option because each product needs to be reviewed by the
> design engineer (some of whom are no longer living) to see if the new
> material properties change the intended function or reliability. That's a
> few thousand reviews and that ain't cheap. So, to answer your question
> about why we use them, it is too painful to change, or we have to be able
> to show that the reliability and cost savings are sufficient to go through
> that change. I have yet to see a large company with diverse product lines
> and high reliability requirements implement such changes without a major
> investment.
>
> But, if you are making products where outgassing is not a concern, or you
> don't conformal coat, the silicones may be just fine. You don't need an
> oven to cure them and they get to at least a tack free state in under an
> hour and you can keep processing them while they cure.
>
> There are ALWAYS alternative materials. The organic material field is
> very
> diverse. You just have to make the determination of the engineering
> tradeoffs with each material and then determine if the benefits of change
> outweigh the pain of change.
>
> As to the land where silicones have only advantages and no disadvantages,
> I
> suggest either Oz, second star on the right and straight on till morning,
> or the marketing department of a large company in Midland, Michigan.
>
> Doug Pauls
> Rockwell Collins
>
> --------------------------------------------------------------------------
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Date: Thu, 14 Feb 2002 11:21:12 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Re: Adhesive Recommendations?
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One more option I will mention that I have used - Humiseal makes a product
called Humigel that is specially for staking. It comes in a can sort of like
those cheese products that you squirt onto crackers. I have also used a
couple of the Dow products mentioned by others, and they worked well too.
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Date: Thu, 14 Feb 2002 09:25:38 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: Class 1 to 3
X-To: "Zweigart, Siegmund" <[log in to unmask]>
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Siggi,
IPC-A-610C defines Class I, II & III as follows.
Class I-- General Electronic Products
Includes consumer products, some computer peripherals suitable
for applications where cosmetic imperfections are not important
and the major requirement is function of the completed electronic
assembly.
Class II-- Dedicated Service Electronic Products
Includes communications equipment, sophisticated business machines,
and instruments where high performance and extended life is required and
for which uninterrupted service is desired but not critical. Certain
cosmetic
imperfections are allowed.
Class III-- High Performance Electronic Products
Includes the equipment and products where continued performance or
performance-on-demand is critical. Equipment downtime cannot be
tolerated
and must function when required, such as in life support items or flight
control
systems. Assemblies in this class are suitable for applications where
high
levels of assurance are required, service is essential, or the end-use
environment
may be uncommonly harsh.
Paragraph 1.4.2 also states:
The customer has the ultimate responsibility to identify the class to which
the assembly is evaluated. Thus, accept and/or reject decision must be based
on applicable documentation such as contracts, drawings, specifications,
standards
reference documents.
Barry.
-----Original Message-----
From: Zweigart, Siegmund [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Thursday, February 14, 2002 7:29 AM
To: [log in to unmask]
Subject: [TN] Class 1 to 3
Hello
Is it possible to find the definition of class1 2 and 3 in the internet?
Thanks
Siggi
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE></TITLE>
<META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD>
<BODY>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT size=2>Siggi,<BR><BR>IPC-A-610C
defines Class I, II & III as follows.<BR><BR>
<STRONG><U>Class I-- General Electronic Products</U></STRONG></FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> Includes consumer
products, some computer peripherals suitable</DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> for applications where
cosmetic imperfections are not important</DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> and the major
requirement is function of the completed electronic</DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> assembly.</DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> </DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <STRONG><FONT
face=Arial size=2><U>Class II-- Dedicated Service Electronic
Products</U></FONT></STRONG></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>Includes communications equipment, sophisticated business
machines,</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2> and instruments where high performance and extended
life is required and</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2> for which uninterrupted service is desired but not
critical. Certain cosmetic</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>imperfections are allowed.</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2></FONT> </DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <STRONG><U><FONT
face=Arial size=2>Class III-- High Performance Electronic
Products</FONT></U></STRONG></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>Includes the equipment and products where continued performance or
</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>performance-on-demand is critical. Equipment downtime cannot be
tolerated</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2> and must function when required, such as in life
support items or flight control</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2> systems. Assemblies in this class are suitable for
applications where high</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>levels of assurance are required, service is essential, or the end-use
environment</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"> <FONT face=Arial
size=2>may be uncommonly harsh.</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2></FONT> </DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial size=2>Paragraph 1.4.2
also states:</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><STRONG><FONT face=Arial size=2>The
customer has the ultimate responsibility to identify the class to
which</FONT></STRONG></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial size=2><STRONG>the
assembly is evaluated. </STRONG>Thus, accept and/or reject decision must be
based</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial size=2>on applicable
documentation such as contracts, drawings, specifications,
standards</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial size=2>reference
documents.</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2></FONT> </DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial
size=2>Barry.</FONT></DIV>
<DIV dir=ltr style="MARGIN-RIGHT: 0px"><FONT
size=2> <BR>
<BR><BR>-----Original Message-----<BR>From: Zweigart, Siegmund [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Sent:
Thursday, February 14, 2002 7:29 AM<BR>To: [log in to unmask]<BR>Subject: [TN]
Class 1 to 3<BR><BR><BR>Hello<BR><BR>Is it possible to find the definition of
class1 2 and 3 in the
internet?<BR><BR>Thanks<BR><BR>Siggi<BR><BR>---------------------------------------------------------------------------------<BR>Technet
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To
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Date: Thu, 14 Feb 2002 09:25:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Re: Reflow heater zones, how many?
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Frank,
Don't forget to count cooling zones when you load options on you machine.
Cooling a BGA at too fast a ramp can induce serious stresses and warpage.
Ideally you would cool close to the same rate as you heat.
JIm KIttel
-----Original Message-----
From: Frank L Norman [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 8:33 AM
To: [log in to unmask]
Subject: [TN] Reflow heater zones, how many?
Hi All,
Can a reflow oven with four heater zones be used to reflow BGA and
0402-0805 chips? And, what is the general school of thought on the subject
of reflow oven heater zones needed to reflow the various technologies?
Frank
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Date: Thu, 14 Feb 2002 17:44:06 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Vapor Phase Soldering ReVisited!
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Jim
I believe the VP is still a good principle. However, the industrial =
partner in LEADFREE that runs the VP trials told me that he has to use a =
liquid with a boiling point of 270 deg.C and that there is nothing =
available that boils around 230 deg.
I had problem to believe this but also after asking again I got the same =
answer.
Best regards
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Thu, 14 Feb 2002 11:54:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Class 1 to 3
X-To: "Zweigart, Siegmund" <[log in to unmask]>
In-Reply-To: <795D6BC907F3D511B450000629554AE60CA56F@RFC1918-Host>
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From IPC 2221
Class 1 General Electronic Products Includes consumer products, some
computer and computer peripherals, as well as general military hardware
suitable for applications where cosmetic imperfections are not important and
the major requirement is function of the completed printed board or printed
board assembly.
Class 2 Dedicated Service Electronic Products Includes communications
equipment, sophisticated business machines, instruments and military
equipment where high performance and extended life is required, and for
which uninterrupted service is desired but is not critical. Certain cosmetic
imperfections are allowed.
Class 3 High Reliability Electronic Products Includes the equipment for
commercial and military products where continued performance or performance
on demand is critical. equipment downtime cannot be tolerated, and must
function when required such as for life support items, or critical weapons
systems. Printed boards and printed board assemblies in this class are
suitable for applications where high levels of assurance are require and
service is essential.
These definitions have the same intent and are similar in all the IPC
Standards but the exact words do vary from document to document. For
example, the IPC-A-610C adds "where the end use environment may be
uncommonly harsh" in Class 3.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Zweigart, Siegmund
> Sent: Thursday, February 14, 2002 9:29 AM
> To: [log in to unmask]
> Subject: [TN] Class 1 to 3
>
>
> Hello
>
> Is it possible to find the definition of class1 2 and 3 in the internet?
>
> Thanks
>
> Siggi
>
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Date: Thu, 14 Feb 2002 10:57:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Re: Preferred Probes for No Clean Processes
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A paper on this issue was presented at APEX last year. It is in Proceeding=
s from APEX 2001, paper MP4-5; Method for Evaluating ICT Probe Penetrabilit=
y of Flux Residues, Karen Tellefsen, Alpha Metals & Mark Weiss, Motorola=20=
Jack
>>> [log in to unmask] 02/14/02 11:10AM >>>
There are no prefered test probes for NC fluxes. Through experimentation,
you can determine proper probes for the characteristics of the flux you =
use.
When considering test requirements in your flux qualification process, you
can choose between fluxes with residues that are soft/brittle, slick/sticky=
,
etc.
Test machine operators:
. Think NC flux residues are a pain in the gluteus maximus.
. Change probes (from a collection of different tip types: crown,
straight point, diamond) to select (tailor) the correct probe for the =
probe
location.
. Dry scrub probe tips with a wire brush (like Techni-Tool 872M1034, =
but
with longer rows of bristles) when a fixture begins to act-up.
. Inspect the probe side surfaces for "black corrosion" [from the
flux???] that prevents good contact. The probe manufacturer recommends a
change-out schedule ... 50k hits or something like that.
Dave Fish
----- Original Message -----
From: "Carl Ray" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 13, 2002 12:15 PM
Subject: [TN] Preferred Probes for No Clean Processes
> I need some feedback as to what types of test probes are preferred for
> No Clean Processes? Need to know for probing vias, pads and test points.
> Also product that has been wave soldered and double sided reflow.
>
> -------------------------------------------------------------------------=
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in
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>
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>
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<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
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<DIV><FONT size=3D1>A paper on this issue was presented at APEX last =
year. =20
It is in Proceedings from APEX 2001, paper MP4-5; Method for Evaluating =
ICT=20
Probe Penetrability of Flux Residues, Karen Tellefsen, Alpha Metals & =
Mark=20
Weiss, Motorola </FONT></DIV>
<DIV> </DIV>
<DIV>Jack</DIV>
<DIV><FONT size=3D1></FONT><BR><BR>>>> [log in to unmask] 02/14/02 =
11:10AM=20
>>><BR>There are no prefered test probes for NC fluxes. =
Through=20
experimentation,<BR>you can determine proper probes for the characteristics=
of=20
the flux you use.<BR>When considering test requirements in your flux=20
qualification process, you<BR>can choose between fluxes with residues that =
are=20
soft/brittle, slick/sticky,<BR>etc.<BR><BR>Test machine=20
operators:<BR> . Think NC flux residues are a pain in =
the=20
gluteus maximus.<BR> . Change probes (from a collection =
of=20
different tip types: crown,<BR>straight point, diamond) to select (tailor) =
the=20
correct probe for the probe<BR>location.<BR> . Dry scrub =
probe=20
tips with a wire brush (like Techni-Tool 872M1034, but<BR>with longer rows =
of=20
bristles) when a fixture begins to act-up.<BR> . Inspect =
the=20
probe side surfaces for "black corrosion" [from the<BR>flux???] that =
prevents=20
good contact. The probe manufacturer recommends a<BR>change-out schedule =
... 50k=20
hits or something like that.<BR><BR>Dave Fish<BR><BR>----- Original =
Message=20
-----<BR>From: "Carl Ray" <[log in to unmask]><BR>To:=20
<[log in to unmask]><BR>Sent: Wednesday, February 13, 2002 12:15=20
PM<BR>Subject: [TN] Preferred Probes for No Clean Processes<BR><BR><BR>>=
I=20
need some feedback as to what types of test probes are preferred for<BR>>=
; No=20
Clean Processes? Need to know for probing vias, pads and test points.<BR>&g=
t;=20
Also product that has been wave soldered and double sided=20
reflow.<BR>><BR>>=20
--------------------------------------------------------------------------<=
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ail=20
Archives<BR>> Please visit IPC web site (<A=20
href=3D"http://www.ipc.org/html/forum.htm)">http://www.ipc.org/html/forum.h=
tm)</A>=20
for<BR>additional<BR>> information, or contact Keach Sasamori at=20
[log in to unmask] or 847-509-9700<BR>ext.5315<BR>>=20
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Date: Thu, 14 Feb 2002 10:57:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Antonio Souza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Antonio Souza <[log in to unmask]>
Subject: Soldering Defects
Does anybody know where can I find free illustrations of soldering
conections of electronic components ?
thanks a lot
Antonio
Brazil
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Date: Thu, 14 Feb 2002 16:27:42 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank Davies <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Davies <[log in to unmask]>
Subject: Porosity testing
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Hello out there:
Looking for some information on Porosity testing:
A. a customer wanting a porosity test on immersion gold, is anyone doing =
this and to what method is it being done?=20
B. Does anyone know of a supply house in western Europe that supplies =
Cadmium sulphide paper for the test per BS-CECC23000? Sorry but the =
only information comes from the 1991 copy.=20
Thanks in Advance
Frank
------=_NextPart_000_0008_01C1B574.870A0860
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charset="iso-8859-1"
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hello out there:</FONT></DIV>
<DIV><FONT size=3D2>Looking for some information on Porosity =
testing:</FONT></DIV>
<DIV><FONT size=3D2>A. a customer wanting a porosity test on immersion =
gold, is=20
anyone doing this and to what method is it being done? </FONT></DIV>
<DIV><FONT size=3D2>B. Does anyone know of a supply house in western =
Europe that=20
supplies Cadmium sulphide paper for the test per BS-CECC23000? =
Sorry but=20
the only information comes from the 1991 copy. </FONT></DIV>
<DIV><FONT size=3D2>Thanks in Advance</FONT></DIV>
<DIV><FONT size=3D2>Frank</FONT></DIV>
<DIV> </DIV></BODY></HTML>
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Date: Thu, 14 Feb 2002 11:11:08 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Re: Class 1 to 3
X-To: [log in to unmask]
Mime-Version: 1.0
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I don't know that they are on our website in anyway that you'd identify =
them. The definitions are published in the front of nearly all the IPC =
standards and guidlines and is quite general in nature. Here's a copy =
from the National Soldering Standard IPC/EIA J-STD-001C. Note the strong =
statement that Class of Construction is determine only be agreement =
between user and supplier. The user particularly needs to drive this =
because only they know the end use environment and minimum reliability =
requirements.=20
I hope this helps.
Jack
1.2 Classification This standard recognizes that electrical and electronic =
assemblies are subject to classifications by intended end-item use. Three =
general end-product classes have been established to reflect differences =
in producibility, complexity, functional performance requirements, and =
verification (inspection/test) frequency. It should be recognized that =
there may be overlaps of equipment
between classes.
The user and manufacturer shall agree on the class to which the product =
belongs. The product class should be stated in the procurement documentatio=
n package.
CLASS 1 General Electronic Products
Includes products suitable for applications where the major requirement is =
function of the completed assembly.
CLASS 2 Dedicated Service Electronic Products
Includes products where continued performance and extended life is =
required, and for which uninterrupted service is desired but not critical. =
Typically the end-use environment would not cause failures.
CLASS 3 High Performance Electronic Products
Includes products where continued high performance or performance-on-demand=
is critical, equipment downtime cannot be tolerated, end-use environment =
may be uncommonly harsh, and the equipment must function when required, =
such as life support or other critical systems.
>>> [log in to unmask] 02/14/02 08:28AM >>>
Hello
Is it possible to find the definition of class1 2 and 3 in the internet?
Thanks
Siggi
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c.org: SET Technet Digest
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additional
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<HTML><HEAD>
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>
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<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1>I don't know that they are on our website in anyway =
that you'd=20
identify them. The definitions are published in the front of nearly =
all=20
the IPC standards and guidlines and is quite general in nature. =
Here's a=20
copy from the National Soldering Standard IPC/EIA J-STD-001C. Note the =
strong=20
statement that Class of Construction is determine only be agreement =
between user=20
and supplier. The user particularly needs to drive this because only they =
know=20
the end use environment and minimum reliability requirements. </FONT></DIV>=
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>I hope this helps.</FONT></DIV>
<DIV><FONT size=3D1>Jack</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV>1.2 Classification This standard recognizes that electrical and =
electronic=20
assemblies are subject to classifications by intended end-item use. =
Three=20
general end-product classes have been established to reflect differences =
in=20
producibility, complexity, functional performance requirements, and =
verification=20
(inspection/test) frequency. It should be recognized that there may be =
overlaps=20
of equipment<BR>between classes.</DIV>
<DIV> </DIV>
<DIV>The user and manufacturer shall agree on the class to which the =
product=20
belongs. The product class should be stated in the procurement documentatio=
n=20
package.</DIV>
<DIV> </DIV>
<DIV>CLASS 1 General Electronic Products<BR>Includes products suitable =
for=20
applications where the major requirement is function of the completed=20
assembly.</DIV>
<DIV> </DIV>
<DIV>CLASS 2 Dedicated Service Electronic Products<BR>Includes products =
where=20
continued performance and extended life is required, and for which =
uninterrupted=20
service is desired but not critical. Typically the end-use environment =
would not=20
cause failures.</DIV>
<DIV> </DIV>
<DIV>CLASS 3 High Performance Electronic Products<BR>Includes products =
where=20
continued high performance or performance-on-demand is critical, =
equipment=20
downtime cannot be tolerated, end-use environment may be uncommonly harsh, =
and=20
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Date: Thu, 14 Feb 2002 12:42:19 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Vacuolar porosity under leads
MIME-Version: 1.0
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Hi All,
I am not aware of any studies, or product experiences, that indicate that
voids constitute a significant reliability problem--mostly BGAs. There has
been some work indicating that some voids [emphasis on some] locally and
temporarily retard crack propagation [so do not try to have more
voids]--again BGA-type solder joints. When you have highly non-uniform
loading, as with gullwing-leads, this may no longer be true--however, since
these leads are highly compliant [QFPs] it still does not make any practical
difference. If however, you have rigid stubby leads [TSOPs, SOTs],
particularly if the foot-length is short [< 3x foot-width], then voids,
particularly in the heel fillet, could lead to earlier failure.
Whether flux residues or any other inclusions in solder voids have a
deleterious effect, I do not know.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Thu, 14 Feb 2002 11:53:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Vacuolar porosity under leads
X-To: [log in to unmask]
I can't rememver all I forgot on the subject. Before BGA days, in the middle
to late 80's, I did some work addressing leaded and chip device voiding.
I'll ask Steve to post a few images showing solder joint voiding in
x-section. I had some from x-ray as well but the images have dissapeared.
Anyway, some of us used the same rule (20%) for maximum voiding allowable
after determining, in small quantities on a few boards, failures occured
after very few mechanical and thermal cycles when the requirement was exceeded.
It should be noted some of the solder thickness, between leads and solder
termination areas, measurments exceeded the 1.5 times requirement then used.
I don't know if this rule still applies but probably is.
I'll get the pictures up for you if interested. They simply will complement
your stuff.
Earl
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Date: Thu, 14 Feb 2002 10:59:14 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
Guenter,
Thanks for your response. I also had trouble finding a liquid with a
boiling point of 225, but according to an article mentioned earlier (
www.assemblymag.com ) the liquids of different boiling points can be blended
to achieve what you need.
Thanks,
Jim Kittel
-----Original Message-----
From: Guenter Grossmann [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 9:44 AM
To: [log in to unmask]
Subject: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
Jim
I believe the VP is still a good principle. However, the industrial partner
in LEADFREE that runs the VP trials told me that he has to use a liquid with
a boiling point of 270 deg.C and that there is nothing available that boils
around 230 deg.
I had problem to believe this but also after asking again I got the same
answer.
Best regards
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Thu, 14 Feb 2002 18:06:17 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Vapor Phase Soldering ReVisited!
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Earl, Jim and others,
I will be delighted to send you information, but it must be off-line!
On-line, I can state that we have a patented process that conducts the
process in a sealed chamber using fluids with various boiling points to suit
the alloy you wish to use.
There is a heat plate in the base that is set to the desired temp so that
the fluid will vaporise. It will then condense on everything colder than it,
thus penetrate under the most discreet devices with absolute control and
efficiency.
When the process is complete - less than 1 minute - the vapour is "vacuum
pumped" out of the chamber. This then ensures the absolute minimal solvent
loss.
Refer to it as a dis-continuous process. The whole process is done in a
sealed chamber with doors at each end. If the chamber is big enough, you
could do a whole weeks soldering production in 2 minutes.
If y'all want more let me know.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: 14 February 2002 15:49
> To: [log in to unmask]
> Subject: Re: [TN] Vapor Phase Soldering ReVisited!
>
>
> Jim and all,
>
> What's the status of the "new" condensation process technology?
>
> MoonMan
>
> ------------------------------------------------------------------
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Date: Thu, 14 Feb 2002 13:11:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I think the problem you will find as was explained before is the cost of
these liquids are very pricey and they only make them a few times a year
and if they have non and you want some you will have to wait. Just my two
cents worth.
Jim Kittel
<[log in to unmask] To: [log in to unmask]
-3COM.COM> cc:
Sent by: Subject: Re: [TN] Antw: [TN] Vapor Phase
TechNet Soldering ReVisited!
<[log in to unmask]
RG>
02/14/02 12:59
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to jkittel
Guenter,
Thanks for your response. I also had trouble finding a liquid with a
boiling point of 225, but according to an article mentioned earlier (
www.assemblymag.com ) the liquids of different boiling points can be
blended
to achieve what you need.
Thanks,
Jim Kittel
-----Original Message-----
From: Guenter Grossmann [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 9:44 AM
To: [log in to unmask]
Subject: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
Jim
I believe the VP is still a good principle. However, the industrial partner
in LEADFREE that runs the VP trials told me that he has to use a liquid
with
a boiling point of 270 deg.C and that there is nothing available that boils
around 230 deg.
I had problem to believe this but also after asking again I got the same
answer.
Best regards
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Thu, 14 Feb 2002 19:40:28 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Matthias Mansfeld <[log in to unmask]>
Organization: Matthias Mansfeld Elektronik
Subject: Re: Vapor Phase Soldering ReVisited!
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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On 14 Feb 2002 at 18:00, Brian Ellis wrote:
[....]
> Regarding equipment, the last machine I saw was of German manufacture
> (I know they were built up to a year or two ago and they may still
> be). It was a batch machine but, IMHO, it was not especially well
> designed to minimise emissions.
Look at
http://www.ibl-loettechnik.de (the first German manufacturer using no
secondary fluid)
http://www.asscon.de (the second, AFAIK a spin of of some people from
IBL)
http://www.streckfuss.com (their server seems to be down currently)
Regards,
Matthias Mansfeld--
Matthias Mansfeld Elektronik
* Leiterplattenlayout, Bestueckung
Am Langhoelzl 11, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de
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Date: Thu, 14 Feb 2002 10:42:39 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: Adhesive Recommendations?
X-To: Guy Ramsey <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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The 'tearing away' is exactly the problem our customer is concerned with
based on their experience. This thing has to go in a bumper car which
has significant impact shock for may hours a day. Unfortunately for us,
the design is a modification of an existing product that doesn't see
this environment. The wire hold downs are a good idea, but we can't use
them is some areas of the board due to the design.
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Wednesday, February 13, 2002 8:02 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
I wondered if anyone was going to caution the group on this fact. I have
seen RTV damage the printed circuit right through solder mask.
The other thing I have observed is that it isn't that good at absorbing
shock. If you hit it hard it can simply tear or worse bounce and
actually return energy to the component.
I think in the context originally described in this thread, used in
conjunction with a wire hold down, it may be okay.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> Sent: Wednesday, February 13, 2002 8:54 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
>
> Use caution if you buy a general purpose RTV at a hardware store. Many
> of those products will be corrosive to electronics. If it smells like
> vinegar when it cures it is no good for electronics. You must use an
> electronic grade of RTV on boards. We use Dow Corning 3145 all the
> time for staking with excellent results. We too transfer it to a
> syringe and use an EFD dispenser.
>
> Bob
>
> =======================
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> > Sent: Wednesday, February 13, 2002 8:15 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations?
>
> >
> > For instant gratification there are several clear RTV products
> > available at the local hardware store that are used for general
> > bonding and sealing. Like replacing those tiles in the bathroom that
> > have come loose.
> >
> > It isn't high tech but it has worked for many years.
>
> ------------------------------------------------------------------
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>
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Date: Thu, 14 Feb 2002 12:52:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Porosity testing
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
You can try IPC-TM-650, method 2.3.24.1 or 2.3.24.2. Try these links.
http://www.ipc.org/html/2.3.24.1.pdf
http://www.ipc.org/html/2.3.24.2.pdf
I don't know about the cadmium sulfide paper
Doug Pauls
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Date: Thu, 14 Feb 2002 13:03:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Christoffel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Christoffel <[log in to unmask]>
Subject: Re: Adhesive Recommendations?
MIME-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
In a former life, I had some great results with a 3M material (#2214
structural adhesive) worked great as passed very rigid (MIL) shock and
vibration testing.
BC
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 12:43 PM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
The 'tearing away' is exactly the problem our customer is concerned with
based on their experience. This thing has to go in a bumper car which
has significant impact shock for may hours a day. Unfortunately for us,
the design is a modification of an existing product that doesn't see
this environment. The wire hold downs are a good idea, but we can't use
them is some areas of the board due to the design.
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Wednesday, February 13, 2002 8:02 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
I wondered if anyone was going to caution the group on this fact. I have
seen RTV damage the printed circuit right through solder mask.
The other thing I have observed is that it isn't that good at absorbing
shock. If you hit it hard it can simply tear or worse bounce and
actually return energy to the component.
I think in the context originally described in this thread, used in
conjunction with a wire hold down, it may be okay.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> Sent: Wednesday, February 13, 2002 8:54 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
>
> Use caution if you buy a general purpose RTV at a hardware store. Many
> of those products will be corrosive to electronics. If it smells like
> vinegar when it cures it is no good for electronics. You must use an
> electronic grade of RTV on boards. We use Dow Corning 3145 all the
> time for staking with excellent results. We too transfer it to a
> syringe and use an EFD dispenser.
>
> Bob
>
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> > Sent: Wednesday, February 13, 2002 8:15 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations?
>
> >
> > For instant gratification there are several clear RTV products
> > available at the local hardware store that are used for general
> > bonding and sealing. Like replacing those tiles in the bathroom that
> > have come loose.
> >
> > It isn't high tech but it has worked for many years.
>
> ------------------------------------------------------------------
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Date: Thu, 14 Feb 2002 14:24:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Tom Parkinson - Quality System Manager <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Parkinson - Quality System Manager <[log in to unmask]>
Organization: WinTronics, Inc.
Subject: Re: Soldering Defects
X-To: Antonio Souza <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Try Circuit Technology - their web site is at:
http://www.circuitnet.com/
Get their free CD-ROM.. At the bottom of the page it says:
"Circuit Board Repair Encyclopedia CD
This free all-and-everything CD is
jam-packed with information and
reference material on circuit board
repair and rework. It contains 85
repair, rework, and assembly
procedures, and over 400
illustrations, photographs and
video clips. "
Antonio Souza wrote:
>
> Does anybody know where can I find free illustrations of soldering
> conections of electronic components ?
>
> thanks a lot
>
> Antonio
> Brazil
>
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Date: Thu, 14 Feb 2002 20:58:32 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Matthias Mansfeld <[log in to unmask]>
Organization: Matthias Mansfeld Elektronik
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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On 14 Feb 2002 at 10:59, Jim Kittel wrote:
> Guenter,
> Thanks for your response. I also had trouble finding a liquid with a
> boiling point of 225, but according to an article mentioned earlier (
> www.assemblymag.com ) the liquids of different boiling points can be
> blended to achieve what you need. Thanks, Jim Kittel
... where is this article (URL)? I can't imagine that, as mixed
liquids with different boiling points are usually separated by
distillation (take brandy - the wine will boil at the boiling point
of ethanole until all ethanol has left the wine, then the temperature
will raise up to 100=B0C). ????
Regards
Matthias--
Matthias Mansfeld Elektronik
* Leiterplattenlayout, Bestueckung
Am Langhoelzl 11, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de
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Date: Thu, 14 Feb 2002 13:32:32 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: Adhesive Recommendations?
X-To: Bill Christoffel <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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The 2214 is the adhesive recommended by 3M for our application. Only
problem was long lead time and minimum buys and we weren't sure it would
work. It's good to get some positive feedback on the product.
Thanks,
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Bill Christoffel
Sent: Thursday, February 14, 2002 11:04 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
In a former life, I had some great results with a 3M material (#2214
structural adhesive) worked great as passed very rigid (MIL) shock and
vibration testing.
BC
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 12:43 PM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
The 'tearing away' is exactly the problem our customer is concerned with
based on their experience. This thing has to go in a bumper car which
has significant impact shock for may hours a day. Unfortunately for us,
the design is a modification of an existing product that doesn't see
this environment. The wire hold downs are a good idea, but we can't use
them is some areas of the board due to the design.
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Wednesday, February 13, 2002 8:02 AM
To: [log in to unmask]
Subject: Re: [TN] Adhesive Recommendations?
I wondered if anyone was going to caution the group on this fact. I have
seen RTV damage the printed circuit right through solder mask.
The other thing I have observed is that it isn't that good at absorbing
shock. If you hit it hard it can simply tear or worse bounce and
actually return energy to the component.
I think in the context originally described in this thread, used in
conjunction with a wire hold down, it may be okay.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> Sent: Wednesday, February 13, 2002 8:54 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adhesive Recommendations?
>
>
> Use caution if you buy a general purpose RTV at a hardware store. Many
> of those products will be corrosive to electronics. If it smells like
> vinegar when it cures it is no good for electronics. You must use an
> electronic grade of RTV on boards. We use Dow Corning 3145 all the
> time for staking with excellent results. We too transfer it to a
> syringe and use an EFD dispenser.
>
> Bob
>
> =======================
> Robert Barr
> Manufacturing Engineering
> Formation, Inc.
> Voice: 856-234-5020 x3035
> Fax: 856-234-6679
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> > Sent: Wednesday, February 13, 2002 8:15 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Adhesive Recommendations?
>
> >
> > For instant gratification there are several clear RTV products
> > available at the local hardware store that are used for general
> > bonding and sealing. Like replacing those tiles in the bathroom that
> > have come loose.
> >
> > It isn't high tech but it has worked for many years.
>
> ------------------------------------------------------------------
> ---------------
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> ---------------
>
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Date: Thu, 14 Feb 2002 14:03:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: CAD Database file v/s Netlist file
MIME-Version: 1.0
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PCB Expert,
If I provide my fab house CAD database file in ASCII format, do I still
have to provide netlist in IPC-356 file format. Can fab house be able to
extract needed netlist info for testing purpose out of database file?
The dilemma I have is that my cad person do not know how to extract the
netlist file from PADS. Any help/clarification in this direction will be
appreciated.
Re,
Ken Patel
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Date: Thu, 14 Feb 2002 14:42:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Parsons <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Parsons <[log in to unmask]>
Subject: Re: CAD Database file v/s Netlist file
X-To: Ken Patel <[log in to unmask]>
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MIME-Version: 1.0
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Ken,
It really depends on the Fab house and on the software they are using. I
don't know what version of PADS you are running but it was my understanding
that a year or so ago that PADS could not export in 356-A format. Our old
GC-CAM (Graphicode) software did have an option available that would import
a number of CAD netlist formats. We would then compare the gerber extracted
netlist against the CAD netlist supplied. If all was OK we would proceed.
The netlist data used for the test fixture was still generated from the
Gerber files but at least we knew they matched. Our new software (Genesis)
can only read 356 or Mentor "Neutral" netlist data.
I suspect that you will be out of luck with what you want to try, but to be
sure contact your favorite fab shop.
Regards
John Parsons
Enigma Interconnect - Vancouver
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Date: Thu, 14 Feb 2002 17:58:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Standards for testing
X-To: "Tempea, Ioan" <[log in to unmask]>
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IPC-222X - Generic & Sectional Standards On Printed Board Design include the
perspectives of automated test in board design.
Recognize the growth in board complexity and size reduction have both been
expediential over the past 10 years, but progress in the automated test
community has been flat line. The test community's answer? SCAN, yawn.
What??? Yes, I'm still here. . ummm leading directly to automated optical
inspection, another programming nightmare. [So, the BIG dogs of ATE are
purchasing the AOI firms and doing what? An integrated ATE/AOI? Gawd,
where are the darn rusty razor blades? ]
Other points:
* SMTA published guidelines a few years ago.
* "Test & Design Strategies For Successful Testing Of SMT High-Density PCBs"
Hanson, RJ, Americom Test [800-650-3033], although little more than a
fleshed-out seminar hand-out, is the most coherent text on the topic.
* Old dogs gaze longingly at Scheiber "Building a Successful Board-Test
Strategy" as manna. So, thankfully Butterworth-Heinemann updated it in 2001
[ISBN 0750672803], although I have not seen the book. I'm still entranced
with the 1995 edition.
Dave Fish
----- Original Message -----
From: "Tempea, Ioan" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, February 14, 2002 5:44 AM
Subject: [TN] Standards for testing
> Hi again,
>
> is there any IPC standard, or any standard, covering ICT, functional and
> system testing?
>
> What I'm looking for are some guidelines on:
> * how to decide what tests are necessary according to the end usage
> * sampling vs. 100% testing
> * burn-in or environmental tests needed or not
>
> Thank you,
>
> Ioan
>
> --------------------------------------------------------------------------
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Date: Fri, 15 Feb 2002 10:41:30 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Subject: Re: Proving the reliability of a solder joint
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
PLease, can you advise where and how can I obtain this CD as well?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
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Date: Thu, 14 Feb 2002 15:47:58 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Axton <[log in to unmask]>
Subject: Re: CAD Database file v/s Netlist file
X-To: Ken Patel <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Ken,
Most fab shops are using CAM based tools (Valor Genesis, Barco U-CAM,
Lavenir, IGI, etc)
and can only deal with standard data formats (ODB++, RS-274X, DPF, GEN-CAM,
IPC-350, etc).
Extracting the IPC-D-356x net list from a PADS database (ASCII) requires CAD
tools, or
third party programs...
You may be able to outsource the extraction to a design service, or find a
PCB fab shop
with in-house design services, cad tools (PADS) and skill sets....(our
company has several
design centers and we perform this service on a regular basis...)
If you need assistance... you can contact me offline..
Jim Axton, Corp. Director of Test, DDi
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ken Patel
Sent: Thursday, February 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] CAD Database file v/s Netlist file
PCB Expert,
If I provide my fab house CAD database file in ASCII format, do I still
have to provide netlist in IPC-356 file format. Can fab house be able to
extract needed netlist info for testing purpose out of database file?
The dilemma I have is that my cad person do not know how to extract the
netlist file from PADS. Any help/clarification in this direction will be
appreciated.
Re,
Ken Patel
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Date: Thu, 14 Feb 2002 23:13:55 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Plating Audit Template
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_a0.222382b0.299de503_boundary"
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Content-Transfer-Encoding: 7bit
I concur with Denny Fritz. The IPC PCQR2 committee has designed a series of
"Test Vehicles " (TV) that are 18" X 24" and comes in 6 MLB versions:
- 6 layer (.031" or .062" thick ),
- 12 layer ( .062"thick ),
- 18 layer ( .093" thick )
- 24 layer (.125" or .250" thick )
Each TV is compromised of 352 modules (1.0 inch square each). Each module is
designed to asses a specific quality attribute and process capability.
Data (electrical test data) is collected from a test batch of 30 TV boards
processed simultaneously. The data is evaluated thru a proprietary software
and the process capability is assessed. The information is then stored in a
data base for reference.
Best Regards
George Milad
Chairman IPC Plating Committee
--part1_a0.222382b0.299de503_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I concur with Denny Fritz. The IPC PCQR2 committee has designed a series of "Test Vehicles " (TV) that are 18" X 24" and comes in 6 MLB versions:
<BR>- 6 layer (.031" or .062" thick ),
<BR>- 12 layer ( .062"thick ),
<BR>- 18 layer ( .093" thick )
<BR>- 24 layer (.125" or .250" thick )
<BR>
<BR>Each TV is compromised of 352 modules (1.0 inch square each). Each module is designed to asses a specific quality attribute and process capability.
<BR>Data (electrical test data) is collected from a test batch of 30 TV boards processed simultaneously. The data is evaluated thru a proprietary software and the process capability is assessed. The information is then stored in a data base for reference.
<BR>
<BR>Best Regards
<BR>George Milad
<BR>Chairman IPC Plating Committee
<BR>
<BR></FONT></HTML>
--part1_a0.222382b0.299de503_boundary--
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Date: Fri, 15 Feb 2002 07:28:03 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
praveen kumar manjeshwar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: praveen kumar manjeshwar <[log in to unmask]>
Subject: Micro lead frames
Mime-Version: 1.0
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Dear all,
I have been looking at websites for any information on Micro lead Frames
(MLFs). Right now i only have the application notes from Amkor.
I was wondering if any one can share some information (like a technical
literature)on issues from the assembly and reliability standpoint of MLFs.
Have any experiments been conducted with MLFs that one could share with me?
I am planning to conduct some experiments on my own, but prior to that I
wanted to gain a little insight into the issues handled by others.
Also, what is the minimum standoff height that is required in order to
ensure that the underside of the component can be completely cleaned of flux
residues during aqueous cleaning? Are there any standards for the same?
Thanks and have a nice day.
=======================================================================
M. Praveen Kumar
2021, North Milpitas Blvd., Apt #320,
Milpitas,
California:95035
Tel:(408) 719 1913
_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail.
http://www.hotmail.com
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Date: Fri, 15 Feb 2002 09:32:16 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Soldering Defects
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Hi Antonio,
I believe that http://www.smtinfocus.com has a few illustrated pages with =
soldering defects.=20
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Antonio Souza <[log in to unmask]> 02/14 5:57 pm >>>
Does anybody know where can I find free illustrations of soldering
conections of electronic components ?
thanks a lot
Antonio
Brazil
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Date: Fri, 15 Feb 2002 05:43:06 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
Folks,
Before I go down the reliability test road, using HALT/HAST, I woulld ask if
data or information exists in industry, as IPC or other, clearly correlating
design rule selections (BGA pad sizes, etc., manufacturing processes, etc.)
to that data? Most large companies in this business, as you all know,
continually develop this data and have clear evidence that if you use a
certain design rule and introduce the design to a certain process, a certain
product reliability factor will be realized.
Does the IPC, through its committee work and round robin testing, have such
data available? Seems like I know the answer, but may never have bothered to
ask before. This data must be available as the IPC could never have
developed its guidelines without it, right?
A little fuzzy after a rather interesting night out of my cave,
MoonMan
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Date: Fri, 15 Feb 2002 06:06:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Just a note of interest concerning the DSP/CSP devices from TI
Some of you may be interested in the following:
1) Starting at the top, the top cover on the TI 6203 DSP/CSP's is aluminum
going to copper plated with something then evolving soon into a glob top
2) The top currently used is only attached to the die - not to the BGA
substrate. Interesting MSD issues as class 4 sensitive devices and all that
entails. Also, the lid could not impose stresses on the BGA substrate
causing excessive warp issues.
3) The flip chip is attached, via "normal" industry bonding and underfill
techniques.
4) The BGA substrate is BT and is 6 layers going to two. Don't know how
they're going to accomplish this feat.
5) Our "X" version parts had BGA balls falling off the substrate first
because of a "bad supplier/process" or some such thing. Others fell off
because of our "bad supplier/process" wherein an adequate thermal profile
could not be achieved. The oven was a Heller 1700 though I belive it
capable, the supplier could not get the recipe and cold solder joints were
effected also causing balls to detach from both substrates.
6) I'll keep you posted as we build new boards and run the reliability
testing.
MoonMan
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Date: Fri, 15 Feb 2002 06:22:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: INDEPENDENT TEST LABS FOR HALT/HAST
I know a couple, but could anyone provide me with some more info concerning
independent test labs capable of doing HALT and/or HAST. I need to test some
assemblies with various component types including some DSP/CSP's. Primary
focus on solder joints, of course.
Thanks,
MoonMan
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Date: Fri, 15 Feb 2002 14:11:31 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Tegehall Per-Erik <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tegehall Per-Erik <[log in to unmask]>
Subject: Re: INDEPENDENT TEST LABS FOR HALT/HAST
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
It depends on what you mean with independent, but QualMark has a number =
of
test labs for HALT/HASS. If you look at their webpage you will find the
addresses (www.qualmark.com).
Per-Erik Tegehall
IVF, Sweden=20
-----Ursprungligt meddelande-----
Fr=E5n: Earl Moon [mailto:[log in to unmask]]
Skickat: den 15 februari 2002 13:23
Till: [log in to unmask]
=C4mne: [TN] INDEPENDENT TEST LABS FOR HALT/HAST
I know a couple, but could anyone provide me with some more info =
concerning
independent test labs capable of doing HALT and/or HAST. I need to test =
some
assemblies with various component types including some DSP/CSP's. =
Primary
focus on solder joints, of course.
Thanks,
MoonMan
------------------------------------------------------------------------=
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Technet NOMAIL
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Date: Fri, 15 Feb 2002 08:18:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: Micro lead frames
X-To: praveen kumar manjeshwar <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Praveen
we've been using amkor mlf packages for some times now and we assembled them
in house, manually. So far we had no major issues. We specify a drill hole
for the paddle and
soldering it for good ground.
-----Original Message-----
From: praveen kumar manjeshwar [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 2:28 AM
To: [log in to unmask]
Subject: [TN] Micro lead frames
Dear all,
I have been looking at websites for any information on Micro lead Frames
(MLFs). Right now i only have the application notes from Amkor.
I was wondering if any one can share some information (like a technical
literature)on issues from the assembly and reliability standpoint of MLFs.
Have any experiments been conducted with MLFs that one could share with me?
I am planning to conduct some experiments on my own, but prior to that I
wanted to gain a little insight into the issues handled by others.
Also, what is the minimum standoff height that is required in order to
ensure that the underside of the component can be completely cleaned of flux
residues during aqueous cleaning? Are there any standards for the same?
Thanks and have a nice day.
=======================================================================
M. Praveen Kumar
2021, North Milpitas Blvd., Apt #320,
Milpitas,
California:95035
Tel:(408) 719 1913
_________________________________________________________________
Join the world's largest e-mail service with MSN Hotmail.
http://www.hotmail.com
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Date: Fri, 15 Feb 2002 09:11:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Lambert, Katherine A." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lambert, Katherine A." <[log in to unmask]>
Subject: Where's your cleaning equipment?
MIME-Version: 1.0
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this format, some or all of this message may not be legible.
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Content-Type: text/plain;
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Hi folks,
We are in the process of rethinking the configuration of our automated
lines. Currently, after reflow, boards are loaded into magazines and onto
carts and transported to the cleaning room, which houses our cleaning
equipment including an in-line cleaner. Although no one wants to admit it,
it may be several hours or several days before the boards get cleaned (big
shudder). Several of us are giving thought to putting small footprint
in-line cleaners at the end of the reflow ovens. We are fairly small
volume, but high mix house. On a good day, boards come out of the reflow
ovens once every 2-3 minutes. We know that there are some technical issues
to resolve - making sure boards aren't too hot going into the cleaner,
aligning them after cleaning & before the magazine loader, etc.
The questions I have are:
1. Does anyone out there actually have this sort of cleaning configuration
& how has it worked?
2. Is this totally crazy?
3. Is there anything else I need to consider (other than the safety &
industrial hygiene sorts of things)?
Thanks,
Kathie Lambert
SMT Process Engineer
Northrop Grumman
Baltimore, MD
------_=_NextPart_001_01C1B62A.9CEC5460
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4616.200" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>Hi
folks,</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>We are
in the process of rethinking the configuration of our automated lines.
Currently, after reflow, boards are loaded into magazines and onto carts and
transported to the cleaning room, which houses our cleaning equipment including
an in-line cleaner. Although no one wants to admit it, it may be several
hours or several days before the boards get cleaned (big shudder). Several
of us are giving thought to putting small footprint in-line cleaners at the end
of the reflow ovens. We are fairly small volume, but high mix house.
On a good day, boards come out of the reflow ovens once every 2-3 minutes.
We know that there are some technical issues to resolve - making sure boards
aren't too hot going into the cleaner, aligning them after cleaning & before
the magazine loader, etc.</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>The
questions I have are:</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>1. Does anyone out there actually have this sort of cleaning
configuration & how has it worked?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>2. Is this totally crazy?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>3. Is there anything else I need to consider (other than the safety
& industrial hygiene sorts of things)?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>Kathie
Lambert</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>SMT
Process Engineer</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Northrop Grumman</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Baltimore, MD</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial color=#0000ff
size=2></FONT> </BLOCKQUOTE></BODY></HTML>
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Date: Fri, 15 Feb 2002 14:16:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
X-To: Earl Moon <[log in to unmask]>
X-cc: TONY GORDON <[log in to unmask]>
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Earl
I recently ran a seminar for the British SMART Group called: Design for
Reliability in a Lead-Free World.
We at the SMART Group are proposing to make a copy of all the presentations
on a CD for a small fee - to be decided.
If you or anyone else would wish to buy a copy, please let me know.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: 15 February 2002 11:43
> To: [log in to unmask]
> Subject: [TN] RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
>
>
> Folks,
>
> Before I go down the reliability test road, using HALT/HAST, I
> would ask if
> data or information exists in industry, as IPC or other, clearly
> correlating
> design rule selections (BGA pad sizes, etc., manufacturing
> processes, etc.)
> to that data? Most large companies in this business, as you all know,
> continually develop this data and have clear evidence that if you use a
> certain design rule and introduce the design to a certain
> process, a certain
> product reliability factor will be realized.
>
> Does the IPC, through its committee work and round robin testing,
> have such
> data available? Seems like I know the answer, but may never have
> bothered to
> ask before. This data must be available as the IPC could never have
> developed its guidelines without it, right?
>
> A little fuzzy after a rather interesting night out of my cave,
>
> Moon Man
>
> ------------------------------------------------------------------
> ---------------
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> additional
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
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>
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Date: Fri, 15 Feb 2002 09:10:07 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
X-To: [log in to unmask]
Graham, and others,
Thanks for the input so far. I'm really very interested in all I've
received. I am interested in lead free reliability data but cannot apply
it in my current situation. Maybe the template and methods would be of
use.
I'm also interested in IPC-9701 and its contents concerning reliability
testing as well as IPC PCQR squared. 9701 is text book and straight
forward. However, I'm looking for industry data concerning overall product
reliability with particular focus on lead based solder joints.
The PCQR squared, and associated test elements (test vehicles and associated
test requirements/elements) is very interesting as well but seems in its
infancy. I had hoped there was more mature IPC data already available
without having to work so hard. Sorry Werner, but really I'm not lazy when
it comes to this stuff.
It seems I must go down a path using company specific test vehicles, as
current product, and do the testing myself - with an independent test lab
either internal to a parent company or outside it. Thanks Per-Erik for you
suggestion. And thanks also to Graham, Steve Sauer, and all others helping
thus far.
Finally, I've been told there is a software database program available that
analyzes an assembly BOM and derives test data on various parts on the BOM.
Does anyone know what this package is and has anyone in this group used it?
Earl
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Date: Fri, 15 Feb 2002 10:27:08 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: SOME VOIDING PICS
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi all!
Earl asked me to post some voiding pictures yesterday, but I wasn't able to
until now. The pictures are now up...
http://www.stevezeva.homestead.com
-Steve Gregory-
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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Earl asked me to post some voiding pictures yesterday, but I wasn't able to until now. The pictures are now up...
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>-Steve Gregory-</FONT></HTML>
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Date: Fri, 15 Feb 2002 10:33:19 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: thermocouple
MIME-Version: 1.0
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Thermocouples are placed within the lay up of a panel prior to lamination to
measure temperature during the lamination cycle. The type of thermocouple
used is quite large. I am concerned that the "hump" it creates affects the
location of nearby innerlayer targets at X-ray drill. I think is is
"dragging" the x-ray drill targets out of position. Targets are located
across the same end of the panel where the thermocouple is located.
It also corrupts data measured at the x-ray drill when the thermocouple lays
across the target area that is measured. The vision system sees the twisted
wire and processes that information.
Has anyone dealt with lamination thermocouples and these specific issues?
What are the best practices for dealing with this problem. Are smaller
thermocouples available?
Mark Julstrom
Multek Irvine
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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Thermocouples are placed within the lay up of a panel prior to lamination to measure temperature during the lamination cycle. The type of thermocouple used is quite large. I am concerned that the "hump" it creates affects the location of nearby innerlayer targets at X-ray drill. I think is is "dragging" the x-ray drill targets out of position. Targets are located across the same end of the panel where the thermocouple is located.
<BR>It also corrupts data measured at the x-ray drill when the thermocouple lays across the target area that is measured. The vision system sees the twisted wire and processes that information.
<BR>Has anyone dealt with lamination thermocouples and these specific issues? What are the best practices for dealing with this problem. Are smaller thermocouples available?
<BR>
<BR>Mark Julstrom
<BR>Multek Irvine</FONT></HTML>
--part1_a7.1ba891cd.299e843f_boundary--
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Date: Fri, 15 Feb 2002 10:44:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIG
X-To: [log in to unmask]
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Hi Graham
I would definitely be interested in purchasing a copy of the data on CD ROM.
Please provide cost and if possible a list of the topic/papers that will be
included.
best regards,
Faz,
(Dan Fazioli, Engrg Technical Mgr.
Smiths Aerospace Electronics Systems
Clearwater, Florida. 33772
727-532-6333)
____________________Reply Separator____________________
Subject: Re: [TN] RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN R
Author: Graham Naisbitt <[log in to unmask]>
Date: 2/15/2002 2:16 PM
Earl
I recently ran a seminar for the British SMART Group called: Design for
Reliability in a Lead-Free World.
We at the SMART Group are proposing to make a copy of all the presentations
on a CD for a small fee - to be decided.
If you or anyone else would wish to buy a copy, please let me know.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: 15 February 2002 11:43
> To: [log in to unmask]
> Subject: [TN] RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
>
>
> Folks,
>
> Before I go down the reliability test road, using HALT/HAST, I
> would ask if
> data or information exists in industry, as IPC or other, clearly
> correlating
> design rule selections (BGA pad sizes, etc., manufacturing
> processes, etc.)
> to that data? Most large companies in this business, as you all know,
> continually develop this data and have clear evidence that if you use a
> certain design rule and introduce the design to a certain
> process, a certain
> product reliability factor will be realized.
>
> Does the IPC, through its committee work and round robin testing,
> have such
> data available? Seems like I know the answer, but may never have
> bothered to
> ask before. This data must be available as the IPC could never have
> developed its guidelines without it, right?
>
> A little fuzzy after a rather interesting night out of my cave,
>
> Moon Man
>
**********************************************************************
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If you have received this e-mail in error please notify the e-mail
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Date: Fri, 15 Feb 2002 09:51:56 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: SOME VOIDING PICS
X-To: [log in to unmask]
Steve,
My thanks as always. Just some notes about the pics:
1) The gull wing lead clearly shows indications of over heating during
reflow as the solder wicked way up the lead. Lot's of focused IR crap in
those days.
2) The J lead solder joint (solder really never wetted to the lead but did
to the board) cracked because of excessively oxidized leads. About all this
customer's product was wiped out because the component supplier, a big one
at that, screwed up.
3) The two chip device voidings were found after soldering them to a ceramic
substrate and then simply pulled off it. We were talking about these
substrates before and I forgot to mention Coors and Kyocera both provide two
inch, or so, square samples. I always carry about half a dozen of them
around until the break - then I get new ones.
Enjoy,
Earl
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Date: Fri, 15 Feb 2002 15:56:19 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: Guenter Grossmann <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Guenter
Your information is not accurate for all VP systems. Note that the term
Condensation Soldering (CS) also applies.
Our system, for SAC alloy melting at 218 DegC uses a 230 DegC boiling point
fluid. The actual temperature delta over melting / eutectic is less than 5
DegC.
In conventional convection ovens, the temp delta may well be 30 to 50DegC
over melting/eutectic, and this might explain the 270 DegC comment. There
are fluids with a 270 DegC boiling point, but they should not be required in
this process.
With a VP or CS type system, the vapour simply condenses onto all surfaces
that are colder than it, thus it is fast but controllable.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Guenter Grossmann
> Sent: 14 February 2002 16:44
> To: [log in to unmask]
> Subject: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
>
>
> Jim
>
> I believe the VP is still a good principle. However, the
> industrial partner in LEADFREE that runs the VP trials told me
> that he has to use a liquid with a boiling point of 270 deg.C and
> that there is nothing available that boils around 230 deg.
> I had problem to believe this but also after asking again I got
> the same answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
> ------------------------------------------------------------------
> ---------------
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> ------------------------------------------------------------------
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>
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Date: Fri, 15 Feb 2002 07:56:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: thermocouple
X-To: [log in to unmask]
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charset="iso-8859-1"
hi,
ohmega engineering has tc wires down to 1 mil. that should be small enough shouldn't it?
phil
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 7:33 AM
To: [log in to unmask]
Subject: [TN] thermocouple
Thermocouples are placed within the lay up of a panel prior to lamination to measure temperature during the lamination cycle. The type of thermocouple used is quite large. I am concerned that the "hump" it creates affects the location of nearby innerlayer targets at X-ray drill. I think is is "dragging" the x-ray drill targets out of position. Targets are located across the same end of the panel where the thermocouple is located.
It also corrupts data measured at the x-ray drill when the thermocouple lays across the target area that is measured. The vision system sees the twisted wire and processes that information.
Has anyone dealt with lamination thermocouples and these specific issues? What are the best practices for dealing with this problem. Are smaller thermocouples available?
Mark Julstrom
Multek Irvine
------_=_NextPart_001_01C1B639.607B29C0
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=042155615-15022002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=042155615-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=042155615-15022002><FONT face=Arial color=#0000ff size=2>ohmega
engineering has tc wires down to 1 mil. that should be small enough
shouldn't it?</FONT></SPAN></DIV>
<DIV><SPAN class=042155615-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=042155615-15022002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, February 15, 2002 7:33
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN]
thermocouple<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT
size=2>Thermocouples are placed within the lay up of a panel prior to
lamination to measure temperature during the lamination cycle. The type
of thermocouple used is quite large. I am concerned that the "hump" it
creates affects the location of nearby innerlayer targets at X-ray drill.
I think is is "dragging" the x-ray drill targets out of position.
Targets are located across the same end of the panel where the
thermocouple is located. <BR>It also corrupts data measured at the x-ray drill
when the thermocouple lays across the target area that is measured. The
vision system sees the twisted wire and processes that information. <BR>Has
anyone dealt with lamination thermocouples and these specific issues?
What are the best practices for dealing with this problem. Are
smaller thermocouples available? <BR><BR>Mark Julstrom <BR>Multek
Irvine</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Fri, 15 Feb 2002 11:19:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Where's your cleaning equipment?
X-To: "Lambert, Katherine A." <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Our in-line aqueous cleaner is positioned after our reflow oven. The boards
cool sufficiently after exiting the oven and before entering the first wash.
(Check your paste datasheet. Some vendors want the board to be warm when it
goes into the wash.) You can even add a short conveyor section between the
two if you like, but we did not find that necessary. It may depend on how
the on load end of your cleaner is configured as to whether a conveyor
section is needed or not. Like you, we are low volume, high mix. I have a
flat belt accumulating conveyor with sensors at the end of the cleaner so
operators don't have to be running to the back of the cleaner whenever a
board comes out. This has worked very well for us. It insures the boards are
cleaned in a timely manner and reduces handling (no batching and carting
boards around between soldering and cleaning.)
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Lambert, Katherine A.
Sent: Friday, February 15, 2002 9:11 AM
To: [log in to unmask]
Subject: [TN] Where's your cleaning equipment?
Hi folks,
We are in the process of rethinking the configuration of our automated
lines. Currently, after reflow, boards are loaded into magazines and onto
carts and transported to the cleaning room, which houses our cleaning
equipment including an in-line cleaner. Although no one wants to admit it,
it may be several hours or several days before the boards get cleaned (big
shudder). Several of us are giving thought to putting small footprint
in-line cleaners at the end of the reflow ovens. We are fairly small
volume, but high mix house. On a good day, boards come out of the reflow
ovens once every 2-3 minutes. We know that there are some technical issues
to resolve - making sure boards aren't too hot going into the cleaner,
aligning them after cleaning & before the magazine loader, etc.
The questions I have are:
1. Does anyone out there actually have this sort of cleaning
configuration & how has it worked?
2. Is this totally crazy?
3. Is there anything else I need to consider (other than the safety &
industrial hygiene sorts of things)?
Thanks,
Kathie Lambert
SMT Process Engineer
Northrop Grumman
Baltimore, MD
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<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D110433515-15022002><FONT face=3DArial size=3D2>Our =
in-line aqueous=20
cleaner is positioned after our reflow oven. The boards cool =
sufficiently=20
after exiting the oven and before entering the first wash. (Check your =
paste=20
datasheet. Some vendors want the board to be warm when it goes into the =
wash.)=20
You can even add a short conveyor section between the two if you like, =
but we=20
did not find that necessary. It may depend on how the on load end of =
your=20
cleaner is configured as to whether a conveyor section is needed or not. =
Like=20
you, we are low volume, high mix. I have a flat belt accumulating =
conveyor with=20
sensors at the end of the cleaner so operators don't have to be running =
to the=20
back of the cleaner whenever a board comes out. This has worked very =
well for=20
us. It insures the boards are cleaned in a timely manner and reduces =
handling=20
(no batching and carting boards around between soldering and cleaning.)=20
</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT =
size=3D2>Bob<BR><BR>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<BR>Robert=20
Barr<BR>Manufacturing Engineering<BR>Formation, Inc.<BR>Voice: =
856-234-5020=20
x3035<BR>Fax: 856-234-6679 </FONT></P>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid; MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Lambert, Katherine=20
A.<BR><B>Sent:</B> Friday, February 15, 2002 9:11 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Where's your cleaning=20
equipment?<BR><BR></FONT></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff size=3D2>Hi=20
folks,</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff size=3D2>We=20
are in the process of rethinking the configuration of our automated=20
lines. Currently, after reflow, boards are loaded into magazines =
and=20
onto carts and transported to the cleaning room, which houses our =
cleaning=20
equipment including an in-line cleaner. Although no one wants to =
admit=20
it, it may be several hours or several days before the boards get =
cleaned (big=20
shudder). Several of us are giving thought to putting small =
footprint=20
in-line cleaners at the end of the reflow ovens. We are fairly =
small=20
volume, but high mix house. On a good day, boards come out of =
the reflow=20
ovens once every 2-3 minutes. We know that there are some =
technical=20
issues to resolve - making sure boards aren't too hot going into the =
cleaner,=20
aligning them after cleaning & before the magazine loader,=20
etc.</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff size=3D2>The=20
questions I have are:</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>1. Does anyone out there actually have this sort =
of cleaning=20
configuration & how has it worked?</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>2. Is this totally crazy?</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>3. Is there anything else I need to consider (other =
than the=20
safety & industrial hygiene sorts of things)?</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Kathie Lambert</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff size=3D2>SMT=20
Process Engineer</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Northrop Grumman</FONT></SPAN></DIV>
<DIV><SPAN class=3D654164413-15022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Baltimore, MD</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px"><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT> </BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 15 Feb 2002 12:06:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Raymond <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: thermocouple
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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We are not a board fab house, but we use thermocouples that are 3 mil thick
to profile BGA solder joints, and I know that you can even buy 1 mil thick
thermocouple wire - I think the source we use is Omega
Engineering... http://www.omega.com
Bill...
At 10:33 AM 02/15/2002 -0500, you wrote:
>Thermocouples are placed within the lay up of a panel prior to lamination
>to measure temperature during the lamination cycle. The type of
>thermocouple used is quite large. I am concerned that the "hump" it
>creates affects the location of nearby innerlayer targets at X-ray
>drill. I think is is "dragging" the x-ray drill targets out of
>position. Targets are located across the same end of the panel where the
>thermocouple is located.
>It also corrupts data measured at the x-ray drill when the thermocouple
>lays across the target area that is measured. The vision system sees the
>twisted wire and processes that information.
>Has anyone dealt with lamination thermocouples and these specific
>issues? What are the best practices for dealing with this problem. Are
>smaller thermocouples available?
>
>Mark Julstrom
>Multek Irvine
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Date: Fri, 15 Feb 2002 17:08:59 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: thermocouple
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Hey Mark,
Sounds like you need to relocate your standard thermocouple wire location -
away from the X-ray targets and the lam. pins. What gauge wire are you
using?
For additional thermocouple options give http://www.omega.com
<http://www.omega.com> or http://www.thermX.com <http://www.thermX.com>
ThermX Southwest, Joe Skowronski (858) 573 - 0983 a try. Sorry, San Diego
is as close as I can get a supplier to you.
What kind of presses are you running? That can limit where you stick the
thermocouple.
I've seen new lamination workers placing the thermocouple in the wrong
place, additional training took care of it. For some reason they loved
sticking them into the test coupon area. It was very rare they'd hit an PLP
X-ray target.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask] <mailto:[log in to unmask]>
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 10:33 AM
To: [log in to unmask]
Subject: [TN] thermocouple
Thermocouples are placed within the lay up of a panel prior to lamination to
measure temperature during the lamination cycle. The type of thermocouple
used is quite large. I am concerned that the "hump" it creates affects the
location of nearby innerlayer targets at X-ray drill. I think is is
"dragging" the x-ray drill targets out of position. Targets are located
across the same end of the panel where the thermocouple is located.
It also corrupts data measured at the x-ray drill when the thermocouple lays
across the target area that is measured. The vision system sees the twisted
wire and processes that information.
Has anyone dealt with lamination thermocouples and these specific issues?
What are the best practices for dealing with this problem. Are smaller
thermocouples available?
Mark Julstrom
Multek Irvine
------_=_NextPart_001_01C1B643.75BA1D00
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>Hey
Mark,</FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>Sounds like you need to
relocate your standard thermocouple wire location - away from the
X-ray targets and the lam. pins. What gauge wire are you
using?</FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>For additional
thermocouple options give <A
href="http://www.omega.com">http://www.omega.com</A> or <A
href="http://www.thermX.com">http://www.thermX.com</A> ThermX Southwest,
Joe Skowronski (858) 573 - 0983 a try. Sorry, San Diego is as close as I
can get a supplier to you.</FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>What kind of presses are
you running? That can limit where you stick the
thermocouple.</FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>I've seen new
lamination workers placing the thermocouple in the wrong place, additional
training took care of it. For some reason they loved sticking them into
the test coupon area. It was very rare they'd hit an PLP X-ray
target. </FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=143255416-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=143255416-15022002>
<P><FONT size=2>Integrity First - Service Before Self -
Excellence in All We Do<BR>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>Hans M.
Hinners<BR>Electronics Engineer<BR>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)<BR>226 Cochran Street<BR>Robins AFB GA 31098-1622<BR><BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR><BR>Com:
(478) 926 - 5224<BR>Fax: (478) 926 - 4911<BR>DSN Prefix:
468<BR></FONT></P></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, February 15, 2002 10:33
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN]
thermocouple<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT
size=2>Thermocouples are placed within the lay up of a panel prior to
lamination to measure temperature during the lamination cycle. The type
of thermocouple used is quite large. I am concerned that the "hump" it
creates affects the location of nearby innerlayer targets at X-ray drill.
I think is is "dragging" the x-ray drill targets out of position.
Targets are located across the same end of the panel where the
thermocouple is located. <BR>It also corrupts data measured at the x-ray drill
when the thermocouple lays across the target area that is measured. The
vision system sees the twisted wire and processes that information. <BR>Has
anyone dealt with lamination thermocouples and these specific issues?
What are the best practices for dealing with this problem. Are
smaller thermocouples available? <BR><BR>Mark Julstrom <BR>Multek
Irvine</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 15 Feb 2002 18:27:47 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
praveen kumar manjeshwar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: praveen kumar manjeshwar <[log in to unmask]>
Subject: Re: Micro lead frames
Mime-Version: 1.0
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Safavi-Bayat Shahed,
Thanks a lot for your reply. Could you please elaborate on the point "We
specify a drill hole for the paddle and soldering it for good ground".
Suppose if I were to assemble this component using water soluble paste, what
should be the minimum standoff height of the component for it to be cleaned
underneath? Are there any specifications on this regard that you could share
with me?
Thanks and have a nice day.
Praveen
>From: Safavi-Bayat Shahed <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, Safavi-Bayat Shahed
><[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Micro lead frames
>Date: Fri, 15 Feb 2002 08:18:22 -0500
>
>Praveen
>we've been using amkor mlf packages for some times now and we assembled
>them
>
>in house, manually. So far we had no major issues. We specify a drill hole
>for the paddle and
>soldering it for good ground.
>
>-----Original Message-----
>From: praveen kumar manjeshwar [mailto:[log in to unmask]]
>Sent: Friday, February 15, 2002 2:28 AM
>To: [log in to unmask]
>Subject: [TN] Micro lead frames
>
>
>Dear all,
>
>I have been looking at websites for any information on Micro lead Frames
>(MLFs). Right now i only have the application notes from Amkor.
>
>I was wondering if any one can share some information (like a technical
>literature)on issues from the assembly and reliability standpoint of MLFs.
>Have any experiments been conducted with MLFs that one could share with me?
>
>I am planning to conduct some experiments on my own, but prior to that I
>wanted to gain a little insight into the issues handled by others.
>
>Also, what is the minimum standoff height that is required in order to
>ensure that the underside of the component can be completely cleaned of
>flux
>residues during aqueous cleaning? Are there any standards for the same?
>
>Thanks and have a nice day.
>========================================================================
>M. Praveen Kumar
>2021, North Milpitas Blvd., Apt #320,
>Milpitas,
>California:95035
>Tel:(408) 719 1913
>
>
>_________________________________________________________________
>Join the world's largest e-mail service with MSN Hotmail.
>http://www.hotmail.com
>
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Date: Fri, 15 Feb 2002 14:15:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: Micro lead frames
X-To: praveen kumar manjeshwar <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Praveen
As I mentioned we assemble manually and for the metal pad under the chip we
add a drill hole so be able to get solder flow easily under the chip.
Amkor has a good document is called " Application Notes for Surface Mount
Assembly of Amkor
Micro Lead Frame (MLF) Packages" which you can find on their web side.
Good Luck.
Shahed
-----Original Message-----
From: praveen kumar manjeshwar [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 1:28 PM
To: [log in to unmask]
Subject: Re: [TN] Micro lead frames
Safavi-Bayat Shahed,
Thanks a lot for your reply. Could you please elaborate on the point "We
specify a drill hole for the paddle and soldering it for good ground".
Suppose if I were to assemble this component using water soluble paste, what
should be the minimum standoff height of the component for it to be cleaned
underneath? Are there any specifications on this regard that you could share
with me?
Thanks and have a nice day.
Praveen
>From: Safavi-Bayat Shahed <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, Safavi-Bayat Shahed
><[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Micro lead frames
>Date: Fri, 15 Feb 2002 08:18:22 -0500
>
>Praveen
>we've been using amkor mlf packages for some times now and we assembled
>them
>
>in house, manually. So far we had no major issues. We specify a drill hole
>for the paddle and
>soldering it for good ground.
>
>-----Original Message-----
>From: praveen kumar manjeshwar [mailto:[log in to unmask]]
>Sent: Friday, February 15, 2002 2:28 AM
>To: [log in to unmask]
>Subject: [TN] Micro lead frames
>
>
>Dear all,
>
>I have been looking at websites for any information on Micro lead Frames
>(MLFs). Right now i only have the application notes from Amkor.
>
>I was wondering if any one can share some information (like a technical
>literature)on issues from the assembly and reliability standpoint of MLFs.
>Have any experiments been conducted with MLFs that one could share with me?
>
>I am planning to conduct some experiments on my own, but prior to that I
>wanted to gain a little insight into the issues handled by others.
>
>Also, what is the minimum standoff height that is required in order to
>ensure that the underside of the component can be completely cleaned of
>flux
>residues during aqueous cleaning? Are there any standards for the same?
>
>Thanks and have a nice day.
>========================================================================
>M. Praveen Kumar
>2021, North Milpitas Blvd., Apt #320,
>Milpitas,
>California:95035
>Tel:(408) 719 1913
>
>
>_________________________________________________________________
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Date: Fri, 15 Feb 2002 13:24:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: HALT AND THE J LEAD IMAGE
I guess I'm going down the HALT highway. Not getting many responses dealing
specifically with design rule correlation to reliability data. Sure thought
it existed.
I also wanted mention, for those interested, the J lead image Steve posted
exhibited some other interesting qualities, or not. I tried finding the pic
showing where I poked a pin into the solder joint. It showed flux, or what
remained of it, oozing out of the "joint."
I'll try and find it as, to me, is one of the more bazaar and interesting
photos I've ever taken. It represents flux remaining in the void/crack
staying behind to fight tooth decay, or was that the excessive lead oxidation.
MoonMan
Has anyone noticed this is an extra quiet day on the forum? Vacation time?
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Date: Fri, 15 Feb 2002 14:33:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Nicholas Ghareeb <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Nicholas Ghareeb <[log in to unmask]>
Subject: Re: Where's your cleaning equipment?
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Kathie,
We are also a low volume high mix production facility. We have our cleaners
set up at the end of our lines with a conveyor and sensors in between to
assure adequate spacing and cooling times. Our cycle time through the line
is a bit longer than yours as we do many very large complex boards, but we
have had no problems here with that set-up.
Good Luck.
Nick Ghareeb
Manufacturing Engineering
CCA Center of Excellence
Raytheon A/MDS
Andover, MA
>From: "Lambert, Katherine A." <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, "Lambert, Katherine
>A." <[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] Where's your cleaning equipment?
>Date: Fri, 15 Feb 2002 09:11:08 -0500
>
>Hi folks,
>
>We are in the process of rethinking the configuration of our automated
>lines. Currently, after reflow, boards are loaded into magazines and onto
>carts and transported to the cleaning room, which houses our cleaning
>equipment including an in-line cleaner. Although no one wants to admit it,
>it may be several hours or several days before the boards get cleaned (big
>shudder). Several of us are giving thought to putting small footprint
>in-line cleaners at the end of the reflow ovens. We are fairly small
>volume, but high mix house. On a good day, boards come out of the reflow
>ovens once every 2-3 minutes. We know that there are some technical issues
>to resolve - making sure boards aren't too hot going into the cleaner,
>aligning them after cleaning & before the magazine loader, etc.
>
>The questions I have are:
>1. Does anyone out there actually have this sort of cleaning configuration
>& how has it worked?
>2. Is this totally crazy?
>3. Is there anything else I need to consider (other than the safety &
>industrial hygiene sorts of things)?
>
>Thanks,
>
>Kathie Lambert
>SMT Process Engineer
>Northrop Grumman
>Baltimore, MD
>
>
>
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Date: Fri, 15 Feb 2002 20:49:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: HALT AND THE J LEAD IMAGE
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi ya Moonman,
Too many arrows from cupid's bow last night and the Monday holiday. ;-)
It can't last though. I'm getting too much work done!!!
Hans
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 2:25 PM
To: [log in to unmask]
Subject: [TN] HALT AND THE J LEAD IMAGE
I guess I'm going down the HALT highway. Not getting many responses dealing
specifically with design rule correlation to reliability data. Sure thought
it existed.
I also wanted mention, for those interested, the J lead image Steve posted
exhibited some other interesting qualities, or not. I tried finding the pic
showing where I poked a pin into the solder joint. It showed flux, or what
remained of it, oozing out of the "joint."
I'll try and find it as, to me, is one of the more bazaar and interesting
photos I've ever taken. It represents flux remaining in the void/crack
staying behind to fight tooth decay, or was that the excessive lead
oxidation.
MoonMan
Has anyone noticed this is an extra quiet day on the forum? Vacation time?
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Date: Fri, 15 Feb 2002 12:58:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Delamination
X-To: "Foote, Jeffery" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jeff
Are you sure it's the laminate side of the copper? With reverse-treat
foils, the tooth side may be adjacent to the prepreg bonding sheets rather
than the laminate.
> ----------
> From: Foote, Jeffery[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Foote, Jeffery
> Sent: Thursday, February 14, 2002 8:18 AM
> To: [log in to unmask]
> Subject: Re: [TN] Delamination
>
> Rudy, You are correct the boards do not have buried vias, but the
> delamination does not necessarily locate adjacent to a hole. Tests on
> bare
> boards showed that they do occur primarily at one end of the PWB on layer
> 5
> of 8. The delaminations occur on the "sawtooth" side of the copper.
> Additionally, examination through the laminate on the secondary side
> (layer
> 8) revealed black patchy areas over large land patterns or ground planes
> on
> layer 7. These also occur on the sawtooth side of the copper. Although
> these areas have not delaminated, I have confirmed that the laminate resin
> does not bond to these areas and EDS showed the same presence of sulfur
> and
> tin that was observed on the delaminated surfaces. Do you know what
> chemical preparation the sawtooth side of the copper is exposed to in
> order
> to improve adhesion?
>
> Thanks Rudy for your time.
> Best Regards,
> Jeff
>
> -----Original Message-----
> From: [log in to unmask] [mailto:[log in to unmask]]
> Sent: Wednesday, February 13, 2002 3:33 PM
> To: [log in to unmask]
> Subject: [TN] Delamination
>
>
> In a message dated 2/13/02 2:58:07 PM Pacific Standard Time,
> [log in to unmask]
> writes:
>
> << I am looking for some information regarding the preparation of copper
> foil
> for adhesion to internal laminate layers in the construction of PWBs. I
> am
> presently experiencing delamination of the copper from the laminate
> prepreg
> on an internal layer after IR reflow exposure. EDS of the delaminated
> surfaces showed localized, high-concentration of sulfur and tin on the
> copper surface >>
>
> Jeff: I assume that this delamination is occuring adjacent to drilled
> holes?
> These are not buried via boards are they?
>
> Rudy Sedlak
> RD Chemical Company
>
> --------------------------------------------------------------------------
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Date: Fri, 15 Feb 2002 14:48:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Richard Carruth <[log in to unmask]>
Subject: Anodize part washing
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello all, I have a question regarding Type II Class II black anodize of
extruded aluminum. I have some extruded aluminum heatsinks that look really good
(dark black and uniform) coming into receiving inspection, however they become
very splotchy and blue colored after they are washed in our MCS100 cleaner with
Kyzen. Does anyone have any information they can share with me regarding this
issue. Our customer will absolutely not accept any non-uniform black anodize.
Richar Carruth
Quality Engineer
LaBarge Inc.
PH# 918-459-2346
[log in to unmask]
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Date: Fri, 15 Feb 2002 22:05:19 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
MIME-Version: 1.0
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boundary="----=_NextPart_000_00E9_01C1B66C.DB93BC20"
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charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
Hi Earl,
This sounds a little bit like what you're looking for, it's from =
http://www.teradyne.com/prods/cbt/products/soft-d2b/a3_ov.html:
"Teradyne GR Force/A3 is the industry leading test and inspection data =
preparation solution in the marketplace today.
Teradyne GR Force/A3 can translate over 30 of the most popular CAD =
design formats.
The software can also import Bill Of Material (BOM) information, =
automatically modify data according to user specified rules and part =
libraries, and automatically assign probe locations for in- circuit and =
flying probe testers. Teradyne GR Force/A3 is powerful, yet the =
intuitive environment provides fast program generation and optimization =
for all major test and inspection equipment vendors."
Daan Terstegge
http://www.smtinfo.net
Finally, I've been told there is a software database program available =
that
analyzes an assembly BOM and derives test data on various parts on the =
BOM.
Does anyone know what this package is and has anyone in this group =
used it?
Earl
=
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in
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[log in to unmask]: SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
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-------------------------------------------------------------------------=
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Content-Type: text/html;
charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1252">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>Hi Earl,</DIV>
<DIV> </DIV>
<DIV>This sounds a little bit like what you're looking for, it's from <A =
href=3D"http://www.teradyne.com/prods/cbt/products/soft-d2b/a3_ov.html">h=
ttp://www.teradyne.com/prods/cbt/products/soft-d2b/a3_ov.html</A>:</DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial>"Teradyne GR Force/A3 is the industry leading =
test and=20
inspection data preparation solution in the marketplace =
today.</FONT></DIV>
<DIV><FONT face=3DArial>Teradyne GR Force/A3 can translate over 30 of =
the most=20
popular CAD design formats.</FONT></DIV>
<DIV><FONT face=3DArial>The software can also import Bill Of Material =
(BOM)=20
information, automatically modify data according to user specified rules =
and=20
part libraries, and automatically assign probe locations for in- circuit =
and=20
flying probe testers. Teradyne GR Force/A3 is powerful, yet the =
intuitive=20
environment provides fast program generation and optimization for all =
major test=20
and inspection equipment vendors."</FONT></DIV>
<DIV><FONT face=3DArial></FONT> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV>http://<A href=3D"http://www.smtinfo.net">www.smtinfo.net</A></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"><BR>Finally,=20
I've been told there is a software database program available =
that<BR>analyzes=20
an assembly BOM and derives test data on various parts on the =
BOM.<BR>Does=20
anyone know what this package is and has anyone in this group used=20
=
it?<BR><BR>Earl<BR><BR>--------------------------------------------------=
-------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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temporarily halt=20
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Digest<BR>Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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ext.5315<BR>-------------------------------------------------------------=
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=========================================================================
Date: Fri, 15 Feb 2002 21:41:56 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Where's your cleaning equipment?
X-To: "Lambert, Katherine A." <[log in to unmask]>
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Hi Kathy,
My first shop had the setup you are proposing.
The Reflow oven's conveyor was in-line with the cleaner and as you point out
the boards can't go in hot. (It looks efficient for the dog & pony tours.)
So, operators would pull the boards off the conveyor by hand, walk a couple
of feet and rack them in an industrial sink. The boards would cool off, get
a prewash spray in the sink and then run through the aqueous cleaner. This
would happen within an hour depending on the batch size.
You aren't crazy - our assembly line didn't want to run assemblies through
the in-line cleaner until final clean (2 to 4 weeks after wave solder).
One thing to keep in mind, be careful which cleaning chemistry you are
using. We also had a manual cleaning station (fume hood) in the same area.
We used a variety of chemicals (Isopropyl Alcohol, Trans LC, etc.) - many
highly flammable. Not the greatest lay-out: highly flammable vapors and
liquids less than 10 feet from a high energy heat source.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask] <mailto:[log in to unmask]>
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Lambert, Katherine A. [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 9:11 AM
To: [log in to unmask]
Subject: [TN] Where's your cleaning equipment?
Hi folks,
We are in the process of rethinking the configuration of our automated
lines. Currently, after reflow, boards are loaded into magazines and onto
carts and transported to the cleaning room, which houses our cleaning
equipment including an in-line cleaner. Although no one wants to admit it,
it may be several hours or several days before the boards get cleaned (big
shudder). Several of us are giving thought to putting small footprint
in-line cleaners at the end of the reflow ovens. We are fairly small
volume, but high mix house. On a good day, boards come out of the reflow
ovens once every 2-3 minutes. We know that there are some technical issues
to resolve - making sure boards aren't too hot going into the cleaner,
aligning them after cleaning & before the magazine loader, etc.
The questions I have are:
1. Does anyone out there actually have this sort of cleaning configuration
& how has it worked?
2. Is this totally crazy?
3. Is there anything else I need to consider (other than the safety &
industrial hygiene sorts of things)?
Thanks,
Kathie Lambert
SMT Process Engineer
Northrop Grumman
Baltimore, MD
------_=_NextPart_001_01C1B669.96DC5D10
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>Hi
Kathy,</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>My first shop had the
setup you are proposing.</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>The Reflow oven's
conveyor was in-line with the cleaner and as you point out the boards can't go
in hot. (It looks efficient for the dog & pony
tours.)</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>So, operators would pull
the boards off the conveyor by hand, walk a couple of feet and rack them in an
industrial sink. The boards would cool off, get a prewash spray in the
sink and then run through the aqueous cleaner. This would happen within an
hour depending on the batch size.</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>You aren't crazy - our
assembly line didn't want to run assemblies through the in-line cleaner until
final clean (2 to 4 weeks after wave solder). </FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>One thing to keep in
mind, be careful which cleaning chemistry you are using. We also had a
manual cleaning station (fume hood) in the same area. We used a
variety of chemicals (Isopropyl Alcohol, Trans LC, etc.) - many highly
flammable. Not the greatest lay-out: highly flammable vapors and
liquids less than 10 feet from a high energy heat source.</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=306312715-15022002><FONT color=#0000ff>
<P><FONT size=2>Integrity First - Service Before Self -
Excellence in All We Do<BR>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>Hans M.
Hinners<BR>Electronics Engineer<BR>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)<BR>226 Cochran Street<BR>Robins AFB GA 31098-1622<BR><BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR><BR>Com:
(478) 926 - 5224<BR>Fax: (478) 926 - 4911<BR>DSN Prefix:
468<BR></FONT></P> </FONT></SPAN></DIV>
<DIV><SPAN class=306312715-15022002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Lambert, Katherine A.
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, February
15, 2002 9:11 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Where's
your cleaning equipment?<BR><BR></FONT></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>Hi
folks,</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>We
are in the process of rethinking the configuration of our automated
lines. Currently, after reflow, boards are loaded into magazines and
onto carts and transported to the cleaning room, which houses our cleaning
equipment including an in-line cleaner. Although no one wants to admit
it, it may be several hours or several days before the boards get cleaned (big
shudder). Several of us are giving thought to putting small footprint
in-line cleaners at the end of the reflow ovens. We are fairly small
volume, but high mix house. On a good day, boards come out of the reflow
ovens once every 2-3 minutes. We know that there are some technical
issues to resolve - making sure boards aren't too hot going into the cleaner,
aligning them after cleaning & before the magazine loader,
etc.</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>The
questions I have are:</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>1. Does anyone out there actually have this sort of cleaning
configuration & how has it worked?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>2. Is this totally crazy?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>3. Is there anything else I need to consider (other than the
safety & industrial hygiene sorts of things)?</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Kathie Lambert</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff size=2>SMT
Process Engineer</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Northrop Grumman</FONT></SPAN></DIV>
<DIV><SPAN class=654164413-15022002><FONT face=Arial color=#0000ff
size=2>Baltimore, MD</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px"><FONT face=Arial color=#0000ff
size=2></FONT> </BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Fri, 15 Feb 2002 16:49:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Yacovitch, Bill" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Yacovitch, Bill" <[log in to unmask]>
Subject: Re: Vacuolar porosity under leads
X-To: Jason Gregory <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jason,
I can't tell you off the top of my head where to get the data from, but I
can tell you that there are studies that address voids in solder joints.
If my memory serves me correctly, the final analysis showed that in most
cases the joints integrity was not effected. In fact, in many cases it was
actually enhanced. The reason was, that in those cases where cracks may
start to propagate in the joint, they stopped at the internal voids. Versus
continuing through the whole joint if it was solid.
Personally, I prefer to see a solid joint. But, given that it may not be
possible in specific cases then past studies and data supports it as being
robust.
These studies were focused on BGA joints big-time.
Bill Yacovitch
Principal Engineer, NPPI
Mercury Computer Systems
[log in to unmask]
-----Original Message-----
From: Jason Gregory [mailto:[log in to unmask]]
Sent: Thursday, February 14, 2002 9:06 AM
To: [log in to unmask]
Subject: [TN] Vacuolar porosity under leads
I have a question regarding vacuolar porosity under leads.
A potential customer has forwarded me some CAD data and will send me some
boards for me to inspect using our 5DX X-ray. His concerns are that during
reflow, the flux attempts to outgas and stops just short of total outgassing
when the joint solidifies. This situation then forms "pockets" in the joint
in the lead/pad interconnect.
My question is this - Has anyone done any studies regarding this phenomena
and if so, does this affect the integrity of the joint? My belief has always
been that the structure and formation of the heel portion of the joint
comprises the actual integrity of the joint and the toe fillet (or lack
thereof) does not play into the lifespan (or strength) of the joint.
Therefore, the lead/pad interconnect would also not be the main point of
contention.
In Alabama, we had some components (QFP48) that had a ground lug on the
bottom part of the package that was soldered to a pad directly beneath. The
lug was approximately 1mm by 1mm and the pad was approximately 7/10mm by
7/10mm. In this case, the porosity dilemma was evident. We would see,
through 3D laminography, that large voids were formed, causing roughly a 40%
or so decrease in actual solder interconnect area. Some playing around with
the reflow profile displayed better results, but never resolved the issue.
Any thoughts/comments would be greatly appreciated.
Thanks,
Jason Gregory
Software Specialist
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
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=========================================================================
Date: Fri, 15 Feb 2002 15:36:09 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Where's your cleaning equipment?
X-To: "Lambert, Katherine A." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Kathie: What you are proposing will certainly work. However if you are a
small volume operation can you really afford to put inline cleaners on each
line? Sounds expensive from a capital $ outlay and like a lot maintenance.
Don't forget even a "small footprint" inline cleaner must be sized right to
do a proper job of both cleaning and drying the assembly.
My guess is management after looking at the real cost will opt for better
coordination between the reflow and wash areas.
We considered this approach a while back and it didn't make good sense at
the time. Just my thoughts
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Lambert, Katherine A. [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 6:11 AM
To: [log in to unmask]
Subject: [TN] Where's your cleaning equipment?
Hi folks,
We are in the process of rethinking the configuration of our automated
lines. Currently, after reflow, boards are loaded into magazines and onto
carts and transported to the cleaning room, which houses our cleaning
equipment including an in-line cleaner. Although no one wants to admit it,
it may be several hours or several days before the boards get cleaned (big
shudder). Several of us are giving thought to putting small footprint
in-line cleaners at the end of the reflow ovens. We are fairly small
volume, but high mix house. On a good day, boards come out of the reflow
ovens once every 2-3 minutes. We know that there are some technical issues
to resolve - making sure boards aren't too hot going into the cleaner,
aligning them after cleaning & before the magazine loader, etc.
The questions I have are:
1. Does anyone out there actually have this sort of cleaning configuration
& how has it worked?
2. Is this totally crazy?
3. Is there anything else I need to consider (other than the safety &
industrial hygiene sorts of things)?
Thanks,
Kathie Lambert
SMT Process Engineer
Northrop Grumman
Baltimore, MD
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 15 Feb 2002 20:16:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
MIME-Version: 1.0
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Hi MoonMan,
I need to burst your bubble, but neither HALT nor HAST are accelerated
reliability tests, and therefore it is impossible to correlate the results
from HALT/HAST to design rule selections (BGA pad sizes, etc., manufacturing
processes, etc.) or other physical/material design parameters and the
resulting reliability for product in normal use. HALT/HAST serve the purpose
of extreme robustness tests, looking for weak spots, and cause failures with
damage mechansims and failure modes not found in product use.
HOWEVER, there sure are lots of data correlating the results from proper
accelerated reliability tests to design rule selections (BGA pad sizes, etc.,
manufacturing processes, etc.) or other physical/material design parameters
and the resulting reliability for product in normal use. That is how
IPC-SM-785, IPC-D279 and IPC-9701 were developed.
You have just been barking up the wrong tree--are there trees in your cave?
Werner
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=========================================================================
Date: Fri, 15 Feb 2002 21:16:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: thermocouple
MIME-Version: 1.0
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Hi Mark,
Your concern about too large thermocouples is appropriate--they definietely
impact the results. I did some work like this many years ago [Ref:
Engelmaier, W., "Thermal Characterization of Multilayer Printed Wiring Boards
During Lamination," Proc. 11th IEEE Electrical/Electronics Insulation Conf.,
Chicago, IL, October 1973, p. 208] and used 1-mil-diameter thermocouples--you
need to treat them gingerly however.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Fri, 15 Feb 2002 22:20:20 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: SNEC Meeting
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_168.8ec4c23.299f29f4_boundary"
--part1_168.8ec4c23.299f29f4_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
DON'T FORGET!!
MEETING OF THE SOUTHERN NEW ENGLAND CHAPTER
OF THE IPC DESIGNERS COUNCIL
Date: Wednesday, the 20th of February 2002
Where: Connies Restaurant - Derby, Ct.
Time: Networking 6:00pm, Meeting 7:00pm
Topic: Hidden Parameters Behind Full Library Development
This meeting will be the first part of a two part series on Library
development. When we hear the term "library development" the first thing that
comes to mind is making a pad-stack and associating it with the component
outline, schematic symbol, etc. However, library development includes many
issues that are more important. The truth becomes more evident as we apply
higher technology to our products.
The February session will be an exploratory session focusing on the issues
facing full library development. Issues such as part interchangeability,
testing parameters, electronic function or special assembly requirements are
just a few of the issues that need to be met.
We intend to develop a comprehensive list of these issues and share them with
several industry library developers. These developers represent the CAD
community as well as those that might have component libraries for sale.
We will then invite these industry leaders to our April meeting to share how
they address these issues. Hopefully we will have identified the strengths,
weaknesses and/or benefits of building your own, using an industry standard
or purchasing a library.
You are requested to RSVP Vin Stabile by end of business on Tuesday at (203)
225-9056 X4142 or [log in to unmask]
Directions to Connie's Restaurant:
Take Route 84 to Route 8 South.
Take Route 8 to Route 34, towards Derby.
Make a right turn at the SECOND traffic light.
Connies is one block, on the right.
--part1_168.8ec4c23.299f29f4_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT COLOR="#8000ff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>DON'T FORGET!!<BR>
<BR>
MEETING OF THE SOUTHERN NEW ENGLAND CHAPTER<BR>
OF THE IPC DESIGNERS COUNCIL<BR>
<BR>
Date: Wednesday, the 20th of February 2002<BR>
Where: Connies Restaurant - Derby, Ct.<BR>
<BR>
Time: Networking 6:00pm, Meeting 7:00pm<BR>
<BR>
Topic: Hidden Parameters Behind Full Library Development<BR>
<BR>
This meeting will be the first part of a two part series on Library development. When we hear the term "library development" the first thing that comes to mind is making a pad-stack and associating it with the component outline, schematic symbol, etc. However, library development includes many issues that are more important. The truth becomes more evident as we apply higher technology to our products.<BR>
<BR>
The February session will be an exploratory session focusing on the issues facing full library development. Issues such as part interchangeability, testing parameters, electronic function or special assembly requirements are just a few of the issues that need to be met. <BR>
<BR>
We intend to develop a comprehensive list of these issues and share them with several industry library developers. These developers represent the CAD community as well as those that might have component libraries for sale. <BR>
<BR>
We will then invite these industry leaders to our April meeting to share how they address these issues. Hopefully we will have identified the strengths, weaknesses and/or benefits of building your own, using an industry standard or purchasing a library.<BR>
<BR>
<BR>
You are requested to RSVP Vin Stabile by end of business on Tuesday at (203) 225-9056 X4142 or [log in to unmask]<BR>
<BR>
Directions to Connie's Restaurant:<BR>
<BR>
Take Route 84 to Route 8 South.<BR>
Take Route 8 to Route 34, towards Derby. <BR>
Make a right turn at the SECOND traffic light.<BR>
Connies is one block, on the right.<BR>
<BR>
</B></I></FONT></HTML>
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Date: Sat, 16 Feb 2002 00:08:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
X-To: [log in to unmask]
Oh Werner,
You sly old fox, or is it dog, you couldn't burst my bubble. It's been long
burst by Arleen Weinberger since we did it in the eighth grade, or was that
Lena Fowler (leaping Lena to you). Don't got no trees in my cave but the
roots sure do grow down here and there's always some dog at tree level
pissin' on them but that just don't bother me this deep.
I knew I could draw you out with my little questions about such a big
subject. Have gone over 279, 785, and 9701 many times. Mostly what I see is
your name as chair and co-chair on each committee. That ought to tell me
something, right? As fine as these documents are, they don't show me the
money/data.
Ok, I believe you and recognize what you say about HALT/HAST. How could I
not, but where's the BEEF? How and where do I get the data from which your
fine guidelines were produced, as you say? Some others don't understand and
want data about the product I am helping improve. They want data about how
long they can expect my boards will last in actual operation. In their
terms, they want MTBF numbers, right ot wrong.
So Werner, where's the beef?
MoonMan
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Date: Sat, 16 Feb 2002 09:51:34 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Where's your cleaning equipment?
X-To: "Lambert, Katherine A." <[log in to unmask]>
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Kathie
As a general rule, small footprint conveyorised machines may not give
you satisfaction. A reasonable wash will take 2-6 minutes and you should
have at least 3 rinse stages, each of a minute, to get minimally clean
results. Then you should have a couple of air knives (each side) and hot
air drying for another couple of minutes. Let's say, conservatively, the
cycle should last 10 minutes. A small conveyorised machine, say 2 m
long, would therefore need to run at about 10-15 cm/min (remember that
loading/unloading areas are usually at least 30 cm long, each, so your
active length is only 1 m 40). This may be insufficient for some
processes.
IMHO, a GOOD batch machine (and I don't mean batch washers with
inadequate pumps and heaters that take an hour or more per cycle) will
give you far more satisfaction. The loading/unloading of the baskets
should take no more labour than your current magazine and can usually
easily be done, especially at your low production rates, by the same
workers who look after the rest of your line. This will give you much
more flexibility (you can adjust the cleaning variables, e.g., wash,
rinse and dry times and temperatures to suit the nature of the product
and the process). With a good system, you can have one basket with 1 m2
of perfectly clean and dry boards coming out of your machine every 10
minutes, if production rates should rise.
Brian
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Date: Sat, 16 Feb 2002 10:01:23 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: Guenter Grossmann <[log in to unmask]>
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Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 °C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial partner in LEADFREE that runs the VP trials told me that he has to use a liquid with a boiling point of 270 deg.C and that there is nothing available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the same answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Sat, 16 Feb 2002 07:12:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
X-To: Daan Terstegge <[log in to unmask]>
Daan,
I don't know if the GR thing is it but it sure sounds interesting. Do you
know how long it's been around?
I got the info on the vague package I posted from some one in Bangkok. They
said, to someone else, there is a program that imports test data directly
from component supplier data sheets, or the stuff that went into them, and
renders long term reliability data from them, or some such thing. A bit
confusing considering how this message got to me and from where it came in
the first place.
Have a question for you and other computer wizards. My new hard drive seems
flakier than the others it replaced. Goes belly up once in awhile. Checked
for viruses, as I do very often and have my guard up all the time, and no
cigar. No problem replacing it again, if needed, but does anyone know what
would wipe out my inbox messages in Outlook Express? They vanished on my
last reboot.
Thanks,
MoonMan
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Date: Sat, 16 Feb 2002 07:53:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
X-To: [log in to unmask]
Werner, or may I call you Sir Werner,
I simply am in awe of all the work you've done in general and with IPC,
especially 279, 785, and 9701. Incredible, but I must ask how the hell can
you chair three comittees, be co-chair on another of the same comitte, and
find time to make a living notwithstanding visiting grand kids?
I have spent the last two days, though not nearly enought time, day and
night reading and reviewing and digesting all possible, for me, concerning
the trilogy. It's all there.
Never had any doubts about you Sir Werner. Never will.
Thanks for it all,
Out of the CaveMan forever,
MoonMan
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Date: Sat, 16 Feb 2002 17:46:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: HALT AND THE J LEAD IMAGE
X-To: Earl Moon <[log in to unmask]>
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An interesting article, but for 'members only'. Maybe your organization can
spring for it.
http://www.worldscinet.com/journals/jem/10/1001/S0960313100000058.html
RL
----- Original Message -----
From: Earl Moon <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, February 15, 2002 2:24 PM
Subject: [TN] HALT AND THE J LEAD IMAGE
> I guess I'm going down the HALT highway. Not getting many responses
dealing
> specifically with design rule correlation to reliability data. Sure
thought
> it existed.
>
> I also wanted mention, for those interested, the J lead image Steve posted
> exhibited some other interesting qualities, or not. I tried finding the
pic
> showing where I poked a pin into the solder joint. It showed flux, or what
> remained of it, oozing out of the "joint."
>
> I'll try and find it as, to me, is one of the more bazaar and interesting
> photos I've ever taken. It represents flux remaining in the void/crack
> staying behind to fight tooth decay, or was that the excessive lead
oxidation.
>
> MoonMan
>
> Has anyone noticed this is an extra quiet day on the forum? Vacation time?
>
> --------------------------------------------------------------------------
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>
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Date: Sun, 17 Feb 2002 08:22:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Alain Savard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Alain Savard <[log in to unmask]>
Subject: Assembly repair - Through hole
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Netters,
This is a question about assemblies being repaired because through holes are
damaged.
In IPC 7721, method 5.1 (no inner layer connection):
Should a jumper (or jumpers)be used to insure reliable electrical
conductivity for class 2 assemblies?
How about class 3?
How about for method 5.2 (with inner layer connection)?
Thanks in advance for all answers,
Alain Savard
QA - PCB
CAE Inc.
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Date: Mon, 18 Feb 2002 09:17:29 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: thermocouple
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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In another life we needed a zero dimension way of measuring temp in a
laminar construction and our R&D people found a supplier of thin film
thermocouples. These would seem to fit your bill.
As is the way of things these days the lab and people are long gone so can't
ask them supplier details for you, but maybe an Internet search or just
mentioning them here will turn something up.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Saturday, February 16, 2002 2:16 AM
To: [log in to unmask]
Subject: Re: [TN] thermocouple
Hi Mark,
Your concern about too large thermocouples is appropriate--they definietely
impact the results. I did some work like this many years ago [Ref:
Engelmaier, W., "Thermal Characterization of Multilayer Printed Wiring
Boards
During Lamination," Proc. 11th IEEE Electrical/Electronics Insulation Conf.,
Chicago, IL, October 1973, p. 208] and used 1-mil-diameter
thermocouples--you
need to treat them gingerly however.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Mon, 18 Feb 2002 06:19:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Antonio Souza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Antonio Souza <[log in to unmask]>
Subject: Reliability Testing of PTH
Please
Does anybody know any Guidelines for Accelerated Reliability Testing of PTH
?
thanks
Antonio
INPE-Brasil
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Date: Mon, 18 Feb 2002 21:40:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
makshuwing <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: makshuwing <[log in to unmask]>
Subject: High temperature solder wire
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PERJVj48Rk9OVCBzaXplPTI+SGFzIGFueW9uZSB1c2luZyB0aGlzIG1ldGhvZCBzZWVuIHByb2Js
ZW1zPzwvRk9OVD4mbmJzcDs8L0RJVj4NCjxESVY+PEZPTlQgc2l6ZT0yPjwvRk9OVD4mbmJzcDs8
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Rk9OVD48L0RJVj48L0JPRFk+PC9IVE1MPg0K
------=_NextPart_000_0056_01C1B8C4.EFEBE6C0--
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Date: Mon, 18 Feb 2002 08:44:48 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: Inspecting Wavesoldered bottom-side SMD joints
X-To: Bill Raymond <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Hi Bill, used to work with an airknife system years ago. The original intent
of the product was to remove any solder which had not adhered to the basis
material and to also remove excessive solder if it was webbed between
component leads i.e solder shorts. If the solder had not wetted to the pads
or was webbed between the component leads, then the molten metal would have
little or no adhesive forces to the product to secure the molten solder to
the joint and it would be removed by the air flow of the hot air knife. One
of the advantages of the air knife at that time was the thought that it
could inspect the solder joints as they were being created. By removing any
excess solder from the solder joints, one could determine whether or not the
intermetallic had been created. The intermetallic compound creates an
adhesive force between the molten tin and the basis copper material and the
air knife should not be able to remove this material.
I know that if the angle of the air knife is set incorrectly or the pressure
is too high, then any and all solder can be blown off any surface. So
assuming the angle and pressures are set correctly the results should be
solder joints that are created with just the correct amount of solder. This
is the type of solder joint which has wetted to the base material, leads and
boards, and any excess solder has been removed from the joint.
What should the joint look like? You mention insufficient solder? This is a
true catch all phrase in the industry. Provided the solder joints look meet
the requirements set forth, for example IPC-A-610, then you should have no
problem. If the process is blowing out the solder from the PTH then take a
look at the pressure and air flow of the system to verify its correctness.
Hope this helps, if not call me at 1 800 643-7822 or reach me offline at
[log in to unmask] and we can talk about it some more.
Regards, Leo Lambert
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bill Raymond
Sent: Wednesday, February 13, 2002 1:32 PM
To: [log in to unmask]
Subject: [TN] Inspecting Wavesoldered bottom-side SMD joints
Hi all,
I'm using a wave solder system with a hot air knife... the knife
reduces solder shorts just fine, however, the inspectors are finding "more"
insufficient solder joints. I've read articles _somewhere_, that when
using a hot air knife system, the joints will tend to look different and
that inspectors will need to be retrained as to what to look for. Can
anyone point me to a source of information??
Thanks, Bill...
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Date: Mon, 18 Feb 2002 08:34:15 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Reliability Testing of PTH
X-To: Antonio Souza <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
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Antonio,
"It depends"! (This statement is certainly getting worn out!)
The methods should be:
1. tailored to the worst case conditions of the projected end use environments and;
2. agreed upon by the vendor and the customer (in writing).
Beyond that it is a matter of budgets and how "lucky" do you feel.
Seriously folks, there is no set, carved in stone guidelines. Testing is very touchy. Changes in the
order of
accelerated loading performed (temp, vibration, humidity, contamination resistance, etc.) , the style,
and the amount
will result in wildly divergent numbers. There is no easy answer.
David A. Douthit
Manager
LoCan LLC
Antonio Souza wrote:
> Please
>
> Does anybody know any Guidelines for Accelerated Reliability Testing of PTH
> ?
>
> thanks
>
> Antonio
> INPE-Brasil
>
> ---------------------------------------------------------------------------------
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Date: Mon, 18 Feb 2002 10:46:14 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: IPC Expo 2002 - Plating Subcommittee 4-14
MIME-Version: 1.0
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The Plating Subcommittee 4-14 will meet at Expo 2002 in Longbeach CA , on
Tuesday March 26th,2002 at 1:30 - 5:00pm.
The subcommittee is reviewing comments to a final draft IPC-4552,
"Specifications for Electroless Nickel/Immersion Gold (ENIG) Plating for
Printed Circuits Boards" and is also pursuing UL Recognition of immersion
silver surface finishes for printed wiring boards in conjunction with the UL
Task Group,3-11f.
The agenda will include updates on existing activities and the determination
of the next topic for "Standard Development". Presently on the list are
additional "Surface Finish" specifications, however the committee is open to
suggestions and priorities from the membership.
As part of the standards development working meetings, you can help develop
internationally recognized documents for PWB component and materials. You'll
be on the cutting edge of PWB design, manufacture and use.
The session is open to all and the Committee welcomes your contribution and
your input.
George Milad
Chairman
Plating Committee 4-14
[log in to unmask]
(516) 901-3874
--part1_8b.13f3aeb7.29a27bc6_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>The Plating Subcommittee 4-14 will meet at Expo 2002 in Longbeach CA , on Tuesday March 26th,2002 at 1:30 - 5:00pm.
<BR>
<BR>The subcommittee is reviewing comments to a final draft IPC-4552, "Specifications for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Circuits Boards" and is also pursuing UL Recognition of immersion silver surface finishes for printed wiring boards in conjunction with the UL Task Group,3-11f.
<BR>
<BR>The agenda will include updates on existing activities and the determination of the next topic for "Standard Development". Presently on the list are additional "Surface Finish" specifications, however the committee is open to suggestions and priorities from the membership.
<BR>
<BR>As part of the standards development working meetings, you can help develop internationally recognized documents for PWB component and materials. You'll be on the cutting edge of PWB design, manufacture and use.
<BR>
<BR>The session is open to all and the Committee welcomes your contribution and your input.
<BR>
<BR>George Milad
<BR>Chairman
<BR>Plating Committee 4-14
<BR>[log in to unmask]
<BR>(516) 901-3874
<BR>
<BR>
<BR>
<BR>
<BR></FONT></HTML>
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Date: Mon, 18 Feb 2002 07:53:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Butman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Butman <[log in to unmask]>
Subject: Re: Assembly repair - Through hole
X-To: Alain Savard <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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HI Alain,
Regarding your damaged PTH. Assuming that the lands,
and any circuitry connected to the lands, are still
good ---- jumper wires are not needed to insure a
reliable electrical connection.
That said. During the repair, first the lands should
be tinned with solder, and once the “correctly sized”
eyelet is installed, the eyelet flanges must be
soldered to the lands.
The forming of the eyelets will create a “mechanical”
connection to the lands, but it is the solder joint
that makes the reliable electrical connection.
OOPs, the technicians at CAE damaged the circuitry
connected to the land, or the land is missing. Now
you use a jumper wire. A flat, ribbon of wire
(Circuit Track material) makes a nicer looking repair.
To make this type of repair: 1. remove the solder
mask from a portion of the existing circuitry and tin
with solder. 2. Clean and tin a jumper
wire/conductor, or ribbon, and lap solder this to the
newly tinned existing circuitry. Note the minimum
over lap requirement of the IPC-7721 procedure 5.1 3.
Insert the other end of the jumper wire/conductor, or
ribbon into the prepared PTH. 4. Insert the
“correctly sized” eyelet into the prepared PTH, such
that the “factory flange” of the eyelet will “trap”
the jumper wire/conductor that is in the PTH. (
Looking at IPC-7721, procedure 5.1, Figure 2. Can you
see the “trapped conductor” coming from the upper left
corner of the figure, and being held by the factory
flange of the eyelet?) Let the jumper wire/conductor
enter the prepared PTH at least 50% of the PCB
thickness. But not so far as to interfere with the
forming of the flange on the opposite side of the PCB.
5. Form the eyelet, and solder the flanges to the
circuitry. 6. Coat the jumper wire/conductor with
epoxy to insulate it, and secure it to the PCB.
Regarding the reliability of the repair. I direct you
back to IPC-7721, page 2. section 1.4.3 “levels of
conformance”. Read the paragraph that starts with,
“Class 3 Products must use procedures rated Higest
level-------.” Note that Procedure 5.1 is rated as
Highest level of conformance.
I do hope that this will help you. You may contact me
off line if you want to kick this around some more:
978-264-0078
Thanx
Bill Butman
**************************************
--- Alain Savard <[log in to unmask]> wrote:
> Hi Netters,
>
> This is a question about assemblies being repaired
> because through holes are
> damaged.
>
> In IPC 7721, method 5.1 (no inner layer connection):
>
> Should a jumper (or jumpers)be used to insure
> reliable electrical
> conductivity for class 2 assemblies?
> How about class 3?
>
> How about for method 5.2 (with inner layer
> connection)?
>
> Thanks in advance for all answers,
>
> Alain Savard
> QA - PCB
> CAE Inc.
>
>
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=====
Bill Butman
Circuit Technology Center
45 Research Drive
Haverhill, MA 01832
__________________________________________________
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Date: Mon, 18 Feb 2002 10:25:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: requalification of expired flux-core solder
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Roger! The only issue I have found is sometimes the flux cored wire
becomes very heavily oxidized - I am still able to solder but have quite a
bit more "dross/floating oxide" than I normally experience. I have a desk
drawer full of solders I have accumulated from various points of the
universe, many which are 20-30 years old, and we are able to use them on
different projects as needed.
Dave Hillman
Rockwell Collins
[log in to unmask]
Roger Bilham <[log in to unmask]>@ipc.org> on 02/13/2002 01:48:31 AM
Please respond to Roger Bilham <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] requalification of expired flux-core solder
As a follow-up question, has anyone ever come across flux cored wire
which has become functionally defective through age? Provided that the
temperature isn't excessive and the outer layers of the wire are
protected from surface oxidation, cored wire should last almost
indefinitley, shouldn't it?
Roger Bilham
In article <48359946794DD511BA3A00508BA5563F0ECE1A@MERCURY>, Ochenas,
Tom <[log in to unmask]> writes
>
> Does anyone know of a method/standard for requalifying expired flux
> core solder wire (62/36/2)?
>
> The simpler the better...
>
> Thanks In Advance,
>
> Tom Ochenas
> Process Engineering
> Maxtek Components Corporation
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Mon, 18 Feb 2002 16:41:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Barton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Re: High temperature solder wire
Mime-Version: 1.0
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If you are going to the trouble to hand solder these parts on why not fit
them after the wave solder process and just tack them on, applying a dab of
of rework flux first, then reflowing the solder that will be present on the
pads? Saves the difficulty of using high temp solder pre-wave, and quite
likely excessive solder on the joints post wave (the solder in your bath
will wet to the high temp. joints already made). I have seen a similar
problem when tack soldering large multi way connectors with high temp.
solder pre-wave.
Regards,
Peter Barton
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
18/02/02 13:40
>Hi all,
>
>We are currently using adhesive to glue chips on PCB and then run the board on reflow oven
followed by wave soldering. After the reflow process we need to rework some
chips occasionally due to chip miss-alignment or missing. To do the rework
we have to remove the original glue, re-glue the chips and let the board go
through the reflow process again. Now we want to eliminate this loop by
using hi-temp solder wire (melting point 268-302 degree C) to solder the
reworked chips without adhesive, then let the reworked board directly go to
wave soldering with solder pot temperature around 245 degree C.
>
>Has anyone using this method seen problems?
>
>Eric
-----------------------------------------------------------------------
Peter Barton
ACW Technology Ltd
Dinas Isaf West
Tonypandy
Mid Glamorgan. CF40 1XX Wales
Tel: 01443 425200 Fax: 01443 436882
International Tel : +44 1443 425200 Fax : +44 1443 436882
E-mail: [log in to unmask] Website/URL: www.acw.co.uk
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Date: Mon, 18 Feb 2002 18:05:46 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Reliability Testing of PTH
X-To: Antonio Souza <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Antonio,
As a member of the IEC committee, we are preparing a new IEC 61189-5 spec
that shall be for "Process Characterisation". IEC = International
Electrotechnical Commission, to be precise: TECHNICAL COMMITTEE NO91
ELECTRONICS ASSEMBLY TECHNOLOGY WORKING GROUP 3: MEASURING AND TEST METHODS
FOR ASSEMBLIES AND ASSEMBLY MATERIALS.
The intention is to provide someone like yourself, with a specification and
procedure to help predict the end product reliability. As such it will take
into account all of the individual "wet" process chemistries and how they
react with one another.
The technique is based upon the latest Surface Insulation Resistance test
methods and procedures.
At present, you can refer to ANSI/IPC JSTD 001C and Appendix B (I think, but
Jack Crawford can correct me?) This will reference you to IPC-TM-650 and the
IPC SIR Test Handbook IPC 9201
Before I hear groans from everyone, the plan is to TRY and make this test as
easy as possible. There have already been a number of Test runs conducted to
verify this to be the case, using the outline protocol. Whilst most of this
cannot be published yet, I can give you copies of the work we have done as
presented to the APEX Conference, Lead-Free session in January 2002.
This new SIR test protocol is intended to determine the electro-chemical
compatibility of the finished assembly under conditions of accelerated
ageing. HARASS - HALT - HASS are different test methods that determine the
robustness of your finished product. If you want more info on this, please
let me know.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Antonio Souza
> Sent: 18 February 2002 12:20
> To: [log in to unmask]
> Subject: [TN] Reliability Testing of PTH
>
>
> Please
>
> Does anybody know any Guidelines for Accelerated Reliability
> Testing of PTH
> ?
>
> thanks
>
> Antonio
> INPE-Brasil
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> ------------------------------------------------------------------
> ---------------
>
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Date: Mon, 18 Feb 2002 12:09:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: BETWEEN A ROCK AND MY CAVE
Folks,
The reason I have been going down the reliability trail and ending up with
most all the answere I expected, is that we have a customer wanting easy
MTBF answere. As you all, especially Sir Werner, have so delicately
indicated: There ain't no easy way though most all data has been capatured
by one or more people regarding reliability.
Unfortunately, our customer has heard of a software package called Relex. I
know, I know, you can't predict something this easily. The customer got wind
of the package and can't understand why we don't know about it or aren't
using it. It is:
<http://www.lambdacorp.com/assets/images/red.gif>
Rapid R, M and LCC Analysis:
Generate an FMEA, R&M prediction and LCC estimate in a matter of hours. So
easily, in fact, that these analyses can be prepared as a part of your
proposal process. Easy report sorting provides the ability to quickly
identify any project's likely R, M or LCC drivers.
<http://www.lambdacorp.com/assets/images/red.gif>
Easy FMEA Preparation:
A preliminary failure modes and effects analysis, sorted by risk priority
number, can be produced for review by a cross-functional team in less than
1/2 day.
<http://www.lambdacorp.com/assets/images/red.gif>
Link the Future to the Past:
Relex provides the ability to store and easily reuse your product's R&M
characteristics, their known failure modes, causes and even "lessons
learned". When you generate a new FMEA or prediction with Relex, it
automatically includes this actionable data in your analysis.
<http://www.lambdacorp.com/assets/images/red.gif>
Simple LCC Analysis:
Life cycle cost analyses that are so simple to prepare that the LCC of your
equipment can actually become a meaningful design consideration. You can
quickly compare the life cycle cost of multiple design choices to determine
which is best from a total cost standpoint.
<http://www.lambdacorp.com/assets/images/red.gif>
Re-use Past Analyses:
Reuse completed FMEAs and predictions from past projects, or even
subassemblies of past projects, through an intuitive "drag and drop"
functionality. This enables you to assemble FMEAs, R&M predictions and LCC
analyses from your company's (or your supplier's) standard subassemblies all
with the click (and drag) of a mouse!
<http://www.lambdacorp.com/assets/images/red.gif>
Design, Manufacturing & Supplier Control Plans:
Reports that identify the design verification and validation activities,
manufacturing quality control or supplier controls required to ensure
machine reliability can be automatically generated from the FMEA.
<http://www.lambdacorp.com/assets/images/red.gif>
Data Import:
Automatically create new analyses by simply importing a bill of material
(BOM). Relex will automatically match the imported BOM data to your custom
libraries of parts and their failure rates, failure modes, and their causes.
I must give a presentation, via phone line, to some folks in the far side of
Asia tonight. No worries. I can put everything as delicately as Sir Werner,
or punt. What yardline and what line should I provide without:
1) Having to go there personally and present my lovable self and blame it
all on you.
2) Finding a way not to offend when we all know this ain't going to work.
I look forward to diplomatically correct answers so as not to offend, which
I often do.
MoonMan
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=========================================================================
Date: Mon, 18 Feb 2002 13:18:58 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: requalification of expired flux-core solder
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Dave Hillman foolishly admits:
"I have a desk drawer full of solders I have accumulated from various
points of the
universe, many which are 20-30 years old,"
Yep. Or, as we call him around here - old Hazmat Hillman.......
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Date: Mon, 18 Feb 2002 12:32:40 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Houston, Terri" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Mil spec translation to IPC needed
Hi folks,
I'm looking for the IPC equivalent for laminate MIL-S-13949/10 type GIN and
prepreg MIL-S13949/13 type PGI materials.
If anyone knows what these materials are currently called in the IPC specs,
it would be greatly appreciated.
Thanks,
Terri
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Date: Mon, 18 Feb 2002 14:40:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Calvin Reynard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Calvin Reynard <[log in to unmask]>
Subject: MIL-P-50884 and MIL-STD-2118
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0007_01C1B88A.37B6A980"
This is a multi-part message in MIME format.
------=_NextPart_000_0007_01C1B88A.37B6A980
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs) =
that are not longer active.=20
I know IPC-2223 replaces them but everybody list these specs in their =
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
------=_NextPart_000_0007_01C1B88A.37B6A980
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2314.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DFixedsys size=3D2>Hello, everyone,</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT face=3DFixedsys><FONT size=3D2>I am looking for<FONT =
size=3D1>=20
</FONT></FONT><FONT size=3D2>MIL-P-50884 and MIL-STD-2118 =
(Flex, Rigid-Flex=20
specs) that are not longer active. </FONT></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>I know IPC-2223 replaces them but =
everybody list=20
these specs in their documentation. Can anyone help?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>I found several sites that list them =
but the=20
links are dead.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>Thanks,</FONT></DIV>
<DIV><FONT size=3D2><BR><FONT=20
face=3DFixedsys> &nb=
sp; =20
\\\|///<BR> &n=
bsp; =20
( 0 0=20
)<BR>+---------oOOO--(_)--OOOo---------+<BR>| &nbs=
p;  =
; =
=20
|<BR>| Calvin=20
Reynard =
=20
|<BR>| Securaplane =
Technologies |<BR>|=20
10800 N. Mavinee=20
Dr. =
|<BR>|=20
Tucson, AZ=20
85737 &n=
bsp; =20
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| Voice =20
520-297-0844 &=
nbsp;=20
|<BR>| Fax =20
520-498-49241 =
|<BR>|=20
Email <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =20
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| =20
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|<BR>| ( =20
) =
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|<BR>+----------\ (----( =20
)-----------+<BR> &n=
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/<BR> &n=
bsp; =20
(_/</FONT></FONT></DIV></BODY></HTML>
------=_NextPart_000_0007_01C1B88A.37B6A980--
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=========================================================================
Date: Mon, 18 Feb 2002 17:01:07 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Reliability Testing of PTH
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi Antonio,
The most effective way is IST IPC-TM-2.6.26. To get some guidance you should
get IPV-TR-486 and IPC-TR-579.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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=========================================================================
Date: Mon, 18 Feb 2002 17:01:06 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: RELIABILITY DATA/INFORMATION CORRELATED TO DESIGN RULES
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Earl,
>They said, to someone else, there is a program that imports test data
directly
>from component supplier data sheets, or the stuff that went into them, and
>renders long term reliability data from them, or some such thing.
I would not trust data from component supplier data sheets--too many bad
experiences, because they generally do not know what they are doing.
Furthermore, I have yet to see the test parameters described to uinderstand
what these data actually could mean. This is the prime reason for IPC-9701.
Werner
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=========================================================================
Date: Mon, 18 Feb 2002 15:09:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: BETWEEN A ROCK AND MY CAVE
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Earl,
Sorry! I am as diplomatic as a sawed off shotgun on this subject.
You might point out that the primary business of the Lamba Corp is to sell software!
David A. Douthit
Manager
LoCan LLC
Earl Moon wrote:
> Folks,
>
> The reason I have been going down the reliability trail and ending up with
> most all the answere I expected, is that we have a customer wanting easy
> MTBF answere. As you all, especially Sir Werner, have so delicately
> indicated: There ain't no easy way though most all data has been capatured
> by one or more people regarding reliability.
>
> Unfortunately, our customer has heard of a software package called Relex. I
> know, I know, you can't predict something this easily. The customer got wind
> of the package and can't understand why we don't know about it or aren't
> using it. It is:
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Rapid R, M and LCC Analysis:
>
> Generate an FMEA, R&M prediction and LCC estimate in a matter of hours. So
> easily, in fact, that these analyses can be prepared as a part of your
> proposal process. Easy report sorting provides the ability to quickly
> identify any project's likely R, M or LCC drivers.
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Easy FMEA Preparation:
>
> A preliminary failure modes and effects analysis, sorted by risk priority
> number, can be produced for review by a cross-functional team in less than
> 1/2 day.
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Link the Future to the Past:
>
> Relex provides the ability to store and easily reuse your product's R&M
> characteristics, their known failure modes, causes and even "lessons
> learned". When you generate a new FMEA or prediction with Relex, it
> automatically includes this actionable data in your analysis.
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Simple LCC Analysis:
>
> Life cycle cost analyses that are so simple to prepare that the LCC of your
> equipment can actually become a meaningful design consideration. You can
> quickly compare the life cycle cost of multiple design choices to determine
> which is best from a total cost standpoint.
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Re-use Past Analyses:
>
> Reuse completed FMEAs and predictions from past projects, or even
> subassemblies of past projects, through an intuitive "drag and drop"
> functionality. This enables you to assemble FMEAs, R&M predictions and LCC
> analyses from your company's (or your supplier's) standard subassemblies all
> with the click (and drag) of a mouse!
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Design, Manufacturing & Supplier Control Plans:
>
> Reports that identify the design verification and validation activities,
> manufacturing quality control or supplier controls required to ensure
> machine reliability can be automatically generated from the FMEA.
>
> <http://www.lambdacorp.com/assets/images/red.gif>
> Data Import:
>
> Automatically create new analyses by simply importing a bill of material
> (BOM). Relex will automatically match the imported BOM data to your custom
> libraries of parts and their failure rates, failure modes, and their causes.
>
> I must give a presentation, via phone line, to some folks in the far side of
> Asia tonight. No worries. I can put everything as delicately as Sir Werner,
> or punt. What yardline and what line should I provide without:
>
> 1) Having to go there personally and present my lovable self and blame it
> all on you.
>
> 2) Finding a way not to offend when we all know this ain't going to work.
>
> I look forward to diplomatically correct answers so as not to offend, which
> I often do.
>
> MoonMan
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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=========================================================================
Date: Mon, 18 Feb 2002 13:15:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Wong <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Wong <[log in to unmask]>
Subject: .DSN files and OrCAD ViewDraw reader
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I have a customer that sent me an OrCAD .dsn file which is supposed to
be a schematic file. I was pointed to Cadence's web site to download
their ViewDraw Reader software which is supposed to be able to open and
print the schematic. I am getting an error message which is leads me to
suspect that I may need library files besides the .dsn file in order to
open this file.
Any advice?
Thanks
Peter
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style=3D'tab-interval:.5in'>
<div class=3DSection1>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>I have a customer that sent me an <span =
class=3DSpellE>OrCAD</span>
.<span class=3DSpellE>dsn</span> file which is supposed to be a =
schematic
file.<span style=3D'mso-spacerun:yes'> </span>I was pointed to =
Cadence’s
web site to download their <span class=3DSpellE>ViewDraw</span> Reader =
software
which is supposed to be able to open and print the schematic.<span
style=3D'mso-spacerun:yes'> </span>I am getting an error message =
which is leads
me to suspect that I may need library files besides the .<span =
class=3DSpellE>dsn</span>
file in order to open this file.<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><span class=3DGramE><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>Any =
advice?</span></font></span><font
face=3DArial><span =
style=3D'font-family:Arial'><o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Thanks<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Peter<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3D"Times New Roman"><span =
style=3D'font-size:
10.0pt'><o:p> </o:p></span></font></p>
</div>
</body>
</html>
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Date: Mon, 18 Feb 2002 15:45:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Calvin Reynard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0053_01C1B893.492ACE90"
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charset="iso-8859-1"
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Try http://astimage.daps.dla.mil/quicksearch=20
----- Original Message -----=20
Wrom: CONEUQZAAFXISHJEX
To: [log in to unmask]
Sent: Monday, February 18, 2002 2:40 PM
Subject: [TN] MIL-P-50884 and MIL-STD-2118
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs) =
that are not longer active.=20
I know IPC-2223 replaces them but everybody list these specs in their =
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
------=_NextPart_000_0053_01C1B893.492ACE90
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Try <A=20
href=3D"http://astimage.daps.dla.mil/quicksearch">http://astimage.daps.dl=
a.mil/quicksearch</A>=20
</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">Calvin=20
Reynard</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, February 18, 2002 =
2:40=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] MIL-P-50884 and=20
MIL-STD-2118</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DFixedsys size=3D2>Hello, everyone,</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT face=3DFixedsys><FONT size=3D2>I am looking for<FONT =
size=3D1>=20
</FONT></FONT><FONT size=3D2>MIL-P-50884 and MIL-STD-2118 =
(Flex, Rigid-Flex=20
specs) that are not longer active. </FONT></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>I know IPC-2223 replaces them but =
everybody=20
list these specs in their documentation. Can anyone help?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>I found several sites that list =
them but the=20
links are dead.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>Thanks,</FONT></DIV>
<DIV><FONT size=3D2><BR><FONT=20
=
face=3DFixedsys> &nb=
sp; =20
=
<A>\\\|///</A><BR> &=
nbsp; =20
( 0 0=20
=
)<BR>+---------oOOO--(_)--OOOo---------+<BR>| &nbs=
p;  =
; =
=20
|<BR>| Calvin=20
=
Reynard =
=20
|<BR>| Securaplane =
Technologies =20
|<BR>| 10800 N. Mavinee=20
Dr. =
|<BR>|=20
Tucson, AZ=20
=
85737 &n=
bsp; =20
=
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| Voice =20
=
520-297-0844 &=
nbsp;=20
|<BR>| Fax =20
=
520-498-49241 =
=20
|<BR>| Email <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =20
=
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| =20
=
ooooO &n=
bsp; =20
|<BR>| ( =20
) =20
Ooooo =20
|<BR>+----------\ (----( =20
=
)-----------+<BR> &n=
bsp; =20
\_) )=20
=
/<BR> &n=
bsp; =20
(_/</FONT></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 18 Feb 2002 17:58:44 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BETWEEN A ROCK AND MY CAVE
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi HardRock Earl,
...and there we thought your cave was this soft cushiony hibernation hollow
you shared with a ground hog.
Well, how do you tell somebody that they have been smoking something witout
telling them they have been smoking something? Why should FMEA, R&M, and LCC
be able to tell you something about reliability?
The only way I can think of is to question the source: where does this stuff
come from? what data is it based on? what physical model(s) is it based on?
why has nobody heard of it?
Sorry, diplomacy was never my long suit and I have always been a
straight-shooter--good consequence, this kept me off the Bell Labs promotion
list. So now you got a tech-guru instead of a lousy Lucent manager.
Sir Knight-in-Somewhat-Tarnished-Armor
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Date: Mon, 18 Feb 2002 16:59:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Calvin Reynard <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Calvin,
Go to the DSCC web site
http://www.dscc.dla.mil/Programs/MilSpec/DocSearch.asp and enter the numeric
for your specs in the search box. I didn't check both, but 50884 is
available as a pdf file.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Calvin Reynard
Sent: Monday, February 18, 2002 3:41 PM
To: [log in to unmask]
Subject: [TN] MIL-P-50884 and MIL-STD-2118
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs) that
are not longer active.
I know IPC-2223 replaces them but everybody list these specs in their
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
------=_NextPart_000_0016_01C1B89D.993973A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2713.1100" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D941505722-18022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Calvin,</FONT></SPAN></DIV>
<DIV><SPAN class=3D941505722-18022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D941505722-18022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Go to=20
the DSCC web site <A=20
href=3D"http://www.dscc.dla.mil/Programs/MilSpec/DocSearch.asp">http://ww=
w.dscc.dla.mil/Programs/MilSpec/DocSearch.asp</A> and=20
enter the numeric for your specs in the search box. I didn't check =
both,=20
but 50884 is available as a pdf file.</FONT></SPAN></DIV>
<DIV><SPAN class=3D941505722-18022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D941505722-18022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Don=20
Vischulis</FONT></SPAN></DIV>
<DIV><SPAN class=3D941505722-18022002></SPAN> </DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Calvin =
Reynard<BR><B>Sent:</B>=20
Monday, February 18, 2002 3:41 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] MIL-P-50884 and=20
MIL-STD-2118<BR><BR></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>Hello, everyone,</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT face=3DFixedsys><FONT size=3D2>I am looking for<FONT =
size=3D1>=20
</FONT></FONT><FONT size=3D2>MIL-P-50884 and MIL-STD-2118 =
(Flex, Rigid-Flex=20
specs) that are not longer active. </FONT></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>I know IPC-2223 replaces them but =
everybody list=20
these specs in their documentation. Can anyone help?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>I found several sites that list them =
but the=20
links are dead.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>Thanks,</FONT></DIV>
<DIV><FONT size=3D2><BR><FONT=20
face=3DFixedsys> &nb=
sp; =20
\\\|///<BR> &n=
bsp; =20
( 0 0=20
)<BR>+---------oOOO--(_)--OOOo---------+<BR>| &nbs=
p;  =
; =
=20
|<BR>| Calvin=20
Reynard =
=20
|<BR>| Securaplane =
Technologies |<BR>|=20
10800 N. Mavinee=20
Dr. =
|<BR>|=20
Tucson, AZ=20
85737 &n=
bsp; =20
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| Voice =20
520-297-0844 &=
nbsp;=20
|<BR>| Fax =20
520-498-49241 =
|<BR>|=20
Email <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =20
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| =20
ooooO &n=
bsp; =20
|<BR>| ( =20
) =
Ooooo =20
|<BR>+----------\ (----( =20
)-----------+<BR> &n=
bsp; =20
\_) )=20
/<BR> &n=
bsp; =20
(_/</FONT></FONT></DIV></BODY></HTML>
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Date: Mon, 18 Feb 2002 17:12:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: BETWEEN A ROCK AND MY CAVE
X-To: [log in to unmask]
Well Sir Knight,
At least your armor is still in tact as is your aim. One thing they can
never acuse you of and that's shooting from the hip.
Yes, they've been smoking something and I'm just trying to cut through the
smog created by it to save my client. Hell, I'll let them believe what they
want until I present the evidence as quality product designed and
manufactured right.
It's really hard to imagine most of these designs working at all. I'll never
let go of my C clamp photo.
As for you, some people are predestined to do something in life, they think.
People like you create your own destiny.
That tarnish could have resulted from your getting pissed off/on a few
times. Like I said, it's gotta look good on you.
I got to go kick some butt now. You'll be right there coaching me.
MoonMan from HardRock
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=========================================================================
Date: Mon, 18 Feb 2002 18:10:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
ATI ProcessGuy <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: ATI ProcessGuy <[log in to unmask]>
Subject: FR-04 questions
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Per IPC 2222 (Feb 1998):
Page 6, table 4-2 lists a selection chart for various Registered FR4 types.
I am familiar with FR4-04 and -06, however, it appears that for boards
requiring to be very flat while still trying to watch cost, I would be
better off specifying something like FR-4-17 or -19.
It appears that the cost for 17 is middle of the road and cost for 19 is
good. The kicker is that the farther down the table I go, it appears that
the minus is the laminate is more difficult to drill.
Is there articles anywhere out there regarding costs once we leave the
FR-04-06, FR-04-04 material and start going into the -17 or 19 etc?
What about the accuracy of the chart? It states material availability is
good. Anyone out there had experience with this?
Reason I ask, I have a 488 pin BGA 1 inch square I have to solder and they
are asking me what to spec. Thanks in advance.
_________________________________________________________________
Send and receive Hotmail on your mobile device: http://mobile.msn.com
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Date: Mon, 18 Feb 2002 19:53:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Re: .DSN files and OrCAD ViewDraw reader
X-To: Peter Wong <[log in to unmask]>
MIME-Version: 1.0
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Peter;
I don't know about their ViewDraw Reader software but you can request a free
viewer sometimes refer to as the student version that would suit you needs.
I contacted a Cadence Orcad representative and was sent a CD ROM Orcad
Family Release 9.2 Lite Edition. Also the .dsn is all you should need.
Regards
Bob Torres
-----Original Message-----
From: Peter Wong [mailto:[log in to unmask]]
Sent: Monday, February 18, 2002 1:15 PM
To: [log in to unmask]
Subject: [TN] .DSN files and OrCAD ViewDraw reader
I have a customer that sent me an OrCAD .dsn file which is supposed to be a
schematic file. I was pointed to Cadence's web site to download their
ViewDraw Reader software which is supposed to be able to open and print the
schematic. I am getting an error message which is leads me to suspect that
I may need library files besides the .dsn file in order to open this file.
Any advice?
Thanks
Peter
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<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D040514800-19022002>Peter;</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D040514800-19022002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D040514800-19022002>I=20
don't know about their ViewDraw Reader software but you can request a =
free=20
viewer sometimes refer to as the student version that would suit you=20
needs.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D040514800-19022002>I=20
contacted a Cadence Orcad representative and was sent a CD ROM =
Orcad=20
Family Release 9.2 Lite Edition. Also the .dsn is all you should=20
need.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D040514800-19022002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D040514800-19022002>Regards</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D040514800-19022002>Bob=20
Torres</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Peter Wong=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, February 18, =
2002 1:15=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] .DSN files =
and OrCAD=20
ViewDraw reader<BR><BR></FONT></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I have a customer that =
sent me an=20
<SPAN class=3DSpellE>OrCAD</SPAN> .<SPAN class=3DSpellE>dsn</SPAN> =
file which is=20
supposed to be a schematic file.<SPAN style=3D"mso-spacerun: =
yes"> =20
</SPAN>I was pointed to Cadence's web site to download their <SPAN=20
class=3DSpellE>ViewDraw</SPAN> Reader software which is supposed to =
be able to=20
open and print the schematic.<SPAN style=3D"mso-spacerun: yes"> =
</SPAN>I=20
am getting an error message which is leads me to suspect that I may =
need=20
library files besides the .<SPAN class=3DSpellE>dsn</SPAN> file in =
order to open=20
this file.<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DGramE><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Any=20
advice?</SPAN></FONT></SPAN><FONT face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial"><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Thanks<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Peter<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D2><SPAN=20
style=3D"FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P></DIV></BLOCKQUOTE></BODY></HTM=
L>
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Date: Mon, 18 Feb 2002 19:57:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Re: .DSN files and OrCAD ViewDraw reader
X-To: Peter Wong <[log in to unmask]>
MIME-Version: 1.0
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Peter;
Try http://www.orcad.com/Partner/Solution/ContentPage/cddemo4.asp
<http://www.orcad.com/Partner/Solution/ContentPage/cddemo4.asp> for the
download of the software mention before.
Regards
Bob Torres
-----Original Message-----
From: Peter Wong [mailto:[log in to unmask]]
Sent: Monday, February 18, 2002 1:15 PM
To: [log in to unmask]
Subject: [TN] .DSN files and OrCAD ViewDraw reader
I have a customer that sent me an OrCAD .dsn file which is supposed to be a
schematic file. I was pointed to Cadence's web site to download their
ViewDraw Reader software which is supposed to be able to open and print the
schematic. I am getting an error message which is leads me to suspect that
I may need library files besides the .dsn file in order to open this file.
Any advice?
Thanks
Peter
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<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Peter;</FONT></SPAN></DIV>
<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff size=3D2>Try <A=20
href=3D"http://www.orcad.com/Partner/Solution/ContentPage/cddemo4.asp">h=
ttp://www.orcad.com/Partner/Solution/ContentPage/cddemo4.asp</A> fo=
r=20
the download of the software mention before.</FONT></SPAN></DIV>
<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Regards</FONT></SPAN></DIV>
<DIV><SPAN class=3D008145700-19022002><FONT face=3DArial =
color=3D#0000ff size=3D2>Bob=20
Torres</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Peter Wong=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, February 18, =
2002 1:15=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] .DSN files =
and OrCAD=20
ViewDraw reader<BR><BR></FONT></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I have a customer that =
sent me an=20
<SPAN class=3DSpellE>OrCAD</SPAN> .<SPAN class=3DSpellE>dsn</SPAN> =
file which is=20
supposed to be a schematic file.<SPAN style=3D"mso-spacerun: =
yes"> =20
</SPAN>I was pointed to Cadence's web site to download their <SPAN=20
class=3DSpellE>ViewDraw</SPAN> Reader software which is supposed to =
be able to=20
open and print the schematic.<SPAN style=3D"mso-spacerun: yes"> =
</SPAN>I=20
am getting an error message which is leads me to suspect that I may =
need=20
library files besides the .<SPAN class=3DSpellE>dsn</SPAN> file in =
order to open=20
this file.<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DGramE><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Any=20
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style=3D"FONT-FAMILY: Arial"><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
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<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Thanks<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
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style=3D"FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P></DIV></BLOCKQUOTE></BODY></HTM=
L>
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Mon, 18 Feb 2002 18:04:24 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: .DSN files and OrCAD ViewDraw reader
X-To: Peter Wong <[log in to unmask]>
In-Reply-To: <001e01c1b8c1$56d9fc90$8464a8c0@peter>
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charset="Windows-1252"
Content-Transfer-Encoding: 8bit
Orcad and Viewdraw are two different programs. Go to the link below and try
the Capture viewer. You may need to have your customer provide any access
codes that are needed.
http://pcb.cadence.com/Registration/captureviewer/
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Wong
Sent: Monday, February 18, 2002 1:15 PM
To: [log in to unmask]
Subject: [TN] .DSN files and OrCAD ViewDraw reader
I have a customer that sent me an OrCAD .dsn file which is supposed to be a
schematic file. I was pointed to Cadence’s web site to download their
ViewDraw Reader software which is supposed to be able to open and print the
schematic. I am getting an error message which is leads me to suspect that
I may need library files besides the .dsn file in order to open this file.
Any advice?
Thanks
Peter
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<BODY lang=3DEN-US style=3D"tab-interval: .5in" vLink=3Dpurple =
link=3Dblue>
<DIV><SPAN class=3D620002801-19022002>Orcad and Viewdraw are two =
different=20
programs. Go to the link below and try the Capture viewer. You may need =
to have=20
your customer provide any access codes that are needed.</SPAN></DIV>
<DIV><SPAN class=3D620002801-19022002></SPAN> </DIV>
<DIV><A=20
href=3D"http://pcb.cadence.com/Registration/captureviewer/">http://pcb.ca=
dence.com/Registration/captureviewer/</A></DIV>
<DIV> </DIV>
<P>David Ricketts<BR><BR>Pertek Engineering<BR>Voice:=20
949-475-4485<BR>Fax: 949-475-4493 </P>
<P><FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Peter Wong<BR><B>Sent:</B> =
Monday,=20
February 18, 2002 1:15 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> [TN]=20
.DSN files and OrCAD ViewDraw reader<BR><BR></FONT><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I have a customer that =
sent me an=20
<SPAN class=3DSpellE>OrCAD</SPAN> .<SPAN class=3DSpellE>dsn</SPAN> file =
which is=20
supposed to be a schematic file.<SPAN style=3D"mso-spacerun: yes"> =
</SPAN>I=20
was pointed to Cadence=92s web site to download their <SPAN=20
class=3DSpellE>ViewDraw</SPAN> Reader software which is supposed to be =
able to=20
open and print the schematic.<SPAN style=3D"mso-spacerun: yes"> =
</SPAN>I am=20
getting an error message which is leads me to suspect that I may need =
library=20
files besides the .<SPAN class=3DSpellE>dsn</SPAN> file in order to open =
this=20
file.<o:p></o:p></SPAN></FONT></P>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DGramE><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Any=20
advice?</SPAN></FONT></SPAN><FONT face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial"><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Thanks<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Peter<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D2><SPAN=20
style=3D"FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P></DIV></BODY></HTML>
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Date: Mon, 18 Feb 2002 23:52:47 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Mil spec translation to IPC needed
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hello Terry,
IPC14101/41 Woven Eglass, Pollyimide, 250 deg C min (formerly
MIL-S-13949/10&13 GIN).
Boston Brad
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Date: Mon, 18 Feb 2002 23:22:47 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: .DSN files and OrCAD ViewDraw reader
X-To: Peter Wong <[log in to unmask]>
In-Reply-To: <001e01c1b8c1$56d9fc90$8464a8c0@peter>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0015_01C1B8D3.2D164910"
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------=_NextPart_000_0015_01C1B8D3.2D164910
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Peter,
Another option is to request that your customer make a PDF file for you
using Adobe Acrobat. Roberto is correct, the DSN file has all the component
information inside. If you opened it on a local copy of Orcad, it may try
to load libraries that you don't have, but this causes no harm. If you
like, send me the DSN file and I'll create a PDF file for you.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Wong
Sent: Monday, February 18, 2002 3:15 PM
To: [log in to unmask]
Subject: [TN] .DSN files and OrCAD ViewDraw reader
I have a customer that sent me an OrCAD .dsn file which is supposed to be
a schematic file. I was pointed to Cadence's web site to download their
ViewDraw Reader software which is supposed to be able to open and print the
schematic. I am getting an error message which is leads me to suspect that
I may need library files besides the .dsn file in order to open this file.
Any advice?
Thanks
Peter
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<DIV><SPAN class=3D645281405-19022002><FONT face=3DArial=20
size=3D2>Peter,</FONT></SPAN></DIV>
<DIV><SPAN class=3D645281405-19022002><FONT face=3DArial=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D645281405-19022002><FONT face=3DArial =
size=3D2>Another option is to=20
request that your customer make a PDF file for you using Adobe =
Acrobat. =20
Roberto is correct, the DSN file has all the component information =
inside. =20
If you opened it on a local copy of Orcad, it may try to load =
libraries=20
that you don't have, but this causes no harm. If you like, send me =
the DSN file and I'll create a PDF file for =
you.</FONT></SPAN></DIV>
<DIV> </DIV>
<DIV><FONT size=3D2><FONT face=3DArial>Regards,<BR><BR>Seth =
Goodman<BR>Goodman=20
Associates, LLC<BR>tel 608.833.9933<BR>fax =
608.833.9966</FONT></FONT><BR></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid; MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Peter Wong<BR><B>Sent:</B> =
Monday,=20
February 18, 2002 3:15 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B>=20
[TN] .DSN files and OrCAD ViewDraw reader<BR><BR></FONT></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I have a customer that =
sent me an=20
<SPAN class=3DSpellE>OrCAD</SPAN> .<SPAN class=3DSpellE>dsn</SPAN> =
file which is=20
supposed to be a schematic file.<SPAN style=3D"mso-spacerun: =
yes"> =20
</SPAN>I was pointed to Cadence’s web site to download their =
<SPAN=20
class=3DSpellE>ViewDraw</SPAN> Reader software which is supposed to be =
able to=20
open and print the schematic.<SPAN style=3D"mso-spacerun: yes"> =
</SPAN>I=20
am getting an error message which is leads me to suspect that I may =
need=20
library files besides the .<SPAN class=3DSpellE>dsn</SPAN> file in =
order to open=20
this file.<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DGramE><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Any=20
advice?</SPAN></FONT></SPAN><FONT face=3DArial><SPAN=20
style=3D"FONT-FAMILY: Arial"><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
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<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">Thanks<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
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<P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D2><SPAN=20
style=3D"FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P></DIV></BLOCKQUOTE></BODY></HTML=
>
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=========================================================================
Date: Mon, 18 Feb 2002 23:50:41 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: CAD Database file v/s Netlist file
X-To: Ken Patel <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Hi Ken,
Just catching up on my TechNet reading and noticed your post. You can get a
macro for PADS to extract the IPC-D-356A netlist for free from the authors
at http://www.capecad.com/htm/programs.htm This macro works very nicely and
has been tested by lots of users. Remember to thank the good folks at Cape
CAD for making this available.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Ken Patel
> Sent: Thursday, February 14, 2002 4:03 PM
> To: [log in to unmask]
> Subject: [TN] CAD Database file v/s Netlist file
>
>
> PCB Expert,
> If I provide my fab house CAD database file in ASCII format, do I still
> have to provide netlist in IPC-356 file format. Can fab house be able to
> extract needed netlist info for testing purpose out of database file?
>
> The dilemma I have is that my cad person do not know how to extract the
> netlist file from PADS. Any help/clarification in this direction will be
> appreciated.
>
> Re,
> Ken Patel
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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>
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=========================================================================
Date: Tue, 19 Feb 2002 00:57:38 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: High Frequency Effects
X-To: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi Robert,
This depends on component geometry (0805, 0603, 0402, etc), pad geometry and
trace geometry, but IMHO, your skepticism is justified. Assuming the pad
geometry is appropriate for the component, the distance between the
component end termination and the PCB pad is so small compared to the
component end termination width and pad overlap that the inductance of this
joint is already negligible compared to the component itself and the trace
leaving the pad. As long the joints are wetted, there is no solder bridging
and the component is not cracked, it sounds like the problem is elsewhere.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Furrow, Robert Gordon
> (Bob)
> Sent: Tuesday, February 12, 2002 1:55 PM
> To: [log in to unmask]
> Subject: [TN] High Frequency Effects
>
>
> Hi TechNet,
>
------------- snip ---------------------
> acceptance. My question to the TechNet is whether it is possible
> to improve
> performance for high speed signals if you add solder volume to a secure
> connection? As always the input from this group is appreciated.
>
> Thanks,
> Robert Furrow
> Printed Wiring Board Engineer
> Supply Chain Networks
> Lucent Technologies
> 978-960-3224 [log in to unmask]
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
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Date: Tue, 19 Feb 2002 15:07:24 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Calvin Reynard <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Calvin,
You may have to resort to old-fashioned technology. Try a big library and
see if they carry these specs on Microfilm, if you can't find a friendly
company with an internal library that still holds them. Or maybe the
'everyone', who sends you drawings that quote these specs can also supply
the specs. They should be able to if their design requires it, but then I'm
an idealist.
Peter
Calvin Reynard
<calvin@SECURA To: [log in to unmask]
PLANE.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] MIL-P-50884 and MIL-STD-2118
<[log in to unmask]
RG>
02/19/02 05:40
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Calvin
Reynard
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs) that
are not longer active.
I know IPC-2223 replaces them but everybody list these specs in their
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date: Tue, 19 Feb 2002 15:24:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Don Vischulis <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Calvin,
My further 2 cents worth is that since MIL-STD-2118 Notice 2 states that
the spec is cancelled and refers you to IPC-2223 or IPC-2221 instead, this
should be sufficient authorisation to use the IPC spec instead. i.e.
* Drg calls up MIL-STD-2118.
* You look up the MIL std and it tells you it's superseded another spec
(IPC-2223)
* You can then legitimately look up IPC-2223 as if it were MIL-STD-2118 and
read it as the requirement called up in the old drawings.
I can't vouch for whether or not there is any difference between the MIL
std content and the IPC std content, insofar as they cross-relate, but
there is no logical or arguable reason why you shouldn't be simplistic and
use the IPC std as if it were the MIL std called up in your drawings.
Peter
Don Vischulis
<dvischulis@W To: [log in to unmask]
I.RR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] MIL-P-50884 and MIL-STD-2118
<[log in to unmask]
ORG>
02/19/02
06:59 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Don Vischulis
Calvin,
Go to the DSCC web site
http://www.dscc.dla.mil/Programs/MilSpec/DocSearch.asp and enter the
numeric for your specs in the search box. I didn't check both, but 50884
is available as a pdf file.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Calvin Reynard
Sent: Monday, February 18, 2002 3:41 PM
To: [log in to unmask]
Subject: [TN] MIL-P-50884 and MIL-STD-2118
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs) that
are not longer active.
I know IPC-2223 replaces them but everybody list these specs in their
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Tue, 19 Feb 2002 10:25:57 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Reliability Testing of PTH
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Antonio
To answer your question you have to ask yourself first what reliability =
is:
Reliability =3D Ability of a given identity to fulfill the required =
mission within a given time frame in a defined environment under a given =
load with a required probability.
This definition gives you the whole bandwidth on the parameters you have =
to look at.
- Thermal=20
- Mechanical
- Thermomechanical
- Electrical (Including EMC)
- Humidity
- Chemical attack (including corrosion)
Depending on the application you have to choose the test sequence that has =
to be applied. No easy job.
But be careful.=20
- You are not only talking about testing. You talk about accelerated =
testing. This means you talk about physics of failure. For each test you =
choose you have to think about the failure mechanisms you are about to =
activate and you have to understand the influence of the testing parameters=
on that particular mechanism.
Examples:
. Chemical processes can be regarded at as thermally activated. This =
means, in a first attempt you can run a tests with at least 3 temperatures =
to evaluate the activation energy for the Arrhenius law you can apply to =
your problem. This activation energy might incorporate several mechanisms =
activated. However, for practical purposes this is precise enough. Based =
on this knowledge you can design the accelerated test that allows you an =
estimation of the reliability in the real world.=20
. Solder joints. A problem that Werner an I work and discuss on for many =
years now. Assuming that our model holds, tin based solder joints deform =
with two deformation mechanisms. Grain Boundary Sliding and Dislocation =
Climb. Both contribute their own part to the degradation of the solder =
joint. Senseless accelerated testing will activate large amounts of DC =
that never occur in reality. It will therefor be very difficult to =
extrapolate (anyway always a dangerous thing to do) the results found to =
the real environment.
- Reliability is a probability. This means, you need enough samples to =
find that number. Just ask the people finding failure rates of IC's they =
might give you an idea.
However, you are not alone. As a matter of fact all these questions are =
subject to research and I only mentioned how difficult the business is to =
show that we scientists are real big cracks. Seriously, there is a lot of =
data around in literature, but it's not a small job to find them. On the =
other hand you might even not ask for reliability but comparative testing. =
In this case, where you have a known specimen that fulfills your reliabilit=
y requirements you can design a test where you activate the interesting =
degradation mechanism(s) in both specimen to the same extend and compare =
the results of the two. Still not a peace of cake but a lot easier than =
starting from scratch.
Still, it's a fun job. Most of the time.
Best regards
Guenter
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Tue, 19 Feb 2002 11:36:08 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
MA Ranganath/SMPLB/SEC/SANMAR <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: MA Ranganath/SMPLB/SEC/SANMAR <[log in to unmask]>
Subject: Re: Reliability Testing of PTH
X-To: Antonio Souza <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dear Antonio,
An easy and simple way of determining the Reliability of a PTH (double-side
or multilayer) is to carry out a
Thermal Stress test on A/B Coupons integrated in the design as a part of
the panel outside the circuit area.
The coupon has to be cut out from the panel after PCB PROCESS Completion
without mechanical stress and coupon
cured for 1 hour at 120 deg C.
The specimen has to be cooled to room temperature under normal room
temperature conditions.
A mould has to be prepared with appropriate grinding and polishing for
metallographic inspection under a Stereo
Microscope having at least 50 magnification with illumination. If there
are no barrel cracks/discontinuity between
inner layers and barrel and also at the knee, then the PTH is supposed to
be reliable. If the Coupon specimen
can withstand higher cycles of thermal stress (>3) without any problems
the reliability is inferred to be high.
Regards,
M A Ranganath
GM - Engineering & Quality
Sanmar Micropack Limited
Plot No.16, Jigani Industrial Area,
Bangalore - 562 106. INDIA
Phone: 91 - 80 - 7825223/224/226/389
Fax : 91 - 80 - 7825225
Email : [log in to unmask]
Antonio Souza
<[log in to unmask] To: [log in to unmask]
INPE.BR>< > cc:
Sent by: Subject: [TN] Reliability Testing of PTH
TechNet
<[log in to unmask]
ORG>
02/18/02
05:49 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Antonio Souza
Please
Does anybody know any Guidelines for Accelerated Reliability Testing of PTH
?
thanks
Antonio
INPE-Brasil
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The information contained in this message is legally privileged and
confidential information intended only for the use of the addressed
individual or entity indicated in this message (or responsible for
delivery of the message to such person). It must not be read, copied,
disclosed, distributed or used by any person other than the addressee.
Unauthorised use, disclosure or copying is strictly prohibited and may be
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Date: Tue, 19 Feb 2002 07:14:12 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: EARL ROCK MOON
X-To: David Douthit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Dave,
I really agree with all you say - to the extent possible without your vast
knowledge and experience. It's really the warm and fuzzy suggestion you made
that has me concerned.
The company selling the software is a consultancy selling their reliability
wares. To me, they have a foot in the door each time they "give" away "free"
software of the type in discussion.
I have, and will continue to, informed my management they will have trouble
down stream if their customer continues pursuing the easy way to
reliability. They are quite aware of my position to the extent they want a
plan essentially to counter the claims made by the software consultants if
the customer continues its use.
I have such a plan and will implement it at time of all the product I did FA
work on while redesigning it using DFM/CE tools. When this happens, I will
provide all the evidence in my plan concerning not only the parts in
question, but the entire assembly. This will be based on industry data used
to construct documents such as several IPC types.
I am a quality and reliability hard case. I do not profess to compete with
fine folks like you, but I certainly can point to you as an example of
someone to call in if and when necessary. Sorry to say, I hope this does not
have to happen because if we in industry haven't gotten it close to right so
far, we never will.
Thanks,
Earl
----- Original Message -----
From: <[log in to unmask]>
To: "pod" <[log in to unmask]>
Sent: Tuesday, February 19, 2002 2:43 AM
Subject: Fw: [TN] BETWEEN A ROCK AND MY CAVE
>
> ----- Original Message -----
> From: "David Douthit" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, February 18, 2002 10:24 PM
> Subject: Re: [TN] BETWEEN A ROCK AND MY CAVE
>
>
> > Earl,
> >
> > You asked for it!
> >
> > Trying to save money no matter how much it costs is not very bright
> >
> > Any form of history based data reliability predictions is "worse than
> useless" (not my
> > phrase).
> > The collection process is limited, filtered, or simply not done.
> > There is no real incentive to "improve" products (you make additional
> money fixing problems
> > on fielded products!)
> > Changes are occurring so fast it is difficult to correlate the new
product
> with old data.
> > Computer reliability programs suffer from GIGO.
> > The current "reliability" engineering process is in reality "infant
> morality" engineering
> > controlled by warranty limits.
> > This software can also be used as a "warm fuzzy" to justify almost
> anything by adjusting
> > input data.
> > Accurate operational in-sutu environmental testing must be done, data
> compiled, and
> > adjustments/corrections/changes made.
> > Anything short of this is a "Death Wish"!!!
> >
> > David A. Douthit
> > Manager
> > LoCan LLC
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Date: Tue, 19 Feb 2002 19:17:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
makshuwing <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: makshuwing <[log in to unmask]>
Subject: Re: High temperature solder wire
X-To: Peter Barton <[log in to unmask]>
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Date: Tue, 19 Feb 2002 19:22:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
makshuwing <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: makshuwing <[log in to unmask]>
Subject: Static conducive solder sucker
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Date: Tue, 19 Feb 2002 08:08:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
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I do not think these are ozone depleter but they are very costly.
=20
This is the statement that they give regarding there material =20
in the data you are talking about. =20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
Hence, Fomblin and Galden perfluoropolyether fluids have a ZERO=20
Ozone Depletion Potential and are not classified as VOCs by the=20
EPA. =20
=20
=20
=
=20
Brian Ellis =
=20
<b_ellis@PROTO To: [log in to unmask] =
=20
NIQUE.COM> cc: =
=20
Sent by: Subject: Re: [TN] Antw: [T=
N] Vapor Phase =20
TechNet Soldering ReVisited! =
=20
<[log in to unmask] =
=20
RG> =
=20
=
=20
=
=20
02/16/02 03:01 =
=20
AM =
=20
Please respond =
=20
to "TechNet =
=20
E-Mail =
=20
Forum."; =
=20
Please respond =
=20
to Brian Ellis =
=20
=
=20
=
=20
Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 =B0C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial
partner in LEADFREE that runs the VP trials told me that he has to use =
a
liquid with a boiling point of 270 deg.C and that there is nothing
available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the s=
ame
answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
>
-----------------------------------------------------------------------=
----------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.=
8d
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t in
> the BODY (NOT the subject field): SIGNOFF Technet
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rg:
SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
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ses
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9=
700
ext.5315
>
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in
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:
SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
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s >
E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-970=
0
ext.5315
-----------------------------------------------------------------------=
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=
---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 19 Feb 2002 07:59:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Antonio Souza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Antonio Souza <[log in to unmask]>
Subject: Solder
Please
Could someone tell me the advantages and disadvantages of using solder
Sn/Pb/Ag instead of Sn/Pb.
Thanks
Antonio
Inpe-Brazil
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=========================================================================
Date: Tue, 19 Feb 2002 07:36:53 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
That would certainly make VP more palatable. If not due to VOC taxes, =
why
are the fluids so expensive?
Jim Kittel
-----Original Message-----
From: James TerVeen [mailto:[log in to unmask]]
Sent: Tuesday, February 19, 2002 6:08 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
I do not think these are ozone depleter but they are very costly.
=20
This is the statement that they give regarding there material =20
in the data you are talking about. =20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
Hence, Fomblin and Galden perfluoropolyether fluids have a ZERO=20
Ozone Depletion Potential and are not classified as VOCs by the=20
EPA. =20
=20
=20
=20
Brian Ellis
<b_ellis@PROTO To: [log in to unmask]
NIQUE.COM> cc:
Sent by: Subject: Re: [TN] Antw: =
[TN]
Vapor Phase =20
TechNet Soldering ReVisited!
<[log in to unmask]
RG>
=20
=20
02/16/02 03:01
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Brian Ellis
=20
=20
Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 =B0C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial
partner in LEADFREE that runs the VP trials told me that he has to use =
a
liquid with a boiling point of 270 deg.C and that there is nothing
available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the =
same
answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
>
------------------------------------------------------------------------=
----
-----
> Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d
> To unsubscribe, send a message to [log in to unmask] with following =
text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]:
SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & =
Databases
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700
ext.5315
>
------------------------------------------------------------------------=
----
-----
------------------------------------------------------------------------=
----
-----
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text =
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[log in to unmask]:
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Search previous postings at: www.ipc.org > On-Line Resources & =
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E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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847-509-9700
ext.5315
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----
-----
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----
-----
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in
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[log in to unmask]: SET
Technet NOMAIL
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E-mail Archives
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additional
information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700
ext.5315
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----
-----
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=========================================================================
Date: Tue, 19 Feb 2002 08:44:53 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mel Parrish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Calvin Reynard <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_001B_01C1B921.B3254CB0"
This is a multi-part message in MIME format.
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Calvin
If you did not find them at the suggested sites, give me a buzz. Being an
ol milspecker, I have a copy on the PC.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
Mel Parrish
Director of Training
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Calvin Reynard
Sent: Monday, February 18, 2002 1:41 PM
To: [log in to unmask]
Subject: [TN] MIL-P-50884 and MIL-STD-2118
Hello, everyone,
I am looking for MIL-P-50884 and MIL-STD-2118 (Flex, Rigid-Flex specs)
that are not longer active.
I know IPC-2223 replaces them but everybody list these specs in their
documentation. Can anyone help?
I found several sites that list them but the links are dead.
Thanks,
\\\|///
( 0 0 )
+---------oOOO--(_)--OOOo---------+
| |
| Calvin Reynard |
| Securaplane Technologies |
| 10800 N. Mavinee Dr. |
| Tucson, AZ 85737 |
| |
| Voice 520-297-0844 |
| Fax 520-498-49241 |
| Email [log in to unmask] |
| |
| ooooO |
| ( ) Ooooo |
+----------\ (----( )-----------+
\_) ) /
(_/
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D687174216-19022002><FONT face=3DTahoma =
color=3D#000080=20
size=3D2>Calvin</FONT></SPAN></DIV>
<DIV><SPAN class=3D687174216-19022002><FONT face=3DTahoma =
color=3D#000080 size=3D2>If=20
you did not find them at the suggested sites, give me a buzz. =
Being an ol=20
milspecker, I have a copy on the PC. </FONT></SPAN></DIV>
<DIV><SPAN class=3D687174216-19022002><FONT face=3DTahoma =
color=3D#000080=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D687174216-19022002>
<P><FONT size=3D2>Mel Parrish<BR>Soldering Technology =
International<BR>102 Tribble=20
Drive<BR>Madison, AL 35758<BR>256 705 5530<BR>256 705 5538=20
Fax<BR>[log in to unmask]<BR>www.solderingtech.com</FONT>=20
</P></SPAN></DIV>
<DIV> </DIV>
<P><FONT size=3D2>Mel Parrish<BR>Director of Training<BR>Soldering =
Technology=20
International<BR>102 Tribble Drive<BR>Madison, AL 35758<BR>256 705 =
5530<BR>256=20
705 5538 =
Fax<BR>[log in to unmask]<BR>www.solderingtech.com</FONT> </P>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Calvin =
Reynard<BR><B>Sent:</B>=20
Monday, February 18, 2002 1:41 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] MIL-P-50884 and=20
MIL-STD-2118<BR><BR></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>Hello, everyone,</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT face=3DFixedsys><FONT size=3D2>I am looking for<FONT =
size=3D1>=20
</FONT></FONT><FONT size=3D2>MIL-P-50884 and MIL-STD-2118 =
(Flex, Rigid-Flex=20
specs) that are not longer active. </FONT></FONT></DIV>
<DIV><FONT face=3DFixedsys size=3D2>I know IPC-2223 replaces them but =
everybody=20
list these specs in their documentation. Can anyone help?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>I found several sites that list =
them but the=20
links are dead.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DFixedsys size=3D2>Thanks,</FONT></DIV>
<DIV><FONT size=3D2><BR><FONT=20
=
face=3DFixedsys> &nb=
sp; =20
=
\\\|///<BR> &n=
bsp; =20
( 0 0=20
=
)<BR>+---------oOOO--(_)--OOOo---------+<BR>| &nbs=
p;  =
; =
=20
|<BR>| Calvin=20
=
Reynard =
=20
|<BR>| Securaplane =
Technologies =20
|<BR>| 10800 N. Mavinee=20
Dr. =
|<BR>|=20
Tucson, AZ=20
=
85737 &n=
bsp; =20
=
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| Voice =20
=
520-297-0844 &=
nbsp;=20
|<BR>| Fax =20
=
520-498-49241 =
=20
|<BR>| Email <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =20
=
|<BR>| &=
nbsp; &n=
bsp; =20
|<BR>| =20
=
ooooO &n=
bsp; =20
|<BR>| ( =20
) =20
Ooooo =20
|<BR>+----------\ (----( =20
=
)-----------+<BR> &n=
bsp; =20
\_) )=20
=
/<BR> &n=
bsp; =20
(_/</FONT></FONT></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_001B_01C1B921.B3254CB0--
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Date: Tue, 19 Feb 2002 09:19:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: How old is old?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
One of the purchasers has asked if they can purchase some parts with a 2000
date code on them for 'a really great deal!' The part is an 8 lead uSOIC
package
At what point do you say they are too old?
I would appreciate info specific to this package or, just in general,
guidelines for chip or standard SM components. We do not use BGA's yet. We
aren't trying to do lead free. We generally spec 60/40 HASL finish on our
boards.
Thanks for your time.
Genny Gibbard (mailto:[log in to unmask])
Product Transition and Support
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Date: Tue, 19 Feb 2002 18:35:19 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: Guenter Grossmann <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
James
They are not known to be ozone depleters but they most certainly are
global warmers.
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial partner in LEADFREE that runs the VP trials told me that he has to use a liquid with a boiling point of 270 deg.C and that there is nothing available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the same answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 19 Feb 2002 10:37:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Alain Savard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Alain Savard <[log in to unmask]>
Subject: Depanalizing mouse bite
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Netters,
What kind of tool is required to depanalize boards with mouse-bite patterns
along the edge?
(Scoring is not in the realm of possible avenues here, there are connectors
and switches along the edge.)
Thanks,
Alain Savard
QA - PCB
CAE Inc.
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=========================================================================
Date: Tue, 19 Feb 2002 17:13:36 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: High temperature solder wire
In-Reply-To: <004101c1b937$148fe900$63010a0a@makshuwing>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit
I can see your thinking, but an earlier poster was correct: although the
melting point of the solder is higher than the wave soldering temperature,
if the higher melting alloy sees the wave it will dissolve in it in much the
same way as say electroless gold (MP 1064C) on a PCB does.
If you still want to go ahead, be aware that there are a number of higher
melting point alloys you could use in the range 270 - 280C. These are
generally characterised as having a high lead content with smaller additions
of tin, silver, indium and so on to 100% according to the precise melting
point you are looking for. This high lead content means the joints will be
slow to form and dull in appearance. At the higher range you will be near to
caramelising the flux and if you need to remove it you may find (according
to the supplier) some difficulty in doing so effectively as it will tend to
bake on.
Because of the small usage of these alloys in wire form - compared to Sn63 -
you may not find they are all available flux cored and you will need to
apply flux separately. Here I would recommend you use a paste flux which you
can apply from a syringe. (ours is called Tacflux, other suppliers will have
their own names). This is less messy and more controlled than painting on
liquid flux and also gives you the opportunity to get more easily cleanable
or no clean types suited to the higher melting alloys.
You will need to use a decent iron capable of operating at the higher
temperatures and delivering the heat correctly without damaging the board
and pad adhesion, and pay attention to proper tip dressing and control so as
not to get tip dewetting.
Alternatives might be to use a dispense solder paste and hot air repair
tool.
Good luck
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of makshuwing
Sent: Tuesday, February 19, 2002 11:18 AM
To: [log in to unmask]
Subject: Re: [TN] High temperature solder wire
Hello eter,
Adhesive dispensing, chip placement, reflow(glue curing), manual insertion,
then wave soldering are our normal processes. After reflow we sometimes find
some mis-aligned chips or missing components. The area of glue in contact
with the surface of the mis-aligned chip could be less than normal and the
adhesion force is insufficient to protect the chip from dropping off during
wave soldering. Therefore we want to use high temp solder to solder the
mis-aligned chips prior to wave soldering. We know that we could detach the
parts after reflow and hand solder the parts after the wave soldering but we
think adding hi-temp solder is the simpliest way since there is no
detachment process is involved.
Eric
----- Original Message -----
From: "Peter Barton" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 19, 2002 12:41 AM
Subject: Re: [TN] High temperature solder wire
> If you are going to the trouble to hand solder these parts on why not fit
> them after the wave solder process and just tack them on, applying a dab
of
> rework flux first, then reflowing the solder that will be present on the
> pads? Saves the difficulty of using high temp solder pre-wave, and quite
> likely excessive solder on the joints post wave (the solder in your bath
> will wet to the high temp. joints already made). I have seen a similar
> problem when tack soldering large multi way connectors with high temp.
> solder pre-wave.
>
> Regards,
>
> Peter Barton
>
> ===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
> 18/02/02 13:40
> >Hi all,
> >
> >We are currently using adhesive to glue chips on PCB and then run the
board on reflow oven
> followed by wave soldering. After the reflow process we need to rework
some
> chips occasionally due to chip miss-alignment or missing. To do the rework
> we have to remove the original glue, re-glue the chips and let the board
go
> through the reflow process again. Now we want to eliminate this loop by
> using hi-temp solder wire (melting point 268-302 degree C) to solder the
> reworked chips without adhesive, then let the reworked board directly go
to
> wave soldering with solder pot temperature around 245 degree C.
> >
> >Has anyone using this method seen problems?
> >
> >Eric
>
>
> -----------------------------------------------------------------------
> Peter Barton
>
> ACW Technology Ltd
> Dinas Isaf West
> Tonypandy
> Mid Glamorgan. CF40 1XX Wales
>
> Tel: 01443 425200 Fax: 01443 436882
>
> International Tel : +44 1443 425200 Fax : +44 1443 436882
>
> E-mail: [log in to unmask] Website/URL: www.acw.co.uk
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
Mç!ëLj)K Ëi®‹âuçZ±§ëyë ®øœy¼ˆ<+¬ x
!$Ò uñÔèº{.nÇ+‰·¬zwZ™ë,j ² M! TƒÂ9 ° Ø_¢YhÂ)àµìm {ax ƒ`Ó“¶ ¬¹¸Þr×âzWR
cN TÞr Þµ:-zjhªâ—(Z–×^–+Þ¯* Mç!ëlzw^™¨¥¶‚â²Û ®ø©r àHDÓyÈgzÓN0
N Þqè¯xãD™¨¥ x)z·Zʇږ[azš,¶Ë צj)m ¸¬¶Ç«¾*\¢¸ 4Þr Þ´8 zËRyªÜ†šÞ¾*.²š,¶)à±
«pà ©r à:râä^²‹«që jÖ›jǬ f¢”
܆+Þ°ù^jǯ È
ð°y»"µèm¶Ÿÿà "¥Ê+ƒømš_ߢ»¦†ÙŸ¢¶v+b¢v¥ wè®f ‰èÊ'µ§-)朅&¬jj+‰«ljƤ¢*\¢¸(¯Î
;çO}ïM ÆÞw
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=========================================================================
Date: Tue, 19 Feb 2002 11:46:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: [log in to unmask]
Mel,
Just a trip to the past. I do remember some fond days working with the two
documents in question.
Ah, the happy times in the late 70's and early 80's in Dayton with Ivan
Jones, then of DESC, Foster Grey of TI, what was his cohort's name, Dave
Wolf, Marty Jawitz, and who was the Navy (from DC) guy we had to visit to
get consideration on any new stuff for them?
Ah yes, the smell of burning flex circuits in the morning! Please pardon the
nostalgia. Have no idea what brought this on, sniff.
Earl
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=========================================================================
Date: Tue, 19 Feb 2002 13:28:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: High temperature solder wire
X-To: makshuwing <[log in to unmask]>
In-Reply-To: <004101c1b937$148fe900$63010a0a@makshuwing>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit
Have you considered temporary spot mask? It works okay for chip resistors
and capacitors, SOT. Not too good for SOIC, stuff gets stuck under the
little legs.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of makshuwing
> Sent: Tuesday, February 19, 2002 6:18 AM
> To: [log in to unmask]
> Subject: Re: [TN] High temperature solder wire
>
>
> Hello eter,
>
> Adhesive dispensing, chip placement, reflow(glue curing), manual
> insertion, then wave soldering are our normal processes. After
> reflow we sometimes find some mis-aligned chips or missing
> components. The area of glue in contact with the surface of the
> mis-aligned chip could be less than normal and the adhesion force
> is insufficient to protect the chip from dropping off during
> wave soldering. Therefore we want to use high temp solder to
> solder the mis-aligned chips prior to wave soldering. We know
> that we could detach the parts after reflow and hand solder the
> parts after the wave soldering but we think adding hi-temp solder
> is the simpliest way since there is no detachment process is involved.
>
> Eric
> ----- Original Message -----
> From: "Peter Barton" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, February 19, 2002 12:41 AM
> Subject: Re: [TN] High temperature solder wire
>
>
> > If you are going to the trouble to hand solder these parts on
> why not fit
> > them after the wave solder process and just tack them on,
> applying a dab of
> > rework flux first, then reflowing the solder that will be present on the
> > pads? Saves the difficulty of using high temp solder pre-wave, and quite
> > likely excessive solder on the joints post wave (the solder in your bath
> > will wet to the high temp. joints already made). I have seen a similar
> > problem when tack soldering large multi way connectors with high temp.
> > solder pre-wave.
> >
> > Regards,
> >
> > Peter Barton
> >
> > ===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
> > 18/02/02 13:40
> > >Hi all,
> > >
> > >We are currently using adhesive to glue chips on PCB and then
> run the board on reflow oven
> > followed by wave soldering. After the reflow process we need to
> rework some
> > chips occasionally due to chip miss-alignment or missing. To do
> the rework
> > we have to remove the original glue, re-glue the chips and let
> the board go
> > through the reflow process again. Now we want to eliminate this loop by
> > using hi-temp solder wire (melting point 268-302 degree C) to solder the
> > reworked chips without adhesive, then let the reworked board
> directly go to
> > wave soldering with solder pot temperature around 245 degree C.
> > >
> > >Has anyone using this method seen problems?
> > >
> > >Eric
> >
> >
> > -----------------------------------------------------------------------
> > Peter Barton
> >
> > ACW Technology Ltd
> > Dinas Isaf West
> > Tonypandy
> > Mid Glamorgan. CF40 1XX Wales
> >
> > Tel: 01443 425200 Fax: 01443 436882
> >
> > International Tel : +44 1443 425200 Fax : +44 1443 436882
> >
> > E-mail: [log in to unmask] Website/URL: www.acw.co.uk
> >
> >
> ------------------------------------------------------------------
> ---------------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with
> following text in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> [log in to unmask]: SET Technet NOMAIL
> > To receive ONE mailing per day of all the posts: send e-mail to
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> > Search previous postings at: www.ipc.org > On-Line Resources &
> Databases > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm)
> for additional
> > information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> >
> ------------------------------------------------------------------
> ---------------
> >
>
> Mç!ëLj)K Ëi®‹âuçZ±§ëyë ®øœy¼ˆ<+¬ x
> !$Ò uñÔèº{.nÇ+‰·¬zwZ™ë,j
> ² M! TƒÂ9 ° Ø_¢YhÂ)àµìm {ax ƒ`Ó“¶ ¬¹¸Þr×âzWR
> cN TÞr Þµ:-zjhªâ—(Z–×^–+Þ¯* Mç!ëlzw^™¨¥¶‚â²Û ®ø©r àHDÓyÈgzÓN0
> N Þqè¯xãD™¨¥ x)z·Zʇږ[azš,¶Ë צj)m ¸¬¶Ç«¾*\¢¸ 4Þr Þ´8
> zËRyªÜ†šÞ¾*.²š,¶)౫pà ©r à:râä^²‹«që jÖ›jǬ f¢”
> ܆+Þ°ù^jǯ È ð°y»"µèm¶Ÿÿà >
"¥Ê+ƒømš_ߢ»¦†ÙŸ¢¶v+b¢v¥ wè®f ‰èÊ'µ§-)朅&¬jj+‰«ljƤ¢*\¢¸(¯Î;çO}ïM ÆÞw
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Date: Tue, 19 Feb 2002 13:41:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charlie Pitarys <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charlie Pitarys <[log in to unmask]>
Subject: Re: Anodize part washing
X-To: "[log in to unmask]" <[log in to unmask]>
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Hello Richard,
This subject comes up about once a year with various CM's and military
packaging accounts.
99.9% of the time the problem is with the supplier.
Please reference the following quote.
"Sealing of Anodic Coatings"
"To achieve the maximum protective qualities and corrosion resistance
required for finished articles, the anodic oxide must be sealed after it is
formed and/or colored. The sealing process consists of immersing the
anodized parts in a solution of boiling water or other solution such as
nickel acetate, wherein the aluminum oxide is hydrated. The hydrated form of
the oxide has greater volume than the unhydrated form and thus the pores of
the coating are filled or plugged and the coating becomes resistant to
further staining and corrosion. The use of nickel containing seals will in
most cases prevent leaching of dyes during the sealing operation."
"Metal Finishing '99 Guidebook and Directory," 67th Guidebook and Directory
Issue, Metal Finishing Magazine, Tarrytown, NY, 1999, p.491.
If you have a quantity of these parts available and need to keep production
going, you can try a boiling water treatment of the heat sink parts.
Typically 20 -30 minutes of immersion will be sufficient.
Any further questions, please do not hesitate to call me.
Best regards
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
-----Original Message-----
From: Richard Carruth [mailto:[log in to unmask]]
Sent: Friday, February 15, 2002 3:48 PM
To: [log in to unmask]
Subject: [TN] Anodize part washing
Hello all, I have a question regarding Type II Class II black anodize of
extruded aluminum. I have some extruded aluminum heatsinks that look really
good
(dark black and uniform) coming into receiving inspection, however they
become
very splotchy and blue colored after they are washed in our MCS100 cleaner
with
Kyzen. Does anyone have any information they can share with me regarding
this
issue. Our customer will absolutely not accept any non-uniform black
anodize.
Richar Carruth
Quality Engineer
LaBarge Inc.
PH# 918-459-2346
[log in to unmask]
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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>RE: [TN] Anodize part washing</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=3D2>Hello Richard, </FONT>
<BR><FONT SIZE=3D2>This subject comes up about once a year with various =
CM's and military packaging accounts.</FONT>
<BR><FONT SIZE=3D2>99.9% of the time the problem is with the =
supplier.</FONT>
<BR><FONT SIZE=3D2>Please reference the following quote.</FONT>
</P>
<P><FONT SIZE=3D2>"Sealing of Anodic Coatings"</FONT>
</P>
<P><FONT SIZE=3D2>"To achieve the maximum protective qualities and =
corrosion resistance</FONT>
<BR><FONT SIZE=3D2>required for finished articles, the anodic oxide =
must be sealed after it is</FONT>
<BR><FONT SIZE=3D2>formed and/or colored. The sealing process consists =
of immersing the</FONT>
<BR><FONT SIZE=3D2>anodized parts in a solution of boiling water or =
other solution such as</FONT>
<BR><FONT SIZE=3D2>nickel acetate, wherein the aluminum oxide is =
hydrated. The hydrated form of</FONT>
<BR><FONT SIZE=3D2>the oxide has greater volume than the unhydrated =
form and thus the pores of</FONT>
<BR><FONT SIZE=3D2>the coating are filled or plugged and the coating =
becomes resistant to</FONT>
<BR><FONT SIZE=3D2>further staining and corrosion. The use of nickel =
containing seals will in</FONT>
<BR><FONT SIZE=3D2>most cases prevent leaching of dyes during the =
sealing operation."</FONT>
</P>
<P><FONT SIZE=3D2>"Metal Finishing '99 Guidebook and =
Directory," 67th Guidebook and Directory</FONT>
<BR><FONT SIZE=3D2>Issue, Metal Finishing Magazine, Tarrytown, NY, =
1999, p.491.</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>If you have a quantity of these parts available and =
need to keep production going, you can try a boiling water treatment of =
the heat sink parts. Typically 20 -30 minutes of immersion will be =
sufficient.</FONT></P>
<P><FONT SIZE=3D2>Any further questions, please do not hesitate to call =
me.</FONT>
<BR><FONT SIZE=3D2>Best regards</FONT>
</P>
<P><FONT SIZE=3D2>Charlie Pitarys</FONT>
<BR><FONT SIZE=3D2>Director of Application Technologies</FONT>
<BR><FONT SIZE=3D2>603.622.2900 X-115</FONT>
<BR><FONT SIZE=3D2>www.kyzen.com </FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Richard Carruth [<A =
HREF=3D"mailto:[log in to unmask]">mailto:Richard.Carruth@LABAR=
GE.COM</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Friday, February 15, 2002 3:48 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Anodize part washing</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>Hello all, I have a question regarding Type II Class =
II black anodize of</FONT>
<BR><FONT SIZE=3D2>extruded aluminum. I have some extruded aluminum =
heatsinks that look really good</FONT>
<BR><FONT SIZE=3D2>(dark black and uniform) coming into receiving =
inspection, however they become</FONT>
<BR><FONT SIZE=3D2>very splotchy and blue colored after they are washed =
in our MCS100 cleaner with</FONT>
<BR><FONT SIZE=3D2>Kyzen. Does anyone have any information they can =
share with me regarding this</FONT>
<BR><FONT SIZE=3D2>issue. Our customer will absolutely not accept any =
non-uniform black anodize.</FONT>
</P>
<P><FONT SIZE=3D2>Richar Carruth</FONT>
<BR><FONT SIZE=3D2>Quality Engineer</FONT>
<BR><FONT SIZE=3D2>LaBarge Inc.</FONT>
<BR><FONT SIZE=3D2>PH# 918-459-2346</FONT>
<BR><FONT SIZE=3D2>[log in to unmask]</FONT>
</P>
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Date: Tue, 19 Feb 2002 11:45:27 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ed Shea <[log in to unmask]>
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: Earl Moon <[log in to unmask]>
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The "Navy Guy" was Jack Kerr.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Tuesday, February 19, 2002 9:47 AM
To: [log in to unmask]
Subject: Re: [TN] MIL-P-50884 and MIL-STD-2118
Mel,
Just a trip to the past. I do remember some fond days working with the two
documents in question.
Ah, the happy times in the late 70's and early 80's in Dayton with Ivan
Jones, then of DESC, Foster Grey of TI, what was his cohort's name, Dave
Wolf, Marty Jawitz, and who was the Navy (from DC) guy we had to visit to
get consideration on any new stuff for them?
Ah yes, the smell of burning flex circuits in the morning! Please pardon the
nostalgia. Have no idea what brought this on, sniff.
Earl
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Date: Tue, 19 Feb 2002 15:14:53 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MIL-P-50884 and MIL-STD-2118
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If you go to www.dscc.dla.mil
and search for the numbers in the specs and standards area, you will be able
to
get a pdf file of each
Susan Mansilla
Robisan Lab
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Date: Tue, 19 Feb 2002 15:29:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Depanalizing mouse bite
X-To: Alain Savard <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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These links will get you to companies that make depanelers for your route
and tab boards (as well as scored boards:)
www.cabtechn.com
www.fknsystek.com
Regards,
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Alain Savard
> Sent: Tuesday, February 19, 2002 10:37 AM
> To: [log in to unmask]
> Subject: [TN] Depanalizing mouse bite
>
>
> Hi Netters,
>
> What kind of tool is required to depanalize boards with
> mouse-bite patterns
> along the edge?
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Date: Tue, 19 Feb 2002 15:31:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Raymond <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
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Hello all, many thanks to all who answered and helped with my questions
about my Hot Air Knife problems... now I have another question.
We have a brand new Agilent 5DX x-ray system. Maybe some users of this
equipment could give me their impression of how well this machine evaluates
Plastic BGA solder joints and also, how well it does with bottom side SMD
that has been wave soldered.
Bill...
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Date: Tue, 19 Feb 2002 14:45:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MIL-P-50884 and MIL-STD-2118
X-To: [log in to unmask]
Thanks Ed,
I was fishing to see who still remembered him. Jack was stoic, to say the
least, and always seemed on top of everyting. This seemed true even, with
pipe in mouth, he drifted off into a semi-conscious world only to be found
very alert as though considering what was "thrown" at him. Lunch at the
Marriott, across the overhead walkway, seemed a good setting to reflect.
He told me he was retiring to a "farm" in Virginia. I lost contact after
that announcement and apparent happening.
Thanks again Ed, I liked the man,
Earl
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Date: Tue, 19 Feb 2002 13:27:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: How old is old?
X-To: [log in to unmask]
MIME-Version: 1.0
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hi,
if they are solderable, and they aren't used parts you shouldn't have any problems.
phil
-----Original Message-----
From: Genny Gibbard [mailto:[log in to unmask]]
Sent: Tuesday, February 19, 2002 7:19 AM
To: [log in to unmask]
Subject: [TN] How old is old?
One of the purchasers has asked if they can purchase some parts with a 2000
date code on them for 'a really great deal!' The part is an 8 lead uSOIC
package
At what point do you say they are too old?
I would appreciate info specific to this package or, just in general,
guidelines for chip or standard SM components. We do not use BGA's yet. We
aren't trying to do lead free. We generally spec 60/40 HASL finish on our
boards.
Thanks for your time.
Genny Gibbard (mailto:[log in to unmask])
Product Transition and Support
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Date: Tue, 19 Feb 2002 18:25:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
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James,
Are you confusing ozone depletion and global warming? They are two
different subjects, although there are compounds that are involved in =
both -
CFC's, for instance. The perfluoro compounds are, as you say, not =
ozone
depleters, since they have no chlorine or bromine, but, as Brian Ellis =
put
so succinctly below, they are raather good at global warming. And that =
is
an understatement. They absorb IR light in just the wrong place and =
have
incredible atmospheric lifetimes because they are so unreactive.
Fortunately not much is being used (relatively speaking) and most have =
low
vapor pressures. However, some of the shorter chain ones... yuck.
Bev Christian
Research in Motion
-----Original Message-----
From: James TerVeen [mailto:[log in to unmask]]
Sent: February 19, 2002 8:08 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
I do not think these are ozone depleter but they are very costly.
=20
This is the statement that they give regarding there material =20
in the data you are talking about. =20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
=20
Hence, Fomblin and Galden perfluoropolyether fluids have a ZERO=20
Ozone Depletion Potential and are not classified as VOCs by the=20
EPA. =20
=20
=20
=20
Brian Ellis
<b_ellis@PROTO To: [log in to unmask]
NIQUE.COM> cc:
Sent by: Subject: Re: [TN] Antw: =
[TN]
Vapor Phase =20
TechNet Soldering ReVisited!
<[log in to unmask]
RG>
=20
=20
02/16/02 03:01
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Brian Ellis
=20
=20
Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 =B0C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial
partner in LEADFREE that runs the VP trials told me that he has to use =
a
liquid with a boiling point of 270 deg.C and that there is nothing
available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the =
same
answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
>
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Date: Tue, 19 Feb 2002 18:54:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jim,
These are expensive because:
1) There are few companies that make them
2) Demand is low
3) Working with fluorine compounds usually ain't cheap. To give you some
idea:
For making perfluoro compounds "A number of reactive metal fluorides have
been employed, including AgF2, PbF4, HgF2 and Co F3, the last being the most
useful. The general reaction may be expressed as follows:
>CH2 + 4CoF3--->CF2 + 4CoF2 + 2HF (at 110 - 400 C)
followed, in a separate stage, by
2CoF2 + F2 ---> 2CoF3 (250 - 400C)"1.
It is not economical because so much fluorine ends up as HF and there are a
whole pile of side reactions, which increase in number as you try to make
longer and longer chains (No surprise there.)
There may be newer, better ways, but you can bet there are still lots of
nasty things to have to deal with. So unless the manufacturer wants to have
a lot of dissolved workers, everything is going to be done in high quality
nickel or Monel metal, with valves that costs thousands of dollars a piece.
1. One of my favourite references, an oldy but a goody (shows what happens
to a hand put in conc. HF - good safety reminder) A.J. Rudge, The
Manufacture and Use of Fluorine and Its Compounds, Oxford University Press,
London, 1962.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Jim Kittel [mailto:[log in to unmask]]
Sent: February 19, 2002 9:37 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
That would certainly make VP more palatable. If not due to VOC taxes, why
are the fluids so expensive?
Jim Kittel
-----Original Message-----
From: James TerVeen [mailto:[log in to unmask]]
Sent: Tuesday, February 19, 2002 6:08 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
I do not think these are ozone depleter but they are very costly.
This is the statement that they give regarding there material
in the data you are talking about.
Hence, Fomblin and Galden perfluoropolyether fluids have a ZERO
Ozone Depletion Potential and are not classified as VOCs by the
EPA.
Brian Ellis
<b_ellis@PROTO To: [log in to unmask]
NIQUE.COM> cc:
Sent by: Subject: Re: [TN] Antw: [TN]
Vapor Phase
TechNet Soldering ReVisited!
<[log in to unmask]
RG>
02/16/02 03:01
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Brian Ellis
Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 °C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial
partner in LEADFREE that runs the VP trials told me that he has to use a
liquid with a boiling point of 270 deg.C and that there is nothing
available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the same
answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
>
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Date: Tue, 19 Feb 2002 17:19:36 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Antw: [TN] Reliability Testing of PTH
X-To: Guenter Grossmann <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
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Guenter,
Well said! I would add that certain tests that use coupons, dummy compontents, and/or special circuitry are not reliability tests at all. They are process indicator tests and even though they may have an impact on reliability they will not tell you if the product really works!
David A. Douthit
Manager
LoCan LLC
Guenter Grossmann wrote:
> Antonio
>
> To answer your question you have to ask yourself first what reliability is:
> Reliability = Ability of a given identity to fulfill the required mission within a given time frame in a defined environment under a given load with a required probability.
>
> This definition gives you the whole bandwidth on the parameters you have to look at.
> - Thermal
> - Mechanical
> - Thermomechanical
> - Electrical (Including EMC)
> - Humidity
> - Chemical attack (including corrosion)
>
> Depending on the application you have to choose the test sequence that has to be applied. No easy job.
>
> But be careful.
>
> - You are not only talking about testing. You talk about accelerated testing. This means you talk about physics of failure. For each test you choose you have to think about the failure mechanisms you are about to activate and you have to understand the influence of the testing parameters on that particular mechanism.
> Examples:
> . Chemical processes can be regarded at as thermally activated. This means, in a first attempt you can run a tests with at least 3 temperatures to evaluate the activation energy for the Arrhenius law you can apply to your problem. This activation energy might incorporate several mechanisms activated. However, for practical purposes this is precise enough. Based on this knowledge you can design the accelerated test that allows you an estimation of the reliability in the real world.
> . Solder joints. A problem that Werner an I work and discuss on for many years now. Assuming that our model holds, tin based solder joints deform with two deformation mechanisms. Grain Boundary Sliding and Dislocation Climb. Both contribute their own part to the degradation of the solder joint. Senseless accelerated testing will activate large amounts of DC that never occur in reality. It will therefor be very difficult to extrapolate (anyway always a dangerous thing to do) the results found to the real environment.
>
> - Reliability is a probability. This means, you need enough samples to find that number. Just ask the people finding failure rates of IC's they might give you an idea.
>
> However, you are not alone. As a matter of fact all these questions are subject to research and I only mentioned how difficult the business is to show that we scientists are real big cracks. Seriously, there is a lot of data around in literature, but it's not a small job to find them. On the other hand you might even not ask for reliability but comparative testing. In this case, where you have a known specimen that fulfills your reliability requirements you can design a test where you activate the interesting degradation mechanism(s) in both specimen to the same extend and compare the results of the two. Still not a peace of cake but a lot easier than starting from scratch.
>
> Still, it's a fun job. Most of the time.
>
> Best regards
>
> Guenter
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
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Date: Tue, 19 Feb 2002 16:17:41 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jana L. Carraway" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jana L. Carraway" <[log in to unmask]>
Subject: Soldermask photo?
In-Reply-To: <45EC695FE212D311A49D0000D11BAF7C053C6DE3@MBRC02>
MIME-Version: 1.0
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Greetings from the Pacific Northwest!
Would anyone have an SEM photo of a negative sidewall on solder mask that I
can use to make a point? I would be greatly appreciative!
Thank you,
Jana Carraway
MicroSystems Engineering, Inc.
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Date: Wed, 20 Feb 2002 09:19:01 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: How old is old?
X-To: Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Genny,
About 5 years is as long as you can store components and expect them to
still work afterwards. If they're "exercised" on a regular basis while in
proper storage (say every 6 months), they can last a lot longer, but it's
impossible to say how much longer.
If you can be assured that the components have bee properly stored and you
can use them up quickly enough, maybe he has got a good deal. I'ld check
their provenance pretty thoroughly first before buying, though.
Peter
Genny Gibbard
<Genny.Gibbard@W To: [log in to unmask]
AVECOM.CA> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] How old is old?
>
02/19/02 11:19
PM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to Genny Gibbard
One of the purchasers has asked if they can purchase some parts with a 2000
date code on them for 'a really great deal!' The part is an 8 lead uSOIC
package
At what point do you say they are too old?
I would appreciate info specific to this package or, just in general,
guidelines for chip or standard SM components. We do not use BGA's yet.
We
aren't trying to do lead free. We generally spec 60/40 HASL finish on our
boards.
Thanks for your time.
Genny Gibbard (mailto:[log in to unmask])
Product Transition and Support
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Date: Wed, 20 Feb 2002 01:54:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Mak <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Mak <[log in to unmask]>
Subject: Re: High temperature solder wire
X-To: [log in to unmask]
Thanks Mike
I have just dipped our hi-temp solder wire to a solder pot. It completely
dissolved within 7 sec.
Best Regards,
Eric
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Date: Wed, 20 Feb 2002 08:59:34 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Solder
Mime-Version: 1.0
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Antonio
None when it comes to reliability or production. When AgPd plated =
terminations are used the 2 percent silver slow down the dissolution of =
the metallisation during the soldering process.
Best regards
Guenter
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Wed, 20 Feb 2002 02:02:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Mak <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Mak <[log in to unmask]>
Subject: Re: High temperature solder wire
X-To: [log in to unmask]
Hello guy,
I have no knowledge about the spot mask. Could you elaborate this method?
Best Regards,
Eric
On Tue, 19 Feb 2002 13:28:10 -0500, Guy Ramsey <[log in to unmask]> wrote:
>Have you considered temporary spot mask? It works okay for chip resistors
>and capacitors, SOT. Not too good for SOIC, stuff gets stuck under the
>little legs.
>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]]On Behalf Of makshuwing
>> Sent: Tuesday, February 19, 2002 6:18 AM
>> To: [log in to unmask]
>> Subject: Re: [TN] High temperature solder wire
>>
>>
>> Hello Peter,
>>
>> Adhesive dispensing, chip placement, reflow(glue curing), manual
>> insertion, then wave soldering are our normal processes. After
>> reflow we sometimes find some mis-aligned chips or missing
>> components. The area of glue in contact with the surface of the
>> mis-aligned chip could be less than normal and the adhesion force
>> is insufficient to protect the chip from dropping off during
>> wave soldering. Therefore we want to use high temp solder to
>> solder the mis-aligned chips prior to wave soldering. We know
>> that we could detach the parts after reflow and hand solder the
>> parts after the wave soldering but we think adding hi-temp solder
>> is the simpliest way since there is no detachment process is involved.
>>
>> Eric
>> ----- Original Message -----
>> From: "Peter Barton" <[log in to unmask]>
>> To: <[log in to unmask]>
>> Sent: Tuesday, February 19, 2002 12:41 AM
>> Subject: Re: [TN] High temperature solder wire
>>
>>
>> > If you are going to the trouble to hand solder these parts on
>> why not fit
>> > them after the wave solder process and just tack them on,
>> applying a dab of
>> > rework flux first, then reflowing the solder that will be present on
the
>> > pads? Saves the difficulty of using high temp solder pre-wave, and
quite
>> > likely excessive solder on the joints post wave (the solder in your
bath
>> > will wet to the high temp. joints already made). I have seen a similar
>> > problem when tack soldering large multi way connectors with high temp.
>> > solder pre-wave.
>> >
>> > Regards,
>> >
>> > Peter Barton
>> >
>> > ===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
>> > 18/02/02 13:40
>> > >Hi all,
>> > >
>> > >We are currently using adhesive to glue chips on PCB and then
>> run the board on reflow oven
>> > followed by wave soldering. After the reflow process we need to
>> rework some
>> > chips occasionally due to chip miss-alignment or missing. To do
>> the rework
>> > we have to remove the original glue, re-glue the chips and let
>> the board go
>> > through the reflow process again. Now we want to eliminate this loop by
>> > using hi-temp solder wire (melting point 268-302 degree C) to solder
the
>> > reworked chips without adhesive, then let the reworked board
>> directly go to
>> > wave soldering with solder pot temperature around 245 degree C.
>> > >
>> > >Has anyone using this method seen problems?
>> > >
>> > >Eric
>> >
>> >
>> > -----------------------------------------------------------------------
>> > Peter Barton
>> >
>> > ACW Technology Ltd
>> > Dinas Isaf West
>> > Tonypandy
>> > Mid Glamorgan. CF40 1XX Wales
>> >
>> > Tel: 01443 425200 Fax: 01443 436882
>> >
>> > International Tel : +44 1443 425200 Fax : +44 1443 436882
>> >
>> > E-mail: [log in to unmask] Website/URL: www.acw.co.uk
>> >
>> >
>> ------------------------------------------------------------------
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>> 847-509-9700 ext.5315
>> >
>>
>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Hello guy,
I have no knowledge about the spot mask. Could you elaborate this method?
Best Regards,
Eric
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Date: Wed, 20 Feb 2002 02:07:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Mak <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Mak <[log in to unmask]>
Subject: Static conducive solder sucker
I am looking for an ESD safe spring-loaded piston type solder sucker but
all suckers provided by several renowned Japanese manufacturers are not
real ESD safe. The tip and the handling body are ok but the push rod
generates more than a thousand volt when the rod is activated and released.
Is it true that there is no real ESD safe piston type solder sucker.
Best Regards
Eric
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Date: Wed, 20 Feb 2002 06:06:37 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
X-To: [log in to unmask]
MIME-Version: 1.0
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Bev,
In my haste to reply I said 'VOC taxes' but I meant ozone depletion =
taxes (I
was thinking of the taxes levied on the CFC's, specifically Freon, =
which
eventually drove them out of common use). =20
Thanks for the insight and details on why the fluids are so costly. =
Sounds
like a very expensive and difficult process. Unfortunately I don't see =
any
easy answers if one converts to lead free solder.
Jim KIttel
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Tuesday, February 19, 2002 4:54 PM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
Jim,
These are expensive because:
1) There are few companies that make them
2) Demand is low
3) Working with fluorine compounds usually ain't cheap. To give you =
some
idea:
For making perfluoro compounds "A number of reactive metal fluorides =
have
been employed, including AgF2, PbF4, HgF2 and Co F3, the last being the =
most
useful. The general reaction may be expressed as follows:
>CH2 + 4CoF3--->CF2 + 4CoF2 + 2HF (at 110 - 400 C)
followed, in a separate stage, by
2CoF2 + F2 ---> 2CoF3 (250 - 400C)"1.
It is not economical because so much fluorine ends up as HF and there =
are a
whole pile of side reactions, which increase in number as you try to =
make
longer and longer chains (No surprise there.)
There may be newer, better ways, but you can bet there are still lots =
of
nasty things to have to deal with. So unless the manufacturer wants to =
have
a lot of dissolved workers, everything is going to be done in high =
quality
nickel or Monel metal, with valves that costs thousands of dollars a =
piece.
1. One of my favourite references, an oldy but a goody (shows what =
happens
to a hand put in conc. HF - good safety reminder) A.J. Rudge, The
Manufacture and Use of Fluorine and Its Compounds, Oxford University =
Press,
London, 1962.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Jim Kittel [mailto:[log in to unmask]]
Sent: February 19, 2002 9:37 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
That would certainly make VP more palatable. If not due to VOC taxes, =
why
are the fluids so expensive?
Jim Kittel
-----Original Message-----
From: James TerVeen [mailto:[log in to unmask]]
Sent: Tuesday, February 19, 2002 6:08 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] Vapor Phase Soldering ReVisited!
I do not think these are ozone depleter but they are very costly.
This is the statement that they give regarding there material
in the data you are talking about.
Hence, Fomblin and Galden perfluoropolyether fluids have a ZERO
Ozone Depletion Potential and are not classified as VOCs by the
EPA.
Brian Ellis
<b_ellis@PROTO To: [log in to unmask]
NIQUE.COM> cc:
Sent by: Subject: Re: [TN] Antw: =
[TN]
Vapor Phase
TechNet Soldering ReVisited!
<[log in to unmask]
RG>
02/16/02 03:01
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Brian Ellis
Guenter
See http://www.ausimont.com/docs/gald_vapor.html
This gives you details of fluids with BPs of 155, 166, 200, 210, 215,
230, 240 and 260 =B0C. Surely you can find one to suit almost any
application in that range.
However, I repeat my earlier warning that these products are horrific
global warmers and are not exactly given away with a packet of corn
flakes.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Jim
>
> I believe the VP is still a good principle. However, the industrial
partner in LEADFREE that runs the VP trials told me that he has to use =
a
liquid with a boiling point of 270 deg.C and that there is nothing
available that boils around 230 deg.
> I had problem to believe this but also after asking again I got the =
same
answer.
>
> Best regards
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
>
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Date: Wed, 20 Feb 2002 08:33:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: how old is too old?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
>From: Genny Gibbard [mailto:[log in to unmask]]
>Sent: Tuesday, February 19, 2002 7:19 AM
>To: [log in to unmask]
>Subject: [TN] How old is old?
>One of the purchasers has asked if they can purchase some parts with a 2000
>date code on them for 'a really great deal!' The part is an 8 lead uSOIC
>package
>
>At what point do you say they are too old?
Do a solderability test. If they pass, they'll be fine!
John
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Date: Wed, 20 Feb 2002 08:59:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: How old is old?
X-To: Genny Gibbard <[log in to unmask]>
In-Reply-To: <A71205756C62D411B06900B0D03DC136B1C1B9@CONNECTOR>
MIME-Version: 1.0
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I was surprised by Peter's response to your post. I wonder what he means by
exercised.
I have work experience with manufactures of electronic instruments that are
serviced for 50+ years (Been in business since just before W.W.II. In the
early seventies they transitioned from analog to digital 27 V NMOS logic
devices. They have components in storage from that time frame. There are
occasional problems with lead frames that have failed (rusted under the
gold) and occasional bad lots of die (didn't test everything before it was
placed in storage). But, mostly, they are able to service and guarantee
their work using solid state devices that were manufactured over 25 years
ago. They use (stored in their own vaults or purchased through brokers)
components that have been out of production for five to ten years; these
would include Crowbar ICs, Switch-mode regulator ICs, Bucket-Brigade ICs, OP
AMPs, Voltage Regulators and Transistors. I cannot recall getting bad (non
functional) parts but we did have our soldering problems.
Occasionally, there were differences in the performance of components that
required changes to passive component values in some designs. We believed
this was due to variation that was present at the time the components were
made rather than related to changes over time.
Relays or other Electro-mechanical devices are a concern (reed switches,
motors, valves, solenoids). We had problems with them. But it would be hard
to place a shelf life on them, are they hermetically sealed (many were to
allow chemical cleaning)? Most of the problems I experienced were with open
parts. Today many relays are open assuming no-clean processing.
Electrolytic capacitors, carbon resistors are a concern but carbon resistors
are really a thing of the past. SMT Electrolytic cans, five years would be a
very conservative limit if you are talking about function.
Solderabiltiy is your main concern Genny.
Guy Ramsey
Senior Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Genny Gibbard
> Sent: Tuesday, February 19, 2002 10:19 AM
> To: [log in to unmask]
> Subject: [TN] How old is old?
>
>
> One of the purchasers has asked if they can purchase some parts
> with a 2000
> date code on them for 'a really great deal!' The part is an 8 lead uSOIC
> package
> At what point do you say they are too old?
> I would appreciate info specific to this package or, just in general,
> guidelines for chip or standard SM components. We do not use
> BGA's yet. We
> aren't trying to do lead free. We generally spec 60/40 HASL finish on our
> boards.
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
> Product Transition and Support
>
> ------------------------------------------------------------------
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>
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Date: Wed, 20 Feb 2002 09:03:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solder
X-To: Antonio Souza <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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There was a pretty good thread on this subject last year. Check the archives
Highlights, stronger wetting forces, less leaching, brighter joints.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Antonio Souza
> Sent: Tuesday, February 19, 2002 8:59 AM
> To: [log in to unmask]
> Subject: [TN] Solder
>
>
> Please
>
> Could someone tell me the advantages and disadvantages of using solder
> Sn/Pb/Ag instead of Sn/Pb.
>
>
> Thanks
>
> Antonio
> Inpe-Brazil
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Date: Wed, 20 Feb 2002 09:02:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dave Blevins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dave Blevins <[log in to unmask]>
Subject: Industry Standards
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hello
Does anyone know of any industry standards for scrap/or rework in the
Circuit Board Industry?
THANKS
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Date: Wed, 20 Feb 2002 08:12:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: How old is old?
MIME-Version: 1.0
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Thanks for all the responses.
The supplier has told us they are still sealed in their original factory
reels and packaging and are 100% guaranteed against quality issues.
So I think we'll go for it!
Thanks again.
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Date: Wed, 20 Feb 2002 08:37:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re:
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Bill,=20
contact me offline with some questions and I'll try to answer them for =
you. I am the resident 5DX Engineer here.
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
(512)796-1997 cell
(512)388-0898 fax
[log in to unmask]
>>> [log in to unmask] 02/19/02 02:31PM >>>
Hello all, many thanks to all who answered and helped with my questions
about my Hot Air Knife problems... now I have another question.
We have a brand new Agilent 5DX x-ray system. Maybe some users of this
equipment could give me their impression of how well this machine =
evaluates
Plastic BGA solder joints and also, how well it does with bottom side SMD
that has been wave soldered.
Bill...
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Date: Wed, 20 Feb 2002 16:05:26 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Owen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: Depanalizing mouse bite
X-To: Alain Savard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Alain,
We depanelize high volumes of scored pcb's with connectors and switches etc
along their edges.
Steve.
-----Original Message-----
From: Alain Savard [mailto:[log in to unmask]]
Sent: 19 February 2002 15:37
To: [log in to unmask]
Subject: [TN] Depanalizing mouse bite
Hi Netters,
What kind of tool is required to depanalize boards with mouse-bite patterns
along the edge?
(Scoring is not in the realm of possible avenues here, there are connectors
and switches along the edge.)
Thanks,
Alain Savard
QA - PCB
CAE Inc.
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Date: Wed, 20 Feb 2002 10:57:21 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard Hawkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard Hawkins <[log in to unmask]>
Subject: pads for so package and sop package?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have a situation in which my company wishes to "dual source" an IC, the
only catch is that one is an so package and the other is a sop package.
This is a new problem for me. I am looking to the experience and expertise
of this list to help me come to the correct answer for my company.
Any advise/opinion/experience will be appreciated.
TIA
Sincerely,
Richard Hawkins
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Date: Wed, 20 Feb 2002 10:14:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: How old is old?
X-To: Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Guy,
The obvious answer is that modern SMT parts are totally different animals than those of past decades.
Even the U.S. Army has major concerns about long term storage of modern components and circuitry.
David A. Douthit
Manager
LoCan LLC
Guy Ramsey wrote:
> I was surprised by Peter's response to your post. I wonder what he means by
> exercised.
>
> I have work experience with manufactures of electronic instruments that are
> serviced for 50+ years (Been in business since just before W.W.II. In the
> early seventies they transitioned from analog to digital 27 V NMOS logic
> devices. They have components in storage from that time frame. There are
> occasional problems with lead frames that have failed (rusted under the
> gold) and occasional bad lots of die (didn't test everything before it was
> placed in storage). But, mostly, they are able to service and guarantee
> their work using solid state devices that were manufactured over 25 years
> ago. They use (stored in their own vaults or purchased through brokers)
> components that have been out of production for five to ten years; these
> would include Crowbar ICs, Switch-mode regulator ICs, Bucket-Brigade ICs, OP
> AMPs, Voltage Regulators and Transistors. I cannot recall getting bad (non
> functional) parts but we did have our soldering problems.
>
> Occasionally, there were differences in the performance of components that
> required changes to passive component values in some designs. We believed
> this was due to variation that was present at the time the components were
> made rather than related to changes over time.
>
> Relays or other Electro-mechanical devices are a concern (reed switches,
> motors, valves, solenoids). We had problems with them. But it would be hard
> to place a shelf life on them, are they hermetically sealed (many were to
> allow chemical cleaning)? Most of the problems I experienced were with open
> parts. Today many relays are open assuming no-clean processing.
>
> Electrolytic capacitors, carbon resistors are a concern but carbon resistors
> are really a thing of the past. SMT Electrolytic cans, five years would be a
> very conservative limit if you are talking about function.
>
> Solderabiltiy is your main concern Genny.
>
> Guy Ramsey
> Senior Technician / Instructor
> E-Mail: [log in to unmask] <mailto:[log in to unmask]>
> Ph: (610) 362-1200 x107
> Fax: (610) 362-1290
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Genny Gibbard
> > Sent: Tuesday, February 19, 2002 10:19 AM
> > To: [log in to unmask]
> > Subject: [TN] How old is old?
> >
> >
> > One of the purchasers has asked if they can purchase some parts
> > with a 2000
> > date code on them for 'a really great deal!' The part is an 8 lead uSOIC
> > package
> > At what point do you say they are too old?
> > I would appreciate info specific to this package or, just in general,
> > guidelines for chip or standard SM components. We do not use
> > BGA's yet. We
> > aren't trying to do lead free. We generally spec 60/40 HASL finish on our
> > boards.
> > Thanks for your time.
> >
> > Genny Gibbard (mailto:[log in to unmask])
> > Product Transition and Support
> >
> > ------------------------------------------------------------------
> > ---------------
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> > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > ------------------------------------------------------------------
> > ---------------
> >
>
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Date: Wed, 20 Feb 2002 12:44:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: pads for so package and sop package?
X-To: Richard Hawkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Richard,
If you send me the recommended footprints, I can give you some general
advice in the Pick and Place / In Circuit Test Pad design. We have done a
few duals, but I try to "prohibit" them as you use up board real estate very
quickly.
Kerry
-----Original Message-----
From: Richard Hawkins [mailto:[log in to unmask]]
Sent: Wednesday, February 20, 2002 11:57 AM
To: [log in to unmask]
Subject: [TN] pads for so package and sop package?
I have a situation in which my company wishes to "dual source" an IC, the
only catch is that one is an so package and the other is a sop package.
This is a new problem for me. I am looking to the experience and expertise
of this list to help me come to the correct answer for my company.
Any advise/opinion/experience will be appreciated.
TIA
Sincerely,
Richard Hawkins
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Date: Wed, 20 Feb 2002 13:42:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Just In Time deliveries
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Schindler Elevator Corp is moving to a just-in-time delivery system for
PWB's. Can anyone provide me with some
advice and/or publications on the do and dont's of a just-in-time service?
Thankyou
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Date: Wed, 20 Feb 2002 13:54:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
Just in time is Lean is pull is a dedicated, functional, management backed,
focused, DFM/CE oriented, waste eliminated, rule based, quality system.
Can't go on here,
MoonMan
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Date: Wed, 20 Feb 2002 13:59:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: MILITARY STYLE ALMOST LCCC PARTS
Kind folks,
I have another board/adventure requiring simple coplanaty issues be resolved
and I know how to do this so don't need advice. Need to know, from R/F
folks, if anyone is using the following:
EM Research Inc. LX-2050-05
EM Research Inc. LX-1450-01
These parts are castellated, are gold plated castellations, are PCB material
interposer types requiring very flat surfaces on which to be mounted. No
problems but for leadless and gold plating. Wondering if anyone out there
has experience with the aforementioned parts and results.
MoonMan
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Date: Wed, 20 Feb 2002 15:20:30 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Moon man:
I a not so long ago life, we used these with great results. We had them
placed on a normal FR-4 board that was HASL. We had a number of 25 mil
pitch components on the board but the stencil thickness was if I remember
.007 thick. I do not remember the parts being gold plated but if they
were we had no problem with the parts in either placement or reliability.
We made a few thousand boards and as I said I can never remember any issues
with these parts.
Just my 2cents worth
Earl Moon
<[log in to unmask] To: [log in to unmask]
.COM> cc:
Sent by: Subject: [TN] MILITARY STYLE ALMOST LCCC PARTS
TechNet
<[log in to unmask]
RG>
02/20/02 02:59
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Earl Moon
Kind folks,
I have another board/adventure requiring simple coplanaty issues be
resolved
and I know how to do this so don't need advice. Need to know, from R/F
folks, if anyone is using the following:
EM Research Inc. LX-2050-05
EM Research Inc. LX-1450-01
These parts are castellated, are gold plated castellations, are PCB
material
interposer types requiring very flat surfaces on which to be mounted. No
problems but for leadless and gold plating. Wondering if anyone out there
has experience with the aforementioned parts and results.
MoonMan
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Date: Wed, 20 Feb 2002 12:52:54 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: 4101 / Sheets
MIME-Version: 1.0
Content-Type: text/plain
The current revision of IPC4101 is now 4+ years old. There have been a lot
of new materials (Rogers 4000, APPE) introduced during that time that don't
seem to fit any of the existing "/" sheet definitions. Does anybody know
how new designations are created and how the spec gets updated?
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Date: Wed, 20 Feb 2002 13:14:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Safe processing window
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_KOU4uCRd88aluixLwwz7ew)"
This is a multi-part message in MIME format.
--Boundary_(ID_KOU4uCRd88aluixLwwz7ew)
Content-type: text/plain; charset=Windows-1252
Content-transfer-encoding: 7BIT
A couple of questions for what has become my best engineering resource.
Management has asked me to provide a re-flow profile for our product, a surface mount component built on FR-4 with lead free solder. I am reluctant, I would prefer to generate a "safe processing window" type document. As manufacturing professionals what do you prefer?
The window would spec ; max 2 C /sec ramp up, max 60 sec dwell above 180 C, max 220 C peak, and a 2 C/sec max ramp down. Could you live with this?
Many thanks for your help,
Dan
--Boundary_(ID_KOU4uCRd88aluixLwwz7ew)
Content-type: text/html; charset=Windows-1252
Content-transfer-encoding: 7BIT
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=windows-1252">
<META content="MSHTML 6.00.2600.0" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT size=2>A couple of questions for what has become my best engineering
resource.</FONT></DIV>
<DIV><FONT size=2></FONT> </DIV>
<DIV><FONT size=2>Management has asked me to provide a re-flow profile for our
product, a surface mount component built on FR-4 with lead free solder. I am
reluctant, I would prefer to generate a "safe processing window" type document.
As manufacturing professionals what do you prefer? </FONT></DIV>
<DIV><FONT size=2></FONT> </DIV>
<DIV><FONT size=2>The window would spec ; max 2 C /sec ramp up,
max 60 sec dwell above 180 C, max 220 C peak, and a 2 C/sec max ramp down. Could
you live with this?</FONT></DIV>
<DIV><FONT size=2></FONT> </DIV>
<DIV><FONT size=2>Many thanks for your help,</FONT></DIV>
<DIV><FONT size=2>Dan</FONT></DIV></BODY></HTML>
--Boundary_(ID_KOU4uCRd88aluixLwwz7ew)--
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=========================================================================
Date: Wed, 20 Feb 2002 16:53:41 -0500
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gerard O'Brien <[log in to unmask]>
Organization: Photocircuits Corporation
Subject: Re: 4101 / Sheets
X-To: "Mcmaster, Michael" <[log in to unmask]>
Michael- there is an up-dated 4101 -Decemeber 2001 IPC-4101A.
Regards
Gerard O'Brien
-----Original Message-----
From: Mcmaster, Michael [SMTP:[log in to unmask]]
Sent: Wednesday, February 20, 2002 3:53 PM
To: [log in to unmask]
Subject: [TN] 4101 / Sheets
The current revision of IPC4101 is now 4+ years old. There have been a lot
of new materials (Rogers 4000, APPE) introduced during that time that don't
seem to fit any of the existing "/" sheet definitions. Does anybody know
how new designations are created and how the spec gets updated?
---------------------------------------------------------------------------------
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Date: Wed, 20 Feb 2002 16:57:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Safe processing window
X-To: "Dan R. Johnson" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0011_01C1BA2F.B010BA00"
This is a multi-part message in MIME format.
------=_NextPart_000_0011_01C1BA2F.B010BA00
Content-Type: text/plain;
charset="Windows-1252"
Content-Transfer-Encoding: 7bit
What you just wrote is a profile. But, more importantly, you said "lead
free". What alloy are you using? This profile looks too cool for lead free.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dan R. Johnson
Sent: Wednesday, February 20, 2002 4:15 PM
To: [log in to unmask]
Subject: [TN] Safe processing window
A couple of questions for what has become my best engineering resource.
Management has asked me to provide a re-flow profile for our product, a
surface mount component built on FR-4 with lead free solder. I am reluctant,
I would prefer to generate a "safe processing window" type document. As
manufacturing professionals what do you prefer?
The window would spec ; max 2 C /sec ramp up, max 60 sec dwell above 180
C, max 220 C peak, and a 2 C/sec max ramp down. Could you live with this?
Many thanks for your help,
Dan
------=_NextPart_000_0011_01C1BA2F.B010BA00
Content-Type: text/html;
charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1252">
<META content=3D"MSHTML 5.50.4912.300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D430285421-20022002><FONT face=3DArial size=3D2>What =
you just wrote=20
is a profile. But, more importantly, you said "lead free". What =
alloy are=20
you using? This profile looks too cool for lead =
free. </FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT =
size=3D2>Bob<BR><BR>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<BR>Robert=20
Barr<BR>Manufacturing Engineering<BR>Formation, Inc.<BR>Voice: =
856-234-5020=20
x3035<BR>Fax: 856-234-6679 </FONT></P>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid; MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Dan R. =
Johnson<BR><B>Sent:</B>=20
Wednesday, February 20, 2002 4:15 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Safe processing=20
window<BR><BR></FONT></DIV>
<DIV><FONT size=3D2>A couple of questions for what has become my best=20
engineering resource.</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT size=3D2>Management has asked me to provide a re-flow =
profile for our=20
product, a surface mount component built on FR-4 with lead free =
solder. I am=20
reluctant, I would prefer to generate a "safe processing window" type=20
document. As manufacturing professionals what do you prefer? =
</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT size=3D2>The window would spec ; max 2 =
C /sec ramp=20
up, max 60 sec dwell above 180 C, max 220 C peak, and a 2 C/sec max =
ramp down.=20
Could you live with this?</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<DIV><FONT size=3D2>Many thanks for your help,</FONT></DIV>
<DIV><FONT size=3D2>Dan</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0011_01C1BA2F.B010BA00--
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Date: Wed, 20 Feb 2002 17:00:15 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Antw: [TN] Vapor Phase Soldering ReVisited!
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2b.22cffc3b.29a5766f_boundary"
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Bev,
I know exactly what you to and not worry about I also can give you the
advantages
disadvantages. How, it would take to long to explain on the TeckNet. If you
would like to talk to me I can be reach at 71829-3539.
Larry Swayer
--part1_2b.22cffc3b.29a5766f_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Bev,
<BR>
<BR>I know exactly what you to and not worry about I also can give you the advantages
<BR>disadvantages. How, it would take to long to explain on the TeckNet. If you would like to talk to me I can be reach at 71829-3539.
<BR>
<BR>Larry Swayer </FONT></HTML>
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Date: Wed, 20 Feb 2002 16:01:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tostevin, Bruce" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tostevin, Bruce" <[log in to unmask]>
Subject: decapping molded tantalum caps
MIME-Version: 1.0
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I'm trying to remove the epoxy encapsulant from some garden variety smt,
molded tantalum caps - Kemet T491 and T495 series. Hot Dynasolve 185 won't
touch it and I don't want to use any fuming acids on the parts. Any tips on
what will either dissolve or soften this encapsulant? It's tough stuff.
Bruce Tostevin
Benchmark Electronics
Hudson, NH
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Date: Wed, 20 Feb 2002 15:10:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Edwards <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Edwards <[log in to unmask]>
Subject: Re: 4101 / Sheets
X-To: "Mcmaster, Michael" <[log in to unmask]>
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A good start is to get a copy of the new IPC-4101A released December 2001.
The IPC Technical Review also tracks what is happening on specification
reviews and I am sure the IPC.org web site also probably has it also. New
materials are usually added at the working sessions on specification
revision at IPC EXPO and the annual meeting later in the year at the request
of the material supplier or a user. The 3-11 subcommittee(4101A) is chaired
by Doug Sober of Polyclad Laminates.
----- Original Message -----
From: "Mcmaster, Michael" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 20, 2002 1:52 PM
Subject: [TN] 4101 / Sheets
> The current revision of IPC4101 is now 4+ years old. There have been a
lot
> of new materials (Rogers 4000, APPE) introduced during that time that
don't
> seem to fit any of the existing "/" sheet definitions. Does anybody know
> how new designations are created and how the spec gets updated?
>
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Date: Wed, 20 Feb 2002 14:16:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: Earl Moon <[log in to unmask]>
MIME-version: 1.0
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Hey Earl,
This product construction is very similar to ours.
Last year I made several visits to a CM in the San Jose area who was having
trouble with the solder of "our" parts. Turns out that they were having
trouble with any part of this type construction, filters, vco's pll's etc.
Here's what I learned from that exercise;
1) Don't let anyone X-ray the parts. Since the castelations are so large
(compared to std leadless ceramic chip carriers) they tend to suck up
solder. X-ray analysis shows voids on the bottom pads. This is not a
problem since the electrical connection is to the top side through the "half
moon via" aka castelation. The connection is ok mechanically too, my
customers component engineer tore a part off the board with vise grips, the
PCB failed before the solder connection. (This ended our discussion with the
CM about the reliability of the solder joint.)
2) This shouldn't be a problem with EM Research but watch out for burrs in
the castelations, they inhibit a good filet.
The gold plating doesn't seem to do anything but help with this type of
part. We use it on some of our high end parts but avoid it because of cost
considerations on the commodity product lines.
Hope you find this helpful,
Dan
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Date: Wed, 20 Feb 2002 17:57:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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JIT is a discipline, a method of improving processes.
Inventory hides problems with processes. When you lower your inventory you
expose problems. Think of it this way. Your business is a ship floating on a
sea of inventory. When you lower the level you expose rocks. You need to
identify the rocks, avoid them, remove them then lower the level some more.
If you simply lower the level (Simply “Move to Just in time deliveries”) you
will crash on the rocks.
JIT is most frequently discussed in the context of quality management.
Kanban is another term for “pull systems”. Do a Google search on Kanban.
Last week someone was looking for Lean Manufacturing Information. There are
some links in the TechNet Archives. They are related disciplines.
Try this link: http://www.apics.org/ as well.
Guy Ramsey
Senior Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of
> [log in to unmask]
> Sent: Wednesday, February 20, 2002 1:43 PM
> To: [log in to unmask]
> Subject: [TN] Just In Time deliveries
>
>
> Schindler Elevator Corp is moving to a just-in-time delivery system for
> PWB's. Can anyone provide me with some
> advice and/or publications on the do and dont's of a just-in-time service?
>
> Thankyou
>
> ------------------------------------------------------------------
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Date: Thu, 21 Feb 2002 09:58:42 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard van Beveren <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard van Beveren <[log in to unmask]>
Subject: Re: Safe processing window
X-To: "Dan R. Johnson" <[log in to unmask]>
Mime-Version: 1.0
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Dan,
Depends on the solder - the window you suggest may be very roughly OK for
conventional solder but if you are using lead free, then your reflow temp
will certainly need to be much higher (check the specs of the solder).
Also, in my experience, a 2 C/sec ramp up is a little conservative - if you
have a good "soak" or level period before rising to relfow you can even
things out and so ramp up a bit faster (never had troubles with 2.5 C/sec).
2 C/sec ramp down is definitely slow and there are probably advantages in
dropping off much faster, particularly from the reflow peak to well under
liquidous (maybe as fast as 4 C/sec?).
Just some thoughts.
Richard van Beveren
NEWTRONICS PTY LTD
> -----Original Message-----
> From: Dan R. Johnson [SMTP:[log in to unmask]]
> Sent: Thursday, 21 February 2002 08:15
> To: [log in to unmask]
> Subject: [TN] Safe processing window
>
> A couple of questions for what has become my best engineering resource.
>
> Management has asked me to provide a re-flow profile for our product, a
> surface mount component built on FR-4 with lead free solder. I am
> reluctant, I would prefer to generate a "safe processing window" type
> document. As manufacturing professionals what do you prefer?
>
> The window would spec ; max 2 C /sec ramp up, max 60 sec dwell above 180
> C, max 220 C peak, and a 2 C/sec max ramp down. Could you live with this?
>
> Many thanks for your help,
> Dan
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Date: Wed, 20 Feb 2002 18:14:55 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: 4101 / Sheets
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Two part question... The first is relative to the beloved 4101; I think the
spec your looking for is actually the IPC-125 "Spec for Substrate of High
Speed/Freq" (or roughly titled like that). Once you dive into the wonderful
world of IPC specs (I am not being sarcastic) you find directional guides as
well. One such document is IPC-107 "STD for PWB Matl" it gives a title and
number run down.
Second part... Actually I don't know how to introduce "new" materials... and
shame on me for not knowing. The IPC being technical based by industry
contributions (technical input) needs some level of "volunteer time." To
that end I plan on attending the IPC west in March and being more ingrained.
The bottom-line, the material you refer to (4K series) is not in the 125 spec
(or any other). It is important to call this type of material by name and
supplier due to it does not have a direct replacement that will not require
some amount of redesign or reengineering. Even in a military environment I
use a "source/spec control" drawing.
Boston Brad
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Date: Wed, 20 Feb 2002 18:15:22 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Just In Time deliveries
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Date: Wed, 20 Feb 2002 17:22:52 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: pads for so package and sop package?
X-To: Richard Hawkins <[log in to unmask]>
In-Reply-To: <80F28D36C87ED51180F800600821574921296D@CEIP1P>
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Hi Richard,
It depends on the actual component dimensions and pinouts. Sometimes it
works out, sometimes it doesn't. Unfortunately, not all component
manufacturers mean the same thing when they say "SO" and "SOP". If you'd
like to send me drawings and pinouts of the two packages (or at least a full
manufacturer's part number for each), I'd be happy to look them over.
Something to consider is that if the pads from one component are under the
body of the other and there is not much standoff height, I could imagine
some trouble. If this is indeed a problem, you would need a separate
stencil for each variant of the assembly.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Richard Hawkins
> Sent: Wednesday, February 20, 2002 10:57 AM
> To: [log in to unmask]
> Subject: [TN] pads for so package and sop package?
>
>
> I have a situation in which my company wishes to "dual source" an IC, the
> only catch is that one is an so package and the other is a sop package.
>
> This is a new problem for me. I am looking to the experience and
> expertise
> of this list to help me come to the correct answer for my company.
>
> Any advise/opinion/experience will be appreciated.
>
> TIA
>
> Sincerely,
>
>
> Richard Hawkins
>
> ------------------------------------------------------------------
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>
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Date: Wed, 20 Feb 2002 18:29:00 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Just In Time deliveries
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Sorry folks, I think I had a false send there... double click madness...
JIT is great, it gets you out of the inventory business. We do quite a bit
Just In Time deliveries. It requires a sound relationship and good contract.
We supply boads per week or month or in some cases there are folks who will
inventory your shelves and replenish accordingly. What's nice in the bare
board business is there is no overage gone to waste and parts can be built
during non busy times maximizing factory capacity. It is a win/win.
Wonderful.
In a more global perspective the book REENGINEERING the CORPORATION gives a
good example of Fords "workforce 2000" and their JIT.
Boston Brad
781 858 9783
... a PCB guy with Coretec, PCB supplier
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Date: Wed, 20 Feb 2002 17:05:05 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: 4101 / Sheets
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
I don't want to speak for Doug or Eric,but we are planning on addressing
that issue in the Materials Sub-committee meeting at IPC Expo.
Dewey
> -----Original Message-----
> From: Mcmaster, Michael [SMTP:[log in to unmask]]
> Sent: Wednesday, February 20, 2002 1:53 PM
> To: [log in to unmask]
> Subject: [TN] 4101 / Sheets
>
> The current revision of IPC4101 is now 4+ years old. There have been a
> lot
> of new materials (Rogers 4000, APPE) introduced during that time that
> don't
> seem to fit any of the existing "/" sheet definitions. Does anybody know
> how new designations are created and how the spec gets updated?
>
> --------------------------------------------------------------------------
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Date: Wed, 20 Feb 2002 18:21:26 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi Greg,
Just in time is a great concept for reducing inventory. It depends on both
you and your supplier being able to predict your schedules fairly
accurately. It also requires that any changes in your demand or their
ability to supply be communicated a reasonable period in advance. This
means that your supplier must either have very reliable component and bare
board suppliers or be willing to inventory parts for you. Does this
describe your situation?
The just in time system works best when the design of the assembly is
stable, all processes are qualified and all supplier relationships are
tight. If a component on your assembly suddenly becomes short
industry-wide, will your supplier go to bat for you? Or will they call you
the week before a scheduled delivery and ask you to find and qualify an
alternative part that someone has 10,000 pieces of on the shelf? Similarly,
is your company willing to give your supplier adequate warning on
engineering changes or does your business require the ability to make last
minute changes?
This system is a thing of beauty when it works and your worst nightmare when
it doesn't. The potential cost savings can be easily eaten up and then some
if either party does not keep their end of the bargain. Make sure your own
purchasing department doesn't think this is a way to reduce inventory with
no extra work on their part. Then ask your supplier to show you how their
processes and supplier relationships give them the ability to reliably
deliver within a given time window. If you can, negotiate a bonus if they
stay within the window and variable penalties of they go outside it.
Finally, you need to consider if the electronics cost is a large enough
fraction of your total product cost to warrant the risk that you won't be
able to deliver to your customers on time?
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of
> [log in to unmask]
> Sent: Wednesday, February 20, 2002 12:43 PM
> To: [log in to unmask]
> Subject: [TN] Just In Time deliveries
>
>
> Schindler Elevator Corp is moving to a just-in-time delivery system for
> PWB's. Can anyone provide me with some
> advice and/or publications on the do and dont's of a just-in-time service?
>
> Thankyou
>
> ------------------------------------------------------------------
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Date: Wed, 20 Feb 2002 16:24:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: 4101 / Sheets
X-To: Ted Edwards <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Thanks for all the replies. I've guess I've gotten a partial answer. I was
unaware that 4101A and 4103 had been published. My updated copies haven't
made it to me yet.
The unanswered portion of my question is what happens as new slash sheets
are created between formal revisions of these documents? Surely the whole
100+ page documents revised just to incorporate a few new material slash
sheets, are they? Is there a subscription that I need to have to
automatically receive new slash sheets as they are added.
> ----------
> From: Ted Edwards[SMTP:[log in to unmask]]
> Sent: Wednesday, February 20, 2002 2:10 PM
> To: TechNet E-Mail Forum.; Mcmaster, Michael
> Subject: Re: [TN] 4101 / Sheets
>
> A good start is to get a copy of the new IPC-4101A released December 2001.
> The IPC Technical Review also tracks what is happening on specification
> reviews and I am sure the IPC.org web site also probably has it also. New
> materials are usually added at the working sessions on specification
> revision at IPC EXPO and the annual meeting later in the year at the
> request
> of the material supplier or a user. The 3-11 subcommittee(4101A) is
> chaired
> by Doug Sober of Polyclad Laminates.
>
> ----- Original Message -----
> From: "Mcmaster, Michael" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Wednesday, February 20, 2002 1:52 PM
> Subject: [TN] 4101 / Sheets
>
>
> > The current revision of IPC4101 is now 4+ years old. There have been a
> lot
> > of new materials (Rogers 4000, APPE) introduced during that time that
> don't
> > seem to fit any of the existing "/" sheet definitions. Does anybody
> know
> > how new designations are created and how the spec gets updated?
> >
> >
> --------------------------------------------------------------------------
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Date: Wed, 20 Feb 2002 18:35:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Re: 4101A & 4103 & L-125
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
IPC-4101A was released in January 2002
IPC-4103 supersedes IPC-L-125 and was released in January 2002. Staff =
liaison for these two docs is Tom Newton [log in to unmask]
More info www.ipc.org/bookstore=20
Document Revision Table is on the site http://www.ipc.org/html/fsstandards.=
htm and click the document revision table link. I've just submitted more =
than a dozen updates that will take a few days to get edited in. Check =
the date top of first page for latest info. Documents are numerical order =
regardless of any associated letters.
Cordially,
Jack
>>> [log in to unmask] 02/20/02 05:14PM >>>
Two part question... The first is relative to the beloved 4101; I think =
the
spec your looking for is actually the IPC-125 "Spec for Substrate of High
Speed/Freq" (or roughly titled like that). Once you dive into the =
wonderful
world of IPC specs (I am not being sarcastic) you find directional guides =
as
well. One such document is IPC-107 "STD for PWB Matl" it gives a title =
and
number run down.
Second part... Actually I don't know how to introduce "new" materials... =
and
shame on me for not knowing. The IPC being technical based by industry
contributions (technical input) needs some level of "volunteer time." To
that end I plan on attending the IPC west in March and being more =
ingrained.
The bottom-line, the material you refer to (4K series) is not in the 125 =
spec
(or any other). It is important to call this type of material by name and
supplier due to it does not have a direct replacement that will not =
require
some amount of redesign or reengineering. Even in a military environment =
I
use a "source/spec control" drawing.
Boston Brad
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Date: Thu, 21 Feb 2002 09:12:43 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: How old is old?
X-To: Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Guy,
The received wisdom I have from our design and engineering team is that
components stored undisturbed for more than 5 years may (and I stress
'may') have a significantly degraded reliability/functionality.
You talked of instruments having been serviced for 50+ years, and that was
the point I was trying to make - if equipment is in service (being used or
'exercised') on a regular basis, it tends to keep going, but degrade if
just left under 'normal' conditions. Consider a car that is left unused for
any length of time. My experience is that they never quite function
properly straight away if you then try to use it. On the other hand, a car
in regular use and properly maintained can go on for years and years.
Genny's situation is a judgement call, based on experience and risk
assesment. I agree that solderability will be the main issue, and that if
properly stored, 5 years is a conservative estimate of a component's
lifespan. Depends on the application. In my line of military avionics, we
don't like to take too many chances on mission critical equipment, and
component obsolescence/lifetime buys is a major issue with us -
increasingly so as technological changes advance at a seemingly exponential
rate. We're also increasingly having to use industrial grade parts instead
of MIL parts as availability of MIL parts diminishes. Additonal screening
to MIL levels is time consuming and expensive, so we have to minimise risks
in other ways. One of them is to limit the time for which components can be
stored. Regular exercise (power up, stimulation or whatever is appropriate)
helps to keep the parts in shape.
Peter
Guy Ramsey
<gramsey@ACIU To: [log in to unmask]
SA.ORG> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] How old is old?
<[log in to unmask]
ORG>
02/20/02
09:59 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Guy Ramsey
I was surprised by Peter's response to your post. I wonder what he means by
exercised.
I have work experience with manufactures of electronic instruments that are
serviced for 50+ years (Been in business since just before W.W.II. In the
early seventies they transitioned from analog to digital 27 V NMOS logic
devices. They have components in storage from that time frame. There are
occasional problems with lead frames that have failed (rusted under the
gold) and occasional bad lots of die (didn't test everything before it was
placed in storage). But, mostly, they are able to service and guarantee
their work using solid state devices that were manufactured over 25 years
ago. They use (stored in their own vaults or purchased through brokers)
components that have been out of production for five to ten years; these
would include Crowbar ICs, Switch-mode regulator ICs, Bucket-Brigade ICs,
OP
AMPs, Voltage Regulators and Transistors. I cannot recall getting bad (non
functional) parts but we did have our soldering problems.
Occasionally, there were differences in the performance of components that
required changes to passive component values in some designs. We believed
this was due to variation that was present at the time the components were
made rather than related to changes over time.
Relays or other Electro-mechanical devices are a concern (reed switches,
motors, valves, solenoids). We had problems with them. But it would be hard
to place a shelf life on them, are they hermetically sealed (many were to
allow chemical cleaning)? Most of the problems I experienced were with open
parts. Today many relays are open assuming no-clean processing.
Electrolytic capacitors, carbon resistors are a concern but carbon
resistors
are really a thing of the past. SMT Electrolytic cans, five years would be
a
very conservative limit if you are talking about function.
Solderabiltiy is your main concern Genny.
Guy Ramsey
Senior Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Genny Gibbard
> Sent: Tuesday, February 19, 2002 10:19 AM
> To: [log in to unmask]
> Subject: [TN] How old is old?
>
>
> One of the purchasers has asked if they can purchase some parts
> with a 2000
> date code on them for 'a really great deal!' The part is an 8 lead uSOIC
> package
> At what point do you say they are too old?
> I would appreciate info specific to this package or, just in general,
> guidelines for chip or standard SM components. We do not use
> BGA's yet. We
> aren't trying to do lead free. We generally spec 60/40 HASL finish on
our
> boards.
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
> Product Transition and Support
>
> ------------------------------------------------------------------
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Date: Wed, 20 Feb 2002 17:40:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: FR-04 questions
X-To: ATI ProcessGuy <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
This chart just shows how different prepreg glass styles (construction) are
used to build up different dielectric thicknesses. FR4-04 is .11mm or
.0043", FR4-06 is .0051". -17 is .0122" thick.
From a cost point of view, prepreg costs are basically the same per sheet
regardless of thickness. The exception is 106 which has a slight premium
because it's so thin there's always an associated amount of handling damage.
When building up a specified thickness, the fewer sheets of prepreg that are
used, the cheaper the construction. Compare -19 and -20. Both are .37mm
thick but one is 2 plies of 7628 while the other is a 3-ply mis of 2113 and
7628. -19 is cheaper becuase it only has 2 plies.
The downside is that the 7628 glass has relatively large bundles making it
difficult to drill. It also has a lower resin content which can limit it's
use in some stackups. There are also other drawbacks to using 7628 is some
applications.
Of course the main driving force in specifying materials is what dielectric
thickness do you need. If you need have 10 layer board .062" thick you're
not going to be able to use -17 or-19. It just won't fit.
Your trusty fabricator should be able to walk you through selecting the
appropriate thicknesses and constructions.
> ----------
> From: ATI ProcessGuy[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;ATI ProcessGuy
> Sent: Monday, February 18, 2002 3:10 PM
> To: [log in to unmask]
> Subject: [TN] FR-04 questions
>
> Per IPC 2222 (Feb 1998):
>
> Page 6, table 4-2 lists a selection chart for various Registered FR4
> types.
> I am familiar with FR4-04 and -06, however, it appears that for boards
> requiring to be very flat while still trying to watch cost, I would be
> better off specifying something like FR-4-17 or -19.
>
> It appears that the cost for 17 is middle of the road and cost for 19 is
> good. The kicker is that the farther down the table I go, it appears that
> the minus is the laminate is more difficult to drill.
>
> Is there articles anywhere out there regarding costs once we leave the
> FR-04-06, FR-04-04 material and start going into the -17 or 19 etc?
>
> What about the accuracy of the chart? It states material availability is
> good. Anyone out there had experience with this?
>
> Reason I ask, I have a 488 pin BGA 1 inch square I have to solder and they
> are asking me what to spec. Thanks in advance.
>
>
> _________________________________________________________________
> Send and receive Hotmail on your mobile device: http://mobile.msn.com
>
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Date: Thu, 21 Feb 2002 09:41:53 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Industry Standards
X-To: Dave Blevins <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
No. There may be some guidelines, but no standards that I've come across.
The decision to scrap a product or rework it is up to the QA Engineer and
depends on things like customer contract conditions (levels of rework
permissible), the value of the product, the nature, time and cost of rework
vs. replacement, and a degree of common sense and practicality. Look to
those things first, and if you can't find adequate guidance there, it has
to be a judgement call.
I feel it's dangerous to always look for standards to solve every problem
anyway. They can't and they won't, and if they tried to, they would
seriously constrain individual man's ability to assess things for himself
and make decisions. Genuine processes DO require standards for consistency
and repeatability, but the paths to arriving at a decision and taking that
decision should never be "standard" - unless you're a computer or a robot.
Peter
Dave Blevins
<dblevins@MCN To: [log in to unmask]
-MMPC.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Industry Standards
<[log in to unmask]
ORG>
02/20/02
10:02 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Dave Blevins
Hello
Does anyone know of any industry standards for scrap/or rework in the
Circuit Board Industry?
THANKS
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Date: Wed, 20 Feb 2002 21:09:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Just In Time deliveries
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JIT is a method of shifting your inventory into your supplier's lap.
If they can do it, great. If they can't, you have to pay for somebody who
will.
Strangely, a JIT shipment has longer lead times than any other - talk about
inflexibility!
RL
[log in to unmask]
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 20, 2002 6:29 PM
Subject: Re: [TN] Just In Time deliveries
> Sorry folks, I think I had a false send there... double click madness...
>
> JIT is great, it gets you out of the inventory business. We do quite a
bit
> Just In Time deliveries. It requires a sound relationship and good
contract.
> We supply boads per week or month or in some cases there are folks who
will
> inventory your shelves and replenish accordingly. What's nice in the bare
> board business is there is no overage gone to waste and parts can be built
> during non busy times maximizing factory capacity. It is a win/win.
> Wonderful.
> In a more global perspective the book REENGINEERING the CORPORATION gives
a
> good example of Fords "workforce 2000" and their JIT.
>
>
> Boston Brad
> 781 858 9783
> ... a PCB guy with Coretec, PCB supplier
>
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Date: Wed, 20 Feb 2002 22:49:16 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Safe processing window
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Hi Richard,
In a message dated 02/20/2002 19:00:45, [log in to unmask] writes:
>there are probably advantages in dropping off much faster, particularly from
the reflow peak to well
>under liquidous (maybe as fast as 4 C/sec?).
No, there is no advantage in dropping off much faster, in fact you risk
fracturing your just formed SJs due to warping because of the thermal shock
temperature gradients.
Werner Engelmaier
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Date: Wed, 20 Feb 2002 21:51:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
You all can download my Lean manufacturing .ppt presentation from Seth's ftp
site. Ioan, did you get it?
Jit is Lean. Lean simply means eliminating waste. Waste is anything not
adding value to product. Waste is excess inventory, wasted motion, wasted
time, etc. The 5 S's are a good starting point for lean. It is impossible to
have lean unless all players in the supply chain are CONCURRENTLY involved
and working in accordance with specified contract requirements up and down
the supply/food chain.
Kanban is an indicator and is used in lean. Lean is linear and nothing can
be moved unless the Kanban is empty. Lean is based on a pull manufacturing
system dictated by customer demand. Customer demand is based on takt time or
a rythm much like a drum beat. Takt time sets the pace for which product is
manufactured and supplied. When the drum beat is faster so is demand.
Unlike a push system employing a highly wasteful manufacturing methodology,
that constantly clogs the system with high inventory, a pull system has no
waste. It goes on and on but it is a simple concept/methodology when understood.
Kaizen is continuous improvement. A good quality system, like ISO when
properly employed and managed, is designed to seek continuous improvement to
eliminate waste.
And on it goes,
MoonMan
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Date: Thu, 21 Feb 2002 17:03:47 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard van Beveren <[log in to unmask]>
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From: Richard van Beveren <[log in to unmask]>
Subject: Re: Safe processing window
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Hi Werner,
Fair comment - I don't claim to be an expert. Temperature gradient on cool
down is a bit of a mystery to me still - I seem to hear a lot of ideas that
are not really compatible. It seems logical enough that components or most
dissimilar materials are going to struggle to hold together under a
temperature change exceeding 4 C/sec, but then I've heard discussion that a
fast cool down can produce a better solder joint
metallurgically....should've paid more attention in materials engineering
back at uni or at least gone back to Wassink, shouldn't I?
Anyway, what about wave soldering? How do things hold together here? On
both entry and exit temperature gradients are clearly extreme.. Should I be
taking steps to gain control over the cooldown rate as soon as possible
after an assembly leaves the wave and then hold it to something close to 2 /
sec?
Regards,
Richard van Beveren
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, 21 February 2002 14:49
> To: [log in to unmask]
> Subject: Re: [TN] Safe processing window
>
> Hi Richard,
> In a message dated 02/20/2002 19:00:45, [log in to unmask]
> writes:
> >there are probably advantages in dropping off much faster, particularly
> from
> the reflow peak to well
> >under liquidous (maybe as fast as 4 C/sec?).
>
> No, there is no advantage in dropping off much faster, in fact you risk
> fracturing your just formed SJs due to warping because of the thermal
> shock
> temperature gradients.
>
> Werner Engelmaier
>
> --------------------------------------------------------------------------
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Date: Thu, 21 Feb 2002 08:36:09 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Marki Sasportas <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Marki Sasportas <[log in to unmask]>
Subject: 0402 technology
MIME-Version: 1.0
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hello All,
I would like to have recommendations for pad geometry for 0402& 0603
components.
Thanks in advance,
Regards,
Marki Sasportas.
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Date: Wed, 20 Feb 2002 22:49:07 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
My Nguyen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: My Nguyen <[log in to unmask]>
Subject: DFM Checklist for SMT product
X-To: [log in to unmask]
MIME-Version: 1.0
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Good morning Techneters,
I am working on DFM Improvement project. Trying to
create a complete DFM list is my first step. Even
though, each manufacture would have their own DFM due
to their specific process and organization; however,
it would be a great start to learn from your
expertises.
Any advise or guideline or example of DFM checklist
for SMT from you will be greatly appreciated.
Stacy
__________________________________________________
Do You Yahoo!?
Yahoo! Sports - Coverage of the 2002 Olympic Games
http://sports.yahoo.com
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Date: Thu, 21 Feb 2002 03:59:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: [log in to unmask]
Thanks Dan and others for the input and it seems mostly positive. Still, I
question the part first because it is based on the LCCC style. I haven't
tried dissecting a part yet to determine what sits atop the PCB and how the
internal device/chip is attached to it - die attache and wire bond I suppose.
My biggest concerns are the gold and bow and twist of the part and the PCB
to which it is attached. We have another out of control board situation, I
just got into yesterday, and its warpage problem I am now solving
(completely unbalanced MLB construction - what else but an unqualified
supplier). The gold bothers me because I do not know its thickness and
whether it is electroplated.
With regards to gold, if electroplated, are you or anyone else solder
dipping to remove it before attempting assembly. Just don't want
embrittlement some where down the line.
Thanks again,
MoonMan
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Date: Thu, 21 Feb 2002 04:02:10 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Just In Time deliveries
Must look like I'm loosing it again posting to my post. At least I didn't
copy myself.
Forgot to add one of the most important parts of Lean, and its JIT element,
is ensuring you have it working in your organization before every attempting
to impose it on your suppliers.
Glad I got to say that to you all and me,
MoonMan
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Date: Thu, 21 Feb 2002 10:04:09 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: How old is old?
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This is not my field but I have been following this with interest. It might
be interesting if it were possible to ask what train companies do - their
signalling equipment is safety critical, legislated/regulated, long lasting
and therefore subject to much the same strictures as mil stuff in terms of
operational requirements interchangeability and so on.
Kind Regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Thursday, February 21, 2002 1:13 AM
To: [log in to unmask]
Subject: Re: [TN] How old is old?
Guy,
The received wisdom I have from our design and engineering team is that
components stored undisturbed for more than 5 years may (and I stress
'may') have a significantly degraded reliability/functionality.
You talked of instruments having been serviced for 50+ years, and that was
the point I was trying to make - if equipment is in service (being used or
'exercised') on a regular basis, it tends to keep going, but degrade if
just left under 'normal' conditions. Consider a car that is left unused for
any length of time. My experience is that they never quite function
properly straight away if you then try to use it. On the other hand, a car
in regular use and properly maintained can go on for years and years.
Genny's situation is a judgement call, based on experience and risk
assesment. I agree that solderability will be the main issue, and that if
properly stored, 5 years is a conservative estimate of a component's
lifespan. Depends on the application. In my line of military avionics, we
don't like to take too many chances on mission critical equipment, and
component obsolescence/lifetime buys is a major issue with us -
increasingly so as technological changes advance at a seemingly exponential
rate. We're also increasingly having to use industrial grade parts instead
of MIL parts as availability of MIL parts diminishes. Additonal screening
to MIL levels is time consuming and expensive, so we have to minimise risks
in other ways. One of them is to limit the time for which components can be
stored. Regular exercise (power up, stimulation or whatever is appropriate)
helps to keep the parts in shape.
Peter
Guy Ramsey
<gramsey@ACIU To: [log in to unmask]
SA.ORG> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] How old is
old?
<[log in to unmask]
ORG>
02/20/02
09:59 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Guy Ramsey
I was surprised by Peter's response to your post. I wonder what he means by
exercised.
I have work experience with manufactures of electronic instruments that are
serviced for 50+ years (Been in business since just before W.W.II. In the
early seventies they transitioned from analog to digital 27 V NMOS logic
devices. They have components in storage from that time frame. There are
occasional problems with lead frames that have failed (rusted under the
gold) and occasional bad lots of die (didn't test everything before it was
placed in storage). But, mostly, they are able to service and guarantee
their work using solid state devices that were manufactured over 25 years
ago. They use (stored in their own vaults or purchased through brokers)
components that have been out of production for five to ten years; these
would include Crowbar ICs, Switch-mode regulator ICs, Bucket-Brigade ICs,
OP
AMPs, Voltage Regulators and Transistors. I cannot recall getting bad (non
functional) parts but we did have our soldering problems.
Occasionally, there were differences in the performance of components that
required changes to passive component values in some designs. We believed
this was due to variation that was present at the time the components were
made rather than related to changes over time.
Relays or other Electro-mechanical devices are a concern (reed switches,
motors, valves, solenoids). We had problems with them. But it would be hard
to place a shelf life on them, are they hermetically sealed (many were to
allow chemical cleaning)? Most of the problems I experienced were with open
parts. Today many relays are open assuming no-clean processing.
Electrolytic capacitors, carbon resistors are a concern but carbon
resistors
are really a thing of the past. SMT Electrolytic cans, five years would be
a
very conservative limit if you are talking about function.
Solderabiltiy is your main concern Genny.
Guy Ramsey
Senior Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Genny Gibbard
> Sent: Tuesday, February 19, 2002 10:19 AM
> To: [log in to unmask]
> Subject: [TN] How old is old?
>
>
> One of the purchasers has asked if they can purchase some parts
> with a 2000
> date code on them for 'a really great deal!' The part is an 8 lead uSOIC
> package
> At what point do you say they are too old?
> I would appreciate info specific to this package or, just in general,
> guidelines for chip or standard SM components. We do not use
> BGA's yet. We
> aren't trying to do lead free. We generally spec 60/40 HASL finish on
our
> boards.
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
> Product Transition and Support
>
> ------------------------------------------------------------------
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Date: Thu, 21 Feb 2002 04:08:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Knut B=?ISO-8859-1?Q?=E5tstol=F8kken?=
<[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Knut B=?ISO-8859-1?Q?=E5tstol=F8kken?=
<[log in to unmask]>
Subject: Re: ODB++
> Could you pass on information as to who is offering free output software?
CADint deliveres GenCAM 1.5 export free of charge.
www.cadint.com
Knut
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Date: Thu, 21 Feb 2002 06:05:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Antonio Souza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Antonio Souza <[log in to unmask]>
Subject: Importance of good solder joint
Please could someone help me to find a paper about the importance of a good
solder joint!
thanks a lot
Antonio Souza
INPE-Brasil
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Date: Thu, 21 Feb 2002 13:10:34 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Environmental Testing - parallel vs. sequential
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Fellow Technetters,
I'm in the middle of a 'frank and forthright' discussion at the moment on whether it is possible to justify substituting a set of environmental
tests carried out in parallel on a device i.e.. 10 devices go through vibration, another 10 go through high temp operating etc... for a customer
requirement for sequential testing i.e. take 10 devices and put them through all the tests.
I'm of the opinion that even if you up the severity of each parallel test it still isn't the same as a sequential test because you won't catch the
failure mechanisms that results from a combination of effects e.g.. high humidity weakening an adhesive joint which then fails the shock test. You
wouldn't see a failure if you tested 10 devices for high humidity and another 10 for shock.
I'd be interested in some opinions or some literature references which discuss this issue.
Regards,
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Date: Thu, 21 Feb 2002 08:20:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: 0402 technology
X-To: Marki Sasportas <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"
Go to www.toplinedummy.com they have all the specs you need.
Shahed
-----Original Message-----
From: Marki Sasportas [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 1:36 AM
To: [log in to unmask]
Subject: [TN] 0402 technology
hello All,
I would like to have recommendations for pad geometry for 0402& 0603
components.
Thanks in advance,
Regards,
Marki Sasportas.
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Date: Thu, 21 Feb 2002 08:26:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey Earl,
This subject brings back a time of trials and tribulations concerning solder
joint crack propogation using LCCCs and "like" devices. Beginning with the
Coffin-Manson Law and the Engelmaier (Sir Werner's) equation, it was
determined that solder joint volume needed to be increased and the
"acceptable geometry" needed to be modified, almost to point of "the bigger
the blob the better the job". Without getting into too many specifics, the
pad dimensions for these parts require augmentation from the norm by
increasing the pad length that extends outward from the device periphery to
a length equal to the pad length that is under the part. The idea is to
increase the solder joint volume up the castellation and outward to the pad
creating a "bulbous" fillet -- this portion of the joint contributes to 85%
of the solder joint life with respect to crack formation and propogation.
The attained solder joints do go against general Rf rules of thumb (the
shortest path is best) but I was unaware of any performance issues with
applications below 2gHz. As one Rf designer told me years ago, ..."don't
put a stress relief bend on that ribbon, just add more solder..."
Hope this helps, if not, sorry for adding clutter to your cave!
Steve Sauer
Manufacturing Engineer
Northrop Grumman, Xetron
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
I have another board/adventure requiring simple coplanaty issues be resolved
and I know how to do this so don't need advice. Need to know, from R/F
folks, if anyone is using the following:
EM Research Inc. LX-2050-05
EM Research Inc. LX-1450-01
These parts are castellated, are gold plated castellations, are PCB material
interposer types requiring very flat surfaces on which to be mounted. No
problems but for leadless and gold plating. Wondering if anyone out there
has experience with the aforementioned parts and results.
MoonMan
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Date: Thu, 21 Feb 2002 09:15:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Via size
MIME-Version: 1.0
Content-Type: text/plain
Hi technos,
first I want to say to the Moonman "got your lean thing, as well as all the
other documents you put there. Big thanks to you and Seth".
Now, my question to the forum is: what are the rules in determining the
diameter of vias? Has it anything to do with the current or the power? Can a
power supply board, stepping down from 600V to 220V, have 0.018" vias?
I know it sounds trivial, but I'm no EE.
Thanks,
Ioan
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Date: Thu, 21 Feb 2002 08:09:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: [log in to unmask]
Yes Steve,
Those were the days. Still active for some but for constraining or tailoring
core requirements for CTE. Don't have that problem here as after taking one
of the little beasts apart, there's really nothing inside that would
override the CTE matching characteristics both on the part and the MLB.
So, life is good but for getting the gold of the part's solder termination
areas. No problem there either.
Straigtening out the MLB's radically unbalanced construction, based on
impedance requirements, has been a bit more interesting but positive as
well. I have a .5 oz. plane on the bottom of the six layer structure and one
on the 4th layer. The space between layer 1 and layer four has to be 39
mils. So, I made the dielectrics up of 2 plies of 7628, sandwiched between 2
plies of 1080, in each of the two dielectrics. Then I made the layer 4 plane
out of 2 oz. Cu foil. The other dielectrics are all 2 ply 2113. Therefore,
when fabricated in a qualified supplier's carefully managed relamination
process, under specified time, temp, and pressure, with a well managed cool
down cycle, the boards will be flat.
Thanks and how's that for one day's work, or was it two?
Earl
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Date: Thu, 21 Feb 2002 08:29:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McGlaughlin, Jeffrey A" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Stencil Design and Documentation
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
Technetters--
I need some information I hope you can supply:
1) What do I need to supply a stencil manufacturer to get a stencil made?
Will a 1:1 artwork of the pads and an array drawing suffice?
2) How do I document that information? Stencil Drawing? Work sheet? Other?
3) How should I control it so that I meet ISO?
4) Any recommendations on stencil manufacturers?
As always TIA,
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
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Date: Thu, 21 Feb 2002 08:22:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Earl! Never a dull moment in that cave of yours! Sorry, I don't have any
experience with those parts but just an FYI - make sure that your soldering
process is robust enough to avoid having gold embrittlement problems due to
the gold plated castillations. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Earl Moon <[log in to unmask]>@ipc.org> on 02/20/2002 01:59:01 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Earl Moon <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] MILITARY STYLE ALMOST LCCC PARTS
Kind folks,
I have another board/adventure requiring simple coplanaty issues be
resolved
and I know how to do this so don't need advice. Need to know, from R/F
folks, if anyone is using the following:
EM Research Inc. LX-2050-05
EM Research Inc. LX-1450-01
These parts are castellated, are gold plated castellations, are PCB
material
interposer types requiring very flat surfaces on which to be mounted. No
problems but for leadless and gold plating. Wondering if anyone out there
has experience with the aforementioned parts and results.
MoonMan
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Date: Thu, 21 Feb 2002 08:28:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Safe processing window
X-To: [log in to unmask]
MIME-Version: 1.0
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Good Morning Dan! From an assembly point of view your temperatures are
pretty workable for a reflow profile but the ramp rates are somewhat
restrictive. I have seen multiple instances of reflow processes running=
at
ramp up/down rates of 4-6 C/sec with no danger of impacting the compone=
nt
integrity. Is there a material rationale for the 2 C/sec ramp rate
suggestion? As an assembler I am always give preference to components w=
ith
the maximum reflow profile robustness.
Dave Hillman
Rockwell Collins
[log in to unmask]
"Dan R. Johnson" <[log in to unmask]>@ipc.org> on 02/20/2002 03:14:49 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please res=
pond
to "Dan R. Johnson" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Safe processing window
A couple of questions for what has become my best engineering resource.=
Management has asked me to provide a re-flow profile for our product, a=
surface mount component built on FR-4 with lead free solder. I am
reluctant, I would prefer to generate a "safe processing window" type
document. As manufacturing professionals what do you prefer?
The window would spec=A0; max 2=A0 C=A0/sec ramp up, max 60 sec dwell a=
bove 180
C, max 220 C peak, and a 2 C/sec max ramp down. Could you live with thi=
s?
Many thanks for your help,
Dan
=
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Date: Thu, 21 Feb 2002 08:46:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Safe processing window
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Richard! There was a considerable discussion several years back on the
"potential" solder joint thermal cycle reliability life improvement by
attempting to create a given solder joint microstructure. However, a number
of industry presentations/papers (by Werner, Klein Wassink, etc) have
demonstrated (based on metallurgical principles) that it is not possible to
"freeze" the solder joint microstructure for a given use environment - the
solder joint microstructure changes even at room temperature. The industry
focus was shifted from solder joint microstructure to solder joint geometry
and wetting attributes. With the implementation of PbFree solder processes
I am guessing the issue will be reexamined.
Dave Hillman
Rockwell Collins
[log in to unmask]
Richard van Beveren <[log in to unmask]>@ipc.org> on 02/21/2002
12:03:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Richard van Beveren <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Safe processing window
Hi Werner,
Fair comment - I don't claim to be an expert. Temperature gradient on cool
down is a bit of a mystery to me still - I seem to hear a lot of ideas that
are not really compatible. It seems logical enough that components or most
dissimilar materials are going to struggle to hold together under a
temperature change exceeding 4 C/sec, but then I've heard discussion that a
fast cool down can produce a better solder joint
metallurgically....should've paid more attention in materials engineering
back at uni or at least gone back to Wassink, shouldn't I?
Anyway, what about wave soldering? How do things hold together here? On
both entry and exit temperature gradients are clearly extreme.. Should I
be
taking steps to gain control over the cooldown rate as soon as possible
after an assembly leaves the wave and then hold it to something close to 2
/
sec?
Regards,
Richard van Beveren
> Hi Richard,
> In a message dated 02/20/2002 19:00:45, [log in to unmask]
> writes:
> >there are probably advantages in dropping off much faster, particularly
> from
> the reflow peak to well
> >under liquidous (maybe as fast as 4 C/sec?).
>
> No, there is no advantage in dropping off much faster, in fact you risk
> fracturing your just formed SJs due to warping because of the thermal
> shock
> temperature gradients.
>
> Werner Engelmaier
>
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Date: Thu, 21 Feb 2002 08:52:41 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: [log in to unmask]
Thanks for the input Dave,
Our posts probably just crossed paths as I just replied to Steve Sauer
concerning that very thing. I said I was concerned and was going to tin away
the gold before soldering to my warped all to hell board but soon not to be.
Just a note about my cave situation as Werner tried to match me up with a
ground hog. Hog maybe, or a bear, but not of the ground variety. Certainly
more esciting lately outside the cave than in it.
Enjoy,
Earl
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Date: Thu, 21 Feb 2002 10:34:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Just In Time deliveries
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Moonman,
I am not familiar with Seth's ftp site.
Thank you for your insightful comments!
Have a Great Day!
Greg
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Date: Thu, 21 Feb 2002 15:50:18 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Boocock <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Boocock <[log in to unmask]>
Subject: Re: Environmental Testing - parallel vs. sequential
X-To: Eric Christison <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Eric,
You might be interested in this reference for behaviour of BGA solder joints
at high temperature under low frequency vibration.
http://www.packaging.buffalo.edu/paper4.pdf
Regards
John
-----Original Message-----
From: Eric Christison [mailto:[log in to unmask]]
Sent: 21 February 2002 13:11
To: [log in to unmask]
Subject: [TN] Environmental Testing - parallel vs. sequential
Fellow Technetters,
I'm in the middle of a 'frank and forthright' discussion at the moment on
whether it is possible to justify substituting a set of environmental
tests carried out in parallel on a device i.e.. 10 devices go through
vibration, another 10 go through high temp operating etc... for a customer
requirement for sequential testing i.e. take 10 devices and put them through
all the tests.
I'm of the opinion that even if you up the severity of each parallel test it
still isn't the same as a sequential test because you won't catch the
failure mechanisms that results from a combination of effects e.g.. high
humidity weakening an adhesive joint which then fails the shock test. You
wouldn't see a failure if you tested 10 devices for high humidity and
another 10 for shock.
I'd be interested in some opinions or some literature references which
discuss this issue.
Regards,
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Date: Thu, 21 Feb 2002 10:13:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
Gregg,
Go to the following and download the program, pushtopull.ppt, to your ftp site.
No problem. You can use either an FTP client or Internet Explorer to
transfer the files to the site.
using FTP client
----------------
log into ftp.GoodmanAssociates.com with
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Date: Thu, 21 Feb 2002 11:37:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Loveless, Peter" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Loveless, Peter" <[log in to unmask]>
Subject: Micro Lead Frames
Mime-Version: 1.0
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Looking for anyone with experience with MLF's, especially anyone that runs a
0.5mm.
Hoping to hear some do and don'ts.
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Date: Thu, 21 Feb 2002 09:06:10 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Stencil Design and Documentation
X-To: "McGlaughlin, Jeffrey A" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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1). Most stencil manufacturers can produce a stencil with a tolerance of
less than 0.5mil, but only if you work from electronic data. So if tolerance
is important, don't send a film and a sketch to a stencil manufacturer ---
send them an electronic file (Gerber 274X is the preferred format, other
formats can be used) showing the apertures you want. You can send a separate
electronic drawing file of the step-and-repeat data, etc. If you do send a
film and sketches, be prepared for some loss in accuracy.
2). Most stencil manufacturers (including A-Laser, ooooops no plugs.) have a
website where you can find an order form which includes almost all the
questions they may want to ask you.
3). That depends mostly on YOUR ISO document. What does it say you need to
do? If it says that you have to verify that your supplier can supply you
with good stencils, go try out the supplier.
4). Ehhh, may be I should pass on this one, but I can give you some
suggestions by phone.
Regards,
Ahne Oosterhof,
A-Laser, Inc.
503-641-9428
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of McGlaughlin, Jeffrey A
Sent: Thursday, February 21, 2002 05:30
To: [log in to unmask]
Subject: [TN] Stencil Design and Documentation
Technetters--
I need some information I hope you can supply:
1) What do I need to supply a stencil manufacturer to get a stencil made?
Will a 1:1 artwork of the pads and an array drawing suffice?
2) How do I document that information? Stencil Drawing? Work sheet? Other?
3) How should I control it so that I meet ISO?
4) Any recommendations on stencil manufacturers?
As always TIA,
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
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Date: Thu, 21 Feb 2002 09:06:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: Re: Solder
X-To: Antonio Souza <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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Primary advantage is that there will be no silver leaching from the plating
on components which are susceptible.
Secondary advantage is the softening of the melt point which can help with
tombstoning of 0402 and maybe even 0201 capacitors.
Primary disadvantage is the increased cost due to the silver content. 2%,
and 0.5% are two commonly seen percentages in the alloys out there in
production.
At 07:59 AM 2/19/02 -0600, Antonio Souza wrote:
>Please
>
>Could someone tell me the advantages and disadvantages of using solder
>Sn/Pb/Ag instead of Sn/Pb.
>
>
>Thanks
>
>Antonio
>Inpe-Brazil
>
>---------------------------------------------------------------------------------
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Date: Thu, 21 Feb 2002 09:08:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: Dendritic growth or what?
Mime-Version: 1.0
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I was asked to comment on the condition shown on the attached photos. What
is your opinion?
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Date: Thu, 21 Feb 2002 11:02:49 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Paul Brionez <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Brionez <[log in to unmask]>
Subject: Reference Designations
MIME-Version: 1.0
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--------------EAF7DA2C07CC14B5B5989F9D
Content-Type: text/plain; charset=us-ascii
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To All
I have a question about what is used as a reference designator for a
mechanical part that is added to the PCB during the assembly process and
is not a post soldering process. This part is a mechanical part that is
soldered to the PCB as a keying feature. Similar to a 7343 part. What do
you use to denote this type of part?
Any input would be appreciated.
Thanks in Advance
Paul Brionez
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and confidential and protected from disclosure. If the
reader of this message is not the intended recipient, or an
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the intended recipient, you are hereby notified that any
reproduction, dissemination or distribution of this
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this communication in error, please notify us immediately by
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Date: Thu, 21 Feb 2002 09:12:55 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Looking for Estimated price difference between 2 & 4 layers
(Roger's)
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PCB Expert,
What will be the price difference (in %) between 2 layer boards and 4
layer boards using Roger's material? Both are impedance control boards.
4 layers board is 62 thick while 2 layers board is 25 mil thick. The
size of the board is 3"X5" for both layer counts.
I know it will be a volume specific so let's assume 100, 500 & 1000
re,
ken patel
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Date: Thu, 21 Feb 2002 09:12:39 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: stripping insulation from polyu-nylon coated magnet wire
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Anyone have a reliable safe method of removing the polyurethane and nylon
coating that protects magnet wire so that the wire can be used to solder as
a jumper wire. I remember using a hot chemical salt type stripping bath
many years ago but was hoping that someone has found a better way to do
this since then.
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Date: Thu, 21 Feb 2002 12:27:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Re: Stencil Design and Documentation
X-To: [log in to unmask]
Mime-Version: 1.0
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The sample order form included with the following document (developed by a =
committee that included most major stencil suppliers) would help you a =
lot.
IPC-7525 Stencil Design Guidelines
This document provides guidelines for the design and fabrication of =
stencils for solder paste and surface-mount adhesive. This is the first =
industry consensus document for stencil design. Stencil design for =
surface-mount technology, as well as mixed technology with through-hole or =
flip chip components is discussed, including overprint, two-print and step =
stencil designs. A sample order form and a user inspection checklist are =
also included for stencil design. 14 pages. Released May 2000.=20
Jeffrey will receive an attachment with the 7525 Table of Contents and =
scope/purpose/background info for the guide. Others receiving this reply =
from TechNet won't get the attachment but can get it from this link: =
http://www.ipc.org/TOC/IPC-7525.pdf
Jack
>>> [log in to unmask] 02/21/02 07:29AM >>>
Technetters--
I need some information I hope you can supply:
1) What do I need to supply a stencil manufacturer to get a stencil made?
Will a 1:1 artwork of the pads and an array drawing suffice?
2) How do I document that information? Stencil Drawing? Work sheet? Other?
3) How should I control it so that I meet ISO?
4) Any recommendations on stencil manufacturers?
As always TIA,
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
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Date: Thu, 21 Feb 2002 13:45:15 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic growth or what?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_a0.2275cc71.29a69a3b_boundary"
--part1_a0.2275cc71.29a69a3b_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 2/21/02 11:13:57 AM Central Standard Time,
[log in to unmask] writes:
> I was asked to comment on the condition shown on the attached photos. What
> is your opinion?
>
Phil,
The server stripped the attachments...I can post them on my web page if you
want. You'll need to send the pictures directly to me...
-Steve Gregory-
--part1_a0.2275cc71.29a69a3b_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 2/21/02 11:13:57 AM Central Standard Time, [log in to unmask] writes:
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I was asked to comment on the condition shown on the attached photos. What
<BR>is your opinion?
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>Phil,
<BR>
<BR>The server stripped the attachments...I can post them on my web page if you want. You'll need to send the pictures directly to me...
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_a0.2275cc71.29a69a3b_boundary--
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Date: Thu, 21 Feb 2002 10:48:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Reference Designations
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
i'll take a run at this. we don't use a reference designator for purely mechanical parts. they are identified on drawings with a 'find no.' (ie a reference to a parts list). reference designators are associated with schematics, among a lot of other things. they are put on assemblies to assist electronic types in troubleshooting assemblies. mechanical parts are not all that important to them.
a caveat for my response is that i don't consider connectors to be a mechanical part. if you do, then go to an ansi document and look up the reference designator for them (eg j1-e).
so, this is a long way to say that i've never seen reference designators assigned to mechanical parts. of course that doesn't mean they aren't.
phil
-----Original Message-----
From: Paul Brionez [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 9:03 AM
To: [log in to unmask]
Subject: [TN] Reference Designations
To All
I have a question about what is used as a reference designator for a
mechanical part that is added to the PCB during the assembly process and
is not a post soldering process. This part is a mechanical part that is
soldered to the PCB as a keying feature. Similar to a 7343 part. What do
you use to denote this type of part?
Any input would be appreciated.
Thanks in Advance
Paul Brionez
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Date: Thu, 21 Feb 2002 11:01:17 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
X-To: "Sauer, Steven T." <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
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Steve,
I would like to hear the pad layout specifics since I have an assignment to
generate recommended PCB layouts for all of our package styles. We plan to
publish them on our web site so I would really like the most technically
accurate design possible.
Thanks,
Dan
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Date: Thu, 21 Feb 2002 18:56:32 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Dendritic growth or what?
X-To: phil bavaro <[log in to unmask]>
In-Reply-To: <[log in to unmask] >
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Phil
If I could see 'em I and others would. TechNet can't take attachments for
obvious reasons.
Can you send to me directly and maybe Steve Gregory could post onto his web
site for all to see and comment - through the TechNet of course!
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of phil bavaro
> Sent: 21 February 2002 17:09
> To: [log in to unmask]
> Subject: [TN] Dendritic growth or what?
>
>
> I was asked to comment on the condition shown on the attached
> photos. What
> is your opinion?
>
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Date: Thu, 21 Feb 2002 10:59:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject: Re: Reference Designations
X-To: Paul Brionez <[log in to unmask]>
MIME-Version: 1.0
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Paul,
MP--Mechanical part mounted
This from an old Electronic drafting text book. Author Beakly and Autore and
Alf
I think it can be what ever you want, some thing like; for example KEY1
Greg Scott
Cray Inc
Paul Brionez wrote:
> To All
>
> I have a question about what is used as a reference designator for a
> mechanical part that is added to the PCB during the assembly process and
>
> is not a post soldering process. This part is a mechanical part that is
> soldered to the PCB as a keying feature. Similar to a 7343 part. What do
>
> you use to denote this type of part?
> Any input would be appreciated.
>
> Thanks in Advance
>
> Paul Brionez
>
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Date: Thu, 21 Feb 2002 14:32:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Reference Designations
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I second the thought.
Phil Nutting
-----Original Message-----
From: Crepeau, Phil [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 1:49 PM
To: [log in to unmask]
Subject: Re: [TN] Reference Designations
hi,
i'll take a run at this. we don't use a reference designator for purely =
mechanical parts. they are identified on drawings with a 'find no.' =
(ie a reference to a parts list). reference designators are associated =
with schematics, among a lot of other things. they are put on =
assemblies to assist electronic types in troubleshooting assemblies. =
mechanical parts are not all that important to them.
a caveat for my response is that i don't consider connectors to be a =
mechanical part. if you do, then go to an ansi document and look up the =
reference designator for them (eg j1-e).
so, this is a long way to say that i've never seen reference =
designators assigned to mechanical parts. of course that doesn't mean =
they aren't.
phil
-----Original Message-----
From: Paul Brionez [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 9:03 AM
To: [log in to unmask]
Subject: [TN] Reference Designations
To All
I have a question about what is used as a reference designator for a
mechanical part that is added to the PCB during the assembly process and
is not a post soldering process. This part is a mechanical part that is
soldered to the PCB as a keying feature. Similar to a 7343 part. What do
you use to denote this type of part?
Any input would be appreciated.
Thanks in Advance
Paul Brionez
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Date: Thu, 21 Feb 2002 15:16:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Blomberg, Rainer (FL51)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Blomberg, Rainer (FL51)" <[log in to unmask]>
Subject: Re: stripping insulation from polyu-nylon coated magnet wire
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Twin-Cone, fine wire abrasive stripping is done routinely on our magnet wire
which has a thin film of insulation. It may work on yours as well.
Check out http://www.series4.co.uk/prodeqpt/section14/section14.htm
> Rainer G. Blomberg
> Honeywell -Space Systems Clearwater
> Staff Production Engineer
(727) 539-5534
-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 12:13 PM
To: [log in to unmask]
Subject: [TN] stripping insulation from polyu-nylon coated magnet wire
Anyone have a reliable safe method of removing the polyurethane and nylon
coating that protects magnet wire so that the wire can be used to solder as
a jumper wire. I remember using a hot chemical salt type stripping bath
many years ago but was hoping that someone has found a better way to do
this since then.
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Date: Thu, 21 Feb 2002 15:23:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: stripping insulation from polyu-nylon coated magnet wire
X-To: phil bavaro <[log in to unmask]>
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Phil,
The simplest method is to dip the wire in a solder pot (~500=B0F, =
260=B0C).
This removes the coating and tins the wire at the same time. Most=20
polyurethanes and nylon coatings are in thermal classes of 105=B0C, =
130=B0C,
155=B0C and 180=B0C which should be removable while immersed in molten =
solder.
The dwell time will be significantly longer than what is used to tin
temperature sensitive components.
Another method is thermal strippers.
The least favorite and hardest to control is abrasion using an exacto =
knife.
Steve Sauer
Manufacturing Engineer
Northrop Grumman, Xetron
-----Original Message-----
Anyone have a reliable safe method of removing the polyurethane and =
nylon
coating that protects magnet wire so that the wire can be used to =
solder as
a jumper wire. I remember using a hot chemical salt type stripping =
bath
many years ago but was hoping that someone has found a better way to do
this since then.
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Date: Thu, 21 Feb 2002 13:36:27 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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It is not so much that "Just In Time" gives you all these wonderful
benefits, but if you implement JIT without dedication, functionality,
management backing, strong focus, DFM/CE orientation, using rules and
keeping track of quality you will GENERATE an awful lot of waste in machine
and people time, sitting and waiting for usable parts to show up.
In JIT you only should now be receiving the parts you now need, no spares,
no parts for next week --- so if there is a problem with the parts you are
down. Therefore everybody (hopefully) has a very good reason to do it right
the first time.
Have fun,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Earl Moon
Sent: Wednesday, February 20, 2002 11:54
To: [log in to unmask]
Subject: Re: [TN] Just In Time deliveries
Just in time is Lean is pull is a dedicated, functional, management backed,
focused, DFM/CE oriented, waste eliminated, rule based, quality system.
Can't go on here,
MoonMan
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Date: Thu, 21 Feb 2002 15:37:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: Ahne Oosterhof <[log in to unmask]>
Ahne,
You obviously didn't need to see/hear this but OUTSTANDING!
MoonMan
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Date: Thu, 21 Feb 2002 13:48:04 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: Reference Designations
X-To: Paul Brionez <[log in to unmask]>
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Paul,
For what its worth I have seen certain mechanical part with ref deg's. Most
notably HS for heat sinks, critical if not installed. These were usually
noted on the schematic and appeared on the silk screen. I have also seen ref
degs on silk screens when stand offs of different lengths were installed on
the same PCB. I think what I'm getting at is standards are fine but we do
what we have to get repeatability out of our process.
Dan
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Date: Thu, 21 Feb 2002 22:55:23 +0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Roger Hammond <[log in to unmask]>
Subject: Flipfet devices
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Hello Technetters,
We have been asked to produce circuit boards with solder resist defined
pads for flipfet devices. The pads are 10 mil in diameter and are
finished with electroless nickel gold. No solder resist thickness has
been specified. We are told that ultimately 5 mil pads will be called
for. My gut feeling is that it will be difficult to solder to the pads
due to the solder being unable to deform round the solder resist into
the hole.
My questions are: -
Are my concerns justified?
Is it usual to have soplder resist defined pads this small?
What solder resist thickness should be specified?
Would an alternative finish be appropriate?
Thanks in advance
Roger Hammond.
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Date: Thu, 21 Feb 2002 19:23:54 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flipfet devices
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Roger,
In a word; yes. Your concerns are justified. Here's a good *.PDF file that
addresses the assembly of Flipfet devices, it's at:
http://www.eetasia.com/ART_8800066987_499505,499512.HTM
Soldermask defined pads are less reliable than non-soldermask defined pads,
and using ENIG finish, gold embrittlement could be a concern with solder
joints that small...
-Steve Gregory-
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Date: Fri, 22 Feb 2002 11:23:54 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Subject: Defects terminology
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Good day,
Did you come across with these defect terms - Manhattan and
Billboard ? If yes do you know what is the meaning?
I assume that Manhattan means either a lot of tombstoned parts on
PCB , right up.
Billboard?
Please can you explain the meaning ?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
> --------------------------------------------------------------------------
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Date: Thu, 21 Feb 2002 19:42:43 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: MILITARY STYLE ALMOST LCCC PARTS
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Hi Steve,
In a message dated 02/21/2002 9:30:10, [log in to unmask] writes:
>Beginning with the Coffin-Manson Law and the Engelmaier (Sir Werner's)
equation, it was
>determined that solder joint volume needed to be increased and the
>"acceptable geometry" needed to be modified, almost to point of "the bigger
>the blob the better the job".
Well, neither Coffin-Manson Law and the Engelmaier (Sir Werner's) equation
would suggest more solder joint volume, only taller solder joints.
>The idea is to increase the solder joint volume up the castellation and
outward to the pad
>creating a "bulbous" fillet -- this portion of the joint contributes to 85%
of the solder joint life with >respect to crack formation and propogation.
This "bulbous" SJ idea did not work very well, as the results provided by
Martin-Marietta during the Industry Days of this Air force clearly showed. In
order to bring any improvement at all, it was necessary that all four sides
of the LLCCCs had identical SJs in terms of their geometry--something that
proved hard to do.
Werner Engelmaier
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Date: Thu, 21 Feb 2002 19:42:42 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Environmental Testing - parallel vs. sequential
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Hi Eric,
You are right. Parallel and sequential testing will likely produce different
results...BUT there are big problems. They are primarily related to how the
results can be extrapolated to product reliability.
For instance, you will get dramatically different results if you first
T-cycle solder joints and than vibration load them or the other way around.
So, you really need to think carefully about what it is you REALLY are trying
to accomplish.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Thu, 21 Feb 2002 18:05:28 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Environmental Testing - parallel vs. sequential
X-To: Eric Christison <[log in to unmask]>
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Erik,
To even consider this requires throwing common sense out the window!
Do not try to save money or time no matter what it costs.
Just my opinion>
David A. Douthit
Manager
LoCan LLC
Eric Christison wrote:
> Fellow Technetters,
>
> I'm in the middle of a 'frank and forthright' discussion at the moment on whether it is possible to justify substituting a set of environmental
> tests carried out in parallel on a device i.e.. 10 devices go through vibration, another 10 go through high temp operating etc... for a customer
> requirement for sequential testing i.e. take 10 devices and put them through all the tests.
>
> I'm of the opinion that even if you up the severity of each parallel test it still isn't the same as a sequential test because you won't catch the
> failure mechanisms that results from a combination of effects e.g.. high humidity weakening an adhesive joint which then fails the shock test. You
> wouldn't see a failure if you tested 10 devices for high humidity and another 10 for shock.
>
> I'd be interested in some opinions or some literature references which discuss this issue.
>
> Regards,
>
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Date: Thu, 21 Feb 2002 20:06:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Environmental Testing - parallel vs. sequential
X-To: Eric Christison <[log in to unmask]>
MIME-Version: 1.0
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My prod floor used to HALT specific models (scrap) without warning, to
confirm process. Repeating material/process related quality, off the line
occasionally, makes sense.
Doing full/combined test on fewer numbers is more effective.
RL
----- Original Message -----
From: Eric Christison <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, February 21, 2002 8:10 AM
Subject: [TN] Environmental Testing - parallel vs. sequential
> Fellow Technetters,
>
> I'm in the middle of a 'frank and forthright' discussion at the moment on
whether it is possible to justify substituting a set of environmental
> tests carried out in parallel on a device i.e.. 10 devices go through
vibration, another 10 go through high temp operating etc... for a customer
> requirement for sequential testing i.e. take 10 devices and put them
through all the tests.
>
> I'm of the opinion that even if you up the severity of each parallel test
it still isn't the same as a sequential test because you won't catch the
> failure mechanisms that results from a combination of effects e.g.. high
humidity weakening an adhesive joint which then fails the shock test. You
> wouldn't see a failure if you tested 10 devices for high humidity and
another 10 for shock.
>
> I'd be interested in some opinions or some literature references which
discuss this issue.
>
> Regards,
>
> --------------------------------------------------------------------------
-------
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Date: Thu, 21 Feb 2002 20:46:36 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Defects terminology
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_196.2a81a94.29a6fcfc_boundary"
--part1_196.2a81a94.29a6fcfc_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Vit!
I've never heard the term "Manhattan", but I think it is the same as a
"Drawbridge" which means that the part (normally passives) aren't quite
"Tombstoned" but have lifted one termination enough to cause a open solder
connection.
"Billboards" are passive components that have been placed on edge, resembling
a Billboard, instead of laying flat on the pads, the component is on edge,
90-degrees from what is supposed to be...that is rooted in the placement
process.
-Steve Gregory-
> Good day,
>
> Did you come across with these defect terms - Manhattan and
> Billboard ? If yes do you know what is the meaning?
>
> I assume that Manhattan means either a lot of tombstoned parts on
> PCB , right up.
>
> Billboard?
>
> Please can you explain the meaning ?
>
> Thank you
>
> Regards
>
> Vit Sklenar MGE4VS
> T: (61 3)9541 7734 F: (61 3) 9541 3909
> e-mail work: [log in to unmask]
> e-mail home: [log in to unmask]
> > Robert Bosch (Aust) ,
> 1555 cnr.Centre and McNaugton Road,
> > Clayton , VIC 3169, Australia
> >
> >
>
--part1_196.2a81a94.29a6fcfc_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Vit!<BR>
<BR>
I've never heard the term "Manhattan", but I think it is the same as a "Drawbridge" which means that the part (normally passives) aren't quite "Tombstoned" but have lifted one termination enough to cause a open solder connection.<BR>
<BR>
"Billboards" are passive components that have been placed on edge, resembling a Billboard, instead of laying flat on the pads, the component is on edge, 90-degrees from what is supposed to be...that is rooted in the placement process. <BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Good day,<BR>
<BR>
Did you come across with these defect terms - Manhattan and<BR>
Billboard ? If yes do you know what is the meaning?<BR>
<BR>
I assume that Manhattan means either a lot of tombstoned parts on<BR>
PCB , right up.<BR>
<BR>
Billboard?<BR>
<BR>
Please can you explain the meaning ?<BR>
<BR>
Thank you<BR>
<BR>
Regards<BR>
<BR>
Vit Sklenar MGE4VS<BR>
T: (61 3)9541 7734 F: (61 3) 9541 3909<BR>
e-mail work: [log in to unmask]<BR>
e-mail home: [log in to unmask]<BR>
> Robert Bosch (Aust) ,<BR>
1555 cnr.Centre and McNaugton Road,<BR>
> Clayton , VIC 3169, Australia<BR>
><BR>
><BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Thu, 21 Feb 2002 19:50:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Neda Thrash <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neda Thrash <[log in to unmask]>
Subject: Re: Defects terminology
Mime-Version: 1.0
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Billboard, I believe, means a chip component standing on it's side. =
Manhattan? Beats me!
>>> [log in to unmask] 02/21/02 06:23PM >>>
Good day,
Did you come across with these defect terms - Manhattan and
Billboard ? If yes do you know what is the meaning?
I assume that Manhattan means either a lot of tombstoned parts on
PCB , right up.
Billboard?
Please can you explain the meaning ?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]=20
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
> -------------------------------------------------------------------------=
-
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Date: Thu, 21 Feb 2002 21:23:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Leland Woodall <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leland Woodall <[log in to unmask]>
Subject: Re: Defects terminology
X-To: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
MIME-Version: 1.0
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Vit,
I'm unsure about a Manhattan, but a billboarded part is typically an SMT
chip component that is soldered to both pads, yet its orientation is
vertical rather than horizontal.
Hope this helps...
Leland Woodall
Quality Coordinator
Keihin Carolina System Technology, Inc.
4047 McNair Road
Tarboro, NC 27886
Phone: (252) 641-6750, ext. 2865
Email: [log in to unmask]
-----Original Message-----
From: Sklenar Vit (RBAU-EB/MGE4) [mailto:[log in to unmask]]
Sent: Thursday, February 21, 2002 7:24 PM
To: [log in to unmask]
Subject: [TN] Defects terminology
Good day,
Did you come across with these defect terms - Manhattan and
Billboard ? If yes do you know what is the meaning?
I assume that Manhattan means either a lot of tombstoned parts on
PCB , right up.
Billboard?
Please can you explain the meaning ?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
> --------------------------------------------------------------------------
> -------
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Date: Fri, 22 Feb 2002 10:22:27 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Environmental Testing - parallel vs. sequential
X-To: Eric Christison <[log in to unmask]>
MIME-Version: 1.0
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Eric,
Opinion: I'm with you in that each part must go through all the tests for
the very reasons you mention. In operation, the parts will be meeting (or
should be meeting, if the tests have been chosen correctly), ALL the
conditions you are qualifying your product to, not just one or some.
Since your customer is requiring sequential testing, that is what you have
to provide or you fail to meet their requirements. What you get then is an
unhappy customer and a lot of wasted time conducting the wrong type of
testing. I can understand your opposition's desire to conduct parallel
testing - 1) it greatly reduces the development time and 2) you stand a
greater chance of passing individual tests, which always looks good on
paper, but when you start getting a load of field failures, how good will
it look then in practice?
I can't offer any literature references on the subject, but I would have
thought common sense and a sense of the company's reputation (damage
thereto) would prevail, even with the most ardent cost-cutter. If you trash
your reputation by not following customer requiremetns and not properly
qualifying your product, how much business do you hope to secure in the
future? ["You" does not mean you personally, of course.]
Good luck with the fight.
Peter
Eric
Christison To: [log in to unmask]
<eric.christis cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
[log in to unmask]> Aero/ST Group)
Sent by: Subject: [TN] Environmental Testing - parallel
TechNet vs. sequential
<[log in to unmask]
RG>
02/21/02 09:10
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Eric
Christison
Fellow Technetters,
I'm in the middle of a 'frank and forthright' discussion at the moment on
whether it is possible to justify substituting a set of environmental
tests carried out in parallel on a device i.e.. 10 devices go through
vibration, another 10 go through high temp operating etc... for a customer
requirement for sequential testing i.e. take 10 devices and put them
through all the tests.
I'm of the opinion that even if you up the severity of each parallel test
it still isn't the same as a sequential test because you won't catch the
failure mechanisms that results from a combination of effects e.g.. high
humidity weakening an adhesive joint which then fails the shock test. You
wouldn't see a failure if you tested 10 devices for high humidity and
another 10 for shock.
I'd be interested in some opinions or some literature references which
discuss this issue.
Regards,
---------------------------------------------------------------------------------
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Date: Fri, 22 Feb 2002 10:56:59 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Via size
X-To: "Tempea, Ioan" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Ioan,
I'm no EE, either - just a confirmed ME, but from the experience I've had,
via hole diameter is dependant on 3 things: 1) current-carrying needs, 2)
board thickness and 3) plating thickness.
1) If you know the power that the via hole has to carry, you can determine
the cross-sectional area of the copper plating you need in the hole.
2) Adequate plating inside a hole depends partly on the plating process
capability of your fab house and partly on the hole's aspect ratio
(diameter to depth). Ask your fab house what their minimum hole diameter
and aspect ratio is for achieving even plating thickness down the hole.
From the thickness of your board, you can then determine whether you can
use the minimum hole diameter as a baseline or diameter based on aspect
ratio as a baseline.
3) Once you also know from your fab house the minimum hole plating
thickness they can achieve, you have all the information you need to
determine your finished hole sizes. Knowing the plating thickness and the
X-sectional area of copper you need, you can simply calculate the length of
copper required, which, of course will be the same as finished
circumference of your finished hole. Divide it by Pi and you have the
diameter. Obviously if your calculations come up with a hole diameter
smaller than you fab house's minimum or, likewise, too large an aspect
ratio, increasing the hole diameter won't do any harm - it only adds a
margin of safety (which you should do yourself in any case).
There is no maximum plating thickness, but bear in mind that you often get
thicker plating on the board outer surfaces than you get in the holes. You
don't want it to get too thick, or you run into over-etching problems,
uneven coverage, etc., etc. You're safe enough with assuming a 1/2 oz (0.7
mils) min hole plating thickness for your calculations.
Conversely, for the future, you can work out that if the current carrying
requirements of a via are less than a certain value, you don't need to
calculate hole diameters, since your fab house's minimum size will cope
with it.
Peter
"Tempea, Ioan"
<itempea@POSIT To: [log in to unmask]
RON.QC.CA> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Via size
<[log in to unmask]
RG>
02/21/02 10:15
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to "Tempea,
Ioan"
Hi technos,
first I want to say to the Moonman "got your lean thing, as well as all the
other documents you put there. Big thanks to you and Seth".
Now, my question to the forum is: what are the rules in determining the
diameter of vias? Has it anything to do with the current or the power? Can
a
power supply board, stepping down from 600V to 220V, have 0.018" vias?
I know it sounds trivial, but I'm no EE.
Thanks,
Ioan
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Date: Fri, 22 Feb 2002 11:15:56 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Stencil Design and Documentation
X-To: "McGlaughlin, Jeffrey A" <[log in to unmask]>
MIME-Version: 1.0
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Stencil data is output as part of the Gerber data that defines the PCB
itself. You will additionally need to specify the stencil thickness (or
thicknesses if you need a stepped stencil), whether you want it made by
etching or laser cutting, what side angles you want on the apertures as a
lead in to minimise solder paste sticking in the stencil, and maybe a
stencil number and revision to be etched onto its surface.
To control it, you add a note to your assembly drawing to state the stencil
number and revision to be used to screen paste onto the board.
Supplying an artwork won't do, as it's imprecise as far as accurate data is
concerned (subject to physical damage, expansion/contraction, etc) and
it's non-modifiable without a replacement artwork. Gerber data is what's
required.
Can't recommend a stencil manufacturer that's useful to you, as I'm in
Singapore. While we have quite a good one that our CM uses, it's maybe a
bit far away for you.
Peter
"McGlaughlin,
Jeffrey A" To: [log in to unmask]
<McGlaughlin@BAT cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TELLE.ORG> Aero/ST Group)
Sent by: TechNet Subject: [TN] Stencil Design and Documentation
<[log in to unmask]
>
02/21/02 09:29
PM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to "McGlaughlin,
Jeffrey A"
Technetters--
I need some information I hope you can supply:
1) What do I need to supply a stencil manufacturer to get a stencil made?
Will a 1:1 artwork of the pads and an array drawing suffice?
2) How do I document that information? Stencil Drawing? Work sheet? Other?
3) How should I control it so that I meet ISO?
4) Any recommendations on stencil manufacturers?
As always TIA,
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
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Date: Thu, 21 Feb 2002 22:07:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Flipfet devices
X-To: [log in to unmask]
Solder mask defined pads are good only for one thing. They hold the pad on
the board. Otherwise, they get in the way.
MoonMan
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Date: Fri, 22 Feb 2002 08:53:59 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Defects terminology
X-To: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
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Manhattan is an alternative term for multiple tombstoning. A load of
tombstoned Rs and Cs looks like Manhattan (before 11 September).
Brian
"Sklenar Vit (RBAU-EB/MGE4)" wrote:
>
> Good day,
>
> Did you come across with these defect terms - Manhattan and
> Billboard ? If yes do you know what is the meaning?
>
> I assume that Manhattan means either a lot of tombstoned parts on
> PCB , right up.
>
> Billboard?
>
> Please can you explain the meaning ?
>
> Thank you
>
> Regards
>
> Vit Sklenar MGE4VS
> T: (61 3)9541 7734 F: (61 3) 9541 3909
> e-mail work: [log in to unmask]
> e-mail home: [log in to unmask]
> > Robert Bosch (Aust) ,
> 1555 cnr.Centre and McNaugton Road,
> > Clayton , VIC 3169, Australia
> >
> >
> > -----Original Message-----
> > From: Earl Moon [SMTP:[log in to unmask]]
> > Sent: Tuesday, February 05, 2002 7:53 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Proving the reliability of a solder joint
> >
> > My company just got a copy on CD. Werner is the chair for the committee.
> > Who
> > else indeed? Other names read like a who's who or Hall Of Fame.
> >
> > Can't wait to get into this little baby!
> >
> > MoonCaveMan
> >
> > --------------------------------------------------------------------------
> > -------
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> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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Date: Fri, 22 Feb 2002 02:11:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ivanoe Pedruzzi <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivanoe Pedruzzi <[log in to unmask]>
Subject: Re: Defects terminology
X-To: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
MIME-Version: 1.0
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No doubt,
Manhattan has the same meaning as tombstone. As I had lots of them I had to
learn that terminology.
Ivan Pedruzzi
Manufacturing Engineering
Jabil Circuit Italy
-----Original Message-----
From: Sklenar Vit (RBAU-EB/MGE4) [mailto:[log in to unmask]]
Sent: Friday, February 22, 2002 1:24 AM
To: [log in to unmask]
Subject: [TN] Defects terminology
Good day,
Did you come across with these defect terms - Manhattan and
Billboard ? If yes do you know what is the meaning?
I assume that Manhattan means either a lot of tombstoned parts on
PCB , right up.
Billboard?
Please can you explain the meaning ?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date: Fri, 22 Feb 2002 09:22:08 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: stripping insulation from polyu-nylon coated magnet wire
X-To: "Sauer, Steven T." <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Beat me to it! If you do a lot of this or the wire is very thin, you may
want to look at a lower tin content solder, also put some good extraction
over the pot.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Sauer, Steven T.
Sent: Thursday, February 21, 2002 8:23 PM
To: [log in to unmask]
Subject: Re: [TN] stripping insulation from polyu-nylon coated magnet
wire
Phil,
The simplest method is to dip the wire in a solder pot (~500°F, 260°C).
This removes the coating and tins the wire at the same time. Most
polyurethanes and nylon coatings are in thermal classes of 105°C, 130°C,
155°C and 180°C which should be removable while immersed in molten solder.
The dwell time will be significantly longer than what is used to tin
temperature sensitive components.
Another method is thermal strippers.
The least favorite and hardest to control is abrasion using an exacto knife.
Steve Sauer
Manufacturing Engineer
Northrop Grumman, Xetron
-----Original Message-----
Anyone have a reliable safe method of removing the polyurethane and nylon
coating that protects magnet wire so that the wire can be used to solder as
a jumper wire. I remember using a hot chemical salt type stripping bath
many years ago but was hoping that someone has found a better way to do
this since then.
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Date: Fri, 22 Feb 2002 10:49:02 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Environmental Testing - parallel vs. sequential
Mime-Version: 1.0
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Eric
Just as a basic thought: It is not the goal of a test to be as severe as =
possible but to proof that a product/process meets the requirements. To do =
so, the tests performed have to be chosen carefully and designed to show =
any week points but not to wreck the specimen on any account.
Now, you talk about different philosophies and different goals:
- Parallel testing:=20
The idea of sequential testing is to find the answer of a specimen on a =
particular stress. There is no sense in starting combined tests is one =
doesn't know how an item to be tested reacts if it is exposed to let's say =
high temperature.
- Sequential testing:=20
As I get it, you want to evaluate the effects of combined environmental =
stress on a specimen by exposing the specimen to the stresses one after =
the other. See, as soon as you get into combined testing the whole thing =
gets quite complex. Your thought is right, if the stresses do occur one =
after the other. One example is the degradation of roads due to frost. =
Firstly water penetrates into small cavities of the surface. When freezing =
the water expands breaking pieces out of the road. However, if the =
combined stress occurs simultaneously the attempt to simulate their =
combined effect by sequential testing seems fruitless to me. Just as an =
example for this thought we can take diffusion. As you know, diffusion =
through a membrane is driven by the temperature and by the difference of =
the concentration of a certain substance on both sides of the membrane. =
High temperature accelerates diffusion and so does a large difference in =
concentration. According to your thought one could theoretically perform a =
test where a specimen is firstly exposed to an environment with high =
temperature and a low difference in concentration dC ( or even worse not =
caring for the dC) and then making a test with the same specimen where it =
is exposed to a high dC with low Temperature (or similarly to above not =
caring for the temperature). As you see clearly, this test is absolutely =
meaningless when it comes to find the effect of the combination of temp. =
and dC. If you want to find that you have to run tests where the dC and =
the high temperature occur together.
I think I mentioned this earlier. Designing sensible tests is a difficult =
business and requires a lot of knowledge of physics of failure and =
incorporates some math. To learn about the mathematical part read =
Montgomerys "Design and Analysis of Experiments". For the physics of =
failure part I am afraid you have to go through some literature dealing =
with physics, failure analysis and material science.
Have a great day=20
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Fri, 8 Feb 2002 16:01:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB Cross-sectional analysis service
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_17d.3449ea5.299596a9_boundary"
--part1_17d.3449ea5.299596a9_boundary
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I recommend using Microtek. They provide very good reports.
Microtek Laboratories
1435 Allec St.
Anaheim, CA 92805
(714) 999-1616
www.thetestlab.com
Susan Allen
HAM Technology
--part1_17d.3449ea5.299596a9_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">I recommend using Microtek. They provide very good reports.
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0"><B>Microtek Laboratories</B>
<BR>1435 Allec St.
<BR>Anaheim, CA 92805
<BR>
<BR>(714) 999-1616
<BR>
<BR>www.thetestlab.com
<BR>
<BR>
<BR>
<BR>Susan Allen
<BR>HAM Technology</FONT></HTML>
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Date: Fri, 22 Feb 2002 12:19:41 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Antw: [TN] Environmental Testing - parallel vs. sequential
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Guenter et al,
Thanks for the input.
The point of environmental testing - in this instance - is to demonstrate=
that the product is fit for service in the environment the product will =
operate in for the lifetime of that product.
In my view parallel testing will demonstrate that a product can or cannot=
withstand a single type of 'stress'. This is useful and of course gives =
an insight into fundamental properties of some aspect of the design. Howe=
ver in real life a product is subjected to many 'stresses' at the same ti=
me and parallel testing will never test for this. Therefore parallel test=
ing may tell you that a product is unfit for service but will never tell =
you that it definitely is. My view is that it is useful as a precursor to=
sequential testing.
It would probably be best if one could apply a lot of 'stresses' simultan=
eously but that is generally impractical. So one is left with sequential =
testing. Yes, it is probably impossible to devise a test spec that will c=
over every possible failure mode. However to say it is therefore not wort=
h doing is like saying half a loaf is no better than no loaf at all. It s=
eems to me that careful consideration of standard test specs e.g. EN 6006=
8 which are based on an accumulation of experience combined with one's ow=
n specific product knowledge should result in the best qualification prog=
ramme.
Regards,
[log in to unmask] wrote:
> Eric
>
> Just as a basic thought: It is not the goal of a test to be as severe a=
s possible but to proof that a product/process meets the requirements. To=
do so, the tests performed have to be chosen carefully and designed to s=
how any week points but not to wreck the specimen on any account.
>
> Now, you talk about different philosophies and different goals:
>
> - Parallel testing:
> The idea of sequential testing is to find the answer of a specimen on a=
particular stress. There is no sense in starting combined tests is one d=
oesn't know how an item to be tested reacts if it is exposed to let's say=
high temperature.
>
> - Sequential testing:
> As I get it, you want to evaluate the effects of combined environmental=
stress on a specimen by exposing the specimen to the stresses one after =
the other. See, as soon as you get into combined testing the whole thing =
gets quite complex. Your thought is right, if the stresses do occur one a=
fter the other. One example is the degradation of roads due to frost. Fir=
stly water penetrates into small cavities of the surface. When freezing t=
he water expands breaking pieces out of the road. However, if the combine=
d stress occurs simultaneously the attempt to simulate their combined eff=
ect by sequential testing seems fruitless to me. Just as an example for t=
his thought we can take diffusion. As you know, diffusion through a membr=
ane is driven by the temperature and by the difference of the concentrati=
on of a certain substance on both sides of the membrane. High temperature=
accelerates diffusion and so does a large difference in concentration. A=
ccording to your thought one could theoretically
> perform a test where a specimen is firstly exposed to an environment wi=
th high temperature and a low difference in concentration dC ( or even wo=
rse not caring for the dC) and then making a test with the same specimen =
where it is exposed to a high dC with low Temperature (or similarly to ab=
ove not caring for the temperature). As you see clearly, this test is abs=
olutely meaningless when it comes to find the effect of the combination =
of temp. and dC. If you want to find that you have to run tests where the=
dC and the high temperature occur together.
>
> I think I mentioned this earlier. Designing sensible tests is a difficu=
lt business and requires a lot of knowledge of physics of failure and inc=
orporates some math. To learn about the mathematical part read Montgomery=
s "Design and Analysis of Experiments". For the physics of failure part I=
am afraid you have to go through some literature dealing with physics, f=
ailure analysis and material science.
>
> Have a great day
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
> -----------------------------------------------------------------------=
----------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d=
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nal
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-970=
0 ext.5315
> -----------------------------------------------------------------------=
----------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Fri, 22 Feb 2002 07:48:42 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: Defects terminology
X-To: Ivanoe Pedruzzi <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Morning Folks,
Ivanoe,
Billboarding is described in IPC-A-610C on page 12-77. Figure 12-130
shows a picture of Billboarding and is acceptable for Class 1 & 2
products providing it meets the criteria stipulated.
Barry Gallegos
-----Original Message-----
From: Ivanoe Pedruzzi [mailto:[log in to unmask]]
Sent: Friday, February 22, 2002 12:11 AM
To: [log in to unmask]
Subject: Re: [TN] Defects terminology
No doubt,
Manhattan has the same meaning as tombstone. As I had lots of them I had to
learn that terminology.
Ivan Pedruzzi
Manufacturing Engineering
Jabil Circuit Italy
-----Original Message-----
From: Sklenar Vit (RBAU-EB/MGE4) [mailto:[log in to unmask]]
Sent: Friday, February 22, 2002 1:24 AM
To: [log in to unmask]
Subject: [TN] Defects terminology
Good day,
Did you come across with these defect terms - Manhattan and
Billboard ? If yes do you know what is the meaning?
I assume that Manhattan means either a lot of tombstoned parts on
PCB , right up.
Billboard?
Please can you explain the meaning ?
Thank you
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, February 05, 2002 7:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proving the reliability of a solder joint
>
> My company just got a copy on CD. Werner is the chair for the committee.
> Who
> else indeed? Other names read like a who's who or Hall Of Fame.
>
> Can't wait to get into this little baby!
>
> MoonCaveMan
>
> --------------------------------------------------------------------------
> -------
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Date: Fri, 22 Feb 2002 10:32:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Safe processing window
MIME-Version: 1.0
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Hi Richard,
In a message dated 02/21/2002 2:04:38, [log in to unmask] writes:
>but then I've heard discussion that a fast cool down can produce a better
solder joint metallurgically....
Yes, this was a bit of red herring in the early 80's. Faster cooling produces
finer grained solder joints which in accelerated testing show about a factor
of 2 longer life. Unfortunately, the grain structure of solder coarsens with
time and temperature and after one year on the shelf you cannot tell the
difference. That is why both IPC-SM-785 and IPC-9701 strongly recommend
artificial aging to coarsen the solder grain structure prior to T-cycling to
prevent unrealistic high test results.
Werner Engelmaier
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Date: Fri, 22 Feb 2002 15:42:19 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Olivia Mc Dermott <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Olivia Mc Dermott <[log in to unmask]>
Subject: Assessments
Mime-Version: 1.0
Content-Type: text/html
<html><div style='background-color:'><DIV></DIV>
<DIV></DIV>
<P>Hi all,</P>
<P>How would you assess/how are you assessed in soldering skills after completion of your initial training. Would it be all theoretical or practical? What would you cover? What do you think of on-line learning and do you know of any web sites I could sample? Even for ice breakers and fun things to break up the re-training sessions? </P>
<P>Thanks in advance for your assistance.<BR><BR><BR>Olivia Mc Dermott </P>
<DIV></DIV></div><br clear=all><hr>Get your FREE download of MSN Explorer at <a href='http://go.msn.com/bql/hmtag_etl_EN.asp'>http://explorer.msn.com</a>.<br></html>
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Date: Fri, 22 Feb 2002 10:12:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
sschiera <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: sschiera <[log in to unmask]>
Subject: Re: Just In Time deliveries
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
For information on what JIT/Lean is try some of the following:
http://www.ame.org
http://www.productivity-inc.com/
Steve
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, February 20, 2002 12:43 PM
Subject: Just In Time deliveries
Schindler Elevator Corp is moving to a just-in-time delivery system for
PWB's. Can anyone provide me with some advice and/or publications on
the do and dont's of a just-in-time service?
Thankyou
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Date: Fri, 22 Feb 2002 09:34:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: ENIG black pad issues
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
We have used ENIG as our primary BGA board finish for many many, many
boards built for cellular communications without issues regarding this problem.
We have a major PWB fabricator telling us that they cannot control what
appears to be a "black pad" problem and that we should be changing to
Entek's OSP combined with a selective gold process for our standard finish.
I cannot say that we have never had this problem before but usually it was
more a case of unrinsed soldermask on a pad rather than corroded nickel
plating beneath the gold finish.
I did the cross sectioning myself and took some great pictures of the
contaminated pad surfaces that were yielding when subjected to drop testing.
I am convinced that ENIG is a solid finish but I know that it can be
susceptible to nickel wetting problems. I have three questions:
1) What kind of frequency are the rest of you finding "black pad" to occur
on ENIG boards?
2) What finish do you use for high density BGA/CSP double sided boards
that have surface contact (gold) plating requirements?
3) Are any of you using underfill to hopefully negate the solder joint
brittleness that the black pad surface inherently creates?
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Date: Fri, 22 Feb 2002 11:52:36 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ENIG black pad issues
X-To: [log in to unmask]
Been down this path many times. It has twist and turns not conducive to high
speed driving. In the early days of enig, lots of black pad at every turn.
Not trying to seem harsh, but I don't used suppliers who cannot prove they
have this problem licked. If you look at Proto Engineering's web site you'll
see they have a plant tour. About two thirds of the way through it, you'll
see how they ensure black pad defects are eliminated.
I use about 6 shops around the country. I have qualified them all to ensure
all processes are effectively managed. I have only had one occurence of
black pad with one of them in the early days of enig.
The enig process is capable of being very well managed and over the past
three years most everyone has caught on how to do it.
So my answer to your question lies above.
MoonMan
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Date: Fri, 22 Feb 2002 13:03:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: ENIG black pad issues
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Phil,
A good article just came out addressing "black pad".
Might want to read it.
www.pcfab.com/db_area/archive/2002/0202/cullen.html
Sounds like your vendor has a process control issue. Or solder mask issues.
We have over 20 boards with BGA's and CSP's and have not had any issues with
black pad.
We do not underfill.
Hope this helps.
-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Friday, February 22, 2002 12:34 PM
To: [log in to unmask]
Subject: [TN] ENIG black pad issues
We have used ENIG as our primary BGA board finish for many many, many
boards built for cellular communications without issues regarding this
problem.
We have a major PWB fabricator telling us that they cannot control what
appears to be a "black pad" problem and that we should be changing to
Entek's OSP combined with a selective gold process for our standard finish.
I cannot say that we have never had this problem before but usually it was
more a case of unrinsed soldermask on a pad rather than corroded nickel
plating beneath the gold finish.
I did the cross sectioning myself and took some great pictures of the
contaminated pad surfaces that were yielding when subjected to drop testing.
I am convinced that ENIG is a solid finish but I know that it can be
susceptible to nickel wetting problems. I have three questions:
1) What kind of frequency are the rest of you finding "black pad" to occur
on ENIG boards?
2) What finish do you use for high density BGA/CSP double sided boards
that have surface contact (gold) plating requirements?
3) Are any of you using underfill to hopefully negate the solder joint
brittleness that the black pad surface inherently creates?
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Date: Fri, 22 Feb 2002 10:30:35 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: Assessments
X-To: Olivia Mc Dermott <[log in to unmask]>
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_k+kQfv9CpyuPVwT4qri1pQ)"
This is a multi-part message in MIME format.
--Boundary_(ID_k+kQfv9CpyuPVwT4qri1pQ)
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
Morning Olivia,
Back in my mil-spec days we had a requirement for periodic re-certification. This training was done in house and consisted of reviewing accept/reject criteria with the operator (the theoretical part). Followed by assembly of a practice/test part (the practical part). The assembly was then sent through normal QC inspection, if the assembly passed the operator got their cert.
For this to work we had to have a mil spec certified trainer in house. This lucky individual was rewarded with periodic trips to China Lake to maintain *their* certification. Should be a lot simpler now a days.
Hope you find this helpful,
Dan
--Boundary_(ID_k+kQfv9CpyuPVwT4qri1pQ)
Content-type: text/html; charset=iso-8859-1
Content-transfer-encoding: 7BIT
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT size=2>Morning Olivia,</FONT></DIV>
<DIV><FONT size=2>Back in my mil-spec days we had a requirement for periodic
re-certification. This training was done in house and consisted of reviewing
accept/reject criteria with the operator (the theoretical part). Followed by
assembly of a practice/test part (the practical part). The assembly was
then sent through normal QC inspection, if the assembly passed the operator got
their cert.</FONT></DIV>
<DIV><FONT size=2>For this to work we had to have a mil spec certified trainer
in house. This lucky individual was rewarded with periodic trips to China Lake
to maintain *their* certification. Should be a lot simpler now a
days.</FONT></DIV>
<DIV><FONT size=2>Hope you find this helpful,</FONT></DIV>
<DIV><FONT size=2>Dan</FONT></DIV></BODY></HTML>
--Boundary_(ID_k+kQfv9CpyuPVwT4qri1pQ)--
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Date: Fri, 22 Feb 2002 11:40:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: ENIG black pad issues
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
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Phil,
Dealing with the "lowest bidder" will not work on this issue!
David A. Douthit
Manager
LoCan LLC
------------------------------
phil bavaro wrote:
> We have used ENIG as our primary BGA board finish for many many, many
> boards built for cellular communications without issues regarding this problem.
>
> We have a major PWB fabricator telling us that they cannot control what
> appears to be a "black pad" problem and that we should be changing to
> Entek's OSP combined with a selective gold process for our standard finish.
>
> I cannot say that we have never had this problem before but usually it was
> more a case of unrinsed soldermask on a pad rather than corroded nickel
> plating beneath the gold finish.
>
> I did the cross sectioning myself and took some great pictures of the
> contaminated pad surfaces that were yielding when subjected to drop testing.
>
> I am convinced that ENIG is a solid finish but I know that it can be
> susceptible to nickel wetting problems. I have three questions:
>
> 1) What kind of frequency are the rest of you finding "black pad" to occur
> on ENIG boards?
> 2) What finish do you use for high density BGA/CSP double sided boards
> that have surface contact (gold) plating requirements?
> 3) Are any of you using underfill to hopefully negate the solder joint
> brittleness that the black pad surface inherently creates?
>
> ---------------------------------------------------------------------------------
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Date: Fri, 22 Feb 2002 13:49:59 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_ca.6feab37.29a7ecd7_boundary"
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Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! Where did
this take place? In a SIR chamber?
-Steve Gregory-
> Hi Steve,
>
> Thanks for offering to post my pictures of the dendritic growth. It will
> be interesting to see what the consensus is although since I sent the email
> out I have been able to get my hands on the defect and take a close enough
> look to answer the question. Let's put the picture up and see what the
> responses are.
>
> Phil
--part1_ca.6feab37.29a7ecd7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Phil!
<BR>
<BR>The pictures are up! Go to:
<BR>
<BR>http://www.stevezeva.homstead.com
<BR>
<BR>Those are the best examples of dendritic growth as I've ever seen! Where did this take place? In a SIR chamber?
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Steve,
<BR>
<BR>Thanks for offering to post my pictures of the dendritic growth. It will
<BR>be interesting to see what the consensus is although since I sent the email
<BR>out I have been able to get my hands on the defect and take a close enough
<BR>look to answer the question. Let's put the picture up and see what the
<BR>responses are.
<BR>
<BR>Phil</FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_ca.6feab37.29a7ecd7_boundary--
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Date: Fri, 22 Feb 2002 13:03:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: ENIG black pad issues
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_A6FBE112.B0D1BC5D"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
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Content-Disposition: inline
I had spoken to a PCB supplier FAE a couple of weeks back and he was =
mentioning that awhile ago he knew of a situation where a PCB had a =
problem with black pad and the customer thought it was poor supplier =
process control. But when the product was moved to a PCB house that had =
been doing this finish and had never had black pad before tried to build =
these same PCB's now had a black pad problem. If this is the case then =
couldn't black pad be tried back to a design and process mismatch? Anyone =
else know of any further such stories? Is this a possibility?
Kathy=20
--=_A6FBE112.B0D1BC5D
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I had spoken to a PCB supplier FAE a couple of weeks back and he was
mentioning that awhile ago he knew of a situation where a PCB had a problem with
black pad and the customer thought it was poor supplier process control.
But when the product was moved to a PCB house that had been doing this finish
and had never had black pad before tried to build these same PCB's now had a
black pad problem. If this is the case then couldn't black pad be tried
back to a design and process mismatch? Anyone else know of any further
such stories? Is this a possibility?</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_A6FBE112.B0D1BC5D--
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Date: Fri, 22 Feb 2002 14:11:05 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic growth or what?
MIME-Version: 1.0
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Have to agree with Steve - really beautiful shots of dendrites!
Susan Mansilla
Robisan Lab
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Date: Fri, 22 Feb 2002 15:04:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
George Boncek <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: George Boncek <[log in to unmask]>
Subject: FW: hole not to spec for compliant pins
-----Original Message-----
From: Loren Hendrix [mailto:[log in to unmask]]
Sent: Friday, February 22, 2002 12:52 PM
To: [log in to unmask]
Cc: ed
Subject: hole not to spec for compliant pins
To all,
I have a test board, that is gold over nickel, and .200 thick.
The problem I have is that the holes for the compliant pins should
have been drill at .045, and plated down to .040. The holes however
have finished at .045. (hole count is 1456)
The range that the assembly house can live with is .040 +/-.003.
I would have to somehow replate the barrels of the holes
with a minimum of .001-.002 mils to get within the compliant pin spec.
Soldering the pins in, is not an option.
If anyone has seen this problem before, could you please respond ASAP, with
any possible solutions, or the name of someone who might be able to fix
these boards.
Thank you,
Loren Hendrix
Sr. Designer
Limat Graphics
128 E.Liberty St.
Danbury, CT 06810
voice 203-798-9771 Ext. 218
fax 203-790-5666
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Date: Fri, 22 Feb 2002 12:22:00 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: Dendritic Growth...
In-Reply-To: <[log in to unmask]>
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Phil,
Beautiful pictures of dendritic growth. Any other background information?
Hans Shin
Pacific Testing Laboratories, Inc.
www.pacifictesting.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, February 22, 2002 10:50 AM
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...
Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! Where
did this take place? In a SIR chamber?
-Steve Gregory-
------=_NextPart_000_0017_01C1BB9B.880B2000
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charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 5.00.3018.900" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D210502020-22022002>Phil,=20
</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D210502020-22022002></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D210502020-22022002>Beautiful pictures of dendritic growth. =
Any other=20
background information?</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D210502020-22022002></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D210502020-22022002>Hans=20
Shin</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D210502020-22022002>Pacific Testing Laboratories, =
Inc.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D210502020-22022002><A=20
href=3D"http://www.pacifictesting.com">www.pacifictesting.com</A></SPAN><=
/FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D210502020-22022002></SPAN></FONT> </DIV>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Friday, February 22, 2002 10:50 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Dendritic=20
Growth...<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi Phil!=20
<BR><BR>The pictures are up! Go to: =
<BR><BR>http://www.stevezeva.homstead.com=20
<BR><BR>Those are the best examples of dendritic growth as I've ever =
seen!=20
Where did this take place? In a SIR chamber? <BR><BR>-Steve Gregory-=20
<BR><BR></FONT></BLOCKQUOTE></FONT></BODY></HTML>
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Date: Fri, 22 Feb 2002 15:27:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: Re: Dendritic Growth...here's the link...
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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http://www.stevezeva.homestead.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, February 22, 2002 1:50 PM
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...
Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! Where
did this take place? In a SIR chamber?
-Steve Gregory-
Hi Steve,
Thanks for offering to post my pictures of the dendritic growth. It
will
be interesting to see what the consensus is although since I sent the
email
out I have been able to get my hands on the defect and take a close
enough
look to answer the question. Let's put the picture up and see what the
responses are.
Phil
------=_NextPart_000_0006_01C1BBB5.6C262B40
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charset="Windows-1252"
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<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DTahoma size=3D2><SPAN class=3D710142620-22022002><A=20
href=3D"http://www.stevezeva.homestead.com">http://www.stevezeva.homestea=
d.com</A></SPAN></FONT></DIV>
<DIV><FONT face=3DTahoma size=3D2><SPAN=20
class=3D710142620-22022002></SPAN></FONT> </DIV>
<DIV><FONT face=3DTahoma><SPAN =
class=3D710142620-22022002></SPAN></FONT><FONT=20
face=3DTahoma><FONT size=3D2><SPAN class=3D710142620-22022002><FONT =
face=3DArial=20
color=3D#0000ff> </FONT></SPAN></FONT></FONT></DIV>
<DIV><FONT face=3DTahoma><FONT size=3D2><SPAN=20
class=3D710142620-22022002></SPAN></FONT></FONT> </DIV>
<DIV><FONT face=3DTahoma><FONT size=3D2><SPAN=20
class=3D710142620-22022002> </SPAN>-----Original =
Message-----<BR><B>From:</B>=20
TechNet [mailto:[log in to unmask]]<B>On Behalf Of=20
</B>[log in to unmask]<BR><B>Sent:</B> Friday, February 22, 2002 1:50=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Dendritic=20
Growth...<BR><BR></DIV></FONT></FONT>
<BLOCKQUOTE><FONT face=3Darial,helvetica><FONT size=3D2>Hi Phil! =
<BR><BR>The=20
pictures are up! Go to: <BR><BR>http://www.stevezeva.homstead.com=20
<BR><BR>Those are the best examples of dendritic growth as I've ever =
seen!=20
Where did this take place? In a SIR chamber? <BR><BR>-Steve Gregory-=20
<BR><BR><BR>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid; MARGIN-RIGHT: 0px"=20
TYPE=3D"CITE">Hi Steve, <BR><BR>Thanks for offering to post my =
pictures of the=20
dendritic growth. It will <BR>be interesting to see what the =
consensus=20
is although since I sent the email <BR>out I have been able to get =
my hands=20
on the defect and take a close enough <BR>look to answer the =
question.=20
Let's put the picture up and see what the <BR>responses are.=20
<BR><BR>Phil</FONT><FONT lang=3D0 face=3DArial size=3D3=20
FAMILY=3D"SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=3D0 =
face=3DArial size=3D2=20
FAMILY=3D"SANSSERIF"><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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Date: Fri, 22 Feb 2002 15:33:19 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...here's the link...
X-To: [log in to unmask]
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OOPS! Didn't use my spell checher...er, I mean Cheker...no wait,
cheecer...ahhhh,
nevermind! B^)~
-Steve Gregory-
> <A HREF="http://www.stevezeva.homestead.com/">http://www.stevezeva.homestead.com</A>
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
> Sent: Friday, February 22, 2002 1:50 PM
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
>
> >> Hi Phil!
>>
>> The pictures are up! Go to:
>>
>> http://www.stevezeva.homstead.com
>>
>> Those are the best examples of dendritic growth as I've ever seen! Where
>> did this take place? In a SIR chamber?
>>
>> -Steve Gregory-
>>
>
--part1_fd.13ff0c92.29a8050f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">OOPS! Didn't use my spell checher...er, I mean Cheker...no wait, cheecer...ahhhh,
<BR>nevermind! B^)~
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Tahoma" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><A HREF="http://www.stevezeva.homestead.com/">http://www.stevezeva.homestead.com</A>
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"> </FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Tahoma" LANG="0">
<BR> -----Original Message-----
<BR><B>From:</B> TechNet [mailto:[log in to unmask]]<B>On Behalf Of </B>[log in to unmask]
<BR><B>Sent:</B> Friday, February 22, 2002 1:50 PM
<BR><B>To:</B> [log in to unmask]
<BR><B>Subject:</B> Re: [TN] Dendritic Growth...
<BR>
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Phil!
<BR>
<BR>The pictures are up! Go to:
<BR>
<BR>http://www.stevezeva.homstead.com
<BR>
<BR>Those are the best examples of dendritic growth as I've ever seen! Where did this take place? In a SIR chamber?
<BR>
<BR>-Steve Gregory-
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
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Date: Fri, 22 Feb 2002 14:41:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
I grow this stuff in my cave all the time with no consequences what what
what what whatsoever.
MoonMan
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Date: Fri, 22 Feb 2002 15:49:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McFaddin, Wade" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McFaddin, Wade" <[log in to unmask]>
Subject: Re: ENIG black pad issues
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Hi Phil,
I can only comment on the last of your questions from a laboratory failure
analysis viewpoint. We have one customer whose PCB assemblies exhibited the
"black pad" separations on a BGA component. They thought that underfilling
the BGA would help hold the solder balls onto the board, but cross-sections
after the underfill process showed that the balls separated anyway. I don't
know if would happen with every type of underfill process, but it did not
seem to have a positve effect for this customer.
Wade McFaddin
Nextek Inc.
> -----Original Message-----
> From: phil bavaro [SMTP:[log in to unmask]]
> Sent: Friday, February 22, 2002 11:34 AM
> To: [log in to unmask]
> Subject: [TN] ENIG black pad issues
>
> We have used ENIG as our primary BGA board finish for many many, many
> boards built for cellular communications without issues regarding this
> problem.
>
> We have a major PWB fabricator telling us that they cannot control what
> appears to be a "black pad" problem and that we should be changing to
> Entek's OSP combined with a selective gold process for our standard
> finish.
>
> I cannot say that we have never had this problem before but usually it was
> more a case of unrinsed soldermask on a pad rather than corroded nickel
> plating beneath the gold finish.
>
> I did the cross sectioning myself and took some great pictures of the
> contaminated pad surfaces that were yielding when subjected to drop
> testing.
>
> I am convinced that ENIG is a solid finish but I know that it can be
> susceptible to nickel wetting problems. I have three questions:
>
> 1) What kind of frequency are the rest of you finding "black pad" to
> occur
> on ENIG boards?
> 2) What finish do you use for high density BGA/CSP double sided boards
> that have surface contact (gold) plating requirements?
> 3) Are any of you using underfill to hopefully negate the solder joint
> brittleness that the black pad surface inherently creates?
>
> --------------------------------------------------------------------------
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Date: Fri, 22 Feb 2002 23:09:37 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Does that prove the law of least resistance?
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: 22 February 2002 20:41
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
>
> I grow this stuff in my cave all the time with no consequences what what
> what what whatsoever.
>
> MoonMan
>
> ------------------------------------------------------------------
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>
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Date: Fri, 22 Feb 2002 15:47:57 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Dendritic Growth...here's the link...
X-To: Joseph Spicuzza <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0009_01C1BBB8.4D1A9990"
This is a multi-part message in MIME format.
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Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Those are gorgeous!!
The only time that I remember battling dendrites like that was on a high
voltage divider resistor. The problem occured only in the areas where the
volts/m where high. Sorry, but I dont remember the numbers anymore. So I am
curious about the field strength across this area. I ended up covering the
resistor with thick layer of a low dielectric constant material that adhered
very well to the surface of the resistor (plasma cleaning before applying!).
The electric field is going to concentrate itself in the material with the
lowest dielectric constant. So if that is represented by small crosssection,
you will find a very high field strength in that location and therefore a
strong tendency to grow dendrites there. That is also why I expect that by
far most of your samples have dendrites growing starting in the narrow spots
in the middle of the part (capacitor?, high voltage?, short distance?).
Any more details available?
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Joseph Spicuzza
Sent: Friday, February 22, 2002 12:27
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...here's the link...
http://www.stevezeva.homestead.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, February 22, 2002 1:50 PM
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...
Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! Where
did this take place? In a SIR chamber?
-Steve Gregory-
Hi Steve,
Thanks for offering to post my pictures of the dendritic growth. It
will
be interesting to see what the consensus is although since I sent the
email
out I have been able to get my hands on the defect and take a close
enough
look to answer the question. Let's put the picture up and see what
the
responses are.
Phil
------=_NextPart_000_0009_01C1BBB8.4D1A9990
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2713.1100" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Those=20
are gorgeous!!</FONT></SPAN></DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2>The=20
only time that I remember battling dendrites like that was on a high =
voltage=20
divider resistor. The problem occured only in the areas where the =
volts/m where=20
high. Sorry, but I dont remember the numbers anymore. So I am curious =
about the=20
field strength across this area. I ended up covering the resistor with =
thick=20
layer of a low dielectric constant material that adhered very well to =
the=20
surface of the resistor (plasma cleaning before applying!). =
</FONT></SPAN></DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2>The=20
electric field is going to concentrate itself in the material with =
the=20
lowest dielectric constant. So if that is represented by small=20
crosssection, you will find a very high field strength in that location =
and=20
therefore a strong tendency to grow dendrites there. That is also why I =
expect=20
that by far most of your samples have dendrites growing starting in the =
narrow=20
spots in the middle of the part (capacitor?, high voltage?, short=20
distance?).</FONT></SPAN></DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Any=20
more details available?</FONT></SPAN></DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Ahne.</FONT></SPAN></DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D240033523-22022002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Joseph =
Spicuzza<BR><B>Sent:</B>=20
Friday, February 22, 2002 12:27<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Dendritic Growth...here's =
the=20
link...<BR><BR></FONT></DIV>
<DIV><FONT face=3DTahoma size=3D2><SPAN class=3D710142620-22022002><A=20
=
href=3D"http://www.stevezeva.homestead.com">http://www.stevezeva.homestea=
d.com</A></SPAN></FONT></DIV>
<DIV><FONT face=3DTahoma size=3D2><SPAN=20
class=3D710142620-22022002></SPAN></FONT> </DIV>
<DIV><FONT face=3DTahoma><SPAN =
class=3D710142620-22022002></SPAN></FONT><FONT=20
face=3DTahoma><FONT size=3D2><SPAN class=3D710142620-22022002><FONT =
face=3DArial=20
color=3D#0000ff></FONT></SPAN></FONT></FONT> </DIV>
<DIV><FONT face=3DTahoma><FONT size=3D2><SPAN=20
class=3D710142620-22022002></SPAN></FONT></FONT> </DIV>
<DIV><FONT face=3DTahoma><FONT size=3D2><SPAN=20
class=3D710142620-22022002> </SPAN>-----Original=20
Message-----<BR><B>From:</B> TechNet [mailto:[log in to unmask]]<B>On =
Behalf Of=20
</B>[log in to unmask]<BR><B>Sent:</B> Friday, February 22, 2002 1:50=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Dendritic =
Growth...<BR><BR></DIV></FONT></FONT>
<BLOCKQUOTE><FONT face=3Darial,helvetica><FONT size=3D2>Hi Phil! =
<BR><BR>The=20
pictures are up! Go to: <BR><BR>http://www.stevezeva.homstead.com=20
<BR><BR>Those are the best examples of dendritic growth as I've ever =
seen!=20
Where did this take place? In a SIR chamber? <BR><BR>-Steve Gregory- =
<BR><BR><BR>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff =
2px solid; MARGIN-RIGHT: 0px"=20
TYPE=3D"CITE">Hi Steve, <BR><BR>Thanks for offering to post my =
pictures of=20
the dendritic growth. It will <BR>be interesting to see what =
the=20
consensus is although since I sent the email <BR>out I have been =
able to=20
get my hands on the defect and take a close enough <BR>look to =
answer the=20
question. Let's put the picture up and see what the =
<BR>responses=20
are. <BR><BR>Phil</FONT><FONT lang=3D0 face=3DArial size=3D3=20
FAMILY=3D"SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=3D0 =
face=3DArial size=3D2=20
=
FAMILY=3D"SANSSERIF"><BR></BLOCKQUOTE></BLOCKQUOTE></FONT></FONT></BODY><=
/HTML>
------=_NextPart_000_0009_01C1BBB8.4D1A9990--
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Date: Fri, 22 Feb 2002 17:29:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
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boundary="------------871AA8C39636BB9084AC0578"
--------------871AA8C39636BB9084AC0578
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GREAT pictures.
Now the what (chip caps/resistors and size), where, when, how long, and
voltage levels would be VERY nice!
David A. Douthit
Manager
LoCan LLC
[log in to unmask] wrote:
> Hi Phil!
>
> The pictures are up! Go to:
>
> http://www.stevezeva.homstead.com
>
> Those are the best examples of dendritic growth as I've ever seen!
> Where did this take place? In a SIR chamber?
>
> -Steve Gregory-
>
>
>
>> Hi Steve,
>>
>> Thanks for offering to post my pictures of the dendritic growth. It
>> will
>> be interesting to see what the consensus is although since I sent
>> the email
>> out I have been able to get my hands on the defect and take a close
>> enough
>> look to answer the question. Let's put the picture up and see what
>> the
>> responses are.
>>
>> Phil
>
>
>
--------------871AA8C39636BB9084AC0578
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
GREAT pictures.
<p>Now the what (chip caps/resistors and size), where, when, how long,
and voltage levels would be VERY nice!
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Hi Phil!</font></font>
<p><font face="arial,helvetica"><font size=-1>The pictures are up! Go to:</font></font>
<p><font face="arial,helvetica"><font size=-1><A HREF="http://www.stevezeva.homstead.com">http://www.stevezeva.homstead.com</A></font></font>
<p><font face="arial,helvetica"><font size=-1>Those are the best examples
of dendritic growth as I've ever seen! Where did this take place? In a
SIR chamber?</font></font>
<p><font face="arial,helvetica"><font size=-1>-Steve Gregory-</font></font>
<br>
<br>
<blockquote TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><font face="arial,helvetica"><font size=-1>Hi
Steve,</font></font>
<p><font face="arial,helvetica"><font size=-1>Thanks for offering to post
my pictures of the dendritic growth. It will</font></font>
<br><font face="arial,helvetica"><font size=-1>be interesting to see what
the consensus is although since I sent the email</font></font>
<br><font face="arial,helvetica"><font size=-1>out I have been able to
get my hands on the defect and take a close enough</font></font>
<br><font face="arial,helvetica"><font size=-1>look to answer the question.
Let's put the picture up and see what the</font></font>
<br><font face="arial,helvetica"><font size=-1>responses are.</font></font>
<p><font face="arial,helvetica"><font size=-1>Phil</font></font></blockquote>
<br> </blockquote>
</html>
--------------871AA8C39636BB9084AC0578--
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Date: Sat, 23 Feb 2002 14:22:39 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
sklenar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: sklenar <[log in to unmask]>
Subject: Re: Solder Paste in through hole
In-Reply-To: <[log in to unmask]>
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Hi Techneters,
please, can somebody help me to find manufacturer of TO220 power transistors
and their equivalents - I, so far, can not find any reference either to
manufacturer ( Korea ) or type:
40871 NPN
40872 PNP
mnfr abbreviation is SM.
Thank you
Vit
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Date: Sat, 23 Feb 2002 14:24:40 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
sklenar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: sklenar <[log in to unmask]>
Subject: 40871-2 transistors
MIME-Version: 1.0
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> Hi Techneters,
>
> please, can somebody help me to find manufacturer of TO220 power
> transistors and their equivalents - I, so far, can not find any
> reference either to manufacturer ( Korea ) or type:
>
> 40871 NPN
> 40872 PNP
>
> mnfr abbreviation is SM.
>
> Thank you
Vit Sklenar
t: 61 3 9720 2419
f: 61 3 9720 0535
email: [log in to unmask]
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Date: Fri, 22 Feb 2002 23:18:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dendritic Growth...
what what what what whatsoever
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Date: Sat, 23 Feb 2002 05:49:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: 40871-2 transistors
X-To: sklenar <[log in to unmask]>
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These are RCA part numbers that were discontinued when the company was
bought by Harris(GE).
100V 7A 40W switching transistors in ~TO220, (not particularly fast).
Try TIP41C, TIP42C originally from TI, but produced now as commodity parts.
RL
----- Original Message -----
From: sklenar <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, February 22, 2002 10:24 PM
Subject: [TN] 40871-2 transistors
> > Hi Techneters,
> >
> > please, can somebody help me to find manufacturer of TO220 power
> > transistors and their equivalents - I, so far, can not find any
> > reference either to manufacturer ( Korea ) or type:
> >
> > 40871 NPN
> > 40872 PNP
> >
> > mnfr abbreviation is SM.
> >
> > Thank you
>
> Vit Sklenar
> t: 61 3 9720 2419
> f: 61 3 9720 0535
> email: [log in to unmask]
>
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Date: Sat, 23 Feb 2002 05:49:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
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Great Pictures
I would like to know the ionic cleanliness by Ion Chromatography of the parts
and flux residues. We have seen similar dendritic growth due to the
component cleanliness, as well as, the cleanliness of the assembly.
Terry Munson
CSL Inc.
P 765-457-8095
F 765-457-9033
<A HREF="www.Residues.com">www.Residues.com</A>
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Date: Sat, 23 Feb 2002 14:25:36 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Dendritic Growth...
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:-)
Terry,
I'm sure you didn't see dendrites because of component/assembly
cleanliness, but rather lack thereof!!! :-)
Best regards,
Nitpicker Brian
[log in to unmask] wrote:
>
> Great Pictures
>
> I would like to know the ionic cleanliness by Ion Chromatography of the parts
> and flux residues. We have seen similar dendritic growth due to the
> component cleanliness, as well as, the cleanliness of the assembly.
>
> Terry Munson
> CSL Inc.
> P 765-457-8095
> F 765-457-9033
>
> <A HREF="www.Residues.com">www.Residues.com</A>
>
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Date: Sat, 23 Feb 2002 07:41:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Request for ENIG finish primer
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For many years I have followed the various threads concerning ENIG finish on
PCB's and have only casually followed them enough to know just a little.
Without clogging the net with a set of questions, does anyone know of a
website or texts that represents a primer about the finish? I guess I'm
looking for real basic stuff here, things like when to use it, when not to
use it, pros and cons, process concerns, can it be selectively placed on
circuit boards, etc. and so on and so forth.
Any and all responses will be appreciated.
Bill Kasprzak
Moog Inc. Manufacturing Engineering, Electronics
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Date: Sun, 24 Feb 2002 18:08:17 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
sangliu <[log in to unmask]>
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Subject: Re: Dendritic Growth...
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Date: Mon, 25 Feb 2002 08:51:03 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Re: ENIG black pad issues
X-To: phil bavaro <[log in to unmask]>
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Hi, Phil,
1) I haven't had enough board volume to give you much of a feel for black
pad occurance, because we've only had about 40 ENIG boards made so far, but
with no problem. Some are well over a year old now and still solder well.
2) Pass - haven't had such a requirement yet.
3) I prescribed underfill for our 21mm sq CBGA and 35mm sq PBGA and several
other types as well - all 1.0 or 1.27mm pitch. The very first ENIG boards
we had with BGA's mounted were designed and assembled for us in the US
(we're in Singapore), and they failed miserably the first time they were
put into any level of vibration. The problem was very poor-looking assembly
processes - balls looked dry-jointed, very coarse with a lot of striations,
different shapes and sizes.
I had 3 more assembled locally, keeping a close eye on all the processes
used, and we got 3 good-looking boards. As a precaution (or extra
insurance), I opted to underfill them as well. The boards are military
avionics boards, subjected to all manner of TC and vibration, so I felt the
extra process was probably worthwhile. I chose a capillary-action type
underfill that is a) reworkable and b) doesn't limit me to the fluxes
contained in the 'no-flow' type of underfill that is applied to the BGA's
prior to assembly and tends not to be reworkable. So far, these new boards
have passed all the tests required of them.
Underfilling is reckoned to improve the reliability of BGA solder joints
under conditions of temperature cycling and vibration by a factor between 3
and 5 times that of joints with no underfill by helping to dissipate the
stresses built up in the joints through CTE mismatches during thermal
cycling, and through vibration. I should say that underfilling won't help
offset the effects of Black Pad and shouldn't be expected to. With Black
Pad, you won't have much of a solder joint, if any, to support with
underfill, and the more brittle nature of the oxidised Nickel plating won't
be made any less brittle with underfill either. Underfilling is intended to
further support good joints on a stable surface against the conditions
mentioned above. I'ld get your boards made right, rather than putting
sticking plasters over damage (if that's what you're [contemplating]
doing).
Hope this helps a bit with whatever you're looking into.
Peter
phil bavaro
<pbavaro@QUAL To: [log in to unmask]
COMM.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] ENIG black pad issues
<[log in to unmask]
ORG>
02/23/02
01:34 AM
Please
respond to
"TechNet
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Please
respond to
phil bavaro
We have used ENIG as our primary BGA board finish for many many, many
boards built for cellular communications without issues regarding this
problem.
We have a major PWB fabricator telling us that they cannot control what
appears to be a "black pad" problem and that we should be changing to
Entek's OSP combined with a selective gold process for our standard finish.
I cannot say that we have never had this problem before but usually it was
more a case of unrinsed soldermask on a pad rather than corroded nickel
plating beneath the gold finish.
I did the cross sectioning myself and took some great pictures of the
contaminated pad surfaces that were yielding when subjected to drop
testing.
I am convinced that ENIG is a solid finish but I know that it can be
susceptible to nickel wetting problems. I have three questions:
1) What kind of frequency are the rest of you finding "black pad" to occur
on ENIG boards?
2) What finish do you use for high density BGA/CSP double sided boards
that have surface contact (gold) plating requirements?
3) Are any of you using underfill to hopefully negate the solder joint
brittleness that the black pad surface inherently creates?
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Date: Mon, 25 Feb 2002 09:04:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
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Hi, Steve,
Just tried looking up your site to see these beautiful dendrite pictures,
but found you have a bully muscling in on your link. Instead of getting to
your site I was beamed off to http://www.megago.com/l/, who then asked me
if I wanted to make them my home page. S.. Off! I thought, but I had to
type your site address manually to get to the pictures.
Anyone else had this problem?
Peter
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Dendritic Growth...
ORG>
02/23/02
02:49 AM
Please
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"TechNet
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Please
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SteveZeva
Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! Where
did this take place? In a SIR chamber?
-Steve Gregory-
Hi Steve,
Thanks for offering to post my pictures of the dendritic growth. It will
be interesting to see what the consensus is although since I sent the
email
out I have been able to get my hands on the defect and take a close enough
look to answer the question. Let's put the picture up and see what the
responses are.
Phil
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Date: Mon, 25 Feb 2002 09:19:42 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENIG black pad issues
X-To: Kathy Kuhlow <[log in to unmask]>
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Boundary="0__=48256B6B0006288A8f9e8a93df938690918c48256B6B0006288A"
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I once read that one of the possible causes of Black Pad was an electrical
imbalance in the plating baths, though that hypothesis was pooh-poohed by
many, because the plating processes are electroless. There are different
metals involved, though, and it's quite possible that some kind of battery
effect is created. If these effects aren't balanced, either in the design
or in the plating process, and it is a cause of Black Pad .....
The question is then, how does one determine if a design is appropriate for
ENIG finishing or not? Or another question is, how to tailor the plating
process for particular design features. It would be interesting to know if
the Fab House who passed this story on to you, Kathy, knows if the black
pad occured in the same area(s) of the boards each time or more randomly.
Also if the board design had anything apparently unusual about it.
A nice thesis for some PhD student!
Peter
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] ENIG black pad issues
<[log in to unmask]
ORG>
02/23/02
03:03 AM
Please
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Kathy Kuhlow
I had spoken to a PCB supplier FAE a couple of weeks back and he was
mentioning that awhile ago he knew of a situation where a PCB had a problem
with black pad and the customer thought it was poor supplier process
control. But when the product was moved to a PCB house that had been doing
this finish and had never had black pad before tried to build these same
PCB's now had a black pad problem. If this is the case then couldn't black
pad be tried back to a design and process mismatch? Anyone else know of
any further such stories? Is this a possibility?
Kathy
(See attached file: TEXT.htm)
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Jm5ic3A7IEFueW9uZSBlbHNlIGtub3cgb2YgYW55IGZ1cnRoZXINCnN1Y2ggc3Rvcmllcz8mbmJz
cDsgSXMgdGhpcyBhIHBvc3NpYmlsaXR5PzwvRElWPg0KPERJVj4mbmJzcDs8L0RJVj4NCjxESVY+
S2F0aHkgPC9ESVY+PC9CT0RZPjwvSFRNTD4NCg==
--0__=48256B6B0006288A8f9e8a93df938690918c48256B6B0006288A--
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=========================================================================
Date: Mon, 25 Feb 2002 13:52:33 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sklenar Vit (RBAU-EB/MGE4)" <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
This is happening to me as well but not even working when I try to type it
manually !....
Regards
Vit Sklenar MGE4VS
T: (61 3)9541 7734 F: (61 3) 9541 3909
e-mail work: [log in to unmask]
e-mail home: [log in to unmask]
> Robert Bosch (Aust) ,
1555 cnr.Centre and McNaugton Road,
> Clayton , VIC 3169, Australia
>
>
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Monday, February 25, 2002 12:05 PM
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
> Hi, Steve,
>
> Just tried looking up your site to see these beautiful dendrite pictures,
> but found you have a bully muscling in on your link. Instead of getting to
> your site I was beamed off to http://www.megago.com/l/, who then asked me
> if I wanted to make them my home page. S.. Off! I thought, but I had to
> type your site address manually to get to the pictures.
>
> Anyone else had this problem?
>
> Peter
>
>
>
>
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN] Dendritic
> Growth...
> ORG>
>
>
> 02/23/02
> 02:49 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hi Phil!
>
> The pictures are up! Go to:
>
> http://www.stevezeva.homstead.com
>
> Those are the best examples of dendritic growth as I've ever seen! Where
> did this take place? In a SIR chamber?
>
> -Steve Gregory-
>
>
> Hi Steve,
>
> Thanks for offering to post my pictures of the dendritic growth. It will
> be interesting to see what the consensus is although since I sent the
> email
> out I have been able to get my hands on the defect and take a close
> enough
>
> look to answer the question. Let's put the picture up and see what the
> responses are.
>
> Phil
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you are not
> the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
>
> --------------------------------------------------------------------------
> -------
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> -------
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=========================================================================
Date: Mon, 25 Feb 2002 01:01:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Joseph Slanina <[log in to unmask]>
Subject: Joe Slanina/ASFMT is out of the office.
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
I will be out of the office starting 02/23/2002 and will not return until
03/04/2002.
I will respond to your message when I return.
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=========================================================================
Date: Mon, 25 Feb 2002 16:56:54 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
hsinsun <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: hsinsun <[log in to unmask]>
Subject: mmDiameter, mmNumber of tubes in
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Sq.mFILCAT 2020065161900,12FILCAT 4040065163900,25FILCAT 92920113708001,25.
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=========================================================================
Date: Mon, 25 Feb 2002 10:37:01 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Yes, me too! Please fix it Steve?
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of
> [log in to unmask]
> Sent: 25 February 2002 01:05
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
>
> Hi, Steve,
>
> Just tried looking up your site to see these beautiful dendrite pictures,
> but found you have a bully muscling in on your link. Instead of getting to
> your site I was beamed off to http://www.megago.com/l/, who then asked me
> if I wanted to make them my home page. S.. Off! I thought, but I had to
> type your site address manually to get to the pictures.
>
> Anyone else had this problem?
>
> Peter
>
>
>
>
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN]
> Dendritic Growth...
> ORG>
>
>
> 02/23/02
> 02:49 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hi Phil!
>
> The pictures are up! Go to:
>
> http://www.stevezeva.homstead.com
>
> Those are the best examples of dendritic growth as I've ever seen! Where
> did this take place? In a SIR chamber?
>
> -Steve Gregory-
>
>
> Hi Steve,
>
> Thanks for offering to post my pictures of the dendritic growth. It will
> be interesting to see what the consensus is although since I sent the
> email
> out I have been able to get my hands on the defect and take a
> close enough
>
> look to answer the question. Let's put the picture up and see what the
> responses are.
>
> Phil
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you
> are not the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Search previous postings at: www.ipc.org > On-Line Resources &
> Databases > E-mail Archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Mon, 25 Feb 2002 12:17:54 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Martin Tarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Martin Tarr <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: Graham Naisbitt <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Graham
I think the problem is that you used the mis-typed URL in Steve's first
message, and not the correction that he posted a bit later, which was to
http://www.stevezeva.homestead.com - this works for me, whilst I agree that
megago seem to have beamed in on the 'homstead' version.
Regards
Martin
********************************************
Martin Tarr
Martin Tarr Associates
1 Methven Drive
DUNFERMLINE
Fife
KY12 0AH
[log in to unmask]
01383 723989 phone
0709 233 3181 fax
07831 550192 mobile
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]On Behalf Of
Graham Naisbitt
Sent: 25 February 2002 10:37
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...
Yes, me too! Please fix it Steve?
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of
> [log in to unmask]
> Sent: 25 February 2002 01:05
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
>
> Hi, Steve,
>
> Just tried looking up your site to see these beautiful dendrite pictures,
> but found you have a bully muscling in on your link. Instead of getting to
> your site I was beamed off to http://www.megago.com/l/, who then asked me
> if I wanted to make them my home page. S.. Off! I thought, but I had to
> type your site address manually to get to the pictures.
>
> Anyone else had this problem?
>
> Peter
>
>
>
>
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN]
> Dendritic Growth...
> ORG>
>
>
> 02/23/02
> 02:49 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hi Phil!
>
> The pictures are up! Go to:
>
> http://www.stevezeva.homstead.com
>
> Those are the best examples of dendritic growth as I've ever seen! Where
> did this take place? In a SIR chamber?
>
> -Steve Gregory-
>
>
> Hi Steve,
>
> Thanks for offering to post my pictures of the dendritic growth. It will
> be interesting to see what the consensus is although since I sent the
> email
> out I have been able to get my hands on the defect and take a
> close enough
>
> look to answer the question. Let's put the picture up and see what the
> responses are.
>
> Phil
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you
> are not the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> ------------------------------------------------------------------
> ---------------
>
----------------------------------------------------------------------------
-----
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=========================================================================
Date: Mon, 25 Feb 2002 07:25:58 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
For those who, like me, made the side trip to Megago.com, look at the
spelling in the link. Steve misspelled "homestead". Correct the spelling
and you go right to Steve's page.
Doug Pauls
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=========================================================================
Date: Mon, 25 Feb 2002 07:31:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Sunny asks:
I'd like to know which type of Ion Chromatography can measure the local
dot ionic cleanliness. Anyone can tell me which company produce this
equipment?
Doug Pauls responds:
No company that I know of builds ion chromatography equipment to do spot
ionic checks. IC equipment merely analyzes extract solutions. If you want
to measure localized ion concentrations, you have to develop a localized
extraction technique. This might involve immersion of a portion of the
assembly in extract solution, or building some time of non-contaminating
enclosure around the area to be extracted. Once you can localize the
extraction, collect the solution an analyze it with the IC equipment
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---------------------------------------------------------------------------------
=========================================================================
Date: Mon, 25 Feb 2002 06:51:45 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
Doug,
Isn't that known as the Mountain "Dew"lution Test?
Dewey
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Monday, February 25, 2002 6:31 AM
> To: [log in to unmask]
> Subject: Re: [TN] Dendritic Growth...
>
> Sunny asks:
> I'd like to know which type of Ion Chromatography can measure the local
> dot ionic cleanliness. Anyone can tell me which company produce this
> equipment?
>
> Doug Pauls responds:
>
> No company that I know of builds ion chromatography equipment to do spot
> ionic checks. IC equipment merely analyzes extract solutions. If you
> want
> to measure localized ion concentrations, you have to develop a localized
> extraction technique. This might involve immersion of a portion of the
> assembly in extract solution, or building some time of non-contaminating
> enclosure around the area to be extracted. Once you can localize the
> extraction, collect the solution an analyze it with the IC equipment
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
---------------------------------------------------------------------------------
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=========================================================================
Date: Mon, 25 Feb 2002 09:35:44 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dennis Fritz <[log in to unmask]>
Subject: Re: Request for ENIG finish primer
X-cc: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Bill,
Do you have a copy of the IPC-4552 Proposal on Electroless Nickel/immersion
Gold plating? The committee head is George Milad. You can reach him at
"[log in to unmask] (George Milad)" I think the document is in interim final
status, but maybe it is ready for publication. George can send you a copy,
or tell you if you can get a copy at "TechDoc" on the ipc server.
Denny Fritz
MacDermid, Inc.
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Date: Mon, 25 Feb 2002 09:53:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: Re: Dendritic Growth...
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YWELL.COM>
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OK, here is the background on this particular dendrite growth:
It is a field failure unit and upon closer inspection, this dendrite
follows a crack in the capacitor from one termination to the other. In my
opinion, the crack was there first, and was filled with contaminated
moisture while the cap had battery voltage (5V) across it, causing the near
perfect dendrite to form along the walls of the crevice.
This CCA was produced on our no clean assembly line, of which the
cleanliness is monitored on each lot of boards produced. We believe that
the solder flux residues are not related to this defect. The soldering
residues do not migrate to this area of the capacitor.
The condensation moisture alone would not seem to be enough to have
generated this dendritic growth so we are investigating other possible
contamination that may have been present such as moisture dripping off of a
dirty shelf above, and also the component cleanliness itself. If the crack
was there from the beginning then the contamination could have been as well.
We have seen shorts across this capacitor before but usually only as random
faint carbon tracks that are nowhere as defined as this one was.
This one is so perfect, it almost looks like an organic plant like a small
fern.
This is an ongoing investigation so all comments are welcome and I will
provide an update at some point in the future.
Phil
At 06:51 AM 2/25/02 -0700, [log in to unmask] wrote:
>Doug,
>Isn't that known as the Mountain "Dew"lution Test?
>Dewey
>
> > -----Original Message-----
> > From: [log in to unmask] [SMTP:[log in to unmask]]
> > Sent: Monday, February 25, 2002 6:31 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Dendritic Growth...
> >
> > Sunny asks:
> > I'd like to know which type of Ion Chromatography can measure the local
> > dot ionic cleanliness. Anyone can tell me which company produce this
> > equipment?
> >
> > Doug Pauls responds:
> >
> > No company that I know of builds ion chromatography equipment to do spot
> > ionic checks. IC equipment merely analyzes extract solutions. If you
> > want
> > to measure localized ion concentrations, you have to develop a localized
> > extraction technique. This might involve immersion of a portion of the
> > assembly in extract solution, or building some time of non-contaminating
> > enclosure around the area to be extracted. Once you can localize the
> > extraction, collect the solution an analyze it with the IC equipment
> >
> > --------------------------------------------------------------------------
> > -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text in
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> > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> > --------------------------------------------------------------------------
> > -------
>
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Date: Mon, 25 Feb 2002 11:55:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Stalcup <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Stalcup <[log in to unmask]>
Subject: Solder Spatter
I am looking for some help concerning solder spatter. I manufacture
ceramic hybrids that have gold plated terminal blocks (50 mil square)
placed near the edge of the hybrid. We contiually see solder spatter
randomly located on the top of the blocks at at yield hit of anywhere from
2 to 30 percent. We have set our oven profile such that there is the
minimum amount of preheat ramp, and we reflow in air. Could anyone provide
some help on how to deal with this? Any good resources for information,
abstracts, etc. that would help out?
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Date: Mon, 25 Feb 2002 19:39:02 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
praveen kumar manjeshwar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: praveen kumar manjeshwar <[log in to unmask]>
Subject: Upper and lower specification limits
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Dear All,
For a stencil of 5 mils, how does one arrive at the upper and lower
specification limits (USL and LSL) of the solder paste to be deposited? I
have read papers on stencil printing that have used the USL and LSL for
arriving at a stable process. Are there any industry standards to arrive at
the USL or LSL or these values have been arrived at based on experience?
Thanks and have a nice day.
Praveen
_________________________________________________________________
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Date: Mon, 25 Feb 2002 14:39:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Dendritic Growth...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Phil,
Do the photos show the top side of the capacitor or the bottom side
after it was removed? Do you know what cracked the capacitor? My first
reaction is that I think I'd be more concerned about the crack than the
dendrites.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Monday, February 25, 2002 12:53 PM
To: [log in to unmask]
Subject: Re: [TN] Dendritic Growth...
OK, here is the background on this particular dendrite growth:
It is a field failure unit and upon closer inspection, this dendrite
follows a crack in the capacitor from one termination to the other. In
my
opinion, the crack was there first, and was filled with contaminated
moisture while the cap had battery voltage (5V) across it, causing the
near
perfect dendrite to form along the walls of the crevice.
This CCA was produced on our no clean assembly line, of which the
cleanliness is monitored on each lot of boards produced. We believe
that
the solder flux residues are not related to this defect. The soldering
residues do not migrate to this area of the capacitor.
The condensation moisture alone would not seem to be enough to have
generated this dendritic growth so we are investigating other possible
contamination that may have been present such as moisture dripping off
of a
dirty shelf above, and also the component cleanliness itself. If the
crack
was there from the beginning then the contamination could have been as
well.
We have seen shorts across this capacitor before but usually only as
random
faint carbon tracks that are nowhere as defined as this one was.
This one is so perfect, it almost looks like an organic plant like a
small
fern.
This is an ongoing investigation so all comments are welcome and I will
provide an update at some point in the future.
Phil
At 06:51 AM 2/25/02 -0700, [log in to unmask] wrote:
>Doug,
>Isn't that known as the Mountain "Dew"lution Test?
>Dewey
>
> > -----Original Message-----
> > From: [log in to unmask] [SMTP:[log in to unmask]]
> > Sent: Monday, February 25, 2002 6:31 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Dendritic Growth...
> >
> > Sunny asks:
> > I'd like to know which type of Ion Chromatography can measure the
local
> > dot ionic cleanliness. Anyone can tell me which company produce
this
> > equipment?
> >
> > Doug Pauls responds:
> >
> > No company that I know of builds ion chromatography equipment to do
spot
> > ionic checks. IC equipment merely analyzes extract solutions. If
you
> > want
> > to measure localized ion concentrations, you have to develop a
localized
> > extraction technique. This might involve immersion of a portion of
the
> > assembly in extract solution, or building some time of
non-contaminating
> > enclosure around the area to be extracted. Once you can localize
the
> > extraction, collect the solution an analyze it with the IC equipment
> >
> >
------------------------------------------------------------------------
--
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text in
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[log in to unmask]:
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> > Search previous postings at: www.ipc.org > On-Line Resources &
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> > E-mail Archives
> > Please visit IPC web site http://www.ipc.org/html/forum.htm for
additional
> > information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700
> > ext.5315
> >
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> > -------
>
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Date: Mon, 25 Feb 2002 12:48:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: phil bavaro <[log in to unmask]>
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Phil,
I assume that CCA stands for Conformally Coated Assembly. If so what chemical family did the coating
fall into (acrylic, urethane, etc...)
How long was this device "in the field" and how much exposure did it receive to humidity above 80%?
BTW those "faint carbon tracks" are usually all that left when the dendrite vaporizes due to current
flow.
I will send you a copy of my paper "Avionics Systems, Reliability, and Harsh Environments". it should
provide some useful info for your investigation.
David A. Douthit
Manager
LoCan LLC
phil bavaro wrote:
> OK, here is the background on this particular dendrite growth:
>
> It is a field failure unit and upon closer inspection, this dendrite
> follows a crack in the capacitor from one termination to the other. In my
> opinion, the crack was there first, and was filled with contaminated
> moisture while the cap had battery voltage (5V) across it, causing the near
> perfect dendrite to form along the walls of the crevice.
>
> This CCA was produced on our no clean assembly line, of which the
> cleanliness is monitored on each lot of boards produced. We believe that
> the solder flux residues are not related to this defect. The soldering
> residues do not migrate to this area of the capacitor.
>
> The condensation moisture alone would not seem to be enough to have
> generated this dendritic growth so we are investigating other possible
> contamination that may have been present such as moisture dripping off of a
> dirty shelf above, and also the component cleanliness itself. If the crack
> was there from the beginning then the contamination could have been as well.
>
> We have seen shorts across this capacitor before but usually only as random
> faint carbon tracks that are nowhere as defined as this one was.
>
> This one is so perfect, it almost looks like an organic plant like a small
> fern.
>
> This is an ongoing investigation so all comments are welcome and I will
> provide an update at some point in the future.
>
> Phil
>
> At 06:51 AM 2/25/02 -0700, [log in to unmask] wrote:
> >Doug,
> >Isn't that known as the Mountain "Dew"lution Test?
> >Dewey
> >
> > > -----Original Message-----
> > > From: [log in to unmask] [SMTP:[log in to unmask]]
> > > Sent: Monday, February 25, 2002 6:31 AM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] Dendritic Growth...
> > >
> > > Sunny asks:
> > > I'd like to know which type of Ion Chromatography can measure the local
> > > dot ionic cleanliness. Anyone can tell me which company produce this
> > > equipment?
> > >
> > > Doug Pauls responds:
> > >
> > > No company that I know of builds ion chromatography equipment to do spot
> > > ionic checks. IC equipment merely analyzes extract solutions. If you
> > > want
> > > to measure localized ion concentrations, you have to develop a localized
> > > extraction technique. This might involve immersion of a portion of the
> > > assembly in extract solution, or building some time of non-contaminating
> > > enclosure around the area to be extracted. Once you can localize the
> > > extraction, collect the solution an analyze it with the IC equipment
> > >
> > > --------------------------------------------------------------------------
> > > -------
> > > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > > To unsubscribe, send a message to [log in to unmask] with following text in
> > > the BODY (NOT the subject field): SIGNOFF Technet
> > > To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
> > > SET Technet NOMAIL
> > > To receive ONE mailing per day of all the posts: send e-mail to
> > > [log in to unmask]: SET Technet Digest
> > > Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> > > E-mail Archives
> > > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > > ext.5315
> > > --------------------------------------------------------------------------
> > > -------
> >
> >---------------------------------------------------------------------------------
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>
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Date: Mon, 25 Feb 2002 13:49:34 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Phil! Good summary! I have been through this issue on a couple of
projects. Use a SEM and confirm what elements comprise the dendrite. Under
typical conditions there is usually not enough ionics running around on an
adequately cleaned assembly to promote the electromigration of the tin/lead
capacitor metallization. However, there will be enough ionic material
present on the assembly to form dendrites provided you: have condensation
moisture, an electrical bias (5 volts is enough) AND there is access to
the silver/palladium capacitor end cap metallization. The crack could
provide access to the Ag/Pd metallization (many capacitors have a Ag/Pd
metallization layer as part of the end cap finish stackup) - Ag is a much
more "migratory" metal than tin or lead. If the dendrite is comprised
mainly of tin/lead then you have more ionic contamination than you think,
if the dendrite is comprised of mainly Ag/Pd then time to stop getting
components with cracks. And if its neither of those two possibilities I'll
have to go get another Coke and really do some brainstorming. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
phil bavaro <[log in to unmask]>@ipc.org> on 02/25/2002 11:53:06 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to phil bavaro <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Dendritic Growth...
OK, here is the background on this particular dendrite growth:
It is a field failure unit and upon closer inspection, this dendrite
follows a crack in the capacitor from one termination to the other. In my
opinion, the crack was there first, and was filled with contaminated
moisture while the cap had battery voltage (5V) across it, causing the near
perfect dendrite to form along the walls of the crevice.
This CCA was produced on our no clean assembly line, of which the
cleanliness is monitored on each lot of boards produced. We believe that
the solder flux residues are not related to this defect. The soldering
residues do not migrate to this area of the capacitor.
The condensation moisture alone would not seem to be enough to have
generated this dendritic growth so we are investigating other possible
contamination that may have been present such as moisture dripping off of a
dirty shelf above, and also the component cleanliness itself. If the crack
was there from the beginning then the contamination could have been as
well.
We have seen shorts across this capacitor before but usually only as random
faint carbon tracks that are nowhere as defined as this one was.
This one is so perfect, it almost looks like an organic plant like a small
fern.
This is an ongoing investigation so all comments are welcome and I will
provide an update at some point in the future.
Phil
At 06:51 AM 2/25/02 -0700, [log in to unmask] wrote:
>Doug,
>Isn't that known as the Mountain "Dew"lution Test?
>Dewey
>
> > -----Original Message-----
> > From: [log in to unmask] [SMTP:[log in to unmask]]
> > Sent: Monday, February 25, 2002 6:31 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Dendritic Growth...
> >
> > Sunny asks:
> > I'd like to know which type of Ion Chromatography can measure the
local
> > dot ionic cleanliness. Anyone can tell me which company produce this
> > equipment?
> >
> > Doug Pauls responds:
> >
> > No company that I know of builds ion chromatography equipment to do
spot
> > ionic checks. IC equipment merely analyzes extract solutions. If you
> > want
> > to measure localized ion concentrations, you have to develop a
localized
> > extraction technique. This might involve immersion of a portion of the
> > assembly in extract solution, or building some time of
non-contaminating
> > enclosure around the area to be extracted. Once you can localize the
> > extraction, collect the solution an analyze it with the IC equipment
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Mon, 25 Feb 2002 15:02:07 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dendritic Growth...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_128.d16d362.29abf23f_boundary"
--part1_128.d16d362.29abf23f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
CCA also stands for Circuit Card Assembly....
Mike Sewell
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<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#ffffff"><FONT style="BACKGROUND-COLOR: #ffffff" SIZE=2>CCA also stands for Circuit Card Assembly....<BR>
<BR>
Mike Sewell</FONT></HTML>
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Date: Mon, 25 Feb 2002 15:22:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
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From: Bev Christian <[log in to unmask]>
Subject: Re: Solder Spatter
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Mark,
I know of no written resources about this, but I would recommend an extra
thorough cleaning of your reflow oven. It could be that what you are
getting is the redistribution of "captive" solder balls that have been
hanging around inside your oven. I wouldn't fool around with the reflow
profiles too much without first talking to your paste vendor.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Mark Stalcup [mailto:[log in to unmask]]
Sent: February 25, 2002 12:56 PM
To: [log in to unmask]
Subject: [TN] Solder Spatter
I am looking for some help concerning solder spatter. I manufacture
ceramic hybrids that have gold plated terminal blocks (50 mil square)
placed near the edge of the hybrid. We contiually see solder spatter
randomly located on the top of the blocks at at yield hit of anywhere from
2 to 30 percent. We have set our oven profile such that there is the
minimum amount of preheat ramp, and we reflow in air. Could anyone provide
some help on how to deal with this? Any good resources for information,
abstracts, etc. that would help out?
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Date: Mon, 25 Feb 2002 14:56:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
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From: Earl Moon <[log in to unmask]>
Subject: Re: Solder Spatter
X-To: [log in to unmask]
There are other issues as well. One very important is flux residue
entrapment in the overhead escape route to the vents. If excess residue
build up is apparent (several ways to determine) severe problems and effects
will present themselves as solder balling and poor solder joint formation.
MoonMan
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Date: Mon, 25 Feb 2002 15:22:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
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From: [log in to unmask]
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
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I assume that CCA stands for Conformally Coated Assembly. If so what
chemical family did the coating
fall into (acrylic, urethane, etc...)
*Usually, CCA stands for circuit card assembly, a synonym of printed wiring
assembly.
How long was this device "in the field" and how much exposure did it
receive to humidity above 80%?
*I seriously doubt this information would be recorded or known. Most units
don't come with build in humidity loggers.
BTW those "faint carbon tracks" are usually all that left when the dendrite
vaporizes due to current
flow.
*Sometimes. They can also be residual tin and lead of the dendrite
themselves.
Doug Pauls
Rockwell Collins
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Date: Mon, 25 Feb 2002 20:02:13 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
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From: David Douthit <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
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Doug,
*Usually, CCA stands for circuit card assembly, a synonym of printed wiring
assembly. Acronym overdose!
How long was this device "in the field" and how much exposure did it
receive to humidity above 80%?
*I seriously doubt this information would be recorded or known. Most units
don't come with build in humidity loggers.
Phil describes a possible "sheltered outdoor" enclosed unit. I wanted to use the ISO 9223 chart (see
below) to get an idea of the
type and duration of the environmental exposure. The possibility of dripping water from a rack above
indicates very high
humidity/condensation or a serious leakage problem.
David A. Douthit
Manager
LoCan LLC
Time of Wetness (80% or higher RH)
The Time of Wetness has been used as a criteria to quantify the
environment as follows:
Time of Wetness
Hours/Year % of Year Example of Occurrence
t1 <10 <0.1 Indoor air with climatic control
t2 10-250 0.1-3 Indoor air in normal rooms for living or working
conditions
t3 250-1000 3-10 Indoor air storage rooms
t4 1000-2500 10-30 Indoor air in some production rooms.
Outdoor air in cold zone, dry zone, parts of
temperate zone.
t5 2500-5500 30-60 Outdoor air in parts of temperate zone, parts of
warm zone. Indoor air in animal houses.
t6 >5500 >60 Outdoor air in tropical zone. Indoor air in
greenhouse.
[log in to unmask] wrote:
> I assume that CCA stands for Conformally Coated Assembly. If so what
> chemical family did the coating
> fall into (acrylic, urethane, etc...)
>
> *Usually, CCA stands for circuit card assembly, a synonym of printed wiring
> assembly.
>
> How long was this device "in the field" and how much exposure did it
> receive to humidity above 80%?
>
> *I seriously doubt this information would be recorded or known. Most units
> don't come with build in humidity loggers.
>
> BTW those "faint carbon tracks" are usually all that left when the dendrite
> vaporizes due to current
> flow.
>
> *Sometimes. They can also be residual tin and lead of the dendrite
> themselves.
>
> Doug Pauls
> Rockwell Collins
>
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Doug,
<p>*<i>Usually, CCA stands for circuit card assembly, a synonym of printed
wiring</i>
<br><i>assembly. </i>Acronym overdose!
<p><i>How long was this device "in the field" and how much exposure did
it</i>
<br><i>receive to humidity above 80%?</i>
<br><i>*I seriously doubt this information would be recorded or known.
Most units</i>
<br><i>don't come with build in humidity loggers.</i><i></i>
<p>Phil describes a possible "sheltered outdoor" enclosed unit. I wanted
to use the ISO 9223 chart (see below) to get an idea of the
<br>type and duration of the environmental exposure. The possibility of
dripping water from a rack above indicates very high
<br>humidity/condensation or a serious leakage problem.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>
Time of Wetness (80% or higher RH)
<br> The Time of
Wetness has been used as a criteria to quantify the
<br> environment
as follows:
<p>
Time of Wetness
<br> Hours/Year
% of Year Example of Occurrence
<p> t1 <10
<0.1 Indoor air with
climatic control
<p> t2 10-250
0.1-3 Indoor air in normal rooms for
living or working
<br>
conditions
<p> t3 250-1000
3-10 Indoor air storage rooms
<p> t4 1000-2500
10-30 Indoor air in some production
rooms.
<br>
Outdoor air in cold zone, dry zone, parts of
<br>
temperate zone.
<p> t5 2500-5500
30-60 Outdoor air in parts of temperate
zone, parts of
<br>
warm zone. Indoor air in animal houses.
<p> t6 >5500
>60 Outdoor air in tropical
zone. Indoor air in
<br>
greenhouse.
<p>
<br>
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE>I assume that CCA stands for Conformally Coated Assembly.
If so what
<br>chemical family did the coating
<br>fall into (acrylic, urethane, etc...)
<p>*Usually, CCA stands for circuit card assembly, a synonym of printed
wiring
<br>assembly.
<p>How long was this device "in the field" and how much exposure did it
<br>receive to humidity above 80%?
<p>*I seriously doubt this information would be recorded or known.
Most units
<br>don't come with build in humidity loggers.
<p>BTW those "faint carbon tracks" are usually all that left when the dendrite
<br>vaporizes due to current
<br>flow.
<p>*Sometimes. They can also be residual tin and lead of the dendrite
<br>themselves.
<p>Doug Pauls
<br>Rockwell Collins
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Date: Tue, 26 Feb 2002 04:09:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ivanoe Pedruzzi <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivanoe Pedruzzi <[log in to unmask]>
Subject: Intermetallic thickness
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I'm looking for information on intermetallic growth, for a good solder
joint, what is acceptable and what is unacceptable as being too low or too
high.
As far as I know, it depends on the elements and thermal cycles.
Assume: Cu-Sn63Pb37 and NiAu-Sn63Pb37,
90 seconds in liquidus, 2 thermal cycles.
How does the intermetallic thickness change if I had to change the paste
from eutectic to Ag2-Sn-Pb? (not even to mention lead-free paste)
Is there any formula that can help in undestanding what would be the
intermetallic thickness if I had to undergo another thermal cycle, or if I
had to change the liquidus time on my oven profile?
Any information will be very welcome.
Thanks,
Ivanoe
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Date: Tue, 26 Feb 2002 04:22:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Mak <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Mak <[log in to unmask]>
Subject: ESD safe solder sucker
I am looking for an ESD safe spring-loaded piston type solder sucker. Of
cource, this sucker shall neither generate static charges greater than 100V
on the tip and the handling body nor the push shaft when the push shaft is
pressed or released. Would appreciate if anyone could give some suggestions.
Best Regards
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Date: Tue, 26 Feb 2002 12:25:32 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Intermetallic thickness
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Ivanoe
Intermetallic Growth =3D Diffusion. Thus not a problem of cycling but of =
alloy, temperature and time.
Formulas: Klein Wassink
Thickness: In my opinion no minimum as long as there is an Intermetallic =
layer that indicates that alloying took place.
Change in thickness from Sn63Pb37 to Sn62Pb36Ag2 =3D marginal, within the =
statistical spread of measurements.
Best regards
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Tue, 26 Feb 2002 07:33:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: ESD safe solder sucker
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I am not aware of any tools, of the type you describe, that meet your
requirements. I think you would be able to find solder extractors by Pace,
Metcal, Air Vac, Hako and Ersa (to name a few) that would meet your
requirements but they are not the simple mechanical design you are seeking.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Mak
> Sent: Tuesday, February 26, 2002 5:23 AM
> To: [log in to unmask]
> Subject: [TN] ESD safe solder sucker
>
>
> I am looking for an ESD safe spring-loaded piston type solder sucker. Of
> cource, this sucker shall neither generate static charges greater
> than 100V
> on the tip and the handling body nor the push shaft when the push shaft is
> pressed or released. Would appreciate if anyone could give some
> suggestions.
>
> Best Regards
>
> ------------------------------------------------------------------
> ---------------
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>
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Date: Tue, 26 Feb 2002 07:36:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: ESD safe solder sucker
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More thinking produced this line of reasoning.
The act of triggering a device like the one you describe will generate an
electro-static charge. The problem is how to move the charge away from the
tip as it is generated.
I think you would have to ground the tool. If the case of the tool is
conductive and the tip is connected to the case, it should be possible to
ground the tool.
You should be able to check the tool using the same tool you use to check
voltage transients on the tip of your soldering Iron.
Good luck.
Guy Ramsey
Senior Technician / Instructor
www.aciusa.org
E-Mail: mailto:[log in to unmask]
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Mak
> Sent: Tuesday, February 26, 2002 5:23 AM
> To: [log in to unmask]
> Subject: [TN] ESD safe solder sucker
>
>
> I am looking for an ESD safe spring-loaded piston type solder sucker. Of
> cource, this sucker shall neither generate static charges greater
> than 100V
> on the tip and the handling body nor the push shaft when the push shaft is
> pressed or released. Would appreciate if anyone could give some
> suggestions.
>
> Best Regards
>
> ------------------------------------------------------------------
> ---------------
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>
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Date: Tue, 26 Feb 2002 08:25:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Antw: [TN] Intermetallic thickness
X-To: Guenter Grossmann <[log in to unmask]>
I've been reading IPC-D-279 with great interest. However, I get a little
more confused about thick IMC layers especially after reading the following:
IPC-D-279
A-3.3 CAVEAT 1 ? SOLDER JOINT QUALITY
The solder joint fatigue behavior and the resulting reliability prediction
equations. Eqs. A-1 through A-2, were determined from thermal cycling
results of solder joints that failed as a result of fracture of the solder,
albeit sometimes close to the IMC layers. For solder joints for which
layered structures are interposed between the base material and the solder
joints, these equations could be optimistic upper bounds if the interposed
layered structures become the ?weakest link? in the surface mount solder
attachments. Such layered structures could be: metallization layers that
have weak bonds to the underlying base material, or are weak themselves, or
dissolve essentially completely in the solder; oxide or contamination layers
preventing a proper metallurgical bond of the solder to the underlying
metal; brittle IMC layers TOO THICK due to too many or improperly long high
temperature processing steps.
Guenter, I'm sure you, Werner, and Dave H. and all others on this planet can
end my pain. I'm talking, of course, about the last, very long paragraph in
the caveat.
MoonMan
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Date: Tue, 26 Feb 2002 07:16:08 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dee Stover <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dee Stover <[log in to unmask]>
Subject: input on pressing cPCI connectors
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
We have recently designed a 6U board that has the J1 & J2 compact PCI
connectors on it. I used the manufacturers spec for the hole sizes and the
board shop fabricated within the tolerance and specification. The problem
is we can not get the connectors to actually press into the holes.
I would appreciate input from anyone who has some experience with these
connectors!
My understanding of the press tool was that it was nothing other than a
flat piece of metal in a bench press. Is that correct?
What finished hole sizes are being used? With all manufacturers? I have
noticed some dimensional differences in the drawings between Erni & FCI/Berg.
Can anyone give me an idea of what the press tools actually look like?
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
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Date: Tue, 26 Feb 2002 08:59:52 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: The board looks funny...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi,
We just received a new rev of a PWB in house. It has not been populated
yet. It looks like it has been built correctly - the right layer order,
connections, etc - but it looks different than the rest of our 4 layer
boards. Normally the traces on the inner layer that is closest to the
surface appear dark in colour and the deeper layer appears lighter. This
board is the opposite. The layer closest to the surface is light in colour
and the deeper layer is dark. Also, the FR4 seems much easier to see
through than usual.
Any thoughts or explanations for this?
Thanks for your time.
Genny Gibbard (mailto:[log in to unmask])
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Date: Tue, 26 Feb 2002 09:16:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charles Caswell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles Caswell <[log in to unmask]>
Subject: Re: input on pressing cPCI connectors
MIME-Version: 1.0
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We made a tool from two heavy bars of Alumininum with guide pins to =
align the connectors. We the use a 12 to shop press to install the =
connectors. I don't know the configuration of your connectors and boards =
but this has worked well for us.
Charles Caswell
Process Lead, PCB
Frontier Electronic Systems
-----Original Message-----
From: Dee Stover [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 8:16 AM
To: [log in to unmask]
Subject: [TN] input on pressing cPCI connectors
We have recently designed a 6U board that has the J1 & J2 compact PCI
connectors on it. I used the manufacturers spec for the hole sizes and =
the
board shop fabricated within the tolerance and specification. The =
problem
is we can not get the connectors to actually press into the holes.
I would appreciate input from anyone who has some experience with these
connectors!
My understanding of the press tool was that it was nothing other than a
flat piece of metal in a bench press. Is that correct?
What finished hole sizes are being used? With all manufacturers? I =
have
noticed some dimensional differences in the drawings between Erni & =
FCI/Berg.
Can anyone give me an idea of what the press tools actually look like?
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
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> E-mail Archives
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Date: Tue, 26 Feb 2002 09:21:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Keach Sasamori <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: Circuit Test
Mime-Version: 1.0
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Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e. =
100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary =
scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not =
adverse
to giving test point access where possible and where the design will not =
be
affected.
The boards we design here are also very complex, we mount SMDs on both =
sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried =
vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so =
these
cannot be used.
I could of course try to manually allocate access points, by increasing =
via
land where appropriate, or thickening and exposing traces where possible =
and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com=20
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
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=========================================================================
Date: Tue, 26 Feb 2002 16:27:29 +0100
Reply-To: Roland Jaquet <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roland Jaquet <[log in to unmask]>
Subject: Re: Dendritic Growth...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_00A0_01C1BEE2.7BD186E0"
C'est un message de format MIME en plusieurs parties.
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Hi Ladies and Gentlemen,
I too got bounced there.. and on a second attempt, was correctly sent to =
Steve's Homepage. Thank you Steve for those magnificent pictures - =
Nothing like it to show to a customer the danger he is facing ..=20
My customer desires to have his PWBs tested with high tension - but this =
is only going to make some smokes and won't be a proof about a Dendrit =
free PWB at all..=20
Very Best Regards
Roland
Http://www.PCBspecialist.com
Roland Jaquet - PCBspecialist - 14 ch. de Vers - CH-1228 Plan-Les-Ouates =
- Geneva - Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) =
+41-79-203-3723 - Fax +41-22-880-0409 - Company Viability - Technical =
Viability - Technology Choice - Yield Improvement - Company Strategy - =
Equipment Choice - Company Acquisition
EIPC Member
----- Message d'origine -----=20
De : [log in to unmask]
=C0 : [log in to unmask]
Envoy=E9 : lundi, 25. f=E9vrier 2002 02:04
Objet : Re: [TN] Dendritic Growth...
Hi, Steve,
Just tried looking up your site to see these beautiful dendrite =
pictures,
but found you have a bully muscling in on your link. Instead of =
getting to
your site I was beamed off to http://www.megago.com/l/, who then asked =
me
if I wanted to make them my home page. S.. Off! I thought, but I had =
to
type your site address manually to get to the pictures.
Anyone else had this problem?
Peter
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN =
Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] =
Dendritic Growth...
ORG>
02/23/02
02:49 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi Phil!
The pictures are up! Go to:
http://www.stevezeva.homstead.com
Those are the best examples of dendritic growth as I've ever seen! =
Where
did this take place? In a SIR chamber?
-Steve Gregory-
Hi Steve,
Thanks for offering to post my pictures of the dendritic growth. It =
will
be interesting to see what the consensus is although since I sent the
email
out I have been able to get my hands on the defect and take a close =
enough
look to answer the question. Let's put the picture up and see what =
the
responses are.
Phil
[This e-mail is confidential and may also be privileged. If you are =
not the
intended recipient, please delete it and notify us immediately; you =
should
not copy or use it for any purpose, nor disclose its contents to any =
other
person. Thank you.]
=
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1.8d
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in
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[log in to unmask]: SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to =
[log in to unmask]: SET Technet Digest
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Please visit IPC web site http://www.ipc.org/html/forum.htm for =
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=
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi Ladies and Gentlemen,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I too got bounced there.. and on a =
second attempt,=20
was correctly sent to Steve's Homepage. Thank you Steve for those =
magnificent=20
pictures - Nothing like it to show to a customer the danger he is facing =
..=20
</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>My customer desires to have his PWBs =
tested with=20
high tension - but this is only going to make some smokes and won't be a =
proof=20
about a Dendrit free PWB at all.. </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV>Very Best Regards</DIV>
<DIV> </DIV>
<DIV>Roland</DIV>
<DIV> </DIV>
<DIV><A=20
href=3D"http://www.PCBspecialist.com">Http://www.PCBspecialist.com</A><BR=
>Roland=20
Jaquet - PCBspecialist - 14 ch. de Vers - CH-1228 Plan-Les-Ouates - =
Geneva -=20
Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - =
Fax=20
+41-22-880-0409 - Company Viability - Technical Viability - Technology =
Choice -=20
Yield Improvement - Company Strategy - Equipment Choice - Company=20
Acquisition<BR>EIPC Member</DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Message d'origine ----- </DIV>
<DIV style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>De=20
:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>=C0 :</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Envoy=E9 :</B> lundi, 25. =
f=E9vrier 2002=20
02:04</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Objet :</B> Re: [TN] Dendritic=20
Growth...</DIV>
<DIV><BR></DIV>Hi, Steve,<BR><BR>Just tried looking up your site to =
see these=20
beautiful dendrite pictures,<BR>but found you have a bully muscling in =
on your=20
link. Instead of getting to<BR>your site I was beamed off to <A=20
href=3D"http://www.megago.com/l/">http://www.megago.com/l/</A>, who =
then asked=20
me<BR>if I wanted to make them my home page. S.. Off! I thought, but I =
had=20
to<BR>type your site address manually to get to the =
pictures.<BR><BR>Anyone=20
else had this=20
=
problem?<BR><BR>Peter<BR><BR><BR><BR><BR><BR> &nbs=
p;  =
; =20
<A=20
=
href=3D"mailto:SteveZeva@AOL">SteveZeva@AOL</A><BR> &nbs=
p;  =
; =20
=
.COM &nb=
sp; =20
To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR> =
&=
nbsp; =20
Sent=20
=
by: &nbs=
p;=20
cc: (bcc: DUNCAN Peter/Asst Prin=20
=
Engr/ST<BR> &n=
bsp; =20
=
TechNet =
=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
<<A=20
=
href=3D"mailto:TechNet@IPC">TechNet@IPC</A>.  =
; =20
Subject: Re: [TN] Dendritic=20
=
Growth...<BR> =
=20
=
ORG><BR><BR><BR> =
=20
=
02/23/02<BR> &=
nbsp; =20
02:49=20
=
AM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
=
Forum.";<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
SteveZeva<BR><BR><BR><BR><BR><BR><BR>Hi Phil!<BR><BR>The pictures are =
up! Go=20
to:<BR><BR><A=20
=
href=3D"http://www.stevezeva.homstead.com">http://www.stevezeva.homstead.=
com</A><BR><BR>Those=20
are the best examples of dendritic growth as I've ever seen! =
Where<BR>did this=20
take place? In a SIR chamber?<BR><BR>-Steve =
Gregory-<BR><BR><BR> Hi=20
Steve,<BR><BR> Thanks for offering to post my pictures of the =
dendritic=20
growth. It will<BR> be interesting to see what the =
consensus is=20
although since I sent the<BR> email<BR> out I have been able =
to get=20
my hands on the defect and take a close enough<BR><BR> look to =
answer the=20
question. Let's put the picture up and see what =
the<BR> responses=20
are.<BR><BR> Phil<BR><BR><BR><BR><BR><BR>[This e-mail is =
confidential and=20
may also be privileged. If you are not the<BR>intended recipient, =
please=20
delete it and notify us immediately; you should<BR>not copy or use it =
for any=20
purpose, nor disclose its contents to any other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
---------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
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&=20
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=========================================================================
Date: Tue, 26 Feb 2002 10:31:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ivanoe Pedruzzi <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivanoe Pedruzzi <[log in to unmask]>
Subject: Re: input on pressing cPCI connectors
X-To: Dee Stover <[log in to unmask]>,
Claudio Cordoni <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 7bit
Try surfing at www.tycoelectronics.com
(see for example:
http://catalog.tycoelectronics.com/TE/bin/TE.Connect?C=12177&F=10431&M=FINF&
N=4&LG=1&I=13&RQS=)
www.fciconnect.com
www.schmidtpresses.com
-----Original Message-----
From: Dee Stover [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 3:16 PM
To: [log in to unmask]
Subject: [TN] input on pressing cPCI connectors
We have recently designed a 6U board that has the J1 & J2 compact PCI
connectors on it. I used the manufacturers spec for the hole sizes and the
board shop fabricated within the tolerance and specification. The problem
is we can not get the connectors to actually press into the holes.
I would appreciate input from anyone who has some experience with these
connectors!
My understanding of the press tool was that it was nothing other than a
flat piece of metal in a bench press. Is that correct?
What finished hole sizes are being used? With all manufacturers? I have
noticed some dimensional differences in the drawings between Erni &
FCI/Berg.
Can anyone give me an idea of what the press tools actually look like?
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
----------------------------------------------------------------------------
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Date: Tue, 26 Feb 2002 11:01:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charles McMahon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles McMahon <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
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Hello Ginny:
I would suggest that the layer in question is not coated with oxide.
The next layer down (assuming it's a plane) did receive an oxide coat.
Charlie McMahon
Genny Gibbard wrote:
>Hi,
>We just received a new rev of a PWB in house. It has not been populated
>yet. It looks like it has been built correctly - the right layer order,
>connections, etc - but it looks different than the rest of our 4 layer
>boards. Normally the traces on the inner layer that is closest to the
>surface appear dark in colour and the deeper layer appears lighter. This
>board is the opposite. The layer closest to the surface is light in colour
>and the deeper layer is dark. Also, the FR4 seems much easier to see
>through than usual.
>
>Any thoughts or explanations for this?
>Thanks for your time.
>
>Genny Gibbard (mailto:[log in to unmask])
>
>---------------------------------------------------------------------------------
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>
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Date: Tue, 26 Feb 2002 09:53:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jim Jenkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Jenkins <[log in to unmask]>
Subject: No No-clean?
Hi everybody,
I was just approached by one of our engineers whose customer told her that
the Air Force has issued a directive disallowing the use of no-clean fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring to?
Thanks,
Jim
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Date: Tue, 26 Feb 2002 10:14:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: [log in to unmask]
Just depends on which layer you look at - one on the back of the top layer
or one more down
MoonMan
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Date: Tue, 26 Feb 2002 11:20:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: The board looks funny...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Genny,
Sounds like your board supplier is using various types of materials and
processes if you are recieving boards from the same supplier. As you
explained
if your inner cores are lighter in color they probably used an oxide
replacement
or double treat copper which will not give you the "black oxide" or very
dark
coloration. If your traces on the outside appear darker they may have
switched
to an adhesion promoter for the soldermask, but usually you would not see
this unless the board has ENIG, white tin, or other aggresive finish which
do in fact
attack the mask.
Tony Steinke
Process Engineer
AIT-Atlanta Inc.(multi-wire lives on)
[log in to unmask]
----- Original Message -----
From: Genny Gibbard <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 26, 2002 6:59 AM
Subject: [TN] The board looks funny...
> Hi,
> We just received a new rev of a PWB in house. It has not been populated
> yet. It looks like it has been built correctly - the right layer order,
> connections, etc - but it looks different than the rest of our 4 layer
> boards. Normally the traces on the inner layer that is closest to the
> surface appear dark in colour and the deeper layer appears lighter. This
> board is the opposite. The layer closest to the surface is light in
colour
> and the deeper layer is dark. Also, the FR4 seems much easier to see
> through than usual.
>
> Any thoughts or explanations for this?
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
>
> --------------------------------------------------------------------------
-------
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Date: Tue, 26 Feb 2002 11:20:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Fw: [TN] The board looks funny...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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----- Original Message -----
From: tony steinke <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 26, 2002 11:18 AM
Subject: Re: [TN] The board looks funny...
> Genny,
> Sounds like your board supplier is using various types of materials and
> processes if you are recieving boards from the same supplier. As you
> explained
> if your inner cores are lighter in color they probably used an oxide
> replacement
> or double treat copper which will not give you the "black oxide" or very
> dark
> coloration. If your traces on the outside appear darker they may have
> switched
> to an adhesion promoter for the soldermask, but usually you would not see
> this unless the board has ENIG, white tin, or other aggresive finish which
> do in fact
> attack the mask.
> Tony Steinke
> Process Engineer
> AIT-Atlanta Inc.(multi-wire lives on)
> [log in to unmask]
> ----- Original Message -----
> From: Genny Gibbard <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, February 26, 2002 6:59 AM
> Subject: [TN] The board looks funny...
>
>
> > Hi,
> > We just received a new rev of a PWB in house. It has not been populated
> > yet. It looks like it has been built correctly - the right layer order,
> > connections, etc - but it looks different than the rest of our 4 layer
> > boards. Normally the traces on the inner layer that is closest to the
> > surface appear dark in colour and the deeper layer appears lighter.
This
> > board is the opposite. The layer closest to the surface is light in
> colour
> > and the deeper layer is dark. Also, the FR4 seems much easier to see
> > through than usual.
> >
> > Any thoughts or explanations for this?
> > Thanks for your time.
> >
> > Genny Gibbard (mailto:[log in to unmask])
> >
>
> --------------------------------------------------------------------------
> -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
in
> > the BODY (NOT the subject field): SIGNOFF Technet
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>
> E-mail Archives
> > Please visit IPC web site http://www.ipc.org/html/forum.htm for
additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
>
> --------------------------------------------------------------------------
> -------
>
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Date: Tue, 26 Feb 2002 11:20:37 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Fw: [TN] The board looks funny...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
----- Original Message -----
From: tony steinke <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 26, 2002 11:19 AM
Subject: Fw: [TN] The board looks funny...
>
> ----- Original Message -----
> From: tony steinke <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, February 26, 2002 11:18 AM
> Subject: Re: [TN] The board looks funny...
>
>
> > Genny,
> > Sounds like your board supplier is using various types of materials and
> > processes if you are recieving boards from the same supplier. As you
> > explained
> > if your inner cores are lighter in color they probably used an oxide
> > replacement
> > or double treat copper which will not give you the "black oxide" or very
> > dark
> > coloration. If your traces on the outside appear darker they may have
> > switched
> > to an adhesion promoter for the soldermask, but usually you would not
see
> > this unless the board has ENIG, white tin, or other aggresive finish
which
> > do in fact
> > attack the mask.
> > Tony Steinke
> > Process Engineer
> > AIT-Atlanta Inc.(multi-wire lives on)
> > [log in to unmask]
> > ----- Original Message -----
> > From: Genny Gibbard <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Tuesday, February 26, 2002 6:59 AM
> > Subject: [TN] The board looks funny...
> >
> >
> > > Hi,
> > > We just received a new rev of a PWB in house. It has not been
populated
> > > yet. It looks like it has been built correctly - the right layer
order,
> > > connections, etc - but it looks different than the rest of our 4 layer
> > > boards. Normally the traces on the inner layer that is closest to the
> > > surface appear dark in colour and the deeper layer appears lighter.
> This
> > > board is the opposite. The layer closest to the surface is light in
> > colour
> > > and the deeper layer is dark. Also, the FR4 seems much easier to see
> > > through than usual.
> > >
> > > Any thoughts or explanations for this?
> > > Thanks for your time.
> > >
> > > Genny Gibbard (mailto:[log in to unmask])
> > >
> >
>
> --------------------------------------------------------------------------
> > -------
> > > Technet Mail List provided as a free service by IPC using LISTSERV
1.8d
> > > To unsubscribe, send a message to [log in to unmask] with following text
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> >
> > E-mail Archives
> > > Please visit IPC web site http://www.ipc.org/html/forum.htm for
> additional
> > > information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700
> > ext.5315
> >
>
> --------------------------------------------------------------------------
> > -------
> >
>
>
>
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Date: Tue, 26 Feb 2002 10:17:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Circuit Test
X-To: [log in to unmask]
You face the problem we all do. I'm spending the day reading IPC stuff and,
as an example, 279 speaks to this in several places. Page 40, sections 8.1
and 8.2 eximplify the rhetoric and present the facts buy no solutions.
MoonMan
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Date: Tue, 26 Feb 2002 11:27:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: input on pressing cPCI connectors
X-To: Dee Stover <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I've found that the scrap developed in this sort of part is pointless if
wave soldering is required anyways. We used only two of the pins for
retention (recommended press-fit), allowing the wave to do the rest of the
work (oversize).
This was in higher power connector, where a damned worm-screw or vise was
necessary to get insertion half the time. Manual, expensive and error-prone.
Only really justified in no-solder assembly (wish on!).
RL
----- Original Message -----
From: Dee Stover <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 26, 2002 9:16 AM
Subject: [TN] input on pressing cPCI connectors
> We have recently designed a 6U board that has the J1 & J2 compact PCI
> connectors on it. I used the manufacturers spec for the hole sizes and
the
> board shop fabricated within the tolerance and specification. The problem
> is we can not get the connectors to actually press into the holes.
>
> I would appreciate input from anyone who has some experience with these
> connectors!
>
> My understanding of the press tool was that it was nothing other than a
> flat piece of metal in a bench press. Is that correct?
>
> What finished hole sizes are being used? With all manufacturers? I have
> noticed some dimensional differences in the drawings between Erni &
FCI/Berg.
>
> Can anyone give me an idea of what the press tools actually look like?
>
> TIA
>
>
> Dee Stover [log in to unmask]
> Associate Technician Design
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520-318-8489
> FAX 520-318-8303
>
> --------------------------------------------------------------------------
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>
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=========================================================================
Date: Tue, 26 Feb 2002 09:24:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: The board looks funny...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Sometimes a change in oxide type or a switch to double treat will cause this
appearance. Ask your supplier.
Rick
-----Original Message-----
From: Genny Gibbard [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 8:00 AM
To: [log in to unmask]
Subject: [TN] The board looks funny...
Hi,
We just received a new rev of a PWB in house. It has not been populated
yet. It looks like it has been built correctly - the right layer order,
connections, etc - but it looks different than the rest of our 4 layer
boards. Normally the traces on the inner layer that is closest to the
surface appear dark in colour and the deeper layer appears lighter. This
board is the opposite. The layer closest to the surface is light in colour
and the deeper layer is dark. Also, the FR4 seems much easier to see
through than usual.
Any thoughts or explanations for this?
Thanks for your time.
Genny Gibbard (mailto:[log in to unmask])
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Date: Tue, 26 Feb 2002 10:36:07 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: The board looks funny...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
That is kind of what I was wondering, Moonman.
Does it appear that our board manufacturers usually etch the copper on the
back of the top sheet of FR4, and instead this manufacturer etched it on the
top of the inner sheet of FR4, so we are seeing the other side of the
copper? As far as I figure, the layer spacing would be effectively the
same, so can anyone see any problems with one type of construction over the
other?
The deeper layer is dark like the close layer usually appears, so to me it
looks like the same processes were used but both inner layers were etched on
the inner sheet of FR4, versus etching them on the inside of the outer two
sheets.
Or, considering the other answer I received regarding no oxide coating, or
double treatment: are these bad things?
Thanks.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: February 26, 2002 10:14 AM
To: [log in to unmask]; [log in to unmask]
Subject: Re: The board looks funny...
Just depends on which layer you look at - one on the back of the top layer
or one more down
MoonMan
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Date: Tue, 26 Feb 2002 10:59:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Paul Brionez <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Brionez <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="------------EC0E54AD785D1D46025DD431"
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Genny
It sounds like your PCB was built with two B stages with FR4 between the copper layers and the prepreg
between layers 2-3.
Similar to this Most 4-layers
1- cu 1- cu
FR-4 pre-preg
2- cu 2- cu
pre-preg Filler FR-4
3- cu 3 - cu
FR-4 pre-preg
4- cu 4 - cu
Genny Gibbard wrote:
> Hi,
> We just received a new rev of a PWB in house. It has not been populated
> yet. It looks like it has been built correctly - the right layer order,
> connections, etc - but it looks different than the rest of our 4 layer
> boards. Normally the traces on the inner layer that is closest to the
> surface appear dark in colour and the deeper layer appears lighter. This
> board is the opposite. The layer closest to the surface is light in colour
> and the deeper layer is dark. Also, the FR4 seems much easier to see
> through than usual.
>
> Any thoughts or explanations for this?
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
>
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Date: Tue, 26 Feb 2002 12:19:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: The board looks funny...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_115.d34b43e.29ad1d9d_boundary"
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Genny,
They may have also used double treat copper which would negate the use of an
additional oxide coating.
Regards,
Gary
--part1_115.d34b43e.29ad1d9d_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT COLOR="#8000ff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>Genny,<BR>
<BR>
They may have also used double treat copper which would negate the use of an additional oxide coating.<BR>
<BR>
Regards,<BR>
<BR>
Gary</B></I></FONT></HTML>
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Date: Tue, 26 Feb 2002 09:27:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: input on pressing cPCI connectors
X-To: Dee Stover <[log in to unmask]>
In-Reply-To: <5.1.0.14.0.20020226070244.01cfb668@orion>
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Dee,
On some early designs done by one of our customers, they found similar
issues. Laying out the board for FCI wouldn't allow AMP connectors to
be pressed in. They ended up using the AMP layout and we haven't had
issues since. I believe AMP and ERNI are virtually identical in spec.
In our experience, tooling is critical, especially underboard support
and even pressure on entire connector. You might check out the AMP site
for documents on their tooling and installation. They have quite a bit
of information available on this.
Regards,
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dee Stover
Sent: Tuesday, February 26, 2002 6:16 AM
To: [log in to unmask]
Subject: [TN] input on pressing cPCI connectors
We have recently designed a 6U board that has the J1 & J2 compact PCI
connectors on it. I used the manufacturers spec for the hole sizes and
the board shop fabricated within the tolerance and specification. The
problem is we can not get the connectors to actually press into the
holes.
I would appreciate input from anyone who has some experience with these
connectors!
My understanding of the press tool was that it was nothing other than a
flat piece of metal in a bench press. Is that correct?
What finished hole sizes are being used? With all manufacturers? I
have noticed some dimensional differences in the drawings between Erni &
FCI/Berg.
Can anyone give me an idea of what the press tools actually look like?
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
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Date: Tue, 26 Feb 2002 11:37:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: [log in to unmask]
Like Paul said, there are two ways to effect the structure. I haven't
designed, built, or used 4 layer boards in years. Most all 4 layer boards,
in ancient times, were core laminated wherein two double sided "boards" were
laminated together with whatever amount of preg was needed to effect the
required thickness. Mass lamination techniques were, and maybe still, used
extensively using core lamination after printing and etching the inner layer
details.
Most all, if not all, "sophisticated" MLB's are foil laminated with preg
facing the outer most layers with thin core materials making up the rest as
printed and etched details.
Everyone else pointed to oxides and double treat foils. They would impact
you visually as pointed out.
In any event, your boards should be reliable and functional unless your
supplier looses the recipe for effective process management.
Enjoy Genny,
MoonMan
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Date: Tue, 26 Feb 2002 11:55:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: The board looks funny...
MIME-Version: 1.0
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Thanks Paul. I believe you have hit the nail on the head. This may seem
like an elementary question, but is it better to spec more pre-preg, like
your standard second sketch, or go with your first sketch?
I guess I don't have a good concept of what prepreg is or when it should be
used. What I think I know about it is that it is not fully cured FR4 and
that the pressing of the layers together is what finishes the cure process.
I think I believed that it was sort of the 'glue' that held a multilayer
board together and thought it should be placed in the middle.
We have only just started to try to be more specific in what materials we
spec, and before, we trusted the manufacturer to figure out what to use. I
believe we probably used to get a construction based exactly on your second
sketch. But this board is built like your first sketch, which, amazingly
enough, was what we spec'd in our brand new revised readme file.
It is comforting to know they read my readme file...even if I don't know
what I am talking about.
Thanks. Any good sources of info on what pre-preg is and where it should be
used would be much appreciated...
-----Original Message-----
From: Paul Brionez [mailto:[log in to unmask]]
Sent: February 26, 2002 11:00 AM
To: TechNet E-Mail Forum.; Genny Gibbard
Subject: Re: [TN] The board looks funny...
Genny
It sounds like your PCB was built with two B stages with FR4 between the
copper layers and the prepreg
between layers 2-3.
Similar to this Most 4-layers
1- cu 1- cu
FR-4 pre-preg
2- cu 2- cu
pre-preg Filler FR-4
3- cu 3 - cu
FR-4 pre-preg
4- cu 4 - cu
Genny Gibbard wrote:
> Hi,
> We just received a new rev of a PWB in house. It has not been populated
> yet. It looks like it has been built correctly - the right layer order,
> connections, etc - but it looks different than the rest of our 4 layer
> boards. Normally the traces on the inner layer that is closest to the
> surface appear dark in colour and the deeper layer appears lighter. This
> board is the opposite. The layer closest to the surface is light in
colour
> and the deeper layer is dark. Also, the FR4 seems much easier to see
> through than usual.
>
> Any thoughts or explanations for this?
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
>
>
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Date: Tue, 26 Feb 2002 11:17:16 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Lucas Paul-R32425 <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lucas Paul-R32425 <[log in to unmask]>
Subject: Re: Circuit Test
X-To: Keach Sasamori <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Alan,
We too have the same situation as you do in regards to ICT of complex PWA's. Our design engineers have not included test points, wide traces or anything else that would allow for the in circuit testing of our boards. Our boards are very dense in component population and use a mixture of fine pitch, SMD and thru hole components on them. They are 10"X18" boards that have 8 to 12 layers. As big as they are there is just no room to fit any test points on there. That's ok because, the designers have no intentions of going back and re-routing the boards to allow for this.
So we have had to compensate by finding an assembly house that has AOI. They do 100% inspection on every board they assemble. When we receive the boards we add several more components by hand and then we do a visual inspection. After that we use a meter or curve tracer to check the power planes for shorts between them and ground. Finally comes what we call the "smoke test". This is were the board is plugged into a test chassis and turned on. You will soon find out if you still have any shorts are reversed components that you missed. Believe it or not this has been successful for us in getting boards built and working. ICT is obviously much faster in testing the boards, but not always more accurate or successful(Test programs are never complete and constantly changing). One of the big reason this works for us is because we have low volumes and a high mix(ICT is expensive for low volume, very complex boards).
You have to balance the cost of adding ICT into your designs and to your assembly costs against the cost of visual inspection and more labor intensive test procedures. For us it was about the same cost and the quality has not suffered by omitting ICT.
Hope this helps,
Paul
-----Original Message-----
From: Keach Sasamori [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 8:21 AM
To: [log in to unmask]
Subject: [TN] Circuit Test
Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e. 100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not adverse
to giving test point access where possible and where the design will not be
affected.
The boards we design here are also very complex, we mount SMDs on both sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so these
cannot be used.
I could of course try to manually allocate access points, by increasing via
land where appropriate, or thickening and exposing traces where possible and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
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Date: Tue, 26 Feb 2002 12:51:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No No-clean?
X-To: [log in to unmask]
MIME-Version: 1.0
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Jim Jenkins nervously writes:
I was just approached by one of our engineers whose customer told her that
the Air Force has issued a directive disallowing the use of no-clean fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring
to?
Doug Pauls, ever calm and collected, responds.
Jim, this is the first I have heard of anything along these lines and we
build LOTS of stuff for the Air Force. On the other hand, we clean our
hardware, so they may not feel the need to talk to us on this issue. I
would think that levying such a requirement on *existing* hardware would be
next to impossible since you affect thousands of contracts. You might want
to determine if this is a requirement for NEW designs. Since many
companies do manufactur hi-rel equipment with no-clean processes, I would
be curious as to the technical rationale for such a requirement.
Doug Pauls
Rockwell Collins
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Date: Tue, 26 Feb 2002 14:00:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Roger Stoops <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Stoops <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
(More wood to the bonfire...)
In addition to the other comments, to expand on what Moonmeister said,
possible that your vendor is using foil construction now versus core
construction. For 4-layer boards, foil construction starts with a core
board already processed and adds laminate/prepreg to the outside with copper
foil added last, then processed. Core construction uses 2 cores (Layers 1 &
2, then Layers 3 & 4) with laminate/prepreg in between.
Does the master (or drill) drawing define board construction, or is it left
to the vendor's discretion?
Roger M. Stoops, CID [log in to unmask]
TRIMBLE NAVIGATION LLC
-----Original Message-----
From: Genny Gibbard [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 11:36 AM
To: [log in to unmask]
Subject: Re: [TN] The board looks funny...
That is kind of what I was wondering, Moonman.
Does it appear that our board manufacturers usually etch the copper on the
back of the top sheet of FR4, and instead this manufacturer etched it on the
top of the inner sheet of FR4, so we are seeing the other side of the
copper? As far as I figure, the layer spacing would be effectively the
same, so can anyone see any problems with one type of construction over the
other?
The deeper layer is dark like the close layer usually appears, so to me it
looks like the same processes were used but both inner layers were etched on
the inner sheet of FR4, versus etching them on the inside of the outer two
sheets.
Or, considering the other answer I received regarding no oxide coating, or
double treatment: are these bad things?
Thanks.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: February 26, 2002 10:14 AM
To: [log in to unmask]; [log in to unmask]
Subject: Re: The board looks funny...
Just depends on which layer you look at - one on the back of the top layer
or one more down
MoonMan
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Date: Tue, 26 Feb 2002 14:18:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Jim Jenkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Jim,
This sounds like a dissident to the DOD Acquistion Reform Policy instituted
back in the mid 90s that did away with the "how to" spec's/std's (i.e.
MIL-E-5400, MIL-STD-275, MIL-P-55110 and MIL-STD-2000) and relies upon the
performance specification to determine the product requirements. In other
words don't tell the manufacturer how to
design/build/qualify/produce/warrant equipment because it costs too much,
tell her/him what you want the equipment to do, for how long, in what
environment and all with minimal risk and a reduced cost -- yeah right!
If I were a betting man, I would say that an Air Force Program Manager (not
the whole Air Force) has been bitten by the misuse of no-clean chemistry on
a previous program or contract. So, in a sense, this may be the second time
and it is not going to be shame on the PM.
This reminds me of years gone by while with the Navy -- after MIL-STD-2000
was cancelled, NAWCADLKE-MISC-05-MT-0002 was developed and released by the
same Navy folks (I'm one of the guilty) who supported the SOLD program.
This document found its way into contracts and product specifications not
without notice but there was little the bigger DOD folks could do.
Remember, you get what you pay for and if that Air Force PM wants no-clean,
he probably has a damn good reason why.
Steve Sauer
Northrop Grumman, Xetron
-----Original Message-----
From: Jim Jenkins
...the Air Force has issued a directive disallowing the use of no-clean
fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring
to?
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Date: Tue, 26 Feb 2002 14:30:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Raymond <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: Circuit Test
X-To: Lucas Paul-R32425 <[log in to unmask]>
In-Reply-To: <[log in to unmask] com>
Mime-Version: 1.0
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You should take a look at the Agilent web site
(http://www.ate.agilent.com/emt/index.shtml)... they look at testing issues
a a combination of AOI, AXI (xray), and of course ICT... with each of the 3
overlapping each other capabilities. We run their AXI with our ICT on
similar boards that have limited conventional test access.
At 11:17 AM 02/26/2002 -0700, you wrote:
>Alan,
>
>We too have the same situation as you do in regards to ICT of complex
>PWA's. Our design engineers have not included test points, wide traces or
>anything else that would allow for the in circuit testing of our boards.
>Our boards are very dense in component population and use a mixture of
>fine pitch, SMD and thru hole components on them. They are 10"X18" boards
>that have 8 to 12 layers. As big as they are there is just no room to fit
>any test points on there. That's ok because, the designers have no
>intentions of going back and re-routing the boards to allow for this.
>
>So we have had to compensate by finding an assembly house that has AOI.
>They do 100% inspection on every board they assemble. When we receive the
>boards we add several more components by hand and then we do a visual
>inspection. After that we use a meter or curve tracer to check the power
>planes for shorts between them and ground. Finally comes what we call the
>"smoke test". This is were the board is plugged into a test chassis and
>turned on. You will soon find out if you still have any shorts are
>reversed components that you missed. Believe it or not this has been
>successful for us in getting boards built and working. ICT is obviously
>much faster in testing the boards, but not always more accurate or
>successful(Test programs are never complete and constantly changing). One
>of the big reason this works for us is because we have low volumes and a
>high mix(ICT is expensive for low volume, very complex boards).
>
>You have to balance the cost of adding ICT into your designs and to your
>assembly costs against the cost of visual inspection and more labor
>intensive test procedures. For us it was about the same cost and the
>quality has not suffered by omitting ICT.
>
>Hope this helps,
>
>Paul
>
>-----Original Message-----
>From: Keach Sasamori [mailto:[log in to unmask]]
>Sent: Tuesday, February 26, 2002 8:21 AM
>To: [log in to unmask]
>Subject: [TN] Circuit Test
>
>
>Forwarding for Alan Groves:
>
> >>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
>Hi, I have not used the forum before but am currently at the centre of an
>internal company clash, and would appreciate any help on the issue below.
>
>My problem involves In Circuit Test ;-
>Our Logistics department here (which includes production, test and
>deployment) are demanding quite strongly that ICT be done on each PWB we
>design, and that every signal and every component value be tested, i.e. 100%
>test point access on traces (even N/Cs).
>The Engineers are not quite so keen as most have used JTAG and Boundary scan
>etc to evaluate the devices they deem critical. They are also worried (and
>rightly so) about the effect that test points may have on traces with
>controlled impedance, or those on critical timing paths, but are not adverse
>to giving test point access where possible and where the design will not be
>affected.
>The boards we design here are also very complex, we mount SMDs on both sides
>and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
>boards are also very dense with real estate at an absolute priority such
>that we use the smallest devices available. Currently we have 0,8mm pitch
>uBGAs whose routing must be resolved vertically, i.e. blind and buried vias,
>with obvious drawbacks for ICT.
>We have in the past used the Specctra autorouter to allocate test point
>access but the best result so far is about 80% (of course I could use bad
>placement to improve this!), and even here we used the smallest possible
>access points 0.03" on the smallest possible grid 0.05". On some boards it
>is below 50% access. Our usual via holes only have land of 0.024", so these
>cannot be used.
>I could of course try to manually allocate access points, by increasing via
>land where appropriate, or thickening and exposing traces where possible and
>deploying all other tricks I can, but the time and effort here would be
>enormous, and other projects may suffer as a result.
>
>Any advise or knowledge that can be offered here would be most welcome.
>Is this problem common to other companies?
>How is the Industry thinking about ICT at the moment?
>Are there better autorouters?
>Are there ICT houses that can use smaller nodes on tighter grids?
>Is there new technology just around the corner?
>Etc Etc.
>
>With many thanks in advance, and regards,
>
>Alan Groves CID,
>Technical Services (D.O.) Team Leader.
>Spectel , 21 Stillorgan Ind. Park, Stillorgan,
>Co. Dublin. Ireland.
>Phone: 353 907 62803
>Fax: 353 1 2953740
>Email: [log in to unmask]
>Internet: www.spectel.com
>
>Or Via :
>Spectel, Inc.
>200 Minuteman Road
>Andover, Massachusetts 01810 USA
>PH: 1.978.552.6260
>FX: 1.978.552.6250
>
>---------------------------------------------------------------------------------
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>
>---------------------------------------------------------------------------------
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----------------------------------------------------------------
Bill Raymond, VP of Technology Development
Trenton Technology Inc.
1001 Broad Street
Utica New York 13501
Phone (315) 797-7534
Fax (315) 797-7159
----------------------------------------------------------------
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=========================================================================
Date: Tue, 26 Feb 2002 14:38:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
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Depends on which surface is an original bond and which surface is laminated
in process.
Relative opacity could just be prepreg type, processing requirements. Color
largely irrelevant.
It's a sign that their process has changed, though, so you'd best be on your
guard for more serious deviations.
RL
----- Original Message -----
From: Genny Gibbard <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 26, 2002 9:59 AM
Subject: [TN] The board looks funny...
> Hi,
> We just received a new rev of a PWB in house. It has not been populated
> yet. It looks like it has been built correctly - the right layer order,
> connections, etc - but it looks different than the rest of our 4 layer
> boards. Normally the traces on the inner layer that is closest to the
> surface appear dark in colour and the deeper layer appears lighter. This
> board is the opposite. The layer closest to the surface is light in
colour
> and the deeper layer is dark. Also, the FR4 seems much easier to see
> through than usual.
>
> Any thoughts or explanations for this?
> Thanks for your time.
>
> Genny Gibbard (mailto:[log in to unmask])
>
> --------------------------------------------------------------------------
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>
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Date: Wed, 27 Feb 2002 08:44:46 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Michael Bell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Re: No No-clean?
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Jim,
Not really an answer, but I am curious to this directive??? Do you have any
idea why the Air Force would disallow such no-clean products. I would have
thought it was more of an issue that some contractors are applying very
aggressive rosin based fluxes to their boards, to the point of having to
clean the residues off. I am a firm believer in no-clean products, I have
always used no-clean wave solder fluxes, and re-work fluxes, and I would
never even consider using fluxes that require cleaning. Our process window
fits the no-clean directive, and I am experiencing perfect solder results.
Surely, the situation of applying possibly corrosive fluxes to a board and
then having to clean these boards would pose more of a threat to
military/air force applications????
Curious,
Mike
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, 27 February 2002 07:51
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Jim Jenkins nervously writes:
I was just approached by one of our engineers whose customer told her that
the Air Force has issued a directive disallowing the use of no-clean fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring
to?
Doug Pauls, ever calm and collected, responds.
Jim, this is the first I have heard of anything along these lines and we
build LOTS of stuff for the Air Force. On the other hand, we clean our
hardware, so they may not feel the need to talk to us on this issue. I
would think that levying such a requirement on *existing* hardware would be
next to impossible since you affect thousands of contracts. You might want
to determine if this is a requirement for NEW designs. Since many
companies do manufactur hi-rel equipment with no-clean processes, I would
be curious as to the technical rationale for such a requirement.
Doug Pauls
Rockwell Collins
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Date: Tue, 26 Feb 2002 13:10:40 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: No No-clean?
X-To: "Sauer, Steven T." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------F6E10CD600203401E81D11E2"
--------------F6E10CD600203401E81D11E2
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Steve,
"relies upon the performance specification to determine the product requirements. In other
words don't tell the manufacturer how to
design/build/qualify/produce/warrant equipment because it costs too much,
tell her/him what you want the equipment to do, for how long, in what
environment and all with minimal risk and a reduced cost --"
Have you heard of this DoD document: DoD 5000.2-R Effective date 06/2001
MANDATORY PROCEDURES FOR MAJOR DEFENSE
ACQUISITION PROGRAMS (MDAPS) AND
MAJOR AUTOMATED INFORMATION SYSTEM (MAIS) ACQUISITION PROGRAMS
C3.2.3.2.2.5. T&E on commercial and non-developmental items shall ensure performance,
operational effectiveness, and operational suitability for the military application in
the military environment, regardless of the manner of procurement.
Test planning for these items shall recognize commercial testing and experience,
but nonetheless determine the appropriate DT&E(Developmental Test And Evaluation),
OT&E(Operational Test and Evaluation), and LFT&E(Live Fire Test and Evaluation)
needed to assure effective performance in the intended operational environment.
David A. Douthit
Manager
LoCan LLC
"Sauer, Steven T." wrote:
> Hi Jim,
> This sounds like a dissident to the DOD Acquistion Reform Policy instituted
> back in the mid 90s that did away with the "how to" spec's/std's (i.e.
> MIL-E-5400, MIL-STD-275, MIL-P-55110 and MIL-STD-2000) and relies upon the
> performance specification to determine the product requirements. In other
> words don't tell the manufacturer how to
> design/build/qualify/produce/warrant equipment because it costs too much,
> tell her/him what you want the equipment to do, for how long, in what
> environment and all with minimal risk and a reduced cost -- yeah right!
> If I were a betting man, I would say that an Air Force Program Manager (not
> the whole Air Force) has been bitten by the misuse of no-clean chemistry on
> a previous program or contract. So, in a sense, this may be the second time
> and it is not going to be shame on the PM.
> This reminds me of years gone by while with the Navy -- after MIL-STD-2000
> was cancelled, NAWCADLKE-MISC-05-MT-0002 was developed and released by the
> same Navy folks (I'm one of the guilty) who supported the SOLD program.
> This document found its way into contracts and product specifications not
> without notice but there was little the bigger DOD folks could do.
> Remember, you get what you pay for and if that Air Force PM wants no-clean,
> he probably has a damn good reason why.
>
> Steve Sauer
> Northrop Grumman, Xetron
>
> -----Original Message-----
> From: Jim Jenkins
>
> ...the Air Force has issued a directive disallowing the use of no-clean
> fluxes
> on any of their hardware. The customer is flowing down that requirement to
> us. Do any of you know of this directive or what they could be referring
> to?
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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--------------F6E10CD600203401E81D11E2
Content-Type: text/html; charset=us-ascii
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Steve,
<p><i>"relies upon the performance specification to determine the product
requirements. In other</i>
<br><i>words don't tell the manufacturer how to</i>
<br><i>design/build/qualify/produce/warrant equipment because it costs
too much,</i>
<br><i>tell her/him what you want the equipment to do, for how long, in
what</i>
<br><i>environment and all with minimal risk and a reduced cost --"</i><i></i>
<p>Have you heard of this DoD document: DoD 5000.2-R Effective
date 06/2001
<p>MANDATORY PROCEDURES FOR MAJOR DEFENSE
<br>ACQUISITION PROGRAMS (MDAPS) AND
<br>MAJOR AUTOMATED INFORMATION SYSTEM (MAIS) ACQUISITION PROGRAMS
<p>C3.2.3.2.2.5. T&E on commercial and non-developmental items
shall ensure performance,
<br>operational effectiveness, and operational suitability for the military
application in
<br>the military environment, regardless of the manner of procurement.
<br>Test planning for these items shall recognize commercial testing and
experience,
<br>but nonetheless determine the appropriate DT&E(Developmental Test
And Evaluation),
<br>OT&E(Operational Test and Evaluation), and LFT&E(Live Fire
Test and Evaluation)
<br>needed to assure effective performance in the intended operational
environment.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC<i></i>
<p>"Sauer, Steven T." wrote:
<blockquote TYPE=CITE>Hi Jim,
<br>This sounds like a dissident to the DOD Acquistion Reform Policy instituted
<br>back in the mid 90s that did away with the "how to" spec's/std's (i.e.
<br>MIL-E-5400, MIL-STD-275, MIL-P-55110 and MIL-STD-2000) and relies upon
the
<br>performance specification to determine the product requirements.
In other
<br>words don't tell the manufacturer how to
<br>design/build/qualify/produce/warrant equipment because it costs too
much,
<br>tell her/him what you want the equipment to do, for how long, in what
<br>environment and all with minimal risk and a reduced cost -- yeah right!
<br>If I were a betting man, I would say that an Air Force Program Manager
(not
<br>the whole Air Force) has been bitten by the misuse of no-clean chemistry
on
<br>a previous program or contract. So, in a sense, this may be the
second time
<br>and it is not going to be shame on the PM.
<br>This reminds me of years gone by while with the Navy -- after MIL-STD-2000
<br>was cancelled, NAWCADLKE-MISC-05-MT-0002 was developed and released
by the
<br>same Navy folks (I'm one of the guilty) who supported the SOLD program.
<br>This document found its way into contracts and product specifications
not
<br>without notice but there was little the bigger DOD folks could do.
<br>Remember, you get what you pay for and if that Air Force PM wants no-clean,
<br>he probably has a damn good reason why.
<p>Steve Sauer
<br>Northrop Grumman, Xetron
<p>-----Original Message-----
<br>From: Jim Jenkins
<p>...the Air Force has issued a directive disallowing the use of no-clean
<br>fluxes
<br>on any of their hardware. The customer is flowing down that requirement
to
<br>us. Do any of you know of this directive or what they could be
referring
<br>to?
<p>---------------------------------------------------------------------------------
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<br>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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Date: Tue, 26 Feb 2002 17:19:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: No No-clean?
X-To: David Douthit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
David,
No I have not, but where is the onus placed? After reading what you
provided, it implies that the buyer is responsible to perform these
evaluations after the hardware is built. In no certain terms, with or
without this new document, design it + build it + qualify it + produce it +
warrant it = prove it, is the mandated acquisition process.
Steve
-----Original Message-----
From: David Douthit
Have you heard of this DoD document: DoD 5000.2-R Effective date 06/2001
MANDATORY PROCEDURES FOR MAJOR DEFENSE
ACQUISITION PROGRAMS (MDAPS) AND
MAJOR AUTOMATED INFORMATION SYSTEM (MAIS) ACQUISITION PROGRAMS
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Date: Tue, 26 Feb 2002 14:34:40 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Looking for Estimated price difference between 2 & 4 lay ers
(Roger's)
X-To: Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Which Rogers materials? There's a big difference in price between them.
> ----------
> From: Ken Patel[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Ken Patel
> Sent: Thursday, February 21, 2002 9:12 AM
> To: [log in to unmask]
> Subject: [TN] Looking for Estimated price difference between 2 & 4
> layers (Roger's)
>
> PCB Expert,
> What will be the price difference (in %) between 2 layer boards and 4
> layer boards using Roger's material? Both are impedance control boards.
> 4 layers board is 62 thick while 2 layers board is 25 mil thick. The
> size of the board is 3"X5" for both layer counts.
>
> I know it will be a volume specific so let's assume 100, 500 & 1000
>
>
> re,
> ken patel
>
> --------------------------------------------------------------------------
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Date: Tue, 26 Feb 2002 17:34:04 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mel Parrish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: No No-clean?
X-To: David Douthit <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Good comments Steve!
Dave
I wonder if this case would qualify for commercial nondevelopmental hardware
considering that they have applied a production material requirement.
Mel Parrish
Director of Training
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
Sent: Tuesday, February 26, 2002 12:11 PM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Steve,
"relies upon the performance specification to determine the product
requirements. In other
words don't tell the manufacturer how to
design/build/qualify/produce/warrant equipment because it costs too much,
tell her/him what you want the equipment to do, for how long, in what
environment and all with minimal risk and a reduced cost --"
Have you heard of this DoD document: DoD 5000.2-R Effective date 06/2001
MANDATORY PROCEDURES FOR MAJOR DEFENSE
ACQUISITION PROGRAMS (MDAPS) AND
MAJOR AUTOMATED INFORMATION SYSTEM (MAIS) ACQUISITION PROGRAMS
C3.2.3.2.2.5. T&E on commercial and non-developmental items shall ensure
performance,
operational effectiveness, and operational suitability for the military
application in
the military environment, regardless of the manner of procurement.
Test planning for these items shall recognize commercial testing and
experience,
but nonetheless determine the appropriate DT&E(Developmental Test And
Evaluation),
OT&E(Operational Test and Evaluation), and LFT&E(Live Fire Test and
Evaluation)
needed to assure effective performance in the intended operational
environment.
David A. Douthit
Manager
LoCan LLC
"Sauer, Steven T." wrote:
Hi Jim,
This sounds like a dissident to the DOD Acquistion Reform Policy
instituted
back in the mid 90s that did away with the "how to" spec's/std's (i.e.
MIL-E-5400, MIL-STD-275, MIL-P-55110 and MIL-STD-2000) and relies upon
the
performance specification to determine the product requirements. In
other
words don't tell the manufacturer how to
design/build/qualify/produce/warrant equipment because it costs too
much,
tell her/him what you want the equipment to do, for how long, in what
environment and all with minimal risk and a reduced cost -- yeah right!
If I were a betting man, I would say that an Air Force Program Manager
(not
the whole Air Force) has been bitten by the misuse of no-clean chemistry
on
a previous program or contract. So, in a sense, this may be the second
time
and it is not going to be shame on the PM.
This reminds me of years gone by while with the Navy -- after
MIL-STD-2000
was cancelled, NAWCADLKE-MISC-05-MT-0002 was developed and released by
the
same Navy folks (I'm one of the guilty) who supported the SOLD program.
This document found its way into contracts and product specifications
not
without notice but there was little the bigger DOD folks could do.
Remember, you get what you pay for and if that Air Force PM wants
no-clean,
he probably has a damn good reason why.
Steve Sauer
Northrop Grumman, Xetron
-----Original Message-----
From: Jim Jenkins
...the Air Force has issued a directive disallowing the use of no-clean
fluxes
on any of their hardware. The customer is flowing down that requirement
to
us. Do any of you know of this directive or what they could be
referring
to?
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<BODY>
<DIV><SPAN class=3D457364100-27022002><FONT face=3DTahoma =
color=3D#000080 size=3D2>Good=20
comments Steve!</FONT></SPAN></DIV>
<DIV><SPAN class=3D457364100-27022002><FONT face=3DTahoma =
color=3D#000080 size=3D2>Dave=20
</FONT></SPAN></DIV>
<DIV><SPAN class=3D457364100-27022002><FONT face=3DTahoma =
color=3D#000080 size=3D2>I=20
wonder if this case would qualify for commercial nondevelopmental =
hardware=20
considering that they have applied a production material requirement.=20
</FONT></SPAN></DIV>
<DIV><SPAN class=3D457364100-27022002><FONT face=3DTahoma =
color=3D#000080=20
size=3D2></FONT></SPAN> </DIV>
<DIV> </DIV>
<P><FONT size=3D2>Mel Parrish<BR>Director of Training<BR>Soldering =
Technology=20
International<BR>102 Tribble Drive<BR>Madison, AL 35758<BR>256 705 =
5530<BR>256=20
705 5538 =
Fax<BR>[log in to unmask]<BR>www.solderingtech.com</FONT> </P>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>David =
Douthit<BR><B>Sent:</B>=20
Tuesday, February 26, 2002 12:11 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] No=20
No-clean?<BR><BR></FONT></DIV>Steve,=20
<P><I>"relies upon the performance specification to determine the =
product=20
requirements. In other</I> <BR><I>words don't tell the =
manufacturer how=20
to</I> <BR><I>design/build/qualify/produce/warrant equipment because =
it costs=20
too much,</I> <BR><I>tell her/him what you want the equipment to do, =
for how=20
long, in what</I> <BR><I>environment and all with minimal risk and a =
reduced=20
cost --"</I><I></I>=20
<P>Have you heard of this DoD document: DoD 5000.2-R =
Effective=20
date 06/2001=20
<P>MANDATORY PROCEDURES FOR MAJOR DEFENSE <BR>ACQUISITION PROGRAMS =
(MDAPS) AND=20
<BR>MAJOR AUTOMATED INFORMATION SYSTEM (MAIS) ACQUISITION PROGRAMS=20
<P>C3.2.3.2.2.5. T&E on commercial and non-developmental =
items shall=20
ensure performance, <BR>operational effectiveness, and operational =
suitability=20
for the military application in <BR>the military environment, =
regardless of=20
the manner of procurement. <BR>Test planning for these items shall =
recognize=20
commercial testing and experience, <BR>but nonetheless determine the=20
appropriate DT&E(Developmental Test And Evaluation),=20
<BR>OT&E(Operational Test and Evaluation), and LFT&E(Live Fire =
Test=20
and Evaluation) <BR>needed to assure effective performance in the =
intended=20
operational environment.=20
<P>David A. Douthit <BR>Manager <BR>LoCan LLC<I></I>=20
<P>"Sauer, Steven T." wrote:=20
<BLOCKQUOTE TYPE=3D"CITE">Hi Jim, <BR>This sounds like a dissident to =
the DOD=20
Acquistion Reform Policy instituted <BR>back in the mid 90s that did =
away=20
with the "how to" spec's/std's (i.e. <BR>MIL-E-5400, MIL-STD-275,=20
MIL-P-55110 and MIL-STD-2000) and relies upon the <BR>performance=20
specification to determine the product requirements. In other=20
<BR>words don't tell the manufacturer how to=20
<BR>design/build/qualify/produce/warrant equipment because it costs =
too=20
much, <BR>tell her/him what you want the equipment to do, for how =
long, in=20
what <BR>environment and all with minimal risk and a reduced cost -- =
yeah=20
right! <BR>If I were a betting man, I would say that an Air Force =
Program=20
Manager (not <BR>the whole Air Force) has been bitten by the misuse =
of=20
no-clean chemistry on <BR>a previous program or contract. So, =
in a=20
sense, this may be the second time <BR>and it is not going to be =
shame on=20
the PM. <BR>This reminds me of years gone by while with the Navy -- =
after=20
MIL-STD-2000 <BR>was cancelled, NAWCADLKE-MISC-05-MT-0002 was =
developed and=20
released by the <BR>same Navy folks (I'm one of the guilty) who =
supported=20
the SOLD program. <BR>This document found its way into contracts and =
product=20
specifications not <BR>without notice but there was little the =
bigger DOD=20
folks could do. <BR>Remember, you get what you pay for and if that =
Air Force=20
PM wants no-clean, <BR>he probably has a damn good reason why.=20
<P>Steve Sauer <BR>Northrop Grumman, Xetron=20
<P>-----Original Message----- <BR>From: Jim Jenkins=20
<P>...the Air Force has issued a directive disallowing the use of =
no-clean=20
<BR>fluxes <BR>on any of their hardware. The customer is =
flowing down=20
that requirement to <BR>us. Do any of you know of this =
directive or=20
what they could be referring <BR>to?=20
=
<P>----------------------------------------------------------------------=
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<BR>Technet Mail List provided as a free service by IPC using =
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<BR>To unsubscribe, send a message to [log in to unmask] with =
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<BR>To receive ONE mailing per day of all the posts: send e-mail to=20
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Archives=20
<BR>Please visit IPC web site <A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>=20
for additional <BR>information, or contact Keach Sasamori at =
[log in to unmask]
or 847-509-9700 ext.5315=20
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Date: Tue, 26 Feb 2002 17:01:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Glynn Shaw <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Glynn Shaw <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
In-Reply-To: <A71205756C62D411B06900B0D03DC136B1C1F0@CONNECTOR>
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I didn't build your boards, but I build them for a living. After reading
numerous comments, I offer the following:
Be careful about specifying the materials. If you spec the glue into the
middle, as you say, then you increase the cost of the boards with no real
benefit. It is cheaper and just as reliable to build the boards with a
single double-sided core and prepreg on both sides against foil
outerlayers. This is the preferred method of manufacture... it costs less
because it is easier to build and the materials are cheaper, but the
pricess itself is every bit as good as the "old way".
The best oxides are no longer black in appearance. If your traces on layer
2 are silver-colored now, this is probably a good thing. Your supplier may
be just improving his quality and forgot to brag about it.
The new oxides are now lighter than the treatment used by laminate
manufacturers. Laminators use a treatment that is tan or reddish colored.
When it was contrasted by black-oxided traces, it appeared light. But now,
against the silver of the new oxides, and covered with soldermask, it can
seem quite dark.
At 08:59 AM 2/26/02 -0600, you wrote:
>Hi,
>We just received a new rev of a PWB in house. It has not been populated
>yet. It looks like it has been built correctly - the right layer order,
>connections, etc - but it looks different than the rest of our 4 layer
>boards. Normally the traces on the inner layer that is closest to the
>surface appear dark in colour and the deeper layer appears lighter. This
>board is the opposite. The layer closest to the surface is light in colour
>and the deeper layer is dark. Also, the FR4 seems much easier to see
>through than usual.
>
>Any thoughts or explanations for this?
>Thanks for your time.
>
>Genny Gibbard (mailto:[log in to unmask])
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
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Date: Tue, 26 Feb 2002 19:27:50 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: Circuit Test
X-To: Keach Sasamori <[log in to unmask]>
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I have also faced "requirements" like this several times. Though is
achievable on lower complexity products, it is typically not possible for
the type of boards you describe. Your boards are the specific test scenario
that led the industry to develop boundary scan test methods and the JTAG
interface. They were invented to give visibility to buried or otherwise
unreachable nodes, thus making higher density products feasible. They did
not come about to make test development easy.
It sounds like your Logistics Group is simplifying their own life and
covering their collective posterior at everyone else's expense. This kind
of mindset is similar to requiring that every component specified has
multiple manufacturers and be in stock at multiple distributors. While
these are laudable goals, if you take these as requirements, you will design
products that are easily manufactured and tested but are too large or
technologically backward for the end use, i.e. they won't sell.
This is a tough nut to crack because 100% test access is not a requirement
for assuring a conforming, quality product. It is a requirement for
enabling someone to do their job without thinking. Being conservative and
insisting on processes that you can stand behind is a reasonable starting
point. When it precludes your achieving customer requirements, it's time
for _them_ to come up with some alternatives.
Complex, dense boards are challenging to create a test strategy for and
there is no avoiding it, at least with today's test technologies. You will
likely have to use a combination of technologies to fully test your product.
The SPECCTRA router is a very capable design tool and there is no magic
bullet here. IMHO, double-sided 12-layer boards and 100% test access are
incompatible.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Keach Sasamori
> Sent: Tuesday, February 26, 2002 9:21 AM
> To: [log in to unmask]
> Subject: [TN] Circuit Test
>
>
> Forwarding for Alan Groves:
>
> >>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
> Hi, I have not used the forum before but am currently at the centre of an
> internal company clash, and would appreciate any help on the issue below.
>
> My problem involves In Circuit Test ;-
> Our Logistics department here (which includes production, test and
> deployment) are demanding quite strongly that ICT be done on each PWB we
> design, and that every signal and every component value be
> tested, i.e. 100%
> test point access on traces (even N/Cs).
> The Engineers are not quite so keen as most have used JTAG and
> Boundary scan
> etc to evaluate the devices they deem critical. They are also worried (and
> rightly so) about the effect that test points may have on traces with
> controlled impedance, or those on critical timing paths, but are
> not adverse
> to giving test point access where possible and where the design
> will not be
> affected.
> The boards we design here are also very complex, we mount SMDs on
> both sides
> and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
> boards are also very dense with real estate at an absolute priority such
> that we use the smallest devices available. Currently we have 0,8mm pitch
> uBGAs whose routing must be resolved vertically, i.e. blind and
> buried vias,
> with obvious drawbacks for ICT.
> We have in the past used the Specctra autorouter to allocate test point
> access but the best result so far is about 80% (of course I could use bad
> placement to improve this!), and even here we used the smallest possible
> access points 0.03" on the smallest possible grid 0.05". On some boards it
> is below 50% access. Our usual via holes only have land of
> 0.024", so these
> cannot be used.
> I could of course try to manually allocate access points, by
> increasing via
> land where appropriate, or thickening and exposing traces where
> possible and
> deploying all other tricks I can, but the time and effort here would be
> enormous, and other projects may suffer as a result.
>
> Any advise or knowledge that can be offered here would be most welcome.
> Is this problem common to other companies?
> How is the Industry thinking about ICT at the moment?
> Are there better autorouters?
> Are there ICT houses that can use smaller nodes on tighter grids?
> Is there new technology just around the corner?
> Etc Etc.
>
> With many thanks in advance, and regards,
>
> Alan Groves CID,
> Technical Services (D.O.) Team Leader.
> Spectel , 21 Stillorgan Ind. Park, Stillorgan,
> Co. Dublin. Ireland.
> Phone: 353 907 62803
> Fax: 353 1 2953740
> Email: [log in to unmask]
> Internet: www.spectel.com
>
> Or Via :
> Spectel, Inc.
> 200 Minuteman Road
> Andover, Massachusetts 01810 USA
> PH: 1.978.552.6260
> FX: 1.978.552.6250
>
> ------------------------------------------------------------------
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Date: Wed, 27 Feb 2002 12:19:20 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Circuit Test
X-To: Keach Sasamori <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Alan,
You have my heartfelt sympathy, and I can only help relieve a tiny portion
of what you're asking, as I'm a Jack of all Trades and Master of the
Inverse.
There are various techniques for grouping and isolating components in a
layout such that they can be tested with fewer test points. The pad sizes
and spaces you quote are at the limit from what I know, but I understand
that probe technology is having to improve all the time to keep pace with
ever-developing miniaturisation. I suggest you talk closely to Agilence, or
similar ICT tester experts to see what they have to say. And don't
necessarily listen too hard to what the jig manufacturers have to say. The
ICT test machine manufacturers will tell you what it's possible to test and
how. All you have to do then is find a jig manufacturer who can comply.
Only relax your requirements as you beat a strategic retreat from the
apparently impossible to the just possible.
Another two cents' worth is - we also have densely populated, double-sided,
12 layer boards, and we opted to manually route them. We couldn't rely on
any autorouter to efficiently route a board and maintain our design rules,
as we wound up with critical traces being routed all over the place and via
a number of layers instead of being 'as short as possible' and limited to
one layer. Manual routing gave us infinitely more control over what was
routed where, and it didn't change out of all recognition with every minor
amendment. It takes longer and is possible to prone to at least the same
number of errors (albeit human rather than machine), but it worked better
for us when laying out how many ICT pads we really needed and where they
should go.
FYI, The routers we s/c to use PADS, Allegro or Mentor, each at latest
versions, which, when comparing results, is a good spread of routing
software in terms of quality.
Peter
ST Aero
Keach
Sasamori To: [log in to unmask]
<KeachSasamor cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
[log in to unmask]> Aero/ST Group)
Sent by: Subject: [TN] Circuit Test
TechNet
<[log in to unmask]
ORG>
02/26/02
11:21 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Keach
Sasamori
Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e.
100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary
scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not
adverse
to giving test point access where possible and where the design will not be
affected.
The boards we design here are also very complex, we mount SMDs on both
sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried
vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so these
cannot be used.
I could of course try to manually allocate access points, by increasing via
land where appropriate, or thickening and exposing traces where possible
and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
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Date: Wed, 27 Feb 2002 12:50:26 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No No-clean?
X-To: Jim Jenkins <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Jim,
I haven't heard of a specific directive banning the use of no-clean, but
having worked all my life in the aerospace manufacturing industry, I
wouldn't naturally us no-cleans to start with.
As has been said before in this forum - no-clean does not mean no-residue.
In the operating environments that expensive aircraft frequent, ANY
residues affect the life and reliability of a board and not predictably so.
Their effect in an aerospace environment is many times more significant
than they are in, say, a PC or VCR, which operate only in relatively very
benign conditions.
If your company is not a specialist CM for aerospace boards - i.e. you're
more commercially oriented - then the directive is possibly issued
specially so that you're not tempted to use no-clean processes.
Peter
Jim Jenkins
<jjenki09@HAR To: [log in to unmask]
RIS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] No No-clean?
<[log in to unmask]
ORG>
02/26/02
11:53 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Jim Jenkins
Hi everybody,
I was just approached by one of our engineers whose customer told her that
the Air Force has issued a directive disallowing the use of no-clean fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring
to?
Thanks,
Jim
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=========================================================================
Date: Tue, 26 Feb 2002 22:46:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: REALLY EXCITING STUFF AND A BUG IN MY CAVE
Hell, It ain't that exciting but it sure got my attention. I asked Steve,
again, to post three pics on his outstanding site. The first shows the
overall view, top down of course, of solder columns at 10x. The second has a
bug in it at 60x. Probably one of those little brown "lady bug" like
creatures infesting us all (damn they're bad, aren't they?). The third is a
more slanted view showing the "columns" that seem partially formed solder
joints that didn't take.
The strange thing, to me, is the CSP/DSP parts fell off the board on
arrival. However, a large ceramic BGA on the same board exhibited perfect
solder ball squat and joint formation.
My question is how do these columns form into almost perfect structures
without reflowing around and into the balls? Eutectic means, I'm told, going
from a solid state to a liquid state without going through a plastic state.
Again, how did this occur without reflowing and effecting a solder joint?
MoonMan
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Date: Wed, 27 Feb 2002 12:56:42 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Circuit Test
X-To: Lucas Paul-R32425 <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
One more cent's worth is to enhance the board's own built-in test (BIT)
capability, wich reduces the amount of ICT tesing required.
Peter
Lucas
Paul-R32425 To: [log in to unmask]
<Paul.Lucas@MOT cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
OROLA.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] Circuit Test
TechNet
<[log in to unmask]
G>
02/27/02 02:17
AM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to Lucas
Paul-R32425
Alan,
We too have the same situation as you do in regards to ICT of complex
PWA's. Our design engineers have not included test points, wide traces or
anything else that would allow for the in circuit testing of our boards.
Our boards are very dense in component population and use a mixture of fine
pitch, SMD and thru hole components on them. They are 10"X18" boards that
have 8 to 12 layers. As big as they are there is just no room to fit any
test points on there. That's ok because, the designers have no intentions
of going back and re-routing the boards to allow for this.
So we have had to compensate by finding an assembly house that has AOI.
They do 100% inspection on every board they assemble. When we receive the
boards we add several more components by hand and then we do a visual
inspection. After that we use a meter or curve tracer to check the power
planes for shorts between them and ground. Finally comes what we call the
"smoke test". This is were the board is plugged into a test chassis and
turned on. You will soon find out if you still have any shorts are reversed
components that you missed. Believe it or not this has been successful for
us in getting boards built and working. ICT is obviously much faster in
testing the boards, but not always more accurate or successful(Test
programs are never complete and constantly changing). One of the big reason
this works for us is because we have low volumes and a high mix(ICT is
expensive for low volume, very complex boards).
You have to balance the cost of adding ICT into your designs and to your
assembly costs against the cost of visual inspection and more labor
intensive test procedures. For us it was about the same cost and the
quality has not suffered by omitting ICT.
Hope this helps,
Paul
-----Original Message-----
From: Keach Sasamori [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 8:21 AM
To: [log in to unmask]
Subject: [TN] Circuit Test
Forwarding for Alan Groves:
>>> "Alan Groves" <[log in to unmask]> 02/26/02 09:13AM >>>
Hi, I have not used the forum before but am currently at the centre of an
internal company clash, and would appreciate any help on the issue below.
My problem involves In Circuit Test ;-
Our Logistics department here (which includes production, test and
deployment) are demanding quite strongly that ICT be done on each PWB we
design, and that every signal and every component value be tested, i.e.
100%
test point access on traces (even N/Cs).
The Engineers are not quite so keen as most have used JTAG and Boundary
scan
etc to evaluate the devices they deem critical. They are also worried (and
rightly so) about the effect that test points may have on traces with
controlled impedance, or those on critical timing paths, but are not
adverse
to giving test point access where possible and where the design will not be
affected.
The boards we design here are also very complex, we mount SMDs on both
sides
and often have 10 or 12 copper layers in (usually) 1,6mm thick FR4, the
boards are also very dense with real estate at an absolute priority such
that we use the smallest devices available. Currently we have 0,8mm pitch
uBGAs whose routing must be resolved vertically, i.e. blind and buried
vias,
with obvious drawbacks for ICT.
We have in the past used the Specctra autorouter to allocate test point
access but the best result so far is about 80% (of course I could use bad
placement to improve this!), and even here we used the smallest possible
access points 0.03" on the smallest possible grid 0.05". On some boards it
is below 50% access. Our usual via holes only have land of 0.024", so these
cannot be used.
I could of course try to manually allocate access points, by increasing via
land where appropriate, or thickening and exposing traces where possible
and
deploying all other tricks I can, but the time and effort here would be
enormous, and other projects may suffer as a result.
Any advise or knowledge that can be offered here would be most welcome.
Is this problem common to other companies?
How is the Industry thinking about ICT at the moment?
Are there better autorouters?
Are there ICT houses that can use smaller nodes on tighter grids?
Is there new technology just around the corner?
Etc Etc.
With many thanks in advance, and regards,
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel , 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
Or Via :
Spectel, Inc.
200 Minuteman Road
Andover, Massachusetts 01810 USA
PH: 1.978.552.6260
FX: 1.978.552.6250
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=========================================================================
Date: Wed, 27 Feb 2002 09:02:43 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Jim Jenkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Jim
Quite an interesting one this, with implications beyond the obvious.
Firstly, despite what Mike says, I think most of us would agree that a
properly cleaned board, even soldered with a reasonably aggressive flux,
is less likely to be unreliable than an uncleaned one, under some given
conditions. Experience has proved this.
Then there are some "no-clean" fluxes/pastes which are REALLY dangerous,
so it is easy to imagine that someone could have been bitten.
However, I strongly suspect, reading between the lines, that this notion
may apply to conformally-coated boards. Here, there is a distinct
problem with "no-cleans" unless the homework is VERY carefully done and
the process is constantly requalified, including checking the
contamination on every batch of incoming components. Personally, I would
never advise a client to use "no-clean" products if the products were to
be coated. It could be a time bomb waiting to go off under your feet
even years later (especially, no pun, with armament electronics which
may be stored for 15 years and then used for the first and only time
during a period of a few minutes).
Finally, a PCB design which is optimised for use with a mild "no-clean"
wave-soldering flux or paste would be better redrafted if it were to be
changed to a less mild flux and cleaned. Many such boards would be
totally unsuitable for cleaning and the result may be worse than ever,
in terms of reliability, if there were no re-design.
I would therefore want the rumour to be substantiated before any action
was to be taken.
Brian
Jim Jenkins wrote:
>
> Hi everybody,
>
> I was just approached by one of our engineers whose customer told her that
> the Air Force has issued a directive disallowing the use of no-clean fluxes
> on any of their hardware. The customer is flowing down that requirement to
> us. Do any of you know of this directive or what they could be referring to?
>
> Thanks,
>
> Jim
>
> ---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 27 Feb 2002 09:11:54 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Re: Antw: [TN] Intermetallic thickness
Mime-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
Earl
Well this really a very long sentence and I had to red it twice to get it. =
However, it sais a lot and nothing. Especially regarding the IMC layers.
The problem is, that IMC's are strong and brittle. This means that usually =
IMC's don't deform in thermal cycling. However, as in all brittle =
materials, a notch or crack propagates very fast through the material ( in =
fact almost instantaneously) due the stress concentration occurring at the =
tip of the crack. To do so a certain stress is needed. Note, degradation =
in solder is strain driven, in the IMC it is stress driven. But, a brittle =
material with a notch needs less load to crack than one without a notch.
The problem of the thickness of an IMC is quite tricky. That's why the IPC =
is somewhat wishy washy about that.=20
- Firstly, the thicker the IMC the more structured is the interface =
solder- IMC, this means the more notches you have.=20
- Secondly, in the gap between a component and the pad you have a limited =
thickness of solder to accommodate the strain forced into the solder joint =
during a thermal cycle. Since stress and strain rate ( It's getting =
academic did you note it? ) are in a direct relationship in creep, this =
results in higher stress the thinner this layer is. Considering the fact =
that IMC's are formed with the solder available one can say that the =
thicker the IMC the thinner the remaining solder gap and thus the higher =
the stress occurring in thermal cycling.
However, who can say how much solder you have between your component and =
the pad. I feel, if 30um of solder between the IMC and the connector of =
the component is left no problem is to expected in an environment above 0 =
deg.C and temperature ramps below 4 deg.C per minute.
Regarding the thickness, well as I said before: I believe the IMC should =
be as thin as possible but there must be one because that's the alloying =
of Sn and Cu we need when soldering but I have no facts. Would be fun to =
look after it.
Have a great day
Guenter
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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=========================================================================
Date: Wed, 27 Feb 2002 10:51:15 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mike Holst." <[log in to unmask]>
Subject: MLB - spotwelding
MIME-Version: 1.0
Content-type: text/plain; charset=US-ASCII
Content-transfer-encoding: 7BIT
We constructed our own machine for spotwelding mlb lay-ups prior
to pressing. It works fine for 6 and 8 layers (standard FR4 thin
laminates and prepreg). However, for higher layer counts especially
12 layers we seem often to loose internal layer / layer registration.
Could anyone kindly suggest a set of operating parameters
(temperature / pressure / time etc) to give more reliable welds for
higher layer counts. Pressed thickness about 1.6mm. Panel sizes
are relatively small - 14" x 11" would be typical, with 3 welds on
each long side about 4" apart.
The welder heads have a round flat point 10mm diameter and
existing settings are as follows:
Air pressure on the 16mm dia. welder cylinders is 5.5 bar, head
temperatures are controlled at 280C and weld timer set at 90 sec.
Any other input on this subject will also be welcome.
Thanks,
Mike Holst
Mike Holst.
TraX Interconnect (Pty) Ltd
Tel:(++27 21)712 5011
Fax:(++27 21)712 5798
Cape Town
South Africa
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Date: Wed, 27 Feb 2002 05:42:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Antw: [TN] Intermetallic thickness
X-To: Guenter Grossmann <[log in to unmask]>
Guenter my great friend, if I may address you that way, I almost understand
all you say to the point of thinner might be better. Of course, I am totally
fact free as well.
Not in any way will an academic point of view make me any more informed. I
want the beef - the facts. If the IPC says something a bit wishy washy,
considering the status of 279's chair (sir Werner) and its fine staff, how
can I even pretend to understand the situation and even feel a bit warm and
fuzzy about solder joint reliability.
I know most of my non academic solder joints are fairly reliable but I still
question how so or much or or or or (cave talk down here)? The photos I
asked Steve to post, defy logic but point to a very messed up process not
even based on IMC formation. However, I did send some others to Werner and
Dave, and based on some findings by Collins and TI that found the IMC layer
to be too thick therefore effecting castration of the balls from the part.
Yes, much to ponder and, seemingly, much more for us all to learn about
solder, solderability, soldering, solder joint formation, and solder joint
reliability.
Are we getting close yet?
MoonMan
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Date: Wed, 27 Feb 2002 13:14:05 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Recycling of electronic waste
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Dear Technetters
We all had numerous discussions about the need of controlled recycling of =
electronic waste as the much famed WEEE and many also famed "greens" =
request it. In a Swiss newspaper (NZZ) I read an interesting article about =
this item. It's in German and I try to translate it into English. Any =
failures in the translation are due to my fault and do not go onto the =
account of NZZ:
San Jose 26. Feb.(sda)
Used computers and other electronic equipment exported as electronic waste =
from the USA threaten the human lives and the environment in China and =
India according to a study. The survey has been published by the environmen=
tal groups Silicon Valley Toxic Coalition and Basel Action Network last =
Monday in San Jose. As an example a region in Southern China has been =
mentioned where approx. 100'000 workers together with their families =
disassemble old computers and are exposed to poisonous substances. The =
electronic waste has already contaminated the groundwater to such an =
extend that drinking water has to be brought to the site. Large amounts of =
contaminated waste and plastics are burned and deposited in farmlands and =
irrigation channels. According to the study the US are the only industriali=
sed country that does not comply with an international treaty that bans =
the export of hazardeous waste to developping countries.=20
Maybe we should not only look on the ban of lead in the WEEE but also on =
the more than necessary regulations how electronic waste has to be =
treated. The sadest thing to me though is the fact that we need regulations=
because many people in industry act irresponsible and without any common =
sense if they are not forced legally to care.
Anyway, have a great day
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Wed, 27 Feb 2002 07:29:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Antw: [TN] Intermetallic thickness
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Hi MoonCaveMan Shacking Up with Ground Hogs,
When we wrote this, we simply wanted to convey the message that if SJ failure
is in any other failure mode than fracture in the solder per se, it will be
earlier than the SJ reliability design equations estimate. At that point in
time people were having an awful time with ENIG and so we wanted to cover all
the bases.
Best regards,
Werner Engelmaier
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Date: Wed, 27 Feb 2002 08:21:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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No pictures on Steves site yet, but I have observed that CSPs are harder to
heat than BGAs, I have worked on boards that exhibited beautiful solder
connections on 1.27mm pitch BGAs and insufficient reflow under .5 mm CSPs.
Finally, there are CSPs out there with 90/10 solder bumps.
I had an experience with a bug once, a fruit fly must have landed in the
solder paste just prior to placement of an 1206 chip resistor. The result, a
solder fillet with wing, eye, and two legs protruding . . . they did not
exhibit good wetting.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: Tuesday, February 26, 2002 11:47 PM
> To: [log in to unmask]
> Subject: [TN] REALLY EXCITING STUFF AND A BUG IN MY CAVE
>
>
> Hell, It ain't that exciting but it sure got my attention. I asked Steve,
> again, to post three pics on his outstanding site. The first shows the
> overall view, top down of course, of solder columns at 10x. The
> second has a
> bug in it at 60x. Probably one of those little brown "lady bug" like
> creatures infesting us all (damn they're bad, aren't they?). The
> third is a
> more slanted view showing the "columns" that seem partially formed solder
> joints that didn't take.
>
> The strange thing, to me, is the CSP/DSP parts fell off the board on
> arrival. However, a large ceramic BGA on the same board exhibited perfect
> solder ball squat and joint formation.
>
> My question is how do these columns form into almost perfect structures
> without reflowing around and into the balls? Eutectic means, I'm
> told, going
> from a solid state to a liquid state without going through a
> plastic state.
>
> Again, how did this occur without reflowing and effecting a solder joint?
>
> MoonMan
>
> ------------------------------------------------------------------
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Date: Wed, 27 Feb 2002 07:21:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Paul Brionez <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Brionez <[log in to unmask]>
Subject: Re: The board looks funny...
X-To: Genny Gibbard <[log in to unmask]>
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Genny
IMO the use of pre-preg should be evaluated based on the operation of the circuit that you are
designing on it. If I had a High Speed circuit the less pre-preg is better since there are less
variables to control. If on the other hand I was creating a low speed power supply type etc., PCB I
would be less likely to be concerned with the materials in the PCB and be concerned with the overall
cost. Remember that the board house builds a panel and if they can build your board in one process it
is easier to control. Work with your board house to see what works better and if it fits in there
process. I hope that helps answers your question.
If you have access to the IPC Standards
One place to start to look at is the IPC 2222 Section 4. for Laminate PrePreg.
IPC
In the assembly of PCBs the Pre-preg is a resin material that has rigid properties until you apply
the necessary heat and pressure at which time the material will flow providing the necessary adhesion
between foil layers and cores. I have found in the past that most manufacturers will have a different
recipe for your PCB depending on the type of process that the vendor uses, the build-up, material
availability, and cost. If your PCB has impedance properties be sure that if you are concerned about
this that the fabricator is aware of your requirements. Various types of Pre-preg have different levels
of glass content and will exhibit different dielectric properties. Ask your board house to provide you
with the build tickets for the two revisions and then you can see what was different about the builds.
This build ticket travels with the PCB throughout the fabrication process.
If you go to the web and search Pre-preg you can find a lot of information some good some bad.
Paul
Genny Gibbard wrote:
> Thanks Paul. I believe you have hit the nail on the head. This may seem
> like an elementary question, but is it better to spec more pre-preg, like
> your standard second sketch, or go with your first sketch?
>
> I guess I don't have a good concept of what prepreg is or when it should be
> used. What I think I know about it is that it is not fully cured FR4 and
> that the pressing of the layers together is what finishes the cure process.
> I think I believed that it was sort of the 'glue' that held a multilayer
> board together and thought it should be placed in the middle.
> We have only just started to try to be more specific in what materials we
> spec, and before, we trusted the manufacturer to figure out what to use. I
> believe we probably used to get a construction based exactly on your second
> sketch. But this board is built like your first sketch, which, amazingly
> enough, was what we spec'd in our brand new revised readme file.
> It is comforting to know they read my readme file...even if I don't know
> what I am talking about.
>
> Thanks. Any good sources of info on what pre-preg is and where it should be
> used would be much appreciated...
>
> -----Original Message-----
> From: Paul Brionez [mailto:[log in to unmask]]
> Sent: February 26, 2002 11:00 AM
> To: TechNet E-Mail Forum.; Genny Gibbard
> Subject: Re: [TN] The board looks funny...
>
> Genny
>
> It sounds like your PCB was built with two B stages with FR4 between the
> copper layers and the prepreg
> between layers 2-3.
>
> Similar to this Most 4-layers
>
> 1- cu 1- cu
> FR-4 pre-preg
> 2- cu 2- cu
> pre-preg Filler FR-4
> 3- cu 3 - cu
> FR-4 pre-preg
> 4- cu 4 - cu
>
> Genny Gibbard wrote:
>
> > Hi,
> > We just received a new rev of a PWB in house. It has not been populated
> > yet. It looks like it has been built correctly - the right layer order,
> > connections, etc - but it looks different than the rest of our 4 layer
> > boards. Normally the traces on the inner layer that is closest to the
> > surface appear dark in colour and the deeper layer appears lighter. This
> > board is the opposite. The layer closest to the surface is light in
> colour
> > and the deeper layer is dark. Also, the FR4 seems much easier to see
> > through than usual.
> >
> > Any thoughts or explanations for this?
> > Thanks for your time.
> >
> > Genny Gibbard (mailto:[log in to unmask])
> >
> >
> ----------------------------------------------------------------------------
> -----
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> SET Technet NOMAIL
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> [log in to unmask]: SET Technet Digest
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> E-mail Archives
> > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> >
> ----------------------------------------------------------------------------
> -----
>
> ---------------------------------------------------------------------------------
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--------------0C9B62B5A360977B84C2E187
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Genny
<p>IMO the use of pre-preg should be evaluated based on the operation of
the circuit that you are designing on it. If I had a High Speed circuit
the less pre-preg is better since there are less variables to control.
If on the other hand I was creating a low speed power supply type etc., PCB I
would be less likely to be concerned with the materials in the PCB and
be concerned with the overall cost. Remember that the board house builds
a panel and if they can build your board in one process it is easier to
control. Work with your board house to see what works better and if it
fits in there process. I hope that helps answers your question.
<br>
<br>
<p>If you have access to the IPC Standards
<p>One place to start to look at is the IPC 2222 Section 4. for Laminate
PrePreg.
<br><br>
<a href="www.ipc.org">IPC</a>
<p> In the assembly of PCBs the Pre-preg is a resin
material that has rigid properties until you apply the necessary heat and
pressure at which time the material will flow providing the necessary adhesion
between foil layers and cores. I have found in the past that most
manufacturers will have a different recipe for your PCB depending on the
type of process that the vendor uses, the build-up, material availability,
and cost. If your PCB has impedance properties be sure that if you
are concerned about this that the fabricator is aware of your requirements.
Various types of Pre-preg have different levels of glass content and will
exhibit different dielectric properties. Ask your board house to provide
you with the build tickets for the two revisions and then you can see what
was different about the builds. This build ticket travels with the PCB
throughout the fabrication process.
<p>If you go to the web and search Pre-preg you can find a lot of information
some good some bad.
<p>Paul
<br>
<p>Genny Gibbard wrote:
<br>
<blockquote TYPE=CITE>Thanks Paul. I believe you have hit the nail
on the head. This may seem
<br>like an elementary question, but is it better to spec more pre-preg,
like
<br>your standard second sketch, or go with your first sketch?
<p>I guess I don't have a good concept of what prepreg is or when it should
be
<br>used. What I think I know about it is that it is not fully cured
FR4 and
<br>that the pressing of the layers together is what finishes the cure
process.
<br>I think I believed that it was sort of the 'glue' that held a multilayer
<br>board together and thought it should be placed in the middle.
<br>We have only just started to try to be more specific in what materials
we
<br>spec, and before, we trusted the manufacturer to figure out what to
use. I
<br>believe we probably used to get a construction based exactly on your
second
<br>sketch. But this board is built like your first sketch, which,
amazingly
<br>enough, was what we spec'd in our brand new revised readme file.
<br>It is comforting to know they read my readme file...even if I don't
know
<br>what I am talking about.</blockquote>
<blockquote TYPE=CITE>
<br>Thanks. Any good sources of info on what pre-preg is and where
it should be
<br>used would be much appreciated...
<p>-----Original Message-----
<br>From: Paul Brionez [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: February 26, 2002 11:00 AM
<br>To: TechNet E-Mail Forum.; Genny Gibbard
<br>Subject: Re: [TN] The board looks funny...
<p>Genny
<p>It sounds like your PCB was built with two B stages with FR4 between
the
<br>copper layers and the prepreg
<br>between layers 2-3.
<p>Similar to this
Most 4-layers
<p>1- cu
1- cu
<br> FR-4
pre-preg
<br>2- cu
2- cu
<br> pre-preg
Filler FR-4
<br>3- cu
3 - cu
<br> FR-4
pre-preg
<br>4- cu
4 - cu
<p>Genny Gibbard wrote:
<p>> Hi,
<br>> We just received a new rev of a PWB in house. It has not been
populated
<br>> yet. It looks like it has been built correctly - the right
layer order,
<br>> connections, etc - but it looks different than the rest of our 4
layer
<br>> boards. Normally the traces on the inner layer that is closest
to the
<br>> surface appear dark in colour and the deeper layer appears lighter.
This
<br>> board is the opposite. The layer closest to the surface is
light in
<br>colour
<br>> and the deeper layer is dark. Also, the FR4 seems much easier
to see
<br>> through than usual.
<br>>
<br>> Any thoughts or explanations for this?
<br>> Thanks for your time.
<br>>
<br>> Genny Gibbard (<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>)
<br>>
<br>>
<br>----------------------------------------------------------------------------
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text in
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<br>SET Technet NOMAIL
<br>> To receive ONE mailing per day of all the posts: send e-mail to
<br>[log in to unmask]: SET Technet Digest
<br>> Search previous postings at: www.ipc.org > On-Line Resources &
Databases >
<br>E-mail Archives
<br>> Please visit IPC web site <a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>
for additional
<br>> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
<br>ext.5315
<br>>
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<br>-----
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Date: Wed, 27 Feb 2002 05:49:04 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Re: input on pressing cPCI connectors
X-cc: JASON POPIELARSKI <[log in to unmask]>, [log in to unmask]
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Dee,
We design and build a lot of these tools for our customers. One possible =
problem is your press may not be powerful enough. You'll be surprised =
when you calculate the average force for all those pins. Backing tooling =
(board support) can be very critical, as we've found the "standard" =
slotted tooling distributes the energy longitudinally and can cause =
latent failures.
Please feel free to call myself or Jason if you would like to discuss =
this in more detail.
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Dee,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>We design and build a lot of these =
tools for our=20
customers. One possible problem is your press may not be powerful =
enough. You'll=20
be surprised when you calculate the average force for all those pins. =
Backing=20
tooling (board support) can be very critical, as we've found the =
"standard"=20
slotted tooling distributes the energy longitudinally and can cause =
latent=20
failures.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Please feel free to call myself or =
Jason if you=20
would like to discuss this in more detail.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
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Date: Wed, 27 Feb 2002 16:36:03 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Recycling of electronic waste
X-To: Guenter Grossmann <[log in to unmask]>
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Guenter
If you go into the IPC EnviroNet, you will see a thread addressing this
issue.
Best regards,
Brian
Guenter Grossmann wrote:
>
> Dear Technetters
>
> We all had numerous discussions about the need of controlled recycling of electronic waste as the much famed WEEE and many also famed "greens" request it. In a Swiss newspaper (NZZ) I read an interesting article about this item. It's in German and I try to translate it into English. Any failures in the translation are due to my fault and do not go onto the account of NZZ:
>
> San Jose 26. Feb.(sda)
> Used computers and other electronic equipment exported as electronic waste from the USA threaten the human lives and the environment in China and India according to a study. The survey has been published by the environmental groups Silicon Valley Toxic Coalition and Basel Action Network last Monday in San Jose. As an example a region in Southern China has been mentioned where approx. 100'000 workers together with their families disassemble old computers and are exposed to poisonous substances. The electronic waste has already contaminated the groundwater to such an extend that drinking water has to be brought to the site. Large amounts of contaminated waste and plastics are burned and deposited in farmlands and irrigation channels. According to the study the US are the only industrialised country that does not comply with an international treaty that bans the export of hazardeous waste to developping countries.
>
> Maybe we should not only look on the ban of lead in the WEEE but also on the more than necessary regulations how electronic waste has to be treated. The sadest thing to me though is the fact that we need regulations because many people in industry act irresponsible and without any common sense if they are not forced legally to care.
>
> Anyway, have a great day
>
> Guenter
>
> .
>
> EMPA
> Swiss Federal Institute for Materials Testing and Research
> Centre for Reliability
> Dipl. Eng. Guenter Grossmann
>
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
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Date: Wed, 27 Feb 2002 09:57:23 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2b.232b0f03.29ae4dd3_boundary"
--part1_2b.232b0f03.29ae4dd3_boundary
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Hey Earl!
The pic's are up! Go to:
http://www.stevezeva.homestead.com
(I spelt it right this time...hehehe)
-Steve Gregory-
--part1_2b.232b0f03.29ae4dd3_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey Earl!
<BR>
<BR>The pic's are up! Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>(I spelt it right this time...hehehe)
<BR>
<BR>-Steve Gregory-
<BR>
<BR></FONT></HTML>
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Date: Wed, 27 Feb 2002 09:00:56 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Antw: [TN] Intermetallic thickness
X-To: [log in to unmask]
Ah, Sir Werner, you are alert as ever. Knew I could draw you out for a
moment. I also knew you would provide the correctomundo answer. Glad not
everyone takes a whole day or ten to read IPC and your stuff in it.
I'll go with your explanation. I hope everyone else does as well - including
soon to be Sir Guenter.
MoonMan with bug and no way to kill it - YET
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Date: Wed, 27 Feb 2002 09:09:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: [log in to unmask]
Guy,
Appreciate the input as always. The strange part of the story is the CSP's
literally fell of the board as clearly shown in the photos now up on Steve's
site. Stranger is the fact the CBGA soldered perfectly and was right next to
the CSP/DSP's.
You can see the solder paste columns as if the stencil was just lifted off
the board. Stranger still, they didn't wet to the CSP balls.
I do have a bit of criticism about your bug findings. I have bugs in my cave
that solder wet rather well. You ever seen these little bbb's (bastard bitch
bugs) some asshole introduced to this country to eat some other crap bug or
larva. You know, the little brown bitch bastard ones looking like lady bugs
but are brown. They're insidious and the winter cold don't kill them though
they do come in out of the cold and bite hell out of you. They solder great.
MoonMan with bugs but no way to RID myself of them.
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Date: Wed, 27 Feb 2002 10:03:10 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MLB - spotwelding
X-To: "Mike Holst." <[log in to unmask]>
Mike,
I'm missing something or have grown way to old. Why weld anything? Don't we
still float the preg with pins in slots, etc?
Misregistration is mostly caused by improper, nonhomogeneous core and preg
selections introduced as too many up books in a press opening that may or
may not be properly calibrated and is not properly managed. In a well
managed relamination process, a very predictable flow front is effected so
everything moves associatively. Therefore, without confining the dynamics of
the process, there is little misregistration.
I need to go back to school on this, I guess, or not.
MoonMan
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Date: Wed, 27 Feb 2002 11:18:03 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
I think Guy got it right. Relooking at the recently posted board level
photos and comparing them with the CSP images, it seems clear the solder
balls were detached and became part of the board columns. Hence, the
following exchange:
How did you get those images? Looks like the image of a collapsed solder
ball with the BGA removed.
Were the CSPs installed using solder paste or tacky flux? Are we looking at
the bottom of the CSP or the board?
My dear friend,
I told you it was really exciting stuff. I got the images with my trusty
rusty Intel Play microscope after cutting the hell out of the printed circus
board.
You are looking at the PCB surface and what I believe to be solder paste,
but how can that be when adjacent component solder joints were formed but
cold. The solder balls never wetted or collapsed. The solder columns still
are visible with solder balls seemingly in suspension unless I don't know
about that which I'm talking.
As the device solder balls did detach, maybe we are looking at them and not
just solder paste. That's why I posted them so informed folks like you could
rationalize the situation.
Keep the information coming. Also, revisit the CSP photos taken from the
bottom of the device showing clearly they detached.
What's going on here?
MoonMan
Guy,
I just went back and looked again. You have to be right. The balls detached
from the device and are shown present on the board's solder termination
areas.
Thanks for the observation,
MoonMan
So, back to ground zero. How could those balls detached in such a way? TI
has promised the problem is solved though they admitted too thick an IMC
layer was to blame
MoonMan
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Date: Wed, 27 Feb 2002 09:50:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: 'Flip-over' Assembly Fixtures?
MIME-Version: 1.0
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I'm looking for a 'flip-over' assembly fixture for large PCBs (20" x
18"). I need something that can have a board inserted, hand load a
quantity of through-hole parts, close a cover and flip over to solder
the parts manually. I've found ones that handle 16" wide boards but
none wider. Does anyone know of a source for this type of fixture?
Thanks in advance.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Wed, 27 Feb 2002 14:54:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Tontis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Tontis <[log in to unmask]>
Subject: warranty
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I tried to look in the archive for anything relating to warranty
issues and could not find anything. So with that said my company had a board
design built a year ago, we are now getting boards sent back because of
contamination issues. There are over 120 boards that show signs of active
flux contamination some next to fine pitch parts and some all over the
board. The board vendor has been contacted, the response from them was the
warranty is up and we can not issue a RMA#. Has anyone ever had to face this
issue before and if so how was it handled?
Thank you
Ted Tontis C.I.D.
Engage Networks
316 N. Milwaukee Street
Suite 214
Milwaukee WI, 53202
PH 414-273-7600 ext. 7607
FX 414-273-7601
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Date: Wed, 27 Feb 2002 15:53:18 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
MIME-Version: 1.0
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Hi MoonMan,
Solder columns are made of high-melt solder.
Werner
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Date: Wed, 27 Feb 2002 15:06:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: [log in to unmask]
I know sir Werner. What caused these?
MoonMan
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Date: Wed, 27 Feb 2002 14:57:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mr. Leslie A. Pollak" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mr. Leslie A. Pollak" <[log in to unmask]>
Subject: Solder Projections
Hi,
Could soemone tell me what causes solder projections or what we call
icicles.
Or point us to IPC documentation that would help us.
Thanks
Mr. Leslie A. Pollak
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Date: Wed, 27 Feb 2002 16:18:05 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: warranty
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If this is an assembly, why would you go back to the bare board supplier?
Wouldn't you go back to the assembler?
Susan Mansilla
Robisan Lab
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Date: Wed, 27 Feb 2002 22:45:18 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Zweigart, Siegmund" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Zweigart, Siegmund" <[log in to unmask]>
Subject: Via in Pad
MIME-Version: 1.0
Content-Type: text/plain
Hello
In the moment we are planing to do an evaluation about VIA in Pad for OCC
finished boards.
Did anybody try the same?
What are the critical Points for 0603 or 0402 passives?
Is the sucking of solderpaste from the top to the bottom side during Reflow
an issue?
Any special requirements regarding profiles?
Thanks for your help
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Date: Wed, 27 Feb 2002 18:34:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Solder Projections
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Mr. Pollak,
High copper content in your solder can cause spikes... or amateur hand
solderers like myself are very good at forming spikes. There may be other
reasons that some of our "older" regulars can contribute.
I looked in IPC/EIA J-STD-006 and it lists max impurity levels for different
elements, but does not give reasons why they are individually considered
impurities. You may be able to find this info from some of the more common
reference books for our industry, the titles of which you can find by doing
a search of the TechNet archives from the IPC homepage.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Mr. Leslie A. Pollak [mailto:[log in to unmask]]
Sent: February 27, 2002 3:57 PM
To: [log in to unmask]
Subject: [TN] Solder Projections
Hi,
Could soemone tell me what causes solder projections or what we call
icicles.
Or point us to IPC documentation that would help us.
Thanks
Mr. Leslie A. Pollak
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Date: Wed, 27 Feb 2002 19:22:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Via in Pad
X-To: [log in to unmask]
No special concerns but not doing it unless the vias are micro and/or
plugged or capped.
MoonMan
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Date: Wed, 27 Feb 2002 21:17:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Leland Woodall <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leland Woodall <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Brian,
Can you elaborate on the dangers of conformally coating a no-clean product?
I would have thought, in my ignorance, that processing in that manner would
be most preferable. What kind of problems could or would one expect?
Thanks,
Leland Woodall
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Wednesday, February 27, 2002 2:03 AM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Jim
Quite an interesting one this, with implications beyond the obvious.
Firstly, despite what Mike says, I think most of us would agree that a
properly cleaned board, even soldered with a reasonably aggressive flux,
is less likely to be unreliable than an uncleaned one, under some given
conditions. Experience has proved this.
Then there are some "no-clean" fluxes/pastes which are REALLY dangerous,
so it is easy to imagine that someone could have been bitten.
However, I strongly suspect, reading between the lines, that this notion
may apply to conformally-coated boards. Here, there is a distinct
problem with "no-cleans" unless the homework is VERY carefully done and
the process is constantly requalified, including checking the
contamination on every batch of incoming components. Personally, I would
never advise a client to use "no-clean" products if the products were to
be coated. It could be a time bomb waiting to go off under your feet
even years later (especially, no pun, with armament electronics which
may be stored for 15 years and then used for the first and only time
during a period of a few minutes).
Finally, a PCB design which is optimised for use with a mild "no-clean"
wave-soldering flux or paste would be better redrafted if it were to be
changed to a less mild flux and cleaned. Many such boards would be
totally unsuitable for cleaning and the result may be worse than ever,
in terms of reliability, if there were no re-design.
I would therefore want the rumour to be substantiated before any action
was to be taken.
Brian
Jim Jenkins wrote:
>
> Hi everybody,
>
> I was just approached by one of our engineers whose customer told her that
> the Air Force has issued a directive disallowing the use of no-clean
fluxes
> on any of their hardware. The customer is flowing down that requirement
to
> us. Do any of you know of this directive or what they could be referring
to?
>
> Thanks,
>
> Jim
>
>
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Date: Wed, 27 Feb 2002 21:25:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Leland Woodall <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
I am also facing the decision of whether to choose no-clean/no wash
process for boards to be conformally coated at customer's site. I am
conducting full qualifying run to confirm the compatibility between
paste/flux and coating material. Unfortunately you rarely can get
confirmation from flux manufacturer about reliability of conformal
coated over noclean boards.
Can anyone share their experience on the risk, precaution steps, and
process control for conformal coat over noclean?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Leland Woodall
Sent: February 27, 2002 6:18 PM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Brian,
Can you elaborate on the dangers of conformally coating a no-clean
product?
I would have thought, in my ignorance, that processing in that manner
would
be most preferable. What kind of problems could or would one expect?
Thanks,
Leland Woodall
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Wednesday, February 27, 2002 2:03 AM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Jim
Quite an interesting one this, with implications beyond the obvious.
Firstly, despite what Mike says, I think most of us would agree that a
properly cleaned board, even soldered with a reasonably aggressive flux,
is less likely to be unreliable than an uncleaned one, under some given
conditions. Experience has proved this.
Then there are some "no-clean" fluxes/pastes which are REALLY dangerous,
so it is easy to imagine that someone could have been bitten.
However, I strongly suspect, reading between the lines, that this notion
may apply to conformally-coated boards. Here, there is a distinct
problem with "no-cleans" unless the homework is VERY carefully done and
the process is constantly requalified, including checking the
contamination on every batch of incoming components. Personally, I would
never advise a client to use "no-clean" products if the products were to
be coated. It could be a time bomb waiting to go off under your feet
even years later (especially, no pun, with armament electronics which
may be stored for 15 years and then used for the first and only time
during a period of a few minutes).
Finally, a PCB design which is optimised for use with a mild "no-clean"
wave-soldering flux or paste would be better redrafted if it were to be
changed to a less mild flux and cleaned. Many such boards would be
totally unsuitable for cleaning and the result may be worse than ever,
in terms of reliability, if there were no re-design.
I would therefore want the rumour to be substantiated before any action
was to be taken.
Brian
Jim Jenkins wrote:
>
> Hi everybody,
>
> I was just approached by one of our engineers whose customer told her
that
> the Air Force has issued a directive disallowing the use of no-clean
fluxes
> on any of their hardware. The customer is flowing down that
requirement
to
> us. Do any of you know of this directive or what they could be
referring
to?
>
> Thanks,
>
> Jim
>
>
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Date: Thu, 28 Feb 2002 09:10:41 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: No No-clean?
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
OK, there are three issues at stake here.
1) The residues from "no-clean" products (and yes, there are residues -
always) may impede adhesion of the coating layer to the substrate
2) Many of the "no-clean" products rely on a slow sublimation of the
residues from the surface, requiring a few weeks to achieve optimal
performance. Sealing these in will prevent this from happening.
3) By definition, all soldering fluxes are ionic. Some may be slightly
hygroscopic, as may also the metal salts formed by the reaction between
the oxides and the flux acids. Some of the rheological additives to
pastes may leave slightly hygroscopic residues. This is an open
invitation to promote vesication, with a potentially very serious loss
of reliability. At the very least, a good "pressure cooker" test is a
must both in qualifying the process and at frequent intervals to check
that it stays on the rails.
I am not saying that coating should never be applied over flux residues.
What I am saying is that anyone who does it without a really thorough
qualification and process control is being professionally irresponsible,
if the products must be reliable. After all, conformal coating is really
a high-rel process and "no-clean" chemistry started as a low-rel
process, creeping up to its present status of medium-rel. It is
therefore really a paradoxal conflict to try and combine the two, likely
to present the disadvantages of both processes with none, or few, of the
advantages.
Brian
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Date: Thu, 28 Feb 2002 17:17:03 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Earl,
What a neat castration job!
Observations:
1) Ball adhesion to the package only seems to have been at the perimeter.
2) Some voiding but nothing too detrimental.
3) Focus on the board-end SJ's isn't so good, but although they look well
wetted and formed, they look a bit barrel-shaped themselves, not filleted
nicely to the balls (unless that's an optical illusion or trick of the
light).
4) Lots of barnacles and whiskers appearing on the balls in picture #3.
5) The bottom right quarter of picture 1 shows a reddish glow - is this
reflection of the hell fire that caused this problem?
6) The brown deposits among the balls in picture 1, I took to be substrate
remains, but the close-up view in picture 2 makes me doubt that.
Questions:
1) Is this the only thermally massive component on the board, or are there
others? How are they distributed?
2) What thermal profiling, temp cycling, rework has the board been through?
3) How old is the BGA?
4) Do you know what the brown deposits are?
5) Under what conditions was the BGA so summarily neutered? Vibration?
Sudden shock (e.g. dropped)? It just came off in my hand, honest!?
6) Are these eutectic balls (PBGA's) or HMP (CBGA's)?
7) Is the soldering process clean or no-clean?
8) Is the board double sided, and subjected to two reflows? And are there
then and through-hole parts that are wave soldered? How many times has this
poor specimen been through the oven, or at least near-reflow temp?
Opinion:
Neither very academic, nor drawn from the wisdom and knowledge of great
experience, but you may have the result of a component that's been around a
while (IMC build-up between balls and component body, causing poor adhesion
to the substrate) being soldered using a profile that may be too low temp
for too long.
I had a couple of boards last year that failed vibration testing very
quickly and the balls looked a bit like those in the pics - maybe not quite
so 'warty' but showing as very coarse and full of striations as if
partially reflowed and solidified again.
Have you done any sections on this one yet? An ESM picture of the result
might be interesting, especially at the interfaces.
Peter
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] REALLY EXCITING STUFF AND A
ORG> BUG IN MY CAVE
02/27/02
10:57 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hey Earl!
The pic's are up! Go to:
http://www.stevezeva.homestead.com
(I spelt it right this time...hehehe)
-Steve Gregory-
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Thu, 28 Feb 2002 09:25:02 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Reid, Lorraine" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Reid, Lorraine" <[log in to unmask]>
Subject: Re: No No-clean?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
I'm not an expert in this but have had some experiences of this in
recent months, as we've had problems with applying conformal coating
over boards assembled with a "no-clean" process.=20
Our customer had decided to use conformal coating as extra insulation in
HV areas of the board ,so the coating was selectively sprayed over
roughly half of the PCBA area. Basically the coating didn't adhere to
the board well enough, and it was noticed that we were getting arcing
between adjecant points when high voltages were applied to the circuit.
We were using Electrolube coatings, and after much discussion with them,
they advised us that the coating wouldn't adhere properly if the boards
weren't cleaned. We asked our board assembler to change processes, the
boards are now throughly cleaned before the coating is applied, and the
problems are much reduced.
Another supplier of coatings did take a different view, suggesting that
clean boards weren't essential to the process, but our experience seemed
to indicate that, in this application at least, cleaning the board prior
to coating was essential.
Suggest you discuss this with the coating supplier to get their advice.
Lorraine
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: 28 February 2002 05:26
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
I am also facing the decision of whether to choose no-clean/no wash
process for boards to be conformally coated at customer's site. I am
conducting full qualifying run to confirm the compatibility between
paste/flux and coating material. Unfortunately you rarely can get
confirmation from flux manufacturer about reliability of conformal
coated over noclean boards.
Can anyone share their experience on the risk, precaution steps, and
process control for conformal coat over noclean?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Leland Woodall
Sent: February 27, 2002 6:18 PM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Brian,
Can you elaborate on the dangers of conformally coating a no-clean
product?
I would have thought, in my ignorance, that processing in that manner
would
be most preferable. What kind of problems could or would one expect?
Thanks,
Leland Woodall
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Wednesday, February 27, 2002 2:03 AM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Jim
Quite an interesting one this, with implications beyond the obvious.
Firstly, despite what Mike says, I think most of us would agree that a
properly cleaned board, even soldered with a reasonably aggressive flux,
is less likely to be unreliable than an uncleaned one, under some given
conditions. Experience has proved this.
Then there are some "no-clean" fluxes/pastes which are REALLY dangerous,
so it is easy to imagine that someone could have been bitten.
However, I strongly suspect, reading between the lines, that this notion
may apply to conformally-coated boards. Here, there is a distinct
problem with "no-cleans" unless the homework is VERY carefully done and
the process is constantly requalified, including checking the
contamination on every batch of incoming components. Personally, I would
never advise a client to use "no-clean" products if the products were to
be coated. It could be a time bomb waiting to go off under your feet
even years later (especially, no pun, with armament electronics which
may be stored for 15 years and then used for the first and only time
during a period of a few minutes).
Finally, a PCB design which is optimised for use with a mild "no-clean"
wave-soldering flux or paste would be better redrafted if it were to be
changed to a less mild flux and cleaned. Many such boards would be
totally unsuitable for cleaning and the result may be worse than ever,
in terms of reliability, if there were no re-design.
I would therefore want the rumour to be substantiated before any action
was to be taken.
Brian
Jim Jenkins wrote:
>
> Hi everybody,
>
> I was just approached by one of our engineers whose customer told her
that
> the Air Force has issued a directive disallowing the use of no-clean
fluxes
> on any of their hardware. The customer is flowing down that
requirement
to
> us. Do any of you know of this directive or what they could be
referring
to?
>
> Thanks,
>
> Jim
>
>
------------------------------------------------------------------------
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Date: Thu, 28 Feb 2002 04:58:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: REALLY EXCITING STUFF AND A BUG IN MY CAVE
X-To: [log in to unmask]
Peter,
Sorry I don't have much time now to answer all your questions. Some I can't
anyway.
However, Steve's site has all the photos of this mess posted as CSP1 - CSP4,
Kester Reflow profile, Successful by Kerry profile, TI no balls CSP board
bottom, and the ones you are referring to. The TI CSP board bottom photo
shows clearly the mating male view where the balls came off and the balls
are shown in the pics to which you refer. The CSP1 - CSP4 images are the
x-sections with CSP4 supposedtly showing the thick IMC formation or so says
TI and Collins labs.
The C clamp photo no longer is up. I thought the folks here were only
joking, but they tell me 4 of 7 of these parts just fell off the board with
little or no interference.
There are several other BGA's on the board and one is a ceramic type that
soldered very well. TI supplied these parts as the X version. This means
they were prototypes and they admitted, after these occurences, one of their
suppliers, whatever that means, had problems with ball attachment - no joke
there.
We have some new parts in now. However, we are going to a new assembler with
older, but not X variety, parts. I ordered new boards as well so
solderability and other MLB issues will be resolved.
I do appreciate the careful observations. I'll talk more when more time is
available.
Earl
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Date: Thu, 28 Feb 2002 06:59:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solder Projections
X-To: "Mr. Leslie A. Pollak" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Electrovert once published a wave soldeing troubleshooting chart. I have a
ragged old copy. It lists many poential causes of the condition.
Process Related: solder temp too low, wave height too low, wave uneven,
solder contaminated (use J-STD-001 to evauate solder purity J-STD-006 is
intended for new alloy material), preheat temp too high or too low, flux
contaminated, flux specific gravity too low, flux no nolonger active, flux
not making contact, flux foam head low, flux uneven, flux blow-off
excessive, pallet too hot, conveyor speed high, conveyor vibration, conveyor
angle low, early removal of board, board not seated properly.
Assembly Related: board contamination, component contamination, component
leads too long, improper board handling.
Board Fab Related: Board Oxidized.
Design Related: Pallet design, large plane on solder side, large unfilled
holes.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mr. Leslie A. Pollak
> Sent: Wednesday, February 27, 2002 3:57 PM
> To: [log in to unmask]
> Subject: [TN] Solder Projections
>
>
> Hi,
>
> Could soemone tell me what causes solder projections or what we call
> icicles.
>
> Or point us to IPC documentation that would help us.
>
> Thanks
> Mr. Leslie A. Pollak
>
> ------------------------------------------------------------------
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>
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Date: Thu, 28 Feb 2002 06:59:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: warranty
X-To: Ted Tontis <[log in to unmask]>
In-Reply-To: <FE89B36841C1D411AB9D0002555830D739DB7D@BARRY>
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There was a discussion on arbitration last year (2001) that may help you.
IMHO you may have discovered the difference referencing J-STD-001C on a
procurement agreement and referencing IPC-A-610C.
I feel your pain.
Guy Ramsey
Senior Technician / Instructor
<outbind://56/www.aciusa.org>
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Ted Tontis
> Sent: Wednesday, February 27, 2002 3:54 PM
> To: [log in to unmask]
> Subject: [TN] warranty
>
>
> I tried to look in the archive for anything relating to warranty
> issues and could not find anything. So with that said my company
> had a board
> design built a year ago, we are now getting boards sent back because of
> contamination issues. There are over 120 boards that show signs of active
> flux contamination some next to fine pitch parts and some all over the
> board. The board vendor has been contacted, the response from them was the
> warranty is up and we can not issue a RMA#. Has anyone ever had
> to face this
> issue before and if so how was it handled?
>
> Thank you
>
> Ted Tontis C.I.D.
> Engage Networks
> 316 N. Milwaukee Street
> Suite 214
> Milwaukee WI, 53202
> PH 414-273-7600 ext. 7607
> FX 414-273-7601
>
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>
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Date: Thu, 28 Feb 2002 05:20:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Nemcik <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Nemcik <[log in to unmask]>
Subject: Electroless nickel to electroplated copper separation
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Can somebody shed some light on possible causes of adhesion problems between electroless nickel and electroplated copper, that occur at random intervals? Analysis of both baths show they are in order, and the nickel plating is not permitted to dry or passivate before going into the copper.
Thanks in advance
Pete
---------------------------------
Do You Yahoo!?
Yahoo! Greetings - Send FREE e-cards for every occasion!
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<FONT size=2>
<P>Can somebody shed some light on possible causes of adhesion problems between electroless nickel and electroplated copper, that occur at random intervals? Analysis of both baths show they are in order, and the nickel plating is not permitted to dry or passivate before going into the copper.</P>
<P>Thanks in advance</P>
<P>Pete</P></FONT><p><br><hr size=1><b>Do You Yahoo!?</b><br>
<a href="http://greetings.yahoo.com">Yahoo! Greetings</a> - Send FREE e-cards for every occasion!
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Date: Thu, 28 Feb 2002 08:54:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: : electronic waste
X-To: [log in to unmask]
MIME-Version: 1.0
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>San Jose 26. Feb.(sda)
>Used computers and other electronic equipment exported as electronic waste from the USA
threaten the human lives and >the environment in China and India according to a study. The
survey has been published by the environmental groups >Silicon Valley Toxic Coalition and
Basel Action Network last Monday in San Jose. As an example a region in Southern >China has
been mentioned where approx. 100'000 workers together with their families disassemble old
computers and are >exposed to poisonous substances. The electronic waste has already
contaminated the groundwater to such an extend that >drinking water has to be brought to the
site. Large amounts of contaminated waste and plastics are burned and >deposited in farmlands
and irrigation channels. According to the study the US are the only industrialised country
>that does not comply with an international treaty that bans the export of hazardeous waste to
developping countries.
>Maybe we should not only look on the ban of lead in the WEEE but also on the more than
necessary regulations how >electronic waste has to be treated. The sadest thing to me though is
the fact that we need regulations because many >people in industry act irresponsible and
without any common sense if they are not forced legally to care.
What's really unfortunate is the amount of emotional claptrap that's fostered off
as science. There is nothing inherently dangerous about electronic waste. What does
appear to be dangerous, is simple mishandling, and careless disposal.
Using the faulty logic that the Silly Valley Toxic Coalition apparently uses, if
people dumped junk cars into their water supply, the auto industry would be responsible
for generating "toxic waste".
The real "toxic waste" is the junk science quoted as fact.
IMHO, of course!
John
[log in to unmask]
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Date: Thu, 28 Feb 2002 08:06:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: No No-clean?
Mime-Version: 1.0
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consider changing to a mail reader or gateway that understands how to
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Not to use was explained to me as such: No clean leaves a residue that =
with heat can reliquify and then start to move which will cause an air =
bubble where the flux was originally at and now isn't. =20
So the question comes to: does and at what temperature would it take for =
the no clean residue you are using to reliquify if it does at all? Then =
if it does liquify is there any activation that is occurring? Does the =
coating withstand the proper adhesion for the application if the air =
bubble does occur? =20
Kathy=20
--=_6835277B.CEAFC22E
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<META content="MSHTML 6.00.2713.1100" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Not to use was explained to me as such: No clean leaves a residue that
with heat can reliquify and then start to move which will cause an air bubble
where the flux was originally at and now isn't. </DIV>
<DIV> </DIV>
<DIV>So the question comes to: does and at what temperature would it take
for the no clean residue you are using to reliquify if it does at all?
Then if it does liquify is there any activation that is occurring? Does
the coating withstand the proper adhesion for the application if the air bubble
does occur? </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 28 Feb 2002 08:18:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No No-clean?
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Well, as Brother Brian copied me on his response about no-cleans and
conformal coat, I took it as a subtle hint to throw my two
cents/shillings/micro-Euros into the mix.
I am of the general opinion that you can make almost any material set do
what you want with sufficient time and attention to the selection of the
materials and the associated process parameters. I know of companies out
there who successfully use no-clean assembly processes and conformally coat
over the residues. Delco Electronics is one such company. They make more
assemblies in a month than Rockwell makes in a year. Many of their product
lines are no-clean and they coat over them. And the under-the-hood
environment of a car is a pretty nasty environment with lots of thermal
cycles, humidity, and salt environment (if you are from the north). I know
that they put a tremendous amount of time into the selection of the flux
and the selection of the process parameters, such that conformal coat would
adhere to whatever they left on the board. There are other companies as
well that manufacturer to Class 3 high-reliability standards that use
no-clean and conformally coat. And all of them spent a lot of money tuning
the process. As Brian said, the person who tries to combine these two
without diligent process control and process qualification is
irresponsibile. I would agree.
Keep in mind what a low solids flux residue represents. The amount of
residue depends on how much you apply and the thermal reflow profile you
use. If you throw huge amounts of 5% flux on an assembly with lots of
entrapment sites, then expect to have lots of residue after soldering. If
you lightly spray on a 1% flux, using no more than you absolutely must
have, and you tune your reflow accordingly, then most or all may flash off
in reflow. Secondly, the flux residues after soldering will have different
characteristics, depending on how you processed the flux. A low solids
flux (LSF) must reach some minimum activation temperature before the
residues fully react and reach the "benign" stage. If the flux is not
fully reacted, then portions of the high molecular weight high boiling
point solvents remain, making the residues mildly conductive. This may be
why Lorraine Reid saw arcing in a high voltage application. The flux
residues may not have been fully reacted, and so did not have the same
dielectric strength as a fully reacted residue. I have seen this failure
mechanism numerous times where the assembler did not fully realize that
throwing more flux at the assembly was not a wise thing to do. One
critical mistake that many assemblers, new to the field of no clean make,
is that they do not understand how a LSF works. With a water soluble flux,
you have a chemical etching that goes on from the point of application to
the point of reflow. For a LSF, you do not get fluxing action until you
drive off the carrier solvent and the crystals of the weak organic acids
(usually one or more dicarboxylic acids) melt, which then provide the oxide
stripping mechanism. So OA flux experience tells an operator that if you
have soldering problems, throw more flux at the assembly, but with a LSF,
if the board reaches the wave wet, you get no oxide removal, so the
solution is to throw less flux at the problem. For the same reasons, you
don't want to squirt liquid LSF on a board as part of hand soldering. The
flux goes a lot farther than the heat from the soldering iron reaches.
That isopropanol carrier takes that flux places you would not believe.
Keep in mind that flux manufacturers can work to tailor the properties of
the residual flux. One example that I know of is Indium SMQ-92 and
SMQ-92J. The residues in the 92J are harder and glossier than those of the
92. Indium did that to make the 92 easier to penetrate in probe testing.
I have found it useful to look at the flux residues as if it were a
material that I design into the board, rather than a process effect. If I
have a great big honkin' electrolytic capacitor, I know that I have
laminate between the through-holes, and solder mask between the through
holes. I would evaluate both the laminate and the solder mask to determine
if they had sufficient dielectric strength for the application. Now, add
to that a layer of flux residue remaining after processing. Does that flux
residue have adequate dielectric strength for the application. Then, if it
does in the fully reacted state, what kinds of processing controls do I
need to have in place in order to make sure that the flux residue reaches
that dielectric state during processing? This is where I see many no-clean
assemblers failing. They fail to take into account the residues as a
dielectric material, affecting dielectic strength, cross talk, impedance,
rise time and propogation in RF, etc., or they fail to make their assembly
process robust enough against these factors.
As Brian pointed out, many of the LSF residues are hydroscopic in nature,
which has to be remembered when considering conformal coating. If you have
a case where you have unreacted flux residues, or a board that has an
unacceptable level of ionic contamination on it, conformal coating will NOT
help you.
I had a number of clients when I was at CSL that had problems identified on
their boards. Maybe it was the unreacted flux, maybe dirty bare boards,
maybe dirty assemblies. Some did not want to spend the time or money to
attack the true cause of the problem, which were the ionic residues. Their
solution was to slap a layer of conformal coating over the problem and ship
product. Of course, choosing the cheapest solution, the acrylic coatings,
which have the higher water permeability of them all. If you remember the
old commercial with the auto mechanic "You can pay me now or pay me later",
that was what happened. Nine months to a year later, they came back saying
"Uhhhhhhh, it didn't work". Conformal coating only buys you time since
moisture WILL go through the coating.
You can't really fault the coating manufacturer either. Assemblers often
expect the coating manufacturers to make a coating that sticks to any
surface, no matter what the assemblers have done to the board, and for low
cost. Most components have plastic release agents build in, most solder
masks have smooth surfaces that may be difficult to adhere to, and now you
throw in residues with a highly variable surface tension, and you have an
adhesion nightmare. You have this nighmare in fully cleaned assemblies
too, so don't be too quick to blame the coating for not sticking to your
residues.
If you have a choice in conformal coating, I would recommend a urethane, I
would recommend it over an acrylic. The acrylic is simply a dried film
over the surface, with limited chemical interaction to the substrate in
terms of bonding. In addition, you might also have the solvents in the
coating soften and attack the LSF residues, changing the properties (keep
that in mind). The urethanes or epoxies tend to chemically react better
with the substrates, forming a better bond, but they are also more
difficult to rework. If your manufacturing process is mature and
controlled, the tech staff of the coating manufacturer should be able to
help you choose a coating for good adhesion. On the other hand, if your
process is not controlled, you will probably get the generic "Well, the
assembly has to be clean before you coat" response.
So, if you are working with a no-clean assembly processes, you should be
doing the following:
1. Working to understand the dielectric properties of the residues
2. Determine what your processing windows need to be in order to make sure
the flux residues are fully reacted
3. Minimize the amount of flux you are applying
4. Work to use a lower percent solids in the process to leave fewer
residues on the board
5. Select your flux for desirable properties for conformal coat adhesion.
6. Tune your process to get the residue properties you want (in
conjunction with #2), such as a matte finish rather than a hard glossy
7. Select your conformal coating so that the solvent system is compatible
with the flux residues and so that the coating sticks to the residues.
As this message is nearing "the Ellis Zone", I will wrap up by saying that
you CAN manufacture hi-rel equipment with no-clean, you CAN make it
reliable for long life, you CAN make coating stick to it for the design
life, IF IF IF you have done your homework and know what you are doing.
Doug Pauls
Rockwell Collins
(And all done without Mountain Dew, which will be immediately remedied)
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Date: Thu, 28 Feb 2002 16:12:49 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mike Holst." <[log in to unmask]>
Subject: Re: MLB - spotwelding
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Earl Moon,
Thank you for the response and input.
Unfortunately, I can't comment on what other people are doing, we
practice our craft in relative isolation at the southern extreme of
Africa.
We assemble multilayers on lightweight registration fixtures on
multiline pins, then 'spotweld' the edges (while still on the fixture),
to hold the layer / layer position during pressing (off the fixture). It
is assumed that the prepreg in these 'spots' has sufficiently gelled
or cured to hold their position. There is no use of heavy caul plates
/ pins etc. only 2mm separators in the press (with packing to
achieve correct time / temp profile).
This does work great up to 8 layers, OK for 10 but then gets a bit
wobbly from 12 up. I was hoping that someone else had already
done their homework on this one so that I could crib the answers
without having to do the hard work myself. We currently limit
ourselves to offer MLB's only up to 10 layers, but would like to go
the next step - customer demand!
Mike.
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Date: Thu, 28 Feb 2002 09:39:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
MIME-Version: 1.0
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Pete:
I am, unfortunately, becoming too knowledgeable about this subject
area...ahem.
To confirm my understanding, you are putting EN down on to Electroplated
Copper?
So, you use a catalyst. Look at your catalyst activity. Too much catalyst
can cause this problem. What can cause too much catalyst activity will
depend on which catalyst you are using, but this is a key area to
investigate.
Rudy Sedlak
RD Chemical Company (Yeah, you guessed it, we sell catalyst for the EN
process)
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Pete:<BR>
<BR>
I am, unfortunately, becoming too knowledgeable about this subject area...ahem.<BR>
<BR>
To confirm my understanding, you are putting EN down on to Electroplated Copper?<BR>
<BR>
So, you use a catalyst. Look at your catalyst activity. Too much catalyst can cause this problem. What can cause too much catalyst activity will depend on which catalyst you are using, but this is a key area to investigate.<BR>
<BR>
Rudy Sedlak<BR>
RD Chemical Company (Yeah, you guessed it, we sell catalyst for the EN process)</FONT></HTML>
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Date: Thu, 28 Feb 2002 09:56:18 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: Solder Projections
X-To: Guy Ramsey <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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A document which may help you out is the IPC-TR-460A, Trouble Shooting
Checklist for Wave Soldering of Printed Wiring Boards. If your in to surface
mount the document is IPC-S-816 SMT Process Guideline and Checklist.
These documents should be able to help you out.
Good Luck,
Leo Lambert
EPTAC Corp.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
Sent: Thursday, February 28, 2002 6:59 AM
To: [log in to unmask]
Subject: Re: [TN] Solder Projections
Electrovert once published a wave soldeing troubleshooting chart. I have a
ragged old copy. It lists many poential causes of the condition.
Process Related: solder temp too low, wave height too low, wave uneven,
solder contaminated (use J-STD-001 to evauate solder purity J-STD-006 is
intended for new alloy material), preheat temp too high or too low, flux
contaminated, flux specific gravity too low, flux no nolonger active, flux
not making contact, flux foam head low, flux uneven, flux blow-off
excessive, pallet too hot, conveyor speed high, conveyor vibration, conveyor
angle low, early removal of board, board not seated properly.
Assembly Related: board contamination, component contamination, component
leads too long, improper board handling.
Board Fab Related: Board Oxidized.
Design Related: Pallet design, large plane on solder side, large unfilled
holes.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mr. Leslie A. Pollak
> Sent: Wednesday, February 27, 2002 3:57 PM
> To: [log in to unmask]
> Subject: [TN] Solder Projections
>
>
> Hi,
>
> Could soemone tell me what causes solder projections or what we call
> icicles.
>
> Or point us to IPC documentation that would help us.
>
> Thanks
> Mr. Leslie A. Pollak
>
> ------------------------------------------------------------------
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Date: Thu, 28 Feb 2002 08:57:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: MLB - spotwelding
X-To: "Mike Holst." <[log in to unmask]>
Mike,
I really appreciate your situation. I've just never even thought of doing it
the way you describe. Glad it works for you to a point.
Instead of doing real work in board shops anymore, I just kind of hang
around during evaluation and qualification processes. All I see is pretty
standard stuff using vacuum presses, or not, preg punches, with attendant
hardware as caul plates, separatory sheets, release materials, thermal lag
materials, tooling pins, details precisely aligned via the pins, and prepreg
slotted to float during the relamination process.
I'm not being sarcastic, but is there a reason you're not doing the above?
Again, I might be out of touch but I've recently worked with 52 and 40 layer
boards with relative ease and good quality/yields when the right design
rules are applied and processes are managed effectively. I, and many others,
during the military days 20 plus years ago were doing many designs over 24
layers even up to 60 in a few cases.
Wish I could help more, but I feel I'm missing something.
Enjoy,
Earl
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Date: Thu, 28 Feb 2002 09:10:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Tontis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Tontis <[log in to unmask]>
Subject: Re: warranty
X-To: Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Guy,
Where can I find information on the discussion you mentioned? This
board was sent out before I became involved in the design and assembly of
our circuit boards. Before me no one knew what IPC stood for or the benefits
of understanding, and utilization of the documents IPC has to offer.
I am trying to find out if anything can be done or if this is going
to be a very painful lesson for our company.
Regards,
Ted
-----Original Message-----
From: Guy Ramsey [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 5:59 AM
To: [log in to unmask]
Subject: Re: [TN] warranty
There was a discussion on arbitration last year (2001) that may help you.
IMHO you may have discovered the difference referencing J-STD-001C on a
procurement agreement and referencing IPC-A-610C.
I feel your pain.
Guy Ramsey
Senior Technician / Instructor
<outbind://56/www.aciusa.org>
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Ted Tontis
> Sent: Wednesday, February 27, 2002 3:54 PM
> To: [log in to unmask]
> Subject: [TN] warranty
>
>
> I tried to look in the archive for anything relating to warranty
> issues and could not find anything. So with that said my company
> had a board
> design built a year ago, we are now getting boards sent back because of
> contamination issues. There are over 120 boards that show signs of active
> flux contamination some next to fine pitch parts and some all over the
> board. The board vendor has been contacted, the response from them was the
> warranty is up and we can not issue a RMA#. Has anyone ever had
> to face this
> issue before and if so how was it handled?
>
> Thank you
>
> Ted Tontis C.I.D.
> Engage Networks
> 316 N. Milwaukee Street
> Suite 214
> Milwaukee WI, 53202
> PH 414-273-7600 ext. 7607
> FX 414-273-7601
>
> ------------------------------------------------------------------
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Date: Thu, 28 Feb 2002 10:12:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1C06A.5168DCCC"
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------_=_NextPart_001_01C1C06A.5168DCCC
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Pete,
Do you have analysis that shows the separation you are experiencing is
an adhesion of the electroless nickel to the electoplated copper? I'm
assuming you are seeing some separation of a part soldered to a ENIG
board (Cu/ENi/IAu). If you are seeing a "clean - flat" separation I'd
look to see if it is a brittle fracture beween an IMC and the ENi.
=20
Regards,=20
George=20
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff=20
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059=20
-----Original Message-----
From: Peter Nemcik [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:21 AM
To: [log in to unmask]
Subject: [TN] Electroless nickel to electroplated copper separation
Can somebody shed some light on possible causes of adhesion problems
between electroless nickel and electroplated copper, that occur at
random intervals? Analysis of both baths show they are in order, and the
nickel plating is not permitted to dry or passivate before going into
the copper.
Thanks in advance
Pete
_____ =20
Do You Yahoo!?
Yahoo! <http://greetings.yahoo.com> Greetings - Send FREE e-cards for
every occasion!
------_=_NextPart_001_01C1C06A.5168DCCC
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D666010715-28022002><FONT face=3DArial color=3D#0000ff =
size=3D2>Pete,</FONT></SPAN></DIV>
<DIV><SPAN class=3D666010715-28022002><FONT face=3DArial color=3D#0000ff =
size=3D2> Do you have analysis that shows the separation you are =
experiencing=20
is an adhesion of the electroless nickel to the electoplated =
copper? I'm=20
assuming you are seeing some separation of a part soldered to a ENIG =
board=20
(Cu/ENi/IAu). If you are seeing a "clean - flat" separation I'd =
look to=20
see if it is a brittle fracture beween an IMC and the =
ENi.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT face=3DArial size=3D2>Regards,</FONT> <BR><FONT face=3D"Script =
MT Bold"=20
color=3D#800000 size=3D6>George</FONT> </P>
<P><FONT face=3DArial size=3D2>George M. Wenger (908)-546-4531=20
[log in to unmask]</FONT> <BR><FONT face=3DArial size=3D2>Distinguished =
Member=20
Technical Staff</FONT> <BR><FONT face=3DArial size=3D2>Celiant =
Corporation, FMA Lab,=20
40 Technology Drive, NJ 07059</FONT> </P>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Peter Nemcik=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, 2002 =
8:21=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Electroless =
nickel to=20
electroplated copper separation<BR><BR></FONT></DIV><FONT size=3D2>
<P>Can somebody shed some light on possible causes of adhesion =
problems=20
between electroless nickel and electroplated copper, that occur at =
random=20
intervals? Analysis of both baths show they are in order, and the =
nickel=20
plating is not permitted to dry or passivate before going into the =
copper.</P>
<P>Thanks in advance</P>
<P>Pete</P></FONT>
<P><BR>
<HR SIZE=3D1>
<B>Do You Yahoo!?</B><BR><A href=3D"http://greetings.yahoo.com">Yahoo! =
Greetings</A> - Send FREE e-cards for every =
occasion!</BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1C06A.5168DCCC--
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Date: Thu, 28 Feb 2002 10:09:24 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: warranty
X-To: Guy Ramsey <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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You bring up an interesting point. Your contractual agreement with the
subcontractor who built the boards should have been qualified to verify that
they in fact can build the product to your requirements. Many time people
get boards built by subcontractors and don't understand the impacts of the
manufacturing process on their products either through chemistry being used
or materials and tools being used.
By specifying on your contract what your cleaning requirements were, the
manufacturer would then be able to decide whether or not they could
manufacture the product or let you know what their process could provide so
you could make a decision as to whether or not go with those folks. We see
this quite often with people requiring the use of Low Solid content flux on
their products then asking the manufacturer to clean the product. Many times
incompatibilities are created between the flux chemistries and the cleaning
process and customers become unhappy with the results.
There were a couple of TechNet message within the last couple of weeks that
talked about the use of Low Solid content fluxes and their ability to be
cleaned and conformal coated.
In closing Soldering may appear and feel like a simple process, but there
are so many variables in the equation that many things can and will go wrong
if one goes about using the process in the wrong way.
Hope this helps. If you want to talk some more about this, please send me an
email of line at [log in to unmask]
Regards,
Leo Lambert
EPTAC Corp.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
Sent: Thursday, February 28, 2002 6:59 AM
To: [log in to unmask]
Subject: Re: [TN] warranty
There was a discussion on arbitration last year (2001) that may help you.
IMHO you may have discovered the difference referencing J-STD-001C on a
procurement agreement and referencing IPC-A-610C.
I feel your pain.
Guy Ramsey
Senior Technician / Instructor
<outbind://56/www.aciusa.org>
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Ted Tontis
> Sent: Wednesday, February 27, 2002 3:54 PM
> To: [log in to unmask]
> Subject: [TN] warranty
>
>
> I tried to look in the archive for anything relating to warranty
> issues and could not find anything. So with that said my company
> had a board
> design built a year ago, we are now getting boards sent back because of
> contamination issues. There are over 120 boards that show signs of active
> flux contamination some next to fine pitch parts and some all over the
> board. The board vendor has been contacted, the response from them was the
> warranty is up and we can not issue a RMA#. Has anyone ever had
> to face this
> issue before and if so how was it handled?
>
> Thank you
>
> Ted Tontis C.I.D.
> Engage Networks
> 316 N. Milwaukee Street
> Suite 214
> Milwaukee WI, 53202
> PH 414-273-7600 ext. 7607
> FX 414-273-7601
>
> ------------------------------------------------------------------
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
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Date: Thu, 28 Feb 2002 07:25:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Nemcik <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Nemcik <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Hi Rudy,
it's the other way around: elecrolytic copper on EN, which is plated onto aluminum.
Regards
Pete
Rudy Sedlak <[log in to unmask]> wrote: Pete:
I am, unfortunately, becoming too knowledgeable about this subject area...ahem.
To confirm my understanding, you are putting EN down on to Electroplated Copper?
So, you use a catalyst. Look at your catalyst activity. Too much catalyst can cause this problem. What can cause too much catalyst activity will depend on which catalyst you are using, but this is a key area to investigate.
Rudy Sedlak
RD Chemical Company (Yeah, you guessed it, we sell catalyst for the EN process)
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<P> Hi Rudy,
<P>it's the other way around: elecrolytic copper on EN, which is plated onto aluminum.
<P>Regards
<P>Pete
<P> <B><I>Rudy Sedlak <[log in to unmask]></I></B> wrote:
<BLOCKQUOTE style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid"><FONT face=arial,helvetica><FONT lang=0 face=Arial size=2 FAMILY="SANSSERIF">Pete:<BR><BR>I am, unfortunately, becoming too knowledgeable about this subject area...ahem.<BR><BR>To confirm my understanding, you are putting EN down on to Electroplated Copper?<BR><BR>So, you use a catalyst. Look at your catalyst activity. Too much catalyst can cause this problem. What can cause too much catalyst activity will depend on which catalyst you are using, but this is a key area to investigate.<BR><BR>Rudy Sedlak<BR>RD Chemical Company (Yeah, you guessed it, we sell catalyst for the EN process)</FONT> </BLOCKQUOTE></FONT><p><br><hr size=1><b>Do You Yahoo!?</b><br>
<a href="http://greetings.yahoo.com">Yahoo! Greetings</a> - Send FREE e-cards for every occasion!
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Date: Thu, 28 Feb 2002 10:31:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Raymond <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: attachments??
X-To: Kathy Kuhlow <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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I wonder why Kathy's posting always include an attached file such as
TEXT.htm... I thought technet stripped all attachments??? As all can see,
I use Eudora as an email client.
bill...
At 08:06 AM 02/28/2002 -0600, you wrote:
>Not to use was explained to me as such: No clean leaves a residue that
>with heat can reliquify and then start to move which will cause an air
>bubble where the flux was originally at and now isn't.
>
>So the question comes to: does and at what temperature would it take for
>the no clean residue you are using to reliquify if it does at all? Then
>if it does liquify is there any activation that is occurring? Does the
>coating withstand the proper adhesion for the application if the air
>bubble does occur?
>
>
>Kathy
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Date: Thu, 28 Feb 2002 10:50:20 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Chris Christian <[log in to unmask]>
Subject: Re: No No-clean?
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Doug,
Excellent information - and well put.
Regards,
Christine A. Christian
Sales Manager - Canada
Indium Corporation of America
Ph: +1 315 853-4900 X7572
Fx: +1 315 853-1000
Mobile: +1 315 796-0627
[log in to unmask] <mailto:[log in to unmask]>
www.indium.com <http://www.indium.com>
www.pb-free.com <http://www.pb-free.com> or www.SMQ230.com
<http://www.SMQ230.com>
[log in to unmask] <mailto:[log in to unmask]>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Thursday, February 28, 2002 9:18 AM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Well, as Brother Brian copied me on his response about no-cleans and
conformal coat, I took it as a subtle hint to throw my two
cents/shillings/micro-Euros into the mix.
I am of the general opinion that you can make almost any material set do
what you want with sufficient time and attention to the selection of the
materials and the associated process parameters. I know of companies out
there who successfully use no-clean assembly processes and conformally coat
over the residues. Delco Electronics is one such company. They make more
assemblies in a month than Rockwell makes in a year. Many of their product
lines are no-clean and they coat over them. And the under-the-hood
environment of a car is a pretty nasty environment with lots of thermal
cycles, humidity, and salt environment (if you are from the north). I know
that they put a tremendous amount of time into the selection of the flux
and the selection of the process parameters, such that conformal coat would
adhere to whatever they left on the board. There are other companies as
well that manufacturer to Class 3 high-reliability standards that use
no-clean and conformally coat. And all of them spent a lot of money tuning
the process. As Brian said, the person who tries to combine these two
without diligent process control and process qualification is
irresponsibile. I would agree.
Keep in mind what a low solids flux residue represents. The amount of
residue depends on how much you apply and the thermal reflow profile you
use. If you throw huge amounts of 5% flux on an assembly with lots of
entrapment sites, then expect to have lots of residue after soldering. If
you lightly spray on a 1% flux, using no more than you absolutely must
have, and you tune your reflow accordingly, then most or all may flash off
in reflow. Secondly, the flux residues after soldering will have different
characteristics, depending on how you processed the flux. A low solids
flux (LSF) must reach some minimum activation temperature before the
residues fully react and reach the "benign" stage. If the flux is not
fully reacted, then portions of the high molecular weight high boiling
point solvents remain, making the residues mildly conductive. This may be
why Lorraine Reid saw arcing in a high voltage application. The flux
residues may not have been fully reacted, and so did not have the same
dielectric strength as a fully reacted residue. I have seen this failure
mechanism numerous times where the assembler did not fully realize that
throwing more flux at the assembly was not a wise thing to do. One
critical mistake that many assemblers, new to the field of no clean make,
is that they do not understand how a LSF works. With a water soluble flux,
you have a chemical etching that goes on from the point of application to
the point of reflow. For a LSF, you do not get fluxing action until you
drive off the carrier solvent and the crystals of the weak organic acids
(usually one or more dicarboxylic acids) melt, which then provide the oxide
stripping mechanism. So OA flux experience tells an operator that if you
have soldering problems, throw more flux at the assembly, but with a LSF,
if the board reaches the wave wet, you get no oxide removal, so the
solution is to throw less flux at the problem. For the same reasons, you
don't want to squirt liquid LSF on a board as part of hand soldering. The
flux goes a lot farther than the heat from the soldering iron reaches.
That isopropanol carrier takes that flux places you would not believe.
Keep in mind that flux manufacturers can work to tailor the properties of
the residual flux. One example that I know of is Indium SMQ-92 and
SMQ-92J. The residues in the 92J are harder and glossier than those of the
92. Indium did that to make the 92 easier to penetrate in probe testing.
I have found it useful to look at the flux residues as if it were a
material that I design into the board, rather than a process effect. If I
have a great big honkin' electrolytic capacitor, I know that I have
laminate between the through-holes, and solder mask between the through
holes. I would evaluate both the laminate and the solder mask to determine
if they had sufficient dielectric strength for the application. Now, add
to that a layer of flux residue remaining after processing. Does that flux
residue have adequate dielectric strength for the application. Then, if it
does in the fully reacted state, what kinds of processing controls do I
need to have in place in order to make sure that the flux residue reaches
that dielectric state during processing? This is where I see many no-clean
assemblers failing. They fail to take into account the residues as a
dielectric material, affecting dielectic strength, cross talk, impedance,
rise time and propogation in RF, etc., or they fail to make their assembly
process robust enough against these factors.
As Brian pointed out, many of the LSF residues are hydroscopic in nature,
which has to be remembered when considering conformal coating. If you have
a case where you have unreacted flux residues, or a board that has an
unacceptable level of ionic contamination on it, conformal coating will NOT
help you.
I had a number of clients when I was at CSL that had problems identified on
their boards. Maybe it was the unreacted flux, maybe dirty bare boards,
maybe dirty assemblies. Some did not want to spend the time or money to
attack the true cause of the problem, which were the ionic residues. Their
solution was to slap a layer of conformal coating over the problem and ship
product. Of course, choosing the cheapest solution, the acrylic coatings,
which have the higher water permeability of them all. If you remember the
old commercial with the auto mechanic "You can pay me now or pay me later",
that was what happened. Nine months to a year later, they came back saying
"Uhhhhhhh, it didn't work". Conformal coating only buys you time since
moisture WILL go through the coating.
You can't really fault the coating manufacturer either. Assemblers often
expect the coating manufacturers to make a coating that sticks to any
surface, no matter what the assemblers have done to the board, and for low
cost. Most components have plastic release agents build in, most solder
masks have smooth surfaces that may be difficult to adhere to, and now you
throw in residues with a highly variable surface tension, and you have an
adhesion nightmare. You have this nighmare in fully cleaned assemblies
too, so don't be too quick to blame the coating for not sticking to your
residues.
If you have a choice in conformal coating, I would recommend a urethane, I
would recommend it over an acrylic. The acrylic is simply a dried film
over the surface, with limited chemical interaction to the substrate in
terms of bonding. In addition, you might also have the solvents in the
coating soften and attack the LSF residues, changing the properties (keep
that in mind). The urethanes or epoxies tend to chemically react better
with the substrates, forming a better bond, but they are also more
difficult to rework. If your manufacturing process is mature and
controlled, the tech staff of the coating manufacturer should be able to
help you choose a coating for good adhesion. On the other hand, if your
process is not controlled, you will probably get the generic "Well, the
assembly has to be clean before you coat" response.
So, if you are working with a no-clean assembly processes, you should be
doing the following:
1. Working to understand the dielectric properties of the residues
2. Determine what your processing windows need to be in order to make sure
the flux residues are fully reacted
3. Minimize the amount of flux you are applying
4. Work to use a lower percent solids in the process to leave fewer
residues on the board
5. Select your flux for desirable properties for conformal coat adhesion.
6. Tune your process to get the residue properties you want (in
conjunction with #2), such as a matte finish rather than a hard glossy
7. Select your conformal coating so that the solvent system is compatible
with the flux residues and so that the coating sticks to the residues.
As this message is nearing "the Ellis Zone", I will wrap up by saying that
you CAN manufacture hi-rel equipment with no-clean, you CAN make it
reliable for long life, you CAN make coating stick to it for the design
life, IF IF IF you have done your homework and know what you are doing.
Doug Pauls
Rockwell Collins
(And all done without Mountain Dew, which will be immediately remedied)
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Date: Thu, 28 Feb 2002 11:07:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charlie Pitarys <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charlie Pitarys <[log in to unmask]>
Subject: Alox 2028D
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One of my customers has
selected the Alox 2028D for use as a protective coating on their CCAs.
Can anyone share any info on the benefits of this product (if any) in
electronic packaging?
It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax.
Described as a metalworking fluid additive.
I can envision a lot of problems with wash chemistry incompatibility,
insolubility and rinse water treatment etc.
Any info will be appreciated.
Thanks
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
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<BODY>
<P><FONT SIZE=2> One of my customers has</FONT>
<BR><FONT SIZE=2>selected the Alox 2028D for use as a protective coating on their CCAs.</FONT>
<BR><FONT SIZE=2>Can anyone share any info on the benefits of this product (if any) in electronic packaging?</FONT>
<BR><FONT SIZE=2>It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax. Described as a metalworking fluid additive.</FONT>
</P>
<P><FONT SIZE=2>I can envision a lot of problems with wash chemistry incompatibility, insolubility and rinse water treatment etc.</FONT>
</P>
<P><FONT SIZE=2>Any info will be appreciated.</FONT>
</P>
<P><FONT SIZE=2>Thanks</FONT>
</P>
<P><FONT SIZE=2>Charlie Pitarys</FONT>
<BR><FONT SIZE=2>Director of Application Technologies</FONT>
<BR><FONT SIZE=2>603.622.2900 X-115</FONT>
<BR><FONT SIZE=2>www.kyzen.com </FONT>
</P>
<P><FONT SIZE=2> </FONT>
</P>
<P><FONT SIZE=2> </FONT>
</P>
</BODY>
</HTML>
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Date: Thu, 28 Feb 2002 10:32:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: No No-clean?
X-To: [log in to unmask]
MIME-Version: 1.0
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Kathy Kuhlow asks:
Not to use was explained to me as such: No clean leaves a residue that with
heat can reliquify and then start to move which will cause an air bubble
where the flux was originally at and now isn't.
So the question comes to: does and at what temperature would it take for
the no clean residue you are using to reliquify if it does at all? Then if
it does liquify is there any activation that is occurring? Does the
coating withstand the proper adhesion for the application if the air bubble
does occur?
Doug Pauls, now fully tanked up with Dew, responds.
Kathy, you are treating the low solids flux as if it were a single animal
with tightly identified characteristics. The residues that you have on the
board can be generically called weak organic acids, or dicarboxylic acids.
A paper by Al Schneider (who has forgotten more about flux than I will ever
know) a few years back listed the menu from which a flux manufacturer has
to choose. If I recall, that information found its way into J-HDBK-001,
section 4. The list is over 36 materials, each of which would give you a
different blend of properties in the final residue. A residue that is 50%
adipic and 50% maleic acid would give you different characteristics than
one that is 33% succinnic, 33% glutaric, and 34% fufu dust / gnats noses.
So the question of "what point does the residue soften and creep" depends
entirely on what flux you are using and a generic classification cannot be
made.. Your flux manufacturer would have to answer the question. They
would also have to address the issue of whether or not the residues had any
kind of chemical activity in the softened condition.
Think of it this way: At what temperature does solder reflow? Kind of
depends on the alloy, right?
Some residues will soften under high heat and may creep. It depends on
whether the residue acts more like a thermoplastic or more like a
thermoset. The latter will resist heat better. If your application has a
high amount of heat, or point heat sources, then LSFs may not be good for
that application, or topical cleaning may be needed for that area. In my
experience, you either want to leave a LSF residue totally alone, or
totally remove it. Doing a half-ass job of cleaning results in an amalgam
of cleaner, flux, and interactive products. Not a pretty sight and often
detrimental.
If you have conformal coating over a residue that will soften and creep, I
would suspect you would have adhesion problems and blister formation. The
same problem arises when solder mask is put over a melting metal. The
metal melts and moves, wrinkling or blistering the mask. Same with
conformal coat.
Doug Pauls
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Date: Thu, 28 Feb 2002 08:40:04 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Alox 2028D
X-To: [log in to unmask]
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hi,
surely you jest. they may be confused. i use it on the chain of my touring bike and it works great there.
phil
-----Original Message-----
From: Charlie Pitarys [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:07 AM
To: [log in to unmask]
Subject: [TN] Alox 2028D
One of my customers has
selected the Alox 2028D for use as a protective coating on their CCAs.
Can anyone share any info on the benefits of this product (if any) in electronic packaging?
It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax. Described as a metalworking fluid additive.
I can envision a lot of problems with wash chemistry incompatibility, insolubility and rinse water treatment etc.
Any info will be appreciated.
Thanks
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
------_=_NextPart_001_01C1C076.92CA4D10
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Alox 2028D</TITLE>
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff size=2>surely
you jest. they may be confused. i use it on the chain of my touring
bike and it works great there.</FONT></SPAN></DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Charlie Pitarys
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, 2002
8:07 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Alox
2028D<BR><BR></FONT></DIV>
<P><FONT size=2> One of my customers has</FONT> <BR><FONT size=2>selected
the Alox 2028D for use as a protective coating on their CCAs.</FONT> <BR><FONT
size=2>Can anyone share any info on the benefits of this product (if any) in
electronic packaging?</FONT> <BR><FONT size=2>It is mainly Naptha,
Trimethylbenzen, hydrocarbon and parrafin wax. Described as a metalworking
fluid additive.</FONT> </P>
<P><FONT size=2>I can envision a lot of problems with wash chemistry
incompatibility, insolubility and rinse water treatment etc.</FONT> </P>
<P><FONT size=2>Any info will be appreciated.</FONT> </P>
<P><FONT size=2>Thanks</FONT> </P>
<P><FONT size=2>Charlie Pitarys</FONT> <BR><FONT size=2>Director of
Application Technologies</FONT> <BR><FONT size=2>603.622.2900 X-115</FONT>
<BR><FONT size=2>www.kyzen.com </FONT></P>
<P><FONT size=2></FONT> </P>
<P><FONT size=2></FONT> </P></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Feb 2002 11:42:20 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Phillip Hinton <[log in to unmask]>
Subject: Solder coating on terminations
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All
With the push ro go lead free, I am looking at trying to get sources for the
small passive devices that have alternate finishes for other than tin/lead.
Phil Hinton
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<BR>
<BR>With the push ro go lead free, I am looking at trying to get sources for the small passive devices that have alternate finishes for other than tin/lead.
<BR>
<BR>Phil Hinton
<BR>[log in to unmask] </FONT></HTML>
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Date: Thu, 28 Feb 2002 17:58:51 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Atkinson, Neil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: Solder Projections
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When you are seeing spikes on wave solder there are a number of things to
consider.
1. Is the boards being fluxed correctly and is the temperature profile
correct.
2. Could the dwell time in the solder be too long.
3. If the spikes are on one component it may be worth checking the
solderability.
It is unlikely that the copper content in the solder will be too high as the
rate at which copper dissolves in solder reduces as the copper content
increases so at normal operating temperatures it tends to be self
regulating. However, you should be doing regular checks on your solder
anyway to be sure!
Regards,
Neil
Neil Atkinson
-----Original Message-----
From: Bev Christian [ mailto:[log in to unmask] <mailto:[log in to unmask]>
]
Sent: 27 February 2002 23:35
Subject: Re: Solder Projections
Mr. Pollak,
High copper content in your solder can cause spikes... or amateur hand
solderers like myself are very good at forming spikes. There may be other
reasons that some of our "older" regulars can contribute.
I looked in IPC/EIA J-STD-006 and it lists max impurity levels for different
elements, but does not give reasons why they are individually considered
impurities. You may be able to find this info from some of the more common
reference books for our industry, the titles of which you can find by doing
a search of the TechNet archives from the IPC homepage.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Mr. Leslie A. Pollak [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: February 27, 2002 3:57 PM
To: [log in to unmask]
Subject: [TN] Solder Projections
Hi,
Could soemone tell me what causes solder projections or what we call
icicles.
Or point us to IPC documentation that would help us.
Thanks
Mr. Leslie A. Pollak
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<P><FONT size=3D2>When you are seeing spikes on wave solder there are a =
number of=20
things to consider.<BR><BR>1. Is the boards being fluxed correctly and =
is the=20
temperature profile correct.<BR>2. Could the dwell time in the solder =
be too=20
long.<BR>3. If the spikes are on one component it may be worth checking =
the=20
solderability.<BR><BR>It is unlikely that the copper content in the =
solder will=20
be too high as the rate at which copper dissolves in solder reduces as =
the=20
copper content increases so at normal operating temperatures it tends =
to be self=20
regulating. However, you should be doing regular checks on your =
solder=20
anyway to be sure!<BR><BR>Regards,<BR><BR>Neil<BR><BR><EM><STRONG>Neil=20
Atkinson<BR><BR><BR><BR><BR></STRONG></EM>-----Original =
Message-----<BR>From:=20
Bev Christian [<A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Sen=
t: 27=20
February 2002 23:35<BR>Subject: Re: Solder Projections<BR><BR><BR>Mr.=20
Pollak,<BR>High copper content in your solder can cause spikes... or =
amateur=20
hand<BR>solderers like myself are very good at forming spikes. =
There may=20
be other<BR>reasons that some of our "older" regulars can =
contribute.<BR><BR>I=20
looked in IPC/EIA J-STD-006 and it lists max impurity levels for=20
different<BR>elements, but does not give reasons why they are =
individually=20
considered<BR>impurities. You may be able to find this info from =
some of=20
the more common<BR>reference books for our industry, the titles of =
which you can=20
find by doing<BR>a search of the TechNet archives from the IPC=20
homepage.<BR><BR>regards,<BR>Bev Christian<BR>Research in=20
Motion<BR><BR><BR>-----Original Message-----<BR>From: Mr. Leslie A. =
Pollak [<A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<=
BR>Sent:=20
February 27, 2002 3:57 PM<BR>To: [log in to unmask]<BR>Subject: [TN] =
Solder=20
Projections<BR><BR><BR>Hi,<BR><BR>Could soemone tell me what causes =
solder=20
projections or what we call<BR>icicles.<BR><BR>Or point us to IPC =
documentation=20
that would help us.<BR><BR>Thanks<BR>Mr. Leslie A.=20
Pollak<BR><BR>----------------------------------------------------------=
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Date: Thu, 28 Feb 2002 13:02:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: No No-clean?
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Doug,
I like your answer. One needs to know what animal they are dealing with
before one can determine that the characteristics are. "No Clean" means
different things to different people. There are no clean low solids
fluxes (No-Clean LSF) based on dicarboxylic acids. There are even
No-Clean LSF's which have a rosin content. In my years with Lucent we
used typical RMA (89% metal 11% flux vehicle)solder pastes and RMA
liquid fluxes (5-40% rosin solids) and we didn't clean them off so many
people referred to them as No-Clean but I liked to call them "leave
behind" systems. I don't like the No-Clean name because it doesn't give
one much information.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 11:33 AM
To: [log in to unmask]
Subject: Re: [TN] No No-clean?
Kathy Kuhlow asks:
Not to use was explained to me as such: No clean leaves a residue that
with
heat can reliquify and then start to move which will cause an air bubble
where the flux was originally at and now isn't.
So the question comes to: does and at what temperature would it take for
the no clean residue you are using to reliquify if it does at all? Then
if
it does liquify is there any activation that is occurring? Does the
coating withstand the proper adhesion for the application if the air
bubble
does occur?
Doug Pauls, now fully tanked up with Dew, responds.
Kathy, you are treating the low solids flux as if it were a single
animal
with tightly identified characteristics. The residues that you have on
the
board can be generically called weak organic acids, or dicarboxylic
acids.
A paper by Al Schneider (who has forgotten more about flux than I will
ever
know) a few years back listed the menu from which a flux manufacturer
has
to choose. If I recall, that information found its way into J-HDBK-001,
section 4. The list is over 36 materials, each of which would give you
a
different blend of properties in the final residue. A residue that is
50%
adipic and 50% maleic acid would give you different characteristics than
one that is 33% succinnic, 33% glutaric, and 34% fufu dust / gnats
noses.
So the question of "what point does the residue soften and creep"
depends
entirely on what flux you are using and a generic classification cannot
be
made.. Your flux manufacturer would have to answer the question. They
would also have to address the issue of whether or not the residues had
any
kind of chemical activity in the softened condition.
Think of it this way: At what temperature does solder reflow? Kind of
depends on the alloy, right?
Some residues will soften under high heat and may creep. It depends on
whether the residue acts more like a thermoplastic or more like a
thermoset. The latter will resist heat better. If your application has
a
high amount of heat, or point heat sources, then LSFs may not be good
for
that application, or topical cleaning may be needed for that area. In
my
experience, you either want to leave a LSF residue totally alone, or
totally remove it. Doing a half-ass job of cleaning results in an
amalgam
of cleaner, flux, and interactive products. Not a pretty sight and
often
detrimental.
If you have conformal coating over a residue that will soften and creep,
I
would suspect you would have adhesion problems and blister formation.
The
same problem arises when solder mask is put over a melting metal. The
metal melts and moves, wrinkling or blistering the mask. Same with
conformal coat.
Doug Pauls
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Date: Thu, 28 Feb 2002 20:51:55 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Gaby Bogdan <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Brian Ellis <[log in to unmask]>
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Brian,
I was following with great interest the subject. Right now, I am in the
middle of trying tosolder CSP's with "Flux underfill", and I see
similarities in the problems that could arise. Could you give me some hints
for the reliability of the process?
Gaby
----- Original Message -----
From: "Brian Ellis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, February 28, 2002 9:10 AM
Subject: Re: [TN] No No-clean?
> OK, there are three issues at stake here.
>
> 1) The residues from "no-clean" products (and yes, there are residues -
> always) may impede adhesion of the coating layer to the substrate
>
> 2) Many of the "no-clean" products rely on a slow sublimation of the
> residues from the surface, requiring a few weeks to achieve optimal
> performance. Sealing these in will prevent this from happening.
>
> 3) By definition, all soldering fluxes are ionic. Some may be slightly
> hygroscopic, as may also the metal salts formed by the reaction between
> the oxides and the flux acids. Some of the rheological additives to
> pastes may leave slightly hygroscopic residues. This is an open
> invitation to promote vesication, with a potentially very serious loss
> of reliability. At the very least, a good "pressure cooker" test is a
> must both in qualifying the process and at frequent intervals to check
> that it stays on the rails.
>
> I am not saying that coating should never be applied over flux residues.
> What I am saying is that anyone who does it without a really thorough
> qualification and process control is being professionally irresponsible,
> if the products must be reliable. After all, conformal coating is really
> a high-rel process and "no-clean" chemistry started as a low-rel
> process, creeping up to its present status of medium-rel. It is
> therefore really a paradoxal conflict to try and combine the two, likely
> to present the disadvantages of both processes with none, or few, of the
> advantages.
>
> Brian
>
> --------------------------------------------------------------------------
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Date: Thu, 28 Feb 2002 14:20:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Alox 2028D
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I fully agree with Phil. Surely they jest! Naphtha and trimethylbenzene
have reasonably high boiling points but they are still flammable solvents
and should be treated with respect. The latter has reported mutation
effects in lab animals (not specifically chemists). "Hydrocarbon" is very
broad, but usually means a cut or two above naphtha on the distillation
column. I would be concerned about higher boiling residues creeping into
switches, connectors; their effects on some of the cheaper plastics and
their really good ability to "suck" airborne dusts onto the circuit pack.
As far as the wax, which I presume is what they actually want to put on
their product, they might as well get my grandmother to melt some jam wax in
a double boiler and just pour it on their boards - just kidding!
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Crepeau, Phil [mailto:[log in to unmask]]
Sent: February 28, 2002 11:40 AM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
hi,
surely you jest. they may be confused. i use it on the chain of my touring
bike and it works great there.
phil
-----Original Message-----
From: Charlie Pitarys [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:07 AM
To: [log in to unmask]
Subject: [TN] Alox 2028D
One of my customers has
selected the Alox 2028D for use as a protective coating on their CCAs.
Can anyone share any info on the benefits of this product (if any) in
electronic packaging?
It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax.
Described as a metalworking fluid additive.
I can envision a lot of problems with wash chemistry incompatibility,
insolubility and rinse water treatment etc.
Any info will be appreciated.
Thanks
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
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<META content="MSHTML 5.50.4207.2601" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=205300819-28022002><FONT face=Arial color=#0000ff size=2>I
fully agree with Phil. Surely they jest! Naphtha and
trimethylbenzene have reasonably high boiling points but they are still
flammable solvents and should be treated with respect. The latter has
reported mutation effects in lab animals (not specifically chemists).
"Hydrocarbon" is very broad, but usually means a cut or two above naphtha on the
distillation column. I would be concerned about higher boiling residues
creeping into switches, connectors; their effects on some of the cheaper
plastics and their really good ability to "suck" airborne dusts onto the circuit
pack. As far as the wax, which I presume is what they actually want to put
on their product, they might as well get my grandmother to melt some jam wax in
a double boiler and just pour it on their boards - just
kidding! </FONT></SPAN></DIV>
<DIV><SPAN class=205300819-28022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=205300819-28022002><FONT face=Arial color=#0000ff
size=2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=205300819-28022002><FONT face=Arial color=#0000ff size=2>Bev
Christian</FONT></SPAN></DIV>
<DIV><SPAN class=205300819-28022002><FONT face=Arial color=#0000ff
size=2>Research in Motion</FONT></SPAN></DIV>
<DIV><SPAN class=205300819-28022002></SPAN><FONT face=Tahoma><FONT face=Arial
color=#0000ff size=2></FONT><BR><FONT size=2>-----Original
Message-----<BR><B>From:</B> Crepeau, Phil
[mailto:[log in to unmask]]<BR><B>Sent:</B> February 28, 2002 11:40
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Alox
2028D<BR><BR></FONT></DIV></FONT>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2>surely you jest. they may be confused. i use it on the
chain of my touring bike and it works great there.</FONT></SPAN></DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=715123916-28022002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Charlie Pitarys
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28,
2002 8:07 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Alox
2028D<BR><BR></FONT></DIV>
<P><FONT size=2> One of my customers has</FONT> <BR><FONT
size=2>selected the Alox 2028D for use as a protective coating on their
CCAs.</FONT> <BR><FONT size=2>Can anyone share any info on the benefits of
this product (if any) in electronic packaging?</FONT> <BR><FONT size=2>It is
mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax. Described as a
metalworking fluid additive.</FONT> </P>
<P><FONT size=2>I can envision a lot of problems with wash chemistry
incompatibility, insolubility and rinse water treatment etc.</FONT> </P>
<P><FONT size=2>Any info will be appreciated.</FONT> </P>
<P><FONT size=2>Thanks</FONT> </P>
<P><FONT size=2>Charlie Pitarys</FONT> <BR><FONT size=2>Director of
Application Technologies</FONT> <BR><FONT size=2>603.622.2900 X-115</FONT>
<BR><FONT size=2>www.kyzen.com </FONT></P>
<P><FONT size=2></FONT></P>
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Date: Thu, 28 Feb 2002 14:44:43 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
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Pete:
Given Electrolytic Copper on to EN, then the place to begin looking might
just be the level of Phosphorus in the EN.
Rudy Sedlak
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Date: Thu, 28 Feb 2002 15:10:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mary Jane Chism <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mary Jane Chism <[log in to unmask]>
Subject: FW: Water soluble w/BGA
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> -----Original Message-----
> From: Mary Jane Chism
> Sent: Thursday, February 28, 2002 2:27 PM
> To: [log in to unmask]
> Subject: Water soluble w/BGA
>
> I wanted to present this question out to the experts; What do you think
> about the validity of using water soluble flux with BGAs? Do you see a
> "residue" issue? Thanks.
>
> Mary Jane Chism
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<BR>
<P><FONT SIZE=3D1 FACE=3D"Arial">-----Original Message-----</FONT>
<BR><B><FONT SIZE=3D1 FACE=3D"Arial">From: </FONT></B> <FONT =
SIZE=3D1 FACE=3D"Arial">Mary Jane Chism </FONT>
<BR><B><FONT SIZE=3D1 FACE=3D"Arial">Sent: </FONT></B> <FONT =
SIZE=3D1 FACE=3D"Arial">Thursday, February 28, 2002 2:27 PM</FONT>
<BR><B><FONT SIZE=3D1 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D1 =
FACE=3D"Arial">Subject: </FONT>=
</B> <FONT SIZE=3D1 FACE=3D"Arial">Water soluble w/BGA</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">I wanted to present this question out =
to the experts; What do you think about the validity of using water =
soluble flux with BGAs? Do you see a "residue" issue? =
Thanks.</FONT></P>
<P><B><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Lucida Handwriting">Mary =
Jane Chism</FONT></B>
</P>
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Date: Thu, 28 Feb 2002 21:22:52 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Alox 2028D
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Hi ya Charlie!
Alox 2028D is covered under MIL-C-81309 Type 3 Class 1 . It's an avionic
grade "soft film" used to temporarily prevent corrosion when shipping
components (up to 1 month) . The Navy uses this stuff. A website:
http://www.ciaci.com/aloxcorporation.htm
<http://www.ciaci.com/aloxcorporation.htm> (although some of it is in
Brazilian I think).
I can see why you'd be concerned.
Hans
MIL-C-81309E
MILITARY SPECIFICATION
CORROSION PREVENTIVE COMPOUNDS, WATER DISPLACING,
ULTRA-THIN FILM
6.1 Intended use. The ultra-thin film, corrosion preventive compounds
covered by this specification are intended for use on any metal surface. It
can be used both for initial protection during shipment and storage and for
in-service treatment. It should not be used around liquid oxygen fittings.
The ability of these materials to prevent corrosion and to displace water
and their ease of application when packaged as class 2 (pressurized spray
cans) make them particularly suited for service use. These materials are
intended for indoor protection and short term protection outdoors where
surfaces can be recoated when required. These materials are not intended as
a substitute for other corrosion preventatives specified for protection of
surfaces for periods of more than one month.
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 2:20 PM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
I fully agree with Phil. Surely they jest! Naphtha and trimethylbenzene
have reasonably high boiling points but they are still flammable solvents
and should be treated with respect. The latter has reported mutation
effects in lab animals (not specifically chemists). "Hydrocarbon" is very
broad, but usually means a cut or two above naphtha on the distillation
column. I would be concerned about higher boiling residues creeping into
switches, connectors; their effects on some of the cheaper plastics and
their really good ability to "suck" airborne dusts onto the circuit pack.
As far as the wax, which I presume is what they actually want to put on
their product, they might as well get my grandmother to melt some jam wax in
a double boiler and just pour it on their boards - just kidding!
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Crepeau, Phil [mailto:[log in to unmask]]
Sent: February 28, 2002 11:40 AM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
hi,
surely you jest. they may be confused. i use it on the chain of my touring
bike and it works great there.
phil
-----Original Message-----
From: Charlie Pitarys [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:07 AM
To: [log in to unmask]
Subject: [TN] Alox 2028D
One of my customers has
selected the Alox 2028D for use as a protective coating on their CCAs.
Can anyone share any info on the benefits of this product (if any) in
electronic packaging?
It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax.
Described as a metalworking fluid additive.
I can envision a lot of problems with wash chemistry incompatibility,
insolubility and rinse water treatment etc.
Any info will be appreciated.
Thanks
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
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<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE>Alox 2028D</TITLE>
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>Hi ya=20
Charlie!</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>Alox 2028D =
is covered=20
under MIL-C-81309 Type 3 Class 1 . It's an avionic =
grade "soft=20
film" used to temporarily prevent corrosion when shipping components =
(up=20
to 1 month) . The Navy uses this stuff. =
A website: =20
</FONT></SPAN><SPAN class=3D944415920-28022002><FONT color=3D#0000ff><A =
href=3D"http://www.ciaci.com/aloxcorporation.htm">http://www.ciaci.com/a=
loxcorporation.htm</A> =20
(although some of it is in Brazilian I think).</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>I can see =
why you'd be=20
concerned.</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT =
color=3D#0000ff>Hans</FONT></SPAN><SPAN=20
class=3D944415920-28022002></DIV></SPAN>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff><FONT =
face=3DCourier=20
color=3D#000000 size=3D2>
<P align=3Dleft>MIL-C-81309E</P></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff><FONT =
face=3DCourier=20
size=3D2>
<P align=3Dleft><FONT color=3D#000000>MILITARY SPECIFICATION</FONT></P>
<P align=3Dleft><FONT color=3D#000000>CORROSION PREVENTIVE COMPOUNDS, =
WATER=20
DISPLACING,</FONT></P>
<P align=3Dleft><FONT color=3D#000000>ULTRA-THIN=20
FILM</FONT></P></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002>
<P align=3Dleft><FONT face=3DCourier size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">6.1=20
Intended use. The ultra-thin film, corrosion preventive =
compounds</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">covered=20
by this specification are intended for use on any metal surface. It can =
be used=20
both for initial protection during shipment and storage and =
for</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">in-service=20
treatment. It should not be used around liquid oxygen fittings. The =
ability of=20
these materials to prevent corrosion and to displace water and their =
ease of=20
application when packaged as class 2 (pressurized spray cans) make them =
particularly suited for service use. These materials are intended for =
indoor=20
protection and short term protection outdoors where surfaces can be =
recoated=20
when required. These materials are not intended as a substitute for =
other=20
corrosion preventatives specified for protection of surfaces for =
periods=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">of=20
more than one month. </SPAN></FONT></P></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Bev Christian=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, =
2002 2:20=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Alox=20
2028D<BR><BR></FONT></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff size=3D2>I=20
fully agree with Phil. Surely they jest! Naphtha and=20
trimethylbenzene have reasonably high boiling points but they are =
still=20
flammable solvents and should be treated with respect. The =
latter has=20
reported mutation effects in lab animals (not specifically =
chemists). =20
"Hydrocarbon" is very broad, but usually means a cut or two above =
naphtha on=20
the distillation column. I would be concerned about higher =
boiling=20
residues creeping into switches, connectors; their effects on some of =
the=20
cheaper plastics and their really good ability to "suck" airborne =
dusts onto=20
the circuit pack. As far as the wax, which I presume is what =
they=20
actually want to put on their product, they might as well get my =
grandmother=20
to melt some jam wax in a double boiler and just pour it on their =
boards -=20
just kidding! </FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff size=3D2>Bev=20
Christian</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Research in Motion</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002></SPAN><FONT =
face=3DTahoma><FONT face=3DArial=20
color=3D#0000ff size=3D2></FONT><BR><FONT size=3D2>-----Original=20
Message-----<BR><B>From:</B> Crepeau, Phil=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> February 28, 2002 11:40 =
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Alox=20
2028D<BR><BR></FONT></DIV></FONT>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>surely you jest. they may be confused. i use =
it on the=20
chain of my touring bike and it works great =
there.</FONT></SPAN></DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Charlie =
Pitarys=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, =
February 28,=20
2002 8:07 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> =
[TN] Alox=20
2028D<BR><BR></FONT></DIV>
<P><FONT size=3D2> One of my customers has</FONT> <BR><FONT=20
size=3D2>selected the Alox 2028D for use as a protective coating =
on their=20
CCAs.</FONT> <BR><FONT size=3D2>Can anyone share any info on the =
benefits of=20
this product (if any) in electronic packaging?</FONT> <BR><FONT =
size=3D2>It=20
is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax. =
Described=20
as a metalworking fluid additive.</FONT> </P>
<P><FONT size=3D2>I can envision a lot of problems with wash =
chemistry=20
incompatibility, insolubility and rinse water treatment =
etc.</FONT> </P>
<P><FONT size=3D2>Any info will be appreciated.</FONT> </P>
<P><FONT size=3D2>Thanks</FONT> </P>
<P><FONT size=3D2>Charlie Pitarys</FONT> <BR><FONT =
size=3D2>Director of=20
Application Technologies</FONT> <BR><FONT size=3D2>603.622.2900 =
X-115</FONT>=20
<BR><FONT size=3D2>www.kyzen.com </FONT></P>
<P><FONT size=3D2></FONT></P>
<P><FONT =
size=3D2></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML=
>
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Date: Thu, 28 Feb 2002 16:32:42 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Chris Christian <[log in to unmask]>
Subject: Re: FW: Water soluble w/BGA
X-To: Mary Jane Chism <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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FW: Water soluble w/BGAI would be the first to admit I am not an expert, but
cleaning under a low stand-off BGA is a major problem. And water soluble
flux residues are definitely not something you want left on a board.
Chris Christian
Indium Corporation of America
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mary Jane Chism
Sent: Thursday, February 28, 2002 3:11 PM
To: [log in to unmask]
Subject: [TN] FW: Water soluble w/BGA
-----Original Message-----
From: Mary Jane Chism
Sent: Thursday, February 28, 2002 2:27 PM
To: [log in to unmask]
Subject: Water soluble w/BGA
I wanted to present this question out to the experts; What do you think
about the validity of using water soluble flux with BGAs? Do you see a
"residue" issue? Thanks.
Mary Jane Chism
------=_NextPart_000_004D_01C1C075.8B4758E0
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
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<HTML><HEAD><TITLE>FW: Water soluble w/BGA</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D280542921-28022002>I=20
would be the first to admit I am not an expert, but cleaning under a low =
stand-off BGA is a major problem. And water soluble flux =
residues=20
are definitely not something you want left on a =
board.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D280542921-28022002></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D280542921-28022002>Chris=20
Christian</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D280542921-28022002>Indium=20
Corporation of America</SPAN></FONT></DIV>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Mary Jane =
Chism<BR><B>Sent:</B>=20
Thursday, February 28, 2002 3:11 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] FW: Water soluble=20
w/BGA<BR><BR></DIV></FONT><BR><BR>
<P><FONT face=3DArial size=3D1>-----Original Message-----</FONT> =
<BR><B><FONT=20
face=3DArial size=3D1>From: </FONT></B> <FONT face=3DArial =
size=3D1>Mary=20
Jane Chism </FONT><BR><B><FONT face=3DArial =
size=3D1>Sent: </FONT></B>=20
<FONT face=3DArial size=3D1>Thursday, February 28, 2002 2:27 PM</FONT> =
<BR><B><FONT face=3DArial =
size=3D1>To: </FONT></B> <FONT=20
face=3DArial size=3D1>[log in to unmask]</FONT> <BR><B><FONT =
face=3DArial=20
size=3D1>Subject: </FONT></B> =
<FONT=20
face=3DArial size=3D1>Water soluble w/BGA</FONT> </P>
<P><FONT face=3DArial size=3D2>I wanted to present this question out =
to the=20
experts; What do you think about the validity of using water soluble =
flux with=20
BGAs? Do you see a "residue" issue? Thanks.</FONT></P>
<P><B><FONT color=3D#0000ff face=3D"Lucida Handwriting" size=3D2>Mary =
Jane=20
Chism</FONT></B> </P></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Feb 2002 21:37:58 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: No No-clean?
X-To: Jim Jenkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey Jim,
That's a good one. Ha! If there's an AF wide directive it hasn't gotten
out this way & you'd think they'd let us Hardware guys know.
It's like Doug, Mel & others have already said, some program (manager or
engineer) might have outlawed no clean for their stuff. But, if I got all
my ducks in a row and convinced my Chief Engineer to sign-off on such a
design change then it rules.
I'm not sure how such a directive could be implemented or paid for!
Hans
They can run . . . but they'll only die tired!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Jim Jenkins [mailto:[log in to unmask]]
Sent: Tuesday, February 26, 2002 10:54 AM
To: [log in to unmask]
Subject: [TN] No No-clean?
Hi everybody,
I was just approached by one of our engineers whose customer told her that
the Air Force has issued a directive disallowing the use of no-clean fluxes
on any of their hardware. The customer is flowing down that requirement to
us. Do any of you know of this directive or what they could be referring
to?
Thanks,
Jim
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Date: Thu, 28 Feb 2002 13:55:00 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Nemcik <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Nemcik <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Thanks, we'll look at that.
Pete
Rudy Sedlak <[log in to unmask]> wrote: Pete:
Given Electrolytic Copper on to EN, then the place to begin looking might
just be the level of Phosphorus in the EN.
Rudy Sedlak
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<P> Thanks, we'll look at that.
<P>Pete
<P> <B><I>Rudy Sedlak <[log in to unmask]></I></B> wrote:
<BLOCKQUOTE style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">Pete:<BR><BR>Given Electrolytic Copper on to EN, then the place to begin looking might<BR>just be the level of Phosphorus in the EN.<BR><BR>Rudy Sedlak<BR><BR>---------------------------------------------------------------------------------<BR>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To unsubscribe, send a message to [log in to unmask] with following text in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To temporarily halt delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL<BR>To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest<BR>Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives<BR>Please visit IPC web site http://www.ipc.org/html/forum.htm for additional<BR>information, or contact Keach Sasamori at [log in to unmask] or 847-509-970!
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Date: Thu, 28 Feb 2002 16:58:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: FW: Water soluble w/BGA
X-To: "[log in to unmask]" <[log in to unmask]>
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We have success where we use WS on 1mm pitch BGAs and 1.25 mm pitch BGAs.
For .8mm pitch BGA's we use no clean. Cannot remove the flux residue from
under them efficiently.
-----Original Message-----
From: Chris Christian [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 4:33 PM
To: [log in to unmask]
Subject: Re: [TN] FW: Water soluble w/BGA
I would be the first to admit I am not an expert, but cleaning under a low
stand-off BGA is a major problem. And water soluble flux residues are
definitely not something you want left on a board.
Chris Christian
Indium Corporation of America
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mary Jane Chism
Sent: Thursday, February 28, 2002 3:11 PM
To: [log in to unmask]
Subject: [TN] FW: Water soluble w/BGA
-----Original Message-----
From: Mary Jane Chism
Sent: Thursday, February 28, 2002 2:27 PM
To: [log in to unmask]
Subject: Water soluble w/BGA
I wanted to present this question out to the experts; What do you think
about the validity of using water soluble flux with BGAs? Do you see a
"residue" issue? Thanks.
Mary Jane Chism
------_=_NextPart_001_01C1C0A3.1B0996A0
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>FW: Water soluble w/BGA</TITLE>
<META content="MSHTML 5.50.4522.1800" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=215410322-28022002><FONT face=Arial color=#0000ff size=2>We
have success where we use WS on 1mm pitch BGAs and 1.25 mm pitch BGAs. For
.8mm pitch BGA's we use no clean. Cannot remove the flux residue from
under them efficiently.</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Chris Christian
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, 2002
4:33 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] FW: Water
soluble w/BGA<BR><BR></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN class=280542921-28022002>I
would be the first to admit I am not an expert, but cleaning under a low
stand-off BGA is a major problem. And water soluble flux residues
are definitely not something you want left on a board.</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=280542921-28022002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=280542921-28022002>Chris Christian</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=280542921-28022002>Indium Corporation of America</SPAN></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>Mary Jane Chism<BR><B>Sent:</B>
Thursday, February 28, 2002 3:11 PM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> [TN] FW: Water soluble
w/BGA<BR><BR></DIV></FONT><BR><BR>
<P><FONT face=Arial size=1>-----Original Message-----</FONT> <BR><B><FONT
face=Arial size=1>From: </FONT></B> <FONT face=Arial size=1>Mary
Jane Chism </FONT><BR><B><FONT face=Arial
size=1>Sent: </FONT></B> <FONT face=Arial size=1>Thursday,
February 28, 2002 2:27 PM</FONT> <BR><B><FONT face=Arial
size=1>To: </FONT></B> <FONT face=Arial
size=1>[log in to unmask]</FONT> <BR><B><FONT face=Arial
size=1>Subject: </FONT></B> <FONT
face=Arial size=1>Water soluble w/BGA</FONT> </P>
<P><FONT face=Arial size=2>I wanted to present this question out to the
experts; What do you think about the validity of using water soluble flux
with BGAs? Do you see a "residue" issue? Thanks.</FONT></P>
<P><B><FONT face="Lucida Handwriting" color=#0000ff size=2>Mary Jane
Chism</FONT></B> </P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Feb 2002 22:06:44 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: MLB - spotwelding
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Hi Mike,
I think you will find misregistration kills this lay-up method for higher
layer count panels. It comes down to basic physics - material expansion,
prepreg flow, thermal variations in the lam stack that some thing has to
maintain registration during the lamination process. I've heard of a shop
in Az (Phoenix or Chandler) that uses rivet lay-up for 10 layers or less and
the more reliable 4-pin lay-up for higher layer counts (12+ layers). (Can't
remember the name off the top of my head.) What you're describing is a step
up from mass lamination. What registration are you trying to maintain? Why
not switch to the standard 4 pin lay-up? What kind of press cycle/lam book
do you run?
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Mike Holst. [mailto:[log in to unmask]]
Sent: Wednesday, February 27, 2002 3:51 AM
To: [log in to unmask]
Subject: [TN] MLB - spotwelding
We constructed our own machine for spotwelding mlb lay-ups prior
to pressing. It works fine for 6 and 8 layers (standard FR4 thin
laminates and prepreg). However, for higher layer counts especially
12 layers we seem often to loose internal layer / layer registration.
Could anyone kindly suggest a set of operating parameters
(temperature / pressure / time etc) to give more reliable welds for
higher layer counts. Pressed thickness about 1.6mm. Panel sizes
are relatively small - 14" x 11" would be typical, with 3 welds on
each long side about 4" apart.
The welder heads have a round flat point 10mm diameter and
existing settings are as follows:
Air pressure on the 16mm dia. welder cylinders is 5.5 bar, head
temperatures are controlled at 280C and weld timer set at 90 sec.
Any other input on this subject will also be welcome.
Thanks,
Mike Holst
Mike Holst.
TraX Interconnect (Pty) Ltd
Tel:(++27 21)712 5011
Fax:(++27 21)712 5798
Cape Town
South Africa
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Date: Thu, 28 Feb 2002 14:14:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Electroless nickel to electroplated copper separation
X-To: Peter Nemcik <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Pete: A few things to consider.
1. Even though you say the nickel is not passivated how do you know for sure
that it is not? Whether you are running an automated or manual line there
could be delays in transfer time between nickel activation - rinse - copper
plate that could occasionally lead to passivatioin of the surface of the
nickel. See if there are certain cycles or timing issues that could cause
this.
2. What are you using for nickel activation chemistry? Is the time, temp,
chemical concentration and bath life correct and being properly maintained?
You could be on the edge of the window on one or a combination of these that
causes the problem to intermittently show up.
3. Are your rinse water temps too hot causing premature drying of the part
during transfer? Are they too cold causing insufficient rinsing of the
previous chemistry resulting in contamination of down stream baths and on
the surface of the part?
4. Is the electrolytic copper rectification working properly? Delays in
applying current or insufficient or excessive current can cause adhesion
problems. In the same vein high or low current density areas can result in
the same type of problem.
5. Check your copper bath for excessive organics.
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Peter Nemcik [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 7:25 AM
To: [log in to unmask]
Subject: Re: [TN] Electroless nickel to electroplated copper separation
Hi Rudy,
it's the other way around: elecrolytic copper on EN, which is plated onto
aluminum.
Regards
Pete
_____
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Date: Thu, 28 Feb 2002 14:07:55 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Debbie Goodwin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Debbie Goodwin <[log in to unmask]>
Subject: Re: Solder coating on terminations
X-To: "[log in to unmask]" <[log in to unmask]>
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Phillip,
Practical Components has many lead-free devices available as "Dummies"
Please, contact me off-line for more details.
Sincerely,
Debbie Goodwin
Account Representative
10867 Portal Dr
Los Alamitos, CA 90720
Phone = (714) 252-0010
Fax = (714) 252-0026
PLEASE NOTE - Effective Immediately New e-mail address is:
[log in to unmask]
__________________________________________________
This message is intended for the use of the individual entity to which it is
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exempt from disclosure under applicable law. If the reader of this message
is not the intended recipient, or the employee or agent responsible for
delivering the message to the intended recipient, you are hereby notified
that any dissemination, distribution or copying of this communication is
strictly prohibited. If you have received this communication in error,
please notify us immediately by calling
714.252.0010 or returning the original message to us. Thank You.
-----Original Message-----
From: Phillip Hinton [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:42 AM
To: [log in to unmask]
Subject: [TN] Solder coating on terminations
All
With the push ro go lead free, I am looking at trying to get sources for the
small passive devices that have alternate finishes for other than tin/lead.
Phil Hinton
[log in to unmask]
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<BODY>
<DIV><FONT face=Arial size=2><SPAN
class=940002122-28022002>Phillip,</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=940002122-28022002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=940002122-28022002>Practical Components
has many lead-free devices available as "Dummies"</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN class=940002122-28022002>Please, contact me
off-line for more details.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=940002122-28022002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN
class=940002122-28022002>Sincerely,</SPAN></FONT></DIV>
<P><FONT face=Arial size=2>Debbie Goodwin</FONT> <BR><FONT face=Arial
size=2>Account Representative</FONT> <BR><FONT face=Arial size=2>10867 Portal
Dr</FONT> <BR><FONT face=Arial size=2>Los Alamitos, CA 90720</FONT> <BR><FONT
face=Arial size=2>Phone = (714) 252-0010 </FONT><BR><FONT face=Arial size=2>Fax
= (714) 252-0026</FONT> <BR><FONT face=Arial size=2>PLEASE NOTE - Effective
Immediately New e-mail address is: [log in to unmask]</FONT>
<BR><FONT face=Arial
size=2>__________________________________________________</FONT> <BR><FONT
face=Arial size=1>This message is intended for the use of the individual entity
to which it is addressed and may contain information that is privileged,
confidential and exempt from disclosure under applicable law. If the
reader of this message is not the intended recipient, or the employee or agent
responsible for delivering the message to the intended recipient, you are hereby
notified that any dissemination, distribution or copying of this communication
is strictly prohibited. If you have received this communication in error,
please notify us immediately by calling </FONT></P>
<P><FONT face=Arial size=1>714.252.0010 or returning the original message to
us. Thank You.</FONT> </P>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Phillip Hinton
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, 2002 8:42
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Solder coating on
terminations<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT size=2>All
<BR><BR>With the push ro go lead free, I am looking at trying to get sources
for the small passive devices that have alternate finishes for other than
tin/lead. <BR><BR>Phil Hinton <BR>[log in to unmask]
</FONT></FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 28 Feb 2002 16:37:56 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: FW: Water soluble w/BGA
X-To: [log in to unmask]
MIME-Version: 1.0
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Mary Jane wisely asks:
I wanted to present this question out to the experts; What do you think
about the validity of using water soluble flux with BGAs? Do you see a
"residue" issue? Thanks.
Doug Pauls, now way overdosed on Dew, replies:
Maaaaaaaaaaaaaaayyyyyyyyyyybe.
What water soluble flux?
What reflow method? Vapor phase, IR reflow, laser, hot gas?
What cleaning process?
Adding anything to the water?
In-line or batch cleaning?
Itty bitty BGAs or big-honkin' BGAs??
Full array or perimeter array?
What standoffs?
Are your boards clean going into it?
What do you mean by residue?
What end use environment?
What reliability requirements?
What is the service life of the product?
What are the consequences of failure?
Are you underfilling the BGA?
Why does the other line always move faster?
Is giving a year's supply of Captain Crunch cereal to my nieces a fitting
revenge on my sister?
I should probably stop now. Too much Dew. Definitely too much Dew!!
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Date: Thu, 28 Feb 2002 17:50:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Alox 2028D
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Hans,
Thanks for the info. When I read the quote your provided, it seems to me
that it only speaks to protecting 100% metal surfaces (like Phil's bicycle
chains). I would NOT take this to mean component leads or contact with
non-metal items like component bodies and circuit boards. Is this how you
all read it?
Bev
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: February 28, 2002 4:23 PM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
Hi ya Charlie!
Alox 2028D is covered under MIL-C-81309 Type 3 Class 1 . It's an avionic
grade "soft film" used to temporarily prevent corrosion when shipping
components (up to 1 month) . The Navy uses this stuff. A website:
http://www.ciaci.com/aloxcorporation.htm
<http://www.ciaci.com/aloxcorporation.htm> (although some of it is in
Brazilian I think).
I can see why you'd be concerned.
Hans
MIL-C-81309E
MILITARY SPECIFICATION
CORROSION PREVENTIVE COMPOUNDS, WATER DISPLACING,
ULTRA-THIN FILM
6.1 Intended use. The ultra-thin film, corrosion preventive compounds
covered by this specification are intended for use on any metal surface. It
can be used both for initial protection during shipment and storage and for
in-service treatment. It should not be used around liquid oxygen fittings.
The ability of these materials to prevent corrosion and to displace water
and their ease of application when packaged as class 2 (pressurized spray
cans) make them particularly suited for service use. These materials are
intended for indoor protection and short term protection outdoors where
surfaces can be recoated when required. These materials are not intended as
a substitute for other corrosion preventatives specified for protection of
surfaces for periods of more than one month.
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 2:20 PM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
I fully agree with Phil. Surely they jest! Naphtha and trimethylbenzene
have reasonably high boiling points but they are still flammable solvents
and should be treated with respect. The latter has reported mutation
effects in lab animals (not specifically chemists). "Hydrocarbon" is very
broad, but usually means a cut or two above naphtha on the distillation
column. I would be concerned about higher boiling residues creeping into
switches, connectors; their effects on some of the cheaper plastics and
their really good ability to "suck" airborne dusts onto the circuit pack.
As far as the wax, which I presume is what they actually want to put on
their product, they might as well get my grandmother to melt some jam wax in
a double boiler and just pour it on their boards - just kidding!
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Crepeau, Phil [mailto:[log in to unmask]]
Sent: February 28, 2002 11:40 AM
To: [log in to unmask]
Subject: Re: [TN] Alox 2028D
hi,
surely you jest. they may be confused. i use it on the chain of my touring
bike and it works great there.
phil
-----Original Message-----
From: Charlie Pitarys [mailto:[log in to unmask]]
Sent: Thursday, February 28, 2002 8:07 AM
To: [log in to unmask]
Subject: [TN] Alox 2028D
One of my customers has
selected the Alox 2028D for use as a protective coating on their CCAs.
Can anyone share any info on the benefits of this product (if any) in
electronic packaging?
It is mainly Naptha, Trimethylbenzen, hydrocarbon and parrafin wax.
Described as a metalworking fluid additive.
I can envision a lot of problems with wash chemistry incompatibility,
insolubility and rinse water treatment etc.
Any info will be appreciated.
Thanks
Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com
------_=_NextPart_001_01C1C0AA.55D1F140
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charset="iso-8859-1"
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<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE>Alox 2028D</TITLE>
<META content=3D"MSHTML 5.50.4207.2601" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D245504522-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Hans,</FONT></SPAN></DIV>
<DIV><SPAN class=3D245504522-28022002><FONT face=3DArial =
color=3D#0000ff size=3D2>Thanks=20
for the info. When I read the quote your provided, it seems to me =
that=20
it only speaks to protecting 100% metal surfaces (like Phil's =
bicycle=20
chains). I would NOT take this to mean component leads or =
contact=20
with non-metal items like component bodies and circuit boards. Is =
this how=20
you all read it?</FONT></SPAN></DIV>
<DIV><SPAN class=3D245504522-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Bev</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Hinners Hans M =
Civ=20
WRALC/LUGE [mailto:[log in to unmask]]<BR><B>Sent:</B> =
February 28,=20
2002 4:23 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: =
[TN] Alox=20
2028D<BR><BR></FONT></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>Hi ya=20
Charlie!</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>Alox =
2028D is covered=20
under MIL-C-81309 Type 3 Class 1 . It's an avionic=20
grade "soft film" used to temporarily prevent corrosion when =
shipping=20
components (up to 1 month) . The Navy uses this =
stuff. =20
A website: </FONT></SPAN><SPAN =
class=3D944415920-28022002><FONT=20
color=3D#0000ff><A=20
=
href=3D"http://www.ciaci.com/aloxcorporation.htm">http://www.ciaci.com/a=
loxcorporation.htm</A> =20
(although some of it is in Brazilian I think).</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff>I can see =
why you'd be=20
concerned.</FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D944415920-28022002><FONT=20
color=3D#0000ff>Hans</FONT></SPAN><SPAN =
class=3D944415920-28022002></DIV></SPAN>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff><FONT =
face=3DCourier=20
color=3D#000000 size=3D2>
<P align=3Dleft>MIL-C-81309E</P></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002><FONT color=3D#0000ff><FONT =
face=3DCourier=20
size=3D2>
<P align=3Dleft><FONT color=3D#000000>MILITARY =
SPECIFICATION</FONT></P>
<P align=3Dleft><FONT color=3D#000000>CORROSION PREVENTIVE COMPOUNDS, =
WATER=20
DISPLACING,</FONT></P>
<P align=3Dleft><FONT color=3D#000000>ULTRA-THIN=20
FILM</FONT></P></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D944415920-28022002>
<P align=3Dleft><FONT face=3DCourier size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">6.1=20
Intended use. The ultra-thin film, corrosion preventive =
compounds</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">covered
by this specification are intended for use on any metal surface. It =
can be=20
used both for initial protection during shipment and storage and=20
for</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">in-service=20
treatment. It should not be used around liquid oxygen fittings. The =
ability of=20
these materials to prevent corrosion and to displace water and their =
ease of=20
application when packaged as class 2 (pressurized spray cans) make =
them=20
particularly suited for service use. These materials are intended for =
indoor=20
protection and short term protection outdoors where surfaces can be =
recoated=20
when required. These materials are not intended as a substitute for =
other=20
corrosion preventatives specified for protection of surfaces for =
periods=20
</SPAN><SPAN=20
style=3D"FONT-SIZE: 12pt; FONT-FAMILY: Courier; =
mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: =
'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: =
EN-US; mso-bidi-language: AR-SA">of=20
more than one month. </SPAN></FONT></P></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Bev Christian=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, February 28, =
2002 2:20=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Alox=20
2028D<BR><BR></FONT></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff size=3D2>I=20
fully agree with Phil. Surely they jest! Naphtha and=20
trimethylbenzene have reasonably high boiling points but they are =
still=20
flammable solvents and should be treated with respect. The =
latter has=20
reported mutation effects in lab animals (not specifically =
chemists). =20
"Hydrocarbon" is very broad, but usually means a cut or two above =
naphtha on=20
the distillation column. I would be concerned about higher =
boiling=20
residues creeping into switches, connectors; their effects on some =
of the=20
cheaper plastics and their really good ability to "suck" airborne =
dusts onto=20
the circuit pack. As far as the wax, which I presume is what =
they=20
actually want to put on their product, they might as well get my =
grandmother=20
to melt some jam wax in a double boiler and just pour it on their =
boards -=20
just kidding! </FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Bev Christian</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Research in Motion</FONT></SPAN></DIV>
<DIV><SPAN class=3D205300819-28022002></SPAN><FONT =
face=3DTahoma><FONT=20
face=3DArial color=3D#0000ff size=3D2></FONT><BR><FONT =
size=3D2>-----Original=20
Message-----<BR><B>From:</B> Crepeau, Phil=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> February 28, 2002 =
11:40=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Alox=20
2028D<BR><BR></FONT></DIV></FONT>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>surely you jest. they may be confused. i use =
it on the=20
chain of my touring bike and it works great =
there.</FONT></SPAN></DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D715123916-28022002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Charlie =
Pitarys=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, =
February=20
28, 2002 8:07 AM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> [TN]=20
Alox 2028D<BR><BR></FONT></DIV>
<P><FONT size=3D2> One of my customers has</FONT> =
<BR><FONT=20
size=3D2>selected the Alox 2028D for use as a protective =
coating on their=20
CCAs.</FONT> <BR><FONT size=3D2>Can anyone share any info on =
the benefits=20
of this product (if any) in electronic packaging?</FONT> =
<BR><FONT=20
size=3D2>It is mainly Naptha, Trimethylbenzen, hydrocarbon and =
parrafin=20
wax. Described as a metalworking fluid additive.</FONT> </P>
<P><FONT size=3D2>I can envision a lot of problems with wash =
chemistry=20
incompatibility, insolubility and rinse water treatment =
etc.</FONT> </P>
<P><FONT size=3D2>Any info will be appreciated.</FONT> </P>
<P><FONT size=3D2>Thanks</FONT> </P>
<P><FONT size=3D2>Charlie Pitarys</FONT> <BR><FONT =
size=3D2>Director of=20
Application Technologies</FONT> <BR><FONT size=3D2>603.622.2900 =
X-115</FONT> <BR><FONT size=3D2>www.kyzen.com =
</FONT></P>
<P><FONT size=3D2></FONT></P>
<P><FONT=20
size=3D2></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE>=
</BODY></HTML>
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=========================================================================
Date: Thu, 28 Feb 2002 22:58:50 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: Many thanks
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi All,
I am burning the midnight Guinness at the moment after finishing a
particularly difficult assignment - writing a PWB (PCB in Europe) test
strategy from scratch.
I know this is not a chatroom, but I sincerely wish to thank all those who
assisted by responding to my first mail to the forum.
In particular "Peter (ST Aero)", Seth Goodman, 'Paul', Charlie McMahon and
Bill Raymond who's website link proved invaluable.
I will be a regular reader of all mails to the forum whether they affect my
immediate (work related) concerns or not.
Thanks also to IPC for setting up such a needed, specific forum ;- your
standards and documentation may be a little 'wishy washy' to the experts,
but to a grunt like me they are the only standard!
Moonman, what's your buzz?
Sir Groove to you!
Alan Groves CID,
Technical Services (D.O.) Team Leader.
Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
---------------------------------------------------------------------------------
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To unsubscribe, send a message to [log in to unmask] with following text in
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---------------------------------------------------------------------------------
=========================================================================
Date: Thu, 28 Feb 2002 18:02:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Alox 2028D
X-To: Bev Christian <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------D15670BC81135DB37EDEA2F5"
--------------D15670BC81135DB37EDEA2F5
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Bev,
I wonder how this stuff would react during an SIR test? (Keep the fire
extinguisher handy!!!)
I don't think I would like to power up a unit with this stuff on it!
David A. Douthit
Manager
LoCan LLC
Bev Christian wrote:
> Hans,Thanks for the info. When I read the quote your provided, it
> seems to me that it only speaks to protecting 100% metal surfaces
> (like Phil's bicycle chains). I would NOT take this to mean component
> leads or contact with non-metal items like component bodies and
> circuit boards. Is this how you all read it?Bev
>
> -----Original Message-----
> From: Hinners Hans M Civ WRALC/LUGE
> [mailto:[log in to unmask]]
> Sent: February 28, 2002 4:23 PM
> To: [log in to unmask]
> Subject: Re: [TN] Alox 2028D
>
> Hi ya Charlie!Alox 2028D is covered under MIL-C-81309 Type 3
> Class 1 . It's an avionic grade "soft film" used to
> temporarily prevent corrosion when shipping components (up
> to 1 month) . The Navy uses this stuff. A
> website: http://www.ciaci.com/aloxcorporation.htm (although
> some of it is in Brazilian I think).I can see why you'd be
> concerned.Hans
>
> MIL-C-81309E
>
> MILITARY SPECIFICATION
>
> CORROSION PREVENTIVE COMPOUNDS, WATER DISPLACING,
>
> ULTRA-THIN FILM
>
> 6.1 Intended use. The ultra-thin film, corrosion preventive
> compoundscovered by this specification are intended for use
> on any metal surface. It can be used both for initial
> protection during shipment and storage and forin-service
> treatment. It should not be used around liquid oxygen
> fittings. The ability of these materials to prevent
> corrosion and to displace water and their ease of
> application when packaged as class 2 (pressurized spray
> cans) make them particularly suited for service use. These
> materials are intended for indoor protection and short term
> protection outdoors where surfaces can be recoated when
> required. These materials are not intended as a substitute
> for other corrosion preventatives specified for protection
> of surfaces for periods of more than one month.
>
> -----Original Message-----
> From: Bev Christian [mailto:[log in to unmask]]
> Sent: Thursday, February 28, 2002 2:20 PM
> To: [log in to unmask]
> Subject: Re: [TN] Alox 2028D
>
> I fully agree with Phil. Surely they jest!
> Naphtha and trimethylbenzene have reasonably high
> boiling points but they are still flammable
> solvents and should be treated with respect. The
> latter has reported mutation effects in lab
> animals (not specifically chemists).
> "Hydrocarbon" is very broad, but usually means a
> cut or two above naphtha on the distillation
> column. I would be concerned about higher boiling
> residues creeping into switches, connectors; their
> effects on some of the cheaper plastics and their
> really good ability to "suck" airborne dusts onto
> the circuit pack. As far as the wax, which I
> presume is what they actually want to put on their
> product, they might as well get my grandmother to
> melt some jam wax in a double boiler and just pour
> it on their boards - just kidding! regards,Bev
> ChristianResearch in Motion
> -----Original Message-----
> From: Crepeau, Phil [mailto:[log in to unmask]]
> Sent: February 28, 2002 11:40 AM
> To: [log in to unmask]
> Subject: Re: [TN] Alox 2028D
>
>
> hi,surely you jest. they may be
> confused. i use it on the chain of my
> touring bike and it works great
> there.phil
>
> -----Original Message-----
> From: Charlie Pitarys
> [mailto:[log in to unmask]]
>
> Sent: Thursday, February 28,
> 2002 8:07 AM
> To: [log in to unmask]
> Subject: [TN] Alox 2028D
>
> One of my customers has
> selected the Alox 2028D for
> use as a protective coating on
> their CCAs.
> Can anyone share any info on
> the benefits of this product
> (if any) in electronic
> packaging?
> It is mainly Naptha,
> Trimethylbenzen, hydrocarbon
> and parrafin wax. Described as
> a metalworking fluid additive.
>
> I can envision a lot of
> problems with wash chemistry
> incompatibility, insolubility
> and rinse water treatment etc.
>
> Any info will be appreciated.
>
> Thanks
>
> Charlie Pitarys
> Director of Application
> Technologies
> 603.622.2900 X-115
> www.kyzen.com
>
>
>
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Bev,
<p>I wonder how this stuff would react during an SIR test? (Keep the fire
extinguisher handy!!!)
<br>I don't think I would like to power up a unit with this stuff on it!
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Bev Christian wrote:
<blockquote TYPE=CITE> <span class=245504522-28022002><font face="Arial"><font color="#0000FF"><font size=-1>Hans,</font></font></font></span><span class=245504522-28022002><font face="Arial"><font color="#0000FF"><font size=-1>Thanks
for the info. When I read the quote your provided, it seems to me
that it only speaks to protecting 100% metal surfaces (like Phil's bicycle
chains). I would NOT take this to mean component leads or contact
with non-metal items like component bodies and circuit boards. Is
this how you all read it?</font></font></font></span><span class=245504522-28022002><font face="Arial"><font color="#0000FF"><font size=-1>Bev</font></font></font></span>
<blockquote dir=ltr style="MARGIN-RIGHT: 0px">
<div class="OutlookMessageHeader" dir="ltr"><font face="Tahoma"><font size=-1>-----Original
Message-----</font></font>
<br><font face="Tahoma"><font size=-1><b>From:</b> Hinners Hans M Civ WRALC/LUGE
[<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</font></font>
<br><font face="Tahoma"><font size=-1><b>Sent:</b> February 28, 2002 4:23
PM</font></font>
<br><font face="Tahoma"><font size=-1><b>To:</b> [log in to unmask]</font></font>
<br><font face="Tahoma"><font size=-1><b>Subject:</b> Re: [TN] Alox 2028D</font></font>
<br> </div>
<span class=944415920-28022002><font color="#0000FF">Hi ya Charlie!</font></span><span class=944415920-28022002></span><span class=944415920-28022002><font color="#0000FF">Alox
2028D is covered under MIL-C-81309 Type 3 Class 1 . It's an
avionic grade "soft film" used to temporarily prevent corrosion when shipping
components (up to 1 month) . The Navy uses this stuff. A website: </span><span class=944415920-28022002><a href="http://www.ciaci.com/aloxcorporation.htm">http://www.ciaci.com/aloxcorporation.htm</a>
(although some of it is in Brazilian I think).</font></span><span class=944415920-28022002></span><span class=944415920-28022002><font color="#0000FF">I
can see why you'd be concerned.</font></span><span class=944415920-28022002></span><span class=944415920-28022002><font color="#0000FF">Hans</font></span><span class=944415920-28022002></span><span class=944415920-28022002>
<p><font face="Courier"><font color="#000000"><font size=-1>MIL-C-81309E</font></font></font>
<br></span><span class=944415920-28022002>
<p><font face="Courier"><font color="#000000"><font size=-1>MILITARY SPECIFICATION</font></font></font>
<p><font face="Courier"><font color="#000000"><font size=-1>CORROSION PREVENTIVE
COMPOUNDS, WATER DISPLACING,</font></font></font>
<p><font face="Courier"><font color="#000000"><font size=-1>ULTRA-THIN
FILM</font></font></font>
<br></span><span class=944415920-28022002>
<p><span
style="FONT-SIZE: 10pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA"><font face="Courier"><font size=-1>6.1
Intended use. The ultra-thin film, corrosion preventive compounds</span><span
style="FONT-SIZE: 12pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA"></span><span
style="FONT-SIZE: 10pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA">covered
by this specification are intended for use on any metal surface. It can
be used both for initial protection during shipment and storage and for</span><span
style="FONT-SIZE: 12pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA"></span><span
style="FONT-SIZE: 10pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA">in-service
treatment. It should not be used around liquid oxygen fittings. The ability
of these materials to prevent corrosion and to displace water and their
ease of application when packaged as class 2 (pressurized spray cans) make
them particularly suited for service use. These materials are intended
for indoor protection and short term protection outdoors where surfaces
can be recoated when required. These materials are not intended as a substitute
for other corrosion preventatives specified for protection of surfaces
for periods </span><span
style="FONT-SIZE: 12pt; FONT-FAMILY: Courier; mso-fareast-font-family: 'Times New Roman'; mso-bidi-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA">of
more than one month. </font></font></span>
<br></span>
<blockquote dir=ltr style="MARGIN-RIGHT: 0px">
<div class="OutlookMessageHeader" dir="ltr"><font face="Tahoma"><font size=-1>-----Original
Message-----</font></font>
<br><font face="Tahoma"><font size=-1><b>From:</b> Bev Christian [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</font></font>
<br><font face="Tahoma"><font size=-1><b>Sent:</b> Thursday, February 28,
2002 2:20 PM</font></font>
<br><font face="Tahoma"><font size=-1><b>To:</b> [log in to unmask]</font></font>
<br><font face="Tahoma"><font size=-1><b>Subject:</b> Re: [TN] Alox 2028D</font></font>
<br> </div>
<span class=205300819-28022002><font face="Arial"><font color="#0000FF"><font size=-1>I
fully agree with Phil. Surely they jest! Naphtha and trimethylbenzene
have reasonably high boiling points but they are still flammable solvents
and should be treated with respect. The latter has reported mutation
effects in lab animals (not specifically chemists). "Hydrocarbon"
is very broad, but usually means a cut or two above naphtha on the distillation
column. I would be concerned about higher boiling residues creeping
into switches, connectors; their effects on some of the cheaper plastics
and their really good ability to "suck" airborne dusts onto the circuit
pack. As far as the wax, which I presume is what they actually want
to put on their product, they might as well get my grandmother to melt
some jam wax in a double boiler and just pour it on their boards - just
kidding! </font></font></font></span><span class=205300819-28022002></span><span class=205300819-28022002><font face="Arial"><font color="#0000FF"><font size=-1>regards,</font></font></font></span><span class=205300819-28022002><font face="Arial"><font color="#0000FF"><font size=-1>Bev
Christian</font></font></font></span><span class=205300819-28022002><font face="Arial"><font color="#0000FF"><font size=-1>Research
in Motion</font></font></font></span><span class=205300819-28022002></span>
<br><font face="Tahoma"><font size=-1>-----Original Message-----</font></font>
<br><font face="Tahoma"><font size=-1><b>From:</b> Crepeau, Phil [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</font></font>
<br><font face="Tahoma"><font size=-1><b>Sent:</b> February 28, 2002 11:40
AM</font></font>
<br><font face="Tahoma"><font size=-1><b>To:</b> [log in to unmask]</font></font>
<br><font face="Tahoma"><font size=-1><b>Subject:</b> Re: [TN] Alox 2028D</font></font>
<br>
<blockquote dir=ltr style="MARGIN-RIGHT: 0px"><span class=715123916-28022002><font face="Arial"><font color="#0000FF"><font size=-1>hi,</font></font></font></span><span class=715123916-28022002></span><span class=715123916-28022002><font face="Arial"><font color="#0000FF"><font size=-1>surely
you jest. they may be confused. i use it on the chain of my
touring bike and it works great there.</font></font></font></span><span class=715123916-28022002></span><span class=715123916-28022002><font face="Arial"><font color="#0000FF"><font size=-1>phil</font></font></font></span>
<blockquote dir=ltr style="MARGIN-RIGHT: 0px">
<div class="OutlookMessageHeader" dir="ltr"><font face="Tahoma"><font size=-1>-----Original
Message-----</font></font>
<br><font face="Tahoma"><font size=-1><b>From:</b> Charlie Pitarys [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</font></font>
<br><font face="Tahoma"><font size=-1><b>Sent:</b> Thursday, February 28,
2002 8:07 AM</font></font>
<br><font face="Tahoma"><font size=-1><b>To:</b> [log in to unmask]</font></font>
<br><font face="Tahoma"><font size=-1><b>Subject:</b> [TN] Alox 2028D</font></font>
<br> </div>
<font size=-1> One of my customers has</font>
<br><font size=-1>selected the Alox 2028D for use as a protective coating
on their CCAs.</font>
<br><font size=-1>Can anyone share any info on the benefits of this product
(if any) in electronic packaging?</font>
<br><font size=-1>It is mainly Naptha, Trimethylbenzen, hydrocarbon and
parrafin wax. Described as a metalworking fluid additive.</font>
<p><font size=-1>I can envision a lot of problems with wash chemistry incompatibility,
insolubility and rinse water treatment etc.</font>
<p><font size=-1>Any info will be appreciated.</font>
<p><font size=-1>Thanks</font>
<p><font size=-1>Charlie Pitarys</font>
<br><font size=-1>Director of Application Technologies</font>
<br><font size=-1>603.622.2900 X-115</font>
<br><font size=-1>www.kyzen.com</font>
<br>
<br> </blockquote>
</blockquote>
</blockquote>
</blockquote>
</blockquote>
</html>
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Date: Thu, 28 Feb 2002 22:00:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Leland Woodall <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leland Woodall <[log in to unmask]>
Subject: Solder Paste - When is Ambient Temperature Reached?
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TechNetters,
I'm wondering if anyone can give me an idea of the amount of time needed for
a jar of solder paste to reach ambient temperature once it is removed from
refrigerated storage. The container is 90 mm tall and 80 mm in
circumference. The net weight is 1 kilogram, and the product is stored in a
40 degree F environment. Our facility consistently ranges from 70 to 72
degrees.
I understand condensation will form if opened prior to reaching room temp.
I had planned to insert a thermometer into the middle of the jar to get an
actual reading, but I also really hate to waste an expensive jar of paste to
perform such a simple experiment.
Thanks in advance for your input!
Leland Woodall
Quality Coordinator
Keihin Carolina System Technology, Inc.
Tarboro, NC 27886
Phone: 252-641-6750, ext. 2865
Email: [log in to unmask]
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Date: Thu, 28 Feb 2002 22:30:57 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: 'Flip-over' Assembly Fixtures?
X-To: Rick Thompson <[log in to unmask]>
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I don't have a source for your flip tables, but we used to use lots of those
tables with mass lead cutters. Maybe a mass lead cutter supplier can give
you a lead. [Is that too may uses of the word "lead"?] Try:
Q Corporation 301 River Derby, KS 67037 800.835.1099/316.788.3746 fax 7428
Fax [log in to unmask]
Dave Fish
----- Original Message -----
From: "Rick Thompson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, February 27, 2002 9:50 AM
Subject: [TN] 'Flip-over' Assembly Fixtures?
> I'm looking for a 'flip-over' assembly fixture for large PCBs (20" x
> 18"). I need something that can have a board inserted, hand load a
> quantity of through-hole parts, close a cover and flip over to solder
> the parts manually. I've found ones that handle 16" wide boards but
> none wider. Does anyone know of a source for this type of fixture?
>
> Thanks in advance.
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
> --------------------------------------------------------------------------
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>
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