Hi All!

I was wondering if there is a "rule-of-thumb" as far as trace length when laying out a via that is connected to a SMT pad to prevent secondary reflow during wave solder?

We just built a board here that I think had secondary reflow on a transistor. We didn't catch it because it is one of those JANTX ceramic leadless transistors. The customer caught it when they tried to power-up the board...it's a new design, so we don't have ICT or any other test yet. There is one location on the board that .020" long traces coming from .032" vias (I know those are big vias, huh?) that had the problem. The traces are .012" wide, 1-oz copper.

I'm gonna plug the via holes with mask on the next run, but I was wondering about a trace length not to go under to prevent the problem...

Thanks!!

-Steve Gregory-