Here is one I have recently been hit with. My current
incarnation as an engineer is with and RF component manufacturer. We recently
hired a new design engineer, he uses embedded inductors in the pcb fab. The
prototypes, produced with a board mill, worked fine. The pilot production boards
had a parametric problem. We traced it to a reduction in the inductor trace
width due to the etch factor (currently unspecified on the fab drawing.) Due to
size constraints the inductor uses .004" traces with .004" separation. So here
is the question; how do I specify the acceptable variation on a specific feature
of the PCB, and what is reasonable (i.e. how tight can I spec. trace variance
without driving the cost out of sight).
Thanks,
Dan