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Date: Mon, 21 Jan 2002 14:18:43 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: WS Solder Mask for Stencil Applications
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jorge: We apply water soluble temporary soldermask (TSR)using screen
printing instead of true stencils. The screens are about 1/10 the cost of a
stencil so you don't tie up a lot of dollars in stencil inventory. Unlike
stencils which are permanent the image can be washed out and the screen
re-imaged if there is a rev change or if you just want to use it on a
different P/N.
We use a contract service to mount/stretch and image the screens, most can
work from Gerber or film.
The screens use an aluminum chase with a 60 mesh polyester screen fabric.
The TSR is applied using a 60 durometer urethane squeegee.
Curing can be done at room temp 6-12hrs or accelerated be baking, 130C 5
mins.
The TSR material is supplied by Saati America 800-766-3676. The product name
is Dorn Temporary Solder Mask.
It is actually manufactured by Cerulean Blue Ltd. 206-525-8992. This used to
be an Alpha Metals product called HV-110 which was the screenable version of
there 110 water soluble TSR product family.
The TSR does not contain insoluble fillers such as clay, fumed silica etc,
which can clog wash nozzles build up in tank sumps or wear out pump seals on
aqueous washers.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Jorge Rodriguez [mailto:[log in to unmask]]
Sent: Monday, January 21, 2002 10:46 AM
To: [log in to unmask]
Subject: [TN] WS Solder Mask for Stencil Applications
Fellow Technetters,
I am looking for a water soluble solder mask that can be compatible
with stencil applications. We do quite a lot of solder mask applications
with a dispensing machine, but I am really looking into using a stencil
since it would speed up the process and help the ability to apply thinner SM
layers. I tried to do it with the one we use on the dispensing machines, but
it's too liquid and starts to cure at ambient temperature after 30 minutes,
so it was not possible.
Ha anybody accomplished this? Would there be a special WS solder
mask for stencil applications?
Any comments would be appreciated
Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]
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Date: Mon, 21 Jan 2002 17:22:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McCabe, Chris" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McCabe, Chris" <[log in to unmask]>
Subject: Re: Label Applications
X-To: Barry Gallegos <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Barry,
Questions that would help us:
What information is on the label (data/human readable)
What step in the process are you going to apply the label? (If you
want to read the label at the beginning of the process, you are looking at a
material like kapton, etc)
Size - do you have room for a 1D label, or will you use 2D (Data
Matrix)
Are you labeling panelized boards? If so, will you serialize the panel and
each individual board?
Are you open to other technologies, like Laser-etch, laser-bonding,
Continuous Ink Jet, etc
We evaluated several serialization options and have chosen to go with laser
etching a 2D data matrix serial number on our boards.
Regards,
Chris
-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Monday, January 21, 2002 2:43 PM
To: [log in to unmask]
Subject: [TN] Label Applications
Good Day,
I have been tasked to par-take in a team effort to identify different
application methods for
labeling. any directions or help would be appreciated.
Barry.
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Date: Tue, 22 Jan 2002 09:16:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Parts with 100% Tin finish
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Danny
We don't run a production. However, in our project LEADFREE we tried =
SnPb36Ag2 in convection and SnPb37 in wave with tin plated components on =
pure tin PCB's and we didn't see any problems when using the standard =
profile our industrial partners suggested.
From the point of reliability I don't see any problem since you don't =
bring any new material into the solder joint and the amount of tin added =
to the solder is not a big deal.
Best regards
Guenter
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Tue, 22 Jan 2002 08:53:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Schwarzkopf, Todd" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Schwarzkopf, Todd" <[log in to unmask]>
Subject: Smoky Mountain IPC Designer's Council January Meeting
X-To: [log in to unmask]
X-cc: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Smoky Mountain IPC Designer's Council January Meeting:
Our next meeting will be January 24th. It will be held at Philips
(directions below). The speaker and sponsor will be Bob Hoffman with
Amitron Corporation. Take a look at their web site at www.amitroncorp.com
<http://www.amitroncorp.com> <http://www.amitroncorp.com
<http://www.amitroncorp.com> > .
Here is a list of topics:
Eductor Plating Technology
Ionic Contamination on Bare Boards
Liquid Photo-Mask Applications for BGAs and/or QFPs
Aluminum Bonded Heat Sink Substrates
10 - 18 Multi-Layer PCB Construction
Agenda:
6:00pm to 7:00pm - Dinner (pizza) and social hour.
7:00pm - 9:00pm - Chapter business followed by a presentation by Bob
Hoffman from Amitron.
This should be a very informative meeting. I hope to see you there.
Directions from Knoxville,
I-40 East (toward Asheville)
Take Strawberry Plains Pike Exit (Exit 398)
Turn right on Strawberry Plains Pike
Go .37 miles to One Philips Drive.
There will be a security gate. State your name and business.
The guard will open the gate.
Someone will meet you in the main lobby.
Please RSVP to me by Email by Wednesday at the latest.
Todd Schwarzkopf, C.I.D.
PCB Designer
AMETEK
Advanced Measurement Technology
801 S. Illinois Ave.
Oak Ridge, TN 37831-0895
[log in to unmask]
Voice: (865) 481-2427
Fax: (865) 481-2438
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Date: Tue, 22 Jan 2002 08:12:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Wire Harness & Cable Standards.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.
Barry.
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Date: Tue, 22 Jan 2002 07:55:22 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
let me refer you to an email from j. crawford that should help you. i've copied and pasted it below.
phil
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness Assemblies is progressing well. It is projected to be circulated as a Proposed Standard within a week pending some last minute tweaks. The goal is still to have it published this year.
You can download review files from the IPC public FTP site using a standard browser (but NOT the AOL built-in browser). Just launch your Netscape or Internet Explorer (if using AOL, log on first, THEN launch one of the browsers and everything will work fine). In the URL Address line, put ONLY the following numbers. DO NOT PUT ANY LETTERS like www or anything: 216.203.210.37
You'll see a folder called 620-WireDocs. Open it and you'll see the files. Start with 620-01 for an index and document scope. Send comments to me directly (OFF NET). Some chapters have both high and low resolution illustrations. Content is the same, high resolution files have better quality pictures but take longer to download with a slow modem connection.
Hope this helps.
Jack
-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 7:12 AM
To: [log in to unmask]
Subject: [TN] Wire Harness & Cable Standards.
Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.
Barry.
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Date: Tue, 22 Jan 2002 10:59:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
X-To: Barry Gallegos <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Barry,
NASA-STD-8739.4 dtd February 1998 (replaced NAS 5300.4(3G-1))
IPC/WHMA-A-620 (which is under development but a good reference)
SAE AS4461 (I have rev A dtd 12/30/92)
Hope this helps!
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.
Barry.
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Date: Tue, 22 Jan 2002 08:13:35 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: WS Solder Mask for Stencil Applications
X-To: [log in to unmask]
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
I have used Wondermask from Techspray, #2207-p. It is billed as a screenable
water soluble mask. I used a standard stencil, .005" thick, after curing for
30 min at 150F the solder paste was stenciled onto the assembly. After
reflow the assemblies were washed and the I/O pins hand soldered, no
problems with solderability.
Dan
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Date: Tue, 22 Jan 2002 11:54:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
X-To: "Crepeau, Phil" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed. Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week. I have the
620 files dated Mar-01. To your knowledge, what are the revision/date of
the latest released working drafts? Thanks in advance.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well. It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal is
still to have it published this year.
You can download review files from the IPC public FTP site using a standard
browser (but NOT the AOL built-in browser). Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine). In the URL Address line, put ONLY
the following numbers. DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37
You'll see a folder called 620-WireDocs. Open it and you'll see the files.
Start with 620-01 for an index and document scope. Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations. Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.
---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 22 Jan 2002 12:10:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Paul Truit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Truit <[log in to unmask]>
Organization: RBB Systems Inc.
Subject: Solder fill of via's and reliability
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.
I am seeing more and more designs with the vias covered. Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA? Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process? Expecting .001" but getting
.0007-.0008" copper plating.
Should via's be left uncovered?
Respectfully
Paul
--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH 44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]
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Date: Tue, 22 Jan 2002 11:38:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: Re: Solder fill of via's and reliability
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Paul,
The need of solder mask when dealing with wave solder and SMT is to
prevent flux entrapment. This can happen when vias are found underneath SMT
devices. The other concern is the heat transfer to the top side under the
same conditions. We are currently facing a problem with a customer that
likes to use 25 mils vias under fine pitch devices. This is causing some
issues at the wave solder operation, the QFPs re-melt again creating solder
opens. The alternative of reducing the temperature at the preheaters doesn't
solve the problem since we face another one, flux doesn't get activated and
we end up with solder balls on the top side, solvents get entrapped on the
vias and explode at the wave like a volcano.
Jorge
-----Original Message-----
From: Paul Truit [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 10:11 AM
To: [log in to unmask]
Subject: [TN] Solder fill of via's and reliability
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.
I am seeing more and more designs with the vias covered. Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA? Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process? Expecting .001" but getting
.0007-.0008" copper plating.
Should via's be left uncovered?
Respectfully
Paul
--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH 44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]
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Date: Tue, 22 Jan 2002 14:02:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Solder fill of via's and reliability
X-To: Paul Truit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Paul,
Years ago, the military high reliability soldering standards required PTHs
to be filled with a solder plug (wave soldered only, 25% recession
acceptable) or wire (swaged stud or clinched "C" or "Z" form) soldered in
the holes of type of 2 and 3 printed wiring boards.
After extensive testing and evaluation (data was also presented to the
military folks by industry), it was determined that the via holes could be
left unsoldered without compromising reliability of the interconnection.
The one drawback is partial fill of these via holes, when subjected to
stress and strain, the forces imparted on the PTH structure are not equally
distributed. As such, this can cause the PTH to fail prematurely. As such,
it is better to either fully fill the hole or leave the hold unfilled.
With respect to tenting of vias, I look at the following factors:
gasketing during in-circuit testing
minimize the amount of exposed conductive circuitry
- shorting potential
- cleaning challenges
In light of the above, it all depends on your end item application and
environment. If you're worried about the reliability of your holes with
respect to wall thickness, I would specify what you want to your supplier
and then verify. As Moonman says, "specify, verify and never trust". The
only time that I would leave PTHs uncovered would be for test purposes, but
I would normally specify pads/targets for test points.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.
I am seeing more and more designs with the vias covered. Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA? Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process? Expecting .001" but getting
.0007-.0008" copper plating.
Should via's be left uncovered?
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Date: Tue, 22 Jan 2002 15:00:43 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Solder fill of via's and reliability
X-To: Paul Truit <[log in to unmask]>
MIME-Version: 1.0
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Vias may rob adjacent SJ if not masked.
That's the only justifiable beef I've had that forces masking. Unmasked vias
are just artifacts of CAD SW, unless used for ICT points.
RL
----- Original Message -----
From: Paul Truit <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 22, 2002 9:10 AM
Subject: [TN] Solder fill of via's and reliability
> I am interested in hearing others views in regard to allowing the wave
> soldering process to fill the vias with solder or tenting the vias with
> soldermask and how this relates to reliability.
>
> I am seeing more and more designs with the vias covered. Wouldn't
> allowing the vias to fill with solder increase the reliability of the
> PCA? Or is this a matter of covering for the "sins" of the bare board
> manufacturer's plating process? Expecting .001" but getting
> .0007-.0008" copper plating.
>
> Should via's be left uncovered?
>
> Respectfully
>
> Paul
>
>
> --
> Paul Truit, Mfg. Eng.
> RBB Systems, Inc.
> 4265C E. Lincolnway
> Wooster, OH 44691
> Ph. (330) 567-2906 ext 514
> Fax (330) 263-5324
> Email: [log in to unmask]
>
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Date: Tue, 22 Jan 2002 13:03:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
X-To: "Sauer, Steven T." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Thank you All for your help.
Barry.
-----Original Message-----
From: Sauer, Steven T. [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 9:55 AM
To: [log in to unmask]
Subject: Re: [TN] Wire Harness & Cable Standards.
Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed. Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week. I have the
620 files dated Mar-01. To your knowledge, what are the revision/date of
the latest released working drafts? Thanks in advance.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well. It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal is
still to have it published this year.
You can download review files from the IPC public FTP site using a standard
browser (but NOT the AOL built-in browser). Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine). In the URL Address line, put ONLY
the following numbers. DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37
You'll see a folder called 620-WireDocs. Open it and you'll see the files.
Start with 620-01 for an index and document scope. Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations. Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.
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Date: Tue, 22 Jan 2002 16:02:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: FR4 power module SMC coplanarity
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
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Any option must be known good before hardware is designed. I don't design
for the trash can.
Am aware of BT material option. We are currently ceramic with no problems,
with much push from high-priced-help to migrate to FR4 ' like everybody
else'. Of course there are no concrete examples of SMD in FR4 forthcoming,
but that doesn't reduce push from above. They would need a documented
disaster story to decide that they knew, all along, it was a bad idea.
Question is to actual performance of FR4 modules with dims equal to or
exceeding 2inches on one side. Any feedback of simple successes/niggling
problems?
Is 0.1millimeter/ .004inch achievable and how?
RL
----- Original Message -----
From: Earl Moon <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 21, 2002 5:24 AM
Subject: Re: [TN] FR4 power module SMC coplanarity
> First let me say Eric must know the lady about whom I speak. Ouch!
>
> Concerning a more vital, doubt it, issue, there is no reason to expect the
> PCB version, on whatever material, will go out of whack like a potato
chip.
> BGA's are built on BT based boards and they stay reasonably flat.
>
> You know it depends on how well the design was effected. You know -
balance,
> construction, etc.
>
> Just have to try them and see. If they do warp, what are your options?
>
> MoonMan
>
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Date: Tue, 22 Jan 2002 15:54:43 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mike Manwell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mike Manwell <[log in to unmask]>
Subject: Solder Analysis
Hello folks,
Im looking for a facility that does solder sample analysis.
Im aware of Alpha Analytical Laboratories but before signing up, cant help
but wonder if there are others out there.
Any suggestions?
Thanks,
Mike Manwell
Integrex Inc.
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Date: Tue, 22 Jan 2002 17:42:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: FR4 power module SMC coplanarity
X-To: R Legg <[log in to unmask]>
I hope we're on the same page. I agree FR4 material should be adequate. BT
offers higher Tg but other characteristice remain the same. That doesn't
matter but for longer z axis expansion duration before delam and total
failure. From a warpage standpoint, is what I'm talking about as I thought
you were. No offense intended. I was trying to back you up.
MoonMan
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Date: Tue, 22 Jan 2002 17:44:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Solder fill of via's and reliability
X-To: R Legg <[log in to unmask]>
I'm currently going down this path - especially pertaining to BGA's, ICT,
and functional testing requirements. Everyone thoroubhly read the test
requirements in 2221?
MoonMan
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Date: Tue, 22 Jan 2002 17:48:07 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: ASSEMBLED BOARD IPC TEST REQUIREMENTS
Never would I question the IPC wisdom concerning anything. I would question
how the heck does one find specific guidelines cocnerning assembled board
requirements? The search engine just didn't get it for me.
What is the guideline, beyond 2221, for loaded board testing as ICT and
functional test requirements?
MoonMan
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Date: Tue, 22 Jan 2002 19:14:59 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Solder Analysis
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_179.286a608.297f5a83_boundary"
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Content-Type: text/plain; charset="US-ASCII"
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Mike,
I know that besides Alpha, Shipley does and so does my company,
Florida CirTech. All companies provide a high quality bar solder and should
provide free analysis. The price of tin is down now so you should see prices
for bar solder around the low $2/lb or less depending on usage.
Steve Wentz
--part1_179.286a608.297f5a83_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Mike,
<BR> I know that besides Alpha, Shipley does and so does my company, Florida CirTech. All companies provide a high quality bar solder and should provide free analysis. The price of tin is down now so you should see prices for bar solder around the low $2/lb or less depending on usage.
<BR>
<BR>Steve Wentz</FONT></HTML>
--part1_179.286a608.297f5a83_boundary--
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Date: Wed, 23 Jan 2002 08:27:05 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
X-To: Barry Gallegos <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Barry,
Don't know your required standard, but the two specs I know of are
MIL-C-45224 (General Spec for Cables and Assemblies, Electrical Missile
System) [This extends to other equipment wiring as well], and MIL-W-5088L
(Wiring, Aerospace Vehicle) [which deals more specifically with aircraft
wiring systems].
Hope this is of some use.
Peter
Barry Gallegos
<barryg@WESTERNELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Wire Harness & Cable Standards.
01/22/02 11:12 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Barry
Gallegos
Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.
Barry.
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Date: Tue, 22 Jan 2002 16:21:29 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Thorup, John" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Thorup, John" <[log in to unmask]>
Subject: Re: Solder Analysis
X-To: Mike Manwell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
among others, the Kester mail in kits are available from any Kester
distributor. You choose your desired level of analysis, pay for it, and
receive a mailer pack with a coupon to submit your sample. A certified
computerized analysis is returned in a week to 10 days.
> -----Original Message-----
> From: Mike Manwell [SMTP:[log in to unmask]]
> Sent: Tuesday, January 22, 2002 1:55 PM
> To: [log in to unmask]
> Subject: [TN] Solder Analysis
>
> Hello folks,
>
> Im looking for a facility that does solder sample analysis.
> Im aware of Alpha Analytical Laboratories but before signing up, cant help
> but wonder if there are others out there.
> Any suggestions?
>
> Thanks,
> Mike Manwell
> Integrex Inc.
>
> --------------------------------------------------------------------------
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Date: Tue, 22 Jan 2002 19:30:59 EST
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Date: Tue, 22 Jan 2002 19:33:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Collins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards.
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Phil / Steve / Barry
The IPC 620 document is released. I'm standing about 100 feet from the IPC =
booth and just checked it out, going to buy a copy but I already have the =
400 lb proceedings book to carry around today.
>>> [log in to unmask] 01/22/02 12:56 PM >>>
Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed. Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week. I have the
620 files dated Mar-01. To your knowledge, what are the revision/date of
the latest released working drafts? Thanks in advance.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well. It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal =
is
still to have it published this year.
You can download review files from the IPC public FTP site using a =
standard
browser (but NOT the AOL built-in browser). Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine). In the URL Address line, put =
ONLY
the following numbers. DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37
You'll see a folder called 620-WireDocs. Open it and you'll see the =
files.
Start with 620-01 for an index and document scope. Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations. Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.
---------------------------------------------------------------------------=
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------
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Date: Wed, 23 Jan 2002 11:53:42 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Colin Weber <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Colin Weber <[log in to unmask]>
Subject: D-Range & EMI
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Folks,
Does anyone know of any D-Range connectors with in-built, In line RF filtering?
Regards,
Colin Weber
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Date: Tue, 22 Jan 2002 20:17:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Stephen Gregory <[log in to unmask]>
Subject: Re: Wire Harness & Cable Standards...and APEX stuff
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_46.2143abeb.297f692d_boundary"
--part1_46.2143abeb.297f692d_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hey Graham!
Do they have all the computers along the wall that you can check your email
with (like last year)?
I think Mike Sewell told me that he was going to try and make the lunch with
you and Ed on Thursday (he's one of the lucky guys that was able to attend
this year from our plant). Ed is real familiar with us in Tulsa,
"Okra-homie", we bought a Treiber 700B wave solder from him, he came out to
help with the installation...ask him about it. There's a REALLY good story
there!
If you run into Mike Sewell, tell him that Steve said he should be glad he's
not here in Tulsa now, and enjoy the time he has away from the
plant...(hehehe).
Wish I was there, maybe next year...
-Steve Gregory-
> Hi Phil / Steve / Barry
> The IPC 620 document is released. I'm standing about 100 feet from the IPC
> booth and just checked it out, going to buy a copy but I already have the
> 400 lb proceedings book to carry around today.
>
--part1_46.2143abeb.297f692d_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey Graham!<BR>
<BR>
Do they have all the computers along the wall that you can check your email with (like last year)?<BR>
<BR>
I think Mike Sewell told me that he was going to try and make the lunch with you and Ed on Thursday (he's one of the lucky guys that was able to attend this year from our plant). Ed is real familiar with us in Tulsa, "Okra-homie", we bought a Treiber 700B wave solder from him, he came out to help with the installation...ask him about it. There's a REALLY good story there!<BR>
<BR>
If you run into Mike Sewell, tell him that Steve said he should be glad he's not here in Tulsa now, and enjoy the time he has away from the plant...(hehehe).<BR>
<BR>
Wish I was there, maybe next year...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Phil / Steve / Barry<BR>
The IPC 620 document is released. I'm standing about 100 feet from the IPC booth and just checked it out, going to buy a copy but I already have the 400 lb proceedings book to carry around today.<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_46.2143abeb.297f692d_boundary--
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=========================================================================
Date: Tue, 22 Jan 2002 17:24:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: D-Range & EMI
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
don't know 'd-range', but if that's the same as 'd-subminiature' try the following:
http://www.ittcannon.com/products/products.asp?pid=1005
phil
-----Original Message-----
From: Colin Weber [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] D-Range & EMI
Folks,
Does anyone know of any D-Range connectors with in-built, In line RF filtering?
Regards,
Colin Weber
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=========================================================================
Date: Tue, 22 Jan 2002 21:41:52 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Stephen Gregory <[log in to unmask]>
Subject: VME stuff again...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hey all ya'll!
VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.
Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will comply
with VME spec's.
This board is 16-layers, within .063" without Stablecor, if we use 2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
far as thermal dissapation and CTE solutions), it will increase .030-.035".
This Stablcor material sounds like a really good solution for thermal and CTE
solutions, but has a hard time staying within the dimensional spec's that are
called out in the VME spec's...trying to change these spec's I know is an act
of God...it's there, and it's done.
Just wondering if anybody else has explored this material, and have come to a
dead-end like I have....because of the reasons like I have.
-Steve Gregory-
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Tue, 22 Jan 2002 21:07:55 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hugh Day <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hugh Day <[log in to unmask]>
Subject: Re: Solder Analysis
X-To: Mike Manwell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Mike,
Here is a real sleeper company that has been around for 100 years,
literally, the name of the company is Nathan Trotter & Co., Inc.
specializing in electronic grade alloys, tin products, and solder analysis.
The phone # is 610-524-1440
ask for Peter Morris.
----- Original Message -----
From: Mike Manwell <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 22, 2002 3:54 PM
Subject: [TN] Solder Analysis
> Hello folks,
>
> Im looking for a facility that does solder sample analysis.
> Im aware of Alpha Analytical Laboratories but before signing up, cant help
> but wonder if there are others out there.
> Any suggestions?
>
> Thanks,
> Mike Manwell
> Integrex Inc.
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
-------
>
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=========================================================================
Date: Wed, 23 Jan 2002 11:36:34 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: VME stuff again...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
We ran into the same problem (more or less) - thermal management
requirements and solutions conflicted with the VME spec (which spec did you
go with, by the way?).
One solution we considered, but didn't implement owing to expense, is to
"step" the PCB so that it's the right thickness at the card guide edges and
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
know. Makes routing traces to the connectors a bit circuitous too (pun
intended). The board thickness outwith these areas is not important, as
long as it, plus the component height, doesn't exceed the envelope max.
You'll need some pretty light-weight copper and very thin separation layers
to fit 16 layers into the spec'd thickness. Good luck!
Peter
Stephen
Gregory To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: [TN] VME stuff again...
TechNet
<[log in to unmask]
ORG>
01/23/02
10:41 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hey all ya'll!
VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just
from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.
Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
comply
with VME spec's.
This board is 16-layers, within .063" without Stablecor, if we use 2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
far as thermal dissapation and CTE solutions), it will increase .030-.035".
This Stablcor material sounds like a really good solution for thermal and
CTE
solutions, but has a hard time staying within the dimensional spec's that
are
called out in the VME spec's...trying to change these spec's I know is an
act
of God...it's there, and it's done.
Just wondering if anybody else has explored this material, and have come to
a
dead-end like I have....because of the reasons like I have.
-Steve Gregory-
---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 22 Jan 2002 23:19:10 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Stephen Gregory <[log in to unmask]>
Subject: Re: VME stuff again...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_da.12886cfe.297f93be_boundary"
--part1_da.12886cfe.297f93be_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Peter!
The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.
From a personal view, I think that VITA established the standards prematurely
without considering how the the technology was going to evolove. As you know,
VME assemblies are extremely dense, basically single board computers.
The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so far
from the BOM).
Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...
Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat dissipation,
and CTE issues, but can't use it because of the VME spec...this is one of
what came first, "The chicken or the egg?" huh?
-Steve Gregory-
> Hi, Steve,
>
> We ran into the same problem (more or less) - thermal management
> requirements and solutions conflicted with the VME spec (which spec did you
> go with, by the way?).
>
> One solution we considered, but didn't implement owing to expense, is to
> "step" the PCB so that it's the right thickness at the card guide edges and
> at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
> know. Makes routing traces to the connectors a bit circuitous too (pun
> intended). The board thickness outwith these areas is not important, as
> long as it, plus the component height, doesn't exceed the envelope max.
>
> You'll need some pretty light-weight copper and very thin separation layers
> to fit 16 layers into the spec'd thickness. Good luck!
>
> Peter
>
>
>
>
> Stephen
> Gregory To: [log in to unmask]
> <SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> L.COM> Aero/ST Group)
> Sent by: Subject: [TN] VME stuff
> again...
> TechNet
> <[log in to unmask]
> ORG>
>
>
> 01/23/02
> 10:41 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hey all ya'll!
>
> VME stuff again. Pretty strict standard. Gotta new technology out there
> called Stablcor from Thermalworks, problem that we're seeing is that board
> thickness is going to increase, which violates the VME spec's. Not just
> from
> the card-guide aspects, but will change the dimension where the P1 and P2
> connectors interface with the backplane on a standard VME card cage.
>
> Just wondering if anybody has anything out there (connectors, etc.), that
> will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
> comply
> with VME spec's.
>
> This board is 16-layers, within .063" without Stablecor, if we use 2-layers
> Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
> far as thermal dissapation and CTE solutions), it will increase .030-.035".
>
> This Stablcor material sounds like a really good solution for thermal and
> CTE
> solutions, but has a hard time staying within the dimensional spec's that
> are
> called out in the VME spec's...trying to change these spec's I know is an
> act
> of God...it's there, and it's done.
>
> Just wondering if anybody else has explored this material, and have come to
> a
> dead-end like I have....because of the reasons like I have.
>
> -Steve Gregory-
>
--part1_da.12886cfe.297f93be_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Peter!<BR>
<BR>
The spec that you quoted, is what is being followed. I'm going to purchase the spec so that we have it here...since it appears that we're getting into the business of "ruggedizing" commercial VME assemblies.<BR>
<BR>
From a personal view, I think that VITA established the standards prematurely without considering how the the technology was going to evolove. As you know, VME assemblies are extremely dense, basically single board computers. <BR>
<BR>
The assembly that I'm looking at is double-sided SMT, fine pitch on both sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so far from the BOM).<BR>
<BR>
Not sure if establishing these restrictions are a good thing, so that everything will fit as established, or if it's better to stay fluid so that you can adjust to adapt to changes in the technology...I suppose there's arguments on both sides...<BR>
<BR>
Just know now that we have an assembly that can take advantage of some new substrate technology, that sounds very promising as far as heat dissipation, and CTE issues, but can't use it because of the VME spec...this is one of what came first, "The chicken or the egg?" huh?<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi, Steve,<BR>
<BR>
We ran into the same problem (more or less) - thermal management<BR>
requirements and solutions conflicted with the VME spec (which spec did you<BR>
go with, by the way?).<BR>
<BR>
One solution we considered, but didn't implement owing to expense, is to<BR>
"step" the PCB so that it's the right thickness at the card guide edges and<BR>
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't<BR>
know. Makes routing traces to the connectors a bit circuitous too (pun<BR>
intended). The board thickness outwith these areas is not important, as<BR>
long as it, plus the component height, doesn't exceed the envelope max.<BR>
<BR>
You'll need some pretty light-weight copper and very thin separation layers<BR>
to fit 16 layers into the spec'd thickness. Good luck!<BR>
<BR>
Peter<BR>
<BR>
<BR>
<BR>
<BR>
Stephen<BR>
Gregory To: [log in to unmask]<BR>
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST<BR>
L.COM> Aero/ST Group)<BR>
Sent by: Subject: [TN] VME stuff again...<BR>
TechNet<BR>
<[log in to unmask]<BR>
ORG><BR>
<BR>
<BR>
01/23/02<BR>
10:41 AM<BR>
Please<BR>
respond to<BR>
"TechNet<BR>
E-Mail<BR>
Forum.";<BR>
Please<BR>
respond to<BR>
SteveZeva<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
Hey all ya'll!<BR>
<BR>
VME stuff again. Pretty strict standard. Gotta new technology out there<BR>
called Stablcor from Thermalworks, problem that we're seeing is that board<BR>
thickness is going to increase, which violates the VME spec's. Not just<BR>
from<BR>
the card-guide aspects, but will change the dimension where the P1 and P2<BR>
connectors interface with the backplane on a standard VME card cage.<BR>
<BR>
Just wondering if anybody has anything out there (connectors, etc.), that<BR>
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will<BR>
comply<BR>
with VME spec's.<BR>
<BR>
This board is 16-layers, within .063" without Stablecor, if we use 2-layers<BR>
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as<BR>
far as thermal dissapation and CTE solutions), it will increase .030-.035".<BR>
<BR>
This Stablcor material sounds like a really good solution for thermal and<BR>
CTE<BR>
solutions, but has a hard time staying within the dimensional spec's that<BR>
are<BR>
called out in the VME spec's...trying to change these spec's I know is an<BR>
act<BR>
of God...it's there, and it's done.<BR>
<BR>
Just wondering if anybody else has explored this material, and have come to<BR>
a<BR>
dead-end like I have....because of the reasons like I have.<BR>
<BR>
-Steve Gregory-<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_da.12886cfe.297f93be_boundary--
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Date: Wed, 23 Jan 2002 12:51:26 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: VME stuff again...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
Sounds like you're having fun with this one, and I would be most interested
in being allowed to share your evolving experiences with trying to use
Stablcor. I flagged this material up to our designers when I first heard of
it (being simple souls, they'd designed our boards with good ol' FR4), but
we haven't had the excuse to look into using it yet.
The specs are now aging, and you're right about how densely packed the
boards have become, with folks trying to pack as much functionality into
each as humanly, or inhumanly, possible. I look at it as a cocoon within
which, and from which, any number of beautiful butterflies can grow and
emerge. (What DID that girl put in my coffee?) We have two boards on the go
that are a distillation of the functionality of five slots previously.
They've given me a folicular race between going grey or bald (it's neck and
neck at the moment).
The one thing we had to give serious priority to after the component
selection stage was layout to balance thermal mass around the board,
placing hotter components closest to the best thermal path through the
board, and particularly putting the hottest ones on the component side
where there was Max Headroom (remember him? I loved that guy). That way, if
the thermal path through the board is still not enough, you have some scope
for taking the heat out over the top with nice chunks of metal and thermal
pads. Pity there's no room for Pentium 4 style heatsinks here! There's no
room at all for overhead heat sinks on the solder side.
My sincerest sympathies!
Peter
Stephen
Gregory To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] VME stuff again...
TechNet
<[log in to unmask]
ORG>
01/23/02
12:19 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi Peter!
The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.
From a personal view, I think that VITA established the standards
prematurely without considering how the the technology was going to
evolove. As you know, VME assemblies are extremely dense, basically single
board computers.
The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so
far from the BOM).
Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...
Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat
dissipation, and CTE issues, but can't use it because of the VME
spec...this is one of what came first, "The chicken or the egg?" huh?
-Steve Gregory-
Hi, Steve,
We ran into the same problem (more or less) - thermal management
requirements and solutions conflicted with the VME spec (which spec did
you
go with, by the way?).
One solution we considered, but didn't implement owing to expense, is to
"step" the PCB so that it's the right thickness at the card guide edges
and
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
know. Makes routing traces to the connectors a bit circuitous too (pun
intended). The board thickness outwith these areas is not important, as
long as it, plus the component height, doesn't exceed the envelope max.
You'll need some pretty light-weight copper and very thin separation
layers
to fit 16 layers into the spec'd thickness. Good luck!
Peter
Stephen
Gregory To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: [TN] VME stuff
again...
TechNet
<[log in to unmask]
ORG>
01/23/02
10:41 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hey all ya'll!
VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just
from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.
Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
comply
with VME spec's.
This board is 16-layers, within .063" without Stablecor, if we use
2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best,
as
far as thermal dissapation and CTE solutions), it will increase
.030-.035".
This Stablcor material sounds like a really good solution for thermal and
CTE
solutions, but has a hard time staying within the dimensional spec's that
are
called out in the VME spec's...trying to change these spec's I know is an
act
of God...it's there, and it's done.
Just wondering if anybody else has explored this material, and have come
to
a
dead-end like I have....because of the reasons like I have.
-Steve Gregory-
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 23 Jan 2002 09:12:43 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Solder Analysis
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Mike
What kind of analysis, what region (US, GB...)
Best regards
Guenter
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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=========================================================================
Date: Wed, 23 Jan 2002 08:11:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Morning Earl,
The only thing I could find that remotely has to do with test is, IPC-6018A
"Microwave End Product Board Inspection and Test". I'll keep looking and
forward what I find something that more closely matches your needs.
So you're going to add DFT to your DFM/CE? Makes sense to be able to test
the darned thing after you've been able to manufacture the thing cost
effectively!!
I thought HP, GenRad, Everett Charles, etc., published testability design
guidelines -- some of which are pie in the sky (i.e. .080" target with .050"
clearance)?
Hope this helps.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
What is the guideline, beyond 2221, for loaded board testing as ICT and
functional test requirements?
MoonMan
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=========================================================================
Date: Wed, 23 Jan 2002 07:49:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: Steve Sauer <[log in to unmask]>
Steve,
Thanks, thought I was loosing it again not finding anything IPC related.
Yes about DFT as, to me, it is an integral part of DFM/CE.
I will use the test equipment recommendations only if IPC doesn't have
anything but what is in 2221.
Enjoy,
Earl
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Date: Wed, 23 Jan 2002 07:40:55 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: VME stuff again...
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
All this talk about getting rid of heat sounds scary. If I remember right,
these bus type frames, of which VME is only one, have a limited amount of
power available per card slot. If you exceed that, the other slots go
hungry, or you find yourself with a long-term power supply reliability
problem. To paint a blacker picture, most of the power supplies in these
boxes have specs that indicate they can deliver lots of power and they can
work at the resulting higher temperatures, but often they cannot do both
simultaneously!!
And a worse result is that all that input power turns into output heat. From
my experience heat is a serious problem in these boxes. It is a problem in
19" rackmount card cages in the first place to get the heat away from the
VME card, secondly to get it out of the VME box and in the third place to
get it out of the 19" rack (or where ever you put it).
A last thought: heat is often not a problem for today, it lets its presence
known in the future, so you end up with field failures: RELIABILITY.
Good luck with your investigations,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of <Peter George Duncan>
Sent: Tuesday, January 22, 2002 20:51
To: [log in to unmask]
Subject: Re: [TN] VME stuff again...
Hi, Steve,
Sounds like you're having fun with this one, and I would be most interested
in being allowed to share your evolving experiences with trying to use
Stablcor. I flagged this material up to our designers when I first heard of
it (being simple souls, they'd designed our boards with good ol' FR4), but
we haven't had the excuse to look into using it yet.
The specs are now aging, and you're right about how densely packed the
boards have become, with folks trying to pack as much functionality into
each as humanly, or inhumanly, possible. I look at it as a cocoon within
which, and from which, any number of beautiful butterflies can grow and
emerge. (What DID that girl put in my coffee?) We have two boards on the go
that are a distillation of the functionality of five slots previously.
They've given me a folicular race between going grey or bald (it's neck and
neck at the moment).
The one thing we had to give serious priority to after the component
selection stage was layout to balance thermal mass around the board,
placing hotter components closest to the best thermal path through the
board, and particularly putting the hottest ones on the component side
where there was Max Headroom (remember him? I loved that guy). That way, if
the thermal path through the board is still not enough, you have some scope
for taking the heat out over the top with nice chunks of metal and thermal
pads. Pity there's no room for Pentium 4 style heatsinks here! There's no
room at all for overhead heat sinks on the solder side.
My sincerest sympathies!
Peter
Stephen
Gregory To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] VME stuff
again...
TechNet
<[log in to unmask]
ORG>
01/23/02
12:19 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi Peter!
The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.
>From a personal view, I think that VITA established the standards
prematurely without considering how the the technology was going to
evolove. As you know, VME assemblies are extremely dense, basically single
board computers.
The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so
far from the BOM).
Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...
Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat
dissipation, and CTE issues, but can't use it because of the VME
spec...this is one of what came first, "The chicken or the egg?" huh?
-Steve Gregory-
Hi, Steve,
We ran into the same problem (more or less) - thermal management
requirements and solutions conflicted with the VME spec (which spec did
you
go with, by the way?).
One solution we considered, but didn't implement owing to expense, is to
"step" the PCB so that it's the right thickness at the card guide edges
and
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
know. Makes routing traces to the connectors a bit circuitous too (pun
intended). The board thickness outwith these areas is not important, as
long as it, plus the component height, doesn't exceed the envelope max.
You'll need some pretty light-weight copper and very thin separation
layers
to fit 16 layers into the spec'd thickness. Good luck!
Peter
Stephen
Gregory To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: [TN] VME stuff
again...
TechNet
<[log in to unmask]
ORG>
01/23/02
10:41 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hey all ya'll!
VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just
from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.
Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
comply
with VME spec's.
This board is 16-layers, within .063" without Stablecor, if we use
2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best,
as
far as thermal dissapation and CTE solutions), it will increase
.030-.035".
This Stablcor material sounds like a really good solution for thermal and
CTE
solutions, but has a hard time staying within the dimensional spec's that
are
called out in the VME spec's...trying to change these spec's I know is an
act
of God...it's there, and it's done.
Just wondering if anybody else has explored this material, and have come
to
a
dead-end like I have....because of the reasons like I have.
-Steve Gregory-
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
----------------------------------------------------------------------------
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=========================================================================
Date: Wed, 23 Jan 2002 10:57:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Tarnished Surface
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi everyone,
We recently had a board fabricated with silver finish.
After it came back from assembly house the exposed silver finish is been
tarnish(color changed to brown)during assembly.
Does any one here has seen this before? The assembly done manually and the
tarnishing
happened after they washed the board.
I appreciate any comment on this.
Thank You
Shahed
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=========================================================================
Date: Wed, 23 Jan 2002 18:21:53 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Tarnished Surface
X-To: Safavi-Bayat Shahed <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Shahed
Because your board is clean, the silver is exposed to the atmosphere.
There are trace amounts of sulfur dioxide and hydrogen sulfide in the
air, derived mostly from burning fossil fuels, but also from volcanic
activity. Silver has an affinity for sulfur and forms silver sulfide,
which is the brownish film you are seeing. Electrically, its presence
will be perfectly benign: it is only cosmetically that it is
disagreeable.
There is no way of preventing it, but its onset may be delayed but,
frankly, I don't recommend it because it means using products which may
degrade the electrical performance, just to gain a few month's
brilliance. If it is really a problem, a clear acrylic conformal coating
is about all you can do.
Brian
Safavi-Bayat Shahed wrote:
>
> Hi everyone,
> We recently had a board fabricated with silver finish.
> After it came back from assembly house the exposed silver finish is been
> tarnish(color changed to brown)during assembly.
> Does any one here has seen this before? The assembly done manually and the
> tarnishing
> happened after they washed the board.
> I appreciate any comment on this.
>
> Thank You
>
> Shahed
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Wed, 23 Jan 2002 08:30:29 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank L Norman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank L Norman <[log in to unmask]>
Subject: Re: Tarnished Surface
X-To: Safavi-Bayat Shahed <[log in to unmask]>
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It sounds like the damage was done during the washing process. If so you
may have an issue with your D.I. water quality, i.e. mix bed may be
exhausted...
Frank Norman
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Date: Wed, 23 Jan 2002 13:59:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
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From: Phil Nutting <[log in to unmask]>
Subject: Off Topic - Hershey's Kisses [Evaluation - see full header]
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A week or two ago the name for the Hershey's Kiss was explained in this =
forum as the appearance the machine was "kissing" the conveyor belt to =
generate each candy. Well, times have changes. I just finished the =
last two Kisses from my bag of "Christmas Kisses" and noticed that the =
candies no longer have that curved bottom edge of the past. It looks =
like with the advent of the Hershey's "Hugs" that they went to a molding =
process rather than the "squirting" process. Sigh! Some things sadly =
change with time.
Phil Nutting
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Date: Wed, 23 Jan 2002 08:51:50 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
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From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: IPC-4101/23 vs /24 [Evaluation - see full header]
X-To: Mark Hargreaves <[log in to unmask]>
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I'm not an expert on this either but looking at the spec sheets for the two
different materials, I'd say you'd have to prove that the /24 will comply
with the requirements for /23. There are a number of differences between the
two. Just looking at the descriptions:
(This is supposed to be a table with columns separated by "|")
/23 | /24
Epoxy | Majority Epoxy
FR5 | FR4
Hot Strength Retention | N/A
Tg 135-175 | Tg 150-200
You can find more comments about the difference between FR4 and FR5 in the
Technet Archives. Fr-5 is typically used in applications with high
operating temperatures.
In addition to the different descriptions, the laminate requirements table
shows that /23 has higher requirements for peel strength, volume and surface
resistivity, dielectric breakdown and arc-resistance.
Perhaps with some of the improvements in FR4 materials, they now comply with
the higher standards for /23, but you or your material supplier would have
to prove that.
> ----------
> From: Mark Hargreaves[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Mark Hargreaves
> Sent: Friday, January 18, 2002 8:24 AM
> To: [log in to unmask]
> Subject: [TN] IPC-4101/23 vs /24
>
> Hi All,
> Does type GF/GFG material (IPC-4101 / 24) meet the requirements of type GH
> material (IPC-4101 / 23) ?
>
> Our customer is requesting type GH. We stock type GF/GFG and would like
> to
> use it instead.
>
> (I hope I've phrased this properly. 4101 is a little over my head)
>
> Many Thanks,
> Mark Hargreaves
>
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>
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Date: Wed, 23 Jan 2002 15:47:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Blomberg, Rainer (FL51)" <[log in to unmask]>
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From: "Blomberg, Rainer (FL51)" <[log in to unmask]>
Subject: Re: Baking of Assemblies?
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We use a semi-aqueous process with final water rinse followed by IPA spray
and then bake 30 minutes at 150 deg. F. Later, we dry out further with 6 hr
vac bake at 200 deg. F prior to conformal coating all our polyamide boards.
Rainer G. Blomberg
Honeywell -Space Systems Clearwater
Staff Production Engineer
13350 US Hwy 19 N MS 802-3
Clearwater, FL 33764-7290
(727) 539-5534 Phone
(727) 790-8738 Pager
(727) 539-4469 Fax
e-mail: [log in to unmask]
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, January 18, 2002 4:04 PM
To: [log in to unmask]
Subject: [TN] Baking of Assemblies?
This should be good fodder! We wash PWAs in a water hurricane type machine,
with
a hot air blower at the end of cycle. We noticed some components mainly
elect.
alum. capacitors have high capacitance. After research on cap. we were
instructed to bake assemblies 20 mins @ 100c to dry them. The long term
effect
of the moisture in the cap would cause electrical leakage then failure due
to
corrosion.
Well this idea expanded into a question should we bake all assemblies
because
many other items such as transformers, pots., coils are not hermetically
sealed.
And then there is the issue with pwb material its self.
My question to the forum is, Does anyone bake after wash as a standard? All
points of view are welcome.
Thanks!
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Date: Wed, 23 Jan 2002 15:35:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Keach Sasamori <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: OT-Test posting to Listserv
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This is a test to various lists on the new Listserv. We have moved the =
Listserv to a new blazing fast Windows 2000 system with lots of RAM.
You may want to clear your internet cache to clear any old setting =
pointing to the old server. The archives were not available earlier today =
but should be operational now.
Thank you
______________
Keach Sasamori
IS Administrator
IPC
2215 Sanders Rd.
Northbrook, IL 60062
Ph: (847) 790-5315=20
Fax: (847) 504-2315
e-mail: [log in to unmask]
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Date: Wed, 23 Jan 2002 13:59:21 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Solder Analysis
X-To: Mike Manwell <[log in to unmask]>
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Content-Type: text/plain; charset="iso-8859-1"
Hi Mike:
What is it that you are looking for? Are you looking for an independent lab
to cross check analysis? Is it that you don't care for Alpha for some
reason? Do you want someone locally, faster turn times, etc?
There are some good independent labs locally that can supply you with a full
analysis, Sn/Pb and trace metals. However, you are going to have to pay
whereas if you go with your solder supplier they normally offer this free,
typically once a month.
Let me know if you need the names of qualified labs in the Greater Seattle
area.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Mike Manwell [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 1:55 PM
To: [log in to unmask]
Subject: [TN] Solder Analysis
Hello folks,
Im looking for a facility that does solder sample analysis.
Im aware of Alpha Analytical Laboratories but before signing up, cant help
but wonder if there are others out there.
Any suggestions?
Thanks,
Mike Manwell
Integrex Inc.
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Date: Wed, 23 Jan 2002 17:03:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: BGA/Vias
X-To: Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
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There could possibly be an interaction with the via pattern under the BGA.
The dense drilled hole grid perforates the glass reinforcement matrix and
reduces the mechanical integrity of that section of the board. You can
actually see a localized increase in the CTE of the material because of the
loss of reinforcement.
> ----------
> From: Guy Ramsey[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Guy Ramsey
> Sent: Wednesday, January 16, 2002 1:42 PM
> To: [log in to unmask]
> Subject: Re: [TN] BGA/Vias
>
> No, I understood you. Some boards will do this. Sometimes they crown
> instead
> of sag. I have not studied why. But increasing the size of the area
> subject
> to preheat may help. In a worst case scenario you may have to reflow the
> entire board in an oven.
>
> Sometimes, as the MoonMan mentions, the BGAs like to curl up on the
> corners
> or down on the corners as well. This is do to CTE mismatches in the
> package
> itself. Then you just have to slow the process down and use as low a
> topside
> heat as you can.
>
> An old axiom worth remembering, when in doubt go low and slow. I give
> credit
> to an old mentor, Ken Lindsey, for this rule. Hope he is doing well.
>
> Guy Ramsey
>
>
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
> > Sent: Wednesday, January 16, 2002 2:41 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] BGA/Vias
> >
> >
> > I probably didn't make myself clear. The problem is the board itself
> > collapses/sinks/"potato chips"...in the area being heated, i.e. BGA
> > location.
> > Rick
> >
> >
>
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Date: Wed, 23 Jan 2002 22:35:04 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: Earl Moon <[log in to unmask]>
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Earl,
It's worse than just using the test equipment guidelines. Along with that,
you have to deal with each of the test fixture makers' preferences as well.
What this boils down to is a negotiation with each CM's test engineering
group as to what is testable. They are not even slightly embarrassed asking
for 100% bottom side only coverage with 0.040" square test pads on 0.100"
centers (on a grid, of course) for a board with 6/6 mil line/space, 8/18 mil
via hole/pad and 0.8mm BGA's. I guess it's a good bargaining tactic, but
I'd like to think we're at least on the same team. Those are the same ICT
rules we were using fifteen years ago. But typical PCB design rules have
shrunk considerably during that time.
Lately, I've had reasonable luck arguing for the first two of the three
following design rules (all test pads are round):
nail size test pad dia. center-to-center
--------- ------------- ----------------
0.100" 0.035" 0.085"
0.075" 0.035" 0.057"
0.050" 0.025" 0.044"
To get the third rule, which is the one you really need on a high-density
board, be prepared for battle. From what I'm told, the problem is that the
50 mil test nails are fragile, and for the closer center-to-center spacings,
they can't be socketed. So when they wear out or bend, the test engineer
has to carefully replace a press-fit test nail. My basic response to this
serious problem is "So what", but NEVER SAY THIS or you will be testing the
boards yourself!
There is also the approximately 0.200" border required for the vacuum test
fixture seal. One shop I work with has mostly changed from vacuum fixtures
to over-clamped fixtures. It avoids the problems with leaky gaskets and
vias and gives the border space back to the PCB. The fixture does cost a
bit more but it is a minimal one-time cost. Most CM's I have worked with do
prefer the vacuum fixtures, so I assume there is a throughput difference,
but I don't know.
Are there any test engineers out there who can comment on whether the above
ICT design rules are typical for fixture fabricators today? Are the smaller
test nails and pads really that much more expensive and troublesome?
Sometimes I can allocate more board area for testing. However, in many
cases, increasing board area is not an option so we either give up test
coverage, rework the circuit to reduce components or use clamshell fixtures.
In these cases, I usually feel the trade off was not cost effective, but as
the circuit designer, I don't have all the information.
I didn't really mean to rant, but it's all over now.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
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Date: Wed, 23 Jan 2002 23:15:34 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: VME stuff again...
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Hi Steve,
I don't have the VITA VME standard, but I have IEEE 1101.1-1998, "IEEE
Standard for Mechanical Core Specifications for Microcomputers Using IEC
60603-2 Connectors", upon which the VME standards are based. There are a
couple of references to thicker boards in here. The bottom line is pretty
much what Peter said: you can have a thicker board, but you have to mill it
down for the card guides. However, since everything is dimensioned from the
center of an 0.063" board, the board can get thicker in the direction of the
bottom side without disturbing the connector locations. This is true as
long as you reduce the thickness from the bottom side back to the reference
0.063" at the card guides. In this case, you can have the full thickness
board under the connectors. This is explained in the notes to figure 15 of
this standard on page 26.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
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Date: Thu, 24 Jan 2002 00:53:01 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
MIME-Version: 1.0
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Hi MoonCaveMan,
Try IPC-9701published January 2002.
Werner
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Date: Thu, 24 Jan 2002 06:05:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA/Vias
X-To: [log in to unmask]
Michael,
Can I "assume" delamination/blistering can be effected by this condition?
I'm seeing some in/under some .8 mm CSP'S.
Earl Moon
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Date: Thu, 24 Jan 2002 06:11:19 -0600
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Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: [log in to unmask]
Seth,
Absolutely great stuff. I've been down this road too many times with
designers, and good ones at that, and share their frustration over what you
have said. I sure agree, we have to get on the same page at some point
though, as you say, the ICT folks have to start the discussion somewhere.
I hope Werner's suggestion about the new IPC 7091 provides some
standardization guidelines for all industry participants. I'm ordering it
today provided I can find it in the catalogue.
Earl
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Date: Thu, 24 Jan 2002 06:26:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: VERY INTERESTING, TO ME, BGA/CSP STUFF
Folks,
First a finding of interest to be sharred (one or two r's, never get this
right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
clue how to spell that). Witnessed the strangest electronic packaging thing
ever in my young and tender life the other day.
A small, but very much on the rise non-manufacturing oriented telecom
company (how about that for irony in these times), with whom I'm currently
consulting, demonstrated a new way to assure circuit continuity. Boards are
suspect and assemblies don't seem much better (why I'm here). Finger
pressure on BGA device top and electrons flow and circuit "works." Finger
gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
work. Electrons flow. Just thought few of you could top this story.
I do love this work so.
This brings to mind another request. I have associations with several good
fab shops. Hope Glynn Shaw is looking in and would like to build some quick
turn 12 layer boards. Don't know a single good PCBA capability wanting to
do protos and medium volume production assemblies with .8 csp's and a
couple of FPGA's as one a perimeter and another a full array metal top
variety (you all know the ones. If anyone knows of this type assembler, in
the northern Ohio area, please let me know. I am a born again "HARD"
supplier qualifier, however.
Earl Moon ---- and don't leave home without your c clamps and a little wood
for top and bottom insulators. I think balsa is best. Maybe IPC has this
covered.
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Date: Thu, 24 Jan 2002 06:35:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: [log in to unmask]
Thanks Werner,
I am having the folks here order 9791, or is it 9701 or 7091, just kidding,
this morning. From where do these numbers come and from who? You have
something to do with this pub, Werner?
MoonCaveMan on a warm spring day in Ohio? Ohio? Ohio? It's a job after all
and nice folks too.
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Date: Thu, 24 Jan 2002 08:04:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: J-STD-001 AND IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good day Technet.
Once again, we're considering changing from military workmanship
specifications (MIL-STD-2000) to industry standards (IPC). The question:
Do both 001 and 610 need to be referenced in our quality manuals and on our
drawings? Could either be stand-alone? If acceptability requirements are
in 001, why have 610?
Thanks for your continued help,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 24 Jan 2002 07:40:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McFaddin, Wade" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McFaddin, Wade" <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
Hey Earl,
Loved your C-clamp story! I knew there had to be a good reason to keep all
that hardware in the tool box. As far as you looking for someone to build
your 12-layer boards with .8 CSPs in proto and medium volume, that sounds
like it's right up our alley. Give me a call and I can put you in touch
with someone that can talk nuts and bolts (not c-clamps) it you want, or
check out our webpage at http://www.nextekinc.com/.
Thanks,
Wade McFaddin
Nextek Inc.
(256) 772-1995 ext. 1064
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, January 24, 2002 6:26 AM
> To: [log in to unmask]
> Subject: [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Folks,
>
> First a finding of interest to be sharred (one or two r's, never get this
> right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
> clue how to spell that). Witnessed the strangest electronic packaging
> thing
> ever in my young and tender life the other day.
>
> A small, but very much on the rise non-manufacturing oriented telecom
> company (how about that for irony in these times), with whom I'm currently
> consulting, demonstrated a new way to assure circuit continuity. Boards
> are
> suspect and assemblies don't seem much better (why I'm here). Finger
> pressure on BGA device top and electrons flow and circuit "works." Finger
> gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
> work. Electrons flow. Just thought few of you could top this story.
>
> I do love this work so.
>
> This brings to mind another request. I have associations with several good
> fab shops. Hope Glynn Shaw is looking in and would like to build some
> quick
> turn 12 layer boards. Don't know a single good PCBA capability wanting to
> do protos and medium volume production assemblies with .8 csp's and a
> couple of FPGA's as one a perimeter and another a full array metal top
> variety (you all know the ones. If anyone knows of this type assembler, in
> the northern Ohio area, please let me know. I am a born again "HARD"
> supplier qualifier, however.
>
> Earl Moon ---- and don't leave home without your c clamps and a little
> wood
> for top and bottom insulators. I think balsa is best. Maybe IPC has this
> covered.
>
> --------------------------------------------------------------------------
> -------
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> additional
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> --------------------------------------------------------------------------
> -------
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Date: Thu, 24 Jan 2002 14:31:15 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rajkumar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rajkumar <[log in to unmask]>
Subject: Electronic Manufacturing Conference in New Zealand
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_007A_01C1A4E3.C776AEE0"
This is a multi-part message in MIME format.
------=_NextPart_000_007A_01C1A4E3.C776AEE0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hello
As anyone has any information (e.g. website) about electronic =
manufacturing conference in New Zealand?
THanx
Rajkumar Durairaj
Electronics Manufacturing Engineering Research Group
School of Aeronautical, Civil and Mechanical Engineering
University of Salford
http://www.acme.salford.ac.uk/emerg
Salford, UK, M5 4WT
Tel: +44-161-2954696
Fax: +44-161-2955575/5060
------=_NextPart_000_007A_01C1A4E3.C776AEE0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hello</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>As anyone has any information (e.g.=20
website) about electronic manufacturing conference in New=20
Zealand?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>THanx</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Rajkumar Durairaj<BR>Electronics =
Manufacturing=20
Engineering Research Group<BR>School of Aeronautical, Civil and =
Mechanical=20
Engineering<BR>University of Salford<BR><A=20
href=3D"http://www.acme.salford.ac.uk/emerg">http://www.acme.salford.ac.u=
k/emerg</A><BR>Salford,=20
UK, M5 4WT<BR>Tel: +44-161-2954696<BR>Fax: =
+44-161-2955575/5060</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV></BODY></HTML>
------=_NextPart_000_007A_01C1A4E3.C776AEE0--
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Date: Thu, 24 Jan 2002 10:29:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Eubank <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Eubank <[log in to unmask]>
Subject: center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.
Thanks
Matt
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Date: Thu, 24 Jan 2002 11:23:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Masking for Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello again...
Looking for suggestions for removing masking material (tape or liquid) which
is applied to mask areas from conformal coating. The way we do it now, the
operator masks off the area (usually tape), sprays the board, cures the
coating, scores the coating around the tape, then removes the tape. We're
trying to eliminate the scoring of the coating since this has potential of
cutting through traces. Removal of the coating prior to curing doesn't work
because the coating runs during the heat cure process. I'm trying to avoid
room temperature cure since this is very time consuming. Ant suggestions?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 24 Jan 2002 16:37:44 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Braime, Justin" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Braime, Justin" <[log in to unmask]>
Subject: Re: Electronic Manufacturing Conference in New Zealand
X-To: Rajkumar <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Hi Rajkumar,
Electronics manufacturing conferences in New Zealand are sometimes organised
by the SMCBA (Surface Mount & Circuit Board Association), which is the
Australasian equivalent of IPC / SMART Group / etc. The SMCBA office is
based in the state of Victoria, Australia. Website is at:
http://www.smcba.asn.au/
J.
> -----Original Message-----
> From: Rajkumar [SMTP:[log in to unmask]]
> Sent: 24 January 2002 14:31
> To: [log in to unmask]
> Subject: [TN] Electronic Manufacturing Conference in New Zealand
>
> Hello
>
> As anyone has any information (e.g. website) about electronic
> manufacturing conference in New Zealand?
>
> THanx
>
> Rajkumar Durairaj
> Electronics Manufacturing Engineering Research Group
> School of Aeronautical, Civil and Mechanical Engineering
> University of Salford
> <http://www.acme.salford.ac.uk/emerg>
> Salford, UK, M5 4WT
> Tel: +44-161-2954696
> Fax: +44-161-2955575/5060
>
>
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Date: Thu, 24 Jan 2002 11:09:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Can't find any neat and tidy formula off the top of my head, but some basic
geometry and trig should handle it. A right triangle always fits in a
semi-circle. You know the diameter (this is your hypotenuse), you can find
the distance between the two arc points in a straight line. This gives you
two sides of the triangle, and one angle (right angle). You can find every
other piece of information about the triangle with this knowledge. Then you
just have to find the coordinates of the midpoint of your hypotenuse to know
the center of your circle.
You might find some helpful info here if you've forgotten you're trig
definitions.
http://www.math2.org/index.xml
-----Original Message-----
From: Matt Eubank [mailto:[log in to unmask]]
Sent: January 24, 2002 9:30 AM
To: [log in to unmask]
Subject: [TN] center of a arc
Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.
Thanks
Matt
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Date: Thu, 24 Jan 2002 09:11:18 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
peter lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Noclean process chemistry loss
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Hello,
We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.
So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.
My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Thu, 24 Jan 2002 11:25:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: OK Industries BGA-3000 Rework Unit
Folks,
Anyone have experience or anything to say, one way or another, about OK
Industries BGA-3000 Rework Unit. I have experience on SRT, AirVac, and
Conceptronic equiptment only.
Thanks,
MoonMan
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Date: Thu, 24 Jan 2002 11:37:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
Wade, and all off-line repliers, thanks for the input. Before I go outside
driving distance from the Akron/Cleveland area, I will continue searching
there. Alabama is nice this time of year though what with all the balmy
weather. Not too far either.
Earl
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Date: Thu, 24 Jan 2002 10:44:52 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
MIME-version: 1.0
Content-type: text/plain; charset=Windows-1252
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I saw something similar early in my career, the design engineer was showing
the boss how a circuit worked when he put his finger "just here". Boss said
that was great we could ship at least 10 units. I don't think he
was called back on the floor til there was a solution.
Dan
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Date: Thu, 24 Jan 2002 13:58:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Julien Bouchard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Julien Bouchard <[log in to unmask]>
Subject: Re: BGA rework
X-To: Don Anderson <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Hi,
Here we allow to change a BGA to a maximum of three times. But I don't
think it's based on any standards or spec. It's just a number time that give
us good balance between the board integrity and the cost of rework.
Julien Bouchard
Matrox Electronis Systems
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Don Anderson
Sent: 16-Jan-02 13:51
To: [log in to unmask]
Subject: [TN] BGA rework
TechNetters,
I am sure there has been some discussion on this subject in the past, but I
need to ask a fairly simple question (I hope). Is there a limit to the
number of times BGA packages can be attached to and removed from a BGA
before the integrity of the board is compromised? Is it in a spec
someplace?
Thanks in advance
Don Anderson
Compunetics, Inc.
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Date: Fri, 25 Jan 2002 08:02:19 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Michael Bell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Re: center of a arc
X-To: Matt Eubank <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
To find the centre all you have to do is draw two lines crossing two sides
of the circle, not to close to the centre (the closer to the edge of the
circle is best), and then bisect them with a protractor. The two bisecting
lines will then cross each other at the centre.
Cheers
-----Original Message-----
From: Matt Eubank [mailto:[log in to unmask]]
Sent: Friday, 25 January 2002 04:30
To: [log in to unmask]
Subject: [TN] center of a arc
Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.
Thanks
Matt
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Date: Fri, 25 Jan 2002 08:05:13 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Michael Bell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Re: Masking for Conformal Coating
X-To: "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
James,
Have you considered using a laser cut or milled steel/aluminium hat that
sits ontop of the PCB. Any clearance for components can be milled out from
the underside, and the weight of it forms a good enough seal around the
bottom. We used this idea ffor a long time for PCB's that were panelized.
The hats were made into a large spider web style with hats adjointing to it.
You simply dropped it over the respective components and in one go, we
masked about 30 components/connectors etc.
Cheers
Mike
-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, 25 January 2002 05:24
To: [log in to unmask]
Subject: [TN] Masking for Conformal Coating
Hello again...
Looking for suggestions for removing masking material (tape or liquid) which
is applied to mask areas from conformal coating. The way we do it now, the
operator masks off the area (usually tape), sprays the board, cures the
coating, scores the coating around the tape, then removes the tape. We're
trying to eliminate the scoring of the coating since this has potential of
cutting through traces. Removal of the coating prior to curing doesn't work
because the coating runs during the heat cure process. I'm trying to avoid
room temperature cure since this is very time consuming. Ant suggestions?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 24 Jan 2002 19:21:52 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Noclean process chemistry loss
X-To: peter lee <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Peter,
Kyzen and I have fought that battle in the past on an old Tooltronics
UltraClean II and a Triton with Aquanox XJN. We went from making a gallon
add daily to four gallons/day before we solved it. (20 gallons was a
complete charge of the system.) Kyzen was very responsive and their
regional tech rep. showed up to help within days.
We did the same stuff you've done in your trouble shooting - blocked the
overflow drain & killed the auto refill (that was murder in the beginning).
We also checked for any solution overflow into down stream chambers - look
for scum rings on the tank walls. We also checked for evaporation and
considered buying a vapor recovery system but it turns out we didn't need
it. When the wash sump is idle the chemistry losses due to evaporation are
very low - the stuff's heavier than water and sinks to the sump's bottom.
You do lose water though. We were running at 130 F and 30 psi.
In the UltraClean II case, the operators were manually overfilling the wash
sump with water and then making the chemistry add. Pure Chemistry was
overflowing into the isolation chamber and going straight to Drain. They
were also placing product on the conveyor very close together that
drastically increase solution dragout. We had to retrain everybody to
follow the procedures and show them what was happening to make it stick.
In the Triton case, the rinse drain & overfill were scaled shut (from the
previous chemistry) and the rinse water cascaded back into the wash sump,
overfilling and draining. We had to replace the drain & overflow piping in
the Rinse Sections - way too much buildup to descale.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: peter lee [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 12:11 PM
To: [log in to unmask]
Subject: [TN] Noclean process chemistry loss
Hello,
We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.
So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.
My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Thu, 24 Jan 2002 11:30:34 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: center of a arc
X-To: Matt Eubank <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Assuming the two points on the arc are the endpoints, construct a line
between the two points. Find the midpoint of that line. A line drawn
through the midpoint and the center of the circle will pass through the
center of the arc at the radius of the circle.
> ----------
> From: Matt Eubank[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Matt Eubank
> Sent: Thursday, January 24, 2002 7:29 AM
> To: [log in to unmask]
> Subject: [TN] center of a arc
>
> Need some help.
> What is the equation for finding the center of a arc given the radius and
> 2
> points on the arc.
>
> Thanks
> Matt
>
> --------------------------------------------------------------------------
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Date: Thu, 24 Jan 2002 13:23:02 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Re: OK Industries BGA-3000 Rework Unit
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
MoonMan,
We are using a Ok-3500 and are pretty well pleased with it. How ever you
would best be able to make a decision by having the rep. bring one in and
demonstrating the machine. Look at things like your board size coupled with
edge connectors and the like.
Barry.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 10:26 AM
To: [log in to unmask]
Subject: [TN] OK Industries BGA-3000 Rework Unit
Folks,
Anyone have experience or anything to say, one way or another, about OK
Industries BGA-3000 Rework Unit. I have experience on SRT, AirVac, and
Conceptronic equiptment only.
Thanks,
MoonMan
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Date: Thu, 24 Jan 2002 14:45:05 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Earl,
Thanks for the encouragement. I received one off-line note from someone who
uses the same design rules I gave. However a sample of two is pretty sparse
data. Would other folks be willing to share the design rules they use for
ICT? If you're not comfortable replying on-line due to company
confidentiality or any other reason, I will keep off-line responses
confidential and just summarize the design rules that people used. I'd
really like to hear from some test engineers to learn why things are the way
they are and figure out how to better dovetail your requirements and
restrictions with those of designers.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
> Sent: Thursday, January 24, 2002 6:11 AM
> To: [log in to unmask]
> Subject: Re: [TN] ASSEMBLED BOARD IPC TEST REQUIREMENTS
>
>
> Seth,
>
> Absolutely great stuff. I've been down this road too many times with
> designers, and good ones at that, and share their frustration
> over what you
> have said. I sure agree, we have to get on the same page at some point
> though, as you say, the ICT folks have to start the discussion somewhere.
>
> I hope Werner's suggestion about the new IPC 7091 provides some
> standardization guidelines for all industry participants. I'm ordering it
> today provided I can find it in the catalogue.
>
> Earl
>
> ------------------------------------------------------------------
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Date: Thu, 24 Jan 2002 16:00:21 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Lead replacement solder alloys
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_17.221b13aa.2981cfe5_boundary"
--part1_17.221b13aa.2981cfe5_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Who is the procurement source for a couple of the newer Sn 63 like solders
that have somewhat better properties than Sn63. Specifically they are the
SnAgCuSb and SnAgCuZn alloys.
Thanks
Phil Hinton
--part1_17.221b13aa.2981cfe5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Who is the procurement source for a couple of the newer Sn 63 like solders that have somewhat better properties than Sn63. Specifically they are the SnAgCuSb and SnAgCuZn alloys.
<BR>
<BR>Thanks
<BR>Phil Hinton </FONT></HTML>
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Date: Thu, 24 Jan 2002 16:16:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
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Hi MoonCaveMan,
Missed you at APEX, together with alot of other folks. "9/11&economy" have a
gruesome impact.
The IPC document numbers came from Dieter--I think; I, among others in the
TAEC protested the change from numbers like IPC-SM-785 [Surface Mount],
IPC-MF-150 [Metal Foil], IPC-D-279 [Design] to such non-descript entiies as
IPC-7901, IPC-2222, etc., but as you can see to no avail.
Among all of the IPC documents, my exhaustive search found no standards on
either balsa wood orC-clamps. Now, if you would make the C-clamps out of
copper, you would have a nice heat sink. Would you want to chair a committee
on this subject?
Seriously, though, your "small, but very much on the rise non-manufacturing
oriented telecom
company" will not be rising much farther, if they assemble BGAs/PWAs this
way. I do not think you reallllly need any help with this.
Can I top this story? Would this qualify? At Bell Labs--the former vibrant
Bell Labs, not the current empty shell--one guy tried to pattent the idea of
putting a screw in the center of the package and fasteninng it to the PCB
through a hole with a nut.
Werner
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Date: Thu, 24 Jan 2002 16:20:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Masking for Conformal Coating
X-To: Michael Bell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Thanks Mike, this sounds like a good idea. One question though, when do you
remove the mask, before or after cure? If before, doesn't the coating run
when heated? If after, how do you separate the tool from the coating? (OK,
three questions)
Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Michael Bell [SMTP:[log in to unmask]]
Sent: Thursday, January 24, 2002 2:05 PM
To: [log in to unmask]
Subject: Re: [TN] Masking for Conformal Coating
James,
Have you considered using a laser cut or milled steel/aluminium hat
that
sits ontop of the PCB. Any clearance for components can be milled
out from
the underside, and the weight of it forms a good enough seal around
the
bottom. We used this idea ffor a long time for PCB's that were
panelized.
The hats were made into a large spider web style with hats
adjointing to it.
You simply dropped it over the respective components and in one go,
we
masked about 30 components/connectors etc.
Cheers
Mike
-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, 25 January 2002 05:24
To: [log in to unmask]
Subject: [TN] Masking for Conformal Coating
Hello again...
Looking for suggestions for removing masking material (tape or
liquid) which
is applied to mask areas from conformal coating. The way we do it
now, the
operator masks off the area (usually tape), sprays the board, cures
the
coating, scores the coating around the tape, then removes the tape.
We're
trying to eliminate the scoring of the coating since this has
potential of
cutting through traces. Removal of the coating prior to curing
doesn't work
because the coating runs during the heat cure process. I'm trying
to avoid
room temperature cure since this is very time consuming. Ant
suggestions?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 24 Jan 2002 16:35:21 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: Noclean process chemistry loss
X-To: peter lee <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Hi Peter, I would check the venting system and how much draw you are getting
to pull off the fumes. With the wash tank at 135F and with a good venting
system it's not improbable to draw the material out of the wash tank. The
other item I would look at would be the drag out by the product as it is
going through the system.
Not knowing the product configuration, lots of connectors could be a cause
of this lost.
Good Luck
Leo Lambert
EPTAC Corp.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of peter lee
Sent: Thursday, January 24, 2002 12:11 PM
To: [log in to unmask]
Subject: [TN] Noclean process chemistry loss
Hello,
We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.
So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.
My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Thu, 24 Jan 2002 16:44:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: solder waste from hand solder/de-solder
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi all,
With the TRI program from the EPA and other factors it comes to mind =
that we have more than dross from the wave solder system or solder pot. =
We have solder from solder suckers and de-soldering systems, soiled =
solder sponges and (should I add) component lead trimmings that =
presently don't make it into a dross bucket. What are you folks using =
for a system (procedure, policy) regarding these wastes containing lead?
Thanks in advance,
Phil Nutting
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Date: Thu, 24 Jan 2002 20:20:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: solder waste from hand solder/de-solder
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_ce.207540dd.29820cf0_boundary"
--part1_ce.207540dd.29820cf0_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Phil!
You bring up some very good points that show what a nightmare this is going
to be!!
We recycle all our dross, but along with the items that you mention, what
about almost empty solder paste jars and tubes, used stencil cleaning rolls
from the screen cleaning systems in the printers nowdays, the wipes that are
used to clean spatulas after depositing paste onto the stencils?
We put these items into a special container for hazardous waste and dispose
of that properly. But we really don't have any real idea of how much lead is
contained within that waste...
I suppose one could do some math caculations that would yield some sort of
figure, but is that real?
Just shows how full of holes this legislation is....and as somebody
brought-up in the past, are the hunting enthusiasts that do their own
reloading going to have to report? How about the fishing nut that make his
own sinkers? It would be easy for anyone of these guys to go through 100-lbs.
of lead in a year...
-Steve Gregory-
> Hi all,
>
> With the TRI program from the EPA and other factors it comes to mind that
> we have more than dross from the wave solder system or solder pot. We have
> solder from solder suckers and de-soldering systems, soiled solder sponges
> and (should I add) component lead trimmings that presently don't make it
> into a dross bucket. What are you folks using for a system (procedure,
> policy) regarding these wastes containing lead?
>
> Thanks in advance,
>
> Phil Nutting
>
--part1_ce.207540dd.29820cf0_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Phil!<BR>
<BR>
You bring up some very good points that show what a nightmare this is going to be!!<BR>
<BR>
We recycle all our dross, but along with the items that you mention, what about almost empty solder paste jars and tubes, used stencil cleaning rolls from the screen cleaning systems in the printers nowdays, the wipes that are used to clean spatulas after depositing paste onto the stencils?<BR>
<BR>
We put these items into a special container for hazardous waste and dispose of that properly. But we really don't have any real idea of how much lead is contained within that waste...<BR>
<BR>
I suppose one could do some math caculations that would yield some sort of figure, but is that real?<BR>
<BR>
Just shows how full of holes this legislation is....and as somebody brought-up in the past, are the hunting enthusiasts that do their own reloading going to have to report? How about the fishing nut that make his own sinkers? It would be easy for anyone of these guys to go through 100-lbs. of lead in a year...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,<BR>
<BR>
With the TRI program from the EPA and other factors it comes to mind that we have more than dross from the wave solder system or solder pot. We have solder from solder suckers and de-soldering systems, soiled solder sponges and (should I add) component lead trimmings that presently don't make it into a dross bucket. What are you folks using for a system (procedure, policy) regarding these wastes containing lead?<BR>
<BR>
Thanks in advance,<BR>
<BR>
Phil Nutting<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_ce.207540dd.29820cf0_boundary--
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Date: Thu, 24 Jan 2002 19:41:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Lefebvre, Scott" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lefebvre, Scott" <[log in to unmask]>
Subject: Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
I recently read an article concerning board finishes. One of the finishes specified was Electroplated Tin/Lead. I have not heard of this process before, I'm only familiar with Electroplated Tin. What I read is that it is vary flat and works well with Fine Pitch and BGA components.
Does any one out their have any information they could share concerning this issue. What are the pros and cons of this board finish.
Scott Lefebvre
Mfg. Engineer
ADC
530-265-1041
[log in to unmask] <[log in to unmask]>
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Date: Thu, 24 Jan 2002 18:22:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank L Norman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank L Norman <[log in to unmask]>
Subject: Water soluble solder mask
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi all,
Looking for insight about using water soluble solder mask.
We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.
Frank Norman
Raytheon
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Date: Thu, 24 Jan 2002 21:44:44 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Water soluble solder mask
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_162.7aa806a.2982209c_boundary"
--part1_162.7aa806a.2982209c_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Frank!
Question: Are you closed-loop with your water?
-Steve Gregory-
> Hi all,
>
> Looking for insight about using water soluble solder mask.
>
> We are currently using a latex solder mask made by Litton. But now the
> question as been asked if water soluble mask could be used instead. Note,
> batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
> Frank Norman
> Raytheon
>
--part1_162.7aa806a.2982209c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Frank!<BR>
<BR>
Question: Are you closed-loop with your water?<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,<BR>
<BR>
Looking for insight about using water soluble solder mask.<BR>
<BR>
We are currently using a latex solder mask made by Litton. But now the<BR>
question as been asked if water soluble mask could be used instead. Note,<BR>
batch washer(Aqueous Tech. Washer) is used to clean PWAs.<BR>
<BR>
Frank Norman<BR>
Raytheon<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_162.7aa806a.2982209c_boundary--
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Date: Thu, 24 Jan 2002 22:38:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Electroplated Tin/Lead
MIME-Version: 1.0
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Lemme butt in with some theoretical stuff, that I have seen evidence of.
The subject is galvanic corrosion, or what happens when you have two metals
(like Tin and Lead) electrically in contact with each other, and with the
corrosive material.
When this is the case, the more readily attacked of the two metals (in this
case Tin) is MUCH more readily attacked, while the less readily attacked
metal is protected. This is why galvanized pails do not rust as easily as a
bare steel pail would, that is why you "galvanize."
However, in this case, you are trying to protect the entire exposed surface,
both Tin and Lead, and keep the surface solderable. So, this is not such a
good idea, as the presence of the Lead should/would accelerate attack on the
Tin. Or, what I am suggesting is that by this theory, Tin/Lead should be
LESS protective than pure Tin.
(All of the above advice goes out the window if you fuse or "reflow" the
Tin/Lead deposit, in which case the plated metals form a true alloy, instead
of discrete crystals of Tin and crystals of Lead, and thus act like a single
metal.)
Remember, free advice is often not worth what you paid for it....:-)
Rudy Sedlak
RD Chemical Company
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Date: Fri, 25 Jan 2002 08:40:44 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
MIME-Version: 1.0
Content-Type: text/plain
Hi,
Sounds like you have cracked joints on your bga.s.
This can happen if you reflow the bga side then wave solder the bottom side.
Try a board with thermocouples under the bga when it goes over the wave, you
will probably frighten yourself. The formally good bga joints can reach 180
to 200 Celsius which is enough to disturb the joints as the board flexes
with heat, but not enough to reflow them back into a consolidated joint.
If this is the case, go double sided reflow.
If it isn't, check your reflow conditions.
You cannot see these cracks with a standard transmission X ray equipment
because they are very narrow, which is why slight finger pressure will cause
the component to start working again.
It had me going when I first saw it, I thought it was an aerial effect.
Hope this helps
Regards
Eric Dawson
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, January 24, 2002 12:26 PM
> To: [log in to unmask]
> Subject: [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Folks,
>
> First a finding of interest to be sharred (one or two r's, never get this
> right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
> clue how to spell that). Witnessed the strangest electronic packaging
> thing
> ever in my young and tender life the other day.
>
> A small, but very much on the rise non-manufacturing oriented telecom
> company (how about that for irony in these times), with whom I'm currently
> consulting, demonstrated a new way to assure circuit continuity. Boards
> are
> suspect and assemblies don't seem much better (why I'm here). Finger
> pressure on BGA device top and electrons flow and circuit "works." Finger
> gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
> work. Electrons flow. Just thought few of you could top this story.
>
> I do love this work so.
>
> This brings to mind another request. I have associations with several good
> fab shops. Hope Glynn Shaw is looking in and would like to build some
> quick
> turn 12 layer boards. Don't know a single good PCBA capability wanting to
> do protos and medium volume production assemblies with .8 csp's and a
> couple of FPGA's as one a perimeter and another a full array metal top
> variety (you all know the ones. If anyone knows of this type assembler, in
> the northern Ohio area, please let me know. I am a born again "HARD"
> supplier qualifier, however.
>
> Earl Moon ---- and don't leave home without your c clamps and a little
> wood
> for top and bottom insulators. I think balsa is best. Maybe IPC has this
> covered.
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date: Fri, 25 Jan 2002 09:19:51 -0000
Reply-To: Dougal Stewart <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Well it's a strange thing how what goes around, comes around. Electroplated
tin lead was (and still is in some companies) the subsequent process step to
electroplate copper, and acts as the etch resist through ammoniacal etchant.
Before the days of HASL, this was then reflowed, and the surface finish of
fused tin lead was commonplace, so much so that all the accelerated ageing
tests were based on fused tin lead finish. With HASL, OSP, ENIG, Immersion
Tin, Immersion Silver finishes, the electroplated tin lead is stripped after
etch, hence the term soldermask over bare copper, and then the final finish
applied.
In my past, we converted a board finish from HASL to reflowed tin lead (but
3-5um, not 8-12um), so that the customer had a perfectly flat finish for
assembling RF cans, and it improved their first pass yield from 86% to 98%.
Unfortunately for the competition, they had thrown out their IR reflow, and
converted the tin lead baths to tin, so couldn't offer the finish !
Concerns over intermetallic growth prior to assembly were proven to be
unjustified, probably due to the short time between manufacture and
assembly - JIT works in some companies - and the commercial advantage was
significant as it reduced process steps, and increased assembly yield.
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 3:38 AM
Subject: Re: [TN] Electroplated Tin/Lead
> Lemme butt in with some theoretical stuff, that I have seen evidence of.
>
> The subject is galvanic corrosion, or what happens when you have two
metals
> (like Tin and Lead) electrically in contact with each other, and with the
> corrosive material.
>
> When this is the case, the more readily attacked of the two metals (in
this
> case Tin) is MUCH more readily attacked, while the less readily attacked
> metal is protected. This is why galvanized pails do not rust as easily as
a
> bare steel pail would, that is why you "galvanize."
>
> However, in this case, you are trying to protect the entire exposed
surface,
> both Tin and Lead, and keep the surface solderable. So, this is not such
a
> good idea, as the presence of the Lead should/would accelerate attack on
the
> Tin. Or, what I am suggesting is that by this theory, Tin/Lead should be
> LESS protective than pure Tin.
>
> (All of the above advice goes out the window if you fuse or "reflow" the
> Tin/Lead deposit, in which case the plated metals form a true alloy,
instead
> of discrete crystals of Tin and crystals of Lead, and thus act like a
single
> metal.)
>
> Remember, free advice is often not worth what you paid for it....:-)
>
> Rudy Sedlak
> RD Chemical Company
>
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Date: Fri, 25 Jan 2002 09:56:21 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Lead replacement solder alloys
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_002C_01C1A586.8BBCC710"
This is a multi-part message in MIME format.
------=_NextPart_000_002C_01C1A586.8BBCC710
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Lead free alloys come in 2 types: generic and proprietary/patented. The
more alloying additions the more likely the alloy is to fall into the second
category.
Generic alloys are available from just about any recognised solder
manufacturer, proprietary alloys are available from the patent holder and
any licensees.
If the alloy has actual or perceived merit for general industry use then it
is likely you will find that other manufacturers have licensed it and you
can again obtain it from just about any recognised manufacturer
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Thursday, January 24, 2002 9:00 PM
To: [log in to unmask]
Subject: [TN] Lead replacement solder alloys
Who is the procurement source for a couple of the newer Sn 63 like solders
that have somewhat better properties than Sn63. Specifically they are the
SnAgCuSb and SnAgCuZn alloys.
Thanks
Phil Hinton
------=_NextPart_000_002C_01C1A586.8BBCC710
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>Lead free=20
alloys come in 2 types: generic and =
proprietary/patented. The=20
more alloying additions the more likely the alloy is to fall into the =
second=20
category. </FONT></SPAN></DIV>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>Generic=20
alloys are available from just about any recognised solder =
manufacturer,=20
proprietary alloys are available from the patent holder and any=20
licensees.</FONT></SPAN></DIV>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>If the alloy=20
has actual or perceived merit for general industry use then it =
is=20
likely you will find that other manufacturers have licensed it and you =
can again=20
obtain it from just about any recognised =
manufacturer</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT face=3DArial color=3D#0000ff>Kind Regards</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Mike Fenner</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Applications Engineer, European=20
Operations</FONT> <BR><B><FONT face=3DArial color=3D#0000ff>Indium=20
Corporation</FONT></B> <BR><FONT face=3DArial color=3D#0000ff> T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial color=3D#0000ff>M: + 44 7810 526 =
317</FONT>=20
<BR><FONT face=3DArial color=3D#0000ff> F: + 44 1908 580 411</FONT> =
<BR><FONT=20
face=3DArial color=3D#0000ff> E: [log in to unmask]</FONT> =
<BR><FONT face=3DArial=20
color=3D#0000ff>W:<U> www.indium.com</U> </FONT><BR><FONT =
face=3DArial=20
color=3D#0000ff>Leadfree:</FONT><U> <FONT face=3DArial=20
color=3D#0000ff>www.Pb-Free.com</FONT></U> </P>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Thursday, January 24, 2002 9:00 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Lead replacement solder=20
alloys<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Who is the=20
procurement source for a couple of the newer Sn 63 like solders that =
have=20
somewhat better properties than Sn63. Specifically they are the =
SnAgCuSb=20
and SnAgCuZn alloys. <BR><BR>Thanks <BR>Phil Hinton=20
</FONT></FONT></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_002C_01C1A586.8BBCC710--
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Date: Fri, 25 Jan 2002 07:13:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
Eric,
I agree with you. Seen it a few times but only from non-qualified/capable
assembly houses. Another thing I've seen are hole wall opens, as cracks and
delam in boards from the same type fab shops.
Earl
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Date: Fri, 25 Jan 2002 07:21:49 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: NEED "GOOD" ASSEMBLY HOUSE
Folks,
I am much in need of a "GOOD" assembly house to do some assemblies. How
about that for irony?
The board is about 10" square, 12 layers, 7 CSP's on .8 mm centers, one
full array ceramic BGA on 1mm centers, 1 perimeter BGA on 1 mm, couple of
20 mil pitch QFP's, and some other "normal" stuff as well as just a few
through hole things and a few passives on the bottom side.
Again, I'd like to have a house in or near northern Ohio but I'll consider
others as needed. How about Steve's house or Dave Fish's fine eatery?
Please get back to me soon concerning this wonderful opportunity.
Earl Moon
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Date: Fri, 25 Jan 2002 07:23:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
Amazing how that works Dan. Really builds confidence as well.
MoonMan
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Date: Fri, 25 Jan 2002 07:28:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: [log in to unmask]
Werner,
Thanks for the numbering info. Thanks as well for the rest. Your following
deserves a reply:
Seriously, though, your "small, but very much on the rise non-manufacturing
oriented telecom
company" will not be rising much farther, if they assemble BGAs/PWAs this
way. I do not think you reallllly need any help with this.
Well, it's up to me to show them the light and error of their ways. So far,
so good.
Can I top this story? Would this qualify? At Bell Labs--the former vibrant
Bell Labs, not the current empty shell--one guy tried to pattent the idea of
putting a screw in the center of the package and fasteninng it to the PCB
through a hole with a nut.
I hesitate to say that idea was brought up in a meeting yesterday. Unreal?
Earl
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Date: Fri, 25 Jan 2002 09:26:13 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_8d.12e552ef.2982c505_boundary"
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Content-Transfer-Encoding: 7bit
Scott
no pun intened - but your e-mail did say "vary" flat, and yes - you are right
- it does vary. one thing to consider - that when metal is electroplated -
whether it be an alloy or not - now we get into a totally new dimension of
things.
electroplating has to deal with metal distribution across the surface of the
board - if a spec of 300 microinches or so of solder is called for - you
would have to worry about the distribution of the metal across the surface of
the circuity. your low current areas maybe right on the money - but now the
high current areas might be off by as much as 20 to 40% - alldepending on the
set up of the electroplating tank - or vice versa.
if you do decide to go with such a finish - i would suggest having a few
pieces protoed with this finish anf check for the distribution across the
surface of the board.
then there is the "galvanic effect " to contend with as Rudy mentioned in his
e-mail.
a third scenario to contend with is that the working bath is in optimum
operating condition - or the alloy will be way off the 60/40 deposit - (plus
or minus a few percent). in the days of fused solder - keeping that bath in
optimum plating conditions was a nightmare for some fab shops - too high a
current - the higher the tin deposit - too low a current - the higher the
lead deposit.
as i mentioned earlier - find a fab shop or plating shop - and have a few
boards finished with the solder first.
regards
Rich Fudalewski
Florida Cirtech Inc
--part1_8d.12e552ef.2982c505_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Scott
<BR>
<BR>no pun intened - but your e-mail did say "vary" flat, and yes - you are right - it does vary. one thing to consider - that when metal is electroplated - whether it be an alloy or not - now we get into a totally new dimension of things.
<BR>
<BR>electroplating has to deal with metal distribution across the surface of the board - if a spec of 300 microinches or so of solder is called for - you would have to worry about the distribution of the metal across the surface of the circuity. your low current areas maybe right on the money - but now the high current areas might be off by as much as 20 to 40% - alldepending on the set up of the electroplating tank - or vice versa.
<BR>
<BR>if you do decide to go with such a finish - i would suggest having a few pieces protoed with this finish anf check for the distribution across the surface of the board.
<BR>then there is the "galvanic effect " to contend with as Rudy mentioned in his e-mail.
<BR>
<BR>a third scenario to contend with is that the working bath is in optimum operating condition - or the alloy will be way off the 60/40 deposit - (plus or minus a few percent). in the days of fused solder - keeping that bath in optimum plating conditions was a nightmare for some fab shops - too high a current - the higher the tin deposit - too low a current - the higher the lead deposit.
<BR>
<BR>as i mentioned earlier - find a fab shop or plating shop - and have a few boards finished with the solder first.
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>
<BR>Florida Cirtech Inc</FONT></HTML>
--part1_8d.12e552ef.2982c505_boundary--
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Date: Fri, 25 Jan 2002 08:30:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Robisan Labs and need for x-sectioning
If Susan is out there, I need a couple of x-sections as received and after
thermal stress. Could you reply so we can trade info?
Earl Moon
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Date: Fri, 25 Jan 2002 15:03:33 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
A nut eh?
Surely a self tapping screw, driven home using the theta drive on the pick
and place head would be more efficient?
Regards
Eric Dawson
> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Friday, January 25, 2002 1:28 PM
> To: [log in to unmask]
> Subject: Re: [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Werner,
>
> Thanks for the numbering info. Thanks as well for the rest. Your following
> deserves a reply:
>
> Seriously, though, your "small, but very much on the rise
> non-manufacturing
> oriented telecom
> company" will not be rising much farther, if they assemble BGAs/PWAs this
> way. I do not think you reallllly need any help with this.
>
> Well, it's up to me to show them the light and error of their ways. So
> far,
> so good.
>
> Can I top this story? Would this qualify? At Bell Labs--the former vibrant
> Bell Labs, not the current empty shell--one guy tried to pattent the idea
> of
> putting a screw in the center of the package and fasteninng it to the PCB
> through a hole with a nut.
>
> I hesitate to say that idea was brought up in a meeting yesterday. Unreal?
>
> Earl
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> SET Technet NOMAIL
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> E-mail Archives
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
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Date: Fri, 25 Jan 2002 07:28:17 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank L Norman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank L Norman <[log in to unmask]>
Subject: Re: Water soluble solder mask
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Steve,
The batch washer is just like your dishwasher at home. It washes with a
saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
monitored), draining and filling with fresh DI water each time.
Frank Norman
Raytheon
[log in to unmask]
805-879-2745
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] Water soluble solder mask
<[log in to unmask]
ORG>
01/24/02
06:44 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi Frank!
Question: Are you closed-loop with your water?
-Steve Gregory-
Hi all,
Looking for insight about using water soluble solder mask.
We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.
Frank Norman
Raytheon
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Date: Thu, 24 Jan 2002 15:47:38 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: center of a arc
X-To: Matt Eubank <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
To construct this on paper is real easy. Draw a straight line between two
points on the arc (called a chord). Then use your compass and draw two
circles each with the same radius as the arc, centered on the end points of
the chord. Where these two circles intersect each other is the center of the
arc. (You can choose which one of the two intersections is the correct one.)
To calculate it with geometry is a little more involved:
You know the two points on the arc: x1,y1 and x2,y2. The centerpoint of the
chord is (x1-x2)/2, (y1-y2)/2, or x3,y3. Half the length of the chord is
h=((x3-x1)^2 +(y3-y1)^2)^0.5. This is one side of the right triangle, of
which the hypotenuse is the arc radius and the third side is the distance
from the center of the chord to the center of the arc. Use Pythagorean
theorem once more: (r^2-h^2)^0.5, and you end up where you want to be.
Regards,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Matt Eubank
Sent: Thursday, January 24, 2002 07:30
To: [log in to unmask]
Subject: [TN] center of a arc
Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.
Thanks
Matt
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Date: Fri, 25 Jan 2002 11:09:12 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Water soluble solder mask
X-To: Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Frank,
What, I believe, Steve is asking is: regarding your washer wastes do you:
* Go to drain
* Reclaim
He is asking you this because some washable temporary solder masks contain
fillers, like clay, that ruin carbon filters used in washer waste
reclaimation systems.
Dave Fish
----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 7:28 AM
Subject: Re: [TN] Water soluble solder mask
> Steve,
>
> The batch washer is just like your dishwasher at home. It washes with a
> saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> monitored), draining and filling with fresh DI water each time.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc:
> TechNet Subject: Re: [TN] Water
soluble solder mask
> <[log in to unmask]
> ORG>
>
>
> 01/24/02
> 06:44 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hi Frank!
>
> Question: Are you closed-loop with your water?
>
> -Steve Gregory-
>
>
> Hi all,
>
> Looking for insight about using water soluble solder mask.
>
> We are currently using a latex solder mask made by Litton. But now the
> question as been asked if water soluble mask could be used instead. Note,
> batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
> Frank Norman
> Raytheon
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
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>
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Date: Fri, 25 Jan 2002 10:25:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Ahne gets you almost all the way there mathematically. You now know the
distance from the center of the chord to the center of the circle. You
don't yet know the actual coordinates of the center. Apply the Pythagorean
theorem a couple more times and solve the simultaneous equations and you got
it.
From Ahne:
(r^2-h^2)^0.5= d, distance from x3,y3 to x4,y4 (the circle center) we need
to find x4,y4
d^2=(x4-x3)^2 + (y4-y3)^2 two unknowns (x4,y4), one equation
we also know:
r^2=(x4-x1)^2 + (y4-y1)^2 two equations, two unknowns, a little
algebra and it's solved
Whew, it is much easier just with a compass and a ruler!!!
-----Original Message-----
From: Ahne Oosterhof [mailto:[log in to unmask]]
Sent: January 24, 2002 5:48 PM
To: [log in to unmask]
Subject: Re: [TN] center of a arc
To construct this on paper is real easy. Draw a straight line between two
points on the arc (called a chord). Then use your compass and draw two
circles each with the same radius as the arc, centered on the end points of
the chord. Where these two circles intersect each other is the center of the
arc. (You can choose which one of the two intersections is the correct one.)
To calculate it with geometry is a little more involved:
You know the two points on the arc: x1,y1 and x2,y2. The centerpoint of the
chord is (x1-x2)/2, (y1-y2)/2, or x3,y3. Half the length of the chord is
h=((x3-x1)^2 +(y3-y1)^2)^0.5. This is one side of the right triangle, of
which the hypotenuse is the arc radius and the third side is the distance
from the center of the chord to the center of the arc. Use Pythagorean
theorem once more: (r^2-h^2)^0.5, and you end up where you want to be.
Regards,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Matt Eubank
Sent: Thursday, January 24, 2002 07:30
To: [log in to unmask]
Subject: [TN] center of a arc
Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.
Thanks
Matt
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Date: Fri, 25 Jan 2002 08:39:14 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Lunch at Apex (NTC)
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_001C_01C1A57B.C4CE4F20"
This is a multi-part message in MIME format.
------=_NextPart_000_001C_01C1A57B.C4CE4F20
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi all,
Just wanted to drop a line to let everyone know that the Apex lunch =
thing did happen. We met at the IPC booth, and coincidentally, Mr. Bev =
Christian, Ph.D. was browsing the bookstand. Also in attendance was =
Graham Collins, Kathy and Joe Palumbo with their sales folks, Arlene and =
Evie (not technetters), Don Roy and Scott Kramer and myself. We =
"invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" =
The rudest, most irreverent service this side of the Mississippi. It was =
a pleasure to meet these folks in person, and I urge that next year, we =
do the same. Maybe a few more of the infamous technet participants will =
show up (nudge, nudge, Steve and Earl!)=20
Have a great weekend!
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
------=_NextPart_000_001C_01C1A57B.C4CE4F20
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Just wanted to drop a line to let =
everyone know=20
that the Apex lunch thing did happen. We met at the IPC booth, and=20
coincidentally, Mr. Bev Christian, Ph.D. was browsing the bookstand. =
Also in=20
attendance was Graham Collins, Kathy and Joe Palumbo with their sales =
folks,=20
Arlene and Evie (not technetters), Don Roy and Scott Kramer and myself. =
We=20
"invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" =
The=20
rudest, most irreverent service this side of the Mississippi. It was a =
pleasure=20
to meet these folks in person, and I urge that next year, we do the =
same. Maybe=20
a few more of the infamous technet participants will show up (nudge, =
nudge,=20
Steve and Earl!) </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Have a great weekend!</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
------=_NextPart_000_001C_01C1A57B.C4CE4F20--
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=========================================================================
Date: Fri, 25 Jan 2002 16:49:07 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Water soluble solder mask
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
The concern would be that some masks have a very fine powder filler. This
might raise some concerns, for example it could accumulate in closed loop
systems.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Frank L Norman
Sent: Friday, January 25, 2002 3:28 PM
To: [log in to unmask]
Subject: Re: [TN] Water soluble solder mask
Steve,
The batch washer is just like your dishwasher at home. It washes with a
saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
monitored), draining and filling with fresh DI water each time.
Frank Norman
Raytheon
[log in to unmask]
805-879-2745
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] Water soluble
solder mask
<[log in to unmask]
ORG>
01/24/02
06:44 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi Frank!
Question: Are you closed-loop with your water?
-Steve Gregory-
Hi all,
Looking for insight about using water soluble solder mask.
We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.
Frank Norman
Raytheon
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Date: Fri, 25 Jan 2002 09:00:32 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank L Norman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank L Norman <[log in to unmask]>
Subject: Re: Water soluble solder mask
X-To: David Fish <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Steve,
Goes to drain.
Frank Norman
Raytheon
[log in to unmask]
805-879-2745
"David Fish"
<dfish@icubed To: "TechNet E-Mail Forum." <[log in to unmask]>, "Frank L Norman"
.com> <[log in to unmask]>
cc:
01/25/02 Subject: Re: Re: [TN] Water soluble solder mask
11:09 AM
Frank,
What, I believe, Steve is asking is: regarding your washer wastes do you:
* Go to drain
* Reclaim
He is asking you this because some washable temporary solder masks contain
fillers, like clay, that ruin carbon filters used in washer waste
reclaimation systems.
Dave Fish
----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 7:28 AM
Subject: Re: [TN] Water soluble solder mask
> Steve,
>
> The batch washer is just like your dishwasher at home. It washes with a
> saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> monitored), draining and filling with fresh DI water each time.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc:
> TechNet Subject: Re: [TN] Water
soluble solder mask
> <[log in to unmask]
> ORG>
>
>
> 01/24/02
> 06:44 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
>
>
>
>
>
> Hi Frank!
>
> Question: Are you closed-loop with your water?
>
> -Steve Gregory-
>
>
> Hi all,
>
> Looking for insight about using water soluble solder mask.
>
> We are currently using a latex solder mask made by Litton. But now the
> question as been asked if water soluble mask could be used instead.
Note,
> batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
> Frank Norman
> Raytheon
>
>
--------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & Databases
>
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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>
--------------------------------------------------------------------------
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>
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Date: Fri, 25 Jan 2002 12:22:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Water soluble solder mask
X-To: Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Frank,
Try:
* Alpha 110 HV
* Techspray Wondermask 2207G
Both 110 and Wondermask are highly ionic and are "SIR killers" [Doug
'Do-The-Do' Pauls' words], but since you're aqueous processing these boards
it may not be BIG concern.
Dave Fish
----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: "David Fish" <[log in to unmask]>
Cc: "TechNet E-Mail Forum." <[log in to unmask]>
Sent: Friday, January 25, 2002 9:00 AM
Subject: Re: Re: [TN] Water soluble solder mask
>
> Steve,
>
> Goes to drain.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
> "David Fish"
> <dfish@icubed To: "TechNet E-Mail Forum."
<[log in to unmask]>, "Frank L Norman"
> .com> <[log in to unmask]>
> cc:
> 01/25/02 Subject: Re: Re: [TN]
Water soluble solder mask
> 11:09 AM
>
>
>
>
>
>
> Frank,
> What, I believe, Steve is asking is: regarding your washer wastes do you:
> * Go to drain
> * Reclaim
>
> He is asking you this because some washable temporary solder masks contain
> fillers, like clay, that ruin carbon filters used in washer waste
> reclaimation systems.
>
> Dave Fish
>
> ----- Original Message -----
> From: "Frank L Norman" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Friday, January 25, 2002 7:28 AM
> Subject: Re: [TN] Water soluble solder mask
>
>
> > Steve,
> >
> > The batch washer is just like your dishwasher at home. It washes with a
> > saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> > monitored), draining and filling with fresh DI water each time.
> >
> > Frank Norman
> > Raytheon
> > [log in to unmask]
> > 805-879-2745
> >
> >
> >
> >
> > SteveZeva@AOL
> > .COM To: [log in to unmask]
> > Sent by: cc:
> > TechNet Subject: Re: [TN] Water
> soluble solder mask
> > <[log in to unmask]
> > ORG>
> >
> >
> > 01/24/02
> > 06:44 PM
> > Please
> > respond to
> > "TechNet
> > E-Mail
> > Forum.";
> > Please
> > respond to
> > SteveZeva
> >
> >
> >
> >
> >
> >
> > Hi Frank!
> >
> > Question: Are you closed-loop with your water?
> >
> > -Steve Gregory-
> >
> >
> > Hi all,
> >
> > Looking for insight about using water soluble solder mask.
> >
> > We are currently using a latex solder mask made by Litton. But now the
> > question as been asked if water soluble mask could be used instead.
> Note,
> > batch washer(Aqueous Tech. Washer) is used to clean PWAs.
> >
> > Frank Norman
> > Raytheon
> >
> >
> --------------------------------------------------------------------------
> -------
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> > To unsubscribe, send a message to [log in to unmask] with following text
in
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> SET Technet NOMAIL
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> >
> E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> >
> --------------------------------------------------------------------------
> -------
> >
>
>
>
>
>
>
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Date: Fri, 25 Jan 2002 10:56:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Water soluble solder mask
X-To: Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Frank: Some things to consider for temporary water soluble solder mask:
1. Method of application: screen print, auto-dispense XY system, hand
application, etc.
Board volume and feature complexity can influence choice of application.
2. Type of material: filled, unfilled, water base, alcohol base etc .
Method of application, type of cure, dissolution rate, type of washing
equipment/chemistry, assembly compatibility SMT-wavesolder-mixed technology
need to be considered for material choice.
3.Board features to be masked: large features, cut-outs, melting metals etc.
These types of masks usually don't do well over large areas or spanning
cut-outs larger than about 0.300 - 0.400", they can also have a tendency to
flake or crack when used on Sn/Pb when subject to melting temperatures.
4. Applied mask shelflife and storage: masked board storage conditions,
method of storage, hold times prior to use etc.
The humidity, how boards are stored ie wrapped-unwrapped-slip sheets-flat
stacked-edge stacked, hold times greater than three to six months can all
influence the ability of the material to perform correctly.
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Frank L Norman [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 6:22 PM
To: [log in to unmask]
Subject: [TN] Water soluble solder mask
Hi all,
Looking for insight about using water soluble solder mask.
We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.
Frank Norman
Raytheon
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Date: Fri, 25 Jan 2002 14:08:23 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Creative Engineering and Manufacturing Methods..
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_16b.7b88968.29830727_boundary"
--part1_16b.7b88968.29830727_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi all!
Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments B^}
-Steve Gregory-
--part1_16b.7b88968.29830727_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Earl sent me a photo showing a fine example of Creative Engineering and Manufacturing methods, and invites any comments B^}
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_16b.7b88968.29830727_boundary--
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Date: Fri, 25 Jan 2002 14:21:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Water soluble solder mask
X-To: "Barmuta, Mike" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Frank:
Two more considerations:
UV curable water-soluble (in lieu of waiting 30-60 minutes to cure the
mask)
Water-soluble tape or tape dots for large holes.
Al Kreplick
Sr. Mfg. Eng.
Teradyne, Inc.
North Reading, MA
978-370-1726
(Embedded
image moved TechNet <[log in to unmask]>
to file: 01/25/2002 01:56 PM
pic27666.pcx)
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to "Barmuta, Mike" <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Water soluble solder mask
Frank: Some things to consider for temporary water soluble solder mask:
1. Method of application: screen print, auto-dispense XY system, hand
application, etc.
Board volume and feature complexity can influence choice of application.
2. Type of material: filled, unfilled, water base, alcohol base etc .
Method of application, type of cure, dissolution rate, type of washing
equipment/chemistry, assembly compatibility SMT-wavesolder-mixed technology
need to be considered for material choice.
3.Board features to be masked: large features, cut-outs, melting metals
etc.
These types of masks usually don't do well over large areas or spanning
cut-outs larger than about 0.300 - 0.400", they can also have a tendency to
flake or crack when used on Sn/Pb when subject to melting temperatures.
4. Applied mask shelflife and storage: masked board storage conditions,
method of storage, hold times prior to use etc.
The humidity, how boards are stored ie wrapped-unwrapped-slip sheets-flat
stacked-edge stacked, hold times greater than three to six months can all
influence the ability of the material to perform correctly.
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Frank L Norman [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 6:22 PM
To: [log in to unmask]
Subject: [TN] Water soluble solder mask
Hi all,
Looking for insight about using water soluble solder mask.
We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.
Frank Norman
Raytheon
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=========================================================================
Date: Fri, 25 Jan 2002 13:05:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
My Nguyen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: My Nguyen <[log in to unmask]>
Subject: How to convert a .dwg to .pdf
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 25 Jan 2002 22:19:41 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0020_01C1A5EE.625DD2C0"
This is a multi-part message in MIME format.
------=_NextPart_000_0020_01C1A5EE.625DD2C0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
I had already heard about IPC class 0 (that's when the components come =
separate, in a box). I suppose this is IPC class =BD ? The product =
works, but it's supplied with some extra's to keep it that way......
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: [log in to unmask]
To: [log in to unmask]
Sent: Friday, January 25, 2002 8:08 PM
Subject: [TN] Creative Engineering and Manufacturing Methods..
Hi all!=20
Earl sent me a photo showing a fine example of Creative Engineering =
and Manufacturing methods, and invites any comments B^}=20
-Steve Gregory-=20
------=_NextPart_000_0020_01C1A5EE.625DD2C0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I had already heard about IPC class 0 =
(that's when=20
the components come separate, in a box). I suppose this =
is IPC=20
class =BD ? The product works, but it's supplied with some =
extra's to=20
keep it that way......</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Daan Terstegge</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>http://<A=20
href=3D"http://www.smtinfo.net">www.smtinfo.net</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, 2002 =
8:08=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Creative =
Engineering and=20
Manufacturing Methods..</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Hi all! =
<BR><BR>Earl=20
sent me a photo showing a fine example of Creative Engineering and=20
Manufacturing methods, and invites any comments B^} =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0020_01C1A5EE.625DD2C0--
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 25 Jan 2002 16:55:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
You will need a full copy of Adobe Acrobat. (street price about $218.00) =
Adobe Acrobat Reader will not convert the files.
Once Adobe Acrobat is installed, from AutoCAD, print the drawing like =
you normally would, but select the "Adobe Distiller" as your printing =
device.
All other users who are viewing your output PDF files will need a copy =
of Adobe Acrobat Reader installed. This is a free download from =
www.adobe.com.
Happy converting.
Phil Nutting
-----Original Message-----
From: My Nguyen [mailto:[log in to unmask]]
Sent: Friday, January 25, 2002 4:06 PM
To: [log in to unmask]
Subject: [TN] How to convert a .dwg to .pdf
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
-------------------------------------------------------------------------=
--------
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To unsubscribe, send a message to [log in to unmask] with following text =
in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]: =
SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to =
[log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases =
> E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 =
ext.5315
-------------------------------------------------------------------------=
--------
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=========================================================================
Date: Fri, 25 Jan 2002 16:33:30 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0002_01C1A5BE.05C720F0"
This is a multi-part message in MIME format.
------=_NextPart_000_0002_01C1A5BE.05C720F0
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Oh my goodness! Earl told us, but a picture is worth a thousand words. I
wonder if there is a torque specification for that thar adjustable
continuity mak'in device.
I've seen lab types do similar stuff before and ask if the added "fix" can
be applied to production to get their design shipped because the project is
behind schedule.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 1:08 PM
To: [log in to unmask]
Subject: [TN] Creative Engineering and Manufacturing Methods..
Hi all!
Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments B^}
-Steve Gregory-
------=_NextPart_000_0002_01C1A5BE.05C720F0
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>Oh my=20
goodness! Earl told us, but a picture is worth a thousand =
words. I=20
wonder if there is a torque specification for that thar adjustable =
continuity=20
mak'in device.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D910312822-25012002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>I've=20
seen lab types do similar stuff before and ask if the added "fix" =
can be=20
applied to production to get their design shipped because the project is =
behind=20
schedule.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D910312822-25012002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>Don=20
Vischulis</SPAN></FONT></DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Friday, January 25, 2002 1:08 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Creative Engineering and =
Manufacturing=20
Methods..<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi all!=20
<BR><BR>Earl sent me a photo showing a fine example of Creative =
Engineering and=20
Manufacturing methods, and invites any comments B^} =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BODY></HTML>
------=_NextPart_000_0002_01C1A5BE.05C720F0--
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Date: Fri, 25 Jan 2002 16:50:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
Daan,
As usual astute as ever. I like it and propose you propose the class to IPC.
Hell, It's a happening. You saw it here first.
Earl
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Date: Fri, 25 Jan 2002 16:53:08 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
Yes sir,
Specified torque values are currently being developed relative to final
reliability studies. I want us to hire Werner, and all other volunteers, to
perform the studies.
MoonMan
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Date: Fri, 25 Jan 2002 16:56:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1A5F3.8E4ECF10"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------_=_NextPart_001_01C1A5F3.8E4ECF10
Content-Type: text/plain;
charset="iso-8859-1"
It's a standing joke around here that one of the RnD projects is to design a
'simulated finger' material. For our purposes, it usually isn't a lot of
pressure that is needed. So I envision a foam type product with an adhesive
on one side that you cut pieces to the size and shape you desire to place on
that unstable RF oscillator...
-----Original Message-----
From: Don Vischulis [mailto:[log in to unmask]]
Sent: January 25, 2002 4:34 PM
To: [log in to unmask]
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..
Oh my goodness! Earl told us, but a picture is worth a thousand words. I
wonder if there is a torque specification for that thar adjustable
continuity mak'in device.
I've seen lab types do similar stuff before and ask if the added "fix" can
be applied to production to get their design shipped because the project is
behind schedule.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 1:08 PM
To: [log in to unmask]
Subject: [TN] Creative Engineering and Manufacturing Methods..
Hi all!
Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments B^}
-Steve Gregory-
------_=_NextPart_001_01C1A5F3.8E4ECF10
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.3315.2870" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=723325222-25012002>It's a
standing joke around here that one of the RnD projects is to design a 'simulated
finger' material. For our purposes, it usually isn't a lot of pressure
that is needed. So I envision a foam type product with an adhesive on one
side that you cut pieces to the size and shape you desire to place on that
unstable RF oscillator...</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=723325222-25012002></SPAN></FONT> </DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Don Vischulis
[mailto:[log in to unmask]]<BR><B>Sent:</B> January 25, 2002 4:34
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Creative
Engineering and Manufacturing Methods..<BR><BR></DIV></FONT>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>Oh
my goodness! Earl told us, but a picture is worth a thousand
words. I wonder if there is a torque specification for that thar
adjustable continuity mak'in device.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=910312822-25012002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>I've
seen lab types do similar stuff before and ask if the added "fix" can be
applied to production to get their design shipped because the project is
behind schedule.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=910312822-25012002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>Don
Vischulis</SPAN></FONT></DIV>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>[log in to unmask]<BR><B>Sent:</B>
Friday, January 25, 2002 1:08 PM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> [TN] Creative Engineering and Manufacturing
Methods..<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi all!
<BR><BR>Earl sent me a photo showing a fine example of Creative Engineering
and Manufacturing methods, and invites any comments B^}
<BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1A5F3.8E4ECF10--
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Date: Fri, 25 Jan 2002 15:02:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dave Snyder <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dave Snyder <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: My Nguyen <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
You need to buy Adobe Acrobat. The reader is free but if you want to make
pdf's, you need to buy Acrobat (List $249 USD).
Dave Snyder
Manf. Eng. Manager
HM Electronics, Inc.
-----Original Message-----
From: My Nguyen [mailto:[log in to unmask]]
Sent: Friday, January 25, 2002 1:06 PM
To: [log in to unmask]
Subject: [TN] How to convert a .dwg to .pdf
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Fri, 25 Jan 2002 15:12:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Carl VanWormer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: My Nguyen <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
There is a free PDF conversion process at
http://www.webxd.com/zipguy/frpdfdl.htm that is a bit of a pain to set up,
but I've been using for a year with very good results.
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: My Nguyen [mailto:[log in to unmask]]
Sent: Friday, January 25, 2002 1:06 PM
To: [log in to unmask]
Subject: [TN] How to convert a .dwg to .pdf
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Fri, 25 Jan 2002 15:13:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Denis Lefebvre <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: My Nguyen <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
It simply requires that you have Adobe Acrobat [full version, not just the
reader] installed on your PC.
With Acrobat installed, simply go to print and select the Acrobat PDF
Writer as your printer. VIOLA! A PDF file!
Denis Lefebvre, C.I.D.
Senior PCB Designer
Salinas, CA 93906
At 01:05 PM 1/25/2002 -0800, you wrote:
>Hello all,
>
>Not all my company have Autocad 2000, thus, they
>wanted me to convert my drawings into pdf format.
>Unfortunately, I don't know how.
>
>Is there any way for it? Please advise!
>
>You all have a great weekend!
>
>M.N
>
>__________________________________________________
>Do You Yahoo!?
>Great stuff seeking new owners in Yahoo! Auctions!
>http://auctions.yahoo.com
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
>
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Date: Fri, 25 Jan 2002 17:21:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
Genny,
A little askew but some folks at HAC, years ago, designed some impedence
controlled flex stuff with styrofoam to emulate the Dk of air. Didn't work
but thought I'd bring this up because without such a low dielectric constant
broadband is history.
MoonMan
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Date: Fri, 25 Jan 2002 17:23:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: [log in to unmask]
Denis,
Thanks for the good input. My printer here defaults to .pdf. I'm going to
use it soon.
Earl
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Date: Fri, 25 Jan 2002 18:18:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ron Olinyk <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ron Olinyk <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: My Nguyen <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
m.n.
Probably the easiest way is to install the PDFWriter printer driver from
Adobe then set this as your printer in Acad, printing the dwg as you
normally would. If you don't have Adobe Acrobat, you can setup a PS printer
driver like AppleWriter, print to file as a PS then use a PS to PDF utility
like with Ghostscript to gen the PDF doc.
Ron O.
At 01:05 PM 1/25/02 -0800, you wrote:
>Hello all,
>
>Not all my company have Autocad 2000, thus, they
>wanted me to convert my drawings into pdf format.
>Unfortunately, I don't know how.
>
>Is there any way for it? Please advise!
>
>You all have a great weekend!
>
>M.N
>
>__________________________________________________
>Do You Yahoo!?
>Great stuff seeking new owners in Yahoo! Auctions!
>http://auctions.yahoo.com
>
>---------------------------------------------------------------------------------
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Date: Fri, 25 Jan 2002 20:11:57 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Creative Engineering and Manufacturing Methods..
MIME-Version: 1.0
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Just realized that I didn't post the URL...here it is:
http://www.stevezeva.homestead.com/
-Steve Gregory-
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Date: Fri, 25 Jan 2002 20:42:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Lunch at Apex (NTC)
MIME-Version: 1.0
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Hi Ed!
From the phone-call that we had, sounds like Dick's Last Resort is one fun
place!
Maybe next year it'll be my turn...scratch that, I'll go no matter what. I'll
take PTO (Personal Time Off) and pay for things myself if the trip isn't
funded. San Diego ain't a bad place to take a vacation anyway...
One thing from your post that interests me, and it always had me wondering
(hoping that Kathy has her TechNet ears on), is that I served with a Aviation
Ordnanceman with the last name Palumbo...I think his first name was Michael,
but not really sure...been a while ago...maybe a relative of theirs.
One thing about being in the military, you remember military people that you
served with by their last names...the people that you got close with, you
learned their first names.
Just curious if there's any connection. The Palumbo guy and me served in
Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in
1985...
-Steve Gregory-
> Hi all,
>
> Just wanted to drop a line to let everyone know that the Apex lunch thing
> did happen. We met at the IPC booth, and coincidentally, Mr. Bev Christian,
> Ph.D. was browsing the bookstand. Also in attendance was Graham Collins,
> Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not
> technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's Last
> Resort and everyone agreed that it was "a hoot!" The rudest, most
> irreverent service this side of the Mississippi. It was a pleasure to meet
> these folks in person, and I urge that next year, we do the same. Maybe a
> few more of the infamous technet participants will show up (nudge, nudge,
> Steve and Earl!)
>
> Have a great weekend!
>
> Regards,
>
> Ed Popielarski
> QTA Machine
> 10 Mc Laren, Ste D
> Irvine, Ca. 92618
>
> Phone:949-581-6601
> Fax: 949-581-2448
> Cel: 949-337-2578
>
> <A HREF="http://www.qta.net/">WWW.QTA.NET</A>
>
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Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Ed!<BR>
<BR>
From the phone-call that we had, sounds like Dick's Last Resort is one fun place!<BR>
<BR>
Maybe next year it'll be my turn...scratch that, I'll go no matter what. I'll take PTO (Personal Time Off) and pay for things myself if the trip isn't funded. San Diego ain't a bad place to take a vacation anyway...<BR>
<BR>
One thing from your post that interests me, and it always had me wondering (hoping that Kathy has her TechNet ears on), is that I served with a Aviation Ordnanceman with the last name Palumbo...I think his first name was Michael, but not really sure...been a while ago...maybe a relative of theirs.<BR>
<BR>
One thing about being in the military, you remember military people that you served with by their last names...the people that you got close with, you learned their first names.<BR>
<BR>
Just curious if there's any connection. The Palumbo guy and me served in Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in 1985...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Just wanted to drop a line to let everyone know that the Apex lunch thing did happen. We met at the IPC booth, and coincidentally, Mr. Bev Christian, Ph.D. was browsing the bookstand. Also in attendance was Graham Collins, Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" The rudest, most irreverent service this side of the Mississippi. It was a pleasure to meet these folks in person, and I urge that next year, we do the same. Maybe a few more of the infamous technet participants will show up (nudge, nudge, Steve and Earl!) </FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Have a great weekend!</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Regards,</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Ed Popielarski<BR>
QTA Machine<BR>
10 Mc Laren, Ste D<BR>
Irvine, Ca. 92618</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Phone:949-581-6601<BR>
Fax: 949-581-2448<BR>
Cel: 949-337-2578</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><A HREF="http://www.qta.net/">WWW.QTA.NET</A></FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
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Date: Fri, 25 Jan 2002 20:12:41 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
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Hey Earl
This is telecom, right? Doesn't GR78 become one of the governing docs?
Better start testing the balsa wood for SIR and ionics. Inner layers too if
the balsa is laminated.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 7:12 PM
To: [log in to unmask]
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..
Just realized that I didn't post the URL...here it is:
http://www.stevezeva.homestead.com/
-Steve Gregory-
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Date: Sat, 26 Jan 2002 01:52:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
Don,
Notwithstanding your serious concerns, ESD is an issue as well. I have
recommended a move away from balsa to a more electrically friendly type wood.
Soon, I will be traveling to Brazil to talk with an enture tribe of
technically astute Amazon ladies who have started a new venture for what
they see as a growth industry focused on users like me. In this light, we
will work very closely together developing new offspring of currently
available arborial saplings providing the characteristics required to
neutralize current deficiencies.
I hope you and all our friends out there realize such dedication and
creativism is born out of DFM/CE and the hard, fast rules making it
possible. Also, realize the "C" clamp business will find new prosperity.
This brings to mind trememdous investment possibilties for all those having
lost their money and asses, not withstanding gunshot wounds to the head, at
Enron.
Kind Regards and wish me well as I do you all,
MoonSapMan
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Date: Sat, 26 Jan 2002 09:23:01 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
X-To: My Nguyen <[log in to unmask]>
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An alternative is JAWS PDF Creator. It's been said that it's better than =
Acrobat, and it sure is cheaper.
At http://www.jawssystems.com/ you can download a free trial version.
Daan
http://www.smtinfo.net
----- Original Message -----=20
From: My Nguyen=20
To: [log in to unmask]
Sent: Friday, January 25, 2002 10:05 PM
Subject: [TN] How to convert a .dwg to .pdf
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
=
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charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>
<DIV><FONT face=3DArial size=3D2>An alternative is JAWS PDF Creator. =
It's been said=20
that it's better than Acrobat, and it sure is cheaper.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>At <A=20
href=3D"http://www.jawssystems.com/">http://www.jawssystems.com/</A> =
;you can=20
download a free trial version.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Daan</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV></=
DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">My=20
Nguyen</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, 2002 =
10:05=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] How to convert a =
.dwg to=20
.pdf</DIV>
<DIV><BR></DIV>Hello all,<BR><BR>Not all my company have Autocad 2000, =
thus,=20
they<BR>wanted me to convert my drawings into pdf =
format.<BR>Unfortunately, I=20
don't know how.<BR><BR>Is there any way for it? Please=20
advise!<BR><BR>You all have a great=20
=
weekend!<BR><BR>M.N<BR><BR>______________________________________________=
____<BR>Do=20
You Yahoo!?<BR>Great stuff seeking new owners in Yahoo! =
Auctions!<BR><A=20
=
href=3D"http://auctions.yahoo.com">http://auctions.yahoo.com</A><BR><BR>-=
-------------------------------------------------------------------------=
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Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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Date: Sat, 26 Jan 2002 08:52:48 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
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I love the K-Mart [plastic] bag in the background of the pix.
Dave Fish
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 5:11 PM
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..
> Just realized that I didn't post the URL...here it is:
>
> http://www.stevezeva.homestead.com/
>
> -Steve Gregory-
>
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Date: Sat, 26 Jan 2002 08:37:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Creative Engineering and Manufacturing Methods..
X-To: [log in to unmask]
What you see came not from my favorite store - the one you put me on to
about two years ago when I needed a bottom side board heater (turned out to
be a pancake griddle as a blue light special) - that I have not been in
since. Gonna miss those folks. Very smart business people. The bag is one
for toting my six pack, from a highly respected Armenian deli, near work and
my palacial suite high above the Cayahoga river and sewage outlet.
Ok, so ESD isn't a big issue around my desk (out back in the bleachers).
However, it will be soon.
For Brian, the folks at this company are some of the brightest, most
creative people I've met in some time. They have the unrestrained freedom to
develop and build product any way they see fit.
The standing joke is "quality system - what a unique concept." Yes folks,
I'm starting at the bottom (whale shit is above my level kinda like an IMC
layer) with this one but one needs a measure of job security in these
trying, economically compromised times. This little project should take no
more than a year or so - then back to my social club in BF Montana.
MoonBagMan
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Date: Sat, 26 Jan 2002 13:30:13 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: (OT) Earl Moon Endowment Fund...
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I know Earl is a man of many, many talents, but I didn't know that he had a
college sponsoring tuitions in his name...I think they've been a little
premature saying that it's a "Memorial Endowment Fund" though...he's alive
and kicking as far as we know?
Check this out:
http://www.spebsqsa.org/HCDC/earlmoon.htm
hehehe...
-Steve Gregory-
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Date: Sat, 26 Jan 2002 15:22:07 -0800
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Date: Sat, 26 Jan 2002 19:27:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: (OT) Earl Moon Endowment Fund...
X-To: [log in to unmask]
Steve,
As with most things in which you take interest, this didn't escape your
sharp eye and keen inquisitiveness. It is true I'm not yet departed, but
this is the point.
All of you out there may take advantage of a secret told me by a very wise
person many years ago. You too may find it advantageous to set up a college
endowment before your time is at an end.
For a small stipend, I will share this fabulous secret that will make you
rich, though not in dollars, beyond your fondest dreams. Simply send me a
large self addressed box, capable of holding many pounds of electronic waste
(produced by creative minds without constraint or rules and no DFM/CE
program) and a few dollars, and I'll send you the effect of that creativity.
Yes folks, you can make it big and bad by allowing me to take the pressure
off your consciences allowing you to run amuck much as most of my clients.
Why be different. Go for it. You may not become successful or rich (leave
that to me), but think of the freedom you'll enjoy without creative constraint.
I look forward to your responses (make cashier's checks payable to MoonMan).
MoonEndowedMan
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Date: Sun, 27 Jan 2002 16:28:09 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
hsinsun <[log in to unmask]>
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Subject: 886-2-27924598 Design &
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; E – Coating, Painting Plating`s Peripherals & Equipments E-Mail :[log in to unmask] [log in to unmask] Web Site: http:// www.john-young.com.tw http:// johnyoung.tisnet.net.tw/ .
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Date: Sat, 26 Jan 2002 12:51:50 +0000
Reply-To: Roger Bilham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Bilham <[log in to unmask]>
Subject: Re: Lead replacement solder alloys
In-Reply-To: <002b01c1a586$8bbcc710$f502a8c0@ukomfenner>
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Mike,
I would like to add a third type of lead free alloy, namely allegedly
patented. There are a lot of patent applications out there that will
never make it to being granted patents and a number of patents granted
but invalid! No names, no pack drill.
Roger
In article <002b01c1a586$8bbcc710$f502a8c0@ukomfenner>, Mike Fenner
<[log in to unmask]> writes
> Lead free alloys come in 2 types: generic and
> proprietary/patented. The more alloying additions the more likely
> the alloy is to fall into the second category.
> Generic alloys are available from just about any recognised solder
> manufacturer, proprietary alloys are available from the patent
> holder and any licensees.
> If the alloy has actual or perceived merit for general
> industry use then it is likely you will find that other
> manufacturers have licensed it and you can again obtain it from
> just about any recognised manufacturer
>
>
> Kind Regards
>
> Mike Fenner
>
> Applications Engineer, European Operations
> Indium Corporation
> T: + 44 1908 580 400
> M: + 44 7810 526 317
> F: + 44 1908 580 411
> E: [log in to unmask]
> W: www.indium.com
> Leadfree: www.Pb-Free.com
>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]]On Behalf Of
>> [log in to unmask]
>> Sent: Thursday, January 24, 2002 9:00 PM
>> To: [log in to unmask]
>> Subject: [TN] Lead replacement solder alloys
>
>> Who is the procurement source for a couple of the newer Sn 63
>> like solders that have somewhat better properties than Sn63.
>> Specifically they are the SnAgCuSb and SnAgCuZn alloys.
>
>> Thanks
>> Phil Hinton
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Sun, 27 Jan 2002 08:47:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: ENVIRONMENT AND TERMITES
As I'm very happy many folks are joining and offering to the EnvironNet, I
would like to offer the following though I'm, thankfully to all, not joining in:
Termites were, before the rain forests were destroyed, by far the largest
methane gas producers on this planet. Maybe they are still.
MoonMan
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Date: Sun, 27 Jan 2002 18:53:29 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: ENVIRONMENT AND TERMITES
X-To: Earl Moon <[log in to unmask]>
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Earl
The largest single methane gas producer in the animal kingdom is almost
certainly the elephant :-) The most important methane emitter, in recent
years, in the animal kingdom is man, but mostly from fossil sources
(even taking into account baked beans).
Termites do produce methane, but a very small part of the total. Of
course, the two major sources of methane are swampland and rice paddies,
counting for over 50% of the total (I have the figures in a book which I
can't seem to lay my hands on, just now).
However, this intervention should most certainly have gone on EnviroNet.
Best regards,
Brian
Earl Moon wrote:
>
> As I'm very happy many folks are joining and offering to the EnvironNet, I
> would like to offer the following though I'm, thankfully to all, not joining in:
>
> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
> MoonMan
>
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Date: Sun, 27 Jan 2002 12:23:16 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENVIRONMENT AND TERMITES
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Hi Earl,
While I have no argument about termites being here for some time, they have
also been kept in check by the balance of nature. I am certain that you
realize that termites and methane are not the only subjects discussed at
EnviroNet. (The forum was not established just for termites and methane
anyway, termites would likely have little interest in the discussions and
methane can't read ;-)
The discussions were, however, meant for humans who, as a species, seem to be
prone to believe either that we can fully master and control nature or that
we are not having any effect or that because we are a product of nature that
what ever we do is, de facto, natural including the ultimate consequences
whatever they may be.
Your wit, intelligence and experience are a delight to this forum and while
they would be welcome in the EnviroNet forum, you are, of course, welcome to
opt out and exclude yourself from the discussions and information on the
EnviroNet. There are no compulsory forums.
The discussions are, however, wide ranging and most interesting and all
welcome to join in and advance their understanding and education on the
environment and share their thoughts, experiences and findings.
If we had done something like this earlier such contentious issues as
lead-free and halogen-free (which have been asserted to be environmentally
friendly without proof) would perhaps not be weighing down the industry at
this time.
Kind regards,
Joe
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Earl,
<BR>
<BR>While I have no argument about termites being here for some time, they have also been kept in check by the balance of nature. I am certain that you realize that termites and methane are not the only subjects discussed at EnviroNet. (The forum was not established just for termites and methane anyway, termites would likely have little interest in the discussions and methane can't read ;-)
<BR>
<BR>The discussions were, however, meant for humans who, as a species, seem to be prone to believe either that we can fully master and control nature or that we are not having any effect or that because we are a product of nature that what ever we do is, de facto, natural including the ultimate consequences whatever they may be.
<BR>
<BR>Your wit, intelligence and experience are a delight to this forum and while they would be welcome in the EnviroNet forum, you are, of course, welcome to opt out and exclude yourself from the discussions and information on the EnviroNet. There are no compulsory forums.
<BR>
<BR>The discussions are, however, wide ranging and most interesting and all welcome to join in and advance their understanding and education on the environment and share their thoughts, experiences and findings.
<BR>
<BR>If we had done something like this earlier such contentious issues as lead-free and halogen-free (which have been asserted to be environmentally friendly without proof) would perhaps not be weighing down the industry at this time.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>
--part1_3c.18458459.29859184_boundary--
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Date: Sun, 27 Jan 2002 14:55:00 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENVIRONMENT AND TERMITES
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In a message dated 1/27/02 9:26:48 AM Pacific Standard Time,
[log in to unmask] writes:
> because we are a product of nature that
> what ever we do is, de facto, natural including the ultimate consequences
> whatever they may be.
The above, of course, is undeniably true...but like cobra venom, and other
wonderful "natural" things, like Anthrax, Black Death, Typhus, and AIDS,
everything natural is not wonderful...at least to the specie it decimates....
Rudy Sedlak
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Date: Sun, 27 Jan 2002 15:41:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ENVIRONMENT AND TERMITES
X-To: [log in to unmask]
Joe,
Love to join you all but am incompetent only at one thing at a time. While
very interested in human survival, I believe we will opt for money down to
the last man/woman left on earth. There is nothing the human condition will
change but itself dependent on green and that ain't nothing but money.
MoonMan
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Date: Sun, 27 Jan 2002 18:39:32 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENVIRONMENT AND TERMITES
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Hi Rudy and Earl,
Rudy, I cannot but agree with the notion that not all in nature is wonderful
to see but it is at least natural. However, when a species sets about
decimating itself it seems to me that such action is unnatural...Or could it
be that our species is unconsciously looking to the lemmings for inspiration.
;-)
Earl, I appreciate your comments. You have live long enough and seen enough
to be cynical. I have put in my years also and have my cynical side as well
but I still feel compelled to continue the struggle no matter the odds or how
low the apparent interest of others. I was taught in the Army and learned in
Viet Nam that the struggle was not for ourselves but more immediately for one
another and ultimately (hopefully) for a distant future, a future in which we
will play no part, except that we are now setting the stage for those who
follow.
"Life is a series of collisions with the future; it is not the sum of what we
have been, but what we yearn to be." -Jose Ortega y Gasset
I just don't have it in me to turn my back and walk away.
This philosophical discussion like many others would be best held over a
pitcher of beer... ;-)
Very best!
Joe
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Rudy and Earl,
<BR>
<BR>Rudy, I cannot but agree with the notion that not all in nature is wonderful to see but it is at least natural. However, when a species sets about decimating itself it seems to me that such action is unnatural...Or could it be that our species is unconsciously looking to the lemmings for inspiration. ;-)
<BR>
<BR>Earl, I appreciate your comments. You have live long enough and seen enough to be cynical. I have put in my years also and have my cynical side as well but I still feel compelled to continue the struggle no matter the odds or how low the apparent interest of others. I was taught in the Army and learned in Viet Nam that the struggle was not for ourselves but more immediately for one another and ultimately (hopefully) for a distant future, a future in which we will play no part, except that we are now setting the stage for those who follow.
<BR>
<BR>"Life is a series of collisions with the future; it is not the sum of what we have been, but what we yearn to be." -Jose Ortega y Gasset </FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>I just don't have it in me to turn my back and walk away.
<BR>
<BR>This philosophical discussion like many others would be best held over a pitcher of beer... ;-)
<BR>
<BR>Very best!
<BR>Joe
<BR></FONT></HTML>
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Date: Sun, 27 Jan 2002 23:06:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Source for SnAgCuZn solder
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Hi
Since I did not get any answers to my earlier inquiry after all of the smart
guys have returned from Apex.
Does any one have a supplier source for a solder, Sn96.3/Ag2.5/Cu0.7/Zn 0.5
Thanks
Phil Hinton
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi
<BR>
<BR>Since I did not get any answers to my earlier inquiry after all of the smart guys have returned from Apex.
<BR>
<BR>Does any one have a supplier source for a solder, Sn96.3/Ag2.5/Cu0.7/Zn 0.5
<BR>
<BR>Thanks
<BR>
<BR>Phil Hinton </FONT></HTML>
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Date: Sun, 27 Jan 2002 23:20:00 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Correction
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After rereading e-mail that I sent last Thursday, I see why I got no
answers, since I typed in a enquiry on Sn63 solder when I met a Sn96 with Ag,
Cu, and Zn.
Phil Hinton
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>After rereading e-mail that I sent last Thursday, I see why I got no answers, since I typed in a enquiry on Sn63 solder when I met a Sn96 with Ag, Cu, and Zn.
<BR>
<BR>Phil Hinton </FONT></HTML>
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Date: Sun, 27 Jan 2002 23:39:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENVIRONMENT AND TERMITES
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In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time,
[log in to unmask] writes:
> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
>
Did I miss the news that the rain forests were gone? Funny, I read last year
that the founder of the Sierra Club did a fly over and proclaimed that they
were at least 90% in tact.....?? Guess I better start paying more attention.
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<HTML><FONT FACE=arial,helvetica><FONT COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time, [log in to unmask] writes:
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Termites were, before the rain forests were destroyed, by far the largest
<BR>methane gas producers on this planet. Maybe they are still.
<BR>
<BR></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">
<BR>Did I miss the news that the rain forests were gone? Funny, I read last year that the founder of the Sierra Club did a fly over and proclaimed that they were at least 90% in tact.....?? Guess I better start paying more attention.</FONT></HTML>
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Date: Mon, 28 Jan 2002 13:42:41 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Creative Engineering and Manufacturing Methods..
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Ouch! All them pressures and leverages and stresses and .... what the hell
kind of chassis does that assemblage fit? Who's the thermal engineer on
this one? - 'coz I don't think much of his thermal pads between chips and
G-clamp. Intel have got the jump on this fellow with their P4 solution,
though it's about as chunky.
What can one say, seriously? Hope it doesn't crop up in anything I buy.
Peter
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Creative Engineering and
ORG> Manufacturing Methods..
01/26/02
03:08 AM
Please
respond to
"TechNet
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Please
respond to
SteveZeva
Hi all!
Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments B^}
-Steve Gregory-
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Date: Mon, 28 Jan 2002 15:36:58 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Basic Board Cleaner
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I am looking for a basic board cleaner and ask for your recommendations -
makes and models. I have in mind the old dish washer style of thing with a
resin bed attached for treating incoming water, but you may have more up to
date ideas than I.
We use a CM for assembling boards, so all the flux removal and heavier duty
cleaning is done by them. What I need is a cheap water wash machine that
can dump to drain after filtering out any harmful chemicals and residues
from rework/repair soldering, handling contamination and stripping of
humiseal coating. If you consider closed-loop systems to be better, I'm
open to suggestions, but low cost is the driving factor I have to live
with.
I have searched the net, but so far have only found fairly high-tech (ergo
expesive) machinery that goes beyond my needs.
Any and all help, as ever, is much appreciated.
Peter
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Date: Mon, 28 Jan 2002 08:21:45 +0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Subject: new photos from my party!
------------------ Virus Warning Message (on the network)
Found virus WORM_MYPARTY.A in file www.myparty.yahoo.com
The file www.myparty.yahoo.com is moved to /var/log/iscan/virus/vire0i9Dg.
---------------------------------------------------------
Hello!
My party... It was absolutely amazing!
I have attached my web page with new photos!
If you can please make color prints of my photos. Thanks!
------------------ Virus Warning Message (on the network)
www.myparty.yahoo.com is removed from here because it contains a virus.
---------------------------------------------------------
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Date: Mon, 28 Jan 2002 08:23:00 +0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Subject: new photos from my party!
------------------ Virus Warning Message (on the network)
Found virus WORM_MYPARTY.A in file www.myparty.yahoo.com
The file www.myparty.yahoo.com is moved to /var/log/iscan/virus/virpug4H8.
---------------------------------------------------------
Hello!
My party... It was absolutely amazing!
I have attached my web page with new photos!
If you can please make color prints of my photos. Thanks!
------------------ Virus Warning Message (on the network)
www.myparty.yahoo.com is removed from here because it contains a virus.
---------------------------------------------------------
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Date: Mon, 28 Jan 2002 11:06:23 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Source for SnAgCuZn solder
Mime-Version: 1.0
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Phil
I have a source for SnZn9 and Sn ZnBi ( don't know the composition right =
now) where we get the stuff for research:
Showa Denko
489 fifth Avenue 18th floor
New York, NY 10017
Phone: 1-212-370-0033
Fax: 1-212-370-4566
or in Japan:
13-9 Shiba Daimon 1-Chome
Minato- ku
Tokyo 105-8518
Solder is pretty cheap. However shipping from Japan costs an arm and a =
leg.
Have a great day
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Mon, 28 Jan 2002 15:41:27 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Anil Kher <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anil Kher <[log in to unmask]>
Subject: Black color thin laminates
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mipl1mighty grateful if u can send me offline contacts for manufacturers =
of black color base copper clad laminate - G-10 - thin laminates of =
0.4mm and lesser.
Thanks
Anil Kher
micro interconnexion pvt. ltd.
D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India - =
403110
Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
E-mail :- [log in to unmask]
LEADERS IN GOLD PLATED PCBS
------=_NextPart_000_0059_01C1A812.3F982DA0
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>mipl1</TITLE><Bass=20
href=3D"file://C:\Program Files\Common Files\Microsoft =
Shared\Stationery\">
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR>
<META content=3D"C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot" =
name=3DTemplate>
<STYLE></STYLE>
</HEAD>
<BODY vLink=3D#800080 link=3D#0000ff bgColor=3D#c0c0c0>
<DIV>mighty grateful if u can send me offline contacts for manufacturers =
of=20
black color base copper clad laminate - G-10 - thin laminates of 0.4mm =
and=20
lesser.</DIV>
<DIV>Thanks</DIV>
<DIV>Anil Kher</DIV><B>
<ADDRESS><FONT size=3D2> </ADDRESS></FONT>
<ADDRESS>micro interconnexion pvt. ltd.</ADDRESS>
<ADDRESS>D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , =
India –=20
403110</ADDRESS>
<ADDRESS>Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 /=20
285271.</ADDRESS>
<ADDRESS>E-mail :- [log in to unmask]</ADDRESS></B><FONT =
color=3D#ffff00>
<ADDRESS>LEADERS IN GOLD PLATED PCBS</ADDRESS></FONT></BODY></HTML>
------=_NextPart_000_0059_01C1A812.3F982DA0--
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Date: Mon, 28 Jan 2002 12:36:43 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Basic Board Cleaner
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Peter
I do not advise "dishwasher" type models for high-tech cleaning, as
their efficiency is not good, they are heavy consumers of water and
electricity per m2 of cleaned assemblies and they are bad at drying
because you have to dry the residual water in the machine as well as on
the assemblies. I know -- I made such machines from 1975 to 1978 and
stopped their manufacture exactly because of these reasons. They were
later replaced by much more efficient batch models, in every respect,
but there was a gap of several years when my company, of that time, did
not offer cleaners, while we sussed these problems out. Of course, the
later machines were more expensive in capital expenditure, but the lower
operating costs compensated in a reasonable amortisation period.
For small equipment, closed circuit operation is rarely worth-while. The
problem is that the wide range of contaminants require many treatments.
A typical sequence may be fine mechanical filtration, single stage
reverse osmosis, two stages of active carbon to remove residual
organics, resp. large and small molecule sizes, either double bed +
mixed bed or two large mixed bed DI column and UV treatment to kill
accumulated micro-organisms that proliferate in the DI columns. In the
smallest system, the cost of this (capital and operating) is more than
that of the machine!
It may interest you to know that I recently visited two factories in
China with three "dishwasher" type machines, between them for defluxing.
These were operating in closed circuit with just carbon and mixed-bed DI
columns. They were not satisfied with the results, the operating costs
were horrendous, they had to buy a separate drying oven and they paid an
arm and a leg for the equipment (I think, if I remember correctly, it
was about $80,000 each). They also had problems at a technical level in
that, in all three cases, the manufacturer had not fool-proofed the
system and the machines became unserviceable within the first few hours.
It took several months before the manufacturer (European) had sorted the
problem out.
If you want more info, please contact me off-line and I'll give you the
name of a Chinese company who may be able to help you, and some others.
Brian
[log in to unmask] wrote:
>
> I am looking for a basic board cleaner and ask for your recommendations -
> makes and models. I have in mind the old dish washer style of thing with a
> resin bed attached for treating incoming water, but you may have more up to
> date ideas than I.
>
> We use a CM for assembling boards, so all the flux removal and heavier duty
> cleaning is done by them. What I need is a cheap water wash machine that
> can dump to drain after filtering out any harmful chemicals and residues
> from rework/repair soldering, handling contamination and stripping of
> humiseal coating. If you consider closed-loop systems to be better, I'm
> open to suggestions, but low cost is the driving factor I have to live
> with.
>
> I have searched the net, but so far have only found fairly high-tech (ergo
> expesive) machinery that goes beyond my needs.
>
> Any and all help, as ever, is much appreciated.
>
> Peter
>
> [This e-mail is confidential and may also be privileged. If you are not the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Mon, 28 Jan 2002 11:44:11 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Black color thin laminates
X-To: [log in to unmask]
MIME-Version: 1.0
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I'd be interested too....................
[log in to unmask] wrote:
> mighty grateful if u can send me offline contacts for manufacturers of
> black color base copper clad laminate - G-10 - thin laminates of 0.4mm
> and lesser.ThanksAnil Kher
>
> micro interconnexion pvt. ltd.
> D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India –
> 403110
> Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
> E-mail :- [log in to unmask]
> LEADERS IN GOLD PLATED PCBS
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Mon, 28 Jan 2002 09:06:39 +0000
Reply-To: Roger Bilham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Bilham <[log in to unmask]>
Subject: Re: Source for SnAgCuZn solder
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Content-Type: text/plain;charset=iso-8859-1
Phil
I believe that Soldertec http://www.lead-free.org keeps a directory of
lead free products, which may help you.
Patents covering the composition you give have been applied for by
Matsushita, Sony and Siegfried Pfyffer (and probably others by now), who
may be able to supply information.
Have fun.
Roger Bilham
In article <[log in to unmask]>, [log in to unmask] writes
> Hi
>
> Since I did not get any answers to my earlier inquiry after all of
> the smart guys have returned from Apex.
>
> Does any one have a supplier source for a solder,
> Sn96.3/Ag2.5/Cu0.7/Zn 0.5
>
> Thanks
>
> Phil Hinton
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Mon, 28 Jan 2002 07:17:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Heller and MPM
Folks,
Could all you Heller fans give me a note about reflow and their ovens. I'm
particularly interested in the 1700WN model and how robust it might be for
fairly high thermal mass boards using Kester's 562R solder paste. Kester's
profile looks straight forward enough but one of our suppliers seems to be
having trouble hitting it consistently. By the way, who owns Heller now?
Also, about 7 years ago, I bought a few MPM 2000 printers. They were great
for what we did then. Can someone tell me how they might perform on extra
fine pitch devices as QFP's and .8mm CSP's today?
Thanks,
Earl Moon
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Date: Mon, 28 Jan 2002 08:23:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: How to convert a .dwg to .pdf
MIME-Version: 1.0
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charset="iso-8859-1"
You should first install "ghostscript" utility and then in AutoCAD make post
script
files from *.dwg files and with ghostcript convert *.plt or *.ps file to
pdf.
Shahed
----- Original Message -----
From: My <mailto:[log in to unmask]> Nguyen
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, January 25, 2002 10:05 PM
Subject: [TN] How to convert a .dwg to .pdf
Hello all,
Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.
Is there any way for it? Please advise!
You all have a great weekend!
M.N
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com <http://auctions.yahoo.com>
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<HTML><HEAD>
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charset=3Diso-8859-1">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN =
class=3D542182613-28012002>You=20
should first install "ghostscript" utility and then in AutoCAD make =
post=20
script</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN =
class=3D542182613-28012002>files=20
from *.dwg files and with ghostcript convert *.plt or *.ps file to =
pdf.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN=20
class=3D542182613-28012002></SPAN></FONT> </DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN=20
class=3D542182613-28012002>Shahed</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">My=20
Nguyen</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, =
2002 10:05=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] How to convert =
a .dwg to=20
.pdf</DIV>
<DIV><BR></DIV>Hello all,<BR><BR>Not all my company have Autocad =
2000, thus,=20
they<BR>wanted me to convert my drawings into pdf =
format.<BR>Unfortunately,=20
I don't know how.<BR><BR>Is there any way for it? Please=20
advise!<BR><BR>You all have a great=20
=
weekend!<BR><BR>M.N<BR><BR>_____________________________________________=
_____<BR>Do=20
You Yahoo!?<BR>Great stuff seeking new owners in Yahoo! =
Auctions!<BR><A=20
=
href=3D"http://auctions.yahoo.com">http://auctions.yahoo.com</A><BR><BR>=
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Date: Mon, 28 Jan 2002 07:52:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Lunch at Apex (NTC)
X-To: [log in to unmask]
Mime-Version: 1.0
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Steve,
You're in Tulsa, right? Come on down to Austin and you and I will drive to =
San Antonio. There's a Dick's Last Resort right on the Riverwalk. (Yes, it =
is a "cuh-razy" place. I'll show you first hand.
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
>>> [log in to unmask] 01/25/02 07:42PM >>>
Hi Ed!
From the phone-call that we had, sounds like Dick's Last Resort is one fun
place!
Maybe next year it'll be my turn...scratch that, I'll go no matter what. =
I'll
take PTO (Personal Time Off) and pay for things myself if the trip isn't
funded. San Diego ain't a bad place to take a vacation anyway...
One thing from your post that interests me, and it always had me wondering
(hoping that Kathy has her TechNet ears on), is that I served with a =
Aviation
Ordnanceman with the last name Palumbo...I think his first name was =
Michael,
but not really sure...been a while ago...maybe a relative of theirs.
One thing about being in the military, you remember military people that =
you
served with by their last names...the people that you got close with, you
learned their first names.
Just curious if there's any connection. The Palumbo guy and me served in
Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in
1985...
-Steve Gregory-
> Hi all,
>
> Just wanted to drop a line to let everyone know that the Apex lunch =
thing
> did happen. We met at the IPC booth, and coincidentally, Mr. Bev =
Christian,
> Ph.D. was browsing the bookstand. Also in attendance was Graham Collins,
> Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not
> technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's =
Last
> Resort and everyone agreed that it was "a hoot!" The rudest, most
> irreverent service this side of the Mississippi. It was a pleasure to =
meet
> these folks in person, and I urge that next year, we do the same. Maybe =
a
> few more of the infamous technet participants will show up (nudge, =
nudge,
> Steve and Earl!)
>
> Have a great weekend!
>
> Regards,
>
> Ed Popielarski
> QTA Machine
> 10 Mc Laren, Ste D
> Irvine, Ca. 92618
>
> Phone:949-581-6601
> Fax: 949-581-2448
> Cel: 949-337-2578
>
> <A HREF=3D"http://www.qta.net/">www.QTA.NET</A>
>
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Date: Mon, 28 Jan 2002 08:17:34 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Heller and MPM
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
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MoonMan,
How the heck are ya?=20
Thought I'd answer what I could on your question. First off, I absolutely =
love Heller ovens had a 1700, Nitrogen-inerted, with high-temp heaters =
(for high-lead, no-lead, 80%gold, 20% tin, etc., etc. stuff). Loved the =
consistency. As far as MPM 2000's. loved them as well. Here's a little =
info that may help you. Printers are printers, and options only enhance =
your printing experience. MPM has shown through the years that their =
products are rugged, dependable, well-thought-out, etc. Try this, K&J =
Marketing sells a kapton stencil. It is marketed as "Kepoch". The kapton =
"melts" as it's laser-cut, leaving an ultra-smooth aperture wall. Release =
problems are sayonara. This works especially well on extra-fine pitch =
parts and epoxy screening. As far as CSP, I can only imagine the further =
benefits. THey cost roughly the same as SS stencils and their turnaround =
time is unparalelled. Here is their info:
KJ Marketing Services
115 Thirtieth Street
Toronto, Ontario=20
M8W 3C1=20
Canada=20
Phone (416) 252 1061=20
fax (416) 253 1687=20
Hope this helps (somewhat).
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
>>> [log in to unmask] 01/28/02 07:17AM >>>
Folks,
Could all you Heller fans give me a note about reflow and their ovens. I'm
particularly interested in the 1700WN model and how robust it might be for
fairly high thermal mass boards using Kester's 562R solder paste. Kester's
profile looks straight forward enough but one of our suppliers seems to be
having trouble hitting it consistently. By the way, who owns Heller now?
Also, about 7 years ago, I bought a few MPM 2000 printers. They were great
for what we did then. Can someone tell me how they might perform on extra
fine pitch devices as QFP's and .8mm CSP's today?
Thanks,
Earl Moon
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Date: Mon, 28 Jan 2002 08:14:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: (OT) Earl Moon Endowment Fund...
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_93CEF7CE.98F9949B"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_93CEF7CE.98F9949B
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Would I be purchasing the Kmart bag and the clamp? =20
Kathy=20
--=_93CEF7CE.98F9949B
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Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Would I be purchasing the Kmart bag and the clamp? </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Mon, 28 Jan 2002 09:08:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: (OT) Earl Moon Endowment Fund...
X-To: [log in to unmask]
For you my dear, anything you want - but it ain't no Kmart bag. It's from
Joe's deli and termite emporium.
Haven't been contacted by your sales people yet.
Enjoy,
Earl
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Date: Mon, 28 Jan 2002 09:12:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Heller and MPM
X-To: [log in to unmask]
Jason,
Thanks for the input. I was just a bit concerned about the possibility of
"amatures" not being able to run our fairly high thermal mass boards in an
oven with only 6 zones. I also am a bit concerned with print characteristics
if the printer hasn't been upgraded over the years.
What the heck are you doing in the software side of things? Hell man, you
belong on the floor where all the action is.
Enjoy,
Earl
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Date: Mon, 28 Jan 2002 10:57:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain
Help! Emergency!
We have a completed assembly (top assembly with many boards, hybrids, etc.)
ready for shipment to our customer (space product). The last operation was
to ink mark a S/N. The ink is cured at 150 F for 2 hours. The assembly was
put in an oven at 150 C for two hours. After hours of reviewing all of the
materials and bill of material, component by component (component data,
supplier phone calls, etc.), the only item that is not rated for 150 C is
the polyurethane conformal coating, which turned yellow/brown in color. Can
anyone explain what actually happened to the coating and if it can be used
as is?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Mon, 28 Jan 2002 11:01:13 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Heller and MPM
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Earl,
I used the Heller four zone oven (thinks its a five) to float .190 inch thick
16 layer (double sided SM) with an active .060 thick CIC slab in the center.
The oven worked great. By the way I used the RF SuperMole on each run and
used a fairly large sheet steel fixture... talk about thermal profiling!
This was all compliant to the MIL-STD-2000 spec and a tough QA group. Later
a larger volume went through the Conceptronic oven without incident.
[Success was a function of dummy parts and teaming process controls... hence
its not all the oven.] Major reason for the fixture: boards got very heavy
after a few of them...
Coretec's Boston Brad
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Date: Mon, 28 Jan 2002 10:13:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Heller and MPM
X-To: [log in to unmask]
Thanks BB,
I sure agree with you on the concurrent thing and the profiling. One of our
suppliers has had a few problems, as evidenced by the "C" clamp fiasco. Just
want to remove all the varialbes as possible bad boards, paste, printer, and
oven/profile.
MoonMan
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Date: Mon, 28 Jan 2002 10:22:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Skinny Stencil
Though I kinda like the look of the solder joints, I do believe they may be
a little light on the solder paste volume having been printed using a 5 mil
thick stencil. The thickness is fine for .8 mm stuff and xfine pitch QFP's.
However, I have used step down foils, from 6.5 mils to 5 mils, to ensure
specified paste volume for all parts to accomodate the 1206 types as well.
Also, as previously discussed, I reduce BGA pad sizes 20% from device ball
sizes. For my current design, with a 5 mil thick stencil, I'm printing one
to one with the pad size.
Can I hear an Ahmen from all you SMT brethren out there or am I in purgatory
about to face eternal damnation?
MoonMan
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Date: Mon, 28 Jan 2002 12:17:31 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Enviromental Stress Testing-----Benefits and Drawbacks
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_23.18472e70.2986e1ab_boundary"
--part1_23.18472e70.2986e1ab_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
To All Technetters,
Being from purchasing, I have been asked to rationalize the inherent cost for
demanding quality standards that my company now prescribes to.
Below, I have outlined our company's test criteria for environmental stress
testing:
Panel Allocation Test Description
Thermal Cycle -55C / 150C X1 15 Min x 2 x 100; Test PC boards
without components
Humidity 85/85 X2 7 Days; Test complete units
150C Bake X3 7 Days
Hot Plate/ Oil Temp Shock X4 10 Sec x 20 0C-100C Water Dip
Via Current X5 7 Days / 14 cycles @
25C & 125C
Below, I have outlined several questions so that I can attain a richer
understanding of the intent, benefit and drawbacks of environmental stress
testing:
a. How would moisture absorption effect results of environmental stress
testing?
b. How would soldermask adhesion be effected by environmental stress testing?
c. How is oxidation formed; is it a function of water
absorption/environmental exposure?
d. What could cause via current test (the via are burnt and opened) after
environmental stress testing?
e. If our product is not exposed to any harsh environmental conditions, what
is the benefit for this type of testing?
I would appreciate any and all comments and feedback all of you have to offer.
Regards,
--part1_23.18472e70.2986e1ab_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>To All Technetters,
<BR>
<BR>Being from purchasing, I have been asked to rationalize the inherent cost for demanding quality standards that my company now prescribes to.
<BR>
<BR>Below, I have outlined our company's test criteria for environmental stress testing:
<BR>
<BR>Panel Allocation Test Description
<BR>Thermal Cycle -55C / 150C X1 15 Min x 2 x 100; Test PC boards without components
<BR>Humidity 85/85 X2 7 Days; Test complete units
<BR>150C Bake X3 7 Days
<BR>Hot Plate/ Oil Temp Shock X4 10 Sec x 20 0C-100C Water Dip
<BR>Via Current X5 7 Days / 14 cycles @ 25C & 125C
<BR>
<BR>Below, I have outlined several questions so that I can attain a richer understanding of the intent, benefit and drawbacks of environmental stress testing:
<BR>
<BR>a. How would moisture absorption effect results of environmental stress testing?
<BR>b. How would soldermask adhesion be effected by environmental stress testing?
<BR>c. How is oxidation formed; is it a function of water absorption/environmental exposure?
<BR>d. What could cause via current test (the via are burnt and opened) after environmental stress testing?
<BR>e. If our product is not exposed to any harsh environmental conditions, what is the benefit for this type of testing?
<BR>
<BR>I would appreciate any and all comments and feedback all of you have to offer.
<BR>
<BR>Regards,
<BR></FONT></HTML>
--part1_23.18472e70.2986e1ab_boundary--
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Date: Mon, 28 Jan 2002 13:58:27 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
MIME-Version: 1.0
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boundary="part1_53.11adb3e5.2986f953_boundary"
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So we're not the only one having trouble with the C vs. F on ovens .... what
does the coating manufacturer say, they can probably make the strongest
argument for use-as-is or rework.
Mike
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<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#ffffff"><FONT style="BACKGROUND-COLOR: #ffffff" SIZE=2>So we're not the only one having trouble with the C vs. F on ovens .... what does the coating manufacturer say, they can probably make the strongest argument for use-as-is or rework.<BR>
<BR>
Mike</FONT></HTML>
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Date: Mon, 28 Jan 2002 14:27:31 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: ODB++
MIME-Version: 1.0
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From: Paul M Fly
My employer is in the process of buying a couple seats of Valor. Naturally
the
question should we give our vendors ODB++ rather than Gerber came up. I
would
be very interested in hearing about some of your experiences in this
matter. In
particular I would like to hear from some fabricators. How many PCB fab
shops
really prefer ODB++? I did a quick look at our preferred vendors web site
and did not
find a word one way or the other.
Thanks,
************************************
Paul Fly
Eastman Kodak Company
Engineering Technology Center - PEDT
2nd Fl. Bld. 205 K.P.
2400 Mt. Read Blvd.
Rochester, New York 14650-3007
Phone: (716) 726-5670
Fax: (716) 726-0275
E-mail: [log in to unmask]
************************************
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Date: Mon, 28 Jan 2002 14:31:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Enviromental Stress Testing-----Benefits and Drawbacks
MIME-Version: 1.0
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Hi "Regards,"
First, we normally put names at the bottom of our messages.
You, in a message dated 01/28/2002 13:22:10, [log in to unmask] write:
>Being from purchasing, I have been asked to rationalize the inherent cost for
>demanding quality standards that my company now prescribes to.
>Below, I have outlined our company's test criteria for environmental stress
testing:
A: You do not tell us what the purpose of your "environmental stress testing"
is supposed to be; nor are you telling us on what units [proptotypes,
coupons, scrp samples, etc.] these tests are to be performed or any test
details; nor are you giving us any design details--consequently, it is very
difficult to say anything pertinent about your tests and your product. You
also do not tell us what the cryptic X1 through X5 means--number of cycles,
sequence?
>Panel Allocation Test Description
>Thermal Cycle -55C / 150C X1 15 Min x 2 x 100; Test PC boards
without components
>Humidity 85/85 X2 7 Days; Test complete units
>150C Bake X3 7 Days
>Hot Plate/ Oil Temp Shock X4 10 Sec x 20 0C-100C Water Dip
>Via Current X5 7 Days / 14 cycles @
25C & 125C
>
>Below, I have outlined several questions so that I can attain a richer
>understanding of the intent, benefit and drawbacks of environmental stress
testing:
>a. How would moisture absorption effect results of environmental stress
testing?
A: Which test?
>b. How would soldermask adhesion be effected by environmental stress
testing?
>c. How is oxidation formed; is it a function of water
absorption/environmental exposure?
>d. What could cause via current test (the via are burnt and opened) after
environmental stress testing?
A: not enough details.
>e. If our product is not exposed to any harsh environmental conditions, what
>is the benefit for this type of testing?
A: None.
Generally speaking, your tests are extreme--without stated details and
purposes general statements are meaningless.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Mon, 28 Jan 2002 13:35:37 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ODB++
X-To: [log in to unmask]
Paul,
As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.
By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.
Earl
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Date: Mon, 28 Jan 2002 16:11:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Decray <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Decray <[log in to unmask]>
Subject: Re: ODB++
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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HEY EARL I WOULD LIKE TO SEE THAT BEING A NEW USER OF VALOR
*GOD BLESS AMERICA*
William W. DeCray III
Waytec Electronics Corp
CAD/CAM & Engineering Services Manager
PHONE:(434) 237-6391 ext 115
CELL: (804) 851-6115
FAX: (434) 237-1324
E-mail:<[log in to unmask]>
Web http://www.waytec.com <http://www.waytec.com/>
FTP ftp://ftp.waytec.com <ftp://ftp.waytec.com/>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Monday, January 28, 2002 2:36 PM
To: [log in to unmask]
Subject: Re: [TN] ODB++
Paul,
As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.
By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.
Earl
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Date: Mon, 28 Jan 2002 15:28:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ODB++
X-To: [log in to unmask]
Bill and all,
I don't think this free offer will be in the proportions of the DFM/CE
checklist thing. If it is, we have a problem. I told a few folks I would try
shipping the stuff out via my work T1 line. However, the four files total
about 60 mb. If it doesn't work, you will have to send a self addressed,
stamped envelop and a blank CD so I can burn and return the files to you. I
don't know if Daan wants to put up with this again.
Earl
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Date: Mon, 28 Jan 2002 23:11:44 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: ODB++
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0010_01C1A851.271094E0"
This is a multi-part message in MIME format.
------=_NextPart_000_0010_01C1A851.271094E0
Content-Type: text/plain;
charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
I have another question about changing from Gerber to filetypes like =
ODB++ (or many other formats). How do you folks out there think about =
sending such data, which may include almost complete design information, =
to the outside world ? I mean with Gerber your stencil vendor or bare =
board vendor may learn some things about mechanical characteristics of =
your designs (so what ?), but isn't it a risk with formats like ODB++ =
that someone steals a major part of your design and your companies =
knowhow ?
Daan Terstegge
http://www.smtinfo.net =20
----- Original Message -----=20
From: Earl Moon=20
To: [log in to unmask]
Sent: Monday, January 28, 2002 8:35 PM
Subject: Re: [TN] ODB++
Paul,
As a thoroughly experienced and long time Valor user, first I can say =
it's a
great package though a bit tough to learn. Concerning ODB++, most all =
my fab
suppliers use the convention. CAM350 and most CAM packages also output =
ODB
as "smart" data instead of "dumb" Gerber.
By the way, I have a set of procedures that cut through the exhaustive =
Valor
documentation. When you're ready, I'll send them to you. Mostly they =
are
actual photos of nearly every screen used in the Valor program.
Earl
=
-------------------------------------------------------------------------=
--------
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1.8d
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in
the BODY (NOT the subject field): SIGNOFF Technet
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[log in to unmask]: SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700 ext.5315
=
-------------------------------------------------------------------------=
--------
------=_NextPart_000_0010_01C1A851.271094E0
Content-Type: text/html;
charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1252">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>I have another question about changing from Gerber =
to filetypes like=20
ODB++ (or many other formats). How do you folks out there =
think about=20
sending such data, which may include almost complete design =
information, to=20
the outside world ? I mean with Gerber your stencil vendor or bare board =
vendor may learn some things about mechanical characteristics =
of your=20
designs (so what ?), but isn't it a risk with formats =
like=20
ODB++ that someone steals a major part of your=20
design and your companies knowhow ?</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A> </D=
IV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, January 28, 2002 =
8:35=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
<DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long time =
Valor=20
user, first I can say it's a<BR>great package though a bit tough to =
learn.=20
Concerning ODB++, most all my fab<BR>suppliers use the convention. =
CAM350 and=20
most CAM packages also output ODB<BR>as "smart" data instead of "dumb" =
Gerber.<BR><BR>By the way, I have a set of procedures that cut through =
the=20
exhaustive Valor<BR>documentation. When you're ready, I'll send them =
to you.=20
Mostly they are<BR>actual photos of nearly every screen used in the =
Valor=20
=
program.<BR><BR><BR>Earl<BR><BR>-----------------------------------------=
----------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
text=20
in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To =
temporarily halt=20
delivery of Technet send e-mail to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet =
NOMAIL<BR>To=20
receive ONE mailing per day of all the posts: send e-mail to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
Digest<BR>Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
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Date: Mon, 28 Jan 2002 14:09:28 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Steele <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Steele <[log in to unmask]>
Subject: Re: ODB++
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Paul,
I work for Toppan Electronics in San Diego, we are a
fab house.
We strongly prefer ODB data. I tell our Sales people
to beg for it!
For the past 2 years we have tracked type of data
(274D, 274X and ODB) and problems with that data such
as bad aperture lists, missing layers, incorrect
filename identification, etc, etc, etc.
For example, for the last 226 jobs we have input we had
41 issues with gerber, 0 for ODB. That's a lot of phone
calls and time spent just getting the data INTO our Genesis
system. We allocate 5 min to get the data and import an
ODB job, 30-40 for gerber (sometimes it takes hours for
gerber, that happens about once a month...)
I realize not everyone uses Genesis as their CAM system, but
I would wager that a majority of the bigger fab houses do.
So, yes, PLEASE generate ODB as a first choice and only send
out gerber if asked too...
Of course that's just my opinion, I could be wrong...
Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]
>-----Original Message-----
>From: [log in to unmask] [mailto:[log in to unmask]]
>Sent: Monday, January 28, 2002 11:28 AM
>To: [log in to unmask]
>Subject: [TN] ODB++
>
>
>From: Paul M Fly
>
>My employer is in the process of buying a couple seats of
>Valor. Naturally
>the
>question should we give our vendors ODB++ rather than Gerber came up. I
>would
>be very interested in hearing about some of your experiences in this
>matter. In
>particular I would like to hear from some fabricators. How many PCB fab
>shops
>really prefer ODB++? I did a quick look at our preferred
>vendors web site
>and did not
>find a word one way or the other.
>
>Thanks,
>************************************
> Paul Fly
>
>Eastman Kodak Company
>Engineering Technology Center - PEDT
>2nd Fl. Bld. 205 K.P.
>2400 Mt. Read Blvd.
>Rochester, New York 14650-3007
>Phone: (716) 726-5670
>Fax: (716) 726-0275
>E-mail: [log in to unmask]
>************************************
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=========================================================================
Date: Mon, 28 Jan 2002 17:16:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kirk Kosel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kirk Kosel <[log in to unmask]>
Subject: Solder pot analysis
Mime-Version: 1.0
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Hi everyone.
Any chance that someone knows the analytical method used to test the =
solder in a HASL for impurities? If possible, I would like to do it =
in-house to save time and money. We have an ICP, which you'd think could =
check for copper and other impurities. Perhaps IPC has a standard =
procedure to go by? If so, tell me where to find it.
Thanks in advance for your help.
Kirk
--=_1E437AC4.0E6F0299
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>
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<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1>Hi everyone.</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Any chance that someone knows the analytical method =
used to=20
test the solder in a HASL for impurities? If possible, I would like =
to do=20
it in-house to save time and money. We have an ICP, which you'd =
think=20
could check for copper and other impurities. Perhaps IPC has a =
standard=20
procedure to go by? If so, tell me where to find it.</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Thanks in advance for your help.</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Kirk</FONT></DIV></BODY></HTML>
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Date: Mon, 28 Jan 2002 17:48:50 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: "Marsico, James" <[log in to unmask]>
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Jim,
You have chemically altered the polymer. It will no longer perform it's designed function.
David A. Douthit
Manager
LoCan LLC
"Marsico, James" wrote:
> Help! Emergency!
>
> We have a completed assembly (top assembly with many boards, hybrids, etc.)
> ready for shipment to our customer (space product). The last operation was
> to ink mark a S/N. The ink is cured at 150 F for 2 hours. The assembly was
> put in an oven at 150 C for two hours. After hours of reviewing all of the
> materials and bill of material, component by component (component data,
> supplier phone calls, etc.), the only item that is not rated for 150 C is
> the polyurethane conformal coating, which turned yellow/brown in color. Can
> anyone explain what actually happened to the coating and if it can be used
> as is?
>
> Thanks,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
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Date: Mon, 28 Jan 2002 18:06:13 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Enviromental Stress Testing-----Benefits and Drawbacks
X-To: [log in to unmask]
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Werner,
This looks like something someone "made up" without any reasoning to it.
David A. Douthit
Manager
LoCan LLC
[log in to unmask] wrote:
> Hi "Regards,"
> First, we normally put names at the bottom of our messages.
> You, in a message dated 01/28/2002 13:22:10, [log in to unmask] write:
> >Being from purchasing, I have been asked to rationalize the inherent cost for
> >demanding quality standards that my company now prescribes to.
> >Below, I have outlined our company's test criteria for environmental stress
> testing:
> A: You do not tell us what the purpose of your "environmental stress testing"
> is supposed to be; nor are you telling us on what units [proptotypes,
> coupons, scrp samples, etc.] these tests are to be performed or any test
> details; nor are you giving us any design details--consequently, it is very
> difficult to say anything pertinent about your tests and your product. You
> also do not tell us what the cryptic X1 through X5 means--number of cycles,
> sequence?
>
> >Panel Allocation Test Description
> >Thermal Cycle -55C / 150C X1 15 Min x 2 x 100; Test PC boards
> without components
> >Humidity 85/85 X2 7 Days; Test complete units
> >150C Bake X3 7 Days
> >Hot Plate/ Oil Temp Shock X4 10 Sec x 20 0C-100C Water Dip
> >Via Current X5 7 Days / 14 cycles @
> 25C & 125C
> >
> >Below, I have outlined several questions so that I can attain a richer
> >understanding of the intent, benefit and drawbacks of environmental stress
> testing:
> >a. How would moisture absorption effect results of environmental stress
> testing?
> A: Which test?
> >b. How would soldermask adhesion be effected by environmental stress
> testing?
> >c. How is oxidation formed; is it a function of water
> absorption/environmental exposure?
> >d. What could cause via current test (the via are burnt and opened) after
> environmental stress testing?
> A: not enough details.
> >e. If our product is not exposed to any harsh environmental conditions, what
> >is the benefit for this type of testing?
> A: None.
> Generally speaking, your tests are extreme--without stated details and
> purposes general statements are meaningless.
>
> Werner Engelmaier
> Engelmaier Associates, L.C.
> Electronic Packaging, Interconnection and Reliability Consulting
> 7 Jasmine Run
> Ormond Beach, FL 32174 USA
> Phone: 904-437-8747, Fax: 904-437-8737
> E-mail: [log in to unmask], Website: www.engelmaier.com
>
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Date: Mon, 28 Jan 2002 20:27:54 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ODB++
X-To: Mark Steele <[log in to unmask]>
In-Reply-To: <B136A0C653FCD311ABA400508B60DAB19C4BA6@EXCHANGE>
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Hi Mark,
From the design engineer's perspective, supporting two different formats
does create a problem. When you release a design to production, it is not
supposed to be specific to one particular vendor (unless you have a captive
fab shop and NEVER go outside). Unfortunately, not all fab shops support
ODB++. If purchasing would be willing to limit themselves to fab shops that
supported ODB++, that would be fine, but since that limits their options it
is unlikely. So in order to be universal, we would have to generate both
ODB++ and Gerber. This is easy to do but can create subtle problems that
could take lots of time and money to run down. The problem is how do you
insure that both sets of output data are identical in every way? While some
programs allow you to import both data sets and compare, as a practical
matter, assuring that they are identical is not possible. Since there will
undoubtedly be subtle differences between the two, which one controls?
Don't we also have to verify and validate both versions by building up both
assemblies? And when problems inevitably arise between boards from two
different vendors using different data files, who 'ya gonna call? Those
dumb design engineers who created the problem, of course.
I don't doubt for an instant that ODB++ saves fabricators time and money.
Do we as customers get a significant discount for making the fabricators job
easier with this superior data format? I've asked several fabricators and
no one has agreed yet. This is the part I don't get. Since it will
increase the cost of design to support dual formats for every job, we'd be
irresponsible to do this without concomitant savings. If you really want to
make any of the competing Gerber replacements widely accepted, get a
significant number of fabricators to offer a discount for designs submitted
in that format. Things will take care of themselves very quickly after
that. Purchasing agents will be after designers to provide the new format,
designers will be after EDA vendors to generate the new format and
fabricators who don't support it will be forced to do so rapidly. But
please, just pick one. We don't need to experience the VHS vs. Beta
scenario again.
I would strongly recommend a format that is under the control of an industry
standards-making body rather than a single vendor to discourage
Microsoft-style abuse of competitors, but that is a separate issue. It's
clear that Gerber should be replaced with something smarter that saves us
ALL money, which would be a real win-win situation. But until it saves
money for the fabricators' customers, we'll all be stuck with Gerber and we
all lose.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mark Steele
> Sent: Monday, January 28, 2002 4:09 PM
> To: [log in to unmask]
> Subject: Re: [TN] ODB++
>
>
> Hi Paul,
>
>
> I work for Toppan Electronics in San Diego, we are a
> fab house.
>
> We strongly prefer ODB data. I tell our Sales people
> to beg for it!
>
> For the past 2 years we have tracked type of data
> (274D, 274X and ODB) and problems with that data such
> as bad aperture lists, missing layers, incorrect
> filename identification, etc, etc, etc.
>
> For example, for the last 226 jobs we have input we had
> 41 issues with gerber, 0 for ODB. That's a lot of phone
> calls and time spent just getting the data INTO our Genesis
> system. We allocate 5 min to get the data and import an
> ODB job, 30-40 for gerber (sometimes it takes hours for
> gerber, that happens about once a month...)
>
> I realize not everyone uses Genesis as their CAM system, but
> I would wager that a majority of the bigger fab houses do.
>
> So, yes, PLEASE generate ODB as a first choice and only send
> out gerber if asked too...
>
> Of course that's just my opinion, I could be wrong...
>
>
>
> Mark Steele
> CAM Automation Engineer
> Toppan Electronics, Inc.
> 858.695.2222
> [log in to unmask]
>
>
>
>
> >-----Original Message-----
> >From: [log in to unmask] [mailto:[log in to unmask]]
> >Sent: Monday, January 28, 2002 11:28 AM
> >To: [log in to unmask]
> >Subject: [TN] ODB++
> >
> >
> >From: Paul M Fly
> >
> >My employer is in the process of buying a couple seats of
> >Valor. Naturally
> >the
> >question should we give our vendors ODB++ rather than Gerber came up. I
> >would
> >be very interested in hearing about some of your experiences in this
> >matter. In
> >particular I would like to hear from some fabricators. How many PCB fab
> >shops
> >really prefer ODB++? I did a quick look at our preferred
> >vendors web site
> >and did not
> >find a word one way or the other.
> >
> >Thanks,
> >************************************
> > Paul Fly
> >
> >Eastman Kodak Company
> >Engineering Technology Center - PEDT
> >2nd Fl. Bld. 205 K.P.
> >2400 Mt. Read Blvd.
> >Rochester, New York 14650-3007
> >Phone: (716) 726-5670
> >Fax: (716) 726-0275
> >E-mail: [log in to unmask]
> >************************************
>
> ------------------------------------------------------------------
> ---------------
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Date: Tue, 29 Jan 2002 10:07:18 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Julian Coates <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Julian Coates <[log in to unmask]>
Subject: Re: ODB++
X-To: "D.Terstegge" <[log in to unmask]>
In-Reply-To: <001301c1a848$c64f9320$b9ce86c2@gompie>
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Hi Daan,
Depending on the software tool which produces the ODB++ data, the user can
select whether to take certain information out of the file before sending
the data to another company. For example, in general it is possible to
remove the netlist data, component layers etc., if required. To put it
another way, ODB++ can be used to define as much or as little of the product
as you want. Having said that, a bare-board vendor would not thank you for
removing the netlist!
Hope this helps,
Julian Coates
Valor
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of D.Terstegge
Sent: 28 January 2002 22:12
To: [log in to unmask]
Subject: Re: [TN] ODB++
I have another question about changing from Gerber to filetypes like ODB++
(or many other formats). How do you folks out there think about sending such
data, which may include almost complete design information, to the outside
world ? I mean with Gerber your stencil vendor or bare board vendor may
learn some things about mechanical characteristics of your designs (so what
?), but isn't it a risk with formats like ODB++ that someone steals a major
part of your design and your companies knowhow ?
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: Earl Moon
To: [log in to unmask]
Sent: Monday, January 28, 2002 8:35 PM
Subject: Re: [TN] ODB++
Paul,
As a thoroughly experienced and long time Valor user, first I can say
it's a
great package though a bit tough to learn. Concerning ODB++, most all my
fab
suppliers use the convention. CAM350 and most CAM packages also output
ODB
as "smart" data instead of "dumb" Gerber.
By the way, I have a set of procedures that cut through the exhaustive
Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.
Earl
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Hi=20
Daan,</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Depending on the software tool which produces the ODB++ data, =
the user=20
can select whether to take certain information out of the file before =
sending=20
the data to another company. For example, in general it is possible to =
remove=20
the netlist data, component layers etc., if required. To put it another =
way,=20
ODB++ can be used to define as much or as little of the product as you =
want.=20
Having said that, a bare-board vendor would not thank you for removing =
the=20
netlist!</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Hope=20
this helps,</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Julian=20
Coates</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Valor</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>D.Terstegge<BR><B>Sent:</B> 28=20
January 2002 22:12<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> =
Re: [TN]=20
ODB++<BR><BR></FONT></DIV>
<DIV>I have another question about changing from Gerber =
to filetypes like=20
ODB++ (or many other formats). How do you folks out there =
think=20
about sending such data, which may include almost complete design =
information, to the outside world ? I mean with Gerber your stencil =
vendor or=20
bare board vendor may learn some things about mechanical=20
characteristics of your designs (so what ?), but isn't it a =
risk=20
with formats like ODB++ that someone steals a major =
part of=20
your design and your companies knowhow ?</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A=20
=
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A> </D=
IV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, January 28, =
2002 8:35=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
<DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long =
time Valor=20
user, first I can say it's a<BR>great package though a bit tough to =
learn.=20
Concerning ODB++, most all my fab<BR>suppliers use the convention. =
CAM350=20
and most CAM packages also output ODB<BR>as "smart" data instead of =
"dumb"=20
Gerber.<BR><BR>By the way, I have a set of procedures that cut =
through the=20
exhaustive Valor<BR>documentation. When you're ready, I'll send them =
to you.=20
Mostly they are<BR>actual photos of nearly every screen used in the =
Valor=20
=
program.<BR><BR><BR>Earl<BR><BR>-----------------------------------------=
----------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
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href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
text=20
in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To =
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halt delivery of Technet send e-mail to <A=20
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NOMAIL<BR>To receive ONE mailing per day of all the posts: send =
e-mail to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
Digest<BR>Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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Date: Tue, 29 Jan 2002 07:25:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain
Thanks for the response, Dave, but could you elaborate? Will the
permeability be affected? How about the Modulus? Will the TCE change?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: David Douthit [SMTP:[log in to unmask]]
Sent: Monday, January 28, 2002 7:49 PM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating
Jim,
You have chemically altered the polymer. It will no longer perform
it's designed function.
David A. Douthit
Manager
LoCan LLC
"Marsico, James" wrote:
> Help! Emergency!
>
> We have a completed assembly (top assembly with many boards,
hybrids, etc.)
> ready for shipment to our customer (space product). The last
operation was
> to ink mark a S/N. The ink is cured at 150 F for 2 hours. The
assembly was
> put in an oven at 150 C for two hours. After hours of reviewing
all of the
> materials and bill of material, component by component (component
data,
> supplier phone calls, etc.), the only item that is not rated for
150 C is
> the polyurethane conformal coating, which turned yellow/brown in
color. Can
> anyone explain what actually happened to the coating and if it can
be used
> as is?
>
> Thanks,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>
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Date: Tue, 29 Jan 2002 06:55:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: HOW TO GET THE ODB ++ FILES
All those contacting me about the how to Valor destructions I believe may
now download them from Seth's FTP site. I hope this is true and the reason
I'm posting here is my email has gone down in flames.
If you do get the files, Section one was, of course, the first written and
was a little rough at the edges. The subsequent three sections smoothed out
a bit. If you have any questions, email me.
If Julian is looking in out there, I would like to talk with you via email.
I have my laptop setup here and don't have your contact information with me.
Thanks all,
Earl
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Date: Tue, 29 Jan 2002 08:57:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Legend Inks
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Good morning all,
I am dutifully trying to finish many action items from the recent IPC
meetings at Apex. The solder mask task group, chaired by Roger Landolt,
Enthone, has been asked to address the issues of legend and marking inks
that go on solder masks. At the Fall meeting (2001) in Orlando, there was
support for forming a small task group focused on Legend Inks, though no
one stepped forward to volunteer to lead the effort, unfortunately.
So, I ask this august group, are there individuals out there who would like
to participate in such an activity and more importantly, is there someone
out there who would LEAD such an activity.
If you have not had the opportunity to lead an IPC task group, I would tell
you from my own experience that it is very rewarding. If you have travel
restrictions, as most of us do now, more and more work is being done
electronically with no travel.
If you have an interest or questions, please respond to either myself
([log in to unmask]), Roger Landolt ([log in to unmask]), or
Cassandra Cummings( [log in to unmask]).
Doug Pauls
Rockwell Collins
Vice Chair, Solder Mask Task Group
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Date: Tue, 29 Jan 2002 15:22:40 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Solder pot analysis
X-To: Kirk Kosel <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Usually Wet chemical or gravimetric for tin, spectrograph for impurities. or
spectrograph for everything.
However I would think you could set up a deal with your bar supplier which
would include a number of free analyses if you get replenishment and
exchange solder from them.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kirk Kosel
Sent: Monday, January 28, 2002 11:16 PM
To: [log in to unmask]
Subject: [TN] Solder pot analysis
Hi everyone.
Any chance that someone knows the analytical method used to test the
solder in a HASL for impurities? If possible, I would like to do it
in-house to save time and money. We have an ICP, which you'd think could
check for copper and other impurities. Perhaps IPC has a standard procedure
to go by? If so, tell me where to find it.
Thanks in advance for your help.
Kirk
------=_NextPart_000_0041_01C1A8D8.CAED82D0
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charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><SPAN class=3D670201615-29012002><FONT face=3DArial color=3D#0000ff =
size=3D3>Usually Wet chemical or gravimetric for tin, spectrograph for =
impurities.=20
or spectrograph for everything.</FONT></SPAN></DIV>
<DIV><SPAN class=3D670201615-29012002><FONT face=3DArial color=3D#0000ff =
size=3D3>However I would think you could set up a deal with your =
bar supplier=20
which would include a number of free analyses if you get =
replenishment and exchange solder from them. </FONT></SPAN></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D3></FONT> </DIV>
<DIV><FONT size=3D3><FONT face=3DArial color=3D#0000ff>Kind Regards=20
</FONT></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D3></FONT> </DIV>
<DIV><FONT size=3D3><FONT size=3D1><FONT face=3DArial><FONT =
color=3D#0000ff><FONT=20
size=3D3>Mik<SPAN class=3D670201615-29012002>e=20
Fenner</SPAN></FONT></FONT></FONT></FONT> </FONT></DIV>
<P><FONT size=3D3><FONT face=3DArial color=3D#0000ff>Applications =
Engineer, European=20
Operations</FONT> <BR><B><FONT face=3DArial color=3D#0000ff>Indium=20
Corporation</FONT></B> <BR><FONT face=3DArial color=3D#0000ff> T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial color=3D#0000ff>M: + 44 7810 526 =
317</FONT>=20
<BR><FONT face=3DArial color=3D#0000ff> F: + 44 1908 580 411</FONT> =
<BR><FONT=20
face=3DArial color=3D#0000ff> E: [log in to unmask]</FONT> =
<BR><FONT face=3DArial=20
color=3D#0000ff>W:<U> www.indium.com</U> </FONT><BR><FONT =
face=3DArial=20
color=3D#0000ff>Leadfree:</FONT><U> <FONT face=3DArial=20
color=3D#0000ff>www.Pb-Free.com</FONT></U> </FONT></P>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D3>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Kirk Kosel<BR><B>Sent:</B> =
Monday,=20
January 28, 2002 11:16 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B>=20
[TN] Solder pot analysis<BR><BR></FONT></DIV>
<DIV><FONT size=3D3>Hi everyone.</FONT></DIV>
<DIV><FONT size=3D3></FONT> </DIV>
<DIV><FONT size=3D3>Any chance that someone knows the analytical =
method used to=20
test the solder in a HASL for impurities? If possible, I would =
like to=20
do it in-house to save time and money. We have an ICP, which =
you'd think=20
could check for copper and other impurities. Perhaps IPC has a =
standard=20
procedure to go by? If so, tell me where to find =
it.</FONT></DIV>
<DIV><FONT size=3D3></FONT> </DIV>
<DIV><FONT size=3D3>Thanks in advance for your help.</FONT></DIV>
<DIV><FONT size=3D3></FONT> </DIV>
<DIV><FONT size=3D3>Kirk</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0041_01C1A8D8.CAED82D0--
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Date: Tue, 29 Jan 2002 09:33:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kirk Kosel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kirk Kosel <[log in to unmask]>
Subject: Re: Solder pot analysis
X-To: [log in to unmask]
Mime-Version: 1.0
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Thanks for the responses. One more question, any idea on how to get the =
solder (and impurities) in solution for ICP analysis? =20
Thanks again for your help,
Kirk
--=_257842E7.51305E38
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>
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<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1></FONT>Thanks for the responses. One more =
question, any=20
idea on how to get the solder (and impurities) in solution for ICP=20
analysis? </DIV>
<DIV> </DIV>
<DIV>Thanks again for your help,</DIV>
<DIV> </DIV>
<DIV>Kirk<FONT face=3D"MS Sans Serif" size=3D1></DIV></FONT></BODY></HTML>
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Date: Tue, 29 Jan 2002 10:37:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Whittaker, Dewey (AZ75)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Subject: Re: Legend Inks
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Doug,
How are you?
We don't mark over solder masks.We mark first and then cover in some
cases,but in most cases we leave a keep-out area for marking.I am moving
toward having a standard defined keep-out area in the solder mask where a
label will be placed in lieu of the standard marking inks.I will help all I
can on this,if you think it will help.
Dewey
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Tuesday, January 29, 2002 7:57 AM
> To: [log in to unmask]
> Subject: [TN] Legend Inks
>
> Good morning all,
>
> I am dutifully trying to finish many action items from the recent IPC
> meetings at Apex. The solder mask task group, chaired by Roger Landolt,
> Enthone, has been asked to address the issues of legend and marking inks
> that go on solder masks. At the Fall meeting (2001) in Orlando, there was
> support for forming a small task group focused on Legend Inks, though no
> one stepped forward to volunteer to lead the effort, unfortunately.
>
> So, I ask this august group, are there individuals out there who would
> like
> to participate in such an activity and more importantly, is there someone
> out there who would LEAD such an activity.
>
> If you have not had the opportunity to lead an IPC task group, I would
> tell
> you from my own experience that it is very rewarding. If you have travel
> restrictions, as most of us do now, more and more work is being done
> electronically with no travel.
>
> If you have an interest or questions, please respond to either myself
> ([log in to unmask]), Roger Landolt ([log in to unmask]), or
> Cassandra Cummings( [log in to unmask]).
>
> Doug Pauls
> Rockwell Collins
> Vice Chair, Solder Mask Task Group
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> --------------------------------------------------------------------------
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Date: Tue, 29 Jan 2002 09:57:43 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Steele <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Steele <[log in to unmask]>
Subject: Re: ODB++
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Hi Daan,
I agree with Julian. We as a fab house have no use for some of the data
that comes along with the ODB data. Sometimes this even creates problems.
We would prefer our customers to delete their component layers, forms,
checklists
and temp layers (but please leave in the netlist!). Although I and some CAM
operators
sometimes take a look at the forms that come in with some jobs (I've even
learned a
thing or two) we would prefer not to have them.
Now if there was an established collaboration and coordination between us,
we
COULD use the customers forms and checklists as part of a larger process.
This
seems to be on the horizon for us at Toppan.
Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]
-----Original Message-----
From: Julian Coates [mailto:[log in to unmask]]
Sent: Tuesday, January 29, 2002 2:07 AM
To: [log in to unmask]
Subject: Re: [TN] ODB++
Hi Daan,
Depending on the software tool which produces the ODB++ data, the user can
select whether to take certain information out of the file before sending
the data to another company. For example, in general it is possible to
remove the netlist data, component layers etc., if required. To put it
another way, ODB++ can be used to define as much or as little of the product
as you want. Having said that, a bare-board vendor would not thank you for
removing the netlist!
Hope this helps,
Julian Coates
Valor
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of D.Terstegge
Sent: 28 January 2002 22:12
To: [log in to unmask]
Subject: Re: [TN] ODB++
I have another question about changing from Gerber to filetypes like ODB++
(or many other formats). How do you folks out there think about sending such
data, which may include almost complete design information, to the outside
world ? I mean with Gerber your stencil vendor or bare board vendor may
learn some things about mechanical characteristics of your designs (so what
?), but isn't it a risk with formats like ODB++ that someone steals a major
part of your design and your companies knowhow ?
Daan Terstegge
http://www.smtinfo.net <http://www.smtinfo.net>
----- Original Message -----
From: Earl Moon <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, January 28, 2002 8:35 PM
Subject: Re: [TN] ODB++
Paul,
As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.
By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.
Earl
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<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>Hi
Daan,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>I agree
with Julian. We as a fab house have no use for some of the data
</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>that comes
along with the ODB data. Sometimes this even creates
problems.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>We would
prefer our customers to delete their component layers, forms,
checklists</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>and temp
layers </SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>(but please leave in the netlist!). Although I and some
CAM operators</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>sometimes
</SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>take a look at the forms that come in with some jobs
(I've even learned a </SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>thing or
</SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>two) we would prefer not to have
them.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>Now if
there was an established collaboration and coordination between us,
we</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>COULD use the customers forms and checklists as
part of a larger process. This</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>seems to
be on the horizon for us at Toppan.</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><BR>
<P><FONT face=Arial size=2>Mark Steele</FONT> <BR><FONT face=Arial size=2>CAM
Automation Engineer</FONT> <BR><B><I><FONT face="Times New Roman" size=2>Toppan
Electronics, Inc.</FONT></I></B> <BR><FONT face=Arial size=2>858.695.2222</FONT>
<BR><FONT face=Arial size=2>[log in to unmask]</FONT> </P></DIV>
<DIV> </DIV>
<BLOCKQUOTE dir=ltr
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Julian Coates
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, January 29, 2002 2:07
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
ODB++<BR><BR></DIV></FONT>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial size=2>Hi
Daan,</FONT></SPAN></DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2>Depending on the software tool which produces the ODB++ data, the user
can select whether to take certain information out of the file before sending
the data to another company. For example, in general it is possible to remove
the netlist data, component layers etc., if required. To put it another way,
ODB++ can be used to define as much or as little of the product as you want.
Having said that, a bare-board vendor would not thank you for removing the
netlist!</FONT></SPAN></DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial size=2>Hope
this helps,</FONT></SPAN></DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2>Julian Coates</FONT></SPAN></DIV>
<DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
size=2>Valor</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>D.Terstegge<BR><B>Sent:</B> 28
January 2002 22:12<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
ODB++<BR><BR></FONT></DIV>
<DIV>I have another question about changing from Gerber to filetypes
like ODB++ (or many other formats). How do you folks out there
think about sending such data, which may include almost complete design
information, to the outside world ? I mean with Gerber your stencil vendor
or bare board vendor may learn some things about mechanical
characteristics of your designs (so what ?), but isn't it a risk
with formats like ODB++ that someone steals a major part of
your design and your companies knowhow ?</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A
href="http://www.smtinfo.net">http://www.smtinfo.net</A> </DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Earl Moon</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, January 28, 2002 8:35
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
<DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long time
Valor user, first I can say it's a<BR>great package though a bit tough to
learn. Concerning ODB++, most all my fab<BR>suppliers use the convention.
CAM350 and most CAM packages also output ODB<BR>as "smart" data instead of
"dumb" Gerber.<BR><BR>By the way, I have a set of procedures that cut
through the exhaustive Valor<BR>documentation. When you're ready, I'll
send them to you. Mostly they are<BR>actual photos of nearly every screen
used in the Valor
program.<BR><BR><BR>Earl<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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Date: Tue, 29 Jan 2002 12:15:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Stern <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Stern <[log in to unmask]>
Subject: Re: Solder pot analysis
X-To: Kirk Kosel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Kirk:
It has been some time since performing this test, but if memory serves
tin is measured chemically by ASTM E46; impurities (including copper,
gold, cadmium, zinc, aluminum, antimony, iron, arsenic, bismuth, silver,
and nickel), are measured spectrometrically (AA) by ASTM E663; and lead
is reported as the "balance".
I am unsure of the ASTM designation for ICP determination, but the
general digestion method described in E663 may be the same for ICP. If
silver is being determined, keep in mind aqua regia (HCl/HNO(3)) cannot
be employed as to dissolve the sample.
As previously mentioned, your current solder supplier should perform
this test for you AND provide you a copy of the method employed.
Regards,
Ted Stern
Kirk Kosel wrote:
> Thanks for the responses. One more question, any idea on how to get
> the solder (and impurities) in solution for ICP analysis? Thanks again
> for your help, Kirk
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Date: Tue, 29 Jan 2002 13:10:41 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: ODB FILES ON SETH'S FTP SITE
For all you folks wanting my Valor destructions, my new best friend Seth
Goodman has set up a site and I think I was able to copy the files there.
Also included is a small presentation used to justify, to management, the
investment in the product.
The following is how to get the files:
log into ftp.GoodmanAssociates.com
Tell your users to log into the same site anonymously. They will see a
directory called "Earl's files" that contain all your stuff. They can then
download to their heart's content.
Let me know if you get the files successfully,
Earl
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Date: Tue, 29 Jan 2002 16:10:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Test Coupons
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi To All
I am stumped - where are the words that say "if a coupon from a panel fails
to meet the specification requirements - all associated boards from that
panel are rejected"?
I know it, but I sure can't find it.
Thanks
Susan Mansilla
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Date: Tue, 29 Jan 2002 15:00:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Doug Pogatetz <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Doug Pogatetz <[log in to unmask]>
Subject: Minimum bend radius calculation in a flex circuit
I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.
I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?
Thanks.
Doug
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Date: Tue, 29 Jan 2002 14:37:58 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Whittaker, Dewey (AZ75)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Subject: Re: Minimum bend radius calculation in a flex circuit
X-To: Doug Pogatetz <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
A starting rule is 12 times the thickness.
Dewey
> -----Original Message-----
> From: Doug Pogatetz [SMTP:[log in to unmask]]
> Sent: Tuesday, January 29, 2002 2:00 PM
> To: [log in to unmask]
> Subject: [TN] Minimum bend radius calculation in a flex circuit
>
> I am on project that requires that I determine the minimum bend radius of
> a
> flex circuit. I have not been able to find out any formulas or
> calculations
> to help out.
>
> I am a mechanical design engineer, so I am not up on all the terminology.
> It will of the class "Flex to Install", and will be of the adhesiveless
> type. Can anyone help out?
>
> Thanks.
>
> Doug
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
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Date: Tue, 29 Jan 2002 15:59:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Test Coupons
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_3D605B25.4928454C"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_3D605B25.4928454C
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
Check out IPC-RB-276 section 4.6.2.2 Acceptance
Kathy=20
--=_3D605B25.4928454C
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Check out IPC-RB-276 section 4.6.2.2 Acceptance</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Tue, 29 Jan 2002 18:01:27 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Minimum bend radius calculation in a flex circuit
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_35.2140995d.298883c7_boundary"
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Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hello Doug,
The answer depends on the construction and the materials used. 1 metal
layer?, 2? ... or more? Also the thickness of the structure and of the
copper must be accounted for. The smaller the bend radius the greater the
strain and the higher the elongation requirement of the copper. If you need a
very small bend radius, very thin, ductile copper and thin polymer films are
best.
Long standing rules of thumb for 35 micron copper and 25 micron base films
and coverlayers have been:
3-6 times the thickness for single metal layer with coverlayer
6-10 X for 2 metal layers with coverlayers
15 to 20 or more times the thickness for bonded multilayers (Again this is
highly construction dependent.)
Use of a forming mandrel is a good idea if you are getting close ot the limits
Finite element modeling is useful to get a sense of the limits. Simple 2D
models will likely serve.
Keep in mind that shock and vibration can make your static design into a
dynamic one.
Kind regards,
Joe
--part1_35.2140995d.298883c7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Doug,
<BR>
<BR>The answer depends on the construction and the materials used. 1 metal layer?, 2? ... or more? Also the thickness of the structure and of the copper must be accounted for. The smaller the bend radius the greater the strain and the higher the elongation requirement of the copper. If you need a very small bend radius, very thin, ductile copper and thin polymer films are best.
<BR>
<BR>Long standing rules of thumb for 35 micron copper and 25 micron base films and coverlayers have been:
<BR>
<BR>3-6 times the thickness for single metal layer with coverlayer
<BR>
<BR>6-10 X for 2 metal layers with coverlayers
<BR>
<BR>15 to 20 or more times the thickness for bonded multilayers (Again this is highly construction dependent.)
<BR>
<BR>Use of a forming mandrel is a good idea if you are getting close ot the limits
<BR>
<BR>Finite element modeling is useful to get a sense of the limits. Simple 2D models will likely serve.
<BR>
<BR>Keep in mind that shock and vibration can make your static design into a dynamic one.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>
--part1_35.2140995d.298883c7_boundary--
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Date: Tue, 29 Jan 2002 17:11:24 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: "Marsico, James" <[log in to unmask]>
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Jim,
Unless you are willing to spend a lot of money to test all these factors all you can say is yes to your
questions.
There is no definitive answer as to "how much" the coating has been "affected".
You have more than likely greatly exceeded the Tg of the coating. At that point all bets are off!
Trying to "certify" these boards without extensive testing would be risky at best.
David A. Douthit
manager
LoCan LLC
"Marsico, James" wrote:
> Thanks for the response, Dave, but could you elaborate? Will the
> permeability be affected? How about the Modulus? Will the TCE change?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> -----Original Message-----
> From: David Douthit [SMTP:[log in to unmask]]
> Sent: Monday, January 28, 2002 7:49 PM
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
> Jim,
>
> You have chemically altered the polymer. It will no longer perform
> it's designed function.
>
> David A. Douthit
> Manager
> LoCan LLC
>
> "Marsico, James" wrote:
>
> > Help! Emergency!
> >
> > We have a completed assembly (top assembly with many boards,
> hybrids, etc.)
> > ready for shipment to our customer (space product). The last
> operation was
> > to ink mark a S/N. The ink is cured at 150 F for 2 hours. The
> assembly was
> > put in an oven at 150 C for two hours. After hours of reviewing
> all of the
> > materials and bill of material, component by component (component
> data,
> > supplier phone calls, etc.), the only item that is not rated for
> 150 C is
> > the polyurethane conformal coating, which turned yellow/brown in
> color. Can
> > anyone explain what actually happened to the coating and if it can
> be used
> > as is?
> >
> > Thanks,
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
> ----------------------------------------------------------------------------
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Date: Wed, 30 Jan 2002 08:37:00 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Enviromental Stress Testing-----Benefits and Drawbacks
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I am taking it that the testing you detailed is a one-off qualification
test and not normal Environmental Stress Screening (ESS), which is done for
each production run?
Environmental Qualification Test (EQT) is designed to prove through
accelerated aging, that your product will function reliably throughout its
intended lifespan in its normal operating environment. ESS is a mini
version of this to weed out any early life failures in conjunction with a
burn-in programme, but should not significantly shorten the life of the
survivors.
To comment on your questions:
a) Moisture absorbtion/transpiration is a natural part of boards and board
assemblies. To try to eliminate it in, or for, environmental testing will
provide a false result, unless that elimination is required in order to
match the intended operating environment of the finished product.
b) If you (or your fab house) has chosen the correct soldermask & hardener
for your application, mask adhesion must be unaffected by the the testing
or your product will have failed the test.
c) Oxidation is formed in the presense of oxygen (air) and moisture. The
degree of oxidation depends on exposure to these factors and also
temperature. Better chemists than I can explain this better, or you can
trawl the TechNet archives for more info. There was a sizeable thread on
oxidation (a.k.a. rust, tarnish, etc).
d) Did the burning to your vias occur during bare board testing or to the
finished assembly? Was the board under power at the time? If the board was
under power during temperature cycling, and it wasn't conformally coated,
then you've probably had a short circuit at the 'dew point', when any
moisture in the chamber air surrounding the boards has condensed onto the
board surface and given you a conductive path you didn't intend. Was the
via a power via?
e) If your product is not to be exposed to any harsh environment (extremes
of temperature, dust abrasion, salty air, vibration, shock, chemicals,
high/low pressures, and so on), then the degree of testing being carried
out is excessive. I wouldn't say unnecessary, because some form of EQT
and/or ESS is useful for product reliability. I'll re-state what I said at
the beginning of this response - the tests must be designed to prove that
your product will function reliably throughout its intended lifespan in its
normal operating environment.
Hope this helps a bit.
Peter Duncan
CircuitekAsia
@AOL.COM To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Enviromental Stress
ORG> Testing-----Benefits and Drawbacks
01/29/02
01:17 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
CircuitekAsia
To All Technetters,
Being from purchasing, I have been asked to rationalize the inherent cost
for demanding quality standards that my company now prescribes to.
Below, I have outlined our company's test criteria for environmental stress
testing:
Panel Allocation Test Description
Thermal Cycle -55C / 150C X1 15 Min x 2 x 100; Test PC boards without
components
Humidity 85/85 X2 7 Days; Test complete units
150C Bake X3 7 Days
Hot Plate/ Oil Temp Shock X4 10 Sec x 20 0C-100C Water Dip
Via Current X5 7 Days / 14 cycles @ 25C & 125C
Below, I have outlined several questions so that I can attain a richer
understanding of the intent, benefit and drawbacks of environmental stress
testing:
a. How would moisture absorption effect results of environmental stress
testing?
b. How would soldermask adhesion be effected by environmental stress
testing?
c. How is oxidation formed; is it a function of water
absorption/environmental exposure?
d. What could cause via current test (the via are burnt and opened) after
environmental stress testing?
e. If our product is not exposed to any harsh environmental conditions,
what is the benefit for this type of testing?
I would appreciate any and all comments and feedback all of you have to
offer.
Regards,
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Wed, 30 Jan 2002 02:09:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Adam Seychell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Adam Seychell <[log in to unmask]>
Subject: pulse plating - without additives
Hello platers. I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.
Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.
A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:
forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2
The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?
If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.
regards,
Adam Seychell.
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Date: Wed, 30 Jan 2002 09:44:19 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Minimum bend radius calculation in a flex circuit
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Doug,
You don't say whether the bend is a permanent, once only bend or a dynamic bend.
If it's a once only then that's dead easy for a mechanical engineer to calculate. Figure out where the
neutral axis is going to be (probably the outside of the coverlay on the inside of the bend) and from
there work out the strain on the copper. Then you have to figure out what the allowable strain is. For
rolled annealed (you'll have to ask the manufacturer) my unreliable memory tells me 10% is a
conservative figure.
If the flex is undergoing dynamic bending then the problem is one of fatigue. So in this case bend
radius (= stress) and number of cycles are both important. Generally it's regarded as a bad idea to
subject multilayer flexes to dynamic bending. For a single layer a rule of thumb is minimum bend radius
> 20 X thickness.
There are also a number of good design guides on the web whose addresses alas, I have also forgotten.
However you could start by looking for a flex manufacturer called Rogers I vaguely remember they had
some good stuff.
Hope this helps,
[log in to unmask] wrote:
> I am on project that requires that I determine the minimum bend radius of a
> flex circuit. I have not been able to find out any formulas or calculations
> to help out.
>
> I am a mechanical design engineer, so I am not up on all the terminology.
> It will of the class "Flex to Install", and will be of the adhesiveless
> type. Can anyone help out?
>
> Thanks.
>
> Doug
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Wed, 30 Jan 2002 07:47:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Robert Peterson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Robert Peterson <[log in to unmask]>
Subject: Re: pulse plating - without additives
X-To: Adam Seychell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html
Hope this helps
Bob Peterson
Alternate Final Finishes, Inc.
-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives
Hello platers. I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.
Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.
A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:
forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2
The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?
If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.
regards,
Adam Seychell.
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Date: Wed, 30 Jan 2002 08:36:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Minimum bend radius calculation in a flex circuit
X-To: Doug Pogatetz <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
General rule is 10 to 12 times the thickness of the circuit. This rule holds
well for most circuits up to 4 layers. For simple flex to install you can
actually crease the circuit as long as it is not creased and uncreased in
the engineering phase.
Regards Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Doug Pogatetz
Sent: Tuesday, January 29, 2002 4:00 PM
To: [log in to unmask]
Subject: [TN] Minimum bend radius calculation in a flex circuit
I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.
I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?
Thanks.
Doug
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Date: Wed, 30 Jan 2002 08:28:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Afri Singh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Afri Singh <[log in to unmask]>
Subject: Re: Black color thin laminates
X-To: Eric Christison <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Try Electroply in California
-----Original Message-----
From: Eric Christison [mailto:[log in to unmask]]
Sent: Monday, January 28, 2002 6:44 AM
To: [log in to unmask]
Subject: Re: [TN] Black color thin laminates
I'd be interested too....................
[log in to unmask] wrote:
> mighty grateful if u can send me offline contacts for manufacturers of
> black color base copper clad laminate - G-10 - thin laminates of 0.4mm
> and lesser.ThanksAnil Kher
>
> micro interconnexion pvt. ltd.
> D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India -
> 403110
> Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
> E-mail :- [log in to unmask]
> LEADERS IN GOLD PLATED PCBS
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Wed, 30 Jan 2002 13:48:28 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Olivia Mc Dermott <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Olivia Mc Dermott <[log in to unmask]>
Subject: Flux residue with a no-clean process
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Is it OK to have flux residue on assemblies when the process is no clean. We
have assemblies that are failing in the field and the customer thinks this
flux residue may be an issue. They think the assembly has been wet.
What do you think???? All help appreciated.
_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail.
http://www.hotmail.com
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Date: Wed, 30 Jan 2002 08:50:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: Re: Test Coupons
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="Windows-1252"
Content-Transfer-Encoding: 7bit
Susan,
MIL-PRF-55110, section 3.1 only verified compliant boards
also A4.6.1.3 and A4.6.2.3, is that what you were looking for?
Joe
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Tuesday, January 29, 2002 4:11 PM
To: [log in to unmask]
Subject: [TN] Test Coupons
Hi To All
I am stumped - where are the words that say "if a coupon from a panel fails
to meet the specification requirements - all associated boards from that
panel are rejected"?
I know it, but I sure can't find it.
Thanks
Susan Mansilla
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Date: Wed, 30 Jan 2002 09:10:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: TBGA
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Engineering here is looking at a TBGA600 for a project (tape ball grid
array). We have been working with PBGAs for years, but I am not familiar
with a TBGA. Is there anything unique about the TBGA as far as processing on
the assembly line as opposed to a PBGA? The package size is 40mm square and
1.55mm high, .75mm dia. balls on 1.27mm centers.
Thanks,
Bob
==========================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
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Date: Wed, 30 Jan 2002 08:19:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
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From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
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IPC-610 has no-clean residues as acceptable. Is it possible that flux may =
have been mixed with a washable? Washing a no-clean off is more detrimenta=
l than leaving it alone. =20
Is the assembly conformally coated? Is the application intended to be in =
a wet or high humidity/moisture enviroment?
Kathy=20
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<DIV>IPC-610 has no-clean residues as acceptable. Is it possible that flux
may have been mixed with a washable? Washing a no-clean off is more
detrimental than leaving it alone. </DIV>
<DIV> </DIV>
<DIV>Is the assembly conformally coated? Is the application intended to be
in a wet or high humidity/moisture enviroment?</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 30 Jan 2002 15:15:30 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
=?ISO-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
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From: =?ISO-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
Subject: Re: pulse plating - without additives
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Adam,
You may also be inspired by this article:
http://www.circuitree.com/CDA/ArticleInformation/features/BNP__Features__Ite
m/0,2133,24954,00.html
regards
Torben Oesteraa
Printca AS
-----Original Message-----
From: Robert Peterson [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 1:47 PM
To: [log in to unmask]
Subject: Re: [TN] pulse plating - without additives
Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html
Hope this helps
Bob Peterson
Alternate Final Finishes, Inc.
-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives
Hello platers. I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.
Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.
A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:
forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2
The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?
If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.
regards,
Adam Seychell.
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Date: Wed, 30 Jan 2002 09:32:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: TBGA
X-To: bbarr <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Been placing and convection reflowing these (along with the PBGA's ) for
over 2 years with no change to my profiles.
-----Original Message-----
From: bbarr [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 9:10 AM
To: [log in to unmask]
Subject: [TN] TBGA
Engineering here is looking at a TBGA600 for a project (tape ball grid
array). We have been working with PBGAs for years, but I am not familiar
with a TBGA. Is there anything unique about the TBGA as far as processing on
the assembly line as opposed to a PBGA? The package size is 40mm square and
1.55mm high, .75mm dia. balls on 1.27mm centers.
Thanks,
Bob
==========================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
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Date: Wed, 30 Jan 2002 14:41:39 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Olivia Mc Dermott <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Olivia Mc Dermott <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
Mime-Version: 1.0
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Kathy,
The assembly is not conformally coated. It is a meter display in which we
build the PCB and then box build & system test. It is for distribution
around the UK.
>From: Kathy Kuhlow <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, Kathy Kuhlow
><[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Flux residue with a no-clean process
>Date: Wed, 30 Jan 2002 08:19:46 -0600
>
>IPC-610 has no-clean residues as acceptable. Is it possible that flux may
>have been mixed with a washable? Washing a no-clean off is more
>detrimental than leaving it alone.
>
>Is the assembly conformally coated? Is the application intended to be in a
>wet or high humidity/moisture enviroment?
>
>Kathy
><< TEXT.htm >>
_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail.
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Date: Wed, 30 Jan 2002 16:05:36 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flux residue with a no-clean process
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Kathy,
I am very interested in this as we have the following processes:
1. No clean smt - no clean wave solder - saponified wash
2. No clean smt - clean wave solder - aqueous wash.
Could you please advise why this would be detrimental. Would this affect the
reliability of the joints and if so is there a paper on this.
Thanks for your help.
Best regards
Marc.
-----Original Message-----
From: Kathy Kuhlow [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 2:20 PM
To: [log in to unmask]
Subject: Re: [TN] Flux residue with a no-clean process
<< File: TEXT.htm >> IPC-610 has no-clean residues as acceptable. Is it
possible that flux may have been mixed with a washable? Washing a no-clean
off is more detrimental than leaving it alone.
Is the assembly conformally coated? Is the application intended to be in a
wet or high humidity/moisture enviroment?
Kathy
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Date: Wed, 30 Jan 2002 07:18:18 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: pulse plating - without additives
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
have you tried the 'american electroplaters society'? their web page is:
http://www.aesf.org/
phil
-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 12:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives
Hello platers. I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.
Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.
A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:
forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2
The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?
If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.
regards,
Adam Seychell.
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Date: Wed, 30 Jan 2002 10:18:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Goldman, Patricia J." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Goldman, Patricia J." <[log in to unmask]>
Subject: Re: pulse plating - without additives
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Adam,
In late 1999 there was a TechNet thread on pulse plating. You should be able to pick it up in the archives on IPC's website. They may contain some useful info for you.
Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]
-----Original Message-----
From: Robert Peterson [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 7:47 AM
To: [log in to unmask]
Subject: Re: [TN] pulse plating - without additives
Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html
Hope this helps
Bob Peterson
Alternate Final Finishes, Inc.
-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives
Hello platers. I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.
Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.
A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:
forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2
The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?
If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.
regards,
Adam Seychell.
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Date: Wed, 30 Jan 2002 10:34:43 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: pulse plating - without additives??
MIME-Version: 1.0
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At risk of stating the obvious...
You really do not want "just any Copper plating", you want brilliant, smooth,
shiney, flexible, stretchable Copper....good luck getting it with ANY
rectifier without "additives". Make up a model plating bath that would fill
a hull cell, and check out what you can expect.
Rudy Sedlak
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Date: Wed, 30 Jan 2002 07:30:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Roger Stoops <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Stoops <[log in to unmask]>
Subject: Re: Minimum bend radius calculation in a flex circuit
X-To: Doug Pogatetz <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
In addition to the comments of our venerable colleagues, the IPC has some
interesting formulas for determining minimum bend radii. The specification
in IPC-2223, Sectional Design Standard for Flexible Printed Boards. In
section 5.2.3.4, formulas for single- and double-sided circuits (with
coverlay) are given. I made a rough Excel spreadsheet that helped me
determine the min radius for a "Flex to Install" application.
My first design didn't work too well because the circuit was too thick for
the required bend radius. Using the IPC guideline really helped (gratuitous
pitch for the IPC), likewise with having nice, understanding engineers
(blatant gratuitous compliment) !
I have sent the file to you; if anyone else wants to get a copy, please give
me an e-jingle.
<<Flex_radius.xls>>
Regards,
Roger M. Stoops, C.I.D. [log in to unmask]
TRIMBLE NAVIGATION LLC
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Telephone: 937 233 8921 800 538 7800 ext. 288
Facsimile: 937 233 7511
http://www.trimble.com
-----Original Message-----
From: Doug Pogatetz [mailto:[log in to unmask]]
Sent: Tuesday, January 29, 2002 4:00 PM
To: [log in to unmask]
Subject: [TN] Minimum bend radius calculation in a flex circuit
I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.
I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?
Thanks.
Doug
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Date: Wed, 30 Jan 2002 10:45:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Hargreaves <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Hargreaves <[log in to unmask]>
Subject: IPC-6011, 6012 testing requirements
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Hi All,
Is the board shop required to make & analyze microsections for every job
fabricated to IPC-6011 & 6012 ? The spec's seem to indicate this.
Thanks,
Mark Hargreaves
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Date: Wed, 30 Jan 2002 10:01:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
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Is it OK to have flux residue on assemblies when the process is no clean.
*That depends entirely on what flux you are using, the amount of flux your
are applying, and the reflow profile you are using. I suggest you get a
copy of IPC-TP-1115, that goes over the things you need to think about when
transitioning to no-clean assembly. Flux is one of the considerations.
We have assemblies that are failing in the field and the customer thinks
this
flux residue may be an issue. They think the assembly has been wet.
*What is the failure mechanism? How many assemblies are affected? What
does your customer mean by "wet"?
What do you think????
*I think we need more information.
Doug Pauls
Rockwell Collins
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Date: Wed, 30 Jan 2002 11:03:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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Subject: Re: Flux residue with a no-clean process
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Oliva
We have seen many failures over the last 10 years associated with No Clean
low solids assembly processes. The failures fall into four general
catigories, electrochemical migration failures, electrical leakage failures,
visible (cosmetic only) residues and insulative failures on contact areas.
It sounds like you are experiencing electrical leakage and electrochemical
migration problems. These problems typically stem from bare board and
component cleanliness (HASL flux is high in chloride and / or bromide
activators) from fluxes, etchants, rinse water quality. The other failure
mechanism that we have seen is the flux from hand solder or touch up not
completely heated (complexed means to drive all the carrier from the flux
after it has reacted it's activation temperature, so as not to absorb
moisture). I would recommend Ion Chromatography analysis on the failed
assemblies and compare this to current production samples. After the failure
analysis is completed and a corrective action plan is put into place I would
suggest a process qualification using a test board built by your fabrication
house and run through your primary (SMT and PTH) processes and your secondary
(hand solder, temporary maskents) processes. Then subject these test boards
to SIR testing protocol identified in J-STD 001.
I have included information from a recent article that we published on
failures.
Electrochemical Migration and Leakage Failures
This type of failure occurs when the following key variables are combined.
1st is a voltage differential (power to ground),
2nd is the transfer fluid (e.g. absorbed surface moisture - in micro-droplet
form) and
3rd is a corrosive (conductive residues for leakage failures)) residue that
will create the deplating of the anode and carry the metal salt into solution
and allow plating along the current path.
All three variables must be present in order for the electrochemical
migration failure to occur. With a power requirement of as little as 1.5
-2.0 volts to drive the dendrite formation, nearly all electronic circuits
are susceptible to this type of failure criteria (as long as the three
conditions exist). Generally, a failure occurs when the spacing between
power and ground is connected by a thin layer of moisture that combines the
corrosive residues and the voltage to create a metal dendrite that shorts the
circuit. This conductive metal path creates a short circuit on an assembly in
the field, and this assembly is then returned to the manufacturer where a
typical failure analysis is performed. This typical failure analysis will
often include a SEM/EDX analysis showing the following elements, carbon,
oxygen, tin, lead, and copper. This elemental investigation provides some
wonderful photos of the dendrite and shows that copper, tin and lead metals
were the metals that created the short, but it doesn't tell us what caused
the dendrite to grow.
We still need to understand the contamination types and levels, as well as
determining the sources and why the assembly surface was absorbing moisture.
Our focus should not be on which metal created the short (it has to be one of
the metals in the area of the failure), but rather, on what corrosive
residues caused the dendrites and where they came from. We have found that
tools such as Ion Chromatography and SIR testing give us a very detailed
understanding of the specific residue species. The No Clean flux residue is
not encapsulating enough to keep the board fabrication residues away from
absorbed moisture and the circuit voltage.
We have published a number of case studies on these issues and are availble
from our web site.
Terry Munson
CSL Inc.
P 765-457-8095
F 765-457-9033
<A HREF="www.Residues.com">www.Residues.com</A>
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Date: Wed, 30 Jan 2002 16:37:16 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: Jim Marsico <[log in to unmask]>,
David Douthit <[log in to unmask]>
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Jim
I know this is a late posting, because I have only just come back on-line
however, what you have encountered is reversion.
The UR materials tend to discolour when exposed to high temperatures, but
this does not generally affect their subsequent performance - if anything it
might improve it because you have ensured a full x-link of the polymer -
fully reacted.
The discoloration may however, be an unacceptable visual condition to your
customer, depending upon their inspection criteria.
Whatever, it will be possible to remove and re-coat if you desire.
You mention that this is a space application, therefore this material will
probably have excellent outgassing characteristics and I can only think of 1
or 2 UR space (NASA / ESA) approved coatings. I am surprised that you have
this reversion, what did their technical staff advise? I would like to know
for my own record.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
> Sent: 29 January 2002 00:49
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
>
> Jim,
>
> You have chemically altered the polymer. It will no longer
> perform it's designed function.
>
> David A. Douthit
> Manager
> LoCan LLC
>
> "Marsico, James" wrote:
>
> > Help! Emergency!
> >
> > We have a completed assembly (top assembly with many boards,
> hybrids, etc.)
> > ready for shipment to our customer (space product). The last
> operation was
> > to ink mark a S/N. The ink is cured at 150 F for 2 hours. The
> assembly was
> > put in an oven at 150 C for two hours. After hours of
> reviewing all of the
> > materials and bill of material, component by component (component data,
> > supplier phone calls, etc.), the only item that is not rated
> for 150 C is
> > the polyurethane conformal coating, which turned yellow/brown
> in color. Can
> > anyone explain what actually happened to the coating and if it
> can be used
> > as is?
> >
> > Thanks,
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
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Date: Wed, 30 Jan 2002 10:39:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flux residue with a no-clean process
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I found an old copy of ipc-tp-1115 "Selection and Implementation Strategy for A
low-residue no-clean process" published Dec. 1998. Have not read thru it yet
but also have simular interest in implementation of no-clean. If any one has
more referance info i would appreciate.
[log in to unmask] on 01/30/2002 09:05:36 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
[log in to unmask]
To: [log in to unmask]
cc: (bcc: Warren Crow/US/I-O INC)
Subject: Re: [TN] Flux residue with a no-clean process
Hi Kathy,
I am very interested in this as we have the following processes:
1. No clean smt - no clean wave solder - saponified wash
2. No clean smt - clean wave solder - aqueous wash.
Could you please advise why this would be detrimental. Would this affect the
reliability of the joints and if so is there a paper on this.
Thanks for your help.
Best regards
Marc.
-----Original Message-----
From: Kathy Kuhlow [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 2:20 PM
To: [log in to unmask]
Subject: Re: [TN] Flux residue with a no-clean process
<< File: TEXT.htm >> IPC-610 has no-clean residues as acceptable. Is it
possible that flux may have been mixed with a washable? Washing a no-clean
off is more detrimental than leaving it alone.
Is the assembly conformally coated? Is the application intended to be in a
wet or high humidity/moisture enviroment?
Kathy
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Date: Wed, 30 Jan 2002 19:01:21 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
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From: Brian Ellis <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
X-To: Olivia Mc Dermott <[log in to unmask]>
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I think there is a strong risk of cross-purposes here.
To reply to the first question: if the product has been operating under
adverse climatic conditions, the "no-clean" chemistry is a no-no, unless
extremely careful qualification has been made.
To add something: "no-clean" chemistry has been designed to be as safe
as possible for what it has been designed, i.e., leaving the residues in
situ. Attempting to clean something which has not been designed to be
cleaned MAY work, but it is just as likely to be a helluva sight more
dangerous than not attempting to clean it, at all. NOT to be recommended
for the faint-hearted or ignorant.
Brian
Olivia Mc Dermott wrote:
>
> Is it OK to have flux residue on assemblies when the process is no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
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Date: Wed, 30 Jan 2002 17:03:30 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
X-To: Olivia Mc Dermott <[log in to unmask]>
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Olivia
No clean fluxes leave residues.
J-STD-001B (can't quote issue C because I don't have a copy to hand) states:
8.3.5 Flux Residues
Assemblies shall be tested in accordance with IPC-TM-650, Test Method 2.3.27
and shall comply with the following requirements for the maximum allowable
level of flux residues:
Class 1 assemblies less than 200 microgram's/sq cm
Class 2 assemblies less than 100 microgram's/sq cm
Class 3 assemblies less than 40 sq/sq cm
In case you don't know the classifications
Class 3 is safety critical products - e.g. gas meters, military hardware,
ABS, air bag or engine management stuff etc..
Class 2 is service dependant products - UPS systems, process plant control
and stuff that doesn't necessarily endanger life but matters if it breaks!
Class 1 is low consequence product - PC's, phones, toys etc..
As to the failures you mention, flux residues + moisture + electricity =
trouble.
Hope this helps.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
> Sent: 30 January 2002 13:48
> To: [log in to unmask]
> Subject: [TN] Flux residue with a no-clean process
>
>
> Is it OK to have flux residue on assemblies when the process is
> no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
> http://www.hotmail.com
>
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Date: Wed, 30 Jan 2002 17:17:01 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: 2 Conformal Coating ?'s
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Peter and other Techies,
With apologies for this very tardy response - and I won't bore you with the
why's and where fore's......and no, it wasn't because I couldn't. So, better
late than never and written at 34,000 feet - that's 10,000 meters in new
money:
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Swanson
Sent: 10 December 2001 17:13
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s
Graham,
UV or light curing coatings:
- Solvent free
As are many thermal and moisture curing silicones. The more recent
developments in water based technology also offer a new solution to the
problem (pardon the intended pun).
- Full cure in seconds, on-line
Yes but this is a misleading statement. Conformal Coatings are intended to
be protective envelopes, conforming to the varied geometry of a printed
circuit assembly and should, ideally, be applied under as well as over,
components. This then begs the question of how to ensure the coating is
properly cured in areas where light cannot be readily applied. The method is
generally to incorporate a secondary curing mechanism thus rendering the
material more akin to a 2 part rather than:
- Single part
As I suggest above, these secondary curing agents often influence the pot
life and the shelf life of the end product. This can be a major drawback for
the smaller / lower volume electronic producers.
Virtually all modern conformal coatings are single part products, and
providing long pot and shelf life, not uncommonly around 12 months, is the
norm. This does not always apply to UV curable coatings nor indeed, to most
silicones.
- Non flammable
What do you mean by non-flammable? Are you referring to the liquid or cured
material?
Materials that are qualified / approved to such specifications as
MIL-I-46058 - IPC-CC-830 - Def Std 59/47 issue 4 - UL - etc., must meet
certain "flammability" tests in their cured state. This would not represent
any particular advantage of UV over conventional coatings.
In their liquid state, I frankly doubt that any coating material has any
greater or lesser degree of flammability. Being "resins or polymers" or
otherwise plastic materials, they have a tendency to "burn" in a rather
dramatic way, under the right conditions.
- Can meet MIL I-46058C and UL
Can meet? This is a rather curious term as it implies that many do not meet
such specifications. I am aware of many UV coatings that cannot meet the
requirements of such specifications. This is quite often in respect to their
flexibility at extremely low temperatures.
I would like to make a point here about such terms as "meets the
requirements of..." or "meets or exceeds...". Either a coating is qualified
/ approved or it is not. It costs a great deal to obtain such qualifications
/ approvals, and is one of the issues delaying the supercession of the MIL
Spec by the IPC-CC-830 - that and the issue regarding independent testing
required under the prevailing MIL spec..
- Good to excellent environmental resistance
Are you suggesting above and beyond conventional materials?
- Can be "rigid" or "flexible" (Shore D80 to Shore D40)
I am not sure that this is a stipulation within the prevailing
specifications. What benefit are you alluding to?
- Can be used on flex
Uniquely? Not in my experience.
- Can have strong fluorescence for inspection, or even be black
A requirement of the MIL Spec and Defence Standards (British) is that the
conformal coating shall not obscure markings on the board and components to
facilitate repair and rework. Whilst this is not usually a requirement for
"commercial" applications, it is fair to say that the addition of pigments
or dye's can greatly influence the performance of the coating under extreme
conditions.
The Military require that qualified coatings contain a UV tracer to aid
inspection. I think it fair to say, that the half-life of the tracer is
affected by its exposure to strong UV light during cure.
There are "black" or indeed other coloured coatings available however, the
addition of such pigments, as I said above, affect performance particularly
in respect to moisture resistance. Such pigments effectively "separate" the
coating molecules leaving space for moisture to more easily migrate in and
out of the film.
Another point - why black or coloured material? It has been my experience
that the customer is often seeking a means of "hiding" the circuit design.
This is not likely to be very successful. Clever use of chemical stripping
agents or mechanical removal of the coating can be easily effected.
They are not suitable for all applications - are better sprayed, not so good
for dipping. If sprayed (say, using PVA or Nordson type selective spray
equipment), then full cure can often be achieved just with light. Otherwise,
secondary cures for shadowed areas may be achieved with heat, anaerobic,
moisture or other mechanisms.
"Horses for courses" is an oft quoted expression - at least by me! UV
curable coatings have many applications: Fibre-optics, LCD's, some
photo-cells, most 2D applications etc.. As we built (probably?) the world's
first in-line dip and UV curing system in 1987, we learnt the hard way, the
many process issues that need to be addressed.
As an example, and as you say Peter, dip coating is not its forte. The
coating area must be separated from the curing zone, no stray light can get
to the tank and no-one should be able to view the light, or it would be the
last thing they saw. Furthermore, the assemblies have to be racked onto the
jigs / carriers face-on, so that the light can shine forth upon the face of
the assembly. This meant that the system has 1/3rd the capacity / throughput
of a conventional cure coating.
Robotic selective coating systems revolutionised the coating business -
thankfully! Yes, these coatings are much more applicable to this method but,
the time it takes to apply the product remains the same whatever the coating
type. Allowing due separation from the application zone, there is not too
much advantage to be gained by using light instead of heat.
To answer Mike Fenner's question, most pcb coatings are acrylic based, which
is a free radical cure. Expose to the correct wavelength/intensity of light
for required time and full cure is achieved. In fact, if the light is taken
away, curing stops. All the coating must be exposed to the light.
There are some coatings (a few) based on epoxy chemistry and a cationic
cure. Some cross linking will continue after the light is removed, but only
for thin sections (i.e. it doesn't propagate far), and just like the free
radical cure, all the coating must be exposed to the light.
You see, its all done with mirrors!
I refuse to be drawn into a discussion on free radicals. People who know me
will know why - I am not a chemist, but the worlds greatest parrot!!
So, an interesting technology which certainly has its place in the panoply
of coatings available for circuit protection. Whilst not a universal
panacea, they can often offer processing speed and simplicity, including
perhaps some environmental and health & safety advantages.
No argument there.
IMHO, they should not be dismissed totally out of hand by competitors to the
technology in an open forum; for one thing, this might insult the many
companies who are successfully using them!
IMHO you are correct. Unlike most suppliers, we offer a comprehensive range
of coatings including UV's.
Regards,
Peter
=========================================================
Peter Swanson [log in to unmask]
INTERTRONICS http://www.intertronics.co.uk
INTERTRONICS is dedicated to providing quality material,
consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
the highest levels of technical support and customer
service.
I hope this will be taken in the spirit in which it is offered and - if you
will pardon the pun: shed more light on the subject. I am sure that I speak
for Peter in inviting comments to the above exchange that may help engineers
decide on the best route for their product.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: 09 December 2001 19:01
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s
Peter,
I am semi-comatose now, so please, tell us what exactly are the advantages
of UV curable coatings?
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Swanson
Sent: Friday, December 07, 2001 05:51
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s
Graham,
You really must see someone about your delusions over UV cured coatings,
which are successfully used to coat many thousands of pcb's each year. I
know someone who has a nice sofa you can stretch out on whilst you tell him
all about it.... <g>
Suitability for UV has nothing to do with 3D v. 2D, more to do with the
complexity of the assembly geometry and the application methodology. These
will determine if a secondary cure mechanism is needed for the application.
In many instances (and with some of our customers), full cure is achieved
just with light.
Regards,
Peter
--
--------------------------------------------------------
Peter Swanson [log in to unmask]
INTERTRONICS http://www.intertronics.co.uk
INTERTRONICS is dedicated to providing quality
material, consumable and equipment solutions to the
electronics manufacturing and other technology based
industries, with the highest levels of technical
support and customer service.
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: 06 December 2001 16:52
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s
Mike
You would be better to go with a conventional coating. UV is not ideal for
3D objects - works great in 2D, cos you don't have to bend light! :-)
I cannot remember what the operating environment was for your circuit - if
you would care to repeat, I can recommend something - however, I am sure
that a one part AR or UR coating from a reliable supplier will give you the
best overall results - process and operating environment.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
Sent: Thursday, December 06, 2001 02:41
To: [log in to unmask]
Subject: [TN] 2 Conformal Coating ?'s
Hello,
Thanks in advance if you have taken the time to read this!
#1- Im trying different materials in a spray application. Both are cured
using UV. One material does a "secondary cure" w/ moisture. This is cool
because after 100 hours after UV cure, all material is fully cured.
The other material Im trying uses HEAT for a secondary cure, or, if
shodowed during UV cure, the material wont cure and never will. Obviously I
dont want the stuff dripping or running anywhere, but being new to this
wonderful process, just dont feel good about leaving uncured material on a
product for it's entire life. Iv been told that you can "test" the product
to see if the uncured material is causing a problem but Im not sure what
type of test that would consist of. Any insight?
#2- Has anyone out there ever installed refelctive metal plates in their UV
oven to limit shadowing?
Thanks so much,
Mike Manwell
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Date: Wed, 30 Jan 2002 09:09:01 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Stop Line Rules
MIME-Version: 1.0
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Production Gurus - was wondering what do you guys use as "stop line" rules
for SMT, Handload, Wave & ICT if you find too many defects - when do you
stop a line and raise a flag? Is there an industry standard? Does IPC have
any guideline? Any information you might have please pass it along.
Regards, Mohit
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Date: Wed, 30 Jan 2002 09:04:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dyane White <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
X-To: Olivia Mc Dermott <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
It says "no clean" and therefore one would think that you do not have t=
o clean it. The IPC standards says that residue from no clean fluxes a=
re acceptable provided it has been qualified and documented by your pro=
cess engineer as benign. It has been my
experience that some "no clean" fluxes have corrosion issues. If I wer=
e you I would do some ionic testing. Check out IPC -TM-650 for test pr=
ocedures. You might also check the chemical content of the flux you're=
using. If it contains halides then you
most likely have a problem. Good luck!
Dyane White
Technical/Process Trainer
Philips Ultrasound
Bothell, WA
=
=20
Olivia Mc Dermott =
=20
<oliviamcdermott01@HO To: [log in to unmask]
G =20
TMAIL.COM> cc: (bcc: Dyane Wh=
ite/ATL-BTL/MS/PHILIPS) =20
Sent by: TechNet Subject: [TN] Flux=
residue with a no-clean process =20
<[log in to unmask]> =
=20
Classification: =
=20
=
=20
01/30/02 05:48 AM =
=20
Please respond to =
=20
"TechNet E-Mail =
=20
Forum."; Please =
=20
respond to Olivia Mc =
=20
Dermott =
=20
=
=20
=
=20
Is it OK to have flux residue on assemblies when the process is no clea=
n. We
have assemblies that are failing in the field and the customer thinks t=
his
flux residue may be an issue. They think the assembly has been wet.
What do you think???? All help appreciated.
_________________________________________________________________
Join the world's largest e-mail service with MSN Hotmail.
http://www.hotmail.com
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Date: Wed, 30 Jan 2002 10:47:24 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Edwards <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Edwards <[log in to unmask]>
Subject: Re: Test Coupons
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I think that is probably what IPC-6011 is saying in para 4.3.2.3 when it
says, Acceptance of product for delivery shall be based on product that has
passed the testing requirements shown in the applicable Preformance
Specification and follows that with para 4.3.2.4 on rejected lots which
calls for 100% inspection and disposition of defective units. IPC-6012A
says shall meet the microsection requirements, if it does not then 6011 on
what you do then should apply
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 29, 2002 2:10 PM
Subject: [TN] Test Coupons
> Hi To All
> I am stumped - where are the words that say "if a coupon from a panel
fails
> to meet the specification requirements - all associated boards from that
> panel are rejected"?
>
> I know it, but I sure can't find it.
>
> Thanks
> Susan Mansilla
>
> --------------------------------------------------------------------------
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Date: Wed, 30 Jan 2002 11:54:55 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC-6011, 6012 testing requirements
X-To: [log in to unmask]
Mark,
The customer specifies requirements OR, depending on several factors, each
supplier lot shall be sectioned and analyzed. For re-qualification to 6012,
the requirements are specified therein.
Back in the good old days, when processes were not nearly as well managed
(nor could the be considering what some of us had to work with) and boards
were complex for the time, we would test small lot sizes. When a board type
was particularly difficult, a lot of one might comprise the it and would be
tested. Obviously, if one board out of a lot of one failed, only one lot was
rejected. There's a lot more to this story and some of the other old timers
can add interest to it.
MoonMan
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Date: Wed, 30 Jan 2002 12:01:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Wave Solder/NoPb Question
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! I just extracted myself from a wonderful discussion on the impact
of PbFree solder alloys on the wave solder equipment, specifically the
impact of molten tin "wear" on the solderpot and pumps. My past
conversations with various folks has been that the impact will be minimal
with some of the stainless steel construction materials (e.g. 301 - 304
alloys) have some problems but cast iron, titanium, or ceramic coated
solderpots/pumps will fair reasonably well. SEHO presented a paper at APEX
which showed some wonderful molten tin attack on the wave solder equipment
(well, it was wonderful from a purely metallurgical view point anyway) but
my question to the forum is this: Does anyone have personal experience,
either good or bad, with PbFree solder alloys and wave solder equipment?
(Hey Eric de Kluizenaar - have you experienced any issues with your wave
solder line?). We don't need to discuss "who's" equipment was impacted but
more of a discussion of the alloy/solderpot interactions.
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Wed, 30 Jan 2002 12:06:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Wetting Balance Survey
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! As chairman of the JSTD-002A and JSTD-003 solderability
committees I have been tasked to get a feel for who is using wetting
balance test equipment and what equipment they are using. The task group
will use this information to assist in improving the wetting balance test
procedure in the specifications by sending draft procedure proposals to
folks for critique. If you are a wetting balance user or use a wetting
balance in your company, could you please email me (off-line so we don't
bombard the TechNet) your contact information (name, email address) and
what equipment you are using (brand X, homemade, etc.).
Thanks for your assistance!
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Wed, 30 Jan 2002 13:38:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: Graham Naisbitt <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
The coating supplier's technical staff stated that the discoloration was
probably due to oxidation of the double bond of the molecules. He also
stated, as you, that the material may have become somewhat harder due to
further cross linking.
I don't think that moisture permeability is an issue, but what is a concern
is if the modulus increased which might affect chip component reliability,
if coating was actually under some ceramic or glass components. In your
opinion, would additional cross linking, oxidation, reversion or being at
150C for 2 hours cause the modulus to increase?
As far as stripping the coating, we crossed this path once before and our
customer will not allow us to use any chemical stripping solution to remove
polyurethane coating. They don't know how it will affect components,
boards, etc.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Graham Naisbitt [SMTP:[log in to unmask]]
Sent: Wednesday, January 30, 2002 11:37 AM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating
Jim
I know this is a late posting, because I have only just come back
on-line
however, what you have encountered is reversion.
The UR materials tend to discolour when exposed to high
temperatures, but
this does not generally affect their subsequent performance - if
anything it
might improve it because you have ensured a full x-link of the
polymer -
fully reacted.
The discoloration may however, be an unacceptable visual condition
to your
customer, depending upon their inspection criteria.
Whatever, it will be possible to remove and re-coat if you desire.
You mention that this is a space application, therefore this
material will
probably have excellent outgassing characteristics and I can only
think of 1
or 2 UR space (NASA / ESA) approved coatings. I am surprised that
you have
this reversion, what did their technical staff advise? I would like
to know
for my own record.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
> Sent: 29 January 2002 00:49
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
>
> Jim,
>
> You have chemically altered the polymer. It will no longer
> perform it's designed function.
>
> David A. Douthit
> Manager
> LoCan LLC
>
> "Marsico, James" wrote:
>
> > Help! Emergency!
> >
> > We have a completed assembly (top assembly with many boards,
> hybrids, etc.)
> > ready for shipment to our customer (space product). The last
> operation was
> > to ink mark a S/N. The ink is cured at 150 F for 2 hours. The
> assembly was
> > put in an oven at 150 C for two hours. After hours of
> reviewing all of the
> > materials and bill of material, component by component
(component data,
> > supplier phone calls, etc.), the only item that is not rated
> for 150 C is
> > the polyurethane conformal coating, which turned yellow/brown
> in color. Can
> > anyone explain what actually happened to the coating and if it
> can be used
> > as is?
> >
> > Thanks,
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
> ------------------------------------------------------------------
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Date: Wed, 30 Jan 2002 12:37:21 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Stop Line Rules
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_4A17237B.B6D7BAB2"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_4A17237B.B6D7BAB2
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There is no defect allowed or production allowed to run without all =
defects being investigated and resolved. This may involve several avenues =
but if a defect is found it is investigated. We acknowledge that either =
the process has been improved and the process parameters are documented. =
If a defect can't be removed we build in process control for those =
inherent issues. Common defects that we consider inherent issues that we =
would build into a secondary op are wave solder skips because of orientatio=
n, sot-23 packages, connector shorts due to wave snapping. =20
All operators must take the initiative and stop. We also hold those =
accountable for the quality of the product (good or bad). I am very firm =
about accountability for good and bad workmanship. =20
--=_4A17237B.B6D7BAB2
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>There is no defect allowed or production allowed to run without all defects
being investigated and resolved. This may involve several avenues but if a
defect is found it is investigated. We acknowledge that either the
process has been improved and the process parameters are documented.
If a defect can't be removed we build in process control for those
inherent issues. Common defects that we consider inherent issues that we
would build into a secondary op are wave solder skips because of
orientation, sot-23 packages, connector shorts due to wave snapping.
</DIV>
<DIV> </DIV>
<DIV>All operators must take the initiative and stop. We also hold those
accountable for the quality of the product (good or bad). I am
very firm about accountability for good and bad workmanship.
</DIV></BODY></HTML>
--=_4A17237B.B6D7BAB2--
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Date: Wed, 30 Jan 2002 12:46:34 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flux residue with a no-clean process
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Just as a note on Graham Naisbitt's response, the test method he quotes is
residual rosin by UV-Vis spectroscopy. The pass-fail limits are based on
RA flux from the first IPC Cleaning and Cleanliness Test Program
(IPC-TR-580). For OA and no-clean fluxes, this test is largely
meaningless.
Doug Pauls
Rockwell Collins
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Date: Wed, 30 Jan 2002 12:48:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: CSP/DSP SOLDERING PROBLEM?
Folks,
Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or some such
thing. I can't imagine there being solderability issues with these things,
but then I didn't think I'd live this long. However, after examining all
other possible process variables, and resolving them to some extent, these
things look to be the last straw.
Solder joints on these parts, mostly, aren't. The "C" clamp thing picture is
holding one of the critters on the board to make electrons flow.
Does anyone have any issues with these parts and their solderability? I do
appreciate the assistance. Steve, these probably are coming your way.
Earl
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Date: Wed, 30 Jan 2002 12:03:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process
X-To: Olivia Mc Dermott <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854";
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Olivia,
You will have to do some testing based on the end use environments.
If this units are exposed to humidity levels above 80% the customer may have
a point.
David A. Douthit
Manager
LoCan LLC
Olivia Mc Dermott wrote:
> Is it OK to have flux residue on assemblies when the process is no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
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Date: Wed, 30 Jan 2002 13:56:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_155.81ce9f1.29899be7_boundary"
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Would microabrasive blasting of the coating be an alternative to chemical
stripping?
Regards,
Mike Sewell
--part1_155.81ce9f1.29899be7_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#ffffff"><FONT style="BACKGROUND-COLOR: #ffffff" SIZE=2>Would microabrasive blasting of the coating be an alternative to chemical stripping?<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT></HTML>
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Date: Wed, 30 Jan 2002 11:09:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dyane White <[log in to unmask]>
Subject: Solder removal
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Greetings,
HELP...this question keeps rearing it's ugly head and I can't find where it is documented. Must you remove solder before attaching or reattaching a component or wire? This circumstances are....solder in a via or through hole...must the solder be removed
before a jumper wire is attached? Can you reheat existing solder and add a component or wire to through hole or for that matter surface mount pads and where does it say it is acceptable or not acceptable?
Thanks,
Dyane White
Technical/Process Trainer
Philips Ultrasound
Bothell, WA
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Date: Wed, 30 Jan 2002 14:34:54 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Laminate Blisters...
MIME-Version: 1.0
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Hi all!
Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through surface
mount.
I went to the inspector, and sure enough, this is what I saw. Go to:
http://www.stevezeva.homestead.com
They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...
Funny thing is they look like blisters, but the laminate isn't displaced like
you normally would see in a blister...to me, it's more like a sort of
delamination.
I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...
Anybody ever see something like this before?
-Steve Gregory-
--part1_120.a945b9d.2989a4de_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Got another strange one again (why me?). Ran 70 peices of a double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
<BR>
<BR>Everything seemed to be going fine until the boards got to an inspector just prior to test. I get paged to look at some blisters she said she was seeing. I was pretty suprised because things were fine when they went through surface mount.
<BR>
<BR>I went to the inspector, and sure enough, this is what I saw. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>They appear randomly at one of four plated mounting holes on the board, and it's on random sides of the boards too...and it only happened on 19-assemblies. I can't find out when it happened. These mounting holes are off away from anything that was hand soldered too...
<BR>
<BR>Funny thing is they look like blisters, but the laminate isn't displaced like you normally would see in a blister...to me, it's more like a sort of delamination.
<BR>
<BR>I didn't see anything like that during SMT processing, I mean you can't miss something like that. But if it were due to excessive heat, I would expect to see it on more assemblies. The same thing would apply if it were caused by absorbed moisture wouldn't it? I would expect to see the problem on more assemblies. The fabs are all the same date code by the way...
<BR>
<BR>Anybody ever see something like this before?
<BR>
<BR>-Steve Gregory-</FONT></HTML>
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Date: Wed, 30 Jan 2002 12:10:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Laminate Blisters...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
At first glimpse, the apparent change in opacity of the soldermask makes it
look like the mask is lifting off the laminate. Is that what you see?
You said the date codes are all the same. How old are they? For moisture
absorption related delamination on FR4 they either have to be pretty old
(months) or been stored in very humid conditions.
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Wednesday, January 30, 2002 11:34 AM
> To: [log in to unmask]
> Subject: [TN] Laminate Blisters...
>
> Hi all!
>
> Got another strange one again (why me?). Ran 70 peices of a double-sided
> SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
>
> Everything seemed to be going fine until the boards got to an inspector
> just prior to test. I get paged to look at some blisters she said she was
> seeing. I was pretty suprised because things were fine when they went
> through surface mount.
>
> I went to the inspector, and sure enough, this is what I saw. Go to:
>
> http://www.stevezeva.homestead.com
>
> They appear randomly at one of four plated mounting holes on the board,
> and it's on random sides of the boards too...and it only happened on
> 19-assemblies. I can't find out when it happened. These mounting holes are
> off away from anything that was hand soldered too...
>
> Funny thing is they look like blisters, but the laminate isn't displaced
> like you normally would see in a blister...to me, it's more like a sort of
> delamination.
>
> I didn't see anything like that during SMT processing, I mean you can't
> miss something like that. But if it were due to excessive heat, I would
> expect to see it on more assemblies. The same thing would apply if it were
> caused by absorbed moisture wouldn't it? I would expect to see the problem
> on more assemblies. The fabs are all the same date code by the way...
>
> Anybody ever see something like this before?
>
> -Steve Gregory-
>
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=========================================================================
Date: Wed, 30 Jan 2002 15:36:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Don't have any experience with micro-blasting, but wouldn't it be difficult
to remove the coating from the entire board, in-between component leads? If
someone is doing this, how's it working? What media, what equipment?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: [log in to unmask] [SMTP:[log in to unmask]]
Sent: Wednesday, January 30, 2002 1:57 PM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating
Would microabrasive blasting of the coating be an alternative to
chemical stripping?
Regards,
Mike Sewell
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Date: Wed, 30 Jan 2002 15:56:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: CSP/DSP SOLDERING PROBLEM?
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
This component package is a pain in a spot somewhat below the neck, because
of the slug of metal used for a heat sink in the package. Issues are:
* Process measurement needs to be measured on the solder balls [both at the
inner row and the corner]. The difference in CTE of all the elements of this
package can make it difficult to profile otherwise.
* Process verfication with a common xray machine is close to futile.
Further, in these TI DSP, Dr. Cemel Basaran, SUNY Buffalo, 716-645-2114
X2429, [log in to unmask] has seen:
* Thinner [2 micron] than normal [20-micron ] AuSn4 IMC
* Black pad
Dave Fish
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 10:48 AM
Subject: [TN] CSP/DSP SOLDERING PROBLEM?
> Folks,
>
> Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or some
such
> thing. I can't imagine there being solderability issues with these things,
> but then I didn't think I'd live this long. However, after examining all
> other possible process variables, and resolving them to some extent, these
> things look to be the last straw.
>
> Solder joints on these parts, mostly, aren't. The "C" clamp thing picture
is
> holding one of the critters on the board to make electrons flow.
>
> Does anyone have any issues with these parts and their solderability? I do
> appreciate the assistance. Steve, these probably are coming your way.
>
> Earl
>
> --------------------------------------------------------------------------
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>
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Date: Wed, 30 Jan 2002 14:59:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: CSP/DSP SOLDERING PROBLEM?
X-To: [log in to unmask]
Thanks Dave,
My thinking exactly. My observations, at this point can't back my thoughts.
I will pursue this and see where we go from here.
Steve, they are coming your way as is the profile board. Not advertising.
Just preparing.
Earl
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Date: Wed, 30 Jan 2002 15:02:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Laminate Blisters...
X-To: [log in to unmask]
Michael and Steve,
Sounds almost right to me. However, it looks like a classic delam/blister
episode possibly brought on by edge condition problems propagating into the
hole. Also, though not being able to see clearly, the hole walls look a bit
rough so is it possible the reverse condition exists. Can't really tell the
"blister" depth.
Earl
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Date: Wed, 30 Jan 2002 13:16:59 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chuck Brummer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Laminate Blisters...
X-To: [log in to unmask]
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If the corners are those near the corner of the panel from which these
boards came? Maybe this is where they had been attached to a rack for
the oxide line and then did not get oxide on the inner layer at that
spot. Heat then cause a loss of adhesion between the inner copper plane
and the prepreg. With that you would not get any lift or distortion.
Just what pops into my head. (Whoops, I think something fell out?)
Chuck Brummer
Acuson.
[log in to unmask] wrote:
> Hi all!
>
> Got another strange one again (why me?). Ran 70 peices of a
> double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is
> hand-soldered.
>
> Everything seemed to be going fine until the boards got to an
> inspector just prior to test. I get paged to look at some blisters she
> said she was seeing. I was pretty suprised because things were fine
> when they went through surface mount.
>
> I went to the inspector, and sure enough, this is what I saw. Go to:
>
> http://www.stevezeva.homestead.com
>
> They appear randomly at one of four plated mounting holes on the
> board, and it's on random sides of the boards too...and it only
> happened on 19-assemblies. I can't find out when it happened. These
> mounting holes are off away from anything that was hand soldered
> too...
>
> Funny thing is they look like blisters, but the laminate isn't
> displaced like you normally would see in a blister...to me, it's more
> like a sort of delamination.
>
> I didn't see anything like that during SMT processing, I mean you
> can't miss something like that. But if it were due to excessive heat,
> I would expect to see it on more assemblies. The same thing would
> apply if it were caused by absorbed moisture wouldn't it? I would
> expect to see the problem on more assemblies. The fabs are all the
> same date code by the way...
>
> Anybody ever see something like this before?
>
> -Steve Gregory-
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<html>
If the corners are those near the corner of the panel from which these
boards came? Maybe this is where they had been attached to a rack
for the oxide line and then did not get oxide on the inner layer at that
spot. Heat then cause a loss of adhesion between the inner copper
plane and the prepreg. With that you would not get any lift or distortion.
<br>Just what pops into my head. (Whoops, I think something fell
out?)
<p>Chuck Brummer
<br>Acuson.
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Hi all!</font></font>
<p><font face="arial,helvetica"><font size=-1>Got another strange one again
(why me?). Ran 70 peices of a double-sided SMT assembly. The board is a
6-layer FR4 board. PTH is hand-soldered.</font></font>
<p><font face="arial,helvetica"><font size=-1>Everything seemed to be going
fine until the boards got to an inspector just prior to test. I get paged
to look at some blisters she said she was seeing. I was pretty suprised
because things were fine when they went through surface mount.</font></font>
<p><font face="arial,helvetica"><font size=-1>I went to the inspector,
and sure enough, this is what I saw. Go to:</font></font>
<p><font face="arial,helvetica"><font size=-1><A HREF="http://www.stevezeva.homestead.com">http://www.stevezeva.homestead.com</A></font></font>
<p><font face="arial,helvetica"><font size=-1>They appear randomly at one
of four plated mounting holes on the board, and it's on random sides of
the boards too...and it only happened on 19-assemblies. I can't find out
when it happened. These mounting holes are off away from anything that
was hand soldered too...</font></font>
<p><font face="arial,helvetica"><font size=-1>Funny thing is they look
like blisters, but the laminate isn't displaced like you normally would
see in a blister...to me, it's more like a sort of delamination.</font></font>
<p><font face="arial,helvetica"><font size=-1>I didn't see anything like
that during SMT processing, I mean you can't miss something like that.
But if it were due to excessive heat, I would expect to see it on more
assemblies. The same thing would apply if it were caused by absorbed moisture
wouldn't it? I would expect to see the problem on more assemblies. The
fabs are all the same date code by the way...</font></font>
<p><font face="arial,helvetica"><font size=-1>Anybody ever see something
like this before?</font></font>
<p><font face="arial,helvetica"><font size=-1>-Steve Gregory-</font></font></blockquote>
</html>
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Date: Wed, 30 Jan 2002 15:27:07 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
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Mike Sewell Suggests: Would microabrasive blasting of the coating be an
alternative to chemical stripping?
*Just be aware that microabrasive blasting generates a hell of a static
charge. Enough to kill a static sensitive component. I think the EMPF did
some work in microabrasion methods relative to ESD in the late 80s early
90s. Check with the librarian at www.empf.org.
Doug Pauls
Rockwell Collins
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Date: Wed, 30 Jan 2002 16:40:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"PERALTA, Kevin (BREA)" <[log in to unmask]>
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From: "PERALTA, Kevin (BREA)" <[log in to unmask]>
Subject: Blacklight Fixture
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Since we've moved to a new facility (w/ a beautiful view of the San Gabriel
Mountain Range), we're in need of purchasing a new blacklight fixture for
our new Conformal Coating Booth. It's not very long, but I was hoping to get
some ideas for the best type of blacklight with a UV rating to put into
place. Can anyone serve up some good suggestions? Thank you!
Kevin L. Peralta
TRW Aeronautical / Lucas Aerospace
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<P><FONT SIZE=3D2 FACE=3D"Arial">Since we've moved to a new facility =
(w/ a beautiful view of the San Gabriel Mountain Range), we're in need =
of purchasing a new blacklight fixture for our new Conformal Coating =
Booth. It's not very long, but I was hoping to get some ideas for the =
best type of blacklight with a UV rating to put into place. Can anyone =
serve up some good suggestions? Thank you!</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Kevin L. Peralta</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">TRW Aeronautical / Lucas =
Aerospace</FONT>
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Date: Wed, 30 Jan 2002 22:49:09 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: CSP/DSP SOLDERING PROBLEM?
X-To: Earl Moon <[log in to unmask]>
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Hope you get this message once, since I had some trouble with sending =
mail (I changed provider, finally broadband !).
Hi Earl,
Couldn't find it on the net, but could it be the same as the =
TMS320C6201GGP (a 352 pins 0.8 mm pitch BGA with heatsink) ?
We've done a few, and so far no problems.=20
Perhaps the opens have their root cause in stencil printing ? =
Stencilling parts like these can be troublesome with incorrect stencil =
or machinesetup (but I don't have to tell you that).
Daan Terstegge
http://www.smtinfo.net =20
----- Original Message -----=20
From: Earl Moon=20
To: [log in to unmask]
Sent: Wednesday, January 30, 2002 7:48 PM
Subject: [TN] CSP/DSP SOLDERING PROBLEM?
Folks,
Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or =
some such
thing. I can't imagine there being solderability issues with these =
things,
but then I didn't think I'd live this long. However, after examining =
all
other possible process variables, and resolving them to some extent, =
these
things look to be the last straw.
Solder joints on these parts, mostly, aren't. The "C" clamp thing =
picture is
holding one of the critters on the board to make electrons flow.
Does anyone have any issues with these parts and their solderability? =
I do
appreciate the assistance. Steve, these probably are coming your way.
Earl
=
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<DIV>Hope you get this message once, since I had some trouble with =
sending mail=20
(I changed provider, finally broadband !).</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Hi Earl,</DIV>
<DIV> </DIV>
<DIV>Couldn't find it on the net, but could it be the=20
same as the <FONT color=3D#000000>TMS320C6201GGP (a 352 =
pins 0.8=20
mm pitch BGA with heatsink) ?</FONT></DIV>
<DIV>We've done a few, and so far no problems. </DIV>
<DIV>Perhaps the opens have their root cause in stencil=20
printing ? Stencilling parts like these can be troublesome =
with=20
incorrect stencil or machinesetup (but I don't have to tell you=20
that).</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV>http://<A=20
href=3D"http://www.smtinfo.net">www.smtinfo.net</A> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, January 30, =
2002 7:48=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] CSP/DSP SOLDERING =
PROBLEM?</DIV>
<DIV><BR></DIV>Folks,<BR><BR>Have some CSP's that are TI DSP's =
(320c6203 TMX=20
320C6203 BGLS), or some such<BR>thing. I can't imagine there being=20
solderability issues with these things,<BR>but then I didn't think I'd =
live=20
this long. However, after examining all<BR>other possible process =
variables,=20
and resolving them to some extent, these<BR>things look to be the last =
straw.<BR><BR>Solder joints on these parts, mostly, aren't. The "C" =
clamp=20
thing picture is<BR>holding one of the critters on the board to make =
electrons=20
flow.<BR><BR>Does anyone have any issues with these parts and their=20
solderability? I do<BR>appreciate the assistance. Steve, these =
probably are=20
coming your=20
=
way.<BR><BR>Earl<BR><BR>-------------------------------------------------=
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Date: Wed, 30 Jan 2002 16:24:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: CSP/DSP SOLDERING PROBLEM?
X-To: [log in to unmask]
I hear you Daan. I've examined/audited most everything to the point of
rejection. Only thing I come up with so far is as Dave says. However, I just
"feel" there is something more.
We had problems with TI parts, of the same ilk, concerning ball separation
dued to a too thick IMC layer (their terms). However. this should not affect
the solder joint on the board unless?
Earl
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Date: Wed, 30 Jan 2002 22:52:23 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Laminate Blisters...
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Hi Steve,
I've seen large and flat blisters like yours from moisture absorption. Can
you press on them and the laminate moves? Somebody forgot to bake prior to
IR Reflow.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask] <mailto:[log in to unmask]>
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 2:35 PM
To: [log in to unmask]
Subject: [TN] Laminate Blisters...
Hi all!
Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through
surface mount.
I went to the inspector, and sure enough, this is what I saw. Go to:
http://www.stevezeva.homestead.com
They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...
Funny thing is they look like blisters, but the laminate isn't displaced
like you normally would see in a blister...to me, it's more like a sort of
delamination.
I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...
Anybody ever see something like this before?
-Steve Gregory-
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<BODY>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>Hi
Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>I've seen large and flat
blisters like yours from moisture absorption. Can you press on them and
the laminate moves? Somebody forgot to bake prior to IR
Reflow.</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=772134722-30012002>
<P><FONT size=2>Integrity First - Service Before Self -
Excellence in All We Do<BR>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>Hans M.
Hinners<BR>Electronics Engineer<BR>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)<BR>226 Cochran Street<BR>Robins AFB GA 31098-1622<BR><BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR><BR>Com:
(478) 926 - 5224<BR>Fax: (478) 926 - 4911<BR>DSN Prefix:
468<BR></FONT></P></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, January 30, 2002 2:35
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Laminate
Blisters...<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi
all! <BR><BR>Got another strange one again (why me?). Ran 70 peices of a
double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is
hand-soldered. <BR><BR>Everything seemed to be going fine until the boards got
to an inspector just prior to test. I get paged to look at some blisters she
said she was seeing. I was pretty suprised because things were fine when they
went through surface mount. <BR><BR>I went to the inspector, and sure enough,
this is what I saw. Go to: <BR><BR>http://www.stevezeva.homestead.com
<BR><BR>They appear randomly at one of four plated mounting holes on the
board, and it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are off
away from anything that was hand soldered too... <BR><BR>Funny thing is they
look like blisters, but the laminate isn't displaced like you normally would
see in a blister...to me, it's more like a sort of delamination. <BR><BR>I
didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way... <BR><BR>Anybody
ever see something like this before? <BR><BR>-Steve Gregory-</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1A9E0.C82263F0--
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Date: Wed, 30 Jan 2002 16:52:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Adam Seychell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Adam Seychell <[log in to unmask]>
Subject: Re: pulse plating - without additives
Thanks everyone for your help. The article at
www.circuitree.com "Copper Plating of Electronic
Interconnects without Additives" was very helpful
indeed. By "additives" they are referring to
brighteners and levelers. The bath they described
contained polyethylene glycol.
This article lead me to find two more lnks.
http://www.pcfab.com/db_area/archive/2001/0103/taylor.html
And US patent 6,303,014, which describes the "additive
free" process in greater detail. However, they
also use a "supressor", such as polyethelene
glycol in combination with the chloride ion.
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1='6,303,014'.WKU.&OS=PN/6,303,014&RS
=PN/6,303,014
In reply to Rudy Sedlak, I beginning to see that
the rectifier cannot be a total solution.
Adam Seychell
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Date: Wed, 30 Jan 2002 17:28:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Laminate Blisters...
In-Reply-To: <[log in to unmask]>
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Steve:
I tend to agree with Mike's comment. You might give one of the blisters a
probe with a sharp Xacto blade to determine if it's soldermask or laminate.
Different set of causes for each.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Wednesday, January 30, 2002 1:35 PM
To: [log in to unmask]
Subject: [TN] Laminate Blisters...
Hi all!
Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through
surface mount.
I went to the inspector, and sure enough, this is what I saw. Go to:
http://www.stevezeva.homestead.com
They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...
Funny thing is they look like blisters, but the laminate isn't displaced
like you normally would see in a blister...to me, it's more like a sort of
delamination.
I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...
Anybody ever see something like this before?
-Steve Gregory-
------=_NextPart_000_001A_01C1A9B3.822D1FC0
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Steve:</FONT></SPAN></DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2>I tend=20
to agree with Mike's comment. You might give one of the blisters a =
probe=20
with a sharp Xacto blade to determine if it's soldermask or =
laminate. =20
Different set of causes for each.</FONT></SPAN></DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Don=20
Vischulis</FONT></SPAN></DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Wednesday, January 30, 2002 1:35 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Laminate=20
Blisters...<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi all!=20
<BR><BR>Got another strange one again (why me?). Ran 70 peices of a =
double-sided=20
SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.=20
<BR><BR>Everything seemed to be going fine until the boards got to an =
inspector=20
just prior to test. I get paged to look at some blisters she said she =
was=20
seeing. I was pretty suprised because things were fine when they went =
through=20
surface mount. <BR><BR>I went to the inspector, and sure enough, this is =
what I=20
saw. Go to: <BR><BR>http://www.stevezeva.homestead.com <BR><BR>They =
appear=20
randomly at one of four plated mounting holes on the board, and it's on =
random=20
sides of the boards too...and it only happened on 19-assemblies. I can't =
find=20
out when it happened. These mounting holes are off away from anything =
that was=20
hand soldered too... <BR><BR>Funny thing is they look like blisters, but =
the=20
laminate isn't displaced like you normally would see in a blister...to =
me, it's=20
more like a sort of delamination. <BR><BR>I didn't see anything like =
that during=20
SMT processing, I mean you can't miss something like that. But if it =
were due to=20
excessive heat, I would expect to see it on more assemblies. The same =
thing=20
would apply if it were caused by absorbed moisture wouldn't it? I would =
expect=20
to see the problem on more assemblies. The fabs are all the same date =
code by=20
the way... <BR><BR>Anybody ever see something like this before? =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BODY></HTML>
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Date: Wed, 30 Jan 2002 15:24:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Steele <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Steele <[log in to unmask]>
Subject: Re: ODB++
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Hi Seth,
I have heard this question before and haven't known how
to respond to it. So I have a question for you, if it
could be shown through real data that the board built
from gerber and the board built from ODB are the "same"
(within a certain tolerance) would you be willing to
generate both sets of data and send them out accordingly?
I assume you are comfortable with your system outputting
gerber, it's ODB that has to "prove" it can duplicate the
gerber.
Here's what I have in mind, an experiment. You asked the
question "The problem is how do you insure that both sets
of output data are identical in every way?" Maybe one way
to test that is to test the input and output capabilities
of Genesis/Enterprise.
Let's translate a set of gerber back and forth with ODB a
certain number of times (10?) and see how the result
compares to the "reference data" (first generation gerber).
They would have to pass two tests, 1, a netlist check of
course and 2, a layer by layer feature comparison. The
netlist check is absolute, it has to pass. The features
could not vary more than (1?) percent. The feature
variation test is something we would have to come up with.
Is 1% to small or to large?
Ideally the 10th generation ODB would match the 1st
generation gerber by some agreed upon amount and pass a
netlist compare of course.
I don't know how sound this hare-brained idea is, I thunk
it up driving to work... But I think your question is valid
and has to be answered in some way.
Who would do the testing and presenting of the results?
Would you trust Valor? Frontline? IPC? NEMI? Maybe Valor,
a designer and a fabricator at the very least. Heck, I
volunteer to play if that's what it takes to get more ODB.
Regards,
Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]
>-----Original Message-----
>From: Seth Goodman [mailto:[log in to unmask]]
>Sent: Monday, January 28, 2002 6:28 PM
>To: TechNet E-Mail Forum.; Mark Steele
>Subject: RE: [TN] ODB++
>
>
>Hi Mark,
>
>From the design engineer's perspective, supporting two
>different formats
>does create a problem. When you release a design to
>production, it is not
>supposed to be specific to one particular vendor (unless you
>have a captive
>fab shop and NEVER go outside). Unfortunately, not all fab
>shops support
>ODB++. If purchasing would be willing to limit themselves to
>fab shops that
>supported ODB++, that would be fine, but since that limits
>their options it
>is unlikely. So in order to be universal, we would have to
>generate both
>ODB++ and Gerber. This is easy to do but can create subtle
>problems that
>could take lots of time and money to run down. The problem is
>how do you
>insure that both sets of output data are identical in every
>way? While some
>programs allow you to import both data sets and compare, as a practical
>matter, assuring that they are identical is not possible.
>Since there will
>undoubtedly be subtle differences between the two, which one controls?
>Don't we also have to verify and validate both versions by
>building up both
>assemblies? And when problems inevitably arise between boards from two
>different vendors using different data files, who 'ya gonna
>call? Those
>dumb design engineers who created the problem, of course.
***stuff deleted*** (I would like to respond to that in another email.)
>
>Regards,
>
>Seth Goodman
>Goodman Associates, LLC
>tel 608.833.9933
>fax 608.833.9966
>
>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mark Steele
>> Sent: Monday, January 28, 2002 4:09 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] ODB++
>>
>>
>> Hi Paul,
>>
>>
>> I work for Toppan Electronics in San Diego, we are a
>> fab house.
>>
>> We strongly prefer ODB data. I tell our Sales people
>> to beg for it!
>>
>> For the past 2 years we have tracked type of data
>> (274D, 274X and ODB) and problems with that data such
>> as bad aperture lists, missing layers, incorrect
>> filename identification, etc, etc, etc.
>>
>> For example, for the last 226 jobs we have input we had
>> 41 issues with gerber, 0 for ODB. That's a lot of phone
>> calls and time spent just getting the data INTO our Genesis
>> system. We allocate 5 min to get the data and import an
>> ODB job, 30-40 for gerber (sometimes it takes hours for
>> gerber, that happens about once a month...)
>>
>> I realize not everyone uses Genesis as their CAM system, but
>> I would wager that a majority of the bigger fab houses do.
>>
>> So, yes, PLEASE generate ODB as a first choice and only send
>> out gerber if asked too...
>>
>> Of course that's just my opinion, I could be wrong...
>>
>>
>>
>> Mark Steele
>> CAM Automation Engineer
>> Toppan Electronics, Inc.
>> 858.695.2222
>> [log in to unmask]
>
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Date: Wed, 30 Jan 2002 16:47:29 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Blacklight Fixture
X-To: "Peralta, Kevin" <[log in to unmask]>
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hi,
in your backyard (upland) is a company called uvp (ne ultraviolet products). they make a unit called 'blak ray', model b-100a. it's been around at least since the early sixties.
phil
-----Original Message-----
From: PERALTA, Kevin (BREA) [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 1:40 PM
To: [log in to unmask]
Subject: [TN] Blacklight Fixture
Since we've moved to a new facility (w/ a beautiful view of the San Gabriel Mountain Range), we're in need of purchasing a new blacklight fixture for our new Conformal Coating Booth. It's not very long, but I was hoping to get some ideas for the best type of blacklight with a UV rating to put into place. Can anyone serve up some good suggestions? Thank you!
Kevin L. Peralta
TRW Aeronautical / Lucas Aerospace
------_=_NextPart_001_01C1A9F0.DC20D930
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Blacklight Fixture</TITLE>
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<BODY>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff size=2>in
your backyard (upland) is a company called uvp (ne ultraviolet products).
they make a unit called 'blak ray', model b-100a. it's been around at
least since the early sixties.</FONT></SPAN></DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> PERALTA, Kevin (BREA)
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, January 30, 2002
1:40 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Blacklight
Fixture<BR><BR></FONT></DIV>
<P><FONT face=Arial size=2>Since we've moved to a new facility (w/ a beautiful
view of the San Gabriel Mountain Range), we're in need of purchasing a new
blacklight fixture for our new Conformal Coating Booth. It's not very long,
but I was hoping to get some ideas for the best type of blacklight with a UV
rating to put into place. Can anyone serve up some good suggestions? Thank
you!</FONT></P>
<P><FONT face=Arial size=2>Kevin L. Peralta</FONT> <BR><FONT face=Arial
size=2>TRW Aeronautical / Lucas Aerospace</FONT> </P></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Wed, 30 Jan 2002 16:36:20 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: ENIG Thickness Standard?
MIME-Version: 1.0
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Is there a standard for the plating thickness of the ENIG surface
finish? I've searched the archives and didn't find anything. Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches. What (if anything) is considered standard for this finish?
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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=========================================================================
Date: Wed, 30 Jan 2002 22:00:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: AOI Stuff again...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi all!
Bringing up the topic of AOI again. Read the Glenn Woodhouse summary (which I
think was GREAT by the way) that Daan reposted about the state of the
technology, had a fellow engineer that I work with attend a session at APEX
about AOI, and it seems that things may have become a bit cheaper, but as far
as using AOI for solder joint evaluation, there's still much to be desired...
The situation here is that there is some pressure from those above to get a
system in here that will be a fool-proof method to put a piece of equipment
in place that will eliminate the need for human inspection.
My take on it is that one focuses on making sure that the process is right
from the beginning, and then you don't need to spend a bunch of money on
automated inspection equipment, or depend on humans to inspect each and every
solder joint.
The reason I say that is because we are a low volume, high part number shop.
We may have ongoing business for years, but it maybe 10 assemblies a
month...what we consider high volume is a run of 250 assemblies per work
order...hehehe.
I just have the opinion that spending the big bucks for the AOI equipment
doesn't make a whole lot of sense in our situation...we'll be tweeking
programs during the run and probably won't have all the false calls, or
missed defects ironed-out by the time the work order is built...then a month
or two later on the same assembly, you go through the same drill again...
Any thoughts on this?
-Steve Gregory-
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Date: Thu, 31 Jan 2002 11:03:53 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENIG Thickness Standard?
X-To: Rick Thompson <[log in to unmask]>
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Rick,
I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.
Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.
Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.
Peter
Rick Thompson
<rthompson@VENTURAELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] ENIG Thickness Standard?
01/31/02 08:36 AM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
Is there a standard for the plating thickness of the ENIG surface
finish? I've searched the archives and didn't find anything. Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches. What (if anything) is considered standard for this finish?
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Wed, 30 Jan 2002 23:47:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
MIME-Version: 1.0
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Not fond of stripping (either chemical or mechanical removal), both have
pros/cons. If the chemical is strong enough to remove a cured (overcured) UR
than its not doing the components or substrate any good either... It was just
food for thought - will look it up with EMPF.
Regards,
Mike Sewell
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<HTML><FONT FACE=arial,helvetica><FONT COLOR="#8080ff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0"><B>Not fond of stripping (either chemical or mechanical removal), both have pros/cons. If the chemical is strong enough to remove a cured (overcured) UR than its not doing the components or substrate any good either... It was just food for thought - will look it up with EMPF. <BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman" LANG="0"></B><BR>
</FONT></HTML>
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Date: Wed, 30 Jan 2002 23:48:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
MIME-Version: 1.0
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Circuitectctr.com has a good guide on coating removal methods with info re:
each method and a preferred order.
http://www.circuittechctr.com/guides/2-3-1.htm
Regards,
Mike Sewell
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"> <BR>
<BR>
<BR>
</FONT><FONT COLOR="#8080ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"><B>Circuitectctr.com has a good guide on coating removal methods with info re: each method and a preferred order.<BR>
<BR>
http://www.circuittechctr.com/guides/2-3-1.htm<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"></B><BR>
</FONT></HTML>
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Date: Thu, 31 Jan 2002 13:45:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating
X-cc: [log in to unmask]
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Unsubscribe.
Regards,
"TechNet
E-Mail Forum." To: [log in to unmask] AT Internet@ACPPSG
<[log in to unmask] cc: (bcc: Ken Fong/LU Plaza/HK/Astec)
RG> MikeSwll Subject: Re: [TN] Conformal Coating
01/31/02 01:23
PM
Circuitectctr.com has a good guide on coating removal methods with info re:
each method and a preferred order.
http://www.circuittechctr.com/guides/2-3-1.htm
Regards,
Mike Sewell
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"> <BR>
<BR>
<BR>
</FONT><FONT COLOR="#8080ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"><B>Circuitectctr.com has
a good guide on coating removal methods with info re: each method and a preferred order.<BR>
<BR>
http://www.circuittechctr.com/guides/2-3-1.htm<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"></B><BR>
</FONT></HTML>
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Date: Thu, 31 Jan 2002 14:09:29 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
kevinyeah <[log in to unmask]>
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From: kevinyeah <[log in to unmask]>
Subject: Re: Resin Recession
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Date: Thu, 31 Jan 2002 00:24:00 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ODB++
X-To: Mark Steele <[log in to unmask]>
In-Reply-To: <B136A0C653FCD311ABA400508B60DAB19C4BB8@EXCHANGE>
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Hi Mark,
> I assume you are comfortable with your system outputting
> gerber, it's ODB that has to "prove" it can duplicate the
> gerber.
Thanks for bringing this up. I'm not suggesting that ODB++ needs to prove
itself, as its' market share among fab shops tells me that it does the job.
Given the choice, I would also opt for ODB++ as it can carry a lot more than
just bare board information. The problem I have is in archiving any data
object in more than one format for the reasons explained below.
> Here's what I have in mind, an experiment. You asked the
> question "The problem is how do you insure that both sets
> of output data are identical in every way?" Maybe one way
> to test that is to test the input and output capabilities
> of Genesis/Enterprise.
This will test, for one particular data set, the ability of the Valor tool
to translate back and forth between Gerber and ODB++ without accumulating
error. It really shows that their forward and reverse translators are
accurate inverses of each other. It doesn't show that the two data files
produce the same board. Even if we made a test to show that these two data
files were comparable, not very many designers use Valor tools to make their
output files. Instead, we typically use the data file generators built into
our CAD systems. If the CAD system doesn't produce ODB++ directly, and most
don't, then we use a third party tool (I use CAM350) to translate into
ODB++, either from the native CAD file or from Gerbers.
Even if the original CAD tool produced both output formats, the problem
remains. Producing an output file, either Gerber or ODB++, from a native
CAD database is a translation process. It is more difficult, though
fundamentally similar to translating Gerber into ODB++. In both cases, some
program looks at a series of data objects and translates them into another
series of data objects of a different format. That program is written by
human beings and therefore it has bugs. I have yet to own a piece of
bug-free software. The software that produces ODB++ is not the same as the
software that produces Gerber. It most likely has different bugs. My point
is that the two output files will not be exactly the same.
I know from experience that there are flaws in the Gerber data generators in
most CAD programs. The nastier ones are history but some subtle ones
remain. Similarly, different Gerber viewers can display the same data file
differently. Occasionally, I have to spend a lot of time working with a fab
shop because their Gerber viewers and my Gerber viewers show different
results from the same data. This is an unfortunate waste of both my time
and theirs, but it has to be done. Because we don't use the same brand and
version of software, it is unavoidable.
What I want to avoid is dealing with problems in ODB++ data in addition to
Gerber data. Also, consider that if ODB++ becomes the Gerber replacement,
there will be companies other than Valor writing software for it. That
means there will be some differences between how a Valor program and someone
else's program interprets the same ODB++ data. This may not come up very
often, but it will come up, especially when other vendors first start using
ODB++. Unless Valor achieves a 100% market share, we will all have to deal
with some subtle differences between vendors' software. This problem could
be lessened if an independent industry group produced a validation suite
that a program would have to pass to call itself ODB++ compliant.
I would be happy to support ODB++ as the single output format for any given
board. In fact, I would prefer almost any intelligent data format to
Gerber, which is truly a rotten old standard. But until my customers'
purchasing departments will accept ODB++ only, the only "universal" option
today is Gerber. Until ODB++ becomes as universally accepted by fab shops
as Gerber, or the fab shops start to give a big enough discount to offset
the extra costs of supporting two data formats, IMO most designers will opt
to stay with Gerber. If using ODB++ really saves the fab shops money, and
I'm sure it does, all they have to do is pass some of those savings on to
their customers who use it and it will become the de facto standard before
you know it.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
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Date: Thu, 31 Jan 2002 09:15:53 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guenter Grossmann <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] Wave Solder/NoPb Question
Mime-Version: 1.0
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Dave
We run trials with folks from ERSA. Actually, due to their knowledge, =
erosion of the solderpot, the wave-nozzle, and the pump are considerable. =
However, new equipment seem to be produced lead-free save with coated =
stainless steel. It seems also as if it is possible to cover the parts in =
danger with a organic coating (paint) which can be done during the =
downtime when a service is done. The coating needs a refreshment every one =
or two years I heard though one line with that coating seems to run now =
three years in 24 hours shift without problems. What we also looked at are =
upgrade kits for older equipment. I am right now writing a cost- evaluation=
.
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Thu, 31 Jan 2002 09:24:50 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Julian Coates <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Julian Coates <[log in to unmask]>
Subject: Re: ODB++
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Hi All,
I am from Valor, I should state that up front, but I would like to offer two
points for consideration:
1. In the mid-1980's the mainstream PCB manufacturers began to accept Gerber
(instead of film) into their tooling departments. In order to do this, they
had to make capital investments. These investments gave them a competitive
advantage, because they were able to cut costs overall, reduce lot-size due
to faster tooling cycles, and increase quality. Despite this, for many
years, the OEMs (their customers) continued to send the design to the
fabricator in two formats; Gerber, and film. The film was regarded as the
reference and ultimate specification of the design, but the fabricator could
use the Gerber if he so chose (those who could, did). What is going on now
between Gerber and ODB++ is basically the same, a transition of formats
which have uncertainties between them, and for each design somewhere down
the line somebody has to decide which format to believe in and work from. In
the case of Gerber, it took a few years for the average fabricator to have
unconditional confidence in the data rather than the film. These days, they
do not receive films at all, and they just work from the Gerber without a
second thought of what became of the film. In the case of ODB++, many
fabricators already have tools (as do the designers by the way) to compare
the graphics and netlist interconnect of the ODB++ versus the Gerber in an
automated fashion, reducing the risks substantially. The upside (as Mark
points out) is faster throughput and higher quality. The question is: who is
the beneficiary? The ultimate beneficiary of these gains is the consumer
(the designer), via the competitive business model of the
fabrication-outsourcing. From my observation, most fabricators do not
recover their actual tooling costs in the charges they make to the customers
anyway (they bury their tooling costs in their overheads), so it is probably
unrealistic to expect PCB fabricators to give tooling price-cuts to the
customers, since they are running their tooling operations at a loss
already. However, there are gains for the customer, albeit indirect: further
reduction in average delivery times, and higher quality over time; prices
are dropping anyway. To turn it around, if the designers continue to send
Gerber, the level of service received from the manufacturers could not
improve so fast as it can with a smarter interchange format.
2. Seth makes a good point about validation of ODB++ input and output
processors. Currently, ODB++ is not a formal standard, though we believe it
will be in good time (thanks to the industry-driven NEMI process). When the
formal standardization occurs, we hope that some independent
compliance-validation service will be offered by the standards-body. Just as
a side note, independent compliance-proving by an independent body never
happened (as far as I know) with Gerber RS274D, and RS274X never was a
standard anyway, the industry just went ahead and implemented the format
widely, though with considerable variation, as Seth points out. Between now
and formal standardisation of ODB++ or some further-developed version, Valor
offers a service of supporting third parties who implement ODB++, via its
3rd-party cooperation program, the "Open Systems Alliance". We do our best
to offer advice and support for interface testing to all organisations,
competitive or non-competitive, so that the format has the best chance of
practical implementation. Some 3rd-parties opt to stay away from this
service due to competitive reasons, which usually (in our view) results in
sub-standard implementation of the format, which is a pity. Those who join
get full support.
After many years of quasi-stability with Gerber, the industry is in
transition again. I do not sure that there is any clear way of accelerating
the shift to a new CAD/CAM format with price-breaks from the manufacturers
(fabrication or assembly), since they are all bleeding cash right now
anyway. The transition will happen steadily, and be driven top-down by more
subtle, but more powerful, factors such as time and quality.
I hope these comment contribute to the debate in a positive way, as
intended.
Julian Coates
Valor
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Seth Goodman
Sent: 31 January 2002 06:24
To: [log in to unmask]
Subject: Re: [TN] ODB++
Hi Mark,
> I assume you are comfortable with your system outputting
> gerber, it's ODB that has to "prove" it can duplicate the
> gerber.
Thanks for bringing this up. I'm not suggesting that ODB++ needs to prove
itself, as its' market share among fab shops tells me that it does the job.
Given the choice, I would also opt for ODB++ as it can carry a lot more than
just bare board information. The problem I have is in archiving any data
object in more than one format for the reasons explained below.
> Here's what I have in mind, an experiment. You asked the
> question "The problem is how do you insure that both sets
> of output data are identical in every way?" Maybe one way
> to test that is to test the input and output capabilities
> of Genesis/Enterprise.
This will test, for one particular data set, the ability of the Valor tool
to translate back and forth between Gerber and ODB++ without accumulating
error. It really shows that their forward and reverse translators are
accurate inverses of each other. It doesn't show that the two data files
produce the same board. Even if we made a test to show that these two data
files were comparable, not very many designers use Valor tools to make their
output files. Instead, we typically use the data file generators built into
our CAD systems. If the CAD system doesn't produce ODB++ directly, and most
don't, then we use a third party tool (I use CAM350) to translate into
ODB++, either from the native CAD file or from Gerbers.
Even if the original CAD tool produced both output formats, the problem
remains. Producing an output file, either Gerber or ODB++, from a native
CAD database is a translation process. It is more difficult, though
fundamentally similar to translating Gerber into ODB++. In both cases, some
program looks at a series of data objects and translates them into another
series of data objects of a different format. That program is written by
human beings and therefore it has bugs. I have yet to own a piece of
bug-free software. The software that produces ODB++ is not the same as the
software that produces Gerber. It most likely has different bugs. My point
is that the two output files will not be exactly the same.
I know from experience that there are flaws in the Gerber data generators in
most CAD programs. The nastier ones are history but some subtle ones
remain. Similarly, different Gerber viewers can display the same data file
differently. Occasionally, I have to spend a lot of time working with a fab
shop because their Gerber viewers and my Gerber viewers show different
results from the same data. This is an unfortunate waste of both my time
and theirs, but it has to be done. Because we don't use the same brand and
version of software, it is unavoidable.
What I want to avoid is dealing with problems in ODB++ data in addition to
Gerber data. Also, consider that if ODB++ becomes the Gerber replacement,
there will be companies other than Valor writing software for it. That
means there will be some differences between how a Valor program and someone
else's program interprets the same ODB++ data. This may not come up very
often, but it will come up, especially when other vendors first start using
ODB++. Unless Valor achieves a 100% market share, we will all have to deal
with some subtle differences between vendors' software. This problem could
be lessened if an independent industry group produced a validation suite
that a program would have to pass to call itself ODB++ compliant.
I would be happy to support ODB++ as the single output format for any given
board. In fact, I would prefer almost any intelligent data format to
Gerber, which is truly a rotten old standard. But until my customers'
purchasing departments will accept ODB++ only, the only "universal" option
today is Gerber. Until ODB++ becomes as universally accepted by fab shops
as Gerber, or the fab shops start to give a big enough discount to offset
the extra costs of supporting two data formats, IMO most designers will opt
to stay with Gerber. If using ODB++ really saves the fab shops money, and
I'm sure it does, all they have to do is pass some of those savings on to
their customers who use it and it will become the de facto standard before
you know it.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
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Date: Thu, 31 Jan 2002 05:40:32 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ODB++
X-To: Julian Coates <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Hi Julian,
You make some very good points and I hope that ODB++, or something very much
like it eventually replaces Gerber. Your arguments aren't specific to
Valor, so that's not an issue at all. I'd like to mention a couple of areas
where we view things a little differently.
In comparing the previous transition from film to Gerber to the imminent
transition from Gerber to an intelligent format, the analogy is not as
strong as you imply. In the transition from film to Gerber, there were
rarely any differences between the two, at least once people learned how to
take care of their photoplotters. This is not surprising, since the early
photoplotters came from the same company that wrote the standard! Even so,
the engineering groups I ran during that period only archived one format of
data. When we changed over from film to Gerber, only the Gerbers were
archived. We added the additional process step, as did many groups back
then, of approving the film plots from the board vendor. This was not to
check for improper interpretation of the Gerber data by the photoplotter, it
was to check that the Gerber data represented the native CAD data properly.
For us, these approval films were really check plots that verified the
Gerber generator in the CAD software. Many board vendors required the
customer to approve the films before fabrication anyway. If I recall
correctly, it was a number of years before affordable Gerber viewers
appeared. After using those for a while, the vendors no longer required our
sign-off on films and we were confident enough to not require it either.
The coming transition is a bit more dicey. We're talking about changing
from a simple, dumb format to a complex hierarchical one. The complexity of
the software to generate and read this new format is much higher than for
Gerber. We can therefore expect more software problems than with the
previous transition. I would like to know what are the tools many designers
currently have, that you mentioned, to compare Gerber and ODB++. If they're
affordable, I'd like to try them out. Obviously the fabricators can do this
task but their software costs more than most CAD packages we use to design
the boards, so that is a barrier.
While we could also use high-end CAM software to improve our design quality
by eliminating slivers, acid traps, etc., the situation is the same as I
mentioned before: the board vendors already do this for us and are not
offering reduced prices if we take on that part of the job. The end-product
quality is the same, it's just a question of who does the work. Likewise,
they are not offering improved turnaround times. They are not even telling
us they are considering such policies. This is a very tough sell to top
management who want to know how much it will pay back and when.
Remember that when we switched from film to Gerber, many fabrication shops
bought their own photoplotters and quickly reduced or eliminated
photoplotting charges. The company I worked for at the time was able to
junk our photoplotter and darkroom, reclaim the space they occupied and put
the operator to better use as a PCB layout person. Similarly, when we
stopped requiring sign-off on films, our turnaround times improved
instantly. If an investment of time and money today won't lower our board
prices, shorten the turnaround time or improve quality, it would be more
accurate to call it a donation.
I'm still very much in favor of adopting an intelligent data format. But it
has to be driven by economics. The return has to be at least in the
foreseeable future. The fab shops are apparently not yet able to make it
profitable for us to make the change. Hopefully, that situation will
change.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: Julian Coates [mailto:[log in to unmask]]
> Sent: Thursday, January 31, 2002 3:25 AM
> To: [log in to unmask]; [log in to unmask]
> Subject: RE: [TN] ODB++
>
>
> Hi All,
>
> I am from Valor, I should state that up front, but I would like
> to offer two
> points for consideration:
>
> 1. In the mid-1980's the mainstream PCB manufacturers began to
> accept Gerber
> (instead of film) into their tooling departments. In order to do
> this, they
> had to make capital investments. These investments gave them a competitive
> advantage, because they were able to cut costs overall, reduce
> lot-size due
> to faster tooling cycles, and increase quality. Despite this, for many
> years, the OEMs (their customers) continued to send the design to the
> fabricator in two formats; Gerber, and film. The film was regarded as the
> reference and ultimate specification of the design, but the
> fabricator could
> use the Gerber if he so chose (those who could, did). What is going on now
> between Gerber and ODB++ is basically the same, a transition of formats
> which have uncertainties between them, and for each design somewhere down
> the line somebody has to decide which format to believe in and
> work from. In
> the case of Gerber, it took a few years for the average fabricator to have
> unconditional confidence in the data rather than the film. These
> days, they
> do not receive films at all, and they just work from the Gerber without a
> second thought of what became of the film. In the case of ODB++, many
> fabricators already have tools (as do the designers by the way) to compare
> the graphics and netlist interconnect of the ODB++ versus the Gerber in an
> automated fashion, reducing the risks substantially. The upside (as Mark
> points out) is faster throughput and higher quality. The question
> is: who is
> the beneficiary? The ultimate beneficiary of these gains is the consumer
> (the designer), via the competitive business model of the
> fabrication-outsourcing. From my observation, most fabricators do not
> recover their actual tooling costs in the charges they make to
> the customers
> anyway (they bury their tooling costs in their overheads), so it
> is probably
> unrealistic to expect PCB fabricators to give tooling price-cuts to the
> customers, since they are running their tooling operations at a loss
> already. However, there are gains for the customer, albeit
> indirect: further
> reduction in average delivery times, and higher quality over time; prices
> are dropping anyway. To turn it around, if the designers continue to send
> Gerber, the level of service received from the manufacturers could not
> improve so fast as it can with a smarter interchange format.
>
> 2. Seth makes a good point about validation of ODB++ input and output
> processors. Currently, ODB++ is not a formal standard, though we
> believe it
> will be in good time (thanks to the industry-driven NEMI
> process). When the
> formal standardization occurs, we hope that some independent
> compliance-validation service will be offered by the
> standards-body. Just as
> a side note, independent compliance-proving by an independent body never
> happened (as far as I know) with Gerber RS274D, and RS274X never was a
> standard anyway, the industry just went ahead and implemented the format
> widely, though with considerable variation, as Seth points out.
> Between now
> and formal standardisation of ODB++ or some further-developed
> version, Valor
> offers a service of supporting third parties who implement ODB++, via its
> 3rd-party cooperation program, the "Open Systems Alliance". We do our best
> to offer advice and support for interface testing to all organisations,
> competitive or non-competitive, so that the format has the best chance of
> practical implementation. Some 3rd-parties opt to stay away from this
> service due to competitive reasons, which usually (in our view) results in
> sub-standard implementation of the format, which is a pity. Those who join
> get full support.
>
> After many years of quasi-stability with Gerber, the industry is in
> transition again. I do not sure that there is any clear way of
> accelerating
> the shift to a new CAD/CAM format with price-breaks from the manufacturers
> (fabrication or assembly), since they are all bleeding cash right now
> anyway. The transition will happen steadily, and be driven
> top-down by more
> subtle, but more powerful, factors such as time and quality.
>
> I hope these comment contribute to the debate in a positive way, as
> intended.
>
> Julian Coates
> Valor
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=========================================================================
Date: Thu, 31 Jan 2002 10:46:07 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Swanson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Swanson <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Doug,
I believe that some suppliers of this kind of equipment have dealt
successfully with this issue (conductive media, ionisation, etc). See
http://www.ccrco.com, for example.
Regards,
Peter
--
=========================================================
Peter Swanson [log in to unmask]
INTERTRONICS http://www.intertronics.co.uk
INTERTRONICS is dedicated to providing quality material,
consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
the highest levels of technical support and customer
service.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: 30 January 2002 21:27
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating
Mike Sewell Suggests: Would microabrasive blasting of the coating be an
alternative to chemical stripping?
*Just be aware that microabrasive blasting generates a hell of a static
charge. Enough to kill a static sensitive component. I think the EMPF did
some work in microabrasion methods relative to ESD in the late 80s early
90s. Check with the librarian at www.empf.org.
Doug Pauls
Rockwell Collins
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Date: Thu, 31 Jan 2002 07:18:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: CERAMIC CSP'S and a MoonMan adventure out of the cave again
Folks,
I have been reviewing all the issues/problems that were faced by my host
company and its supplier ? before I arrived. I would like to share some for
comment as well as my observations, if you would be so kind.
We have one board design using seven .8 mm ceramic CSP?s made by TI. The
first issue facing my company was cracking or separation of balls from the
device. I have reports from Rockwell, who did the F/A and from TI both
pointing to the failure mechanism as possible excessive IMC formation as in
the following without the photos, of course:
Attached are four photos:
CSP-1 shows multiple insertions into sockets.
CSP-2 shows x-section of stock unit
CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
appears thick.
CSP-4 shows x-section of device which broke off the PCB - clean break at the
intermetallic layer.
Because of the multiple insertions into sockets, as evidenced by
indentations on the balls, it is considered that multiple thermal excursions
contributed to IMC growth. As the clean break occurred at the IMC interface,
again, this is thought to be the failure mechanism. This may be so, but
other things must be considered as well.
This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
no repeat of this occurrence. No reason is available to me, at least,
concerning the part?s improvement. No matter, there now exist other issues.
I believe, as in a few comment trades, with others (Dave Fish for one), that
our assembler?s inexperience profiling and soldering these devices has been
responsible for poor quality/reliability solder joints. In their defense,
there aren?t/weren?t many suppliers with this experience. Simply, cold
solder joints probably contributed to unacceptability and complete failure
as received ? evidenced by the infamous "C" clamp. The ceramic portion of
the device is extremely massive compared to ball size and the ability to get
required heat to the solder medium and balls to effect acceptable solder
joints. This means, I believe based on past experience, the reflow profile
must be "maxed" out in terms of solder paste performance and joint
formation. I don?t think this was done.
To add to the situation, the CTE mis-match of ceramic and PCB material
certainly has been known to ruin even good solder joints. This may account
to the failure at the IMC interface as well as at the board level.
Therefore, a "too thick" IMC layer probably is/was not the failure
mechanism, or was it?
All solder pads have been re-evaluated and now definitely meet alignment and
size requirements. Stencil apertures are as specified. Solder paste now is
Kester?s 562R, solder volume is acceptable, surface solderability is as
required. What remains is developing a solder reflow profile that will
effect acceptable solder joints for the CSP?s as well as all other devices
on the board.
I realize this should not be a big issue, but having had to go way back to
visit initial failures at the device ball interface, I have some concerns
about whoever builds our next lot of boards. Steve, are you listening.
I would appreciate any comments concerning this small part of the picture. I
would appreciate anyone sharing experiences with what should be another BGA
success story but for what I have presented here.
Thank you all much,
Earl
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Date: Thu, 31 Jan 2002 08:34:11 -0500
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gerard O'Brien <[log in to unmask]>
Organization: Photocircuits Corporation
Subject: Re: ENIG Thickness Standard?
X-To: "[log in to unmask]" <[log in to unmask]>
As co-chairman of the 4552 committee, I must take exception to your
comment" It does not contain a
lot of useful detail". For this specification extensive testing was
performed and data presented , paper appeared in the last issue of IPC
review as well as in the Orlando fall conference. The specification for
ENIG is 2 micro inches minimum Au at -4 sigma from the mean and 120 to
240 microinches for the nickel. As a point of note, I tested two days ago
samples from two of the five vendors that supplied samples for wetting
balance testing that were used to generate this specification. The samples
are now 14 months old (they have been lying around my office not protected)
and for the test we had them plated with 1 microinch of gold. THEY STILL
SOLDER AND PASS ALL WETTING BALANCE CRITERIA!!! The degree of porosity at 1
microinch is obviously greater than at 5 microinches however the protection
afforded the underlying nickel is still excellent, solderability testing
was with a ROL0 type flux per j-std 004.
It is intention of the 4552 committee to publish the total data set as a TR
report.
If anyone would like a copy of testing specifics or a copy of a specific
test data set - XRF , wetting balance, contact resistance , please feel
free to contact myself, George Milad -chairman of the committee or Tom
Newton at the IPC
Regards
Gerard O'Brien
Photocircuits Corp.
-----Original Message-----
From: [log in to unmask] [SMTP:[log in to unmask]]
Sent: Wednesday, January 30, 2002 10:04 PM
To: [log in to unmask]
Subject: Re: [TN] ENIG Thickness Standard?
Rick,
I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.
Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.
Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.
Peter
Rick Thompson
<rthompson@VENTURAELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] ENIG
Thickness Standard?
01/31/02 08:36 AM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
Is there a standard for the plating thickness of the ENIG surface
finish? I've searched the archives and didn't find anything. Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches. What (if anything) is considered standard for this finish?
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Thu, 31 Jan 2002 08:43:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marion A. Graybeal" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marion A. Graybeal" <[log in to unmask]>
Subject: Re: ENIG Thickness Standard?
X-To: Rick Thompson <[log in to unmask]>
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Rick,
The IPC spec for ENIG, which is near release, specifies 120-240
microinches of Ni and 2-4 microinches of Au.
Marion Graybeal
----- Original Message -----
From: Rick Thompson <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 7:36 PM
Subject: [TN] ENIG Thickness Standard?
> Is there a standard for the plating thickness of the ENIG surface
> finish? I've searched the archives and didn't find anything. Based on
> a customer request we had increased the requirement for the electroless
> nickel to 200u inches. A couple of our board vendors are telling me that
> that is excessive and that anything over 100u inches is overkill. I've
> seen references in the archives for anything from 120u inches to 200u
> inches. What (if anything) is considered standard for this finish?
>
> Thanks for your inputs.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
> --------------------------------------------------------------------------
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Date: Thu, 31 Jan 2002 08:49:34 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ODB++ ... or GenCAM?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_a9.22238cfe.298aa56e_boundary"
--part1_a9.22238cfe.298aa56e_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Good day to all,
It seems that IPC GenCAM is missing from this discussion. 25 years or so of
group effort to develop a generic industry standard sitting on the sidelines
in this dialog.
The following is taken from the forum sponsors website
"...Establishes the capability for a single ANSI STD datafile format to
transfer data to all disciplines in the PCB supply chain.
...Provides for complete transfer of test data and electrical test parameters.
...Can accommodate several BOM descriptions in a single data file.
...Brings your design into close contact with DFM issues."
Has anyone taken it for a lap? Is (are) there a reason(s) for its absence in
this dialog?
Best to all,
Joe
--part1_a9.22238cfe.298aa56e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Good day to all,
<BR>
<BR>It seems that IPC GenCAM is missing from this discussion. 25 years or so of group effort to develop a generic industry standard sitting on the sidelines in this dialog.
<BR>
<BR>The following is taken from the forum sponsors website
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0">"...Establishes the capability for a single ANSI STD datafile format to transfer data to all disciplines in the PCB supply chain.
<BR>
<BR>...Provides for complete transfer of test data and electrical test parameters.
<BR>
<BR>...Can accommodate several BOM descriptions in a single data file.
<BR>
<BR>...Brings your design into close contact with DFM issues."
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Has anyone taken it for a lap? Is (are) there a reason(s) for its absence in this dialog? </FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0">
<BR>
<BR>Best to all,
<BR>Joe</FONT></HTML>
--part1_a9.22238cfe.298aa56e_boundary--
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Date: Thu, 31 Jan 2002 08:19:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: AOI Stuff again...
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I work for a CM with high mix low runs. We use an AOI right now. I find =
that one aspect of AOI that has really reduced labor was the first article =
process for component id and placement. We spend a lot of labor for the =
first board to confirm correct part and alignment from pick and place. We =
also do the same process if we use a Final Inspection. Having the machine =
to do this is much, much faster which gives a quicker set-up and run =
approvals. =20
As far as solder joints I agree the AOI leaves a lot to be desired. It =
does good with shorts but insufficient and no solders are dependent on =
device. Like a "J" lead or a QFP it just doesn't do well. But non =
solders on discretes are pretty good. =20
As with most equipment made to make our lives easier and less of us needed =
it has it's limitations but what it can do it does well. =20
Kathy=20
--=_CE93A691.9BFA979C
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I work for a CM with high mix low runs. We use an AOI right
now. I find that one aspect of AOI that has really reduced labor was the
first article process for component id and placement. We spend a lot of
labor for the first board to confirm correct part and alignment from pick and
place. We also do the same process if we use a Final Inspection.
Having the machine to do this is much, much faster which gives a quicker set-up
and run approvals. </DIV>
<DIV> </DIV>
<DIV>As far as solder joints I agree the AOI leaves a lot to be desired.
It does good with shorts but insufficient and no solders are dependent on
device. Like a "J" lead or a QFP it just doesn't do well. But non
solders on discretes are pretty good. </DIV>
<DIV> </DIV>
<DIV>As with most equipment made to make our lives easier and less of us needed
it has it's limitations but what it can do it does well. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 31 Jan 2002 08:27:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: AOI Stuff again...
X-To: [log in to unmask]
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Aaaaah Steve,
I believe you're in the same boat I was in around two years ago. We were =
building assemblies (down-hole, oilfield & class 3 medical (implantable)) =
and we were having major quality concerns. Products were going out the =
door missing components, being damaged from rework, etc. and it would've =
been a saving grace to have AOI capabilities. Alas, it was not to be. We =
didn't have the money for such elaborate systems. Any way, I don't know =
how to answer your question. You either use your available human eyes or =
buy a machine and hope it can pay for itself. You can also request from =
customers for "golden boards", fully populated, to use for programming =
prior to build. If you need leads on good systems, here's a few:
Agilent (MVT) - Agilent bought MVT and is making a real nice system. Don't =
know much about it, just know MVT had a good system, just not enough cash =
to improve and market it broadly.
Cyberoptics - Don't know much about it. Only that it can configured either =
as a paste inspection machine or post-reflow AOI.
Orbotech - We had a few in Alabama and they're very nice, just a tad =
difficult to program.
Or you can do like me and get an Agilent 5DX and have fun immersing =
yourself in the complex task of programming (it dang sure ain't cost-effect=
ive for your needs, though).
Hope this helps
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
>>> [log in to unmask] 01/30/02 09:00PM >>>
Hi all!
Bringing up the topic of AOI again. Read the Glenn Woodhouse summary =
(which I
think was GREAT by the way) that Daan reposted about the state of the
technology, had a fellow engineer that I work with attend a session at =
APEX
about AOI, and it seems that things may have become a bit cheaper, but as =
far
as using AOI for solder joint evaluation, there's still much to be =
desired...
The situation here is that there is some pressure from those above to get =
a
system in here that will be a fool-proof method to put a piece of =
equipment
in place that will eliminate the need for human inspection.
My take on it is that one focuses on making sure that the process is right
from the beginning, and then you don't need to spend a bunch of money on
automated inspection equipment, or depend on humans to inspect each and =
every
solder joint.
The reason I say that is because we are a low volume, high part number =
shop.
We may have ongoing business for years, but it maybe 10 assemblies a
month...what we consider high volume is a run of 250 assemblies per work
order...hehehe.
I just have the opinion that spending the big bucks for the AOI equipment
doesn't make a whole lot of sense in our situation...we'll be tweeking
programs during the run and probably won't have all the false calls, or
missed defects ironed-out by the time the work order is built...then a =
month
or two later on the same assembly, you go through the same drill again...
Any thoughts on this?
-Steve Gregory-
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Date: Thu, 31 Jan 2002 08:36:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENIG Thickness Standard?
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Good Morning TechNet! Rick, I have a very different perspective on ENIG
than Peter so here is some food for thought. There is a specification for
ENIG - IPC-4552 - which is in final ballot and should be release in the
March/May timeframe. I recommend getting a copy. It's my opinion that the
specification is quite useful considering there is no other specification
available for industry use. The ASTM B488 specification is not a workable
solution for electronics applications. There was a great deal of committee
discussion on the electroless nickel plating thickness. The nickel
thickness is very much viewed as application specific, for example, RF
designers desire minimal thickness (30-50 uinches) as opposed to connecting
applications which use 200 uinches. Rockwell Collins is successfully using
2-5 uninches for the immersion gold thickness and 50-150 uinches for the
electroless nickel thickness in avionics applications and we intend on
using the IPC-4552 specification in our documentation. Additionally, 50
uinches of electroless nickel is very adequate as a diffusion barrier as
both the nickel/copper and nickel/gold phase diagrams demonstrate a wide
range of immiscibility The only instances I have seen a 50 uinch
electroless nickel thickness not be adequate was for pwbs which were
subjected to repetitive thermal excursions (e.g. lots of rework, or 4
reflow passes). Using an immersion gold thickness of 6 uinches will not
guarantee you solderability - the 4552 committee demonstrated that (by
conducting testing) that 2 uinches of immersion gold can be steam
conditioned and still provide expected solderability coverage. Teaming with
your ENIG vendor, understanding their plating process control practices and
requiring some level of solderability testing is the best way of insuring
solderability. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
[log in to unmask]@ipc.org> on 01/30/2002 09:03:53 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to [log in to unmask]
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] ENIG Thickness Standard?
Rick,
I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.
Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.
Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.
Peter
Rick Thompson
<rthompson@VENTURAELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] ENIG
Thickness Standard?
01/31/02 08:36 AM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
Is there a standard for the plating thickness of the ENIG surface
finish? I've searched the archives and didn't find anything. Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches. What (if anything) is considered standard for this finish?
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Thu, 31 Jan 2002 08:49:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Antw: [TN] Wave Solder/NoPb Question
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Guenter! Great information! One additional question - do you know if
the molten tin attack is more severe on base stainless steel alloys such as
the 301-304 alloy series or are the microalloyed 316/321/347 alloy series
equally attacked? Also, I have always made the assumption that titanium
with its tough natural oxide would be pretty immune to molten tin attack
but don't have any experience or data to back that up. I know that some of
the equipment vendors use titanium in the wave equipment but haven't seen
any information of molten tin attack.
Dave
Guenter Grossmann <[log in to unmask]>@ipc.org> on 01/31/2002
02:15:53 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Guenter Grossmann <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Antw: [TN] Wave Solder/NoPb Question
Dave
We run trials with folks from ERSA. Actually, due to their knowledge,
erosion of the solderpot, the wave-nozzle, and the pump are considerable.
However, new equipment seem to be produced lead-free save with coated
stainless steel. It seems also as if it is possible to cover the parts in
danger with a organic coating (paint) which can be done during the downtime
when a service is done. The coating needs a refreshment every one or two
years I heard though one line with that coating seems to run now three
years in 24 hours shift without problems. What we also looked at are
upgrade kits for older equipment. I am right now writing a cost-
evaluation.
Guenter
.
EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Thu, 31 Jan 2002 15:13:43 -0000
Reply-To: Dougal Stewart <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: pulse plating - without additives
X-To: Adam Seychell <[log in to unmask]>
MIME-Version: 1.0
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I don't know whether this is a cynical remark (as if), but none of the
chemistry suppliers have ever promoted pulse plating with copper without
additives. In all the years I have had experience with acid copper pulse
plating (and Exacta led the way) it has been notable that simpler forms of
plating chemistry (ie with carrier and brightener, but NO leveller) worked
best. I have had long discussions with Jack Josefowicz from Tyco on the
subject, and I would suggest that he would be an authority on whether it is
possible.
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Adam Seychell" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 8:09 AM
Subject: [TN] pulse plating - without additives
> Hello platers. I am hoping someone here can share a few words
> of wisdom about reverse pulse plating. I'm having difficulty
> finding detailed information on the subject, as my local university
> library showed to carry almost nothing. It seems that the
> literature on reverse pulse plating is bound to research papers
> only (which I latter learned can be quite costly and time
> consuming to obtain). What I like to know is a method of plating
> "standard" printed circuit boards in acid copper bath *without*
> the use of additives. Pulse plating without additives has been
> done or so I've been told, however most documents I have
> read only talk about baths containing additives.
>
> Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
> would produce a rough and grainy deposit, especially when
> thickness' become high ( >35 um). The problem is aggravated by
> increasing current density. Even at current densities of
> 0.5A/dm2 the deposits still remain unacceptable. This is
> something I have observed through experimentation.
>
> A test panel was plated using reverse pulse technique to see
> what effect it had compared to DC plating at an equivalent
> average current density. Not having a proper pulse plating power
> supply I constructed my own basic one, using standard DC supply
> and an electronic circuit to periodically reverse the output. The
> parameters of the plating were:
>
> forward time = 5 ms
> reverse time = 1.7 ms
> forward & reverse current densities = 3 A/dm2
> average current density = 1.5 A/dm2
>
> The pulse plating deposits were only slightly improved over DC
> plating. A rough and crystalline surface was clearly visible under a
> 40X microscope. This does not sound promising and I am hoping
> this is due to incorrect characteristics of the current pulse. Most
> reverse pulse plating systems tend to use forward/reverse current
> ratios of around 3, forward times of 10~20ms and reverse times
> 1~2ms. Is important for the current reverse pulse to be short and
> high ?
>
> If anyone could guide me to right path I'd be greatly thankful. If
> there is no such thing as additive free copper plating for PC
> fabrication then kindly let me know as this could save me lot of
> time doing what others have already attempted.
>
> regards,
>
> Adam Seychell.
>
> --------------------------------------------------------------------------
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Date: Thu, 31 Jan 2002 07:19:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: AOI Stuff again...
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Steve,
We've been using AOI in a similar environment for about 18 months. While
there is a somewhat constant 'tweaking' effort adjusting for part and
vendor changes, we still have found it more efficient than simply doing
visual inspection. Stepping through and adjusting for false calls and
changes is still significantly faster than visual inspection as well as
being more consistent. Yes, process control is the obvious way to go,
but stuff happens <g>. We've seen a significant decrease in customer
return rates since putting it in place. With the data collection, it
also allows us to pinpoint specific problem areas and address them on
the line, thus improving overall yield.
That said, it did not allow us to eliminate an inspector. For one thing,
you need someone to run the machine and maintain programs. There's also
the defect classes that aren't readily detectable in AOI. Solder
inspection is still a very 'iffy' area in my opinion. Despite
manufacturer's claims, I haven't seen any solder inspection that's
really effective. I know there are some vector based systems that
supposedly increase the ability to define and inspect solder joints but
there are so many areas that are difficult or impossible to view
adequately that solder inspection with the AOI systems I've seen is a
hit or miss proposition. What we have found is that certain types of
solder inspection is useful for verifying product. The main thing is
that it has allowed our inspectors to concentrate on the areas that
aren't inspectable with AOI, like through-hole parts, connectors, etc.
Regards,
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of [log in to unmask]
Sent: Wednesday, January 30, 2002 7:00 PM
To: [log in to unmask]
Subject: [TN] AOI Stuff again...
Hi all!
Bringing up the topic of AOI again. Read the Glenn Woodhouse summary
(which I think was GREAT by the way) that Daan reposted about the state
of the technology, had a fellow engineer that I work with attend a
session at APEX about AOI, and it seems that things may have become a
bit cheaper, but as far as using AOI for solder joint evaluation,
there's still much to be desired...
The situation here is that there is some pressure from those above to
get a system in here that will be a fool-proof method to put a piece of
equipment in place that will eliminate the need for human inspection.
My take on it is that one focuses on making sure that the process is
right from the beginning, and then you don't need to spend a bunch of
money on automated inspection equipment, or depend on humans to inspect
each and every solder joint.
The reason I say that is because we are a low volume, high part number
shop. We may have ongoing business for years, but it maybe 10 assemblies
a month...what we consider high volume is a run of 250 assemblies per
work order...hehehe.
I just have the opinion that spending the big bucks for the AOI
equipment doesn't make a whole lot of sense in our situation...we'll be
tweeking programs during the run and probably won't have all the false
calls, or missed defects ironed-out by the time the work order is
built...then a month or two later on the same assembly, you go through
the same drill again...
Any thoughts on this?
-Steve Gregory-
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Date: Thu, 31 Jan 2002 08:35:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Denis Lefebvre <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: ODB++ or GenCAM or IPC-350?
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: multipart/alternative;
boundary="=====================_266668889==_.ALT"
--=====================_266668889==_.ALT
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From a designers point of view:
Even before the advent of GENCAM was IPC's effort with IPC-350. In fact,
that is where CAM350 got it's name. The original intent of that application
was to output the "new" industry standard data format, IPC-350. This later
gave way to GENCAM which has now stepped aside (or- been pushed aside) for
ODB++.
The impetus to develop an industry standard data exchange format has been
around for over a decade.
So, what is standing the way? EDA software companies!
Imagine the convenience designers would experience if there was a data
format that could be easily exchanged between design platforms! Good God,
could this have any effect on market share? I think not.. but I believe
that is the fear held by the EDA vendors. It will surely be a cold day when
a standard data format will be supported by vendors of PCB design
applications. I am convinced this function will continue to be relegated to
applications that are in the CAM arena and will remain a post-processing
function for the designer.
The objectives Joe listed below were shared by the IPC-350 effort as well.
Denis Lefebvre, C.I.D.
Senior PCB Designer
Finisar Corporation
(408)542-3832
http://www.finisar.com
At 08:49 AM 1/31/2002 -0500, you wrote:
>Good day to all,
>
>It seems that IPC GenCAM is missing from this discussion. 25 years or so
>of group effort to develop a generic industry standard sitting on the
>sidelines in this dialog.
>
>The following is taken from the forum sponsors website
>
>"...Establishes the capability for a single ANSI STD datafile format to
>transfer data to all disciplines in the PCB supply chain.
>
>...Provides for complete transfer of test data and electrical test
>parameters.
>
>...Can accommodate several BOM descriptions in a single data file.
>
>...Brings your design into close contact with DFM issues."
>
>Has anyone taken it for a lap? Is (are) there a reason(s) for its absence
>in this dialog?
>
>Best to all,
>Joe
--=====================_266668889==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
From a designers point of view:<br><br>
Even before the advent of GENCAM was IPC's effort with IPC-350. In fact,
that is where CAM350 got it's name. The original intent of that
application was to output the "new" industry standard data
format, IPC-350. This later gave way to GENCAM which has now stepped
aside (or- been pushed aside) for ODB++. <br><br>
The impetus to develop an industry standard data exchange format has been
around for over a decade. <br><br>
So, what is standing the way? EDA software companies! <br><br>
Imagine the convenience designers would experience if there was a data
format that could be easily exchanged between design platforms! Good God,
could this have any effect on market share? I think not.. but I believe
that is the fear held by the EDA vendors. It will surely be a cold day
when a standard data format will be supported by vendors of PCB design
applications. I am convinced this function will continue to be relegated
to applications that are in the CAM arena and will remain a
post-processing function for the designer. <br><br>
The objectives Joe listed below were shared by the IPC-350 effort as
well.<br><br>
<font face="arial">Denis Lefebvre, C.I.D.<br>
Senior PCB Designer<br>
Finisar Corporation<br>
(408)542-3832<br>
<a href="http://www.finisar.com/" eudora="autourl">http://www.finisar.com<br><br>
</a></font>At 08:49 AM 1/31/2002 -0500, you wrote:<br>
<blockquote type=cite class=cite cite><font face="Arial, Helvetica" size=2>Good
day to all, <br><br>
It seems that IPC GenCAM is missing from this discussion. 25 years or so
of group effort to develop a generic industry standard sitting on the
sidelines in this dialog. <br><br>
The following is taken from the forum sponsors website <br><br>
</font>"...Establishes the capability for a single ANSI STD datafile
format to transfer data to all disciplines in the PCB supply chain.
<br><br>
...Provides for complete transfer of test data and electrical test
parameters. <br><br>
...Can accommodate several BOM descriptions in a single data file.
<br><br>
...Brings your design into close contact with DFM issues."
<br><br>
<font face="Arial, Helvetica" size=2>Has anyone taken it for a lap? Is
(are) there a reason(s) for its absence in this dialog? </font>
<br><br>
Best to all, <br>
Joe<font face="arial"> </font></blockquote></html>
--=====================_266668889==_.ALT--
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Date: Thu, 31 Jan 2002 08:19:56 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: ODB++
X-cc: Jim <[log in to unmask]>
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Yikes, sorry, wrong button pushed and there went an unfinished
-mail ------------
Following is a more finished one:
I have been trying to follow the development of new data standards in this
industry. I have listened to the various interested parties make very
interesting claims about the goodness of their products. But at the moment I
hope that the GenCAM type effort is going to win. Even though I have no
reason to wish that Gerber would go away.
The nice things about Gerber are that it is a very simple standard and I can
read and understand the file. Therefore I can check the content of a file
and fix problems with the data. And I have not yet come across images that
cannot be represented by Gerber data.
The unpleasant things that have happened with Gerber is, that there are
always software designers who can and will "improve" things. And now their
"Gerber-like" output cannot be read by input devices that fully comply with
the Gerber Standard.
Then there are software engineers who design input devices and decide that
certain features and rules in the standard are superfluous and exclude those
from their package. The result is of course that their product at times does
not show results that were in the original fully complying data.
With more complex data standards it is hard to believe that these problems
are going away or are going to be easier to deal with. And the reason that I
lean towards GenCAM is that the effort to develop that standard includes
compliance checkers to help users determine that their output or input files
do indeed comply with the standard. The data format is readable so it is
easier to check what is inside the file and there is intent to assure that
all future versions are backwards compatible. So when I store data I don't
have to store interpreters to go with that specific data.
Next question: when is it going to be ready and is it going to be accepted
widely?
And of course a disadvantage of these new all-encompassing data files is
that I only need the layers that have the information needed to make a
stencil and I don't need (and I really don't want) 25Mbyte of data,
including the information on what parts to buy where and how to build and
test the board. We already have received files that include the little note:
Please destroy files after delivery of stencil !!!
Have fun,
Ahne.
A-Laser, Inc.
* I assume you are comfortable with your system outputting gerber, ---
I would also opt for ODB++ as it can carry a lot more than just bare board
information. ---
The problem I have is in archiving any data object in more than one
ormat ---
how do you insure that both sets of output data are identical in every
way? ---
If the CAD system doesn't produce ODB++ directly, and most don't ----
we use a third party tool (I use CAM350) to translate into ODB++, either
from the native CAD file or from Gerbers. ---
Producing an output file, either Gerber or ODB++, from a native CAD database
is a translation process. ---
I have yet to own a piece of bug-free software. ---
I know from experience that there are flaws in the Gerber data generators in
most CAD programs. ---
Similarly, different Gerber viewers can display the same data file
differently. ---
if an independent industry group produced a validation suite that a program
would have to pass to call itself ODB++ compliant. ---
Gerber, which is truly a rotten old standard. ---
Until ODB++ becomes as universally accepted by fab shops as Gerber ---
Regards,
From Seth Goodman's e-mail.
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Date: Thu, 31 Jan 2002 10:54:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jeff Ferry <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: BGA Rework Using Paste vs. No Paste
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 31 Jan 2002 12:08:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: CERAMIC CSP'S and a MoonMan adventure out of the cave again
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Hey Everybody!
I've got Earls pictures up on my web page. Go to:
http://www.stevezeva.homestead.com/
Yes, Earl I'm not only listening, but taking notes as well...
-Steve Gregory-
> Folks,
>
> I have been reviewing all the issues/problems that were faced by my host
> company and its supplier ? before I arrived. I would like to share some for
> comment as well as my observations, if you would be so kind.
>
> We have one board design using seven .8 mm ceramic CSP?s made by TI. The
> first issue facing my company was cracking or separation of balls from the
> device. I have reports from Rockwell, who did the F/A and from TI both
> pointing to the failure mechanism as possible excessive IMC formation as in
> the following without the photos, of course:
>
> Attached are four photos:
>
> CSP-1 shows multiple insertions into sockets.
> CSP-2 shows x-section of stock unit
> CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
> appears thick.
> CSP-4 shows x-section of device which broke off the PCB - clean break at the
> intermetallic layer.
>
> Because of the multiple insertions into sockets, as evidenced by
> indentations on the balls, it is considered that multiple thermal excursions
> contributed to IMC growth. As the clean break occurred at the IMC interface,
> again, this is thought to be the failure mechanism. This may be so, but
> other things must be considered as well.
>
> This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
> no repeat of this occurrence. No reason is available to me, at least,
> concerning the part?s improvement. No matter, there now exist other issues.
>
> I believe, as in a few comment trades, with others (Dave Fish for one), that
> our assembler?s inexperience profiling and soldering these devices has been
> responsible for poor quality/reliability solder joints. In their defense,
> there aren?t/weren?t many suppliers with this experience. Simply, cold
> solder joints probably contributed to unacceptability and complete failure
> as received ? evidenced by the infamous "C" clamp. The ceramic portion of
> the device is extremely massive compared to ball size and the ability to get
> required heat to the solder medium and balls to effect acceptable solder
> joints. This means, I believe based on past experience, the reflow profile
> must be "maxed" out in terms of solder paste performance and joint
> formation. I don?t think this was done.
>
> To add to the situation, the CTE mis-match of ceramic and PCB material
> certainly has been known to ruin even good solder joints. This may account
> to the failure at the IMC interface as well as at the board level.
> Therefore, a "too thick" IMC layer probably is/was not the failure
> mechanism, or was it?
>
> All solder pads have been re-evaluated and now definitely meet alignment and
> size requirements. Stencil apertures are as specified. Solder paste now is
> Kester?s 562R, solder volume is acceptable, surface solderability is as
> required. What remains is developing a solder reflow profile that will
> effect acceptable solder joints for the CSP?s as well as all other devices
> on the board.
>
> I realize this should not be a big issue, but having had to go way back to
> visit initial failures at the device ball interface, I have some concerns
> about whoever builds our next lot of boards. Steve, are you listening.
>
> I would appreciate any comments concerning this small part of the picture. I
> would appreciate anyone sharing experiences with what should be another BGA
> success story but for what I have presented here.
>
> Thank you all much,
>
> Earl
>
--part1_8.2088dbdb.298ad420_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey Everybody!
<BR>
<BR>I've got Earls pictures up on my web page. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com/
<BR>
<BR>Yes, Earl I'm not only listening, but taking notes as well...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Folks,
<BR>
<BR>I have been reviewing all the issues/problems that were faced by my host
<BR>company and its supplier ? before I arrived. I would like to share some for
<BR>comment as well as my observations, if you would be so kind.
<BR>
<BR>We have one board design using seven .8 mm ceramic CSP?s made by TI. The
<BR>first issue facing my company was cracking or separation of balls from the
<BR>device. I have reports from Rockwell, who did the F/A and from TI both
<BR>pointing to the failure mechanism as possible excessive IMC formation as in
<BR>the following without the photos, of course:
<BR>
<BR>Attached are four photos:
<BR>
<BR>CSP-1 shows multiple insertions into sockets.
<BR>CSP-2 shows x-section of stock unit
<BR>CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
<BR>appears thick.
<BR>CSP-4 shows x-section of device which broke off the PCB - clean break at the
<BR>intermetallic layer.
<BR>
<BR>Because of the multiple insertions into sockets, as evidenced by
<BR>indentations on the balls, it is considered that multiple thermal excursions
<BR>contributed to IMC growth. As the clean break occurred at the IMC interface,
<BR>again, this is thought to be the failure mechanism. This may be so, but
<BR>other things must be considered as well.
<BR>
<BR>This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
<BR>no repeat of this occurrence. No reason is available to me, at least,
<BR>concerning the part?s improvement. No matter, there now exist other issues.
<BR>
<BR>I believe, as in a few comment trades, with others (Dave Fish for one), that
<BR>our assembler?s inexperience profiling and soldering these devices has been
<BR>responsible for poor quality/reliability solder joints. In their defense,
<BR>there aren?t/weren?t many suppliers with this experience. Simply, cold
<BR>solder joints probably contributed to unacceptability and complete failure
<BR>as received ? evidenced by the infamous "C" clamp. The ceramic portion of
<BR>the device is extremely massive compared to ball size and the ability to get
<BR>required heat to the solder medium and balls to effect acceptable solder
<BR>joints. This means, I believe based on past experience, the reflow profile
<BR>must be "maxed" out in terms of solder paste performance and joint
<BR>formation. I don?t think this was done.
<BR>
<BR>To add to the situation, the CTE mis-match of ceramic and PCB material
<BR>certainly has been known to ruin even good solder joints. This may account
<BR>to the failure at the IMC interface as well as at the board level.
<BR>Therefore, a "too thick" IMC layer probably is/was not the failure
<BR>mechanism, or was it?
<BR>
<BR>All solder pads have been re-evaluated and now definitely meet alignment and
<BR>size requirements. Stencil apertures are as specified. Solder paste now is
<BR>Kester?s 562R, solder volume is acceptable, surface solderability is as
<BR>required. What remains is developing a solder reflow profile that will
<BR>effect acceptable solder joints for the CSP?s as well as all other devices
<BR>on the board.
<BR>
<BR>I realize this should not be a big issue, but having had to go way back to
<BR>visit initial failures at the device ball interface, I have some concerns
<BR>about whoever builds our next lot of boards. Steve, are you listening.
<BR>
<BR>I would appreciate any comments concerning this small part of the picture. I
<BR>would appreciate anyone sharing experiences with what should be another BGA
<BR>success story but for what I have presented here.
<BR>
<BR>Thank you all much,
<BR>
<BR>Earl
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_8.2088dbdb.298ad420_boundary--
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Date: Thu, 31 Jan 2002 11:12:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: CERAMIC CSP'S and a MoonMan adventure out of the cave again
X-To: [log in to unmask]
Thanks for the posting of the dirty pictures. Nasty is more like it. Even
got old Werner's interest as he asked me to send them directly to him. Hell,
I sent the whole report. Can't wait to get the facts.
Also, one of our key players is using about 60 of these little muthas on a
board. Kerry McMullin is sending a profile later. Can't wait to see that as
well.
This IS turning out to be an adventure. I do love this stuff.
Earl
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Date: Thu, 31 Jan 2002 11:15:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
Jeff,
It's the only way to go. I've been designing, placing, reflowing and
reworking BGA's for nearly 8 years now. It took me five minutes to make the
discovery and, as I've said far too often, I'd use flux only on initial
production if feasible.
Regards and respect,
Earl Moon
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Date: Thu, 31 Jan 2002 09:22:10 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process, BGA Reballing
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0019_01C1AA38.C2A26E40"
This is a multi-part message in MIME format.
------=_NextPart_000_0019_01C1AA38.C2A26E40
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi all,
I've found this thread to be very interesting and informative, but would =
like to present a "different twist" to the subject:
I have a client using our Reballing system to recondition all sorts of =
BGA and uBGA for re-use after de-soldering. They are currently using a =
water soluble paste and cleaning with DI, however the residual absorbed =
moisture presents a concern, so the devices are baked after cleaning. =
This increases turnaround time, so they are considering moving to a =
no-clean process.=20
My opinion is that there will be residues and they could possibly be =
incompatible with subsequent platforms utilized by the end user, as well =
as creating aesthetic impact. Cleaning alternatives for no-clean fluxes =
rival the more aggressive (therefore more forgiving) water solubles, so =
the benefit is lost if cleaned.
Any and all opinions, theories, suggestions and experiences are =
welcomed!
=20
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
------=_NextPart_000_0019_01C1AA38.C2A26E40
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I've found this thread to be very =
interesting and=20
informative, but would like to present a "different twist" to the=20
subject:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I have a client using our Reballing =
system to=20
recondition all sorts of BGA and uBGA for re-use after de-soldering. =
They are=20
currently using a water soluble paste and cleaning with DI, however the =
residual=20
absorbed moisture presents a concern, so the devices are baked after =
cleaning.=20
This increases turnaround time, so they are considering moving to a =
no-clean=20
process. </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>My opinion is that there will be =
residues and=20
they could possibly be incompatible with subsequent platforms utilized =
by the=20
end user, as well as creating aesthetic impact. Cleaning =
alternatives for=20
no-clean fluxes rival the more aggressive (therefore more forgiving) =
water=20
solubles, so the benefit is lost if cleaned.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Any and all opinions, theories, =
suggestions and=20
experiences are welcomed!</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
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Date: Thu, 31 Jan 2002 12:22:19 -0500
Reply-To: Mark Charlton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Charlton <[log in to unmask]>
Organization: MSI of Central Florida, Inc.
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Jeff,
My "rule of thumb" is plastic BGA's with eutectic balls - I use stick flux
only. For ceramic BGA's with non-eutectic or "hard" balls, I must use a
microscreen and apply solder paste.
Mark
----- Original Message -----
From: "Jeff Ferry" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, January 31, 2002 11:54 AM
Subject: BGA Rework Using Paste vs. No Paste
> Fellow TechNetters,
>
> We nearly always apply solder paste to the circuit board when we replace
> BGA components during rework. Yet, after speaking with a handfull of BGA
> equipment companies at APEX, seems like they all recommend using flux only
> vs. paste, unless the circuit board is used in a high rel application.
>
> What do ya'all do/recommend for BAG rework? Can you point me to any
> studies/reports on the subject?
>
> Thanks,
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
-------
>
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Date: Thu, 31 Jan 2002 12:27:43 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ODB++
X-To: [log in to unmask]
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It has been an interesting dialogue thus far with many interesting issues
raised.
Going back over the years, we have witnessed many data transfer schemes that
have served many purposes. Gerber has served very well for what it was
original intended to do. As our designs become more complex and demand more
complex fabrication, assembly and testing processes and techniques, we find
ourselves looking for the next generation data transfer vehicle.
In the 1970s IPC created the IPC-D-350 data format to address a more
intelligent transfer of fabrication data. It included hole, outline and other
important information. IPC even established a certification system to ensure
that the data coming from many sources complied to the format rules and would
not generate errors upon read-in. No, the industry did not embrace it as
expected. Why? For several reasons, reasons that are very applicable to this
current discussion.
First, a number of fabricators offered severe discounts to customers sending
350 data. The discounts were applied against the tooling charges, not the
actual fabrication costs of the board. Hmmmm, tooling charges are in the
range of $400 - $500. Even if the fabricators gave the tooling away for free,
it would take an awful lot of orders to justify the cost of the CAD output
software. You see, it has never been in the best interest for a CAD software
supplier to permit intelligent data output. lest the user wish to switch his
CAD software to another supplier. Therefore, some of the CAD suppliers placed
exorbitant fees on the 350 output software. Not doing the user community
justice at all. Therefore, when the designer requested the software update
from his management, he was told that the amount saved was not cost
justified.
Second, fabricators realized several savings when using intelligent data
files. They saved by eliminating a number of data files that invariably
conflicted with each other. It took manpower and time to resolve these
differences before a job could proceed into fabrication. So, fabricators
provided discounts on tooling and requested these intelligent files from
their customers. In some cases insisted upon it only to be told by their
customers "if you can't do the job with what we send you, we'll find someone
who can." Faced with this choice and since the fabricator was comfortable
with the evils of Gerber, he accepted the Gerber files.
Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing the
same issues. Yes, IPC has again provided a compliance test module to verify
the output/input of GenCAM data. Yes, some of the output software is being
offered for free. Yes, companies are offering tooling discounts for
intelligent data files. And yes many companies are using either of the two
formats. Will either format take 100% market share? No! The fact remains that
there will be followers of both formats, followers of new formats, and then a
large group that will do nothing but sit around and wait for who knows what
to happen.
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
860-350-9300
fax 413-771-5386
--part1_81.16de019b.298ad88f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">It has been an interesting dialogue thus far with many interesting issues raised.<BR>
<BR>
Going back over the years, we have witnessed many data transfer schemes that have served many purposes. Gerber has served very well for what it was original intended to do. As our designs become more complex and demand more complex fabrication, assembly and testing processes and techniques, we find ourselves looking for the next generation data transfer vehicle.<BR>
<BR>
In the 1970s IPC created the IPC-D-350 data format to address a more intelligent transfer of fabrication data. It included hole, outline and other important information. IPC even established a certification system to ensure that the data coming from many sources complied to the format rules and would not generate errors upon read-in. No, the industry did not embrace it as expected. Why? For several reasons, reasons that are very applicable to this current discussion. <BR>
<BR>
First, a number of fabricators offered severe discounts to customers sending 350 data. The discounts were applied against the tooling charges, not the actual fabrication costs of the board. Hmmmm, tooling charges are in the range of $400 - $500. Even if the fabricators gave the tooling away for free, it would take an awful lot of orders to justify the cost of the CAD output software. You see, it has never been in the best interest for a CAD software supplier to permit intelligent data output. lest the user wish to switch his CAD software to another supplier. Therefore, some of the CAD suppliers placed exorbitant fees on the 350 output software. Not doing the user community justice at all. Therefore, when the designer requested the software update from his management, he was told that the amount saved was not cost justified. <BR>
<BR>
Second, fabricators realized several savings when using intelligent data files. They saved by eliminating a number of data files that invariably conflicted with each other. It took manpower and time to resolve these differences before a job could proceed into fabrication. So, fabricators provided discounts on tooling and requested these intelligent files from their customers. In some cases insisted upon it only to be told by their customers "if you can't do the job with what we send you, we'll find someone who can." Faced with this choice and since the fabricator was comfortable with the evils of Gerber, he accepted the Gerber files.<BR>
<BR>
Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing the same issues. Yes, IPC has again provided a compliance test module to verify the output/input of GenCAM data. Yes, some of the output software is being offered for free. Yes, companies are offering tooling discounts for intelligent data files. And yes many companies are using either of the two formats. Will either format take 100% market share? No! The fact remains that there will be followers of both formats, followers of new formats, and then a large group that will do nothing but sit around and wait for who knows what to happen.<BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
860-350-9300<BR>
fax 413-771-5386</FONT></HTML>
--part1_81.16de019b.298ad88f_boundary--
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Date: Thu, 31 Jan 2002 10:36:13 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dave Pahlas <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dave Pahlas <[log in to unmask]>
Subject: PCB Hole Diameters for Gold Press-fit
MIME-Version: 1.0
Content-Type: text/plain
Hello All,
I am working with a customer to determine the optimal finished hole diameter
for press-fit connectors into a Gold finish PCB. The supplier's data sheet
for the connector specifies .024"+/-.002" HASL plated holes. We have learned
from experience that the connector insertion success rate is greatly
improved when using a slightly larger hole on a gold finish PCB since it is
less compliant with the connector pins than the soft HASL.
So far, the supplier has not given a recommendation on a diameter for gold,
so I am looking for other industry standards to validate our findings.
Any ideas would be greatly appreciated.
Thanks, Dave
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Date: Thu, 31 Jan 2002 11:37:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
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Jeff,
It is my opinion that pasting the board enhances wetting and a superior =
joint.
Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508 Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]
>>> [log in to unmask] 01/31/02 10:54AM >>>
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 31 Jan 2002 11:35:53 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: [log in to unmask]
Mark,
I shouldn't have, but I just assumed eutectic. Shame on the moonman.
I tried the stick stuff, but couldn't get the compliance microstenciled
paste flux gives. It just reaches up and grabs the balls even when
coplanarity isn't perfect.
MoonMan
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Date: Thu, 31 Jan 2002 11:41:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: ODB++
X-To: [log in to unmask]
Gary,
Outstanding!
I'm a big fan of ODB because I'm a big fan of Valor. Please understand, I'm
not a sales representative. I just can't do in any other CAM package that
which I can do in Valor.
That's all I've got as it just gets the job done. Don't know what tomorrow
will bring but I ain't sittin' on it or waitin' for it.
Enjoy,
MoonMan
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Date: Thu, 31 Jan 2002 12:44:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Jeff,
For our eutectic PBGA's, we only flux (no clean). Have only done about 50
or so over the past year with very good (97% yield) results.
Have not seen any studies or papers. Just worked closely with our CM to
create the profile for each type of BGA. We use Air-Vac.
Kerry
-----Original Message-----
From: Jeff Ferry [mailto:[log in to unmask]]
Sent: Thursday, January 31, 2002 11:54 AM
To: [log in to unmask]
Subject: [TN] BGA Rework Using Paste vs. No Paste
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 31 Jan 2002 17:53:00 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Conformal Coating
X-To: "Marsico, James" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Jim
Having kicked this around here, the general consensus is that you do NOT
ship the product.
Without knowing the exact coating material, nor your end product, we could
not say how the "overcooked / oxidised" coating will behave. We would figure
that its moisture and chemical resistance might be improved but, its
potentially less flexible nature might over-stress components.
As to removing it, I think that a chemical stripper would probably be safer
but it will have to be done very carefully by hand, a little at a time. I
could not comment upon its effect on components and understand why your
customer would be unhappy with this. This is a space product, and the cost
of launch, much less manufacture, would probably demand that you re-make the
product - it might give all the data acquisition to the Aliens on planet
Tharg.
Sorry, but I don't think we can give you an acceptable alternative. Best of
luck.
Regards Graham Naisbitt
[log in to unmask] <mailto:[log in to unmask]>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
> Sent: 30 January 2002 18:39
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
>
> The coating supplier's technical staff stated that the discoloration was
> probably due to oxidation of the double bond of the molecules. He also
> stated, as you, that the material may have become somewhat harder due to
> further cross linking.
>
> I don't think that moisture permeability is an issue, but what is
> a concern
> is if the modulus increased which might affect chip component reliability,
> if coating was actually under some ceramic or glass components. In your
> opinion, would additional cross linking, oxidation, reversion or being at
> 150C for 2 hours cause the modulus to increase?
>
> As far as stripping the coating, we crossed this path once before and our
> customer will not allow us to use any chemical stripping solution
> to remove
> polyurethane coating. They don't know how it will affect components,
> boards, etc.
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>
> -----Original Message-----
> From: Graham Naisbitt [SMTP:[log in to unmask]]
> Sent: Wednesday, January 30, 2002 11:37 AM
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
> Jim
>
> I know this is a late posting, because I have only just come back
> on-line
> however, what you have encountered is reversion.
>
> The UR materials tend to discolour when exposed to high
> temperatures, but
> this does not generally affect their subsequent performance - if
> anything it
> might improve it because you have ensured a full x-link of the
> polymer -
> fully reacted.
>
> The discoloration may however, be an unacceptable visual condition
> to your
> customer, depending upon their inspection criteria.
>
> Whatever, it will be possible to remove and re-coat if you desire.
>
> You mention that this is a space application, therefore this
> material will
> probably have excellent outgassing characteristics and I can only
> think of 1
> or 2 UR space (NASA / ESA) approved coatings. I am surprised that
> you have
> this reversion, what did their technical staff advise? I
> would like
> to know
> for my own record.
>
> Regards Graham Naisbitt
>
> [log in to unmask]
> <mailto:[log in to unmask]>
>
> Concoat Limited
> Alasan House, Albany Park
> Camberley GU16 7PH - UK
>
> www.concoat.co.uk <http://www.concoat.co.uk>
>
> Phone: +44 1276 691100
> Fax: +44 1276 691227
> Mobile: +44 79 6858 2121
>
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
> > Sent: 29 January 2002 00:49
> > To: [log in to unmask]
> > Subject: Re: [TN] Conformal Coating
> >
> >
> > Jim,
> >
> > You have chemically altered the polymer. It will no longer
> > perform it's designed function.
> >
> > David A. Douthit
> > Manager
> > LoCan LLC
> >
> > "Marsico, James" wrote:
> >
> > > Help! Emergency!
> > >
> > > We have a completed assembly (top assembly with many boards,
> > hybrids, etc.)
> > > ready for shipment to our customer (space product). The last
> > operation was
> > > to ink mark a S/N. The ink is cured at 150 F for 2
> hours. The
> > assembly was
> > > put in an oven at 150 C for two hours. After hours of
> > reviewing all of the
> > > materials and bill of material, component by component
> (component data,
> > > supplier phone calls, etc.), the only item that is not rated
> > for 150 C is
> > > the polyurethane conformal coating, which turned yellow/brown
> > in color. Can
> > > anyone explain what actually happened to the coating and if it
> > can be used
> > > as is?
> > >
> > > Thanks,
> > >
> > > Jim Marsico
> > > Senior Engineer
> > > Production Engineering
> > > EDO Electronics Systems Group
> > > [log in to unmask] <mailto:[log in to unmask]>
> > > 631-595-5879
> > >
> > >
> >
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Date: Thu, 31 Jan 2002 10:04:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: ODB++
X-To: Mark Steele <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
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Just a thought, wouldn't the gerber be absolute too? Just compare data
rather than the image. I seem to recall an old OS that had a command called
"compare".
Dan
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Date: Thu, 31 Jan 2002 11:58:06 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: MoonCaveMan cleaning out the cave. Lot's of free stuff.
Yes friends,
The MoonCaveMan has reached a limit. He is making an offer as none other
before. As a kind and giving, though a bit rough around the edges (much like
some of my current solder joints) kinda guy, he's cleaned out his cave and
now is making available a bunch of manufacturing operations procedures.
Some of the stuff is not so good, but most of it ain't too bad. All
procedures, including moisture, stencil printing, rework, wave soldering,
placement, reflow, and a bunch more are photo documents dating way back to
the present.
If Seth still allows, I'm going to place them all on his FTP site within my
folder.
My users may log into ftp.GoodmanAssociates.com anonymously. They will see a
directory called "Earl's files" that contain all your stuff. They can then
download to their heart's content.
Happy hunting,
MoonCaveMan
Oh yes, I'll complete the transfer tomorrow so you might want to wait a day
or so.
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Date: Thu, 31 Jan 2002 13:26:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Water Drop Test
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Technetters,
Do any of you have the instructions for the water drop test handy? If so,
could you post it, please. Thanks.
Bev Christian
Research in Motion
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Date: Thu, 31 Jan 2002 10:58:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Jeff,
We have been working and reworking BGA and Micro BGA for quite sometime.
This is a requirement in a prorotye environment. We tried using micro
stencil when we first attempt to replace the BGAs and found out that using
micro stencil was not a good method. We then tried using no-clean tacky
past fux and applied to both the BGA and the PWB substrates. This process
has been adopted in our process and has been working well for us. Here are
some great benefit of using flux paste only.
- No micro stencil cost.
- No cleaning is needed (No-clean flux).
- No aligning equipment is needed, since we can place the BGA into its
footprints without worry about smearing the solder paste, and if the
hand alignment if off ( no more than 50%), the liquid tension of the
reflowed solder balls will pull it back.
- Save time and money. ( stencil cost, cleaning, and aligning).
If the solder balls on the BGA are made of non-eutectic, solder paste is
required.
Tuan Bui
Conexant Systems Inc.
Prototype Process Dev. Eng.
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc:
Sent by: TechNet Subject: [TN] BGA Rework Using Paste vs.
<[log in to unmask]> No Paste
01/31/02 08:54 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Jeff
Ferry
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 31 Jan 2002 11:00:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: ENIG Thickness Standard?
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Dave,
Thanks for the feedback. I did get some specifics on IPC-4552 proposed
recommendations from the committee co-chair that we're going to put in
our requirements.
Regards,
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of
[log in to unmask]
Sent: Thursday, January 31, 2002 6:37 AM
To: [log in to unmask]
Subject: Re: [TN] ENIG Thickness Standard?
Good Morning TechNet! Rick, I have a very different perspective on ENIG
than Peter so here is some food for thought. There is a specification
for ENIG - IPC-4552 - which is in final ballot and should be release in
the March/May timeframe. I recommend getting a copy. It's my opinion
that the specification is quite useful considering there is no other
specification available for industry use. The ASTM B488 specification is
not a workable solution for electronics applications. There was a great
deal of committee discussion on the electroless nickel plating
thickness. The nickel thickness is very much viewed as application
specific, for example, RF designers desire minimal thickness (30-50
uinches) as opposed to connecting applications which use 200 uinches.
Rockwell Collins is successfully using 2-5 uninches for the immersion
gold thickness and 50-150 uinches for the electroless nickel thickness
in avionics applications and we intend on using the IPC-4552
specification in our documentation. Additionally, 50 uinches of
electroless nickel is very adequate as a diffusion barrier as both the
nickel/copper and nickel/gold phase diagrams demonstrate a wide range of
immiscibility The only instances I have seen a 50 uinch electroless
nickel thickness not be adequate was for pwbs which were subjected to
repetitive thermal excursions (e.g. lots of rework, or 4 reflow passes).
Using an immersion gold thickness of 6 uinches will not guarantee you
solderability - the 4552 committee demonstrated that (by conducting
testing) that 2 uinches of immersion gold can be steam conditioned and
still provide expected solderability coverage. Teaming with your ENIG
vendor, understanding their plating process control practices and
requiring some level of solderability testing is the best way of
insuring solderability. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
[log in to unmask]@ipc.org> on 01/30/2002 09:03:53 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond
to [log in to unmask]
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] ENIG Thickness Standard?
Rick,
I went through this pain a while ago, and got a lot of tremendous help
from Ingemar Hernefjord in particular. I believe there is no released
standard for ENIG, though there is an empirical spec IPC-4552. It does
not contain a lot of useful detail, though. I specify 5 microinches
(0.12 microns) of Gold over minimum 235 microinches (6 microns) Nickel
for my boards, after reading a number of studies and failure reports. In
fact I was recommended to use 250 microinches of Nickel, but this would
have made our boards too thick. The thicker gold layer minimises
porosity and therefore oxidation to the underlying Nickel layer.
Older thinking was for around 100 to 120 microinches Nickel, but studies
by Eriksson and others concluded that with the growth of gold flashing
through the Nickel from one side and Cu/Ni intermetallics on the other
side of the plating, that a thicker Nickel layer would offer the boards
a longer solderability shelf life and greater solder joint reliability.
Hope this helps a bit. Certainly, I haven't experienced any problems
with soldering or mounting of components on boards to this spec.
Peter
Rick Thompson
<rthompson@VENTURAELECTR To:
[log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN]
ENIG
Thickness Standard?
01/31/02 08:36 AM
Please respond to
"TechNet E-Mail Forum.";
Please respond to Rick
Thompson
Is there a standard for the plating thickness of the ENIG surface
finish? I've searched the archives and didn't find anything. Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches. What (if anything) is considered standard for this finish?
Thanks for your inputs.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Thu, 31 Jan 2002 14:10:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Collins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: ODB++
X-To: [log in to unmask]
Mime-Version: 1.0
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Ahne
The last one is a good point! We do contract manufacturing of military =
products. Currently when I need a stencil all I'm sending out is the =
paste layer gerber file, and the aperture report. I'd be nervous sending =
the full design data out, and I'm sure my customer would be unhappy. =
Either we would have to get vendors cleared for security purposes, or we =
would have to manipulate the data here - which I'd rather avoid doing. =
Being able to easily send just a layer of the data is very handy.
This is true for many parts of build - getting pwb's made, stencils, wave =
soldering fixtures, test fixtures... yikes!
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> Ahne Oosterhof <[log in to unmask]> 01/31/02 12:19PM >>>
Yikes, sorry, wrong button pushed and there went an unfinished
-mail ------------
Following is a more finished one:
I have been trying to follow the development of new data standards in this
industry. I have listened to the various interested parties make very
interesting claims about the goodness of their products. But at the moment =
I
hope that the GenCAM type effort is going to win. Even though I have no
reason to wish that Gerber would go away.
The nice things about Gerber are that it is a very simple standard and I =
can
read and understand the file. Therefore I can check the content of a file
and fix problems with the data. And I have not yet come across images that
cannot be represented by Gerber data.
The unpleasant things that have happened with Gerber is, that there are
always software designers who can and will "improve" things. And now their
"Gerber-like" output cannot be read by input devices that fully comply =
with
the Gerber Standard.
Then there are software engineers who design input devices and decide that
certain features and rules in the standard are superfluous and exclude =
those
from their package. The result is of course that their product at times =
does
not show results that were in the original fully complying data.
With more complex data standards it is hard to believe that these problems
are going away or are going to be easier to deal with. And the reason that =
I
lean towards GenCAM is that the effort to develop that standard includes
compliance checkers to help users determine that their output or input =
files
do indeed comply with the standard. The data format is readable so it is
easier to check what is inside the file and there is intent to assure that
all future versions are backwards compatible. So when I store data I don't
have to store interpreters to go with that specific data.
Next question: when is it going to be ready and is it going to be accepted
widely?
And of course a disadvantage of these new all-encompassing data files is
that I only need the layers that have the information needed to make a
stencil and I don't need (and I really don't want) 25Mbyte of data,
including the information on what parts to buy where and how to build and
test the board. We already have received files that include the little =
note:
Please destroy files after delivery of stencil !!!
Have fun,
Ahne.
A-Laser, Inc.
* I assume you are comfortable with your system outputting gerber, ---
I would also opt for ODB++ as it can carry a lot more than just bare board
information. ---
The problem I have is in archiving any data object in more than one
ormat ---
how do you insure that both sets of output data are identical in every
way? ---
If the CAD system doesn't produce ODB++ directly, and most don't ----
we use a third party tool (I use CAM350) to translate into ODB++, either
from the native CAD file or from Gerbers. ---
Producing an output file, either Gerber or ODB++, from a native CAD =
database
is a translation process. ---
I have yet to own a piece of bug-free software. ---
I know from experience that there are flaws in the Gerber data generators =
in
most CAD programs. ---
Similarly, different Gerber viewers can display the same data file
differently. ---
if an independent industry group produced a validation suite that a =
program
would have to pass to call itself ODB++ compliant. ---
Gerber, which is truly a rotten old standard. ---
Until ODB++ becomes as universally accepted by fab shops as Gerber ---
Regards,
From Seth Goodman's e-mail.
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Date: Thu, 31 Jan 2002 14:19:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Collins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Flux residue with a no-clean process, BGA Reballing
Mime-Version: 1.0
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Ed
If they do change to no-clean, please give me a name so I know who not to =
use!!! :-)
Seriously, I'd have some serious issues with this. There is no way they =
can know what the end use of the part is - unless they ask each time and =
tailor the process to fit. So someone might end up with a big hidden =
problem. Potentially the end user has a no-clean residue in an application=
that won't tolerate it, or they process the board with a wash and they =
end up with a mystery residue (as has been discussed on TechNet previously)=
.
I have to ask though, can they process them fast enough that they aren't =
worried about moisture from the air? =20
Doesn't sound like a great plan to me...
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 01/31/02 01:22PM >>>
Hi all,
I've found this thread to be very interesting and informative, but would =
like to present a "different twist" to the subject:
I have a client using our Reballing system to recondition all sorts of BGA =
and uBGA for re-use after de-soldering. They are currently using a water =
soluble paste and cleaning with DI, however the residual absorbed moisture =
presents a concern, so the devices are baked after cleaning. This =
increases turnaround time, so they are considering moving to a no-clean =
process.=20
My opinion is that there will be residues and they could possibly be =
incompatible with subsequent platforms utilized by the end user, as well =
as creating aesthetic impact. Cleaning alternatives for no-clean fluxes =
rival the more aggressive (therefore more forgiving) water solubles, so =
the benefit is lost if cleaned.
Any and all opinions, theories, suggestions and experiences are welcomed!
=20
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
www.QTA.NET
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Date: Thu, 31 Jan 2002 11:21:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chad Haima <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chad Haima <[log in to unmask]>
Subject: Solder Pallet Material Test
MIME-Version: 1.0
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Hello all,
We're in the process of evaluating a new solder pallet material and was
wondering if someone out there had a wave machine we could basically "rent"
for a 4-6 month period. Any correspondence would be appreciated.
Chad Haima
National Sales Manager
S.P. Precision International, Ltd.
1-800-PALLETT
http://www.spprecision.com/
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Date: Thu, 31 Jan 2002 14:56:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Flux residue with a no-clean process, BGA Reballing
MIME-Version: 1.0
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Ed
In answer to your question, yes the benefit can be lost if the component is
cleaned. We have worked with clients that have experienced problems with BGA
components that were balled using a low solids no clean flux. These units
were assembled with water-soluble solderpaste and cleaned in an aqueous
inline system. The low solids no clean residue absorbed the activators and
moisture from the assembly process and created a corrosion cell on finished
assemblies. I would recommend that good cleaning and drying process for the
components that will be subjected to aqueous cleaning of water-soluble
solderpaste.
We found that Ion Chromatography analysis corresponded well to the electrical
performance testing (failures had high chloride levels).
Terry Munson
CSL Inc.
P 765-457-8095
F 765-457-9033
<A HREF="www.Residues.com">www.Residues.com</A>
<< have a client using our Reballing system to recondition all sorts of BGA
and uBGA for re-use after de-soldering. They are currently using a water
soluble paste and cleaning with DI, however the residual absorbed moisture
presents a concern, so the devices are baked after cleaning. This increases
turnaround time, so they are considering moving to a no-clean process.
My opinion is that there will be residues and they could possibly be
incompatible with subsequent platforms utilized by the end user, as well as
creating aesthetic impact. Cleaning alternatives for no-clean fluxes rival
the more aggressive (therefore more forgiving) water solubles, so the benefit
is lost if cleaned.
Ed
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Date: Thu, 31 Jan 2002 13:59:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jeff Ferry <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
Thanks for the replies (see below) to my original posting (see below).
Seems like several of you are having good luck using flux only vs. solder
paste during BGA rework. The thing I wonder about is the reliability of
reworked BGA solder joints. I thought that proper BGA solder joint volume
was based on the original BGA ball combined with the solder added during
the solder paste screen printing process. Thus, what effect does solder
volume and solder joint height have on the reliability of a BGA solder
joints for plastic BGA components?
Thanks again,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
Some Replies to prior posting included:
---------------------------
My "rule of thumb" is plastic BGA's with eutectic balls - I use stick flux
only. For ceramic BGA's with non-eutectic or "hard" balls, I must use a
microscreen and apply solder paste.
Mark
---------------------------
For our eutectic PBGA's, we only flux (no clean). Have only done about 50
or so over the past year with very good (97% yield) results.
Have not seen any studies or papers. Just worked closely with our CM to
create the profile for each type of BGA. We use Air-Vac.
Kerry
---------------------------
It's the only way to go. I've been designing, placing, reflowing and
reworking BGA's for nearly 8 years now. It took me five minutes to make the
discovery and, as I've said far too often, I'd use flux only on initial
production if feasible.
Regards and respect,
Earl Moon
---------------------------
We have been working and reworking BGA and Micro BGA for quite sometime.
This is a requirement in a prorotye environment. We tried using micro
stencil when we first attempt to replace the BGAs and found out that using
micro stencil was not a good method. We then tried using no-clean tacky
past fux and applied to both the BGA and the PWB substrates. This process
has been adopted in our process and has been working well for us. Here are
some great benefit of using flux paste only.
- No micro stencil cost.
- No cleaning is needed (No-clean flux).
- No aligning equipment is needed, since we can place the BGA into its
footprints without worry about smearing the solder paste, and if the
hand alignment if off ( no more than 50%), the liquid tension of the
reflowed solder balls will pull it back.
- Save time and money. ( stencil cost, cleaning, and aligning).
If the solder balls on the BGA are made of non-eutectic, solder paste is
required.
Tuan Bui
Conexant Systems Inc.
Prototype Process Dev. Eng.
---------------------------
It is my opinion that pasting the board enhances wetting and a superior
joint.
Jason Gregory
---------------------------
On Thu, 31 Jan 2002 10:54:24 -0600, Jeff Ferry <[log in to unmask]>
wrote:
>Fellow TechNetters,
>
>We nearly always apply solder paste to the circuit board when we replace
>BGA components during rework. Yet, after speaking with a handfull of BGA
>equipment companies at APEX, seems like they all recommend using flux only
>vs. paste, unless the circuit board is used in a high rel application.
>
>What do ya'all do/recommend for BAG rework? Can you point me to any
>studies/reports on the subject?
>
>Thanks,
>
>Jeff Ferry
>CEO
>Circuit Technology Center, Inc.
>
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Date: Thu, 31 Jan 2002 14:24:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
Jeff,
I know how busy you must be but we (me, Werner, Dave Fisherman, et al.) have
discussed this at some length over time but most recently as well. This is
one of those times where I didn't get my ass kicked too badly.
It all comes down to more isn't necessarily better.
Enjoy,
Earl
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Date: Fri, 1 Feb 2002 07:52:34 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Colin Weber <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Colin Weber <[log in to unmask]>
Subject: Graphics Cards
Mime-Version: 1.0
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Folks,
I know this isn't exactly PCB design but as CAD users I though someone
might be able to share their knowledge.
I am after any experiences with running a dual video card or two individual
cards for dual monitor arrangements under MS Windows 2000.
In particular, I'd like to know what the card(s) are and what cost,
success/failure, perhaps even what CAD packages you run. Also, any
success with OpenGL over the two monitors, 2D & 3D/performance.
Finally, another issue, anyone who runs a 17" to 20" flat panel LCD screen
and how they like/dislike it.
Regards,
Colin Weber
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Date: Thu, 31 Jan 2002 16:17:37 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ODB++
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Graham,
Formats are formats. The implementor of the output software usually provides
an interface that allows one to select the proper output information. I do
know that the GenCAM data format permits the selection of any specific data
set that is desired to be output.
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
860-350-9300
fax 413-771-5386
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Graham,<BR>
<BR>
Formats are formats. The implementor of the output software usually provides an interface that allows one to select the proper output information. I do know that the GenCAM data format permits the selection of any specific data set that is desired to be output.<BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
860-350-9300<BR>
fax 413-771-5386</FONT></HTML>
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Date: Thu, 31 Jan 2002 15:34:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Graphics Cards
X-To: [log in to unmask]
I have had great success with Matrox dual head products up to and including
the "latest" 450 series. There is other product available for "serious" CAD
users but at much higher cost and maybe not such good performance. You may
need a "higher" end card.
I use a ViewSonic 17" flat panel monitor with great results as well. I
really liked the Silicon Graphics stuff but for Silicon Graphics the company
and all its problems.
MoonMan
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Date: Thu, 31 Jan 2002 13:38:57 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Steele <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Steele <[log in to unmask]>
Subject: Re: ODB++
X-To: "Dan R. Johnson" <[log in to unmask]>
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Hi Dan,
I'm sure the pads and lines would be identical in both. I was
just thinking of the complex apertures that we sometimes get
in gerber 274X might not be a 100% one-to-one match with the
surfaces that we would end up with ODB++. I don't know that
they would be different but I do think there would be some
kind of difference, but hopefully a very small one.
I guess the question is what kind or tolerance are we going to
have to be considered 'different'. A difference of .000001
doesn't seem to qualify since we could never see it or even
measure it.
Mark
>From: Dan R. Johnson [mailto:[log in to unmask]]
>Sent: Thursday, January 31, 2002 10:05 AM
>To: TechNet E-Mail Forum.; Mark Steele
>Subject: Re: Re: [TN] ODB++
>
>
>Just a thought, wouldn't the gerber be absolute too? Just compare data
>rather than the image. I seem to recall an old OS that had a
>command called
>"compare".
>Dan
>
>
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Date: Thu, 31 Jan 2002 14:08:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Jeff,
No studies to cite, but in our admittedly informal internal testing
we've found consistently better yields using paste rather than flux for
BGA replacements. Some of this may be due to the condition of pcb and
pads on the boards after removal but we really haven't studied it in
detail.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: Thursday, January 31, 2002 8:54 AM
To: [log in to unmask]
Subject: [TN] BGA Rework Using Paste vs. No Paste
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux
only vs. paste, unless the circuit board is used in a high rel
application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 31 Jan 2002 15:19:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"PHC L.L." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "PHC L.L." <[log in to unmask]>
Subject: PCB Cross-sectional analysis service
MIME-Version: 1.0
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Anyone knows where I can get PCB cross-sectional
analysis service?? with reasonal price?
Thanks
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Thu, 31 Jan 2002 17:29:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PCB Cross-sectional analysis service
X-To: [log in to unmask]
Robisan Labs in Indiana - where else. Susan Mansilla. She and the lab owe me
now for some very cost effective sections.
Susan, where are they? Also, give this kind person some direction.
Earl
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Date: Thu, 31 Jan 2002 18:33:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Leland Woodall <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leland Woodall <[log in to unmask]>
Subject: Looking for Dr. Kantesh Doss
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Can anyone assist me in contacting Dr. Kantesh Doss? I understand he was
working on a PWB cleaning standard for IPC.
I believe he left Siemens Energy and Automation in Johnson City, TN, to go
to work with Nokia in TX, but I haven't spoken with him since.
Thanks for the info,
Leland Woodall
Keihin Carolina System Technology, Inc.
Tarboro, NC
252-212-1565, ext. 2865
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Date: Thu, 31 Jan 2002 16:36:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB Cross-sectional analysis service
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MIME-Version: 1.0
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Try these two places:
http://www.aciusa.org
http://www.solderingtech.com/
-----Original Message-----
From: PHC L.L. [mailto:[log in to unmask]]
Sent: Thursday, January 31, 2002 4:20 PM
To: [log in to unmask]
Subject: [TN] PCB Cross-sectional analysis service
Anyone knows where I can get PCB cross-sectional
analysis service?? with reasonal price?
Thanks
__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com
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Date: Thu, 31 Jan 2002 17:53:48 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: ODB++
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Gary,
Thanks so much for adding the GenCAM part of the story. Here are a couple
of questions concerning the points you made:
> Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing
the same issues.
> Yes, IPC has again provided a compliance test module to verify the
output/input of GenCAM data.
> Yes, some of the output software is being offered for free. Yes, companies
are offering tooling
> discounts for intelligent data files. And yes many companies are using
either of the two formats.
Could you pass on information as to who is offering free output software?
Also, I would like to know about fabrication shops that offer discounts for
use of intelligent tooling. When you say many companies are using either
format, are you talking about fabrication shops?
> Will either format take 100% market share? No! The fact remains that there
will be followers of
> both formats, followers of new formats, and then a large group that will
do nothing but sit around
> and wait for who knows what to happen.
This is the real tragedy. Right now, all fabrication shops accept Gerber,
as far as I know. The more different intelligent formats we standardize,
the more expensive and complicated the software for the fab shops will
become since they will be forced to deal with multiple formats. That will
eat up much or all of the possible savings the smart format was intended to
provide. Consider that a CAM engineer at the fab shop will have to be
conversant in each format as well as be familiar with the bugs, tricks and
workarounds for each format on his/her importing software. IMHO, one new
format would be a boon to the industry, while several new formats would be a
drain on resources. In that case, we may be better off turning RS-274X into
a real standard and create a validation suite for it. I can't believe I
just suggested that in public, but it's better than dealing with a Tower of
Babel due to multiple standards.
Another issue that I've heard bandied about is the possible merging of
ODB++ and GenCAM. Can't recall where I heard this, but it is an interesting
idea. Is this rumor correct and if so, what is the status of that effort?
We can look at the personal computer industry and see examples of how single
and multiple standard solutions fared. In the early 1980's, IBM released
the workings of the ISA bus. Though their information was not totally
complete and there was no validation mechanism that I remember, it wasn't
too hard to fill in the blanks and it became the de facto standard for about
10 years. Even after the initial period of heavy use, motherboard and
software vendors were compelled to provide backward compatibility for this
standard. Toward the end of the useful life of the ISA bus, it became a
bottleneck for increased performance and there was a huge amount of pressure
to come up with an alternative. A number of companies extended the ISA
architecture and released the EISA standard. About the same time, the
industry formed the VESA consortium and came up with an architecture that
gave better access to the processor local bus. Also around the same time,
IBM released the MicroChannel Architecture because, well, they were IBM.
Despite their technical superiority to ISA, none of these solutions lasted
more than a couple of years.
Enter the PCI special interest group who took the best of MicroChannel, VESA
and EISA and came up with an extensible bus architecture that served the
industry well up through the present. By the time it is superceded, the PCI
bus will have been useful for about 10 years. If you look at the period
when ISA, EISA, VESA and MicroChannel coexisted, progress in the industry
was stymied by the multiple standards. Both hardware and software companies
were hamstrung and tried to hedge their bets by producing the same product
on multiple bus platforms. In contrast, during both the stable ISA years
and the stable PCI years, technical advancements and total sales took off.
Everyone could work efficiently as there was a single hardware platform and
the market for every product was larger due to the single standard. The
software situation was not as good because a single company controlled the
de facto standard. This is not inherently bad, but due to their mindset and
the lack of broader industry control, they made frequent, undocumented
changes to their interfaces and tools that made software development a very
expensive endeavor. Those with limited resources were slowed to a crawl or
eliminated.
There's a lot we can learn from this.
1) It is to our mutual advantage to select a single standard, even if it is
not optimal. Having several similar competing solutions will slow down
industry progress. IMHO, we will do better with a single mediocre standard
than several more advanced but competing approaches.
2) It is dangerous to have a single company in a position to control the
standard. If their market share is great enough, they could, like
Microsoft, participate in industry standards efforts and sign off on the
results (i.e. HTML, Java), then go ahead and violate the standard so
competing products were not interoperable. If the standards were not
controlled by a couple of players who had large competitive axes to grind,
this probably wouldn't have happened. This is not meant as a criticism of
Valor and does not discourage ODB++ from becoming the new standard. It does
have implications as to how the new standard should be managed.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
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<BODY>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>Gary,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>Thanks =
so much for=20
adding the GenCAM part of the story. Here are a couple of =
questions=20
concerning the points you made:</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>> =
Today, with=20
intelligent data such as ODB++ and IPC's GenCAM we are facing the same=20
issues.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>> =
Yes, IPC has=20
again provided a compliance test module to verify the output/input of =
GenCAM=20
data.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>> =
Yes, some of=20
the output software is being offered for free. Yes, companies are =
offering=20
tooling</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>> =
discounts for=20
intelligent data files. And yes many companies are using either of the =
two=20
formats.</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>Could you pass on=20
information as to who is offering free output software? Also, I =
would=20
like to know about fabrication shops that offer discounts for use of=20
intelligent tooling. When you say many companies are using =
either=20
format, are you talking about fabrication=20
shops?</SPAN></FONT></DIV></BLOCKQUOTE>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>> Will=20
either format take 100% market share? No! The fact remains that there =
will be=20
followers of</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>> both=20
formats, followers of new formats, and then a large group that will do =
nothing=20
but sit around</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>> and wait for who knows what to=20
happen.</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>This is=20
the real tragedy. Right now, all fabrication shops accept =
Gerber, as far=20
as I know. The more different intelligent formats we =
standardize, the=20
more expensive and complicated the software for the fab shops will =
become=20
since they will be forced to deal with multiple formats. That =
will eat=20
up much or all of the possible savings the smart format was =
intended to=20
provide. Consider that a CAM engineer at the fab shop will have =
to be=20
conversant in each format as well as be familiar with the bugs, tricks =
and=20
workarounds for each format on his/her importing software. IMHO, =
one new=20
format would be a boon to the industry, while several new formats =
would be a=20
drain on resources. In that case, we may be better off turning =
RS-274X=20
into a real standard and create a validation suite for it. I =
can't=20
believe I just suggested that in public, but it's better than dealing =
with a=20
Tower of Babel due to multiple standards.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT><FONT face=3DArial =
size=3D2><SPAN=20
class=3D729443522-31012002>Another issue that I've heard bandied about =
is the=20
possible merging of ODB++ and GenCAM. Can't recall where I heard =
this,=20
but it is an interesting idea. Is this rumor correct and if so, =
what is=20
the status of that effort?</SPAN></FONT></DIV></BLOCKQUOTE>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>We can look=20
at the personal computer industry and see examples of how single and =
multiple=20
standard solutions fared. In the early 1980's, IBM released the =
workings=20
of the ISA bus. Though their information was not totally complete =
and=20
there was no validation mechanism that I remember, it wasn't too hard to =
fill in=20
the blanks and it became the de facto standard for about 10 years. =
Even=20
after the initial period of heavy use, motherboard and software vendors =
were=20
compelled to provide backward compatibility for this standard. =
Toward the=20
end of the useful life of the ISA bus, it became a bottleneck for =
increased=20
performance and there was a huge amount of pressure to come up with an=20
alternative. A number of companies extended the ISA architecture =
and=20
released the EISA standard. About the same time, the industry =
formed the=20
VESA consortium and came up with an architecture that gave better access =
to the=20
processor local bus. Also around the same time, IBM released the=20
MicroChannel Architecture because, well, they were IBM. Despite =
their=20
technical superiority to ISA, none of these solutions lasted more than a =
couple=20
of years.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>Enter the=20
PCI special interest group who took the best of MicroChannel, VESA and =
EISA=20
and came up with an extensible bus architecture that served the =
industry=20
well up through the present. By the time it is superceded, the PCI =
bus=20
will have been useful for about 10 years. If you look at the =
period when=20
ISA, EISA, VESA and MicroChannel coexisted, progress in the industry was =
stymied=20
by the multiple standards. Both hardware and software companies =
were=20
hamstrung and tried to hedge their bets by producing the same =
product on=20
multiple bus platforms. In contrast, during both the stable ISA =
years and=20
the stable PCI years, technical advancements and total sales took=20
off. Everyone could work efficiently as there was a single =
hardware=20
platform and the market for every product was larger due to the =
single=20
standard. The software situation was not as good because a single =
company=20
controlled the de facto standard. This is not inherently bad, but =
due to=20
their mindset and the lack of broader industry control, they made =
frequent,=20
undocumented changes to their interfaces and tools that made =
software=20
development a very expensive endeavor. Those with limited =
resources were=20
slowed to a crawl or eliminated.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>There's a=20
lot we can learn from this.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>1) <STRONG><EM>It is to our mutual =
advantage to=20
select a single standard, even if it is not optimal.</EM></STRONG> =
Having=20
several similar competing solutions will slow down industry =
progress. =20
IMHO, we will do better with a single mediocre standard than several =
more=20
advanced but competing approaches.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT> </DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>2) <STRONG><EM>It is dangerous to have a =
single=20
company in a position to control the standard.</EM></STRONG> If =
their=20
market share is great enough, they could, like Microsoft, participate in =
industry standards efforts and sign off on the results (i.e. HTML, =
Java),=20
then go ahead and violate the standard so competing products were not=20
interoperable. If the standards were not controlled by a couple of =
players=20
who had large competitive axes to grind, this probably wouldn't have=20
happened. This is not meant as a criticism of Valor and does not=20
discourage ODB++ from becoming the new standard. It does have =
implications as to how the new standard should be =
managed.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,<BR><BR>Seth Goodman<BR>Goodman =
Associates,=20
LLC<BR>tel 608.833.9933<BR>fax =
608.833.9966<BR></FONT></DIV></BODY></HTML>
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Date: Thu, 31 Jan 2002 19:13:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB Cross-sectional analysis service
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I recommend you try Soldering Technology International in Madison
(Huntsville), Alabama. Tel: 256-461-9191.
This is the home of the infamous Jim Raby.
Phil Zarrow
ITM Consulting
Durham, NH USA
www.ITMConsulting.org
T: (603) 868-1754
F: (603) 868-3623
EM:[log in to unmask]
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I recommend you try Soldering Technology International in Madison (Huntsville), Alabama. Tel: 256-461-9191.<BR>
This is the home of the infamous Jim Raby.<BR>
<BR>
Phil Zarrow<BR>
<BR>
<B>ITM Consulting <BR>
Durham, NH USA<BR>
www.ITMConsulting.org<BR>
T: (603) 868-1754<BR>
F: (603) 868-3623<BR>
EM:[log in to unmask]</B></FONT></HTML>
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Date: Thu, 31 Jan 2002 19:28:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Dupont CB100 VIA Plug and Delamination
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
We have been having a problem with Dupont silver CB100 VIA Plug. The
boards are 12 layer, .062", FR4, Nickel/Gold plated.
We have a BGA pattern with VIA in hole. The VIAs are filled with CB100 VIA
plug and then the board is plated.
The VIAs are .010 causing an aspect ratio of 6.2:1. We are seeing after
solder reflow, inner layer delamination in the area of the
VIA filled BGA patterns. Has anyone seen this before? Does anyone use a
similar construction and had success? There are a few
theories flying around but I wanted to ask the IPC community for any
insight. Thank you in advance.
Best Regards,
Mike Forrester
Sr. Manufacturing Engineer
[log in to unmask]
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Date: Sun, 27 Jan 2002 23:39:40 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ENVIRONMENT AND TERMITES
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In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time,
[log in to unmask] writes:
> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
>
Did I miss the news that the rain forests were gone? Funny, I read last year
that the founder of the Sierra Club did a fly over and proclaimed that they
were at least 90% in tact.....?? Guess I better start paying more attention.
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<HTML><FONT FACE=arial,helvetica><FONT COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time, [log in to unmask] writes:
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Termites were, before the rain forests were destroyed, by far the largest
<BR>methane gas producers on this planet. Maybe they are still.
<BR>
<BR></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">
<BR>Did I miss the news that the rain forests were gone? Funny, I read last year that the founder of the Sierra Club did a fly over and proclaimed that they were at least 90% in tact.....?? Guess I better start paying more attention.</FONT></HTML>
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Date: Fri, 1 Feb 2002 13:28:02 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA Rework Using Paste vs. No Paste
X-To: Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
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Can't give much of an insight from experience, but I know that PBGA's
solder beautifully simply using flux. Paste is used to mount them during
initial assembly, simply because all the other components require it and
it's difficult to just flux the BGA's alone.
For re-work, though, you can concentrate on the BGA alone. You don't need
mini stencils and little squeegees - you just remove the old component,
clean up the site with a solder sucker (don't use wicks), apply flux to the
component contacts, place and reflow. The experts (Atmel/Thomson) tell me
it works a treat and have it written up as a guideline.
It doesn't work for CBGA's, which have 90/10 solder balls that don't melt
during reflow. These do require solder paste to replace them.
Peter
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] BGA Rework Using Paste vs. No
Paste
02/01/02 12:54 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Jeff
Ferry
Fellow TechNetters,
We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.
What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?
Thanks,
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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