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Date:         Tue, 8 Jan 2002 16:24:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tom Colby <[log in to unmask]>
Subject:      Re: Off Topic:The MoonMan has a "Microsoft Moment"
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Something promising may be on the horizon.

See: http://www.lindows.com/

I wonder if this would be the best (does windoze have a best?) or the worst
of both worlds. Anyone have any information other than what is provided at
this website?

Tom

At 12:00 AM 1/8/02 -0600, you wrote:
>Date:    Mon, 7 Jan 2002 02:11:08 -0500
>From:    Jeff Seeger <[log in to unmask]>
>Subject: Re: Off Topic:The MoonMan has a "Microsoft Moment"
>
>,
>
>         What you gents are pointing out are the reasons I've quit
>         using any Microsloth products, for several years.  Unix
>         has been very very good for me.
>
>         Sadly I cannot say the same about our whole outfit, as the
>         office stuff and two of our CAD proggies remain mired in
>         the Windoze world, to my chagrin and that of our Sysop.
>
>         In fact, maybe some of you could help.  If you use CAM350,
>         perhaps you could add your voice to those of us who would
>         like to keep it running on Unix.  Perhaps if enough of us
>         call and beg...
>
>         Cheers,

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Date:         Tue, 8 Jan 2002 16:37:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Scott Westheimer <[log in to unmask]>
Subject:      Thermal Paper
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0009_01C19862.B7A782B0"

This is a multi-part message in MIME format.

------=_NextPart_000_0009_01C19862.B7A782B0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I was wondering if someone out there might remember a paper material =
that was used to find the location of a electrical shorts on boards by =
supplying current on the net and placing the paper on top of the board =
turning the paper different colors where the short was located.

Scott B. Westheimer
General Manager
Gultech North Carolina, Inc.
E-mail: [log in to unmask]
Phone: (919)872-0100
Fax: (919)713-4849
Cell: (919)649-1510
Direct# (919)-713-4830


------=_NextPart_000_0009_01C19862.B7A782B0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I was wondering if someone out there =
might remember=20
a paper material that was used to find the location of a electrical =
shorts on=20
boards by supplying current on the net and placing the paper on top of =
the board=20
turning the paper different colors where the short was =
located.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Scott B. Westheimer<BR>General =
Manager<BR>Gultech=20
North Carolina, Inc.<BR>E-mail: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><B=
R>Phone:=20
(919)872-0100<BR>Fax: (919)713-4849<BR>Cell: (919)649-1510<BR>Direct#=20
(919)-713-4830<BR></FONT></DIV></BODY></HTML>

------=_NextPart_000_0009_01C19862.B7A782B0--

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Date:         Tue, 8 Jan 2002 17:10:23 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Use of IPC-7095, -SM-782, and -7525

TechNetters, I have a question regarding consistency of 7095 (Design and
Assembly Process Implementation for BGAs), SM-782 (the Surface Mount pad
document), and 7525 (Stencil Design Guidelines), resulting from discussion
with process engineers and techs earlier today.

We were looking at a BGA, 20x20 package, with 1.27 mm pitch.  The stencil
design guidelines (7525, Table 1 on p. 4), call for an aperture of 0.75 mm.
 That table also refers to a 0.80 mm pad.  SM-782 (section 14) says a 20x20
BGA will have 0.75 mm balls that should go onto 0.60 mm pads.  Do these
documents contradict each other regarding pad size, and is 7525 wrong with
regard to BGA stencils?

Further, the bare board does have 0.60 mm pads for the BGA.  7095, in
6.2.1, p. 33, says "land diameter is usually smaller than the ball
diameter..land size reduction of 20 to 25% has been determined to provide
reliable attachment...".

As always, thanks for any comments.  Lou Hart

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Date:         Tue, 8 Jan 2002 14:17:41 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Butman <[log in to unmask]>
Subject:      Re: Words of wisdom
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

HI Ron,

Thanks for the smiles.

thanx

Bill
--- "Dieselberg, Ron" <[log in to unmask]>
wrote:
> I feel that because of my advanced age and mushy
> brain I can send this to
> you all without fear of beatings or such. See the
> inner wisdom of each
> statement. The first one obviously fits me
> perfectly.
>
> Subject: Words of Wisdom
>
>
> Inside every older person is a younger person --
> wondering what the
> heck happened.
>
> Love is grand; divorce is a hundred grand.
>
> I am in shape. Round is a shape.
>
> Time may be a great healer, but it's a lousy
> beautician.
>
> Never be afraid to try something new.
> Remember, amateurs built the ark. Professionals
> built the Titanic.
>
> Conscience is what hurts when everything else feels
> so good.
>
> Talk is cheap because supply exceeds demand.
>
> Even if you are on the right track, you'll get run
> over if you just sit
> there.
>
> Politicians and diapers have one thing in common.
> They should both be
> changed regularly and for the same reason.
>
> An optimist thinks that this is the best possible
> world. A pessimist
> fears that this is true.
>
> There will always be death and taxes; however, death
> doesn't get
> worse every year.
>
> In just two days, tomorrow will be yesterday.
>
> I am a nutritional overachiever.
>
> I am having an out of money experience.
>
> I plan on living forever. So far, so good.
>
> Practice safe eating -- always use condiments.
>
> A day without sunshine is like .......night.
>
> If marriage were outlawed, only outlaws would have
> in-laws.
>
> It's frustrating when you know all the answers, but
> nobody bothers to
> ask you the questions.
>
> The real art of conversation is not only to say the
> right thing at
> the right time, but also to leave unsaid the wrong
> thing at the
> tempting moment.
>
> Brain cells come and brain cells go, but fat cells
> live forever.
>
> Age doesn't always bring wisdom. Sometimes age comes
> alone.
>
> Life not only begins at forty, it also begins to
> show.
>
> And this one is the real truth, so pay attention:
>
> You don't stop laughing because you grow old, you
> grow old because
> you stopped laughing.
>
> Ron Dieselberg
> Trainer/Auditor
> CMC ELECTRONICS
> CINCINNATI
> [log in to unmask]
>


=====
Bill Butman
Circuit Technology Center
45 Research Drive
Haverhill, MA 01832

__________________________________________________
Do You Yahoo!?
Send FREE video emails in Yahoo! Mail!
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Date:         Tue, 8 Jan 2002 17:04:02 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Thermal Paper
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_FBA6F1EE.08690436"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_FBA6F1EE.08690436
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

yep used to use it when I built PCB's for Cray.  Slick stuff.  I have only =
seen it in use once since then. =20

Kathy  =20

--=_FBA6F1EE.08690436
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>yep used to use it when I built PCB's for Cray.&nbsp; Slick stuff.&nbsp; I
have only seen it in use once since then.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy &nbsp; </DIV></BODY></HTML>

--=_FBA6F1EE.08690436--

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Date:         Tue, 8 Jan 2002 15:19:52 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: Thermal Paper
MIME-Version: 1.0
Content-Type: text/plain

Edmund has liquid crystal temperature sensitive sheets in their optics
catalog.  They should do the job nicely.  12" x 12" = $21.00
www.edmundoptics.com
> -----Original Message-----
> From: Kathy Kuhlow [SMTP:[log in to unmask]]
> Sent: Tuesday, January 08, 2002 3:04 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Thermal Paper
>
> yep used to use it when I built PCB's for Cray.  Slick stuff.  I have only
> seen it in use once since then.
>
> Kathy    << File: TEXT.htm >>

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Date:         Tue, 8 Jan 2002 17:24:21 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      reference paper
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

a mechanical engineer here passed along this report on a solder joint study that some of you may be interested in.  you can get it at:

http://www.packaging.buffalo.edu/paper4.pdf

phil

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Date:         Tue, 8 Jan 2002 20:35:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McCabe, Chris" <[log in to unmask]>
Subject:      Board numbering convention for Panels
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

        Is there an industry standard for numbering, and identifying boards
on a panel? At Bose, we are installing updated data collection systems in
our electronics manufacturing process and have noticed that CAD designers,
test engineers and operators may designate boards differently on a panel. We
also have had designers makes boards "reversible" on a line so that  you
have to be careful of board orientation on the conveyor when using automated
test equipment.
Unless there is an industry standard, we will be requiring a process flow
arrow on the panel which will be lined up with the fixed rail of our
conveyors and help operators to keep the orientation on the conveyor the
same. We will then visually identify the board number on the panel in the
silk-screen as a number enclosed in a circle. The board numbering scheme
would be from left to right, if there were only one row of boards on a panel
and left to right - bottom (closest to the operator) to top on panels with
multiple rows of boards.
I would appreciate any feedback from the group if a standard exists, and if
not, what practices they employ to accomplish this task. Thanks.

Regards,

Chris McCabe
Corporate Quality
Bose Corporation

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Date:         Wed, 9 Jan 2002 10:52:47 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Removal of Conformal Coating
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Morning, All,

This is one for Graham really. I'm looking, please, for your valuable
assistance to determine the best methods, solvents and equipment for
completely stripping Humiseal 1B31 from Board Assemblies.

The boards are military avionics boards, the volume/qty that require
stripping is low, but they need to be cleaned well enough to avoid coating
residues contaminating connector pins and getting inside unsealed
components that weren't intended to be internally coated.

Can thinners/solvents be recycled or must they be disposed of once the
coating reaches a certain concentration?
At what concentration level does the coating in the solvent cause as much
contamination as it removes?
How is it measured?

I haven't had to strip boards for a while, and when I did, the only
facility we had were three small tanks of humiseal thinner to soak/strip,
wash and final rinse the boards of coating, then doing a DI water wash on
them. The first tank was emptied and cleaned quite ofen, the wash tank then
became the strip tank, the rinse tank became the wash tank and the cleaned
out strip tank then became the rinse tank. I'm hoping there is something a
little more sophisticated now that doesn't involve soaking the boards, as
this method allows a lovely thin coating of humiseal to get into every nook
and cranny there is, and it was impossible to prevent it getting where you
didn't want it.

Does anyone have a set-up they can recommend and send me details about?

Many TIA's

Peter Duncan

[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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Date:         Wed, 9 Jan 2002 12:39:07 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Staking compounds
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Doug,

We used to use Araldite or Loctite "Black Tack" in my former incarnation
but moved to Eccobond 45 for securing components, hay wires, etc to boards.

Peter Duncan




                    dopauls@ROCKWELLC
                    OLLINS.COM               To:     [log in to unmask]
                    Sent by: TechNet         cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    <[log in to unmask]>        Aero/ST Group)
                                             Subject:     [TN] Staking compounds

                    01/08/02 03:40 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Good day all,

I am curious as to what all y'all use for staking compounds (to fix wires
or components in place) on your assemblies, especially if you are in the
high-rel area or aerospace sector.  Thanks.

Doug Pauls
Rockwell Collins

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[This e-mail is confidential and may also be privileged. If you are not the
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not copy or use it for any purpose, nor disclose its contents to any other
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Date:         Wed, 9 Jan 2002 12:59:40 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: ONE LAST QUESTION ABOUT QUALITY
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Earl,

Hope the hibernation goes well while the hyper nation continues it's merry
whirl.

Ref your Delphi quote - there was a time when the term "Man" or "Men" was
all-embracing (took in both men AND women) and meant mankind in general.
These days men and women seem to have become separate species, which is a
shame. I like the embracing bit - can't we get back to that?

Peter Duncan




                    Earl Moon
                    <[log in to unmask]        To:     [log in to unmask]
                    M.COM>               cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:             Aero/ST Group)
                    TechNet              Subject:     Re: [TN] ONE LAST QUESTION ABOUT
                    <[log in to unmask]        QUALITY
                    ORG>


                    01/08/02
                    10:40 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum."






Ioan,

Thanks for the history lesson. Isn't it remarkable the cycle of things.

Speaking of the good old days - do you remember when most everyone had
jobs?
Talk about wisdom and no compromise, how about those car folks. Ford is
about to layoff another 20,000 or so folks why introducing new models
costing more than some of their employee's houses.

How about GM introducing super charged 500 hp models while laying off an
unknown number of people - soon to be announced. All this while gas
production is being cut by OPEC and we have no "local" sources. Where do
you
think prices are going soon? More management wisdom!

I'll bet those upper management types still are making a few bucks through
their infinite wisdom. Bet they can weather the storm and buy what they are
currently designing though few others can while 0% financing car returns
are
soaring as are home repo's.

Where's the little, economical car we're all going to need just to get
increasingly high priced food products - with warning labels. Hell, where
are the jobs? There's wisdom and quality in all that.

Again, your historical thoughts ring through. You and Brian might
appreciate
this:

An Introduction to
the Oracle at Delphi

"In this place I am minded to build a glorious temple to be an oracle for
MEN, and here they will always bring perfect hecatombs, both they who dwell
in Peloponnesus and the men of Europe and from all the wave-washed isles,
coming to question me. And I will deliver to them all counsel that cannot
fail, answering them in my rich temple."

What comes around, goes around. What of the women of Delphi?

Actually, my cave is a bit more than that. I was attempting to build a
social club on a couple of acres in BF Montana. However, I ran just a bit
afoul of the law. So, I'll just write there. Sorry Paul "Classic."

Moonman
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Date:         Wed, 9 Jan 2002 13:01:55 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Staking compounds
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

It did us well enough in Marconi for a while, but took a bit longer to cure
(or something) than alternatives. We changed to Eccobond 45 eventually.

Peter Duncan




                    "Bissonnette,
                    Jean-Francois"         To:     [log in to unmask]
                    <JBissonnette@W        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    ABTEC.COM>             Aero/ST Group)
                    Sent by:               Subject:     Re: [TN] Staking compounds
                    TechNet
                    <[log in to unmask]
                    G>


                    01/08/02 10:56
                    PM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Since we're in that subject, anyone has a good or bad opinion on loctite
444 (Tack pack).  We sometimes use it for staking wire
to pcb.

Thanks!

JF
     -----Original Message-----
     From: Hinners Hans M Civ WRALC/LUGE
     [mailto:[log in to unmask]]
     Sent: Tuesday, January 08, 2002 9:44 AM
     To: [log in to unmask]
     Subject: Re: [TN] Staking compounds

     Hi All,

     This is great information.  I've had an Assembly supplier suggest
     using an RTV to stake discrete components to FR-4.  Graham confirmed
     that it wasn't a good combination with a silicone based conformal
     coating.  (Thanks Graham.)  The last thing I or the customer needs is
     dewetting of the conformal coating.  My applications are hi-rel
     military avionics - in a rather harsh environment: high vibration,
     high humidity and some salt water.

     Is there some cutoff point when it's better to go with mechanical
     staking?  I'm new to staking.

     Hans



     Integrity First  -  Service Before Self  -  Excellence in All We Do
     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     Hans M. Hinners
     Electronics Engineer
     Warner Robins - Air Logistics Center (WR-ALC/LUGE)
     226 Cochran Street
     Robins AFB GA 31098-1622

     mailto:[log in to unmask]

     Com: (478) 926 - 5224
     Fax:   (478) 926 - 4911
     DSN Prefix: 468


          -----Original Message-----
          From: Dieselberg, Ron [mailto:[log in to unmask]]
          Sent: Tuesday, January 08, 2002 7:28 AM
          To: [log in to unmask]
          Subject: Re: [TN] Staking compounds



          Doug, we have used CONAP K-20 for a long time with good results.
          We have also used Loctite 416 with 18580 activator. The Loctite
          is easier to use since it "sets" more quickly.


          All depends on how you want to use it and how much time you have
          available for curing.
          In either case be sure the materials that you are going to stake
          to are "sqweekey" clean!


          Ron Dieselberg
          Trainer/Auditor
          CMC ELECTRONICS
          CINCINNATI
          [log in to unmask]


                    -----Original Message-----
                    From:   [log in to unmask] [
                    mailto:[log in to unmask]]
                    Sent:   Monday, January 07, 2002 14:41 PM
                    To:     [log in to unmask]
                    Subject:        [TN] Staking compounds


                    Good day all,


                    I am curious as to what all y'all use for staking
                    compounds (to fix wires
                    or components in place) on your assemblies, especially
                    if you are in the
                    high-rel area or aerospace sector.  Thanks.


                    Doug Pauls
                    Rockwell Collins


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Date:         Wed, 9 Jan 2002 00:28:29 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_138.772baf3.296d2efd_boundary"

--part1_138.772baf3.296d2efd_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hello all you Techies ou there. First off - Happy New Year to one and all -
trusting this year will be a tad better than the last one we had.

I've been reading the postings about hole-wall sep. I must agree with Susan
on the point she brought up - on " Low Tg material". When using low Tg
material - by the time an aggressive desmear or etchback is applied....at
times...all is left but the glass bundles. Then of course a good glass
etch...and voila...not much there.

Poor conditioning in the PTH process....and of course....it is much more
difficult to deposit copper on glass strands .... and eventually by the time
we get to "Thermal Shocking" the board " HASL " ..... lucky if anything is
stuck to anything.

Also, a fast accelerated electroless deposit doesn't help the condition
either. Gouging during drilling adds to the final condition....and so on and
so on.

Susan....not for the sake of sounding rude...but isn't microsectioning a
visual assessment?

Hole walls do explode..especially when there isn't enough electroplated
copper in the through-holes. Any good microsection will diplay that. Copper
must attain a certain thickness in order to take the HASL application. If
not, you'll usually see the solder being sucked in on one side. If you
section that hole, 9 out of 10 times one will see, that there is an
insufficient electroplated copper deposit in it.

But in my most humble opinion, there are several causes as to why hole-wall
pull away,resin recession and separation can be all linked into one major
situation...every board shop has a situation...not a problem...and
eventually...every situation is finally put under control.

If one saw sections with copper adhering to the inner layers and not the
resin, i would have to believe that there was no copper in the hole wall to
begin with. But again, that's only my opinion...and we know what they say
about opions...they're like the nose on a face...everybody has one.

Cheers

Rick Fudalewski

Florida Cirtech

--part1_138.772baf3.296d2efd_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hello all you Techies ou there. First off - Happy New Year to one and all - trusting this year will be a tad better than the last one we had.
<BR>
<BR>I've been reading the postings about hole-wall sep. I must agree with Susan on the point she brought up - on " Low Tg material". When using low Tg material - by the time an aggressive desmear or etchback is applied....at times...all is left but the glass bundles. Then of course a good glass etch...and voila...not much there.
<BR>
<BR>Poor conditioning in the PTH process....and of course....it is much more difficult to deposit copper on glass strands .... and eventually by the time we get to "Thermal Shocking" the board " HASL " ..... lucky if anything is stuck to anything.
<BR>
<BR>Also, a fast accelerated electroless deposit doesn't help the condition either. Gouging during drilling adds to the final condition....and so on and so on.
<BR>
<BR>Susan....not for the sake of sounding rude...but isn't microsectioning a visual assessment?
<BR>
<BR>Hole walls do explode..especially when there isn't enough electroplated copper in the through-holes. Any good microsection will diplay that. Copper must attain a certain thickness in order to take the HASL application. If not, you'll usually see the solder being sucked in on one side. If you section that hole, 9 out of 10 times one will see, that there is an insufficient electroplated copper deposit in it.
<BR>
<BR>But in my most humble opinion, there are several causes as to why hole-wall pull away,resin recession and separation can be all linked into one major situation...every board shop has a situation...not a problem...and eventually...every situation is finally put under control.
<BR>
<BR>If one saw sections with copper adhering to the inner layers and not the resin, i would have to believe that there was no copper in the hole wall to begin with. But again, that's only my opinion...and we know what they say about opions...they're like the nose on a face...everybody has one.
<BR>
<BR>Cheers
<BR>
<BR>Rick Fudalewski
<BR>
<BR>Florida Cirtech</FONT></HTML>

--part1_138.772baf3.296d2efd_boundary--

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=========================================================================
Date:         Wed, 9 Jan 2002 09:23:58 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Off Topic:The MoonMan has a "Microsoft Moment"
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Lindows is also based on WINE

Brian

Tom Colby wrote:
>
> Something promising may be on the horizon.
>
> See: http://www.lindows.com/
>
> I wonder if this would be the best (does windoze have a best?) or the worst
> of both worlds. Anyone have any information other than what is provided at
> this website?
>
> Tom
>
> At 12:00 AM 1/8/02 -0600, you wrote:
> >Date:    Mon, 7 Jan 2002 02:11:08 -0500
> >From:    Jeff Seeger <[log in to unmask]>
> >Subject: Re: Off Topic:The MoonMan has a "Microsoft Moment"
> >
> >,
> >
> >         What you gents are pointing out are the reasons I've quit
> >         using any Microsloth products, for several years.  Unix
> >         has been very very good for me.
> >
> >         Sadly I cannot say the same about our whole outfit, as the
> >         office stuff and two of our CAD proggies remain mired in
> >         the Windoze world, to my chagrin and that of our Sysop.
> >
> >         In fact, maybe some of you could help.  If you use CAM350,
> >         perhaps you could add your voice to those of us who would
> >         like to keep it running on Unix.  Perhaps if enough of us
> >         call and beg...
> >
> >         Cheers,
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date:         Wed, 9 Jan 2002 18:17:29 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Off Topic:The MoonMan has a "Microsoft Moment"
MIME-Version: 1.0
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Sounds like a Chinese copy to me!

Peter Duncan





                    Brian Ellis
                    <b_ellis@PROTO        To:     [log in to unmask]
                    NIQUE.COM>            cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:              Aero/ST Group)
                    TechNet               Subject:     Re: [TN] Off Topic:The MoonMan has a
                    <[log in to unmask]        "Microsoft Moment"
                    RG>


                    01/09/02 03:23
                    PM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Lindows is also based on WINE

Brian

Tom Colby wrote:
>
> Something promising may be on the horizon.
>
> See: http://www.lindows.com/
>
> I wonder if this would be the best (does windoze have a best?) or the
worst
> of both worlds. Anyone have any information other than what is provided
at
> this website?
>
> Tom
>
> At 12:00 AM 1/8/02 -0600, you wrote:
> >Date:    Mon, 7 Jan 2002 02:11:08 -0500
> >From:    Jeff Seeger <[log in to unmask]>
> >Subject: Re: Off Topic:The MoonMan has a "Microsoft Moment"
> >
> >,
> >
> >         What you gents are pointing out are the reasons I've quit
> >         using any Microsloth products, for several years.  Unix
> >         has been very very good for me.
> >
> >         Sadly I cannot say the same about our whole outfit, as the
> >         office stuff and two of our CAD proggies remain mired in
> >         the Windoze world, to my chagrin and that of our Sysop.
> >
> >         In fact, maybe some of you could help.  If you use CAM350,
> >         perhaps you could add your voice to those of us who would
> >         like to keep it running on Unix.  Perhaps if enough of us
> >         call and beg...
> >
> >         Cheers,
>
>
---------------------------------------------------------------------------------

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>
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Date:         Wed, 9 Jan 2002 06:33:57 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: hole wall pull away and resin recession
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Hi Rick and all
In my humble opinion - visual inspections are ones that can be done and still
allow you to use the product, if found in conformance.  Microsection
inspections are destructive and the board can no longer be used.

Susan Mansilla
Robisan Lab

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Date:         Wed, 9 Jan 2002 05:48:22 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Thermal Paper
X-To:         Kathy Kuhlow <[log in to unmask]>

There is a liquid form used to find ESD damages in semiconductor and hybrid
devices. Once applied, in a FA laboratory, on the bare substrate, a mild
current is applied and the damaged area appears.

MoonMan

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Date:         Wed, 9 Jan 2002 08:05:41 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Susan,

But aren't test coupons built on the edge of the panels made to be
sectioned? You can do both X and Y one thermally stressed, one not and see a
lot of potential problems. This causes absolutely no damage to the board
itself.

You don't need to do 100%, but occasional sampling may not be a bad idea.
You board vendor may even prepare them for you if you request it. (They may
be doing it as part of their own evaluation.)

Alain Savard
QA-PCB
CAE Inc.

-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: January 9, 2002 6:34 AM
To: [log in to unmask]
Subject: Re: [TN] hole wall pull away and resin recession


Hi Rick and all
In my humble opinion - visual inspections are ones that can be done and
still
allow you to use the product, if found in conformance.  Microsection
inspections are destructive and the board can no longer be used.

Susan Mansilla
Robisan Lab

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Date:         Wed, 9 Jan 2002 07:08:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
X-To:         [log in to unmask]

I have always stressed the use of quality conformance test circuitry and
attendant test coupons. Amazing how many people won't/don't use them.

MoonMan

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Date:         Wed, 9 Jan 2002 13:41:03 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Olivia Mc Dermott <[log in to unmask]>
Subject:      Lead Length/Protrusion
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2 lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

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Date:         Wed, 9 Jan 2002 08:58:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Removal of Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello Peter Duncan

Humiseal's Stripper 1080 does an excellent job.  You already described using
the 3 wash/strip pans and I've found that works very well.  We never did an
analysis on our stripping pans.  We had some motivated operators that would
change out the solution once they saw it lose effectiveness or start leaving
a conformal coating ring in the pan.  Since it was a single 8 hour shift/day
process the pans would remain covered in the fume hood when not in use.
This was for a real low/no volume process otherwise we might have had
tighter controls.  The used stripper was poured into 10 gallon totes that
were picked up by the haz mat folks for disposal.

I also played with a "water pick" device that could get stripping solution
under components real well - can't remember the name.  We learned real quick
that spot stripping didn't work - you have to strip the entire board, run it
through the aqueous cleaner to remove residues and then continue the repair
process.  We used a black light inspection step (sometimes with a Mantis
Macroscope) to check connectors & the board for residue.  Our customers,
also military, expected to see a uniform, "like new" conformal coating on
the repaired assemblies.

I think Humiseal might have come out with a gel version of that stripper -
you might check @ http://www.humiseal.com  And yeah, Graham is the man when
it comes to conformal coating.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Tuesday, January 08, 2002 9:53 PM
To: [log in to unmask]
Subject: [TN] Removal of Conformal Coating


Morning, All,

This is one for Graham really. I'm looking, please, for your valuable
assistance to determine the best methods, solvents and equipment for
completely stripping Humiseal 1B31 from Board Assemblies.

The boards are military avionics boards, the volume/qty that require
stripping is low, but they need to be cleaned well enough to avoid coating
residues contaminating connector pins and getting inside unsealed
components that weren't intended to be internally coated.

Can thinners/solvents be recycled or must they be disposed of once the
coating reaches a certain concentration?
At what concentration level does the coating in the solvent cause as much
contamination as it removes?
How is it measured?

I haven't had to strip boards for a while, and when I did, the only
facility we had were three small tanks of humiseal thinner to soak/strip,
wash and final rinse the boards of coating, then doing a DI water wash on
them. The first tank was emptied and cleaned quite ofen, the wash tank then
became the strip tank, the rinse tank became the wash tank and the cleaned
out strip tank then became the rinse tank. I'm hoping there is something a
little more sophisticated now that doesn't involve soaking the boards, as
this method allows a lovely thin coating of humiseal to get into every nook
and cranny there is, and it was impossible to prevent it getting where you
didn't want it.

Does anyone have a set-up they can recommend and send me details about?

Many TIA's

Peter Duncan

[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]

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=========================================================================
Date:         Wed, 9 Jan 2002 10:05:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit

Susan,
Thanks for the feedback.
Since the inner layers must be attached we would have to cross-section to see
if that were the condition, which would destroy the board anyway.
We are sure of the HASL stress as the cause first, by visual and later by cross-
section. It involved only thick (.200") boards. We solved the problem by baking
the boards for 4-8 hrs @ 300F, although we don't really know if the pullaway
was due to trapped moisture or the "shock" of HASL.
Joe


Quoting [log in to unmask]:

> Joe
> I have seen many microsections in years passed where the plating was
> stuck to
> the inner layers only and none to the laminate.  Inner layers must be
> attached.  Military specs still have a resin recession requirement "as
> received".  IPC specs evaluate after stress and therefore have dropped
> the
> consideration that resin recession is a defect.
>
> The theory being if there is no requirement after stress, then why have
> a
> limit before?
>
> Inner layers must be attached.
>
> How do you know the hole wall "explodes" or "delaminates" after HASL?
> Is
> this by microsection or visual assessment?
>
> Susan
>



Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Wed, 9 Jan 2002 08:05:15 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2 lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

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=========================================================================
Date:         Wed, 9 Jan 2002 10:12:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit

WE use coupons on just about every job we do, but when the question is the
integrity of the board itself checking the coupon provides only some certainty.
Ultimately the customer must decide if the product is "usable".


Quoting Earl Moon <[log in to unmask]>:

> I have always stressed the use of quality conformance test circuitry
> and
> attendant test coupons. Amazing how many people won't/don't use them.
>
> MoonMan
>
> ------------------------------------------------------------------------------
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> additional
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> ext.5315
> ------------------------------------------------------------------------------
---
>



Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Wed, 9 Jan 2002 09:12:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Franck, George" <[log in to unmask]>
Subject:      Re: Use of IPC-7095, -SM-782, and -7525
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

I have been playing around, blindly, with this topic for a little while.
This is what I have learned, precious little that it is.

The answer depends on the BGA construction.  Many/most BGAs do not actually
have balls on them, they have 'bumps' of 63/37 solder.  These bumps will
completely melt during reflow, allowing the BGA to float on molten solder
during the soldering process.  For these components, you *generally* want
the pad on the board to be the same size as the pad on the component.  With
the pads being the same size, the resulting solder joint will be
symmetrical, top to bottom.  Since the writers of the Specs, (bless them
all), can only guess at what pad size the manufacturers of future BGAs will
use, it becomes difficult to always have the right answer.

Other BGAs have real 90% Pb balls on them.  These do not melt, and the
soldering process for these components create two solder joints.  One from
the Component to the 90% Pb ball, and a second from the ball to the board.
In this case, the board pad size will depend on the ball size.

There are other BGA configurations, such as solder columns, which, again,
you have to look at individually.

As an aside question (or complaint), Have people found that the information
the component manufacturers put in their component spec sheets (pad size and
spacing, and what has to be done to route the pin out....)  Have people
found that these follow any kind of DFM process?  In my experience, when my
Engineers choose the smallest, most dense component packages, we often end
up with a very interesting Fab and Assembly designs.

George Franck

-----Original Message-----
From: Lou Hart [mailto:[log in to unmask]]
Sent: Tuesday, January 08, 2002 5:10 PM
To: [log in to unmask]
Subject: [TN] Use of IPC-7095, -SM-782, and -7525


TechNetters, I have a question regarding consistency of 7095 (Design and
Assembly Process Implementation for BGAs), SM-782 (the Surface Mount pad
document), and 7525 (Stencil Design Guidelines), resulting from discussion
with process engineers and techs earlier today.

We were looking at a BGA, 20x20 package, with 1.27 mm pitch.  The stencil
design guidelines (7525, Table 1 on p. 4), call for an aperture of 0.75 mm.
 That table also refers to a 0.80 mm pad.  SM-782 (section 14) says a 20x20
BGA will have 0.75 mm balls that should go onto 0.60 mm pads.  Do these
documents contradict each other regarding pad size, and is 7525 wrong with
regard to BGA stencils?

Further, the bare board does have 0.60 mm pads for the BGA.  7095, in
6.2.1, p. 33, says "land diameter is usually smaller than the ball
diameter..land size reduction of 20 to 25% has been determined to provide
reliable attachment...".

As always, thanks for any comments.  Lou Hart

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Date:         Wed, 9 Jan 2002 09:32:44 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Please stop revising these documents.

Dave Fish
----- Original Message -----
From: "Mel Parrish" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 09, 2002 8:05 AM
Subject: Re: [TN] Lead Length/Protrusion


> Olivia
> Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
> was released a couple of months ago and is available on the IPC web site.
> By the way, work is in progress toward Revision D to this document.  We
have
> accumulated a number of comments and would appreciate any additional
> information that you would like to see in the new 610. We certainly could
> use some additional information on the newer technology applications.
>
> The next technical meeting will be at APEX on 19 Jan.
>
> Mel Parrish
> Soldering Technology International
> Madison, AL
> 256 705 5530
> 256 705 5538 Fax
> [log in to unmask]
>
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
> Sent: Wednesday, January 09, 2002 5:41 AM
> To: [log in to unmask]
> Subject: [TN] Lead Length/Protrusion
>
>
> Hi ALl,
> Why are there 2 references to lead length/protrusion in IPC-A-610C. In
> 'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
> protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1
lead
> protrusion for class 2 is 2.3mm. Which one do we use?
>
> _________________________________________________________________
> MSN Photos is the easiest way to share and print your photos:
> http://photos.msn.com/support/worldwide.aspx
>
> --------------------------------------------------------------------------
--
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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SET
> Technet NOMAIL
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
--
> -----
>
> --------------------------------------------------------------------------
-------
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=========================================================================
Date:         Wed, 9 Jan 2002 09:36:23 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: ONE LAST QUESTION ABOUT QUALITY
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Peter,
This confusing situation exist only in English. In German the distiction is
quite clear: Mann, Frau, Mensch, Menschen [man, woman, human, mankind]. Thus,
the Delphi translation is likely not quite correct--'man' as you point out
should really be translated 'human.'

Best regards,
Werner Engelmaier

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Date:         Wed, 9 Jan 2002 09:36:22 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi All,
To really address a problem, one needs to understand its root cause(s).
Resin Ressession and Hole Wall Pullaway [Separation] are related phenomena.
Unlike a hole in a steel plate, a hole in a PCB gets smaller when heated, not
larger--this is the consequence of the constraining effect of the glass-fiber
reinforcements. Thus, on heating the epoxy will move towards the copper
plating, not away. The resin will 'recede' to its initial geometry on
cooling. This recession on cooling can leave voids when other materials do
not return to their original position.
What happens is that the resin on heating will compress the copper barrel.
For PTHs with thin plating, large diameters, low Tg resins, and absence of
internal lands this is more pronounced. This barrel compression can
plastically deform the copper barrel which thus will not return to its
original geometry--the resin will. The result is 'hole wall pullaway.'

Werner Engelmaier

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Date:         Wed, 9 Jan 2002 08:37:08 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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The URL for 610C, Amendment 1 is http://www.ipc.org/html/fsresources.htm
"IPC Documents Available for Download"
IPC-A-610C, Amendment 1, November 2001.
Mel

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2 lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

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Date:         Wed, 9 Jan 2002 09:38:10 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Re: Lead Length/Protrusion

Olivia, maybe others will have noticed this, too, but Amendment 1 to 610C changes 2.3 to 2.5.  Lou Hart

-----Original Message-----
From:   Olivia Mc Dermott [SMTP:[log in to unmask]]
Sent:   Wednesday, January 09, 2002 8:41 AM
To:     [log in to unmask]
Subject:        [TN] Lead Length/Protrusion

Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2 lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

---------------------------------------------------------------------------------
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Date:         Wed, 9 Jan 2002 09:42:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Re: Lead Length/Protrusion

Mel, can I suggest removing 10.4 from 610 entirely.  It deals with solder
mask, not laminate.  The "defect" added in amendment 1 is redundant with
portions of section 9.  Lou Hart

-----Original Message-----
From:   Mel Parrish [SMTP:[log in to unmask]]
Sent:   Wednesday, January 09, 2002 11:05 AM
To:     [log in to unmask]
Subject:        Re: [TN] Lead Length/Protrusion

Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We
have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

------------------------------------------------------------------------
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Date:         Wed, 9 Jan 2002 09:59:42 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
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Olivia, I wastold by my certifying instructor that the value in Table 6-1
should be 2.5. 2.3 is believed to be a typo. It was corrected in my copy
during class.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Olivia Mc Dermott
[mailto:[log in to unmask]]
                Sent:   Wednesday, January 09, 2002 8:41 AM
                To:     [log in to unmask]
                Subject:        [TN] Lead Length/Protrusion

                Hi ALl,
                Why are there 2 references to lead length/protrusion in
IPC-A-610C. In
                'Component Installation Location/Orientation' - point
5.2.7.1 table 5.2 lead
                protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2
table 6.1 lead
                protrusion for class 2 is 2.3mm. Which one do we use?


_________________________________________________________________
                MSN Photos is the easiest way to share and print your
photos:
                http://photos.msn.com/support/worldwide.aspx


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<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2652.35">
<TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Olivia, I wastold by my certifying =
instructor that the value in Table 6-1 should be 2.5. 2.3 is believed =
to be a typo. It was corrected in my copy during class.</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Olivia Mc =
Dermott [<A =
HREF=3D"mailto:[log in to unmask]">mailto:oliviamcdermott01@H=
OTMAIL.COM</A>]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Wednesday, January 09, 2002 8:41 AM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">[TN] Lead Length/Protrusion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Hi ALl,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Why are there 2 references to lead =
length/protrusion in IPC-A-610C. In</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">'Component Installation =
Location/Orientation' - point 5.2.7.1 table 5.2 lead</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">protrusion for class 2 is 2.5mm but =
in 'Soldering' point 6.2 table 6.1 lead</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">protrusion for class 2 is 2.3mm. =
Which one do we use?</FONT>
</P>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">_________________________________________________________=
________</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">MSN Photos is the easiest way to =
share and print your photos:</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial"><A =
HREF=3D"http://photos.msn.com/support/worldwide.aspx" =
TARGET=3D"_blank">http://photos.msn.com/support/worldwide.aspx</A></FONT=
>
</P>

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Date:         Wed, 9 Jan 2002 10:15:48 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: undercut specification
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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It is not in the specification. "Normal" undercut varies depending on
methods and materials used in the process of etching. I believe there were
specifications in the now obsolete IPC-D-275. There is some guidance and
discussion of the topic in IPC-2221, and the ammendment.

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Smith, Russell (US
> LA)
> Sent: Tuesday, January 08, 2002 11:41 AM
> To: [log in to unmask]
> Subject: [TN] undercut specification
>
>
>         Just a quick brain dead beginning of the year question , Anyone
> know where in the IPC specs ( if it exists) as to what is considered
> acceptable and unacceptable undercut , (or overhang) on  etched traces,
>
>         Thanks , hope everyone had good holidays and are well!
>
>         Russell Smith
>         vantico LA
>
> ------------------------------------------------------------------
> ---------------
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Wed, 9 Jan 2002 09:17:20 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Lou,
Think we addressed this in the initial meetings for 610D.  For the purpose
of the Amendment, we wanted to have a defect statement for the stand alone
acceptable condition in the 610C, paragraph 10.4.
For those concerned about frequent changes, consider that the last revision
took over three years to complete. So don't hold your breath or get too
concerned just yet.
Best regards,
Mel

It's a beautiful day in ALABAMA!

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Lou Hart
Sent: Wednesday, January 09, 2002 6:42 AM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Mel, can I suggest removing 10.4 from 610 entirely.  It deals with solder
mask, not laminate.  The "defect" added in amendment 1 is redundant with
portions of section 9.  Lou Hart

-----Original Message-----
From:   Mel Parrish [SMTP:[log in to unmask]]
Sent:   Wednesday, January 09, 2002 11:05 AM
To:     [log in to unmask]
Subject:        Re: [TN] Lead Length/Protrusion

Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We
have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

------------------------------------------------------------------------
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Date:         Wed, 9 Jan 2002 10:16:57 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
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How do you find it and download it? I went in circles.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Mel Parrish [mailto:[log in to unmask]]
                Sent:   Wednesday, January 09, 2002 11:37 AM
                To:     [log in to unmask]
                Subject:        Re: [TN] Lead Length/Protrusion

                The URL for 610C, Amendment 1 is
http://www.ipc.org/html/fsresources.htm
                "IPC Documents Available for Download"
                IPC-A-610C, Amendment 1, November 2001.
                Mel

                Mel Parrish
                Soldering Technology International
                Madison, AL
                256 705 5530
                256 705 5538 Fax
                [log in to unmask]



                -----Original Message-----
                From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc
Dermott
                Sent: Wednesday, January 09, 2002 5:41 AM
                To: [log in to unmask]
                Subject: [TN] Lead Length/Protrusion


                Hi ALl,
                Why are there 2 references to lead length/protrusion in
IPC-A-610C. In
                'Component Installation Location/Orientation' - point
5.2.7.1 table 5.2 lead
                protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2
table 6.1 lead
                protrusion for class 2 is 2.3mm. Which one do we use?


_________________________________________________________________
                MSN Photos is the easiest way to share and print your
photos:
                http://photos.msn.com/support/worldwide.aspx


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charset=3Diso-8859-1">
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5.5.2652.35">
<TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">How do you find it and download it? I =
went in circles.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Mel Parrish [<A =
HREF=3D"mailto:[log in to unmask]">mailto:mparrish@SOLDERINGTECH=
.COM</A>]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Wednesday, January 09, 2002 11:37 AM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">Re: [TN] Lead =
Length/Protrusion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">The URL for 610C, Amendment 1 is <A =
HREF=3D"http://www.ipc.org/html/fsresources.htm" =
TARGET=3D"_blank">http://www.ipc.org/html/fsresources.htm</A></FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&quot;IPC Documents Available for =
Download&quot;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">IPC-A-610C, Amendment 1, November =
2001.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Mel</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Mel Parrish</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Soldering Technology =
International</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Madison, AL</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">256 705 5530</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">256 705 5538 Fax</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">[log in to unmask]</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2 FACE=3D"Arial">-----Original Message-----</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">From: TechNet [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]On Behalf Of =
Olivia Mc Dermott</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Sent: Wednesday, January 09, 2002 =
5:41 AM</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Subject: [TN] Lead =
Length/Protrusion</FONT>
</P>
<BR>

<P><FONT SIZE=3D2 FACE=3D"Arial">Hi ALl,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Why are there 2 references to lead =
length/protrusion in IPC-A-610C. In</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">'Component Installation =
Location/Orientation' - point 5.2.7.1 table 5.2 lead</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">protrusion for class 2 is 2.5mm but =
in 'Soldering' point 6.2 table 6.1 lead</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">protrusion for class 2 is 2.3mm. =
Which one do we use?</FONT>
</P>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">_________________________________________________________=
________</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">MSN Photos is the easiest way to =
share and print your photos:</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial"><A =
HREF=3D"http://photos.msn.com/support/worldwide.aspx" =
TARGET=3D"_blank">http://photos.msn.com/support/worldwide.aspx</A></FONT=
>
</P>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">---------------------------------------------------------=
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Date:         Wed, 9 Jan 2002 10:50:18 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
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RE: [TN] Lead Length/ProtrusionRon

Near the bottom of the "On-Line Resources & Databases" page is an item =
...

IPC Documents Available for Download IPC standards and manuals that may =
be downloaded for free.=20

Look there.

Dave Fish
  ----- Original Message -----=20
  From: Dieselberg, Ron=20
  To: [log in to unmask]
  Sent: Wednesday, January 09, 2002 7:16 AM
  Subject: Re: [TN] Lead Length/Protrusion


  How do you find it and download it? I went in circles.=20

  Ron Dieselberg=20
  Trainer/Auditor=20
  CMC ELECTRONICS=20
  CINCINNATI=20
  [log in to unmask]

      -----Original Message-----=20
      From:   Mel Parrish [mailto:[log in to unmask]]=20
      Sent:   Wednesday, January 09, 2002 11:37 AM=20
      To:     [log in to unmask]
      Subject:        Re: [TN] Lead Length/Protrusion=20

      The URL for 610C, Amendment 1 is =
http://www.ipc.org/html/fsresources.htm=20
      "IPC Documents Available for Download"=20
      IPC-A-610C, Amendment 1, November 2001.=20
      Mel=20

      Mel Parrish=20
      Soldering Technology International=20
      Madison, AL=20
      256 705 5530=20
      256 705 5538 Fax=20
      [log in to unmask]




      -----Original Message-----=20
      From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc =
Dermott=20
      Sent: Wednesday, January 09, 2002 5:41 AM=20
      To: [log in to unmask]
      Subject: [TN] Lead Length/Protrusion=20



      Hi ALl,=20
      Why are there 2 references to lead length/protrusion in =
IPC-A-610C. In=20
      'Component Installation Location/Orientation' - point 5.2.7.1 =
table 5.2 lead=20
      protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table =
6.1 lead=20
      protrusion for class 2 is 2.3mm. Which one do we use?=20

      _________________________________________________________________=20
      MSN Photos is the easiest way to share and print your photos:=20
      http://photos.msn.com/support/worldwide.aspx=20

      =
-------------------------------------------------------------------------=
---=20
      -----=20
      Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d=20
      To unsubscribe, send a message to [log in to unmask] with following =
text in=20
      the BODY (NOT the subject field): SIGNOFF Technet=20
      To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]: SET=20
      Technet NOMAIL=20
      To recieve ONE mailing per day of all the posts: send e-mail to=20
      [log in to unmask]: SET Technet Digest=20
      Search previous postings at: www.ipc.org > On-Line Resources & =
Databases >=20
      E-mail Archives=20
      Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional=20
      information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700=20
      ext.5315=20
      =
-------------------------------------------------------------------------=
---=20
      -----=20

      =
-------------------------------------------------------------------------=
--------=20
      Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d=20
      To unsubscribe, send a message to [log in to unmask] with following =
text in=20
      the BODY (NOT the subject field): SIGNOFF Technet=20
      To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]: SET Technet NOMAIL=20
      To recieve ONE mailing per day of all the posts: send e-mail to =
[log in to unmask]: SET Technet Digest=20
      Search previous postings at: www.ipc.org > On-Line Resources & =
Databases > E-mail Archives=20
      Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional=20
      information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700 ext.5315=20
      =
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Ron</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Near the bottom of the "On-Line =
Resources &amp;=20
Databases" page is an item ...</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><A =
href=3D"http://www.ipc.org/html/downloads.htm">IPC=20
Documents Available for Download</A> IPC standards and manuals that may =
be=20
downloaded for free. </FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Look there.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Dave Fish</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>Dieselberg, Ron</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, January 09, =
2002 7:16=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Lead=20
  Length/Protrusion</DIV>
  <DIV><BR></DIV>
  <P><FONT face=3DArial size=3D2>How do you find it and download it? I =
went in=20
  circles.</FONT> </P>
  <P><FONT face=3D"Courier New" size=3D2>Ron Dieselberg</FONT> <BR><FONT =

  face=3D"Courier New" size=3D2>Trainer/Auditor</FONT> <BR><FONT =
face=3D"Courier New"=20
  size=3D2>CMC ELECTRONICS</FONT> <BR><FONT face=3D"Courier New"=20
  size=3D2>CINCINNATI</FONT> <BR><FONT face=3D"Courier New" size=3D2><A=20
  =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></FO=
NT>=20
</P>
  <UL>
    <UL>
      <P><A name=3D_MailData><FONT face=3DArial size=3D2>-----Original=20
      Message-----</FONT></A> <BR><B><FONT face=3DArial =
size=3D2>From:&nbsp;&nbsp;=20
      Mel Parrish [<A=20
      =
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
COM</A>]</FONT></B>=20
      <BR><B><FONT face=3DArial size=3D2>Sent:&nbsp;&nbsp;</FONT></B> =
<FONT=20
      face=3DArial size=3D2>Wednesday, January 09, 2002 11:37 AM</FONT> =
<BR><B><FONT=20
      face=3DArial size=3D2>To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT =
face=3DArial=20
      size=3D2><A =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></FONT>=20
      <BR><B><FONT face=3DArial=20
      =
size=3D2>Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> =
<FONT=20
      face=3DArial size=3D2>Re: [TN] Lead Length/Protrusion</FONT> </P>
      <P><FONT face=3DArial size=3D2>The URL for 610C, Amendment 1 is <A =

      href=3D"http://www.ipc.org/html/fsresources.htm"=20
      target=3D_blank>http://www.ipc.org/html/fsresources.htm</A></FONT> =
<BR><FONT=20
      face=3DArial size=3D2>"IPC Documents Available for =
Download"</FONT> <BR><FONT=20
      face=3DArial size=3D2>IPC-A-610C, Amendment 1, November =
2001.</FONT> <BR><FONT=20
      face=3DArial size=3D2>Mel</FONT> </P>
      <P><FONT face=3DArial size=3D2>Mel Parrish</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>Soldering Technology International</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>Madison, AL</FONT> <BR><FONT face=3DArial size=3D2>256 =
705 5530</FONT>=20
      <BR><FONT face=3DArial size=3D2>256 705 5538 Fax</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>[log in to unmask]</FONT> </P><BR><BR>
      <P><FONT face=3DArial size=3D2>-----Original Message-----</FONT> =
<BR><FONT=20
      face=3DArial size=3D2>From: TechNet [<A=20
      href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]On =
Behalf Of=20
      Olivia Mc Dermott</FONT> <BR><FONT face=3DArial size=3D2>Sent: =
Wednesday,=20
      January 09, 2002 5:41 AM</FONT> <BR><FONT face=3DArial =
size=3D2>To:=20
      [log in to unmask]</FONT> <BR><FONT face=3DArial size=3D2>Subject: =
[TN] Lead=20
      Length/Protrusion</FONT> </P><BR>
      <P><FONT face=3DArial size=3D2>Hi ALl,</FONT> <BR><FONT =
face=3DArial size=3D2>Why=20
      are there 2 references to lead length/protrusion in IPC-A-610C. =
In</FONT>=20
      <BR><FONT face=3DArial size=3D2>'Component Installation =
Location/Orientation'=20
      - point 5.2.7.1 table 5.2 lead</FONT> <BR><FONT face=3DArial=20
      size=3D2>protrusion for class 2 is 2.5mm but in 'Soldering' point =
6.2 table=20
      6.1 lead</FONT> <BR><FONT face=3DArial size=3D2>protrusion for =
class 2 is=20
      2.3mm. Which one do we use?</FONT> </P>
      <P><FONT face=3DArial=20
      =
size=3D2>________________________________________________________________=
_</FONT>=20
      <BR><FONT face=3DArial size=3D2>MSN Photos is the easiest way to =
share and=20
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Date:         Wed, 9 Jan 2002 09:54:45 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
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RE: [TN] Lead Length/ProtrusionRon
Go to the site as indicated ( http://www.ipc.org/html/fsresources.htm )
Scroll down to "IPC Documents Available for Download"  and click on that
title
The second document down is "IPC-A-610C, Amendment 1, November 2001"
Click on "Download Amendment 1"

Mel Parrish


  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Dieselberg, Ron
  Sent: Wednesday, January 09, 2002 7:17 AM
  To: [log in to unmask]
  Subject: Re: [TN] Lead Length/Protrusion


  How do you find it and download it? I went in circles.

  Ron Dieselberg
  Trainer/Auditor
  CMC ELECTRONICS
  CINCINNATI
  [log in to unmask]

      -----Original Message-----
      From:   Mel Parrish [mailto:[log in to unmask]]
      Sent:   Wednesday, January 09, 2002 11:37 AM
      To:     [log in to unmask]
      Subject:        Re: [TN] Lead Length/Protrusion

      The URL for 610C, Amendment 1 is
http://www.ipc.org/html/fsresources.htm
      "IPC Documents Available for Download"
      IPC-A-610C, Amendment 1, November 2001.
      Mel

      Mel Parrish
      Soldering Technology International
      Madison, AL
      256 705 5530
      256 705 5538 Fax
      [log in to unmask]




      -----Original Message-----
      From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
      Sent: Wednesday, January 09, 2002 5:41 AM
      To: [log in to unmask]
      Subject: [TN] Lead Length/Protrusion



      Hi ALl,
      Why are there 2 references to lead length/protrusion in IPC-A-610C. In
      'Component Installation Location/Orientation' - point 5.2.7.1 table
5.2 lead
      protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1
lead
      protrusion for class 2 is 2.3mm. Which one do we use?

      _________________________________________________________________
      MSN Photos is the easiest way to share and print your photos:
      http://photos.msn.com/support/worldwide.aspx

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<HTML><HEAD><TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DTahoma =
color=3D#000080=20
size=3D2>Ron</FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DTahoma =
color=3D#000080 size=3D2>Go to=20
the site as indicated ( <A =
href=3D"http://www.ipc.org/html/fsresources.htm"=20
target=3D_blank><FONT=20
face=3DArial>http://www.ipc.org/html/fsresources.htm</FONT></A><FONT=20
face=3D"Times New Roman" color=3D#000000 size=3D3> <FONT face=3DTahoma =
color=3D#000080=20
size=3D2>)</FONT></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DTahoma =
color=3D#000080><FONT=20
size=3D2>Scroll down to <FONT color=3D#000000><FONT face=3DArial>"IPC =
Documents=20
Available for Download"&nbsp; and click on that=20
title</FONT></FONT></FONT></FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DArial size=3D2>The =
second document=20
down is "IPC-A-610C, Amendment 1, November 2001"</FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DArial size=3D2>Click =
on "Download=20
Amendment 1"</FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DArial=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DArial size=3D2>Mel=20
Parrish</FONT></SPAN></DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DArial=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D160544817-09012002><FONT face=3DTahoma =
color=3D#000080=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of </B>Dieselberg, =
Ron<BR><B>Sent:</B>=20
  Wednesday, January 09, 2002 7:17 AM<BR><B>To:</B>=20
  [log in to unmask]<BR><B>Subject:</B> Re: [TN] Lead=20
  Length/Protrusion<BR><BR></FONT></DIV>
  <P><FONT face=3DArial size=3D2>How do you find it and download it? I =
went in=20
  circles.</FONT> </P>
  <P><FONT face=3D"Courier New" size=3D2>Ron Dieselberg</FONT> <BR><FONT =

  face=3D"Courier New" size=3D2>Trainer/Auditor</FONT> <BR><FONT =
face=3D"Courier New"=20
  size=3D2>CMC ELECTRONICS</FONT> <BR><FONT face=3D"Courier New"=20
  size=3D2>CINCINNATI</FONT> <BR><FONT face=3D"Courier New"=20
  size=3D2>[log in to unmask]</FONT> </P>
  <UL>
    <UL>
      <P><A name=3D_MailData><FONT face=3DArial size=3D2>-----Original=20
      Message-----</FONT></A> <BR><B><FONT face=3DArial =
size=3D2>From:&nbsp;&nbsp;=20
      Mel Parrish [<A=20
      =
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
COM</A>]</FONT></B>=20
      <BR><B><FONT face=3DArial size=3D2>Sent:&nbsp;&nbsp;</FONT></B> =
<FONT=20
      face=3DArial size=3D2>Wednesday, January 09, 2002 11:37 AM</FONT> =
<BR><B><FONT=20
      face=3DArial size=3D2>To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT =
face=3DArial=20
      size=3D2>[log in to unmask]</FONT> <BR><B><FONT face=3DArial=20
      =
size=3D2>Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> =
<FONT=20
      face=3DArial size=3D2>Re: [TN] Lead Length/Protrusion</FONT> </P>
      <P><FONT face=3DArial size=3D2>The URL for 610C, Amendment 1 is <A =

      href=3D"http://www.ipc.org/html/fsresources.htm"=20
      target=3D_blank>http://www.ipc.org/html/fsresources.htm</A></FONT> =
<BR><FONT=20
      face=3DArial size=3D2>"IPC Documents Available for =
Download"</FONT> <BR><FONT=20
      face=3DArial size=3D2>IPC-A-610C, Amendment 1, November =
2001.</FONT> <BR><FONT=20
      face=3DArial size=3D2>Mel</FONT> </P>
      <P><FONT face=3DArial size=3D2>Mel Parrish</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>Soldering Technology International</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>Madison, AL</FONT> <BR><FONT face=3DArial size=3D2>256 =
705 5530</FONT>=20
      <BR><FONT face=3DArial size=3D2>256 705 5538 Fax</FONT> <BR><FONT =
face=3DArial=20
      size=3D2>[log in to unmask]</FONT> </P><BR><BR>
      <P><FONT face=3DArial size=3D2>-----Original Message-----</FONT> =
<BR><FONT=20
      face=3DArial size=3D2>From: TechNet [<A=20
      href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]On =
Behalf Of=20
      Olivia Mc Dermott</FONT> <BR><FONT face=3DArial size=3D2>Sent: =
Wednesday,=20
      January 09, 2002 5:41 AM</FONT> <BR><FONT face=3DArial =
size=3D2>To:=20
      [log in to unmask]</FONT> <BR><FONT face=3DArial size=3D2>Subject: =
[TN] Lead=20
      Length/Protrusion</FONT> </P><BR>
      <P><FONT face=3DArial size=3D2>Hi ALl,</FONT> <BR><FONT =
face=3DArial size=3D2>Why=20
      are there 2 references to lead length/protrusion in IPC-A-610C. =
In</FONT>=20
      <BR><FONT face=3DArial size=3D2>'Component Installation =
Location/Orientation'=20
      - point 5.2.7.1 table 5.2 lead</FONT> <BR><FONT face=3DArial=20
      size=3D2>protrusion for class 2 is 2.5mm but in 'Soldering' point =
6.2 table=20
      6.1 lead</FONT> <BR><FONT face=3DArial size=3D2>protrusion for =
class 2 is=20
      2.3mm. Which one do we use?</FONT> </P>
      <P><FONT face=3DArial=20
      =
size=3D2>________________________________________________________________=
_</FONT>=20
      <BR><FONT face=3DArial size=3D2>MSN Photos is the easiest way to =
share and=20
      print your photos:</FONT> <BR><FONT face=3DArial size=3D2><A=20
      href=3D"http://photos.msn.com/support/worldwide.aspx"=20
      =
target=3D_blank>http://photos.msn.com/support/worldwide.aspx</A></FONT> =
</P>
      <P><FONT face=3DArial=20
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Date:         Wed, 9 Jan 2002 07:45:44 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
Content-Type: text/plain

Take the link to the "on line resources" page on the IPC web site, scroll
down to the bottom of the page and click on "IPC documents available for
download"  You'll find it there.
I'm curious why tables 12-9, 12-10 and 12-11 are obscured in the amendment.
The first two show some kind of change.

> -----Original Message-----
> From: Dieselberg, Ron [SMTP:[log in to unmask]]
> Sent: Wednesday, January 09, 2002 7:17 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Lead Length/Protrusion
>
> How do you find it and download it? I went in circles.
>
> Ron Dieselberg
> Trainer/Auditor
> CMC ELECTRONICS
> CINCINNATI
> [log in to unmask]
>
>       -----Original Message-----
>       From:   Mel Parrish [ <mailto:[log in to unmask]>]
>       Sent:   Wednesday, January 09, 2002 11:37 AM
>       To:     [log in to unmask]
>       Subject:        Re: [TN] Lead Length/Protrusion
>
>       The URL for 610C, Amendment 1 is
> <http://www.ipc.org/html/fsresources.htm>
>       "IPC Documents Available for Download"
>       IPC-A-610C, Amendment 1, November 2001.
>       Mel
>
>       Mel Parrish
>       Soldering Technology International
>       Madison, AL
>       256 705 5530
>       256 705 5538 Fax
>       [log in to unmask]
>
>
>
>       -----Original Message-----
>       From: TechNet [ <mailto:[log in to unmask]>]On Behalf Of Olivia Mc
> Dermott
>       Sent: Wednesday, January 09, 2002 5:41 AM
>       To: [log in to unmask]
>       Subject: [TN] Lead Length/Protrusion
>
>
>       Hi ALl,
>       Why are there 2 references to lead length/protrusion in IPC-A-610C.
> In
>       'Component Installation Location/Orientation' - point 5.2.7.1 table
> 5.2 lead
>       protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table
> 6.1 lead
>       protrusion for class 2 is 2.3mm. Which one do we use?
>
>       _________________________________________________________________
>       MSN Photos is the easiest way to share and print your photos:
>       <http://photos.msn.com/support/worldwide.aspx>
>
>
> --------------------------------------------------------------------------
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Date:         Wed, 9 Jan 2002 15:41:40 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Peter Swanson <[log in to unmask]>
Subject:      Re: Staking compounds
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Doug,

I wrote a review of the wire tacking process, which might assist you in your
research - http://www.intertronics.co.uk/articles/tb003.htm. Component
staking has slightly different requirements - a large blob underneath a
component may raise further CTE related questions.

Regards,
Peter
--
=========================================================
Peter Swanson            [log in to unmask]
INTERTRONICS                http://www.intertronics.co.uk

INTERTRONICS is dedicated to providing quality material,
  consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
   the highest levels of technical support and customer
                         service.


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: 07 January 2002 19:41
To: [log in to unmask]
Subject: [TN] Staking compounds


Good day all,

I am curious as to what all y'all use for staking compounds (to fix wires
or components in place) on your assemblies, especially if you are in the
high-rel area or aerospace sector.  Thanks.

Doug Pauls
Rockwell Collins

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Date:         Wed, 9 Jan 2002 12:24:39 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
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Thanks Guys, I found it.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Thorup, John [mailto:[log in to unmask]]
                Sent:   Wednesday, January 09, 2002 10:46 AM
                To:     [log in to unmask]
                Subject:        Re: [TN] Lead Length/Protrusion

                Take the link to the "on line resources" page on the IPC web
site, scroll
                down to the bottom of the page and click on "IPC documents
available for
                download"  You'll find it there.
                I'm curious why tables 12-9, 12-10 and 12-11 are obscured in
the amendment.
                The first two show some kind of change.

                > -----Original Message-----
                > From: Dieselberg, Ron [SMTP:[log in to unmask]]
                > Sent: Wednesday, January 09, 2002 7:17 AM
                > To:   [log in to unmask]
                > Subject:      Re: [TN] Lead Length/Protrusion
                >
                > How do you find it and download it? I went in circles.
                >
                > Ron Dieselberg
                > Trainer/Auditor
                > CMC ELECTRONICS
                > CINCINNATI
                > [log in to unmask]
                >
                >       -----Original Message-----
                >       From:   Mel Parrish [
<mailto:[log in to unmask]>]
                >       Sent:   Wednesday, January 09, 2002 11:37 AM
                >       To:     [log in to unmask]
                >       Subject:        Re: [TN] Lead Length/Protrusion
                >
                >       The URL for 610C, Amendment 1 is
                > <http://www.ipc.org/html/fsresources.htm>
                >       "IPC Documents Available for Download"
                >       IPC-A-610C, Amendment 1, November 2001.
                >       Mel
                >
                >       Mel Parrish
                >       Soldering Technology International
                >       Madison, AL
                >       256 705 5530
                >       256 705 5538 Fax
                >       [log in to unmask]
                >
                >
                >
                >       -----Original Message-----
                >       From: TechNet [ <mailto:[log in to unmask]>]On Behalf
Of Olivia Mc
                > Dermott
                >       Sent: Wednesday, January 09, 2002 5:41 AM
                >       To: [log in to unmask]
                >       Subject: [TN] Lead Length/Protrusion
                >
                >
                >       Hi ALl,
                >       Why are there 2 references to lead length/protrusion
in IPC-A-610C.
                > In
                >       'Component Installation Location/Orientation' -
point 5.2.7.1 table
                > 5.2 lead
                >       protrusion for class 2 is 2.5mm but in 'Soldering'
point 6.2 table
                > 6.1 lead
                >       protrusion for class 2 is 2.3mm. Which one do we
use?
                >
                >
_________________________________________________________________
                >       MSN Photos is the easiest way to share and print
your photos:
                >       <http://photos.msn.com/support/worldwide.aspx>
                >
                >
                >
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------_=_NextPart_001_01C19932.84924EC0
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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2652.35">
<TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks Guys, I found it.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Thorup, John [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT></=
B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Wednesday, January 09, 2002 10:46 AM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">Re: [TN] Lead =
Length/Protrusion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Take the link to the &quot;on line =
resources&quot; page on the IPC web site, scroll</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">down to the bottom of the page and =
click on &quot;IPC documents available for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">download&quot;&nbsp; You'll find it =
there.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">I'm curious why tables 12-9, 12-10 =
and 12-11 are obscured in the amendment.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">The first two show some kind of =
change.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; From: Dieselberg, Ron =
[SMTP:[log in to unmask]]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Sent: Wednesday, January 09, =
2002 7:17 AM</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; To:&nbsp;&nbsp; =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; =
Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Lead =
Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; How do you find it and download =
it? I went in circles.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; [log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -----Original =
Message-----</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
From:&nbsp;&nbsp; Mel Parrish [ &lt;<A =
HREF=3D"mailto:[log in to unmask]">mailto:mparrish@SOLDERINGTECH=
.COM</A>&gt;]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Sent:&nbsp;&nbsp; Wednesday, January 09, 2002 11:37 AM</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
To:&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Lead =
Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The URL for =
610C, Amendment 1 is</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; &lt;<A =
HREF=3D"http://www.ipc.org/html/fsresources.htm" =
TARGET=3D"_blank">http://www.ipc.org/html/fsresources.htm</A>&gt;</FONT>=

<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &quot;IPC =
Documents Available for Download&quot;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IPC-A-610C, =
Amendment 1, November 2001.</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mel</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mel =
Parrish</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Soldering =
Technology International</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Madison, =
AL</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705 =
5530</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705 5538 =
Fax</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -----Original =
Message-----</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; From: TechNet [ =
&lt;<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>&gt;]On =
Behalf Of Olivia Mc</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Dermott</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent: =
Wednesday, January 09, 2002 5:41 AM</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To: =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject: [TN] =
Lead Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hi ALl,</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Why are there 2 =
references to lead length/protrusion in IPC-A-610C.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; In</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 'Component =
Installation Location/Orientation' - point 5.2.7.1 table</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; 5.2 lead</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; protrusion for =
class 2 is 2.5mm but in 'Soldering' point 6.2 table</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; 6.1 lead</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; protrusion for =
class 2 is 2.3mm. Which one do we use?</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
_________________________________________________________________</FONT>=

<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSN Photos is =
the easiest way to share and print your photos:</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;<A =
HREF=3D"http://photos.msn.com/support/worldwide.aspx" =
TARGET=3D"_blank">http://photos.msn.com/support/worldwide.aspx</A>&gt;</=
FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; =
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--</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; --</FONT>
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Date:         Wed, 9 Jan 2002 12:34:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
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John, I just ran a copy of the amendment and it did not show the tables
obscured as you indicated.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Thorup, John [mailto:[log in to unmask]]
                Sent:   Wednesday, January 09, 2002 10:46 AM
                To:     [log in to unmask]
                Subject:        Re: [TN] Lead Length/Protrusion

                Take the link to the "on line resources" page on the IPC web
site, scroll
                down to the bottom of the page and click on "IPC documents
available for
                download"  You'll find it there.
                I'm curious why tables 12-9, 12-10 and 12-11 are obscured in
the amendment.
                The first two show some kind of change.

                > -----Original Message-----
                > From: Dieselberg, Ron [SMTP:[log in to unmask]]
                > Sent: Wednesday, January 09, 2002 7:17 AM
                > To:   [log in to unmask]
                > Subject:      Re: [TN] Lead Length/Protrusion
                >
                > How do you find it and download it? I went in circles.
                >
                > Ron Dieselberg
                > Trainer/Auditor
                > CMC ELECTRONICS
                > CINCINNATI
                > [log in to unmask]
                >
                >       -----Original Message-----
                >       From:   Mel Parrish [
<mailto:[log in to unmask]>]
                >       Sent:   Wednesday, January 09, 2002 11:37 AM
                >       To:     [log in to unmask]
                >       Subject:        Re: [TN] Lead Length/Protrusion
                >
                >       The URL for 610C, Amendment 1 is
                > <http://www.ipc.org/html/fsresources.htm>
                >       "IPC Documents Available for Download"
                >       IPC-A-610C, Amendment 1, November 2001.
                >       Mel
                >
                >       Mel Parrish
                >       Soldering Technology International
                >       Madison, AL
                >       256 705 5530
                >       256 705 5538 Fax
                >       [log in to unmask]
                >
                >
                >
                >       -----Original Message-----
                >       From: TechNet [ <mailto:[log in to unmask]>]On Behalf
Of Olivia Mc
                > Dermott
                >       Sent: Wednesday, January 09, 2002 5:41 AM
                >       To: [log in to unmask]
                >       Subject: [TN] Lead Length/Protrusion
                >
                >
                >       Hi ALl,
                >       Why are there 2 references to lead length/protrusion
in IPC-A-610C.
                > In
                >       'Component Installation Location/Orientation' -
point 5.2.7.1 table
                > 5.2 lead
                >       protrusion for class 2 is 2.5mm but in 'Soldering'
point 6.2 table
                > 6.1 lead
                >       protrusion for class 2 is 2.3mm. Which one do we
use?
                >
                >
_________________________________________________________________
                >       MSN Photos is the easiest way to share and print
your photos:
                >       <http://photos.msn.com/support/worldwide.aspx>
                >
                >
                >
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                > additional
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charset=3Diso-8859-1">
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5.5.2652.35">
<TITLE>RE: [TN] Lead Length/Protrusion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">John, I just ran a copy of the =
amendment and it did not show the tables obscured as you =
indicated.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Thorup, John [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT></=
B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Wednesday, January 09, 2002 10:46 AM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">Re: [TN] Lead =
Length/Protrusion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Take the link to the &quot;on line =
resources&quot; page on the IPC web site, scroll</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">down to the bottom of the page and =
click on &quot;IPC documents available for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">download&quot;&nbsp; You'll find it =
there.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">I'm curious why tables 12-9, 12-10 =
and 12-11 are obscured in the amendment.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">The first two show some kind of =
change.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; From: Dieselberg, Ron =
[SMTP:[log in to unmask]]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Sent: Wednesday, January 09, =
2002 7:17 AM</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; To:&nbsp;&nbsp; =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; =
Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Lead =
Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; How do you find it and download =
it? I went in circles.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; [log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -----Original =
Message-----</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
From:&nbsp;&nbsp; Mel Parrish [ &lt;<A =
HREF=3D"mailto:[log in to unmask]">mailto:mparrish@SOLDERINGTECH=
.COM</A>&gt;]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Sent:&nbsp;&nbsp; Wednesday, January 09, 2002 11:37 AM</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
To:&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Lead =
Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The URL for =
610C, Amendment 1 is</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; &lt;<A =
HREF=3D"http://www.ipc.org/html/fsresources.htm" =
TARGET=3D"_blank">http://www.ipc.org/html/fsresources.htm</A>&gt;</FONT>=

<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &quot;IPC =
Documents Available for Download&quot;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; IPC-A-610C, =
Amendment 1, November 2001.</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mel</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mel =
Parrish</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Soldering =
Technology International</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Madison, =
AL</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705 =
5530</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705 5538 =
Fax</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -----Original =
Message-----</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; From: TechNet [ =
&lt;<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>&gt;]On =
Behalf Of Olivia Mc</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; Dermott</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent: =
Wednesday, January 09, 2002 5:41 AM</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To: =
[log in to unmask]</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject: [TN] =
Lead Length/Protrusion</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hi ALl,</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Why are there 2 =
references to lead length/protrusion in IPC-A-610C.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; In</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 'Component =
Installation Location/Orientation' - point 5.2.7.1 table</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; 5.2 lead</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; protrusion for =
class 2 is 2.5mm but in 'Soldering' point 6.2 table</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; 6.1 lead</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; protrusion for =
class 2 is 2.3mm. Which one do we use?</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
_________________________________________________________________</FONT>=

<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSN Photos is =
the easiest way to share and print your photos:</FONT>
<BR><FONT SIZE=3D2 =
FACE=3D"Arial">&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;<A =
HREF=3D"http://photos.msn.com/support/worldwide.aspx" =
TARGET=3D"_blank">http://photos.msn.com/support/worldwide.aspx</A>&gt;</=
FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; =
------------------------------------------------------------------------=
--</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&gt; --</FONT>
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Date:         Wed, 9 Jan 2002 13:25:18 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <1BB7006CDCB0D3118F0300104B68201080E594@PROORBANX1>
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John
Do you have the big black dot scourge? Not serious.
I usually find that to be a printer (memory?) capacity issue. Sometimes you
can get past it by printing the single page and reassembling.
Mel P

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Thorup, John
Sent: Wednesday, January 09, 2002 7:46 AM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Take the link to the "on line resources" page on the IPC web site, scroll
down to the bottom of the page and click on "IPC documents available for
download"  You'll find it there.
I'm curious why tables 12-9, 12-10 and 12-11 are obscured in the amendment.
The first two show some kind of change.

> -----Original Message-----
> From: Dieselberg, Ron [SMTP:[log in to unmask]]
> Sent: Wednesday, January 09, 2002 7:17 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Lead Length/Protrusion
>
> How do you find it and download it? I went in circles.
>
> Ron Dieselberg
> Trainer/Auditor
> CMC ELECTRONICS
> CINCINNATI
> [log in to unmask]
>
>       -----Original Message-----
>       From:   Mel Parrish [ <mailto:[log in to unmask]>]
>       Sent:   Wednesday, January 09, 2002 11:37 AM
>       To:     [log in to unmask]
>       Subject:        Re: [TN] Lead Length/Protrusion
>
>       The URL for 610C, Amendment 1 is
> <http://www.ipc.org/html/fsresources.htm>
>       "IPC Documents Available for Download"
>       IPC-A-610C, Amendment 1, November 2001.
>       Mel
>
>       Mel Parrish
>       Soldering Technology International
>       Madison, AL
>       256 705 5530
>       256 705 5538 Fax
>       [log in to unmask]
>
>
>
>       -----Original Message-----
>       From: TechNet [ <mailto:[log in to unmask]>]On Behalf Of Olivia Mc
> Dermott
>       Sent: Wednesday, January 09, 2002 5:41 AM
>       To: [log in to unmask]
>       Subject: [TN] Lead Length/Protrusion
>
>
>       Hi ALl,
>       Why are there 2 references to lead length/protrusion in IPC-A-610C.
> In
>       'Component Installation Location/Orientation' - point 5.2.7.1 table
> 5.2 lead
>       protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table
> 6.1 lead
>       protrusion for class 2 is 2.3mm. Which one do we use?
>
>       _________________________________________________________________
>       MSN Photos is the easiest way to share and print your photos:
>       <http://photos.msn.com/support/worldwide.aspx>
>
>
> --------------------------------------------------------------------------
> --
>       -----
>       Technet Mail List provided as a free service by IPC using LISTSERV
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> text in
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>
>
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Date:         Wed, 9 Jan 2002 15:14:26 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Green Slime on QFP lead toes...
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_18e.18f59c8.296dfea2_boundary"

--part1_18e.18f59c8.296dfea2_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hey All!

I gotta weird one here. I was inspecting some Analog Devices QFP's today
(ADSP--21062's) to check if there were any coplanarity problems of the
devices in the trays as they came in from the manufacturer..

I used a vacuum pen to take one out of the tray so I could hold it on edge to
look down the row of leads figuring I would be able to spot a lead out of
plane easier that way. But I noticed something on the toes of the leads that
I have never seen before,
check out "Green Slime" on my web page:

http://www.stevezeva.homestead.com

It looks like some sort of green jelly or grease on the toes of the
leads...and it's only on two quadrants of the QFP, the other two quadrants
don't have this.

Anybody ever see this? I'm gonna send it out for analysis, but I was
wondering if anybody has ever seen this stuff before. There was a suggestion
here that it could be some sort of flux residues, but I don't think so,
because to me it looks like the lead finish is electroplated, so there
shouldn't be flux around this part at all until board assembly...these parts
were fresh out of the OEM packaging.

The part is a 240-pin, 19.7-pitch MQFP with a heat slug in the top.

Thanks All!!

-Steve Gregory-

--part1_18e.18f59c8.296dfea2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hey All!
<BR>
<BR>I gotta weird one here. I was inspecting some Analog Devices QFP's today (ADSP--21062's) to check if there were any coplanarity problems of the devices in the trays as they came in from the manufacturer..
<BR>
<BR>I used a vacuum pen to take one out of the tray so I could hold it on edge to look down the row of leads figuring I would be able to spot a lead out of plane easier that way. But I noticed something on the toes of the leads that I have never seen before,
<BR>check out "Green Slime" on my web page:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>It looks like some sort of green jelly or grease on the toes of the leads...and it's only on two quadrants of the QFP, the other two quadrants don't have this.
<BR>
<BR>Anybody ever see this? I'm gonna send it out for analysis, but I was wondering if anybody has ever seen this stuff before. There was a suggestion here that it could be some sort of flux residues, but I don't think so, because to me it looks like the lead finish is electroplated, so there shouldn't be flux around this part at all until board assembly...these parts were fresh out of the OEM packaging.
<BR>
<BR>The part is a 240-pin, 19.7-pitch MQFP with a heat slug in the top.
<BR>
<BR>Thanks All!!
<BR>
<BR>-Steve Gregory-</FONT></HTML>

--part1_18e.18f59c8.296dfea2_boundary--

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Date:         Wed, 9 Jan 2002 12:15:40 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello Mel
Who told you about my personal problems?
Actually when I send a single page to the HP it comes out the same.  Sent it
to a different printer (with much less memory) and the tables came out fine.
Seems the HP driver is interpreting any vertical lines except the border as
a circle with the diameter being the height of the table.  Other locally
created tables print perfectly.  As they say, to err is human but to really
@#$% it up takes a computer.  Go figure!

> -----Original Message-----
> From: Mel Parrish [SMTP:[log in to unmask]]
> Sent: Wednesday, January 09, 2002 1:25 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Lead Length/Protrusion
>
> John
> Do you have the big black dot scourge? Not serious.
> I usually find that to be a printer (memory?) capacity issue. Sometimes
> you
> can get past it by printing the single page and reassembling.
> Mel P
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Thorup, John
> Sent: Wednesday, January 09, 2002 7:46 AM
> To: [log in to unmask]
> Subject: Re: [TN] Lead Length/Protrusion
>
>
> Take the link to the "on line resources" page on the IPC web site, scroll
> down to the bottom of the page and click on "IPC documents available for
> download"  You'll find it there.
> I'm curious why tables 12-9, 12-10 and 12-11 are obscured in the
> amendment.
> The first two show some kind of change.
>
> > -----Original Message-----
> > From: Dieselberg, Ron [SMTP:[log in to unmask]]
> > Sent: Wednesday, January 09, 2002 7:17 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] Lead Length/Protrusion
> >
> > How do you find it and download it? I went in circles.
> >
> > Ron Dieselberg
> > Trainer/Auditor
> > CMC ELECTRONICS
> > CINCINNATI
> > [log in to unmask]
> >
> >       -----Original Message-----
> >       From:   Mel Parrish [ <mailto:[log in to unmask]>]
> >       Sent:   Wednesday, January 09, 2002 11:37 AM
> >       To:     [log in to unmask]
> >       Subject:        Re: [TN] Lead Length/Protrusion
> >
> >       The URL for 610C, Amendment 1 is
> > <http://www.ipc.org/html/fsresources.htm>
> >       "IPC Documents Available for Download"
> >       IPC-A-610C, Amendment 1, November 2001.
> >       Mel
> >
> >       Mel Parrish
> >       Soldering Technology International
> >       Madison, AL
> >       256 705 5530
> >       256 705 5538 Fax
> >       [log in to unmask]
> >
> >
> >
> >       -----Original Message-----
> >       From: TechNet [ <mailto:[log in to unmask]>]On Behalf Of Olivia Mc
> > Dermott
> >       Sent: Wednesday, January 09, 2002 5:41 AM
> >       To: [log in to unmask]
> >       Subject: [TN] Lead Length/Protrusion
> >
> >
> >       Hi ALl,
> >       Why are there 2 references to lead length/protrusion in
> IPC-A-610C.
> > In
> >       'Component Installation Location/Orientation' - point 5.2.7.1
> table
> > 5.2 lead
> >       protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table
> > 6.1 lead
> >       protrusion for class 2 is 2.3mm. Which one do we use?
> >
> >       _________________________________________________________________
> >       MSN Photos is the easiest way to share and print your photos:
> >       <http://photos.msn.com/support/worldwide.aspx>
> >
> >
> >
> --------------------------------------------------------------------------
> > --
> >       -----
> >       Technet Mail List provided as a free service by IPC using LISTSERV
> > 1.8d
> >       To unsubscribe, send a message to [log in to unmask] with following
> > text in
> >       the BODY (NOT the subject field): SIGNOFF Technet
> >       To temporarily halt delivery of Technet send e-mail to
> > [log in to unmask]: SET
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> > Databases >
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> >       Please visit IPC web site ( <http://www.ipc.org/html/forum.htm>)
> for
> > additional
> >       information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700
> >       ext.5315
> >
> >
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> for
> > additional
> >       information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> >
> >
> --------------------------------------------------------------------------
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> >
>
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Date:         Wed, 9 Jan 2002 14:31:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Possibly your version of Acrobat is old - I have sometimes seen the big dot
phenomenon in that case.   try updating your reader.

-----Original Message-----
From: Thorup, John [mailto:[log in to unmask]]
Sent: January 9, 2002 2:16 PM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Hello Mel
Who told you about my personal problems?
Actually when I send a single page to the HP it comes out the same.  Sent it
to a different printer (with much less memory) and the tables came out fine.
Seems the HP driver is interpreting any vertical lines except the border as
a circle with the diameter being the height of the table.  Other locally
created tables print perfectly.  As they say, to err is human but to really
@#$% it up takes a computer.  Go figure!

> -----Original Message-----
> From: Mel Parrish [SMTP:[log in to unmask]]
> Sent: Wednesday, January 09, 2002 1:25 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Lead Length/Protrusion
>
> John
> Do you have the big black dot scourge? Not serious.
> I usually find that to be a printer (memory?) capacity issue. Sometimes
> you
> can get past it by printing the single page and reassembling.
> Mel P
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Thorup, John
> Sent: Wednesday, January 09, 2002 7:46 AM
> To: [log in to unmask]
> Subject: Re: [TN] Lead Length/Protrusion
>
>
> Take the link to the "on line resources" page on the IPC web site, scroll
> down to the bottom of the page and click on "IPC documents available for
> download"  You'll find it there.
> I'm curious why tables 12-9, 12-10 and 12-11 are obscured in the
> amendment.
> The first two show some kind of change.
>
> > -----Original Message-----
> > From: Dieselberg, Ron [SMTP:[log in to unmask]]
> > Sent: Wednesday, January 09, 2002 7:17 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] Lead Length/Protrusion
> >
> > How do you find it and download it? I went in circles.
> >
> > Ron Dieselberg
> > Trainer/Auditor
> > CMC ELECTRONICS
> > CINCINNATI
> > [log in to unmask]
> >
> >       -----Original Message-----
> >       From:   Mel Parrish [ <mailto:[log in to unmask]>]
> >       Sent:   Wednesday, January 09, 2002 11:37 AM
> >       To:     [log in to unmask]
> >       Subject:        Re: [TN] Lead Length/Protrusion
> >
> >       The URL for 610C, Amendment 1 is
> > <http://www.ipc.org/html/fsresources.htm>
> >       "IPC Documents Available for Download"
> >       IPC-A-610C, Amendment 1, November 2001.
> >       Mel
> >
> >       Mel Parrish
> >       Soldering Technology International
> >       Madison, AL
> >       256 705 5530
> >       256 705 5538 Fax
> >       [log in to unmask]
> >
> >
> >
> >       -----Original Message-----
> >       From: TechNet [ <mailto:[log in to unmask]>]On Behalf Of Olivia Mc
> > Dermott
> >       Sent: Wednesday, January 09, 2002 5:41 AM
> >       To: [log in to unmask]
> >       Subject: [TN] Lead Length/Protrusion
> >
> >
> >       Hi ALl,
> >       Why are there 2 references to lead length/protrusion in
> IPC-A-610C.
> > In
> >       'Component Installation Location/Orientation' - point 5.2.7.1
> table
> > 5.2 lead
> >       protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table
> > 6.1 lead
> >       protrusion for class 2 is 2.3mm. Which one do we use?
> >
> >       _________________________________________________________________
> >       MSN Photos is the easiest way to share and print your photos:
> >       <http://photos.msn.com/support/worldwide.aspx>
> >
> >
> >
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Date:         Wed, 9 Jan 2002 16:08:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Green Slime on QFP lead toes...
MIME-Version: 1.0
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Steve,
It looks like the ends of the leads were cut and not plated over.  I would
guess that the green material is either copper chloride or copper abietate
where the exposed copper of the lead is attacked.  Check to see if the ends
are cut or plated over on the two sides that don't have the green material.

Doug Pauls

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Date:         Wed, 9 Jan 2002 17:23:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: Green Slime on QFP lead toes...
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Steve,
You say it looks like green slime.  But does it feel like green slime?  What
I mean is it soft and moveable like Vaseline, flux residue, etc, or is it
rock hard?  I wish the image of the stuff was at a higher mag.  Have you
found out for sure whether these leads or electroplated or not?  And if they
are electroplated did it (electroplating) happen before or after the lead
toes were clipped?  And is it only one device or all of them in the tray?
regards,
Bev Christian
Research in Motion

-----Original Message-----
From: Stephen Gregory [mailto:[log in to unmask]]
Sent: January 9, 2002 3:14 PM
To: [log in to unmask]
Subject: [TN] Green Slime on QFP lead toes...


Hey All!

I gotta weird one here. I was inspecting some Analog Devices QFP's today
(ADSP--21062's) to check if there were any coplanarity problems of the
devices in the trays as they came in from the manufacturer..

I used a vacuum pen to take one out of the tray so I could hold it on edge
to look down the row of leads figuring I would be able to spot a lead out of
plane easier that way. But I noticed something on the toes of the leads that
I have never seen before,
check out "Green Slime" on my web page:

http://www.stevezeva.homestead.com

It looks like some sort of green jelly or grease on the toes of the
leads...and it's only on two quadrants of the QFP, the other two quadrants
don't have this.

Anybody ever see this? I'm gonna send it out for analysis, but I was
wondering if anybody has ever seen this stuff before. There was a suggestion
here that it could be some sort of flux residues, but I don't think so,
because to me it looks like the lead finish is electroplated, so there
shouldn't be flux around this part at all until board assembly...these parts
were fresh out of the OEM packaging.

The part is a 240-pin, 19.7-pitch MQFP with a heat slug in the top.

Thanks All!!

-Steve Gregory-


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Content-Type: text/html;
        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 5.50.4207.2601" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=987241822-09012002><FONT face=Arial color=#0000ff
size=2>Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=987241822-09012002><FONT face=Arial color=#0000ff size=2>You
say it looks like green slime.&nbsp; But does it feel like green slime?&nbsp;
What I mean is it soft and moveable like Vaseline, flux residue, etc, or is it
rock hard?&nbsp; I wish the image of the stuff was at a higher mag.&nbsp; Have
you found out for sure whether these leads or electroplated or not?&nbsp; And if
they are electroplated did it (electroplating) happen before or after the lead
toes were clipped?&nbsp; And is it only one device or all of them in the
tray?</FONT></SPAN></DIV>
<DIV><SPAN class=987241822-09012002><FONT face=Arial color=#0000ff
size=2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=987241822-09012002><FONT face=Arial color=#0000ff size=2>Bev
Christian</FONT></SPAN></DIV>
<DIV><SPAN class=987241822-09012002><FONT face=Arial color=#0000ff
size=2>Research in Motion</FONT></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Stephen Gregory
  [mailto:[log in to unmask]]<BR><B>Sent:</B> January 9, 2002 3:14
  PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Green Slime on QFP
  lead toes...<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hey
  All! <BR><BR>I gotta weird one here. I was inspecting some Analog Devices
  QFP's today (ADSP--21062's) to check if there were any coplanarity problems of
  the devices in the trays as they came in from the manufacturer.. <BR><BR>I
  used a vacuum pen to take one out of the tray so I could hold it on edge to
  look down the row of leads figuring I would be able to spot a lead out of
  plane easier that way. But I noticed something on the toes of the leads that I
  have never seen before, <BR>check out "Green Slime" on my web page:
  <BR><BR>http://www.stevezeva.homestead.com <BR><BR>It looks like some sort of
  green jelly or grease on the toes of the leads...and it's only on two
  quadrants of the QFP, the other two quadrants don't have this. <BR><BR>Anybody
  ever see this? I'm gonna send it out for analysis, but I was wondering if
  anybody has ever seen this stuff before. There was a suggestion here that it
  could be some sort of flux residues, but I don't think so, because to me it
  looks like the lead finish is electroplated, so there shouldn't be flux around
  this part at all until board assembly...these parts were fresh out of the OEM
  packaging. <BR><BR>The part is a 240-pin, 19.7-pitch MQFP with a heat slug in
  the top. <BR><BR>Thanks All!! <BR><BR>-Steve Gregory-</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C1995C.41E0D860--

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Date:         Wed, 9 Jan 2002 17:27:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Green Slime on QFP lead toes...
MIME-Version: 1.0
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              boundary="part1_11f.9d61ddc.296e1dcf_boundary"

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Hi Doug!

The ends of the leads aren't plated over. They were cut in a burr-up fashion.
So there is smeared plating over the toes from the bottom of the foot up
about three quarters of the thickness of the lead...if you closely, you can
see the silver color of the tin plating through the green glop...

This stuff almost looks like some sort of grease or something that was on the
die or anvil when they did form and trim...weirdest stuff I ever saw.

-Steve Gregory-

> Steve,
> It looks like the ends of the leads were cut and not plated over.  I would
> guess that the green material is either copper chloride or copper abietate
> where the exposed copper of the lead is attacked.  Check to see if the ends
> are cut or plated over on the two sides that don't have the green material.
>
> Doug Pauls
>



--part1_11f.9d61ddc.296e1dcf_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Doug!
<BR>
<BR>The ends of the leads aren't plated over. They were cut in a burr-up fashion. So there is smeared plating over the toes from the bottom of the foot up about three quarters of the thickness of the lead...if you closely, you can see the silver color of the tin plating through the green glop...
<BR>
<BR>This stuff almost looks like some sort of grease or something that was on the die or anvil when they did form and trim...weirdest stuff I ever saw.
<BR>
<BR>-Steve Gregory-
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve,
<BR>It looks like the ends of the leads were cut and not plated over. &nbsp;I would
<BR>guess that the green material is either copper chloride or copper abietate
<BR>where the exposed copper of the lead is attacked. &nbsp;Check to see if the ends
<BR>are cut or plated over on the two sides that don't have the green material.
<BR>
<BR>Doug Pauls
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_11f.9d61ddc.296e1dcf_boundary--

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Date:         Wed, 9 Jan 2002 17:49:47 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: Green Slime on QFP lead toes...
MIME-Version: 1.0
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Steve,
Sounds like it is time for FTIR...

regards,
Bev

-----Original Message-----
From: Stephen Gregory [mailto:[log in to unmask]]
Sent: January 9, 2002 5:27 PM
To: [log in to unmask]
Subject: Re: [TN] Green Slime on QFP lead toes...


Hi Doug!

The ends of the leads aren't plated over. They were cut in a burr-up
fashion. So there is smeared plating over the toes from the bottom of the
foot up about three quarters of the thickness of the lead...if you closely,
you can see the silver color of the tin plating through the green glop...

This stuff almost looks like some sort of grease or something that was on
the die or anvil when they did form and trim...weirdest stuff I ever saw.

-Steve Gregory-



Steve,
It looks like the ends of the leads were cut and not plated over.  I would
guess that the green material is either copper chloride or copper abietate
where the exposed copper of the lead is attacked.  Check to see if the ends
are cut or plated over on the two sides that don't have the green material.

Doug Pauls







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        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 5.50.4207.2601" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=996064922-09012002><FONT face=Arial color=#0000ff
size=2>Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=996064922-09012002><FONT face=Arial color=#0000ff size=2>Sounds
like it is time for FTIR...</FONT></SPAN></DIV>
<DIV><SPAN class=996064922-09012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=996064922-09012002><FONT face=Arial color=#0000ff
size=2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=996064922-09012002><FONT face=Arial color=#0000ff
size=2>Bev</FONT></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Stephen Gregory
  [mailto:[log in to unmask]]<BR><B>Sent:</B> January 9, 2002 5:27
  PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Green Slime on
  QFP lead toes...<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT
  size=2>Hi Doug! <BR><BR>The ends of the leads aren't plated over. They were
  cut in a burr-up fashion. So there is smeared plating over the toes from the
  bottom of the foot up about three quarters of the thickness of the lead...if
  you closely, you can see the silver color of the tin plating through the green
  glop... <BR><BR>This stuff almost looks like some sort of grease or something
  that was on the die or anvil when they did form and trim...weirdest stuff I
  ever saw. <BR><BR>-Steve Gregory- <BR><BR>
  <BLOCKQUOTE
  style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
  TYPE="CITE">Steve, <BR>It looks like the ends of the leads were cut and not
    plated over. &nbsp;I would <BR>guess that the green material is either
    copper chloride or copper abietate <BR>where the exposed copper of the lead
    is attacked. &nbsp;Check to see if the ends <BR>are cut or plated over on
    the two sides that don't have the green material. <BR><BR>Doug Pauls
    <BR></FONT><FONT lang=0 face=Arial color=#000000 size=3
  FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0 face=Arial
  color=#000000 size=2
FAMILY="SANSSERIF"><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>

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Date:         Thu, 10 Jan 2002 08:38:58 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Mel,

I whole-heartedly second your desire to see more SMT applications detailed
in the spec, especially BGA mounting and inspection (with X-ray pictures
and how to interpret them).

Peter




                    Mel Parrish
                    <mparrish@SOLDERIN        To:     [log in to unmask]
                    GTECH.COM>                cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet          Aero/ST Group)
                    <[log in to unmask]>         Subject:     Re: [TN] Lead Length/Protrusion


                    01/10/02 12:05 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We
have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
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Date:         Thu, 10 Jan 2002 09:34:02 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Use of IPC-7095, -SM-782, and -7525
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

George,

To respond to your aside, my 2 cents worth is that the "mechanical" info on
component data sheets is very poor. Most of the content focusses on the
electrical functionality of the device, but there's precious little help
with mounting the b-----s. A few data sheets have land pattern
recommendations if you're lucky (one diode spec I came across even had
separate land pattern recommendations for both CR and Wave  solder -
exceptional! or may be there isn't enough to say about a diode otherwise to
fill a decent data sheet). BUT, there is little or nothing about
"environment/habitat" requirements for where the component is going to
live. How is it to be established in its new home, what sort of neighbours
should it have/not have, how much space it needs from said neighbours, etc.
Particularly tiresome to find at times is lead finish information - it's
available, often on a separate spec for the package, but there's no cross
reference to where this info can be found, and you can be left guessing if
it's not a "standard" package.

Some more assistance to the poor board stuffer would be welcome instead of
giving everything to our ethereal design engineers, who move on a higher
plane. Many board designs, especially aerospace applications, use a great
many components on a board, and to get all the needed information on each
to integrate them all into a working design that can be manufactured is a
herculean task. It could, I'm sure, be made a lot easier with the
co-operation of the component manufacturers, though I guess there's a fair
amount of butt protection involved - the more they say, the more they can
be held liable for. Or am I getting too cynical now?

I suggested a while ago on this forum that perhaps IPC could produce a
guideline about component specs - their format, content, minimum info
requirements for all those involved with using the component. It met with
deafening silence - probably because there is an almost infinite number of
design permutations and it would be impossible to cover all the bases with
hard facts, but better information on how to determine our own solutions
could be included, and not have the specs turn into Encyclopedia
Britannica.

End winge.

Peter




                    "Franck, George"
                    <george_h_franck@RAY        To:     [log in to unmask]
                    THEON.COM>                  cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet            Aero/ST Group)
                    <[log in to unmask]>           Subject:     Re: [TN] Use of IPC-7095, -SM-782,
                                                and -7525

                    01/09/02 10:12 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






I have been playing around, blindly, with this topic for a little while.
This is what I have learned, precious little that it is.

The answer depends on the BGA construction.  Many/most BGAs do not actually
have balls on them, they have 'bumps' of 63/37 solder.  These bumps will
completely melt during reflow, allowing the BGA to float on molten solder
during the soldering process.  For these components, you *generally* want
the pad on the board to be the same size as the pad on the component.  With
the pads being the same size, the resulting solder joint will be
symmetrical, top to bottom.  Since the writers of the Specs, (bless them
all), can only guess at what pad size the manufacturers of future BGAs will
use, it becomes difficult to always have the right answer.

Other BGAs have real 90% Pb balls on them.  These do not melt, and the
soldering process for these components create two solder joints.  One from
the Component to the 90% Pb ball, and a second from the ball to the board.
In this case, the board pad size will depend on the ball size.

There are other BGA configurations, such as solder columns, which, again,
you have to look at individually.

As an aside question (or complaint), Have people found that the information
the component manufacturers put in their component spec sheets (pad size
and
spacing, and what has to be done to route the pin out....)  Have people
found that these follow any kind of DFM process?  In my experience, when my
Engineers choose the smallest, most dense component packages, we often end
up with a very interesting Fab and Assembly designs.

George Franck

-----Original Message-----
From: Lou Hart [mailto:[log in to unmask]]
Sent: Tuesday, January 08, 2002 5:10 PM
To: [log in to unmask]
Subject: [TN] Use of IPC-7095, -SM-782, and -7525


TechNetters, I have a question regarding consistency of 7095 (Design and
Assembly Process Implementation for BGAs), SM-782 (the Surface Mount pad
document), and 7525 (Stencil Design Guidelines), resulting from discussion
with process engineers and techs earlier today.

We were looking at a BGA, 20x20 package, with 1.27 mm pitch.  The stencil
design guidelines (7525, Table 1 on p. 4), call for an aperture of 0.75 mm.
 That table also refers to a 0.80 mm pad.  SM-782 (section 14) says a 20x20
BGA will have 0.75 mm balls that should go onto 0.60 mm pads.  Do these
documents contradict each other regarding pad size, and is 7525 wrong with
regard to BGA stencils?

Further, the bare board does have 0.60 mm pads for the BGA.  7095, in
6.2.1, p. 33, says "land diameter is usually smaller than the ball
diameter..land size reduction of 20 to 25% has been determined to provide
reliable attachment...".

As always, thanks for any comments.  Lou Hart

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=========================================================================
Date:         Wed, 9 Jan 2002 21:49:38 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_160.6def5c6.296e5b42_boundary"

--part1_160.6def5c6.296e5b42_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Joe

remember that baking also anneals the copper

Rich Fudalewski

--part1_160.6def5c6.296e5b42_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Joe
<BR>
<BR>remember that baking also anneals the copper
<BR>
<BR>Rich Fudalewski</FONT></HTML>

--part1_160.6def5c6.296e5b42_boundary--

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Date:         Wed, 9 Jan 2002 21:54:03 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Use of IPC-7095, -SM-782, and -7525
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

whinge  Verb. To persistently complain, in an irritating manner. {Informal}.
Noun. To act in the manner of the verb. {Informal}.
whinger  Noun. A person who whinges. {Informal}.
whingey  Adj. In the manner of a whinger. {Informal}.
 [http://www.peevish.co.uk/slang/w.htm]


----- Original Message -----
From: "<Peter George Duncan>" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 09, 2002 5:34 PM
Subject: Re: [TN] Use of IPC-7095, -SM-782, and -7525


> George,
>
> To respond to your aside, my 2 cents worth is that the "mechanical" info
on
> component data sheets is very poor. Most of the content focusses on the
> electrical functionality of the device, but there's precious little help
> with mounting the b-----s. A few data sheets have land pattern
> recommendations if you're lucky (one diode spec I came across even had
> separate land pattern recommendations for both CR and Wave  solder -
> exceptional! or may be there isn't enough to say about a diode otherwise
to
> fill a decent data sheet). BUT, there is little or nothing about
> "environment/habitat" requirements for where the component is going to
> live. How is it to be established in its new home, what sort of neighbours
> should it have/not have, how much space it needs from said neighbours,
etc.
> Particularly tiresome to find at times is lead finish information - it's
> available, often on a separate spec for the package, but there's no cross
> reference to where this info can be found, and you can be left guessing if
> it's not a "standard" package.
>
> Some more assistance to the poor board stuffer would be welcome instead of
> giving everything to our ethereal design engineers, who move on a higher
> plane. Many board designs, especially aerospace applications, use a great
> many components on a board, and to get all the needed information on each
> to integrate them all into a working design that can be manufactured is a
> herculean task. It could, I'm sure, be made a lot easier with the
> co-operation of the component manufacturers, though I guess there's a fair
> amount of butt protection involved - the more they say, the more they can
> be held liable for. Or am I getting too cynical now?
>
> I suggested a while ago on this forum that perhaps IPC could produce a
> guideline about component specs - their format, content, minimum info
> requirements for all those involved with using the component. It met with
> deafening silence - probably because there is an almost infinite number of
> design permutations and it would be impossible to cover all the bases with
> hard facts, but better information on how to determine our own solutions
> could be included, and not have the specs turn into Encyclopedia
> Britannica.
>
> End winge.
>
> Peter
>
>
>
>
>                     "Franck, George"
>                     <george_h_franck@RAY        To:     [log in to unmask]
>                     THEON.COM>                  cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
>                     Sent by: TechNet            Aero/ST Group)
>                     <[log in to unmask]>           Subject:     Re: [TN] Use
of IPC-7095, -SM-782,
>                                                 and -7525
>
>                     01/09/02 10:12 PM
>                     Please respond to
>                     "TechNet E-Mail
>                     Forum."
>
>
>
>
>
>
> I have been playing around, blindly, with this topic for a little while.
> This is what I have learned, precious little that it is.
>
> The answer depends on the BGA construction.  Many/most BGAs do not
actually
> have balls on them, they have 'bumps' of 63/37 solder.  These bumps will
> completely melt during reflow, allowing the BGA to float on molten solder
> during the soldering process.  For these components, you *generally* want
> the pad on the board to be the same size as the pad on the component.
With
> the pads being the same size, the resulting solder joint will be
> symmetrical, top to bottom.  Since the writers of the Specs, (bless them
> all), can only guess at what pad size the manufacturers of future BGAs
will
> use, it becomes difficult to always have the right answer.
>
> Other BGAs have real 90% Pb balls on them.  These do not melt, and the
> soldering process for these components create two solder joints.  One from
> the Component to the 90% Pb ball, and a second from the ball to the board.
> In this case, the board pad size will depend on the ball size.
>
> There are other BGA configurations, such as solder columns, which, again,
> you have to look at individually.
>
> As an aside question (or complaint), Have people found that the
information
> the component manufacturers put in their component spec sheets (pad size
> and
> spacing, and what has to be done to route the pin out....)  Have people
> found that these follow any kind of DFM process?  In my experience, when
my
> Engineers choose the smallest, most dense component packages, we often end
> up with a very interesting Fab and Assembly designs.
>
> George Franck
>
> -----Original Message-----
> From: Lou Hart [mailto:[log in to unmask]]
> Sent: Tuesday, January 08, 2002 5:10 PM
> To: [log in to unmask]
> Subject: [TN] Use of IPC-7095, -SM-782, and -7525
>
>
> TechNetters, I have a question regarding consistency of 7095 (Design and
> Assembly Process Implementation for BGAs), SM-782 (the Surface Mount pad
> document), and 7525 (Stencil Design Guidelines), resulting from discussion
> with process engineers and techs earlier today.
>
> We were looking at a BGA, 20x20 package, with 1.27 mm pitch.  The stencil
> design guidelines (7525, Table 1 on p. 4), call for an aperture of 0.75
mm.
>  That table also refers to a 0.80 mm pad.  SM-782 (section 14) says a
20x20
> BGA will have 0.75 mm balls that should go onto 0.60 mm pads.  Do these
> documents contradict each other regarding pad size, and is 7525 wrong with
> regard to BGA stencils?
>
> Further, the bare board does have 0.60 mm pads for the BGA.  7095, in
> 6.2.1, p. 33, says "land diameter is usually smaller than the ball
> diameter..land size reduction of 20 to 25% has been determined to provide
> reliable attachment...".
>
> As always, thanks for any comments.  Lou Hart
>
> --------------------------------------------------------------------------
--
>
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Technet NOMAIL
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
--
>
> -----
>
> --------------------------------------------------------------------------
-------
>
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> --------------------------------------------------------------------------
-------
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you are not
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> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
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>
> --------------------------------------------------------------------------
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=========================================================================
Date:         Thu, 10 Jan 2002 11:06:31 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Olivia Mc Dermott <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Thanks Lou,
Has anyone noticed another error in the amendment? 6.8.2.2 - High Voltage -
Solder Cups - Unused - a defect for the unused cup is if the insulation
clearance is greater than one wire diameter. If the cup is unused, where is
the wire coming from??????


>From: Lou Hart <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Lead Length/Protrusion
>Date: Wed, 9 Jan 2002 09:38:10 -0500
>
>Olivia, maybe others will have noticed this, too, but Amendment 1 to 610C
>changes 2.3 to 2.5.  Lou Hart
>
>-----Original Message-----
>From:   Olivia Mc Dermott [SMTP:[log in to unmask]]
>Sent:   Wednesday, January 09, 2002 8:41 AM
>To:     [log in to unmask]
>Subject:        [TN] Lead Length/Protrusion
>
>Hi ALl,
>Why are there 2 references to lead length/protrusion in IPC-A-610C. In
>'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
>lead
>protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
>protrusion for class 2 is 2.3mm. Which one do we use?
>
>_________________________________________________________________
>MSN Photos is the easiest way to share and print your photos:
>http://photos.msn.com/support/worldwide.aspx
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
>
>---------------------------------------------------------------------------------
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Date:         Thu, 10 Jan 2002 12:25:16 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Olivia Mc Dermott <[log in to unmask]>
Subject:      Blow Holes
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Hi All, Busy today,
Blow holes/pin holes, according to table 6-2 in IPC-A-610C are accpetable as
long as circumferential wetting on secondary side is 270 degrees for class 2
and 330 degrees for class 3. What quantity of blow holes does that cover on
one assembly? If it were all over the PCB randomly every board, would it
still be acceptable?

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Date:         Thu, 10 Jan 2002 07:20:58 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Green Slime on QFP lead toes...
MIME-Version: 1.0
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Steve,
From your description, I would guess that the green material is a grease,
probably a die lubricant used in the lead trimming operation, that has
picked up copper over time.  The copper turns green.  Running some FTIR, as
Bev suggests, would give you some insight on the nature of the grease.
Doing  a SEM/EDX would tell you if you have copper in the sample.  You will
also likely see chloride and sulfur, common to lubricants.

Doug

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Date:         Thu, 10 Jan 2002 07:55:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
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Olivia,
Thanks, we'll put that on the slate for revision D.
I could use my favorite excuse and blame it on Jack but that really wouldn't
be true or fair.  Aw heck who wants to be fair this time of the morning,
Jack did it.

Mel P


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Thursday, January 10, 2002 3:07 AM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Thanks Lou,
Has anyone noticed another error in the amendment? 6.8.2.2 - High Voltage -
Solder Cups - Unused - a defect for the unused cup is if the insulation
clearance is greater than one wire diameter. If the cup is unused, where is
the wire coming from??????


>From: Lou Hart <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Lead Length/Protrusion
>Date: Wed, 9 Jan 2002 09:38:10 -0500
>
>Olivia, maybe others will have noticed this, too, but Amendment 1 to 610C
>changes 2.3 to 2.5.  Lou Hart
>
>-----Original Message-----
>From:   Olivia Mc Dermott [SMTP:[log in to unmask]]
>Sent:   Wednesday, January 09, 2002 8:41 AM
>To:     [log in to unmask]
>Subject:        [TN] Lead Length/Protrusion
>
>Hi ALl,
>Why are there 2 references to lead length/protrusion in IPC-A-610C. In
>'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
>lead
>protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
>protrusion for class 2 is 2.3mm. Which one do we use?
>
>_________________________________________________________________
>MSN Photos is the easiest way to share and print your photos:
>http://photos.msn.com/support/worldwide.aspx
>
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Date:         Thu, 10 Jan 2002 08:06:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Thanks Peter,
Wish you could have been there for the last revision.  There was a concerted
effort to block inclusion of BGA criteria in the last release. Hopefully we
can do better this time around.  Any pictures you can spare would be
appreciated.  We have added a new XRay capability and should be able to
support that development also.
What about Flip Chip content from the assembly acceptability viewpoint?
Also with the advent of newer technology applications, wire bond criteria?

Mel Parrish


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
Sent: Wednesday, January 09, 2002 4:39 PM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Mel,

I whole-heartedly second your desire to see more SMT applications detailed
in the spec, especially BGA mounting and inspection (with X-ray pictures
and how to interpret them).

Peter




                    Mel Parrish
                    <mparrish@SOLDERIN        To:     [log in to unmask]
                    GTECH.COM>                cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    Sent by: TechNet          Aero/ST Group)
                    <[log in to unmask]>         Subject:     Re: [TN] Lead
Length/Protrusion


                    01/10/02 12:05 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We
have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

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Date:         Thu, 10 Jan 2002 10:47:39 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Rich,
I must be braindead this morning, expound on "anneals" if you would,
rather, remind me what that means.
Thanx
braindead Joe

Quoting [log in to unmask]:

> Joe
>
> remember that baking also anneals the copper
>
> Rich Fudalewski
>



Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Thu, 10 Jan 2002 08:49:41 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: Blow Holes
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable

HI Olivia! The quantity of blowholes you consider to be acceptable woul=
d
depend heavily on the use environment where that assembly is going to
reside. For example, I would be less concern with blowholes on an assem=
bly
which was going into an office use environment in comparison to an avio=
nics
equipment bay environment. However, you should be asking one important
question - why are you getting all of these blowholes? Are the blowhole=
s a
sign of a bigger problem such a poor plated thru hole plating integrity=
?
Blowholes should be a random, isolated, occasional issue and not someth=
ing
you typically observe. Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]





Olivia Mc Dermott <[log in to unmask]>@ipc.org> on 01/10/200=
2
06:25:16 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] Blow Holes


Hi All, Busy today,
Blow holes/pin holes, according to table 6-2 in IPC-A-610C are accpetab=
le
as
long as circumferential wetting on secondary side is 270 degrees for cl=
ass
2
and 330 degrees for class 3. What quantity of blow holes does that cove=
r on
one assembly? If it were all over the PCB randomly every board, would i=
t
still be acceptable?

_________________________________________________________________
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Date:         Thu, 10 Jan 2002 15:03:14 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Owen <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Joseph,

Anneal
1 To temper or toughen (something) by heat treatment to remove internal
stress, crystal defects, and dislocations.

Steve.

-----Original Message-----
From: Joseph Spicuzza [mailto:[log in to unmask]]
Sent: 10 January 2002 15:48
To: [log in to unmask]
Subject: Re: [TN] hole wall pull away and resin recession


Rich,
I must be braindead this morning, expound on "anneals" if you would,
rather, remind me what that means.
Thanx
braindead Joe

Quoting [log in to unmask]:

> Joe
>
> remember that baking also anneals the copper
>
> Rich Fudalewski
>



Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Thu, 10 Jan 2002 16:17:10 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Blow Holes
Mime-Version: 1.0
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Olivia

It might not only be the question wether the quantity of blowholes you see =
is acceptable but rather that the occurrence of a large number of =
blowholes is an indicator that something in your process is going to run =
wild. You better try to pin that problem before you have more holes than =
solder.

Have a great day


Guenter


.

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Thu, 10 Jan 2002 11:36:34 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
In-Reply-To:  <D1D4A262894FD511A65900902707BB243845C0@CARDIFF-NT-MAIL>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
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Thanks Steve,
A follow up question: Does the copper then get more brittle? To a point that
the processing should change?
Joe


Quoting Steve Owen <[log in to unmask]>:

> Joseph,
>
> Anneal
> 1 To temper or toughen (something) by heat treatment to remove internal
> stress, crystal defects, and dislocations.
>
> Steve.
>
> -----Original Message-----
> From: Joseph Spicuzza [mailto:[log in to unmask]]
> Sent: 10 January 2002 15:48
> To: [log in to unmask]
> Subject: Re: [TN] hole wall pull away and resin recession
>
>
> Rich,
> I must be braindead this morning, expound on "anneals" if you would,
> rather, remind me what that means.
> Thanx
> braindead Joe
>
> Quoting [log in to unmask]:
>
> > Joe
> >
> > remember that baking also anneals the copper
> >
> > Rich Fudalewski
> >
>
>
>
> Joseph Spicuzza
> Quality Assurance Supervisor
> Advanced Interconnect Products Division
> Compunetics, Inc.
> ph: 412 858-6166
> fax 412 373-8060
> [log in to unmask]
>
> ----------------------------------------------------------------------------
> -----
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> ------------------------------------------------------------------------------
---
>



Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Thu, 10 Jan 2002 10:45:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Joseph,

the annealing normally precedes lamination, so it does not make the metals
more brittle, but ductile.

Ioan

> -----Original Message-----
> From: Joseph Spicuzza [SMTP:[log in to unmask]]
> Sent: Thursday, January 10, 2002 11:37 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] hole wall pull away and resin recession
>
> Thanks Steve,
> A follow up question: Does the copper then get more brittle? To a point
> that
> the processing should change?
> Joe
>
>
> Quoting Steve Owen <[log in to unmask]>:
>
> > Joseph,
> >
> > Anneal
> > 1 To temper or toughen (something) by heat treatment to remove internal
> > stress, crystal defects, and dislocations.
> >
> > Steve.
> >
> > -----Original Message-----
> > From: Joseph Spicuzza [mailto:[log in to unmask]]
> > Sent: 10 January 2002 15:48
> > To: [log in to unmask]
> > Subject: Re: [TN] hole wall pull away and resin recession
> >
> >
> > Rich,
> > I must be braindead this morning, expound on "anneals" if you would,
> > rather, remind me what that means.
> > Thanx
> > braindead Joe
> >
> > Quoting [log in to unmask]:
> >
> > > Joe
> > >
> > > remember that baking also anneals the copper
> > >
> > > Rich Fudalewski
> > >
> >
> >
> >
> > Joseph Spicuzza
> > Quality Assurance Supervisor
> > Advanced Interconnect Products Division
> > Compunetics, Inc.
> > ph: 412 858-6166
> > fax 412 373-8060
> > [log in to unmask]
> >
> >
> --------------------------------------------------------------------------
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>
> Joseph Spicuzza
> Quality Assurance Supervisor
> Advanced Interconnect Products Division
> Compunetics, Inc.
> ph: 412 858-6166
> fax 412 373-8060
> [log in to unmask]
>
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Date:         Thu, 10 Jan 2002 11:18:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jack Crawford <[log in to unmask]>
Subject:      Re: Lead Length/Protrusion
Mime-Version: 1.0
Content-Type: multipart/alternative; boundary="=_4C1140E9.503157F1"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_4C1140E9.503157F1
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

>>> [log in to unmask] 01/10/02 05:06AM >>>

Has anyone noticed another error in the amendment? 6.8.2.2 - High Voltage =
-
Solder Cups - Unused - a defect for the unused cup is if the insulation
clearance is greater than one wire diameter. If the cup is unused, where =
is
the wire coming from??????

--=_4C1140E9.503157F1
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY=20
style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">&gt;&g=
t;&gt;=20
[log in to unmask] 01/10/02 05:06AM &gt;&gt;&gt;<BR><BR>Has =
anyone=20
noticed another error in the amendment? 6.8.2.2 - High Voltage -<BR>Solder =
Cups=20
- Unused - a defect for the unused cup is if the insulation<BR>clearance =
is=20
greater than one wire diameter. If the cup is unused, where is<BR>the =
wire=20
coming from??????<BR><BR><BR></BODY></HTML>

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Date:         Thu, 10 Jan 2002 15:43:41 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Gary Bremer <[log in to unmask]>
Subject:      Lead Free Soldering
Mime-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable

I am looking at moving my soldering process to use leadfree solder
sometime this year.  Has anyone already shifted over to using
leadfree solder?  What type of problems would I expect to
encounter with using a leadfree solder?  The solder material that
NEMI is suggesting is SnAgCu, is this going to pose any real
problems because the temperature is at 217=B0 Celsius with the
laminate material or what components are selected?  Will I be
forced to change the finish on the bare board from HASL?  Any help
or suggestions I get will be greatly appriciated.

Gary Bremer,
Manufacturing Engineer

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Date:         Thu, 10 Jan 2002 14:02:34 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Abrahamson <[log in to unmask]>
Subject:      Re: Lead Free Soldering
X-To:         "[log in to unmask]" <[log in to unmask]>

Hey Gary,

Not to be sarcastic or anything, but you would want to get rid of HASL if
you want to make an attempt to be lead free!- although good luck getting
component suppliers to "get the lead out"..  Electroless Nickel Immersion
Gold (ENIG), Immersion Silver or Immersion Tin might be a good alternative
for surface finish.  If you are doing straight SMT you could even go with an
OSP.  If you have a mixed technology process, you might want to check the
capabilities of your wave solder equipment, and consider that the elevated
preheat for wavesolder might affect some low temp topside TH devices.

Steve A

> -----Original Message-----
> From: Gary Bremer [SMTP:[log in to unmask]]
> Sent: Thursday,January 10,2002 1:44 PM
> To:   [log in to unmask]
> Subject:      [TN] Lead Free Soldering
>
> I am looking at moving my soldering process to use leadfree solder
> sometime this year.  Has anyone already shifted over to using
> leadfree solder?  What type of problems would I expect to
> encounter with using a leadfree solder?  The solder material that
> NEMI is suggesting is SnAgCu, is this going to pose any real
> problems because the temperature is at 217? Celsius with the
> laminate material or what components are selected?  Will I be
> forced to change the finish on the bare board from HASL?  Any help
> or suggestions I get will be greatly appriciated.
>
> Gary Bremer,
> Manufacturing Engineer
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
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Date:         Thu, 10 Jan 2002 16:23:35 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lee Whiteman <[log in to unmask]>
Subject:      Re: Lead Free Soldering
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

Gary,

In a nutshell, here are some answers:

1. Depending on the industry (commercial vs. civil vs. aerospace), some
manufacturers have made the conversion to Pb-Free. I know that Nortel
converted some of their cell phone line in Europe to Pb-Free. I've heard
that HP is in process of converting some of their commercial lines to
Pb-Free.

2. Depending on your manufacturing equipment, you may have problems reaching
the Pb-Free reflow soldering temperatures. For example, for SnPb, reflow
soldering is usually 220C. For SnAgCu, reflow soldering temperatures are
approximately 240C, with some alloys (depending upon the vendor) getting as
high as 260C.

3. At such high temperatures, board materials and components may not
survive. I've run FR4 through at the higher temperatures successfully.
Boards (especially polyimide boards which absorb moisture like a sponge)
must be baked out thoroughly to assure no moisture is entrapped. Concerning
components, plastic components must be baked out very thoroughly to prevent
popcorning.

4. With proper care, you can meet Class 3 soldering requirements with OSP,
but if I had a preference, I would go with immersion Sn or ENIG. I know
folks are working on Pb-Free HASL, and I would be interested in what the
forum has to say on that one.

From a product reliability perspective, depending upon how much care you put
into the process, you can achieve similar reliability results to SnPb.
Suggest that you get a copy of  the Pb-Free Component Focus Group's report
from IPC Works 2001 as 1 of many sources of information on reliability. The
NCMS report is another source of information.

Good Luck.

Lee Whiteman
Senior Manufacturing Engineer
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x208
Fax: (610) 362-1290



> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Gary Bremer
> Sent: Thursday, January 10, 2002 3:44 PM
> To: [log in to unmask]
> Subject: [TN] Lead Free Soldering
>
>
> I am looking at moving my soldering process to use leadfree solder
> sometime this year.  Has anyone already shifted over to using
> leadfree solder?  What type of problems would I expect to
> encounter with using a leadfree solder?  The solder material that
> NEMI is suggesting is SnAgCu, is this going to pose any real
> problems because the temperature is at 217° Celsius with the
> laminate material or what components are selected?  Will I be
> forced to change the finish on the bare board from HASL?  Any help
> or suggestions I get will be greatly appriciated.
>
> Gary Bremer,
> Manufacturing Engineer
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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>

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Date:         Thu, 10 Jan 2002 16:55:15 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Good day technet:

We're considering designing a multilayer polyimide PWB with a number of vias
(approximately .021" diameter holes, .062" thick PWB) that are plated shut,
for thermal reasons.  Can anyone comment on pitfalls regarding the fab
process?  How about voids in the solid copper via?  Entrapped plating
solution?

All comments are appreciated.  Thanks in advance...

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Thu, 10 Jan 2002 17:10:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Lead Free Soldering
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_13d.78934a5.296f6b45_boundary"

--part1_13d.78934a5.296f6b45_boundary
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi Gary,

Another thing you might want to be aware of is your wave solder...I've heard=
=20
from more than just a few people that high tin content solders will eat=20
through stainless steel solder pots. I've heard that you could be changing=20
pots every few years depending on how much you run.

-Steve Gregory-

> I am looking at moving my soldering process to use leadfree solder
> sometime this year.  Has anyone already shifted over to using
> leadfree solder?  What type of problems would I expect to
> encounter with using a leadfree solder?  The solder material that
> NEMI is suggesting is SnAgCu, is this going to pose any real
> problems because the temperature is at 217=B0 Celsius with the
> laminate material or what components are selected?  Will I be
> forced to change the finish on the bare board from HASL?  Any help
> or suggestions I get will be greatly appriciated.
>=20
> Gary Bremer,
> Manufacturing Engineer
>=20



--part1_13d.78934a5.296f6b45_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

<HTML><FONT FACE=3Darial,helvetica><FONT  SIZE=3D2>Hi Gary,
<BR>
<BR>Another thing you might want to be aware of is your wave solder...I've h=
eard from more than just a few people that high tin content solders will eat=
 through stainless steel solder pots. I've heard that you could be changing=20=
pots every few years depending on how much you run.
<BR>
<BR>-Steve Gregory-
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I am looking at moving my s=
oldering process to use leadfree solder
<BR>sometime this year. &nbsp;Has anyone already shifted over to using
<BR>leadfree solder? &nbsp;What type of problems would I expect to
<BR>encounter with using a leadfree solder? &nbsp;The solder material that
<BR>NEMI is suggesting is SnAgCu, is this going to pose any real
<BR>problems because the temperature is at 217=B0 Celsius with the
<BR>laminate material or what components are selected? &nbsp;Will I be
<BR>forced to change the finish on the bare board from HASL? &nbsp;Any help
<BR>or suggestions I get will be greatly appriciated.
<BR>
<BR>Gary Bremer,
<BR>Manufacturing Engineer
<BR></FONT><FONT  COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR></FONT></HTML>

--part1_13d.78934a5.296f6b45_boundary--

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Date:         Thu, 10 Jan 2002 16:18:08 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Jim

IMO you should avoid true plated shut vias.  As holes plate in an
electrolytic process, the outer portion of the hole plates faster than the
portion of the barrel that is near the center of board (dog bone plating).
This can result in trapped chemicals in the barrel of the hole.  As an
alternative you might consider plugging the holes with a conductive epoxy
such as DuPont's CB100.  A .021 dia hole in a .062 thick board is within the
capability of several board shops.  You will most likely find this
capability with shops that build high reliability products.

The holes are plugged before the final finish is applied, and they should
provide a flat final surface on the finished board.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Thursday, January 10, 2002 3:55 PM
To: [log in to unmask]
Subject: [TN] VIAS PLATED CLOSED


Good day technet:

We're considering designing a multilayer polyimide PWB with a number of vias
(approximately .021" diameter holes, .062" thick PWB) that are plated shut,
for thermal reasons.  Can anyone comment on pitfalls regarding the fab
process?  How about voids in the solid copper via?  Entrapped plating
solution?

All comments are appreciated.  Thanks in advance...

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

----------------------------------------------------------------------------
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Date:         Thu, 10 Jan 2002 16:59:34 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jack Crawford <[log in to unmask]>
Subject:      Re: Lead Free Soldering
Mime-Version: 1.0
Content-Type: multipart/alternative; boundary="=_84D98BF2.59385EF1"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_84D98BF2.59385EF1
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable

Of course, subscribing to the IPC sponsored forum NoLeadTech is another =
way to get answers. That forum is reserved for discussion of lead-free =
soldering research and implementation issues. Another forum is leadfree =
but questions about how to do something on that forum usually get more =
comments about why you shouldn't be asking than answers to your questions.

>>> [log in to unmask] 01/10/02 04:10PM >>>
Hi Gary,=20

Another thing you might want to be aware of is your wave solder...I've =
heard from more than just a few people that high tin content solders will =
eat through stainless steel solder pots. I've heard that you could be =
changing pots every few years depending on how much you run.=20

-Steve Gregory-=20


I am looking at moving my soldering process to use leadfree solder=20
sometime this year.  Has anyone already shifted over to using=20
leadfree solder?  What type of problems would I expect to=20
encounter with using a leadfree solder?  The solder material that=20
NEMI is suggesting is SnAgCu, is this going to pose any real=20
problems because the temperature is at 217=B0 Celsius with the=20
laminate material or what components are selected?  Will I be=20
forced to change the finish on the bare board from HASL?  Any help=20
or suggestions I get will be greatly appriciated.=20

Gary Bremer,=20
Manufacturing Engineer=20

--=_84D98BF2.59385EF1
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px"><FONT=20
size=3D1>Of course, subscribing to the IPC sponsored forum NoLeadTech =
is=20
another&nbsp;way to get answers. That forum is reserved for discussion =
of=20
lead-free soldering research and implementation issues. Another forum =
is=20
leadfree but questions about how to do something on that forum usually get =
more=20
comments about why you shouldn't be asking than answers to your=20
questions.</FONT><BR><BR>&gt;&gt;&gt; [log in to unmask] 01/10/02 04:10PM=20=

&gt;&gt;&gt;<BR><FONT face=3Darial,helvetica><FONT size=3D2>Hi Gary, =
<BR><BR>Another=20
thing you might want to be aware of is your wave solder...I've heard from =
more=20
than just a few people that high tin content solders will eat through =
stainless=20
steel solder pots. I've heard that you could be changing pots every few =
years=20
depending on how much you run. <BR><BR>-Steve Gregory- <BR><BR>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid; MARGIN-RIGHT: 0px"=20
TYPE=3D"CITE">I am looking at moving my soldering process to use leadfree =
solder=20
  <BR>sometime this year. &nbsp;Has anyone already shifted over to =
using=20
  <BR>leadfree solder? &nbsp;What type of problems would I expect to=20
  <BR>encounter with using a leadfree solder? &nbsp;The solder material =
that=20
  <BR>NEMI is suggesting is SnAgCu, is this going to pose any real =
<BR>problems=20
  because the temperature is at 217=B0 Celsius with the <BR>laminate =
material or=20
  what components are selected? &nbsp;Will I be <BR>forced to change the =
finish=20
  on the bare board from HASL? &nbsp;Any help <BR>or suggestions I get =
will be=20
  greatly appriciated. <BR><BR>Gary Bremer, <BR>Manufacturing Engineer=20
  <BR></FONT><FONT lang=3D0 face=3DArial color=3D#000000 size=3D3=20
FAMILY=3D"SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=3D0 face=3DArial =
color=3D#000000=20
size=3D2 FAMILY=3D"SANSSERIF"><BR></FONT></FONT></BODY></HTML>

--=_84D98BF2.59385EF1--

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Date:         Thu, 10 Jan 2002 15:28:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Dupont LG1000
MIME-Version: 1.0
Content-Type: text/plain

I'm looking for info about a material (prepreg) called LG1000 from DuPont.
I'm not finding anything on their webpage, on dogpile or in the archives.
Can anybody provide a lead?

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Date:         Thu, 10 Jan 2002 18:32:47 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Fjelstad <[log in to unmask]>
Subject:      Re: Lead Free Soldering
Mime-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit

Hi Jack

What is the intent of this comment?

"Of course, subscribing to the IPC sponsored forum NoLeadTech is another way to get answers. That forum is reserved for discussion of lead-free soldering research and implementation issues. Another forum is leadfree but questions about how to do something on that forum usually get more comments about why you shouldn't be asking than answers to your questions."

It sounds rather disparaging.

Information about the problems of leadfree should not be swept under the rug. Opposing information and views are not threats. Shutting down this site is one way to end the discussion if that is what is sought.

Kind regards,
Joe

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Date:         Thu, 10 Jan 2002 19:21:39 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Dupont LG1000
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_9d.2156dc05.296f8a13_boundary"

--part1_9d.2156dc05.296f8a13_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Here's a link:

http://map3.msfc.nasa.gov/mapweb/tr/tr3_01181.html

-Steve Gregory-


> I'm looking for info about a material (prepreg) called LG1000 from DuPont.
> I'm not finding anything on their webpage, on dogpile or in the archives.
> Can anybody provide a lead?
>


--part1_9d.2156dc05.296f8a13_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Here's a link:<BR>
<BR>
http://map3.msfc.nasa.gov/mapweb/tr/tr3_01181.html<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I'm looking for info about a material (prepreg) called LG1000 from DuPont.<BR>
I'm not finding anything on their webpage, on dogpile or in the archives.<BR>
Can anybody provide a lead?<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_9d.2156dc05.296f8a13_boundary--

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Date:         Thu, 10 Jan 2002 16:35:57 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brooks,Bill" <[log in to unmask]>
Subject:      Re: Lead Free Soldering
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Joe and Jack,

You peaked my interest enough to make a comment and ask a question...
I have been hearing rumblings in the industry about lead free soldering for
awhile now... and I understand that there are some obstacles to the process
that are undesirable at best. Pure tin welds for component mounting are more
than likely more brittle compared to tin/lead alloy welds. And the tin/lead
alloy melts at a much lower temp than tin by itself... This means exposing
the components to much higher temperatures in order to solder. Extreme temp
exposure is probably undesirable for a lot of reasons structurally and
electrically...
Is the only benefit environmental? Are we just trying to formulate 'lead
free' to avoid using lead because of its poisonous nature or is there some
other benefit from the process that escapes me? Gold uses cyanide in its
process.... should we be gold free too?


Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm


-----Original Message-----
From: Joseph Fjelstad [mailto:[log in to unmask]]
Sent: Thursday, January 10, 2002 3:33 PM
To: [log in to unmask]
Subject: Re: [TN] Lead Free Soldering


Hi Jack

What is the intent of this comment?

"Of course, subscribing to the IPC sponsored forum NoLeadTech is another way
to get answers. That forum is reserved for discussion of lead-free soldering
research and implementation issues. Another forum is leadfree but questions
about how to do something on that forum usually get more comments about why
you shouldn't be asking than answers to your questions."

It sounds rather disparaging.

Information about the problems of leadfree should not be swept under the
rug. Opposing information and views are not threats. Shutting down this site
is one way to end the discussion if that is what is sought.

Kind regards,
Joe

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Date:         Fri, 11 Jan 2002 09:34:27 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: IPC-A-610 update - BGA's
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Mel,

I wish I had some good pictures I could send you, and X-rays, but on two
counts, that's not quite possible yet - 1) we actually don't have a handy
digital camera for such work, though I'm aiming to get one and 2) the X-ray
facilities out here in Singapore are well less than wonderful. I could try
a hospital set-up, but they're fully booked. To get any half way decent
magnification on our images, the machine our test lab has suffers from a
wide angle effect - i.e. the straight lines of balls have developed a
distinct curvature at the outer edges. If it were a straight picture, the
results could be interpreted as incorrect land pattern size, as I get
increasingly oval features on the X-rays, radiating out from the centre to
the edges and corners, but I know the BGA's are OK.

If you're putting BGA's into 610D, maybe you can include underfilling as
well. Anyone know of anyone in Singapore with an ultrasonic inspection
machine for checking underfill, by the way? So far, as long as the board
has had a good clean and the underfill comes out the other sides, I have to
accept that the fill underneath is OK, as I haven't found anywhere to check
it out.

I haven't found an official spec yet either that covers requirements for
underfilling BGA's, especially on class 3 military boards - only learned
papers on what the material does, how it works and how it can be inspected.
Does anyone know of one? Are there any added problems if underfill is
incomplete, for example, or is there just reduced effectiveness if there
are voids around any of the balls or elsewhere in the fill?

Another topic for 610D could be more on MSD's and the effects/inspection
methodology/acceptability of moisture-laden components having been mounted
onto boards - warping, delaminating, etc.

610D could become substantially fatter than its earlier versions!

Peter




                    Mel Parrish
                    <mparrish@SOLDERIN        To:     [log in to unmask]
                    GTECH.COM>                cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet          Aero/ST Group)
                    <[log in to unmask]>         Subject:     Re: [TN] Lead Length/Protrusion


                    01/11/02 12:06 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Thanks Peter,
Wish you could have been there for the last revision.  There was a
concerted
effort to block inclusion of BGA criteria in the last release. Hopefully we
can do better this time around.  Any pictures you can spare would be
appreciated.  We have added a new XRay capability and should be able to
support that development also.
What about Flip Chip content from the assembly acceptability viewpoint?
Also with the advent of newer technology applications, wire bond criteria?

Mel Parrish


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
Sent: Wednesday, January 09, 2002 4:39 PM
To: [log in to unmask]
Subject: Re: [TN] Lead Length/Protrusion


Mel,

I whole-heartedly second your desire to see more SMT applications detailed
in the spec, especially BGA mounting and inspection (with X-ray pictures
and how to interpret them).

Peter




                    Mel Parrish
                    <mparrish@SOLDERIN        To:     [log in to unmask]
                    GTECH.COM>                cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    Sent by: TechNet          Aero/ST Group)
                    <[log in to unmask]>         Subject:     Re: [TN] Lead
Length/Protrusion


                    01/10/02 12:05 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Olivia
Amendment 1 to 610C identifies 2.5mm as the correct value.  The amendment
was released a couple of months ago and is available on the IPC web site.
By the way, work is in progress toward Revision D to this document.  We
have
accumulated a number of comments and would appreciate any additional
information that you would like to see in the new 610. We certainly could
use some additional information on the newer technology applications.

The next technical meeting will be at APEX on 19 Jan.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
Sent: Wednesday, January 09, 2002 5:41 AM
To: [log in to unmask]
Subject: [TN] Lead Length/Protrusion


Hi ALl,
Why are there 2 references to lead length/protrusion in IPC-A-610C. In
'Component Installation Location/Orientation' - point 5.2.7.1 table 5.2
lead
protrusion for class 2 is 2.5mm but in 'Soldering' point 6.2 table 6.1 lead
protrusion for class 2 is 2.3mm. Which one do we use?

_________________________________________________________________
MSN Photos is the easiest way to share and print your photos:
http://photos.msn.com/support/worldwide.aspx

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Date:         Thu, 10 Jan 2002 20:37:06 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Lead Free Soldering
MIME-Version: 1.0
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Hi Bill,

I'm just going to express what my opinions are, and invite others to look at
the facts.

All the horror stories and history about lead poisoning mostly come from lead
based paint...kids eating paint chips that peeled from from old walls, etc..
So we learned that lead was toxic, that's a good thing, no more lead
containing paints.

Another thing that I observed as the "lead-free" ground-swell developed, was
from the guys who hunt ducks, they were affected because it was stated that
the shot from their guns were polluting the wetlands, and were eventually
forced to use steel shot.
Of course this doesn't apply to the miltary, but there are a lot of
projectiles made from depleted uranium...don't know how bad that stuff is,
and don't know if it matters...but, after all, we're talking planet ecology
here aren't we?

Now we got TRI facing everybody...including the home gun enthusiasts who
shoots skeet on a regular basis. If the poor guy reloads more than a 100-lbs
of shells that  contain lead over the year, he, by law has to file with the
EPA.

I'm not against protecting the environment, but it needs to be done in a more
rational method in my opinion. The push for us in the electronics industry to
turn the processes that have been developed over many, many years
upside-down, in the name of enviromental benefit to me is very, very shallow.

Anyone can search and find for themselves that the use of lead in our
industry is minuscule in the overall scheme of things...we ARE NOT THE
POLLUTERS!!!

Look at the battery industry...why aren't they being forced to go "Lead
Free"?

Somebody is standing to make a lot of money by forcing this issue, it's not
environmental in my opinion...the Japanese are jumping on board because
Europe is forcing the issue....

I won't say that making things "lead-free" is a bad thing (but there are some
aspects of it that maybe a bad thing). But those statements that say it's
"for the environment", are misleading, and not the TRUE reason.

-Steve Gregory-





> Hi Joe and Jack,
>
> You peaked my interest enough to make a comment and ask a question...
> I have been hearing rumblings in the industry about lead free soldering for
> awhile now... and I understand that there are some obstacles to the process
> that are undesirable at best. Pure tin welds for component mounting are
> more
> than likely more brittle compared to tin/lead alloy welds. And the tin/lead
> alloy melts at a much lower temp than tin by itself... This means exposing
> the components to much higher temperatures in order to solder. Extreme temp
> exposure is probably undesirable for a lot of reasons structurally and
> electrically...
> Is the only benefit environmental? Are we just trying to formulate 'lead
> free' to avoid using lead because of its poisonous nature or is there some
> other benefit from the process that escapes me? Gold uses cyanide in its
> process.... should we be gold free too?
>
>
> Bill Brooks
> PCB Design Engineer , C.I.D.
> DATRON WORLD COMMUNICATIONS, INC
> 3030 Enterprise Court
> Vista, CA 92083
> Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
> mailto:[log in to unmask]
> IPC Designers Council, San Diego Chapter
> http://www.ipc.org/SanDiego/
> http://home.fda.net/bbrooks/pca/pca.htm
>


--part1_180.1ed3f19.296f9bc2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Bill,<BR>
<BR>
I'm just going to express what my opinions are, and invite others to look at the facts. <BR>
<BR>
All the horror stories and history about lead poisoning mostly come from lead based paint...kids eating paint chips that peeled from from old walls, etc.. So we learned that lead was toxic, that's a good thing, no more lead containing paints.<BR>
<BR>
Another thing that I observed as the "lead-free" ground-swell developed, was from the guys who hunt ducks, they were affected because it was stated that the shot from their guns were polluting the wetlands, and were eventually forced to use steel shot.<BR>
Of course this doesn't apply to the miltary, but there are a lot of projectiles made from depleted uranium...don't know how bad that stuff is, and don't know if it matters...but, after all, we're talking planet ecology here aren't we?<BR>
<BR>
Now we got TRI facing everybody...including the home gun enthusiasts who shoots skeet on a regular basis. If the poor guy reloads more than a 100-lbs of shells that&nbsp; contain lead over the year, he, by law has to file with the EPA.<BR>
<BR>
I'm not against protecting the environment, but it needs to be done in a more rational method in my opinion. The push for us in the electronics industry to turn the processes that have been developed over many, many years upside-down, in the name of enviromental benefit to me is very, very shallow.<BR>
<BR>
Anyone can search and find for themselves that the use of lead in our industry is minuscule in the overall scheme of things...we ARE NOT THE POLLUTERS!!!<BR>
<BR>
Look at the battery industry...why aren't they being forced to go "Lead Free"?<BR>
<BR>
Somebody is standing to make a lot of money by forcing this issue, it's not environmental in my opinion...the Japanese are jumping on board because Europe is forcing the issue....<BR>
<BR>
I won't say that making things "lead-free" is a bad thing (but there are some aspects of it that maybe a bad thing). But those statements that say it's "for the environment", are misleading, and not the TRUE reason.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Joe and Jack,<BR>
<BR>
You peaked my interest enough to make a comment and ask a question...<BR>
I have been hearing rumblings in the industry about lead free soldering for<BR>
awhile now... and I understand that there are some obstacles to the process<BR>
that are undesirable at best. Pure tin welds for component mounting are more<BR>
than likely more brittle compared to tin/lead alloy welds. And the tin/lead<BR>
alloy melts at a much lower temp than tin by itself... This means exposing<BR>
the components to much higher temperatures in order to solder. Extreme temp<BR>
exposure is probably undesirable for a lot of reasons structurally and<BR>
electrically...<BR>
Is the only benefit environmental? Are we just trying to formulate 'lead<BR>
free' to avoid using lead because of its poisonous nature or is there some<BR>
other benefit from the process that escapes me? Gold uses cyanide in its<BR>
process.... should we be gold free too?<BR>
<BR>
<BR>
Bill Brooks<BR>
PCB Design Engineer , C.I.D.<BR>
DATRON WORLD COMMUNICATIONS, INC<BR>
3030 Enterprise Court<BR>
Vista, CA 92083<BR>
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510<BR>
mailto:[log in to unmask]<BR>
IPC Designers Council, San Diego Chapter<BR>
http://www.ipc.org/SanDiego/<BR>
http://home.fda.net/bbrooks/pca/pca.htm<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_180.1ed3f19.296f9bc2_boundary--

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Date:         Fri, 11 Jan 2002 09:50:00 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: hole wall pull away and resin recession
MIME-Version: 1.0
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No, Joe,

Annealing is used to relieve "work hardening" in metals and other materials
caused by bending, and the process makes the materials more maleable again
(able to bend). Have you ever seen a blacksmith at work? He pounds away at
red hot iron for a while and then puts it back into his furnace to heat up
to red heat again before pounding on it some more. The heating process
allows the internal stresses that have built up by working the metal to be
relieved, and make the workpiece capable of accepting further work.

Try it yourself. Take a piece of thick copper wire and bend it backwards
and forwards for a bit. You notice it will become increasingly difficult to
bend. This is work-hardening as the stresses are built up, and if you
continue to force the copper to bend, it will become brittle and break
eventually. If, before it breaks, you heat up your bent copper (not a
corrupt policeman, for you Brits out there) to a few hundred degrees for a
little while and allow it to cool slowly, you will find that you can bend
it easily again. The copper has been annealed. Get the picture?

Peter




                    Joseph Spicuzza
                    <jspicuzza@COMPUN        To:     [log in to unmask]
                    ETICS.COM>               cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet         Aero/ST Group)
                    <[log in to unmask]>        Subject:     Re: [TN] hole wall pull away and
                                             resin recession

                    01/11/02 12:36 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Thanks Steve,
A follow up question: Does the copper then get more brittle? To a point
that
the processing should change?
Joe


Quoting Steve Owen <[log in to unmask]>:

> Joseph,
>
> Anneal
> 1 To temper or toughen (something) by heat treatment to remove internal
> stress, crystal defects, and dislocations.
>
> Steve.
>
> -----Original Message-----
> From: Joseph Spicuzza [mailto:[log in to unmask]]
> Sent: 10 January 2002 15:48
> To: [log in to unmask]
> Subject: Re: [TN] hole wall pull away and resin recession
>
>
> Rich,
> I must be braindead this morning, expound on "anneals" if you would,
> rather, remind me what that means.
> Thanx
> braindead Joe
>
> Quoting [log in to unmask]:
>
> > Joe
> >
> > remember that baking also anneals the copper
> >
> > Rich Fudalewski
> >
>
>
>
> Joseph Spicuzza
> Quality Assurance Supervisor
> Advanced Interconnect Products Division
> Compunetics, Inc.
> ph: 412 858-6166
> fax 412 373-8060
> [log in to unmask]
>
>
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Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
ph: 412 858-6166
fax 412 373-8060
[log in to unmask]

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Date:         Fri, 11 Jan 2002 10:27:51 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, James,

I'm trying to picture your "thermal reasons" and how plating over the holes
will help, reliably. I haven't encountered a process for plating over
holes, and 21 mils seems quite a canyon to bridge. I'ld be very interested
to know how this is done.

I'm very involved with conduction-cooled MLB's 60 mils thk, that require a
lot of thermal management. 'Thermal' via holes are punched through the
board and plated to internal thermal planes. To improve the conductive
cross-sectional area of these holes, I had them filled with silver-loaded
epoxy, which was then Cu-plated over. This process also served the
secondary purpose of filling holes that otherwise, as you suggest, would
contain entrapped plating solutions.

Depending on your substrate material and operating environment, I could
imagine a plated 'cap' splitting over time through temp cycling and
mechanical stresses, assuming it survives the hot assembly processes with
the expansion of entrapped gasses. Not serious, thermally, perhaps, but it
would allow the outside atmosphere to circulate inside the holes as well,
which might not be so good inteh long run.

Peter




                    "Marsico, James"
                    <James.Marsico@D        To:     [log in to unmask]
                    P.AIL.COM>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet        Aero/ST Group)
                    <[log in to unmask]        Subject:     [TN] VIAS PLATED CLOSED
                    >


                    01/11/02 05:55
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Good day technet:

We're considering designing a multilayer polyimide PWB with a number of
vias
(approximately .021" diameter holes, .062" thick PWB) that are plated shut,
for thermal reasons.  Can anyone comment on pitfalls regarding the fab
process?  How about voids in the solid copper via?  Entrapped plating
solution?

All comments are appreciated.  Thanks in advance...

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Fri, 11 Jan 2002 10:38:11 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

To expand slightly on Don's comments, I would find out about the plugging
process and quiz your fab shop about its  capability to do it first. Some
shops are much better than others.

The finish is not universally flat, though not bad. I don't recommend it
for BGA via in pad designs, as the plugged finish looks and is slightly
pitted. Hole aspect ratios that can be filled should not exceed 1:6, though
fab shops that do this process are often more comfortable at 1:4. At the
other end of the range, I sucessfully had 24 mils diameter holes filled
that was only 7 mils deep (aspect ratio of 7:2). Dupont's CB100 is what I
specify, "or similar".

Peter




                    Don Vischulis
                    <dvischulis@W        To:     [log in to unmask]
                    I.RR.COM>            cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:             Aero/ST Group)
                    TechNet              Subject:     Re: [TN] VIAS PLATED CLOSED
                    <[log in to unmask]
                    ORG>


                    01/11/02
                    06:18 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum."






Jim

IMO you should avoid true plated shut vias.  As holes plate in an
electrolytic process, the outer portion of the hole plates faster than the
portion of the barrel that is near the center of board (dog bone plating).
This can result in trapped chemicals in the barrel of the hole.  As an
alternative you might consider plugging the holes with a conductive epoxy
such as DuPont's CB100.  A .021 dia hole in a .062 thick board is within
the
capability of several board shops.  You will most likely find this
capability with shops that build high reliability products.

The holes are plugged before the final finish is applied, and they should
provide a flat final surface on the finished board.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Thursday, January 10, 2002 3:55 PM
To: [log in to unmask]
Subject: [TN] VIAS PLATED CLOSED


Good day technet:

We're considering designing a multilayer polyimide PWB with a number of
vias
(approximately .021" diameter holes, .062" thick PWB) that are plated shut,
for thermal reasons.  Can anyone comment on pitfalls regarding the fab
process?  How about voids in the solid copper via?  Entrapped plating
solution?

All comments are appreciated.  Thanks in advance...

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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=========================================================================
Date:         Fri, 11 Jan 2002 02:18:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Neil Flatter <[log in to unmask]>
Subject:      Lead Free Soldering
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

What sorts of options are there for the flux?  Anything I've read either =
uses zinc chloride or simply skirts the issue.  I'm trying to get some =
idea of the contamination to expect on finished assemblies.

Neil Flatter
Process Quality
TRW Automotive

>>> [log in to unmask] 01/11/02 12:00AM >>>
Date:    Thu, 10 Jan 2002 15:43:41 -0500
From:    Gary Bremer <[log in to unmask]>
Subject: Lead Free Soldering

I am looking at moving my soldering process to use leadfree solder
sometime this year.  Has anyone already shifted over to using
leadfree solder?  What type of problems would I expect to
encounter with using a leadfree solder?  The solder material that
NEMI is suggesting is SnAgCu, is this going to pose any real
problems because the temperature is at 217=3DB0 Celsius with the
laminate material or what components are selected?  Will I be
forced to change the finish on the bare board from HASL?  Any help
or suggestions I get will be greatly appriciated.

Gary Bremer,
Manufacturing Engineer

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Date:         Fri, 11 Jan 2002 08:28:42 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Diamond, Pat" <[log in to unmask]>
Subject:      Anodised Aluminium wire
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I am looking for information on a supplier for anodised aluminium wire, the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Fri, 11 Jan 2002 07:09:54 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi, Peter, thanks for the response.

Let me try to explain further.  We're using ceramic leadless chip carriers
which give off a lot of heat.  In an effort to dissipate the heat to the
ground planes, we're placing thermal vias underneath.  We wanted the thermal
vias to be plated closed, resulting in a solid plug of copper, which we then
can deposit solder paste on top which would contact the bottom of the
ceramic package.  The heat path would be from the component through the
solder bumps on the thermal vias through the solid copper via.  Our board
supplier claims that he can plate the vias closed, but when I asked about
voids and entrapped plating chemicals, he said he was never asked that
before and would have to look into it.  I'm getting concerned with this
design, thinking that an epoxy-filled via which is plated over on top would
be better.  I now need recommendations for a THERMALLY conductive adhesive,
it doesn't have to be electrically conductive but I don't really care.

Thanks again,

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   <Peter George Duncan> [SMTP:[log in to unmask]]
        Sent:   Thursday, January 10, 2002 9:28 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        Hi, James,

        I'm trying to picture your "thermal reasons" and how plating over
the holes
        will help, reliably. I haven't encountered a process for plating
over
        holes, and 21 mils seems quite a canyon to bridge. I'ld be very
interested
        to know how this is done.

        I'm very involved with conduction-cooled MLB's 60 mils thk, that
require a
        lot of thermal management. 'Thermal' via holes are punched through
the
        board and plated to internal thermal planes. To improve the
conductive
        cross-sectional area of these holes, I had them filled with
silver-loaded
        epoxy, which was then Cu-plated over. This process also served the
        secondary purpose of filling holes that otherwise, as you suggest,
would
        contain entrapped plating solutions.

        Depending on your substrate material and operating environment, I
could
        imagine a plated 'cap' splitting over time through temp cycling and
        mechanical stresses, assuming it survives the hot assembly processes
with
        the expansion of entrapped gasses. Not serious, thermally, perhaps,
but it
        would allow the outside atmosphere to circulate inside the holes as
well,
        which might not be so good inteh long run.

        Peter




                            "Marsico, James"
                            <James.Marsico@D        To:     [log in to unmask]
                            P.AIL.COM>              cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                            Sent by: TechNet        Aero/ST Group)
                            <[log in to unmask]        Subject:     [TN] VIAS
PLATED CLOSED
                            >


                            01/11/02 05:55
                            AM
                            Please respond
                            to "TechNet
                            E-Mail Forum."






        Good day technet:

        We're considering designing a multilayer polyimide PWB with a number
of
        vias
        (approximately .021" diameter holes, .062" thick PWB) that are
plated shut,
        for thermal reasons.  Can anyone comment on pitfalls regarding the
fab
        process?  How about voids in the solid copper via?  Entrapped
plating
        solution?

        All comments are appreciated.  Thanks in advance...

        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879


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Date:         Fri, 11 Jan 2002 07:30:17 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Creswick, Steven" <[log in to unmask]>
Subject:      Re: Anodised Aluminium wire
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Pat,

I have never attempted to use anodized aluminum wire before, but have
frequently used PURE 1.25 - 20 mil diameter aluminum wire for wire bonding
in automotive and power applications.

You can try the following three sites.  I KNOW they can provide the wire
diameter you want, but it may be too pure for your needs.  Normal wire
bonding wire is very pure, and hence, very soft.

What I DO NOT know, is if they will anodize it for you.  I rather doubt it,
but then it is worth a phone call.

May I be inquisitive and ask why one would use anodized aluminum wire of
this diameter??



http://www.semx.com/companies/spm.asp   - SPM

http://www.williams-adv.com/   - Williams

http://www.kulickeandsoffa.com/  - American Fine Wire


Best of luck,

Steven Creswick - Gentex Corp



-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 3:29 AM
To: [log in to unmask]
Subject: [TN] Anodised Aluminium wire


I am looking for information on a supplier for anodised aluminium wire, the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Fri, 11 Jan 2002 07:37:22 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_9.2186c688.29703682_boundary"

--part1_9.2186c688.29703682_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Jim!

Have you looked into using Stablcor as the substrate for your assembly to
dissipate heat? We're looking into using this, it transfers heat at a rate
1000 times faster than FR4 material. Go to:

http://www.thermalworks.com

-Steve Gregory-

 Peter, thanks for the response.
>
>
> Let me try to explain further.  We're using ceramic leadless chip carriers
> which give off a lot of heat.  In an effort to dissipate the heat to the
> ground planes, we're placing thermal vias underneath.  We wanted the
> thermal
> vias to be plated closed, resulting in a solid plug of copper, which we
> then
> can deposit solder paste on top which would contact the bottom of the
> ceramic package.  The heat path would be from the component through the
> solder bumps on the thermal vias through the solid copper via.  Our board
> supplier claims that he can plate the vias closed, but when I asked about
> voids and entrapped plating chemicals, he said he was never asked that
> before and would have to look into it.  I'm getting concerned with this
> design, thinking that an epoxy-filled via which is plated over on top would
> be better.  I now need recommendations for a THERMALLY conductive adhesive,
> it doesn't have to be electrically conductive but I don't really care.
>
> Thanks again,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>




--part1_9.2186c688.29703682_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Jim!<BR>
<BR>
Have you looked into using Stablcor as the substrate for your assembly to dissipate heat? We're looking into using this, it transfers heat at a rate 1000 times faster than FR4 material. Go to:<BR>
<BR>
http://www.thermalworks.com<BR>
<BR>
-Steve Gregory-</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"> Peter, thanks for the response.</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><BR>
<BR>
Let me try to explain further.&nbsp; We're using ceramic leadless chip carriers<BR>
which give off a lot of heat.&nbsp; In an effort to dissipate the heat to the<BR>
ground planes, we're placing thermal vias underneath.&nbsp; We wanted the thermal<BR>
vias to be plated closed, resulting in a solid plug of copper, which we then<BR>
can deposit solder paste on top which would contact the bottom of the<BR>
ceramic package.&nbsp; The heat path would be from the component through the<BR>
solder bumps on the thermal vias through the solid copper via.&nbsp; Our board<BR>
supplier claims that he can plate the vias closed, but when I asked about<BR>
voids and entrapped plating chemicals, he said he was never asked that<BR>
before and would have to look into it.&nbsp; I'm getting concerned with this<BR>
design, thinking that an epoxy-filled via which is plated over on top would<BR>
be better.&nbsp; I now need recommendations for a THERMALLY conductive adhesive,<BR>
it doesn't have to be electrically conductive but I don't really care.<BR>
<BR>
Thanks again,<BR>
<BR>
Jim Marsico<BR>
Senior Engineer<BR>
Production Engineering<BR>
EDO Electronics Systems Group<BR>
[log in to unmask] &lt;mailto:[log in to unmask]&gt;<BR>
631-595-5879<BR>
</BLOCKQUOTE><BR>
<BR>
<BR>
<BR>
</FONT></HTML>
--part1_9.2186c688.29703682_boundary--

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Date:         Fri, 11 Jan 2002 08:03:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      virus
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I just received an anti-virus report claiming that the e-mail from MR. TONG
with the subject "Re: [TN] Staking compounds" contains an attachment with a
virus.  Please be advised accordingly.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Fri, 11 Jan 2002 08:05:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Steve, I can't seem to access http://www.thermalworks.com
<http://www.thermalworks.com> .  Is the address correct?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   Stephen Gregory [SMTP:[log in to unmask]]
        Sent:   Friday, January 11, 2002 7:37 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        Hi Jim!

        Have you looked into using Stablcor as the substrate for your
assembly to dissipate heat? We're looking into using this, it transfers heat
at a rate 1000 times faster than FR4 material. Go to:

        http://www.thermalworks.com

        -Steve Gregory-

        Peter, thanks for the response.




                Let me try to explain further.  We're using ceramic leadless
chip carriers
                which give off a lot of heat.  In an effort to dissipate the
heat to the
                ground planes, we're placing thermal vias underneath.  We
wanted the thermal
                vias to be plated closed, resulting in a solid plug of
copper, which we then
                can deposit solder paste on top which would contact the
bottom of the
                ceramic package.  The heat path would be from the component
through the
                solder bumps on the thermal vias through the solid copper
via.  Our board
                supplier claims that he can plate the vias closed, but when
I asked about
                voids and entrapped plating chemicals, he said he was never
asked that
                before and would have to look into it.  I'm getting
concerned with this
                design, thinking that an epoxy-filled via which is plated
over on top would
                be better.  I now need recommendations for a THERMALLY
conductive adhesive,
                it doesn't have to be electrically conductive but I don't
really care.

                Thanks again,

                Jim Marsico
                Senior Engineer
                Production Engineering
                EDO Electronics Systems Group
                [log in to unmask] <mailto:[log in to unmask]>
                631-595-5879







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Date:         Fri, 11 Jan 2002 08:12:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject:      Re: virus
X-cc:         "DesignerCouncil (E-mail)" <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"

Our Trend Anti-virus reported a similar problem with "RE: RE:[DC]AutoCad
Dimensioning - Message(HTML)" from MR.TONG. The Attachment is reported as
[Filename: HAMSTER.DOC.pif, Content-Type: audio/x-wav].

Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]



-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 8:03 AM
To: [log in to unmask]
Subject: [TN] virus


I just received an anti-virus report claiming that the e-mail from MR. TONG
with the subject "Re: [TN] Staking compounds" contains an attachment with a
virus.  Please be advised accordingly.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Fri, 11 Jan 2002 14:18:39 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Busko, Wolfgang" <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

The subject of this mail is different for each individual that=B4s =
getting
mail from this friendly MR.TONG. Seems that it knows about the =
individual
subjects one has used for this forum.

Wolfgang

> -----Original Message-----
> From: Marsico, James [mailto:[log in to unmask]]
> Sent: Friday, January 11, 2002 2:03 PM
> To: [log in to unmask]
> Subject: [TN] virus
>=20
>=20
> I just received an anti-virus report claiming that the e-mail=20
> from MR. TONG
> with the subject "Re: [TN] Staking compounds" contains an=20
> attachment with a
> virus.  Please be advised accordingly.
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>=20
> --------------------------------------------------------------
> -------------------
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> --------------------------------------------------------------
> -------------------
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Date:         Fri, 11 Jan 2002 08:48:55 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Dupont LG1000
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Michael,

I say contact Dupont direct.  http://www.dupont.com/fcm/

Product Information
1-800-441-7515

I did find an MSDS link with Pyralux LG in it
http://www.dupont.com/msds/60_65_cww00029.html
Didn't find anything with product info though.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468



-----Original Message-----
From: Mcmaster, Michael [mailto:[log in to unmask]]
Sent: Thursday, January 10, 2002 6:29 PM
To: [log in to unmask]
Subject: [TN] Dupont LG1000


I'm looking for info about a material (prepreg) called LG1000 from DuPont.
I'm not finding anything on their webpage, on dogpile or in the archives.
Can anybody provide a lead?

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Date:         Fri, 11 Jan 2002 14:49:45 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Lead Free Soldering
Mime-Version: 1.0
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Gary

In our project LEADFREE we made our first production trials. Just some =
statements about what we found. The tests where intended to get our feet =
wet much more work has to be done and a lot has been done in the IDEALS =
project and in the NCMS project:
Drawbacks:
- No complex boards, no large BGA's on SMT, no real heavy components (SMT =
and wave)
- only test boards
- No mass production just 3-10 PCB's

Materials
- Boards: standard FR4, 2 inner layers completely plated with copper
- Components SMT. Plating: whatever was available on the market, whenever =
possible the same component leadfree and with tin lead :=20
SO 014
SO 016
SO 020
SOT 23
C1206
C0603
C0805
- Components wave
C1812
C0603
R0603
R0402
MELF0204
MELF0102
TO 220
Elco axial
Connector V96
Resistor axial 2W

- Board finishes
NiAu
Immersion tin
SnPb HAL

- Solder
SnPbAg
SnCuAg
SnAg
SnZn ( only reflow)
Solder pastes of the same alloy from various suppliers where used.

- Results Reflow
Equipment: Full convection reflow
A quick and dirty approach with using a standard profile for SnPbAg and =
rising the peak temperature to 233=B0C gave excellent solder joints with =
all alloys on all surfaces. The influence of the flux composition was more =
significant than the one from the alloy on a given surface.

- Results Wave
Equipment: Double wave, preheating IR plus convection, fully closed N2 =
system, nozzle geometry adapted to lead free solder.
Preheating: Top of PCB 118=B0C, TO220 Package 92.2=B0C
Flux: Synthetic flux ( no composition available)
Conveyor speed: 1m/min.
Solderpot temperature: Test Tmax=3D 255=B0C; Test Tmin=3D245=B0C
Soldering with a solderpot temperature of 245=B0C gave perfect solder =
joints. Even under air. Earlier trials with 280=B0C gave very poor =
results.
Trials with table top wave solder equipment gave "icicles" and shorts even =
with 280=B0C. Which makes sense, since the thermal energy in a small pot =
is much smaller than in a big one a fact that is more important with lead =
free solders than with SnPb. We will have to confirm these results with a =
complex PCB. The problem is to find a sponsor that supplies us with a =
large THT board that is a challenge to solder since such a thing tents to =
be quite expensive.

- Problems to come
Reflow equipment doesn't like the temperatures needed for lead free =
solder. Even 240=B0C seems to be too much and wear out has to be expected.
Tin is a good solvent. Thus all parts made of stainless steel that are in =
contact wit liquid tin erode. There is equipment available suited for lead =
free solder.
When using VOC free flux in wave soldering the preaheating of the PCB's =
becomes a problem to get the water out of the flux. Convection is =
rcommended.
Dross formation and its costs ( better with N2)
Higher process temperatures migt be necessary in reflow with large =
components. I have no experience so far.
Reliability has the potential to become a problem. Our slow thermal =
cycling tests show a tendency of faster degradation of lead free solder =
compared to Tin Lead.


I hope this helps a bit.


Best regards

Guenter

.



EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Fri, 11 Jan 2002 09:01:16 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_d6.10851810.29704a2c_boundary"

--part1_d6.10851810.29704a2c_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Jim!

Yep...just tried it again myself, got there no problem..

-Steve Gregory-


> Steve, I can't seem to access http://www.thermalworks.com
> <http://www.thermalworks.com> .  Is the address correct?
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>



--part1_d6.10851810.29704a2c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Jim!
<BR>
<BR>Yep...just tried it again myself, got there no problem..
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve, I can't seem to access http://www.thermalworks.com
<BR>&lt;http://www.thermalworks.com&gt; . &nbsp;Is the address correct?
<BR>Jim Marsico
<BR>Senior Engineer
<BR>Production Engineering
<BR>EDO Electronics Systems Group
<BR>[log in to unmask] &lt;mailto:[log in to unmask]&gt;
<BR>631-595-5879
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_d6.10851810.29704a2c_boundary--

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Date:         Fri, 11 Jan 2002 09:02:14 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: Anodised Aluminium wire
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Pat,

Not knowing what your end use is, I am intrigued by anodized aluminum =
wire.  Anodizing, by definition, is an insulator. I would understand =
irridite as a coating for aluminum.

How would this be used, terminated, etc.?

Phil Nutting

-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 3:29 AM
To: [log in to unmask]
Subject: [TN] Anodised Aluminium wire


I am looking for information on a supplier for anodised aluminium wire, =
the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Fri, 11 Jan 2002 09:12:15 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_38.21630f9e.29704cbf_boundary"

--part1_38.21630f9e.29704cbf_boundary
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Content-Transfer-Encoding: quoted-printable

I got it too, the subject was Re: Re: [TN] Lead Free Soldering =20

This is the W32/Badtrans@MM virus, VERY nasty virus!!=20

Once running, the trojan attempts to mail the victim's IP Address to the=20
author. Once this information is obtained, the author can connect to the=20
infected system via the Internet and steal personal information such as=20
usernames, and passwords. In addition, the trojan also contains a keylogger=20
program which is capable of capturing other vital information such as credit=
=20
card and bank account numbers and passwords.=20

-Steve Gregory-=20
   =20
   =20
   =20
   =20
   =20
   =20
   =20
   =20
   =20



> The subject of this mail is different for each individual that=B4s getting
> mail from this friendly MR.TONG. Seems that it knows about the individual
> subjects one has used for this forum.
>=20
> Wolfgang
>=20




--part1_38.21630f9e.29704cbf_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

<HTML><FONT FACE=3Darial,helvetica><FONT  SIZE=3D2>I got it too, the subject=
 was <B>Re: Re: [TN] Lead Free Soldering</B> =20
<BR>
<BR>This is the <B>W32/Badtrans@MM </B>virus, VERY nasty virus!!=20
<BR>
<BR>Once running, the trojan attempts to mail the victim's IP Address to the=
 author. Once this information is obtained, the author can connect to the in=
fected system via the Internet and steal personal information such as userna=
mes, and passwords. In addition, the trojan also contains a keylogger progra=
m which is capable of capturing other vital information such as credit card=20=
and bank account numbers and passwords.=20
<BR>
<BR>-Steve Gregory-=20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>   =20
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">The subject of this mail is=
 different for each individual that=B4s getting
<BR>mail from this friendly MR.TONG. Seems that it knows about the individua=
l
<BR>subjects one has used for this forum.
<BR>
<BR>Wolfgang
<BR></FONT><FONT  COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR>
<BR></FONT></HTML>

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Date:         Fri, 11 Jan 2002 17:07:22 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Steve

This virus works ONLY if you use a Microsoft e-mail client. What I don't
understand is that I've not received any messages from this Mr. Tong. I
thought that all attachments were stripped by the ListServer before the
messages are transmitted.

Brian

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Date:         Fri, 11 Jan 2002 09:53:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: virus
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_FFA2F19E.2948251A"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_FFA2F19E.2948251A
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

I received one this morning with a re: thermal paper.  I don't use =
microsoft and my virus detection found nothing wrong with the email.  I =
was precautious and deleted it and emptied my trash bin right away.=20

Kathy=20

--=_FFA2F19E.2948251A
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I received one this morning with a re: thermal paper.&nbsp; I don't use
microsoft and my virus detection found nothing wrong with the email.&nbsp; I was
precautious and deleted it and emptied my trash bin right away.&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

--=_FFA2F19E.2948251A--

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Date:         Fri, 11 Jan 2002 12:08:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Seeger <[log in to unmask]>
Organization: Applied CAD Knowledge Inc
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

"Busko, Wolfgang" wrote:
>
> The subject of this mail is different for each individual that´s getting
> mail from this friendly MR.TONG. Seems that it knows about the individual
> subjects one has used for this forum.
>
        ...laughing uncontrollably...

        I received a message from Mr Tong, apparently a reply to
        my rant early in the week on the topic of Microsoft.  The
        message was blank.  I wrote back to Mr Tong apologizing
        that I could not read his message, assuming it was some
        offline defense for Microsoft.

        I asked him if perhaps I should be reading it on a PC?

        ...OOPS fell off chair...

        But I still will apologize for my inappropriate rant.

        Happy Friday,
--

      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

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Date:         Fri, 11 Jan 2002 13:13:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Altera Flex BGA
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

We got a board in here for evaluation with an Altera FPGA in a Flex BGA
package. The package is doing a good impersonation of a potato chip. Any
chance it would flaten back out if I took it off and reballed it?

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Date:         Fri, 11 Jan 2002 12:09:52 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Solder Balls on Wave Solder
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Technetters,

        My company is having a solder ball problem on the wave solder. The
issue is primarily caused by overly large un-masked  vias on both sides. The
via diameter is 25 mils with an annular ring of 25 mils on a .062"  board.
On the wave solder process, the flux gets entrapped inside the vias and no
matter what we do on the pre-heating section there still flux remaining
inside that causes the solder to explode into tiny solder balls when it gets
to the laminar section of the wave, like a volcano effect on the component
side. These boards have also a good amount of the same vias under fine pitch
QFP devices , this narrows our process window  if we want to heat the board
even more. Heating the board more on the preheaters to resolve the solder
ball problem leads on re-reflowing of the leads of those devices and quality
problems as a result of that, the QFP pins pop up and become un-soldered.
The customer does not want to use smaller vias or get them masked off since
vias are used for test and rework purposes, they want to be able to insert
wires inside the vias in case they need to change the board configuration.
Any ideas on what to do with the wave process to resolve this issue?


        Any ideas would be greatly appreciated.



Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Fri, 11 Jan 2002 14:32:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: Solder Balls on Wave Solder
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

 I'm guessing VOC free and foam fluxer. An alcohol based flux should not be
doing this to you.

Does your machine have and air knife? Try changing the angle of the knife,
pressure and/or volume of air.

What kind of preheater? IR?

You might consider the aggressive approach of adding a home-made manifold in
the preheat zones to stir the air. Copper pipe, drill some small holes in
the pipe add an air flow regulator and you can augment the preheat action
with a little convection.




> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jorge Rodriguez
> Sent: Friday, January 11, 2002 2:10 PM
> To: [log in to unmask]
> Subject: [TN] Solder Balls on Wave Solder
>
>
> Technetters,
>
>         My company is having a solder ball problem on the wave solder. The
> issue is primarily caused by overly large un-masked  vias on both
> sides. The
> via diameter is 25 mils with an annular ring of 25 mils on a .062"  board.
> On the wave solder process, the flux gets entrapped inside the vias and no
> matter what we do on the pre-heating section there still flux remaining
> inside that causes the solder to explode into tiny solder balls
> when it gets
> to the laminar section of the wave, like a volcano effect on the component
> side. These boards have also a good amount of the same vias under
> fine pitch
> QFP devices , this narrows our process window  if we want to heat
> the board
> even more. Heating the board more on the preheaters to resolve the solder
> ball problem leads on re-reflowing of the leads of those devices
> and quality
> problems as a result of that, the QFP pins pop up and become un-soldered.
> The customer does not want to use smaller vias or get them masked
> off since
> vias are used for test and rework purposes, they want to be able to insert
> wires inside the vias in case they need to change the board configuration.
> Any ideas on what to do with the wave process to resolve this issue?
>
>
>         Any ideas would be greatly appreciated.
>
>
>
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> 615 South River Drive
> Tempe, AZ 85281
> Phone: (480) 968-6790 X 4258
> Fax: (480) 829-4000
> E-mail: [log in to unmask]
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Search previous postings at: www.ipc.org > On-Line Resources &
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Fri, 11 Jan 2002 14:42:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hello all,

I cannot believe that this sort of thing got sent to me through the =
IPC. So,
my question is, how and why this happened?

If these kind of things cannot be filtered out, then membership to any =
IPC
email forum might be a bad idea.

So, what's the story?

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Stephen Gregory [SMTP:[log in to unmask]]
> Sent: Friday, January 11, 2002 9:12 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] virus
>=20
> I got it too, the subject was Re: Re: [TN] Lead Free Soldering=20
>=20
> This is the W32/Badtrans@MM virus, VERY nasty virus!!=20
>=20
> Once running, the trojan attempts to mail the victim's IP Address to =
the
> author. Once this information is obtained, the author can connect to =
the
> infected system via the Internet and steal personal information such =
as
> usernames, and passwords. In addition, the trojan also contains a
> keylogger program which is capable of capturing other vital =
information
> such as credit card and bank account numbers and passwords.=20
>=20
> -Steve Gregory-=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>       The subject of this mail is different for each individual that=B4s
> getting=20
>       mail from this friendly MR.TONG. Seems that it knows about the
> individual=20
>       subjects one has used for this forum.=20
> =09
>       Wolfgang=20
> =09
>=20
>=20
>=20
>=20
>=20

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=========================================================================
Date:         Fri, 11 Jan 2002 14:37:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Olinger, Patty" <[log in to unmask]>
Subject:      Re: Solder Balls on Wave Solder
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Jorge,
Why don't you try a water soluble masking on the via's? That is what we
do and it works for us. After cleaning, the holes are ready for test.
The Masking is: Wondermask by Techspray P/N 2204-8SQ. Yes, this adds one
more step to the process but saves a lot of touchup later. I hope this
info is of value.

Patty Olinger=20
Manufacturing Engineer
Projects Unlimited
(937)918-2267
[log in to unmask]


-----Original Message-----
From: Jorge Rodriguez [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 2:10 PM
To: [log in to unmask]
Subject: [TN] Solder Balls on Wave Solder


Technetters,

        My company is having a solder ball problem on the wave solder.
The
issue is primarily caused by overly large un-masked  vias on both sides.
The
via diameter is 25 mils with an annular ring of 25 mils on a .062"
board.
On the wave solder process, the flux gets entrapped inside the vias and
no
matter what we do on the pre-heating section there still flux remaining
inside that causes the solder to explode into tiny solder balls when it
gets
to the laminar section of the wave, like a volcano effect on the
component
side. These boards have also a good amount of the same vias under fine
pitch
QFP devices , this narrows our process window  if we want to heat the
board
even more. Heating the board more on the preheaters to resolve the
solder
ball problem leads on re-reflowing of the leads of those devices and
quality
problems as a result of that, the QFP pins pop up and become
un-soldered.
The customer does not want to use smaller vias or get them masked off
since
vias are used for test and rework purposes, they want to be able to
insert
wires inside the vias in case they need to change the board
configuration.
Any ideas on what to do with the wave process to resolve this issue?


        Any ideas would be greatly appreciated.



Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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=========================================================================
Date:         Fri, 11 Jan 2002 13:59:17 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: virus
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

Bill

I haven't received any of these emails, and I'm subscribed to three of the
IPC forums.  I suggest you take a close look at the header information on
the email.  My suspicion is that it didn't come through technet.  Rather it
has a subject line that looks like a technet posting.  The only attachments
I currently receive with technet postings are Kathy's business card
attachment.

I also didn't participate in the recent Microsoft Moment thread - mainly
because I was having one myself.  An upgrade went bad and I had to rebuild
the hard drive structure.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kasprzak, Bill (sys)
USX
Sent: Friday, January 11, 2002 1:42 PM
To: [log in to unmask]
Subject: Re: [TN] virus


Hello all,

I cannot believe that this sort of thing got sent to me through the IPC. So,
my question is, how and why this happened?

If these kind of things cannot be filtered out, then membership to any IPC
email forum might be a bad idea.

So, what's the story?

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Stephen Gregory [SMTP:[log in to unmask]]
> Sent: Friday, January 11, 2002 9:12 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] virus
>
> I got it too, the subject was Re: Re: [TN] Lead Free Soldering
>
> This is the W32/Badtrans@MM virus, VERY nasty virus!!
>
> Once running, the trojan attempts to mail the victim's IP Address to the
> author. Once this information is obtained, the author can connect to the
> infected system via the Internet and steal personal information such as
> usernames, and passwords. In addition, the trojan also contains a
> keylogger program which is capable of capturing other vital information
> such as credit card and bank account numbers and passwords.
>
> -Steve Gregory-
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>       The subject of this mail is different for each individual that´s
> getting
>       mail from this friendly MR.TONG. Seems that it knows about the
> individual
>       subjects one has used for this forum.
>
>       Wolfgang
>
>
>
>
>
>

----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date:         Fri, 11 Jan 2002 14:56:07 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject:      Re: virus
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
Content-transfer-encoding: quoted-printable

All-

The mailing I received was direct, *NOT* through the IPC forum. This =
virus
is one of the new breed of "smart" worms capable of picking off email
addresses from the message header. It is nasty and virulent, but =
fortunately
well known and defended by most of the major Anti-Virus softwares out
(McAffe, Trend, Norton, etc.) with the most recent pattern files =
loaded.  =20

Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]



-----Original Message-----
From: Kasprzak, Bill (sys) USX [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 2:42 PM
To: [log in to unmask]
Subject: Re: [TN] virus


Hello all,

I cannot believe that this sort of thing got sent to me through the =
IPC. So,
my question is, how and why this happened?

If these kind of things cannot be filtered out, then membership to any =
IPC
email forum might be a bad idea.

So, what's the story?

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Stephen Gregory [SMTP:[log in to unmask]]
> Sent: Friday, January 11, 2002 9:12 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] virus
>=20
> I got it too, the subject was Re: Re: [TN] Lead Free Soldering=20
>=20
> This is the W32/Badtrans@MM virus, VERY nasty virus!!=20
>=20
> Once running, the trojan attempts to mail the victim's IP Address to =
the
> author. Once this information is obtained, the author can connect to =
the
> infected system via the Internet and steal personal information such =
as
> usernames, and passwords. In addition, the trojan also contains a
> keylogger program which is capable of capturing other vital =
information
> such as credit card and bank account numbers and passwords.=20
>=20
> -Steve Gregory-=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>=20
>       The subject of this mail is different for each individual =
that=B4s
> getting=20
>       mail from this friendly MR.TONG. Seems that it knows about the
> individual=20
>       subjects one has used for this forum.=20
> =09
>       Wolfgang=20
> =09
>=20
>=20
>=20
>=20
>=20

------------------------------------------------------------------------=
----
-----
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text =
in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]: SET
Technet NOMAIL
To recieve ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & =
Databases >
E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700
ext.5315
------------------------------------------------------------------------=
----
-----

---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date:         Fri, 11 Jan 2002 15:01:00 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_69.205df078.29709e7c_boundary"

--part1_69.205df078.29709e7c_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Bill!

My email that I got didn't go through the server, it came directly from Mr.
Tong's computer. He obviously is a TechNet member, and that's where the virus
got everybodies email addresses. Mr. Tong probably has no idea that his
computer is infected.

This internet worm is very insidious, it looks on your computer to find email
addresses to send itself to.

-Steve Gregory-

> Hello all,
>
> I cannot believe that this sort of thing got sent to me through the IPC. So,
> my question is, how and why this happened?
>
> If these kind of things cannot be filtered out, then membership to any IPC
> email forum might be a bad idea.
>
> So, what's the story?
>
> Bill Kasprzak
> Moog Inc.
>



--part1_69.205df078.29709e7c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Bill!
<BR>
<BR>My email that I got didn't go through the server, it came directly from Mr. Tong's computer. He obviously is a TechNet member, and that's where the virus got everybodies email addresses. Mr. Tong probably has no idea that his computer is infected.
<BR>
<BR>This internet worm is very insidious, it looks on your computer to find email addresses to send itself to.
<BR>
<BR>-Steve Gregory-
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello all,
<BR>
<BR>I cannot believe that this sort of thing got sent to me through the IPC. So,
<BR>my question is, how and why this happened?
<BR>
<BR>If these kind of things cannot be filtered out, then membership to any IPC
<BR>email forum might be a bad idea.
<BR>
<BR>So, what's the story?
<BR>
<BR>Bill Kasprzak
<BR>Moog Inc.
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_69.205df078.29709e7c_boundary--

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---------------------------------------------------------------------------------
=========================================================================
Date:         Fri, 11 Jan 2002 12:01:03 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I think it's because the e-mail it didn't come through Technet but =
directly
from Mr Tong.  I have my e-mail program setup to siphon off all Technet =
mail
into a separate folder, then read it when I have time.  The virus =
containing
e-mail was not in my Technet inbox but my regular one, as if the sender =
was
replying off-line. The subject line was also different which means we
received different e-mails not copies of the same one.

I know I've noticed a change recently when replying to Technet =
postings.  It
used to be that when you replied the address line would include both =
Technet
and the original sender.  That's no longer the case.  Now only Technet =
shows
up.  While this is a little inconvenient if you wanted to do an =
off-line
reply (all you had to do was delete the technet address) I suspect this
change was made for exactly this reason.  I'm willing to bet that those =
of
us who received the virus posted to Technet on the relevant topic prior =
to
the change.  That's the only way I can see for the insidious Mr. Tong =
(man,
is that a name out of a James Bond movie or what) to get all of our =
e-mail
addresses. =20

Maybe Keach can enlighten us?

> ----------
> From:         Kasprzak, Bill (sys) USX[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Friday, January 11, 2002 11:42 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] virus
>=20
> Hello all,
>=20
> I cannot believe that this sort of thing got sent to me through the =
IPC.
> So,
> my question is, how and why this happened?
>=20
> If these kind of things cannot be filtered out, then membership to =
any IPC
> email forum might be a bad idea.
>=20
> So, what's the story?
>=20
> Bill Kasprzak
> Moog Inc.
>=20
> > -----Original Message-----
> > From: Stephen Gregory [SMTP:[log in to unmask]]
> > Sent: Friday, January 11, 2002 9:12 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] virus
> >=20
> > I got it too, the subject was Re: Re: [TN] Lead Free Soldering=20
> >=20
> > This is the W32/Badtrans@MM virus, VERY nasty virus!!=20
> >=20
> > Once running, the trojan attempts to mail the victim's IP Address =
to the
> > author. Once this information is obtained, the author can connect =
to the
> > infected system via the Internet and steal personal information =
such as
> > usernames, and passwords. In addition, the trojan also contains a
> > keylogger program which is capable of capturing other vital =
information
> > such as credit card and bank account numbers and passwords.=20
> >=20
> > -Steve Gregory-=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >=20
> >       The subject of this mail is different for each individual =
that=B4s
> > getting=20
> >       mail from this friendly MR.TONG. Seems that it knows about =
the
> > individual=20
> >       subjects one has used for this forum.=20
> > =09
> >       Wolfgang=20
> > =09
> >=20
> >=20
> >=20
> >=20
> >=20
>=20
> =
------------------------------------------------------------------------=
--
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d
> To unsubscribe, send a message to [log in to unmask] with following =
text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]:
> SET Technet NOMAIL
> To recieve ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & =
Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700
> ext.5315
> =
------------------------------------------------------------------------=
--
> -------
>=20

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=========================================================================
Date:         Fri, 11 Jan 2002 15:07:31 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Hinton <[log in to unmask]>
Subject:      Solder properties
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_168.6fed2ed.2970a003_boundary"

--part1_168.6fed2ed.2970a003_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Could anyone give me the properties of a solder, Ostaloy 428 (ie) MP,
Solidus, liquidus, composition.

Phil Hinton

--part1_168.6fed2ed.2970a003_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Could anyone give me the properties of a solder, <B>Ostaloy 428 </B>(ie) MP, Solidus, liquidus, composition.
<BR>
<BR>Phil Hinton &nbsp;</FONT></HTML>

--part1_168.6fed2ed.2970a003_boundary--

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=========================================================================
Date:         Fri, 11 Jan 2002 15:33:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hello again,

My apologies to the IPC. But it has to be through this forum that =
Mr.Tong
knows me. I personally have never sent him anything. I guess from now =
on,
any email with an attachment from an unidentifed person will be
automatically deleted!

Thanks for the heads up from all who responded.

Bill Kasprzak=09
Moog Inc.

> -----Original Message-----
> From: Mcmaster, Michael [SMTP:[log in to unmask]]
> Sent: Friday, January 11, 2002 3:01 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] virus
>=20
> I think it's because the e-mail it didn't come through Technet but
> directly
> from Mr Tong.  I have my e-mail program setup to siphon off all =
Technet
> mail
> into a separate folder, then read it when I have time.  The virus
> containing
> e-mail was not in my Technet inbox but my regular one, as if the =
sender
> was
> replying off-line. The subject line was also different which means we
> received different e-mails not copies of the same one.
>=20
> I know I've noticed a change recently when replying to Technet =
postings.
> It
> used to be that when you replied the address line would include both
> Technet
> and the original sender.  That's no longer the case.  Now only =
Technet
> shows
> up.  While this is a little inconvenient if you wanted to do an =
off-line
> reply (all you had to do was delete the technet address) I suspect =
this
> change was made for exactly this reason.  I'm willing to bet that =
those of
> us who received the virus posted to Technet on the relevant topic =
prior to
> the change.  That's the only way I can see for the insidious Mr. Tong
> (man,
> is that a name out of a James Bond movie or what) to get all of our =
e-mail
> addresses. =20
>=20
> Maybe Keach can enlighten us?
>=20
> > ----------
> > From:         Kasprzak, Bill (sys) USX[SMTP:[log in to unmask]]
> > Reply To:     TechNet E-Mail Forum.
> > Sent:         Friday, January 11, 2002 11:42 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] virus
> >=20
> > Hello all,
> >=20
> > I cannot believe that this sort of thing got sent to me through the =
IPC.
> > So,
> > my question is, how and why this happened?
> >=20
> > If these kind of things cannot be filtered out, then membership to =
any
> IPC
> > email forum might be a bad idea.
> >=20
> > So, what's the story?
> >=20
> > Bill Kasprzak
> > Moog Inc.
> >=20
> > > -----Original Message-----
> > > From: Stephen Gregory [SMTP:[log in to unmask]]
> > > Sent: Friday, January 11, 2002 9:12 AM
> > > To:   [log in to unmask]
> > > Subject:      Re: [TN] virus
> > >=20
> > > I got it too, the subject was Re: Re: [TN] Lead Free Soldering=20
> > >=20
> > > This is the W32/Badtrans@MM virus, VERY nasty virus!!=20
> > >=20
> > > Once running, the trojan attempts to mail the victim's IP Address =
to
> the
> > > author. Once this information is obtained, the author can connect =
to
> the
> > > infected system via the Internet and steal personal information =
such
> as
> > > usernames, and passwords. In addition, the trojan also contains a
> > > keylogger program which is capable of capturing other vital
> information
> > > such as credit card and bank account numbers and passwords.=20
> > >=20
> > > -Steve Gregory-=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> > >       The subject of this mail is different for each individual =
that=B4s
> > > getting=20
> > >       mail from this friendly MR.TONG. Seems that it knows about =
the
> > > individual=20
> > >       subjects one has used for this forum.=20
> > > =09
> > >       Wolfgang=20
> > > =09
> > >=20
> > >=20
> > >=20
> > >=20
> > >=20
> >=20
> >
> =
------------------------------------------------------------------------=
--
> > -------
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> > To recieve ONE mailing per day of all the posts: send e-mail to
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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Date:         Fri, 11 Jan 2002 14:47:53 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: Solder properties
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable

Hi Phil! Ostalloy is an alloy designation for the Arconium Specialty Al=
loys
company. But - I can't find any listing for an alloy 428 on my Arconium=

alloy data sheets. You might try contacting Arconium directly
(arconium.com) for information. Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




Phil Hinton <[log in to unmask]>@ipc.org> on 01/11/2002 02:07:31 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] Solder properties


Could anyone give me the properties of a solder, Ostaloy 428 (ie) MP,
Solidus, liquidus, composition.

Phil Hinton

=

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Date:         Fri, 11 Jan 2002 15:56:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brad Saunders <[log in to unmask]>
Subject:      Re: virus
MIME-Version: 1.0
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The virus issue is an awful one and -as Bill states- makes it questionible
future involvment in forums.   The Wall Street Journal states that today time
spent emailing; 49 minutes to 4 hours a day and 1 of 300 emails contain a
virus AND by 2004 it will be 1 in 12.  Ouch!
I recently buried my "ole faithful" PC of a couple of years due to a email
virus that I picked up in the technet.  The address it came from -or that
person- actually sent another email stating it wasn't he.  In any case I
invest my money into anti virus and a cheap PC just for emailing.
To end I don't open emails of folks I don't know and I don't open forum mails
with enclosures. These awful 'puter virus are right up there with "Homeland
Security" issues, and to this end I will continue to be active in the forums.
 I refuse to be minipulated by the data foes and corruptors of things good.

Boston Brad

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Date:         Fri, 11 Jan 2002 15:18:25 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         pratap singh <[log in to unmask]>
Organization: RAMP Inc.
Subject:      Re: Solder Balls on Wave Solder
MIME-version: 1.0
Content-type: multipart/alternative;
              boundary="Boundary_(ID_hrMUd+IIYKjPaDxO2/SsRw)"

--Boundary_(ID_hrMUd+IIYKjPaDxO2/SsRw)
Content-type: text/plain; charset=us-ascii; format=flowed
Content-transfer-encoding: 7BIT

Jorge,

Solder balls at Wave Solder are caused by:

    * Moisture in PCB laminate
    * Poor /Porous copper plating in PTH

When PCB hits wave solder, rise in temperature causes the moisture to
blow off as steam  coming through the PTH copper plating voids. If you
cross section the PTH that shows indication of solder balls, you can
verify the presence of plating voids. You may also cross section as
received PCB to establish PTH quality.

Assembly process changes will have minimal affect on solder balls. Your
PCB supplier has to provide void free copper in PTH to eliminate solder
balls at wave solder.

If it is a few holes per board, you may use Water Soluble Tape to mask
the PTH.. The tape will be cleaned off during warm water rinse section
of cleaning process.

You can contact me off line for use of water soluble tape and technical
requirements for the process if you so wish.




Jorge Rodriguez wrote:

>Technetters,
>
>        My company is having a solder ball problem on the wave solder. The
>issue is primarily caused by overly large un-masked  vias on both sides. The
>via diameter is 25 mils with an annular ring of 25 mils on a .062"  board.
>On the wave solder process, the flux gets entrapped inside the vias and no
>matter what we do on the pre-heating section there still flux remaining
>inside that causes the solder to explode into tiny solder balls when it gets
>to the laminar section of the wave, like a volcano effect on the component
>side. These boards have also a good amount of the same vias under fine pitch
>QFP devices , this narrows our process window  if we want to heat the board
>even more. Heating the board more on the preheaters to resolve the solder
>ball problem leads on re-reflowing of the leads of those devices and quality
>problems as a result of that, the QFP pins pop up and become un-soldered.
>The customer does not want to use smaller vias or get them masked off since
>vias are used for test and rework purposes, they want to be able to insert
>wires inside the vias in case they need to change the board configuration.
>Any ideas on what to do with the wave process to resolve this issue?
>
>
>        Any ideas would be greatly appreciated.
>
>
>
>Jorge Rodriguez
>Process Engineer
>Varian Electronics Manufacturing
>615 South River Drive
>Tempe, AZ 85281
>Phone: (480) 968-6790 X 4258
>Fax: (480) 829-4000
>E-mail: [log in to unmask]
>
>---------------------------------------------------------------------------------
>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
>To unsubscribe, send a message to [log in to unmask] with following text in
>the BODY (NOT the subject field): SIGNOFF Technet
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>Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
>Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
>---------------------------------------------------------------------------------
>

--
_________________________
pratap singh
tel/fax: 512-255-6820
email: [log in to unmask]
WEB: www.rampinc.com



--Boundary_(ID_hrMUd+IIYKjPaDxO2/SsRw)
Content-type: text/html; charset=us-ascii
Content-transfer-encoding: 7BIT

<html>
<head>
</head>
<body>
Jorge,<br>
<br>
Solder balls at Wave Solder are caused by:<br>
<ul>
  <li>Moisture in PCB laminate</li>
  <li>Poor /Porous copper plating in PTH</li>
</ul>
When PCB hits wave solder, rise in temperature causes the moisture to blow
off as steam &nbsp;coming through the PTH copper plating voids. If you cross section
the PTH that shows indication of solder balls, you can verify the presence
of plating voids. You may also cross section as received PCB to establish
PTH quality.<br>
<br>
Assembly process changes will have minimal affect on solder balls. Your PCB
supplier has to provide void free copper in PTH to eliminate solder balls
at wave solder. <br>
<br>
If it is a few holes per board, you may use Water Soluble Tape to mask the
PTH.. The tape will be cleaned off during warm water rinse section of cleaning
process. <br>
<br>
You can contact me off line for use of water soluble tape and technical requirements
for the process if you so wish. <br>
<br>
<br>
<br>
<br>
Jorge Rodriguez wrote:<br>
<blockquote type="cite" cite="mid:[log in to unmask]">
  <pre wrap="">Technetters,<br><br>        My company is having a solder ball problem on the wave solder. The<br>issue is primarily caused by overly large un-masked  vias on both sides. The<br>via diameter is 25 mils with an annular ring of 25 mils on a .062"  board.<br>On the wave solder process, the flux gets entrapped inside the vias and no<br>matter what we do on the pre-heating section there still flux remaining<br>inside that causes the solder to explode into tiny solder balls when it gets<br>to the laminar section of the wave, like a volcano effect on the component<br>side. These boards have also a good amount of the same vias under fine pitch<br>QFP devices , this narrows our process window  if we want to heat the board<br>even more. Heating the board more on the preheaters to resolve the solder<br>ball problem leads on re-reflowing of the leads of those devices and quality<br>problems as a result of that, the QFP pins pop up and become un-soldered.<br>The customer d
oes not want to use smaller vias or get them masked off since<br>vias are used for test and rework purposes, they want to be able to insert<br>wires inside the vias in case they need to change the board configuration.<br>Any ideas on what to do with the wave process to resolve this issue?<br><br><br>        Any ideas would be greatly appreciated.<br><br><br><br>Jorge Rodriguez<br>Process Engineer<br>Varian Electronics Manufacturing<br>615 South River Drive<br>Tempe, AZ 85281<br>Phone: (480) 968-6790 X 4258<br>Fax: (480) 829-4000<br>E-mail: <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a><br><br>---------------------------------------------------------------------------------<br>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d<br>To unsubscribe, send a message to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> with following text in<br>the BODY (NOT t
he subject field): SIGNOFF Technet<br>To temporarily halt delivery of Technet send e-mail to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]:">[log in to unmask]:</a> SET Technet NOMAIL<br>To recieve ONE mailing per day of all the posts: send e-mail to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]:">[log in to unmask]:</a> SET Technet Digest<br>Search previous postings at: <a class="moz-txt-link-abbreviated" href="http://www.ipc.org">www.ipc.org</a> &gt; On-Line Resources &amp; Databases &gt; E-mail Archives<br>Please visit IPC web site (<a class="moz-txt-link-freetext" href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>) for additional<br>information, or contact Keach Sasamori at <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> or 847-509-9700 ext.5315<br>---------------------------------------------------------------------------------<br><br></pre>
  </blockquote>
  <br>
  <pre class="moz-signature" cols="$mailwrapcol">--
_________________________
pratap singh
tel/fax: 512-255-6820
email: <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a>
WEB: <a class="moz-txt-link-abbreviated" href="http://www.rampinc.com">www.rampinc.com</a></pre>
  <br>
  </body>
  </html>

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=========================================================================
Date:         Fri, 11 Jan 2002 16:48:20 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Leo Lambert <[log in to unmask]>
Subject:      Re: Solder properties
In-Reply-To:  <[log in to unmask]>
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Hi Phil, if I remember correctly Arconium Specialty alloys is in Rhode
Island and was bought by Alpha, perhaps if you call Walter Zelop at Alpha he
should be able to help you out.

Till later, Leo Lambert.
EPTAC Corp
[log in to unmask]

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of David Hillman
Sent: Friday, January 11, 2002 3:48 PM
To: [log in to unmask]
Subject: Re: [TN] Solder properties


Hi Phil! Ostalloy is an alloy designation for the Arconium Specialty Alloys
company. But - I can't find any listing for an alloy 428 on my Arconium
alloy data sheets. You might try contacting Arconium directly
(arconium.com) for information. Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




Phil Hinton <[log in to unmask]>@ipc.org> on 01/11/2002 02:07:31 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] Solder properties


Could anyone give me the properties of a solder, Ostaloy 428 (ie) MP,
Solidus, liquidus, composition.

Phil Hinton


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Date:         Fri, 11 Jan 2002 14:11:53 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Patrick Lam <[log in to unmask]>
Subject:      Remove unused "dead" pads on internal layers
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution or
other use is prohibited.  If you received this e-mail in error, please notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Fri, 11 Jan 2002 17:33:46 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
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              boundary="part1_160.6fa979d.2970c24a_boundary"

--part1_160.6fa979d.2970c24a_boundary
Content-Type: text/plain; charset="US-ASCII"
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Hi Pat!

I don't think it's a good idea, we got burned by it once. The internal pads
will provide support during drilling, and will help prevent rough walls
during drilling.

In our case, the unused pads were removed (this was a fairly thick ~.093" or
so polyimide PCB) and plating chemicals were absorbed into the fibers from
the rough drilling. We built the boards, did ICT and a low power functional
test, everything was fine. The boards were shipped to our customer and they
plugged it into their system, powered it up, and then the board died after
about 20-minutes, internal short in the fab. They RMA'd the board back to us,
we sent it out for cross sectioning and found the problem.

Had the used pads put back in and haven't had a problem since.

-Steve Gregory-


> Hi TechNetters,
>
> For class 3 boards, is it acceptable to have unused pads removed on
> interanal
> layers.
>
> Thanks,
> Pat
>



--part1_160.6fa979d.2970c24a_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Pat!
<BR>
<BR>I don't think it's a good idea, we got burned by it once. The internal pads will provide support during drilling, and will help prevent rough walls during drilling.
<BR>
<BR>In our case, the unused pads were removed (this was a fairly thick ~.093" or so polyimide PCB) and plating chemicals were absorbed into the fibers from the rough drilling. We built the boards, did ICT and a low power functional test, everything was fine. The boards were shipped to our customer and they plugged it into their system, powered it up, and then the board died after about 20-minutes, internal short in the fab. They RMA'd the board back to us, we sent it out for cross sectioning and found the problem.
<BR>
<BR>Had the used pads put back in and haven't had a problem since.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi TechNetters,
<BR>
<BR>For class 3 boards, is it acceptable to have unused pads removed on interanal
<BR>layers.
<BR>
<BR>Thanks,
<BR>Pat
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_160.6fa979d.2970c24a_boundary--

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Date:         Fri, 11 Jan 2002 16:33:00 -0600
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>>> [log in to unmask] 01/11/02 03:49PM >>>
CALL FOR PARTICIPATION
IPC and JEDEC bring you the International Conference on Lead-Free =
Electronic Assemblies
April 30, 2002  - Education Courses
May 1-2, 2002 - Technical Conference=20
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IPC - the Association Connecting Electronic Industries and JEDEC - the =
Solid State Technology Association are sponsoring an International =
Conference on Lead-Free Electronic Assemblies. The conference will be held =
April 30 - May 2, 2002 in San Jose, CA.  Mr. Marty Freedman of Molex and =
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The European Union marches closer to establishing a firm date for lead =
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lead continues to grow, especially outside the US.  Japan, Denmark and the =
European Union (EU) are all proposing bans on lead and products containing =
lead.  International OEMs are becoming more sensitive to the issue and =
continue to press their suppliers to develop plans.  A ban in Europe will =
have an effect in the global marketplace, which will force many US =
manufacturers to eliminate lead as effectively as a US ban.

Data is now coming in from individual companies' and consortia efforts.  =
Many challenges still exist and the path forward to success is not one of =
consensus.  Companies need to stay aware of the hot issues remaining in =
order to focus efforts that will allow success to be achieved by 2006/7.

Papers are sought in all areas, including:=20
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To submit an abstract, please complete the second page of this form and =
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Complete and mail, fax or e-mail your biography and abstract to:

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be=20
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solder=20
protectants, immersion tin, silver, electroless nickel, palladium,=20
etc.<BR><BR>The International Lead-Free Conference offers time slots =
between=20
30-45 minutes long. Some papers may be grouped together in a forum or =
panel=20
discussion.<BR><BR>To submit an abstract, please complete the second page =
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rather than a company's product. It is mandatory to provide a print-quality=
=20
paper or hard copies of visuals for the conference proceedings in order =
to=20
deliver an oral presentation. If your paper is accepted, the deadline for =
paper=20
submission is April 7, 2002.<BR><BR>Speakers at the conference will =
receive free=20
admission to the conference, including lunch both days, proceedings, =
and=20
admission to an evening reception on June 12th. The Conference-only =
registration=20
fee is $450 for IPC/JEDEC member companies and $550 for non-members.&nbsp;=
=20
Course-only registration is $295 for members and $395 for=20
non-members.<BR><BR>Complete and mail, fax or e-mail your biography and =
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-=20
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Date:         Fri, 11 Jan 2002 15:01:42 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Patrick Lam <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
Mime-Version: 1.0
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Thanks Steve,

Would 0.010" over the finished hole size be good pad size to be used on internal
layers?

Thanks,
Pat




Stephen Gregory <[log in to unmask]> on 01/11/2002 02:33:46 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Patrick Lam/SEL)
Subject:  Re: [TN] Remove unused "dead" pads on internal layers



Hi Pat!

I don't think it's a good idea, we got burned by it once. The internal pads
will provide support during drilling, and will help prevent rough walls
during drilling.

In our case, the unused pads were removed (this was a fairly thick ~.093" or
so polyimide PCB) and plating chemicals were absorbed into the fibers from
the rough drilling. We built the boards, did ICT and a low power functional
test, everything was fine. The boards were shipped to our customer and they
plugged it into their system, powered it up, and then the board died after
about 20-minutes, internal short in the fab. They RMA'd the board back to us,
we sent it out for cross sectioning and found the problem.

Had the used pads put back in and haven't had a problem since.

-Steve Gregory-


> Hi TechNetters,
>
> For class 3 boards, is it acceptable to have unused pads removed on
> interanal
> layers.
>
> Thanks,
> Pat
>




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This e-mail may contain SEL confidential information.  The opinions expressed
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Date:         Fri, 11 Jan 2002 20:55:40 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
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Hi again Pat,

That sounds okay to me, within the the tolerances that are spec'd out for
drilling, right?

What I can do is look at the gerbers for the board that I was talking about
in my case, and do a quick check to see what the diameter was on those
pads...but can't do that until Monday.

-Steve Gregory-


> Thanks Steve,
>
> Would 0.010" over the finished hole size be good pad size to be used on
> internal
> layers?
>
> Thanks,
> Pat
>


--part1_ac.20ccdc7e.2970f19c_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi again Pat,<BR>
<BR>
That sounds okay to me, within the the tolerances that are spec'd out for drilling, right?<BR>
<BR>
What I can do is look at the gerbers for the board that I was talking about in my case, and do a quick check to see what the diameter was on those pads...but can't do that until Monday.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Thanks Steve,<BR>
<BR>
Would 0.010" over the finished hole size be good pad size to be used on internal<BR>
layers?<BR>
<BR>
Thanks,<BR>
Pat<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date:         Sat, 12 Jan 2002 13:29:50 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      EnviroNet Forum
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I'd like to say to subscribers of the two forums most concerned that the
new EnviroNet list is proving itself as sustainable as the subject it
handles. Some statistics;
In its first week, it has attracted exactly 100 subscribers, which means
that it has probably reached its critical mass
In the same time, there are 13 new threads, some of which are
controversial (granted, I seeded some of them deliberately).
In the same time, 29 messages have been posted.

Want to see them? Go to
http://jefry.ipc.org/SCRIPTS/WA.EXE?A1=ind0201&L=environet

Want to join in? Go to
http://jefry.ipc.org/SCRIPTS/WA.EXE?SUBED1=environet&A=1 or
simply send an e-mail as follows:
TO:          [log in to unmask]
SUBJECT:
MESSAGE:     subscribe EnviroNet <first name> <family name>

This forum is not one with strict formal definitions but you can post
messages concerning anything to do with the environment, sustainability,
health & safety (the worker's environment) etc. Nor is it restricted to
industry-specific subjects, although these are welcome, of course! You
can be as provocative as you like.

See you there, guys and gals, the more the merrier.

Brian

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Date:         Mon, 14 Jan 2002 07:47:46 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
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Hi, James,





                    "Marsico, James"
                    <James.Marsico@D        To:     [log in to unmask]
                    P.AIL.COM>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet        Aero/ST Group)
                    <[log in to unmask]        Subject:     Re: [TN] VIAS PLATED CLOSED
                    >


                    01/11/02 08:09
                    PM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Hi, Peter, thanks for the response.

Let me try to explain further.  We're using ceramic leadless chip carriers
which give off a lot of heat.  In an effort to dissipate the heat to the
ground planes, we're placing thermal vias underneath.  We wanted the
thermal
vias to be plated closed, resulting in a solid plug of copper, which we
then
can deposit solder paste on top which would contact the bottom of the
ceramic package.  The heat path would be from the component through the
solder bumps on the thermal vias through the solid copper via.  Our board
supplier claims that he can plate the vias closed, but when I asked about
voids and entrapped plating chemicals, he said he was never asked that
before and would have to look into it.  I'm getting concerned with this
design, thinking that an epoxy-filled via which is plated over on top would
be better.  I now need recommendations for a THERMALLY conductive adhesive,
it doesn't have to be electrically conductive but I don't really care.

Thanks again,

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   <Peter George Duncan> [SMTP:[log in to unmask]]
        Sent:   Thursday, January 10, 2002 9:28 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        Hi, James,

        I'm trying to picture your "thermal reasons" and how plating over
the holes
        will help, reliably. I haven't encountered a process for plating
over
        holes, and 21 mils seems quite a canyon to bridge. I'ld be very
interested
        to know how this is done.

        I'm very involved with conduction-cooled MLB's 60 mils thk, that
require a
        lot of thermal management. 'Thermal' via holes are punched through
the
        board and plated to internal thermal planes. To improve the
conductive
        cross-sectional area of these holes, I had them filled with
silver-loaded
        epoxy, which was then Cu-plated over. This process also served the
        secondary purpose of filling holes that otherwise, as you suggest,
would
        contain entrapped plating solutions.

        Depending on your substrate material and operating environment, I
could
        imagine a plated 'cap' splitting over time through temp cycling and
        mechanical stresses, assuming it survives the hot assembly
processes
with
        the expansion of entrapped gasses. Not serious, thermally, perhaps,
but it
        would allow the outside atmosphere to circulate inside the holes as
well,
        which might not be so good inteh long run.

        Peter




                            "Marsico, James"
                            <James.Marsico@D        To:     [log in to unmask]
                            P.AIL.COM>              cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                            Sent by: TechNet        Aero/ST Group)
                            <[log in to unmask]        Subject:     [TN] VIAS
PLATED CLOSED
                            >


                            01/11/02 05:55
                            AM
                            Please respond
                            to "TechNet
                            E-Mail Forum."






        Good day technet:

        We're considering designing a multilayer polyimide PWB with a
number
of
        vias
        (approximately .021" diameter holes, .062" thick PWB) that are
plated shut,
        for thermal reasons.  Can anyone comment on pitfalls regarding the
fab
        process?  How about voids in the solid copper via?  Entrapped
plating
        solution?

        All comments are appreciated.  Thanks in advance...

        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879


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Date:         Mon, 14 Jan 2002 08:21:30 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, James,

Hearing of what you're trying to do, I furrow my brow in anxiety. If you're
plating the entire hole closed, what surface copper weight are you
expecting as a result, especially with 21 mil diameter holes? My estimate
is about 8 oz. What trace widths and spacings are involved? If they're
fairly fine, the undercut from the etching process will probably sever them
from the board, or make them extremely weak. It is possible to grind excess
copper of the board surface, but this is a brutal and risky process as
well, since if the board isn't dead flat, you can take off traces and pads
adn go through to the substrate material.

 If it's only the thermal holes you're trying to plate shut, how are you
going to prevent the other holes in the board from being filled as well
without a lot of selective masking? Also, I suspect that the holes will
close at the top and bottom first, leaving a void in the centre that will
contain plating solutions and cause all kinds of corrosive and expansion
problems.

This is not a good idea!!! My strong recommendation is that you use silver
loaded epoxy to fill the thermal via holes prior to final plating. It's
thermal conductivity is not as good as that of copper, but is relatively a
lot less hassle and will be a lot cheaper than all that plating. There are
a number of epoxies  available, though Dupont's CB100 is one that is
commonly cited. It has a thermal conductivity value of 5.23 W/mK, so is
pretty good for this type of material. Other makes are similar.

Let us know how it goes. Good luck!!

Peter




                    "Marsico, James"
                    <James.Marsico@D        To:     [log in to unmask]
                    P.AIL.COM>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet        Aero/ST Group)
                    <[log in to unmask]        Subject:     Re: [TN] VIAS PLATED CLOSED
                    >


                    01/11/02 08:09
                    PM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Hi, Peter, thanks for the response.

Let me try to explain further.  We're using ceramic leadless chip carriers
which give off a lot of heat.  In an effort to dissipate the heat to the
ground planes, we're placing thermal vias underneath.  We wanted the
thermal
vias to be plated closed, resulting in a solid plug of copper, which we
then
can deposit solder paste on top which would contact the bottom of the
ceramic package.  The heat path would be from the component through the
solder bumps on the thermal vias through the solid copper via.  Our board
supplier claims that he can plate the vias closed, but when I asked about
voids and entrapped plating chemicals, he said he was never asked that
before and would have to look into it.  I'm getting concerned with this
design, thinking that an epoxy-filled via which is plated over on top would
be better.  I now need recommendations for a THERMALLY conductive adhesive,
it doesn't have to be electrically conductive but I don't really care.

Thanks again,

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   <Peter George Duncan> [SMTP:[log in to unmask]]
        Sent:   Thursday, January 10, 2002 9:28 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        Hi, James,

        I'm trying to picture your "thermal reasons" and how plating over
the holes
        will help, reliably. I haven't encountered a process for plating
over
        holes, and 21 mils seems quite a canyon to bridge. I'ld be very
interested
        to know how this is done.

        I'm very involved with conduction-cooled MLB's 60 mils thk, that
require a
        lot of thermal management. 'Thermal' via holes are punched through
the
        board and plated to internal thermal planes. To improve the
conductive
        cross-sectional area of these holes, I had them filled with
silver-loaded
        epoxy, which was then Cu-plated over. This process also served the
        secondary purpose of filling holes that otherwise, as you suggest,
would
        contain entrapped plating solutions.

        Depending on your substrate material and operating environment, I
could
        imagine a plated 'cap' splitting over time through temp cycling and
        mechanical stresses, assuming it survives the hot assembly
processes
with
        the expansion of entrapped gasses. Not serious, thermally, perhaps,
but it
        would allow the outside atmosphere to circulate inside the holes as
well,
        which might not be so good inteh long run.

        Peter




                            "Marsico, James"
                            <James.Marsico@D        To:     [log in to unmask]
                            P.AIL.COM>              cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                            Sent by: TechNet        Aero/ST Group)
                            <[log in to unmask]        Subject:     [TN] VIAS
PLATED CLOSED
                            >


                            01/11/02 05:55
                            AM
                            Please respond
                            to "TechNet
                            E-Mail Forum."






        Good day technet:

        We're considering designing a multilayer polyimide PWB with a
number
of
        vias
        (approximately .021" diameter holes, .062" thick PWB) that are
plated shut,
        for thermal reasons.  Can anyone comment on pitfalls regarding the
fab
        process?  How about voids in the solid copper via?  Entrapped
plating
        solution?

        All comments are appreciated.  Thanks in advance...

        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879


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Date:         Mon, 14 Jan 2002 10:54:38 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Patrick,

In general I would say "No", it is not acceptable to remove unused pads on
internal layers, the reason being that these pads greatly assist in
"keying" the plated copper in the holes to the walls. For class 3 boards
undergoing thermal cycling, retaining unused pads therefore improves the
reliability of the PCB's.

Peter Duncan




                    Patrick Lam
                    <Patrick_Lam@S        To:     [log in to unmask]
                    ELINC.COM>            cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:              Aero/ST Group)
                    TechNet               Subject:     [TN] Remove unused "dead" pads on
                    <[log in to unmask]        internal layers
                    RG>


                    01/12/02 06:11
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
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distribution or
other use is prohibited.  If you received this e-mail in error, please
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Date:         Mon, 14 Jan 2002 11:08:00 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-type: multipart/mixed;
              Boundary="0__=48256B410010568D8f9e8a93df938690918c48256B410010568D"

--0__=48256B410010568D8f9e8a93df938690918c48256B410010568D
Content-type: text/plain; charset=us-ascii

Another 2 cents' worth from me - what is the surface pad diameter for the
holes in question? Our normal routing procedure is that the surface pad
diameter is a "keep-out" diameter right through the board, and the surface
pad diameter is maintained on all the other layers. Unless you're really
short of real estate, I would suggest you follow this same "rule", as it's
less trouble that specifying a different diameter for internal layers.

10 mils over finished hole diameter gives you a 5 mils pad around the hole.
Depending on the plating thickness, that will give you less than 4 mils
annular ring, which  (though not so important on internal layers) could be
a bit tight if registration/drill placement accuracy isn't tightly
controlled. Again how does the 10 mils diameter you propose compare with
the surface pad diameter?

Best regards

Peter




                    Patrick Lam
                    <Patrick_Lam@S        To:     [log in to unmask]
                    ELINC.COM>            cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:              Aero/ST Group)
                    TechNet               Subject:     Re: [TN] Remove unused "dead" pads on
                    <[log in to unmask]        internal layers
                    RG>


                    01/12/02 07:01
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum."








Thanks Steve,

Would 0.010" over the finished hole size be good pad size to be used on
internal
layers?

Thanks,
Pat




Stephen Gregory <[log in to unmask]> on 01/11/2002 02:33:46 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Patrick Lam/SEL)
Subject:  Re: [TN] Remove unused "dead" pads on internal layers



Hi Pat!

I don't think it's a good idea, we got burned by it once. The internal pads
will provide support during drilling, and will help prevent rough walls
during drilling.

In our case, the unused pads were removed (this was a fairly thick ~.093"
or
so polyimide PCB) and plating chemicals were absorbed into the fibers from
the rough drilling. We built the boards, did ICT and a low power functional
test, everything was fine. The boards were shipped to our customer and they
plugged it into their system, powered it up, and then the board died after
about 20-minutes, internal short in the fab. They RMA'd the board back to
us,
we sent it out for cross sectioning and found the problem.

Had the used pads put back in and haven't had a problem since.

-Steve Gregory-


> Hi TechNetters,
>
> For class 3 boards, is it acceptable to have unused pads removed on
> interanal
> layers.
>
> Thanks,
> Pat
>



(See attached file: att1.htm)






This e-mail may contain SEL confidential information.  The opinions
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Date:         Mon, 14 Jan 2002 06:46:45 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
X-To:         "<Peter George Duncan>" <[log in to unmask]>

Peter,

I echo all you say. What do the board shop folks say? Does anyone have any
x-sections showing one or more of these plated "shut" holes?

Also, back up what you said about "divots" in pads plated over. Haven't been
able to ge a flat surface on these things but they work well enough when
used with RF chip device solder termination areas to prevent solder
drain-off. This is a good alternative, to sequential lamination, for those
convinced these vias are necessary in the firt place to ensure required
performance.

Earl

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Date:         Mon, 14 Jan 2002 06:50:05 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      SOLDER PASTE LOYALTY

Folks,

But for their web site, I really am impressed with Indium's SMQ-92 solder
paste. Been using it in some form for over three years.

Who does or doesn't like the stuff, if you please? What's better, IHMO's?
Objective evidence is better though.

Thanks,

MoonMan

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Date:         Mon, 14 Jan 2002 14:16:18 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Busko, Wolfgang" <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
MIME-Version: 1.0
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Content-Transfer-Encoding: quoted-printable

You want my IMHO ?
... alright, here it is:

The one that I=B4m  currently using with no problems is the best, no =
matter
what time or brand!!!
If it were Indium=B4s SMQ-92 than it would be the best.=20

Get me ?

Wolfgang

PS: Already back from your cave?
=20

> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: Monday, January 14, 2002 1:50 PM
> To: [log in to unmask]
> Subject: [TN] SOLDER PASTE LOYALTY
>=20
>=20
> Folks,
>=20
> But for their web site, I really am impressed with Indium's=20
> SMQ-92 solder
> paste. Been using it in some form for over three years.
>=20
> Who does or doesn't like the stuff, if you please? What's=20
> better, IHMO's?
> Objective evidence is better though.
>=20
> Thanks,
>=20
> MoonMan
>=20
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Date:         Mon, 14 Jan 2002 07:16:48 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
X-To:         Wolfgang Busko <[log in to unmask]>

Wolfy,

Thanks for the welcome, but I'm in the cave. I get you but want to know what
is best based on objective performance. You have any of that comparing
pastes versus what there supposed to do? Hopefully, not another loaded
question, but?

Earl

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Date:         Mon, 14 Jan 2002 08:43:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Telgen <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Pat,
Most board shops remove unused pads to reduce the possibility of etch or
imaging problems, especially with false AOI errors. I don't believe Class 3
addresses this.  On some designs its better to leave the pads on if there's
going to be excessive fill necessary.  To Steve's point, I don't understand
how a copper pad would prevent glass fiber tear-away.  Sound more like his
fab-house fixed a drilling problem.  If there is a benefit to leaving them
on, I'd like to know.
Steve Telgen

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Patrick Lam
Sent: Friday, January 11, 2002 17:12
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
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notify
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Date:         Mon, 14 Jan 2002 15:14:37 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Zweigart, Siegmund" <[log in to unmask]>
Subject:      finish
MIME-Version: 1.0
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Dear All

I am looking about a comparison of different Finishes of PCBs (HASL, =
chem.
Tin, NiAu, chem. Ag, OCC .....) with all advantages and disadvantages.
Also I am interested in details about the plating procedure for these
finishes.
Is there any information available?

Siggi
------------------------------------------------------------------------=
----
-
Kind regards / Mit freundlichen Gr=FC=DFen

Dr. Siegmund Zweigart
New Technology Manager

Solectron GmbH
Solectronstrasse 2              Fon. ++49 7032 998 194
D - 71083 Herrenberg         Fax  ++49 7032 998 49 222

e-mail: [log in to unmask] =
<mailto:[log in to unmask]>=20
internet: www.solectron.com <http://www.solectron.com>=20
------------------------------------------------------------------------=
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Date:         Mon, 14 Jan 2002 08:38:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Remove unused "dead" pads on internal layers
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

not a bad idea to remove them, one less place to "short out". If you want them
in, then use atleast .010" wide space around them to clear anything that could
short.







Patrick Lam <[log in to unmask]> on 01/11/2002 04:11:53 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>








 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  [TN] Remove unused "dead" pads on internal layers








Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions expressed
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Date:         Mon, 14 Jan 2002 09:48:12 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         George Milad <[log in to unmask]>
Subject:      Re: finish
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_8b.1220eccf.297449ac_boundary"

--part1_8b.1220eccf.297449ac_boundary
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Siggi,
U will find a very comprehensive discussion of the Surface Finshes in Chapter
32 of the same title in the Fifth Edition 2001 of Clyde Coombs "Printed
Circuits Handbook".
The next Issue of the magazine "The Board Authority" will have a full
didscussion in its opening paper authored by Milad and Obrien.
George Milad
Chairman
IPC Plating Committee

--part1_8b.1220eccf.297449ac_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Siggi,
<BR>U will find a very comprehensive discussion of the Surface Finshes in Chapter 32 of the same title in the Fifth Edition 2001 of Clyde Coombs "Printed Circuits Handbook".
<BR>The next Issue of the magazine "The Board Authority" will have a full didscussion in its opening paper authored by Milad and Obrien.
<BR>George Milad
<BR>Chairman
<BR>IPC Plating Committee</FONT></HTML>

--part1_8b.1220eccf.297449ac_boundary--

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Date:         Mon, 14 Jan 2002 09:53:50 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Taconic teflon TLX-8
MIME-Version: 1.0
Content-Type: text/plain

Hi technos,

please give me a hint on what Taconic Teflon TLX-8 is and it's solderability
properties. I saw this specified on an RF drawing and I wonder if it can be
reflowed. Any other concerns?

Also, any directions towards an on-line resource would be highly
appreciated.

Thanks,
Ioan

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Date:         Mon, 14 Jan 2002 09:54:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: finish
In-Reply-To:  <795D6BC907F3D511B450000629554AE60CA4F1@RFC1918-Host>
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Here's a link with some information
http://www.pcfab.com/db_area/archive/2000/0010/dfe.html
and another
http://www.smta.org/knowledge/proceedings_abstract.cfm?PROCEEDING_ID=571

In a nutshell, IMHO, Nothing solders or protects like HASL but, it may not
provide a level enough finish for some applications.

All immersion tins are not equal and they do not protect the copper as well
as HASL. But they do provide a level surface on which to place components.

As for Nickel Gold, you are not soldering to copper but nickel. The finish
is flat but the solder process may not exhibit the same wetting as with a
good HASL, OSP, SN or Ag finish. There are many discussions of Black Pad in
the technet archives.

Immersion silver is well liked and seems to provide good process results.
May not be as robust as HASL.

OSP works good but, the first time you find out if you can plate to the
copper on the board is when you try to solder to it. That can be a little
late.

This is far from "all advantages and disadvantages" but such a reply would
require one to follow MoonMan's steps to a cave.


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Zweigart, Siegmund
> Sent: Monday, January 14, 2002 9:15 AM
> To: [log in to unmask]
> Subject: [TN] finish
>
>
> Dear All
>
> I am looking about a comparison of different Finishes of PCBs (HASL, chem.
> Tin, NiAu, chem. Ag, OCC .....) with all advantages and disadvantages.
> Also I am interested in details about the plating procedure for these
> finishes.
> Is there any information available?
>
> Siggi
> ------------------------------------------------------------------
> ----------
> -
> Kind regards / Mit freundlichen Grüßen
>
> Dr. Siegmund Zweigart
> New Technology Manager
>
> Solectron GmbH
> Solectronstrasse 2              Fon. ++49 7032 998 194
> D - 71083 Herrenberg         Fax  ++49 7032 998 49 222
>
> e-mail: [log in to unmask] <mailto:[log in to unmask]>
> internet: www.solectron.com <http://www.solectron.com>
> ------------------------------------------------------------------
> ----------
> -
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date:         Mon, 14 Jan 2002 10:08:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      AOI
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I'm looking for a low end ($65k) optical inspection system for SMT component
placement and polarity inspection.  Anyone have any recommendations?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Mon, 14 Jan 2002 10:18:06 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Angelo DiMichele <[log in to unmask]>
Subject:      Re: Taconic teflon TLX-8
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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     I have never used it but here is a website that you may want to try.
http://www.taconic-add.com/

Angelo Dimichele
AMS Electronics Inc.
----- Original Message -----
From: Tempea, Ioan <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 14, 2002 9:53 AM
Subject: [TN] Taconic teflon TLX-8


> Hi technos,
>
> please give me a hint on what Taconic Teflon TLX-8 is and it's
solderability
> properties. I saw this specified on an RF drawing and I wonder if it can
be
> reflowed. Any other concerns?
>
> Also, any directions towards an on-line resource would be highly
> appreciated.
>
> Thanks,
> Ioan
>
> --------------------------------------------------------------------------
-------
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> --------------------------------------------------------------------------
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>

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Date:         Mon, 14 Jan 2002 10:06:16 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         James TerVeen <[log in to unmask]>
Subject:      Re: Taconic teflon TLX-8
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

You can go to there web sight a thttp://www.4taconic.com/index.htmln
This should help you and they have been very helpful on issues on material
I have had in the past




                    "Tempea, Ioan"
                    <itempea@POSIT       To:     [log in to unmask]
                    RON.QC.CA>           cc:
                    Sent by:             Subject:     [TN] Taconic teflon TLX-8
                    TechNet
                    <[log in to unmask]
                    RG>


                    01/14/02 09:53
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum."






Hi technos,

please give me a hint on what Taconic Teflon TLX-8 is and it's
solderability
properties. I saw this specified on an RF drawing and I wonder if it can be
reflowed. Any other concerns?

Also, any directions towards an on-line resource would be highly
appreciated.

Thanks,
Ioan

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Date:         Mon, 14 Jan 2002 09:24:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         Earl Moon <[log in to unmask]>
Subject:      Re: finish
X-To:         Guy Ramsey <[log in to unmask]>

Guy,

The cave is quite resplendent with most ameneties. HASL is not one of them.

Werner once responded, accurately, any process can be mis-managed as in the
HASL thing. One thing that cannot be managed is the copper surface of a
board about to enter HASL hell. The copper surface is cleaned, micro-etched,
rinsed, dried (wherein the biggest process mis-management occurs), then
introduced to fluxes often incapable of removing the oxidation imparted by
the drying process. This is my big gripe against HASL now that I've grown so
fond of very "thick" IMC's.

Amazingly, I have seen HASL surfaces very flat, shiney, bright, and
solderable. I don't remember where I saw this phenomonom. Probably in my
dreams but it was a wonder. I also wonder, if it was not a dream, where
these conditions were produced. Any board fab folks out there?

As for popping my head out of the cave, it gets very lonely in here, or not,
and fresh air always is appreciated. However, I'm not a weather reporter
based on shadow. What's with this strange passage. No snow covering my cave
opening.

MoonMan

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Date:         Mon, 14 Jan 2002 07:35:20 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: Anodised Aluminium wire
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hi,

you might try california fine wire at:

http://www.calfinewire.com/

phil

-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 12:29 AM
To: [log in to unmask]
Subject: [TN] Anodised Aluminium wire


I am looking for information on a supplier for anodised aluminium wire, the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Mon, 14 Jan 2002 16:39:09 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: AOI
X-cc:         [log in to unmask]
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Hi Jim,

In my mailbox Iarchived an earlier posting from Glenn Woodhouse that =
contained some very usefull information about the subject of AOI. I hope =
that Glenn doesn't mind that I repost his input here:

Daan Terstegge
Unclassified mail

> For the evaluation and selection of an AOI system there are a few key
> points
> that I suggest you focus on.
>=20
> 1.  Solder Joint Inspection - Most AOI suppliers claim solder joint
> inspection capability but this is really one of the differentiating
> points.
> You need to decide how badly you want good solder joint inspection
> capability.  Truly capable systems are more complex mechanically as well
> as
> in their programming thus requiring a higher level of expertise, as well
> as
> investment in time, for program development and optimization.  For low
> volume-high mix and prototyping environments, it often takes more time =
to
> develop robust solder joint inspection that it takes to build and ship =
the
> product!  Solder joint inspection will increase the false call rate of =
any
> system.  Finally, it is important to remember that video based AOI =
systems
> can only operate in a line of sight fashion.  Packages like SOJ's, =
PLCC's,
> and BGA's will not support solder joint inspection.  There are x-ray
> "combi"
> machines available as well but you have to weigh the cost and throughput
> implications of a combi.  If you make the required commitment in capital
> expenditure and engineering support, solder joint inspection can yield
> very
> good results and help to take your process to the next level.  If you
> don't
> provide the appropriate level of commitment in support resources, then =
the
> investment in solder joint inspection capability will be a waste and =
cause
> frustration and confusion on the line until you ultimately turn off that
> portion of the inspection.  Look for systems that use convergent =
software
> technology where the s/w keeps track of false calls and the conditions
> surrounding them as a means to automatically and statistically refine
> inspection algorithms as a means to reduce false calls.
>=20
> 2.  Production Environment - As eluded to above, it is my opinion that =
the
> state of the AOI industry today does not provide a single machine that
> "does
> it all".  If you are running in a high mix/low volume/high change
> environment then machine speed/throughput is less important than ease in
> program development.  In this environment if you can't get a program
> cranked
> out and reasonably optimized in 2 hours or less you will spend all of =
your
> time programming and very little time running the machine in production.
> Look for off-line programming capabilities as a means to help free the
> machine up a bit more, but you still always need machine time for =
initial
> image capture and final debug.
>=20
> 3.  Vector Based versus Pattern Recognition -
>=20
>      Vector based machines will find the edges of packages and leads,
> determine centroids, compare this to CAD data, and except/reject based =
on
> numerical tolerance settings.  This allows for the building of numericall=
y
> based part data files, like with pick-n-place machines.  Vector based
> machines can provide you with very accurate x-y offset data to validate
> and
> tweak in your p-n-p equipment.  This keeps the AOI machine from =
"learning"
> a
> bad placement or condition as the "golden" model.  There is also at =
least
> an
> order of magnitude greater complexity, difficulty, and time investment =
in
> the programming and optimization of vector based machines, but vector
> based
> machines generally offer greater flexibility over the long run for odd
> packages, special measurement applications, and fine pitch lead
> measurement.
> The vector machines I am familiar with (MVT and VI) are generally faster
> than the pattern rec. class of machines although some companies like CR
> Technology are steadily developing faster and faster machines, thus
> closing
> the gap.
>=20
>      Pattern Recognition, or correlation based vision processing =
compares
> a
> bit map from the camera field of view FOV for the current board to a =
saved
> "golden" image for the same FOV.  The user defines the degree of bit map
> correlation required to achieve the pass threshold.  Bit map correlation
> algorithms are used to break up the FOV into smaller chunks, allowing =
for
> the detection and identification of a small defect like a skewed 0402
> although comparing FOV images that may be larger  (~1" x 1").  The
> advantages to pattern recognition is that it is generally easier to
> program,
> using wizard style teach functions combined with cad data, and easier to
> understand.  Great for a proto or high mix shop, or an environment where
> you
> don't have the luxury of throwing a high level tech(s) or engineer(s) at
> the
> process.  The disadvantage is that often acceptable manufacturing
> variation,
> such as a different color tantalum cap off of the approved vendor list,
> will
> result in a reject.  It then requires you to teach this as an alternate
> acceptable image.  Depending on who is allowed to teach  alternates, you
> can
> get in the situation where pretty soon you have dozens of alternates for
> many FOV's which can start to affect the speed of inspection and
> inadvertently create opportunities for false passes.
>=20
> 4.  SPC - It amazes me how many AOI systems out there provide inadequate
> supporting SPC packages.  Without a system that provides good real time
> SPC
> feedback up the line, the AOI machine is only a failure screen that =
helps
> you increase your ICT yields but does not reduce rework (assuming you =
are
> repairing AOI detected defects in advance of ICT).  Look for systems =
that
> allow for web based live SPC reporting so you don't have to invest in a
> separate data server and set of applications/licenses requiring =
dedicated
> data terminals.  Web based output allows you to leverage your existing
> plant
> PC infrastructure in the factory and at the desks of those who need this
> data.  All you need is an Ethernet card in the machine which writes data
> to
> a network target, and a standard browser to run the AOI manufacturer's
> Java
> scripts for displaying the live data from that target.  If you want to
> integrate the AOI data real time and automatically into your plant's
> existing quality tracking system, evaluate the data output structures =
and
> communications interfaces that the machine supports.
>=20
> 5.  Company Stability/Structure - There is something like 20 players in
> this
> market today.  Considering the current electronics industry market
> condition, and the natural tendency for consolidation in this type of
> business, I think we'll see many of these 20 disappear over the next
> couple
> of years either through lack of funding, lack of market share, or
> acquisition by larger companies.  Work to understand the AOI company's
> financial health (private, public, venture capital funded, cash??, =
etc.),
> short and long term business strategy (IPO, acquire or be acquired),
> historical and current growth rate compared to competitors, and if they
> posses any differentiating technology that has inherent value over their
> competitors (this point often makes a small company ripe for acquisition
> which can be good over the long haul).  The quantum leap in PC processor
> speeds, cheap RAM, and quality high resolution color CCD cameras =
available
> today is the primary reason for this explosion in AOI products, i.e. we
> can
> finally afford them due to affordable components!  This levels the =
playing
> field so to speak from the hardware standpoint, making the software side
> of
> the product the key differentiating feature.  Look for companies that
> recognize this and possess evolved machine algorithms, program developmen=
t
> tools, and SPC packages.  They should have a large software development
> resource with many experienced software engineers and developers.  They
> should be able to demonstrate active software improvement projects and
> have
> a "roadmap" of additional features and enhancements they are working on.
> If
> they cant, and are focused on hardware and speed improvements only,
> beware!
>=20
>=20
> There's more to think about but I feel these are the biggies.
>=20
> Good luck,
>=20
>          Glenn Woodhouse
>                  MCMS
> Advanced Technology Development
>           (208) 898-2753


>>> "Marsico, James" <[log in to unmask]> 01/14 4:08 pm >>>
I'm looking for a low end ($65k) optical inspection system for SMT =
component
placement and polarity inspection.  Anyone have any recommendations?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Mon, 14 Jan 2002 09:43:22 -0600
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Just wanted to clarify the virus-attachment and <Reply-To> issues with the =
Technet list.=20

First of all, Technet does not allow for any attachments to be sent with =
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Occasionally a virus-generated e-mail will find it's way to the list =
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Hope this helps.



______________
Keach Sasamori
IS Administrator
IPC
2215 Sanders Rd.
Northbrook, IL 60062
Ph: (847) 790-5315=20
Fax: (847) 504-2315
e-mail: [log in to unmask]

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Date:         Mon, 14 Jan 2002 11:01:06 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Zarrow <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
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Earl, Wofly and all -
I guess that with "not causing any problems", Wolfy must be getting zero
defect reflow soldering.  Cool !  I want some of that stuff.
In my experience, there is always something better out there.  The solder
paste manufacturers are beating their brains out and their R&D budgets trying
to come up with better performing solder pastes.  What seems to be working
well, and has been for the last few months, years..(as in Wolfy's case) might
very well be - but most likely there is something out there that works
better.  Every time I have done a solder paste evaluation with a client, we
always come up with something that works better than what they are using
currently - and these are blind tests that include the current formulation as
well.  Better wetting, less (or no) solder ball generation, better tack time,
better tack performance with a high-speed chip shooter, etc.
I urge anyone who has not evaluated solder paste for over a year to do so -
especially if you are using a no-clean.

Phil Zarrow

ITM Consulting
Durham, NH  USA
www.ITM-SMT.com
T: (603) 868-1754
F: (603) 868-3623
EM:[log in to unmask]

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Earl, Wofly and all - <BR>
I guess that with "not causing any problems", Wolfy must be getting zero defect reflow soldering.&nbsp; Cool !&nbsp; I want some of that stuff.&nbsp; <BR>
In my experience, there is always something better out there.&nbsp; The solder paste manufacturers are beating their brains out and their R&amp;D budgets trying to come up with better performing solder pastes.&nbsp; What seems to be working well, and has been for the last few months, years..(as in Wolfy's case) might very well be - but most likely there is something out there that works better.&nbsp; Every time I have done a solder paste evaluation with a client, we always come up with something that works better than what they are using currently - and these are blind tests that include the current formulation as well.&nbsp; Better wetting, less (or no) solder ball generation, better tack time, better tack performance with a high-speed chip shooter, etc.<BR>
I urge anyone who has not evaluated solder paste for over a year to do so - especially if you are using a no-clean.<BR>
<BR>
Phil Zarrow<BR>
<BR>
<B>ITM Consulting&nbsp; <BR>
Durham, NH&nbsp; USA<BR>
www.ITM-SMT.com<BR>
T: (603) 868-1754<BR>
F: (603) 868-3623<BR>
EM:[log in to unmask]</B></FONT></HTML>

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Date:         Mon, 14 Jan 2002 09:53:52 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: AOI
X-To:         [log in to unmask]

This one of the most outstanding posts, in my opinion, in a long time about
such an important new technology. Says it like it is but holds positive
views about what is needed in the future.

Going down this road a lot lately, like so many of us. Don't know where it
will lead but problem still is attributes instead of variables. Can SPC
analysis correlate findings and give quality and realibility information
instead of raw data (BS)?

MoonMan

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Date:         Mon, 14 Jan 2002 11:26:10 EST
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Subject:      Re: AOI
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For the lower end cost wise, but still good performance, I would check out
CyberOptics KS50 machine.  A little more than your $65K (around $80K), but
very nice.

Jon Moore

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Date:         Mon, 14 Jan 2002 10:23:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
X-To:         Phil Zarrow <[log in to unmask]>

I'm with you. Only problem is getting anyone, as is often usual, to
entertain the project. Need more consultants with clout I suspect.

I usually, as with my DFM/CE, enter a contract to "prove" how much better
life could be if positive change was made (improvement?) and everyone buys
in. Later, they revert. With all this, we look to lead free, environmental
issues, and all else but the bottom line prevails.

Sure would like to see some independent study results without regard for
"loyalty." Does the IPC do this stuff?

MoonMan

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Date:         Mon, 14 Jan 2002 17:52:04 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "Busko, Wolfgang" <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
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Phil, Earl et all,
seems to get philosophical?
Well,  Wolfy might be a bit conservative in this case but as long as =
he=B4s
not seeing any paste related problems (or thinks if there are problems =
they
are obviously not paste related) he doesn=B4t want to perform tests =
with new
paste.
We have certain processes, variables and settings, and they perfectly =
fit
our demands to our all agreed satisfaction ( worked on that long enough =
)
and we don=B4t like to fuzz around with new things unless we are to.=20
=20
Although .... sometimes ... we like to play a little and look what =
works ...
than we might find one or two problems that need to be looked after  =
;-).
But I have to admit that this is only the case if we=B4re asked to =
check a new
formula and doesn=B4t mean that we automatically switch to other brands =
even
if the tests show good results but it=B4s nice to have a second choice.
=20
All new things have to compete with our "old stuff" and I won=B4t check =
for
100mph abilities in our 55mph zone.
=20
Wolfy
=20
=20
=20
=20

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Date:         Mon, 14 Jan 2002 09:51:43 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Top Side Solder Balls on Wave Process
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Fellow,

        I am trying to look for possible causes for a solder ball problem on
the wave process. These boards are practically a Swiss cheese, unmasked 25
mils via holes all over the place, under QFPs, SOIC and everything else,
which limits the wave process window. These assemblies don't have SMT on the
bottom, wave is used only for TH. We've done everything, checking of flux
specific gravity, changed the flux, verified the profile, made sure the flux
get activated...Our process uses a foam fluxer and WS flux. What could
possibly cause solder balls on the top side? the defect rate is aprox. 2-5
boards with solder balls every 20 boards. Any Ideas?

        Any comments would be appreciated


Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 14 Jan 2002 11:03:48 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: SOLDER PASTE LOYALTY
X-To:         Wolfgang Busko <[log in to unmask]>

Wolfy,

You are absolutely right except when it comes to new product evaluation
requirements. The old saying "if it ain't broke, don't fix it" has meaning
here - to a point. However, someone must advance the cause and come up with
new and better stuff. It can't always be the suppliers.

MoonMan

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Date:         Mon, 14 Jan 2002 12:14:55 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: Taconic teflon TLX-8
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Ioan,
Try their webpage for data sheets, etc. <http://www.4taconic.com/>

----- Original Message -----
From: "Tempea, Ioan" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 14, 2002 9:53 AM
Subject: [TN] Taconic teflon TLX-8


> Hi technos,
>
> please give me a hint on what Taconic Teflon TLX-8 is and it's
solderability
> properties. I saw this specified on an RF drawing and I wonder if it can
be
> reflowed. Any other concerns?
>
> Also, any directions towards an on-line resource would be highly
> appreciated.
>
> Thanks,
> Ioan
>
> --------------------------------------------------------------------------
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Date:         Mon, 14 Jan 2002 11:08:43 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Top Side Solder Balls on Wave Process
X-To:         Jorge Rodriguez <[log in to unmask]>

Jorge,

What's the most common cause of the effect? Volatiles are not driven off -
whetere in the flux, solder mask, or whatever else.

MoonMan

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Date:         Mon, 14 Jan 2002 18:25:42 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: Top Side Solder Balls on Wave Process
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Maybe you can correlate the good and bad boards with the datecodes on the =
boards ?  If so, than it's very likely that something went wrong in =
pcb-manufacturing.
If several datecodes have the problem than I'd say it's probably the =
assembly process (did you bake long enough ?).

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

>>> Jorge Rodriguez <[log in to unmask]> 01/14 5:51 pm >>>
Fellow,

        I am trying to look for possible causes for a solder ball problem =
on
the wave process. These boards are practically a Swiss cheese, unmasked 25
mils via holes all over the place, under QFPs, SOIC and everything else,
which limits the wave process window. These assemblies don't have SMT on =
the
bottom, wave is used only for TH. We've done everything, checking of flux
specific gravity, changed the flux, verified the profile, made sure the =
flux
get activated...Our process uses a foam fluxer and WS flux. What could
possibly cause solder balls on the top side? the defect rate is aprox. 2-5
boards with solder balls every 20 boards. Any Ideas?

        Any comments would be appreciated


Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 14 Jan 2002 11:29:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Virus and Reply-To issues
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Keach,
Just so you know, the Reply to All function does not work in Lotus Notes.
All my off line replies have to be manually entered.

Doug Pauls

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Date:         Mon, 14 Jan 2002 11:38:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Top Side Solder Balls on Wave Process
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_D38EA1D3.3D5C3108"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_D38EA1D3.3D5C3108
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

Do you do a moisture bake prior to using the PCB's?  Do you have any =
turbulence to the wave?  I have seen this defect mainly caused due to PCB =
moisture that is erupting causing the solder ball but also by a wave that =
had too much turbulence and the wave forces the solder to the top side. =
=20

My $.02 anyway.

--=_D38EA1D3.3D5C3108
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Do you do a moisture bake prior to using the PCB's?&nbsp; Do you have any
turbulence to the wave?&nbsp; I have seen this defect mainly caused due to PCB
moisture that is erupting causing the solder ball but also by a wave that had
too much turbulence and the wave forces the solder to the top side.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>My $.02 anyway.</DIV></BODY></HTML>

--=_D38EA1D3.3D5C3108--

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Date:         Mon, 14 Jan 2002 12:44:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Re: Top Side Solder Balls on Wave Process
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Jorge
I agree with the other responses you've gotten thus far, but can add one =
possibility.  One customer I've got likes to add a couple of unplated =
through-holes per board, in case there is a requirement to jumper from one =
side to the other.  Sounds reasonable, but these small holes are amazing =
at generating solder balls.  We typically do not mask any through holes =
(plated or un-plated), but have to do these because they spit solder balls =
up some times.  If you have any small (e.g. 25 mil unplated holes) try =
masking those.

regards

Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215

>>> [log in to unmask] 01/14/02 12:51PM >>>
Fellow,

        I am trying to look for possible causes for a solder ball problem =
on
the wave process. These boards are practically a Swiss cheese, unmasked 25
mils via holes all over the place, under QFPs, SOIC and everything else,
which limits the wave process window. These assemblies don't have SMT on =
the
bottom, wave is used only for TH. We've done everything, checking of flux
specific gravity, changed the flux, verified the profile, made sure the =
flux
get activated...Our process uses a foam fluxer and WS flux. What could
possibly cause solder balls on the top side? the defect rate is aprox. 2-5
boards with solder balls every 20 boards. Any Ideas?

        Any comments would be appreciated


Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 14 Jan 2002 14:23:23 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Taconic teflon TLX-8... thanks
MIME-Version: 1.0
Content-Type: text/plain

Hi,

and thanks for the link. I am in contact with Taconic and hopefully my
questions will be answered.

Ioan

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Date:         Mon, 14 Jan 2002 14:48:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Stuart Korringa <[log in to unmask]>
Subject:      hand lotion
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What are some acceptable hand lotions that could be purchased by my company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


**********************************************************************
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Date:         Mon, 14 Jan 2002 15:02:58 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
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We have been using the "I.C. Lotion" Non-Contaminating Hand Lotion for =
Assemblers and Technicians from Contact East.  There are others in the =
Contact East selection to chose from.

www.contacteast.com

Phil Nutting

-----Original Message-----
From: Stuart Korringa [mailto:[log in to unmask]]
Sent: Monday, January 14, 2002 2:49 PM
To: [log in to unmask]
Subject: [TN] hand lotion


What are some acceptable hand lotions that could be purchased by my =
company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


**********************************************************************
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be legally privileged or otherwise exempt from disclosure under
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Date:         Mon, 14 Jan 2002 15:12:20 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Angelo DiMichele <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
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Stuart,
    Chemtronics sells a product called "Static Free Hand Guard".It is
noncontaminating. The Chemtronics part number is C805. Our operators don't
mind using it.

    Angelo DiMichele

----- Original Message -----
From: Stuart Korringa <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 14, 2002 2:48 PM
Subject: [TN] hand lotion


> What are some acceptable hand lotions that could be purchased by my
company for
> distribution to the assembly areas? There must be something that is not
> repugnant and would make the operators be happy to use.
>
> Thanks,
>
> Stu Korringa
>
> Smiths Electronic Systems
> Grand Rapids, Mi
>
>
> **********************************************************************
> This e-mail and any files transmitted with it are confidential and may
> be legally privileged or otherwise exempt from disclosure under
> applicable law. This e-mail and its files are intended solely for
> the individual or entity to whom they are addressed and their content
> is the property of Smiths Aerospace.  If you are not the intended
> recipient, please do not read, copy, use or disclose this communication.
> If you have received this e-mail in error please notify the e-mail
> administrator at [log in to unmask] and then delete this e-mail, its
> files and any copies.
>
> This footnote also confirms that this e-mail message has been scanned
> for the presence of known computer viruses.
> ***********************************************************************
>
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Date:         Mon, 14 Jan 2002 15:09:25 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Olinger, Patty" <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Stu,
We use Techspray Zero Charge Hand Lotion P/N: 1702-8FP. Smells o.k. All
our operators seem to like it. Hope this helps, ask for samples, that's
what I do.

Patty Olinger=20
Manufacturing Engineer
Projects Unlimited
(937)918-2267
[log in to unmask]


-----Original Message-----
From: Stuart Korringa [mailto:[log in to unmask]]
Sent: Monday, January 14, 2002 2:49 PM
To: [log in to unmask]
Subject: [TN] hand lotion


What are some acceptable hand lotions that could be purchased by my
company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


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Date:         Mon, 14 Jan 2002 12:12:39 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: text/plain

I also recommend the IC Lotion from R and R lotions.  We've used it for a
number of years.   www.rrlotion.com

> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Monday, January 14, 2002 12:03 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] hand lotion
>
> We have been using the "I.C. Lotion" Non-Contaminating Hand Lotion for
> Assemblers and Technicians from Contact East.  There are others in the
> Contact East selection to chose from.
>
> www.contacteast.com
>
> Phil Nutting
>
> -----Original Message-----
> From: Stuart Korringa [mailto:[log in to unmask]]
> Sent: Monday, January 14, 2002 2:49 PM
> To: [log in to unmask]
> Subject: [TN] hand lotion
>
>
> What are some acceptable hand lotions that could be purchased by my
> company for
> distribution to the assembly areas? There must be something that is not
> repugnant and would make the operators be happy to use.
>
> Thanks,
>
> Stu Korringa
>
> Smiths Electronic Systems
> Grand Rapids, Mi
>
>
> **********************************************************************
> This e-mail and any files transmitted with it are confidential and may
> be legally privileged or otherwise exempt from disclosure under
> applicable law. This e-mail and its files are intended solely for
> the individual or entity to whom they are addressed and their content
> is the property of Smiths Aerospace.  If you are not the intended
> recipient, please do not read, copy, use or disclose this communication.
> If you have received this e-mail in error please notify the e-mail
> administrator at [log in to unmask] and then delete this e-mail, its
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>
> This footnote also confirms that this e-mail message has been scanned
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> ***********************************************************************
>
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Date:         Tue, 15 Jan 2002 09:12:58 NZT
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Liane Williams <[log in to unmask]>
Organization: Christchurch Polytechnic
Subject:      Re: hand lotion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=US-ASCII
Content-transfer-encoding: 7BIT

Hi Stu,

I am not sure about the best lotion for your particular application, but working
in a lab and workshop I would offer the following advice:

Look for something neutral & and scent free.

I use "silicone barrier cream", non-perfumed, non-toxic, antiseptic, water
repellant.

You don't need much and it keeps your hands free of any irritations.
I have used it for 4 years now.  I am the only one in my workshop and the
tube is nowhere near finished - still on same bottle and it wasn't even new
when I got here.  Lasting that long, you could supply one per station!

Purchased from NZ Safety Limited in Auckland, New Zealand.
I am sure similar products are available anywhere.

Cheers
Liane.



Physics Technician
Faculty of Health & Sciences
CPIT
[log in to unmask]
ph 9408330

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Date:         Mon, 14 Jan 2002 15:41:53 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tom Parkinson - Quality Assurance Manager <[log in to unmask]>
Organization: WinTronics, Inc.
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

SILICONE??? Isn't getting silicone on a solderable surface the death of
trying to get a solder joint?

We use Techspray - Zero Charge Hand Lotion (anti-static. no silicone,
lanolin, non-contaminating)

Tom

Liane Williams wrote:
>
> Hi Stu,
>
> I am not sure about the best lotion for your particular application, but working
> in a lab and workshop I would offer the following advice:
>
> Look for something neutral & and scent free.
>
> I use "silicone barrier cream", non-perfumed, non-toxic, antiseptic, water
> repellant.
>
> You don't need much and it keeps your hands free of any irritations.
> I have used it for 4 years now.  I am the only one in my workshop and the
> tube is nowhere near finished - still on same bottle and it wasn't even new
> when I got here.  Lasting that long, you could supply one per station!
>
> Purchased from NZ Safety Limited in Auckland, New Zealand.
> I am sure similar products are available anywhere.
>
> Cheers
> Liane.
>
> Physics Technician
> Faculty of Health & Sciences
> CPIT
> [log in to unmask]
> ph 9408330
>
> ---------------------------------------------------------------------------------
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Date:         Mon, 14 Jan 2002 15:53:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kane, Joseph" <[log in to unmask]>
Subject:      Re: hand lotion
MIME-version: 1.0
Content-type: text/plain

We stock Clocream from Lee Pharmaceuticals for our
operators.  It's the only thing we allow in the shop,
specifically to avoid silicone contamination, which
has caused fisheyes in conformal coat.


-----Original Message-----
From: Tom Parkinson - Quality Assurance Manager
[mailto:[log in to unmask]]
Sent: Monday, January 14, 2002 3:42 PM
To: [log in to unmask]
Subject: Re: [TN] hand lotion


SILICONE??? Isn't getting silicone on a solderable surface the death of
trying to get a solder joint?

We use Techspray - Zero Charge Hand Lotion (anti-static. no silicone,
lanolin, non-contaminating)

Tom

Liane Williams wrote:
>
> Hi Stu,
>
> I am not sure about the best lotion for your particular application, but
working
> in a lab and workshop I would offer the following advice:
>
> Look for something neutral & and scent free.
>
> I use "silicone barrier cream", non-perfumed, non-toxic, antiseptic, water
> repellant.
>
> You don't need much and it keeps your hands free of any irritations.
> I have used it for 4 years now.  I am the only one in my workshop and the
> tube is nowhere near finished - still on same bottle and it wasn't even
new
> when I got here.  Lasting that long, you could supply one per station!
>
> Purchased from NZ Safety Limited in Auckland, New Zealand.
> I am sure similar products are available anywhere.
>
> Cheers
> Liane.
>
> Physics Technician
> Faculty of Health & Sciences
> CPIT
> [log in to unmask]
> ph 9408330
>
>
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Date:         Tue, 15 Jan 2002 10:01:39 NZT
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Liane Williams <[log in to unmask]>
Organization: Christchurch Polytechnic
Subject:      hand lotion
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=US-ASCII
Content-transfer-encoding: 7BIT

Oh,  fair enough.

I regularly solder (albeit not as much as an manufacturing assembler), and
haven't had any problems .

But, like I said,  I am not familiar with your particular application.
Learnt something new.

Regards
Liane.

Date sent:              Mon, 14 Jan 2002 15:41:53 -0500
Send reply to:          "TechNet E-Mail Forum." <[log in to unmask]>
From:                   Tom Parkinson - Quality Assurance Manager <[log in to unmask]>
Organization:           WinTronics, Inc.
Subject:                Re: [TN] hand lotion
To:                     [log in to unmask]

> SILICONE??? Isn't getting silicone on a solderable surface the death of
> trying to get a solder joint?
>
> We use Techspray - Zero Charge Hand Lotion (anti-static. no silicone,
> lanolin, non-contaminating)
>
> Tom
>

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Date:         Mon, 14 Jan 2002 15:01:23 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tenison Stone <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Be careful with this lotion.  It made me break out on my hands.  I had to
go back to I.C. Lotion.  I have never been allergic to any hand lotion in
the normal drugstore, so I don't know why this one bothered me.

Tenison Stone
Telex Communications






"Olinger, Patty" <[log in to unmask]>@IPC.ORG> on 01/14/2002 02:09:25 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  Re: [TN] hand lotion


Stu,
We use Techspray Zero Charge Hand Lotion P/N: 1702-8FP. Smells o.k. All
our operators seem to like it. Hope this helps, ask for samples, that's
what I do.

Patty Olinger
Manufacturing Engineer
Projects Unlimited
(937)918-2267
[log in to unmask]


-----Original Message-----
From: Stuart Korringa [mailto:[log in to unmask]]
Sent: Monday, January 14, 2002 2:49 PM
To: [log in to unmask]
Subject: [TN] hand lotion


What are some acceptable hand lotions that could be purchased by my
company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


**********************************************************************
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Date:         Mon, 14 Jan 2002 15:30:06 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: hand lotion
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_BBE6C9E1.4E2F427B"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_BBE6C9E1.4E2F427B
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

Chemtronics has a good lotion it is called static free hand guard.  I =
haven't broken out from it and it actually works.  I have had problems =
with the IC Lotion. =20

Kathy

--=_BBE6C9E1.4E2F427B
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Chemtronics has a good lotion it is called static free hand guard.&nbsp; I
haven't broken out from it and it actually works.&nbsp; I have had problems with
the IC Lotion.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy</DIV></BODY></HTML>

--=_BBE6C9E1.4E2F427B--

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=========================================================================
Date:         Mon, 14 Jan 2002 13:40:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: Virus and Reply-To issues
MIME-Version: 1.0
Content-Type: text/plain

It doesn't work in Exchange either.

> ----------
> From:
> [log in to unmask][SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Monday, January 14, 2002 9:29 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Virus and Reply-To issues
>
> Keach,
> Just so you know, the Reply to All function does not work in Lotus Notes.
> All my off line replies have to be manually entered.
>
> Doug Pauls
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
> SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
>

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=========================================================================
Date:         Mon, 14 Jan 2002 16:54:47 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Clements John <[log in to unmask]>
Subject:      Re: Virus and Reply-To issues
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

It also doesn't work in Outlook.

-----Original Message-----
From: Mcmaster, Michael [mailto:[log in to unmask]]
Sent: Monday, January 14, 2002 4:40 PM
To: [log in to unmask]
Subject: Re: [TN] Virus and Reply-To issues


It doesn't work in Exchange either.

> ----------
> From:
> [log in to unmask][SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Monday, January 14, 2002 9:29 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Virus and Reply-To issues
>
> Keach,
> Just so you know, the Reply to All function does not work in Lotus Notes.
> All my off line replies have to be manually entered.
>
> Doug Pauls
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
> SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
>

----------------------------------------------------------------------------
-----
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ext.5315
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=========================================================================
Date:         Mon, 14 Jan 2002 16:30:30 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Keach Sasamori <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Keach Sasamori <[log in to unmask]>
Subject:      Reply-To Issues
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

I've reset the Technet List so that a <Reply-To> will reply back to =
Technet and the original poster.

Lets see if this works.



______________
Keach Sasamori
IS Administrator
IPC
2215 Sanders Rd.
Northbrook, IL 60062
Ph: (847) 790-5315=20
Fax: (847) 504-2315
e-mail: [log in to unmask]

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=========================================================================
Date:         Mon, 14 Jan 2002 18:09:50 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Peter Codella <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Peter Codella <[log in to unmask]>
Subject:      Company Phone Number:.
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding:  7bit

Phone Number: 886-3-465-3096
Email: [log in to unmask]

Company FTP Server:
___ UNIX,   X  Microsoft, ___Other  If other what?: ________________________________
FTP IP Address :       203.65.184.5
Or Host name:          HYPERLINK "ftp://ftp.maxedge.com.tw" ftp.maxedge.

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---------------------------------------------------------------------------------
=========================================================================
Date:         Mon, 14 Jan 2002 15:29:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain

If you're talking about a Class 2 board, .010" over would be good, but for
Class 3, there's a 0.001" annular ring requirement.  Because of that, you
should increase to 0.012".

You'll find a good series of e-mails on the benefits and detractions of
leaving unused pads in the board in the Technet archives from Feb 1999.

> ----------
> From:         Stephen Gregory[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Friday, January 11, 2002 5:55 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Remove unused "dead" pads on internal layers
>
> Hi again Pat,
>
> That sounds okay to me, within the the tolerances that are spec'd out for
> drilling, right?
>
> What I can do is look at the gerbers for the board that I was talking
> about in my case, and do a quick check to see what the diameter was on
> those pads...but can't do that until Monday.
>
> -Steve Gregory-
>
>
>
>
>       Thanks Steve,
>
>       Would 0.010" over the finished hole size be good pad size to be used
> on internal
>       layers?
>
>       Thanks,
>       Pat
>
>
>
>
>

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=========================================================================
Date:         Mon, 14 Jan 2002 15:30:04 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: Virus and Reply-To issues
MIME-Version: 1.0
Content-Type: text/plain

There's not much left, is there?

> ----------
> From:         Clements John[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Monday, January 14, 2002 1:54 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Virus and Reply-To issues
>
> It also doesn't work in Outlook.
>
> -----Original Message-----
> From: Mcmaster, Michael [mailto:[log in to unmask]]
> Sent: Monday, January 14, 2002 4:40 PM
> To: [log in to unmask]
> Subject: Re: [TN] Virus and Reply-To issues
>
>
> It doesn't work in Exchange either.
>
> > ----------
> > From:
> > [log in to unmask][SMTP:[log in to unmask]]
> > Reply To:     TechNet E-Mail Forum.
> > Sent:         Monday, January 14, 2002 9:29 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] Virus and Reply-To issues
> >
> > Keach,
> > Just so you know, the Reply to All function does not work in Lotus
> Notes.
> > All my off line replies have to be manually entered.
> >
> > Doug Pauls
> >
> >
> --------------------------------------------------------------------------
> > -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
> in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
> > SET Technet NOMAIL
> > To receive ONE mailing per day of all the posts: send e-mail to
> > [log in to unmask]: SET Technet Digest
> > Search previous postings at: www.ipc.org > On-Line Resources & Databases
> >
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
> --------------------------------------------------------------------------
> > -------
> >
>
> --------------------------------------------------------------------------
> --
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Technet NOMAIL
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> --
> -----
>
> --------------------------------------------------------------------------
> -------
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> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
>

---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date:         Mon, 14 Jan 2002 21:05:34 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: finish
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

In a message dated 1/14/02 7:33:36 AM Pacific Standard Time,
[log in to unmask] writes:

> Amazingly, I have seen HASL surfaces very flat, shiney, bright, and
>  solderable

Earl:  I also have seen such surfaces....and I remember clearly where I saw
them.

The salient features of the process were:

A CONTINUOUS process line....essentially ZERO time, between processes.
Oxide removal--(usually done with a microetch)....in this case done with a
cleaner that removed only a trace of Copper, then, rinse, barely dry
(unheated), flux application, then to HASL immediately....beautiful results,
pretty and flatter than I have ever seen elsewhere.

Well done, its almost a shame HASL cannot be used universally.

Rudy Sedlak
RD Chemical Company

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=========================================================================
Date:         Mon, 14 Jan 2002 22:08:37 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: finish
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Earl,

While we have you, don't keep us in suspense any longer. Please, is it:
* Six additional weeks of winter?  ...  OR
* Early spring?

Dave Fish

----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 14, 2002 7:24 AM
Subject: Re: [TN] finish


> Guy,
>
> The cave is quite resplendent with most ameneties. HASL is not one of
them.
>
> Werner once responded, accurately, any process can be mis-managed as in
the
> HASL thing. One thing that cannot be managed is the copper surface of a
> board about to enter HASL hell. The copper surface is cleaned,
micro-etched,
> rinsed, dried (wherein the biggest process mis-management occurs), then
> introduced to fluxes often incapable of removing the oxidation imparted by
> the drying process. This is my big gripe against HASL now that I've grown
so
> fond of very "thick" IMC's.
>
> Amazingly, I have seen HASL surfaces very flat, shiney, bright, and
> solderable. I don't remember where I saw this phenomonom. Probably in my
> dreams but it was a wonder. I also wonder, if it was not a dream, where
> these conditions were produced. Any board fab folks out there?
>
> As for popping my head out of the cave, it gets very lonely in here, or
not,
> and fresh air always is appreciated. However, I'm not a weather reporter
> based on shadow. What's with this strange passage. No snow covering my
cave
> opening.
>
> MoonMan
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>

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---------------------------------------------------------------------------------
=========================================================================
Date:         Tue, 15 Jan 2002 09:27:58 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I recommend that hands be washed thoroughly and rinsed even more
thoroughly with NO hand lotion before entering the assembly area. Here
is a typical formulation of a hand lotion
Aqua (water)
Paraffinum liquidum (mineral oil)
Propylene glycol (hygroscopic surfactant)
Propylene glycol stearate (hygroscopic and ionic ester)
Cetearyl alcohol
Stearic acid (ionic carboxylic acid)
Parfum (fragrance)
Triethanolamine (ionic saponifier)
PEG30 (polyethylene glycol, hygroscopic)
Lanolin (animal fat)
Methylparaben (goodness knows!)
Propylparaben (ditto)
Sodium lauryl sulfate (ionic surfactant- hygroscopic)
PEG75/lanolin blend (see PEG30 and lanolin)
P-chloro-M-cresol-BHT (whatever that may be)
Colours
This is taken off the bottle of a well known make.

Which of these products would you like to see on your assemblies?

It is dangerous to allow a specific "safe" make: operators will still
prefer their own and there is no way you can prevent them from using it.
As for so-called anti-static ones: this is a sales gimmick that means
that they have an extra dose of hygroscopic surfactants which is one of
the last things you wish on an assembly. So, if you wish to respect the
electrical integrity of your assemblies: NO HAND CREAMS.

Brian


Stuart Korringa wrote:
>
> What are some acceptable hand lotions that could be purchased by my company for
> distribution to the assembly areas? There must be something that is not
> repugnant and would make the operators be happy to use.
>
> Thanks,
>
> Stu Korringa
>
> Smiths Electronic Systems
> Grand Rapids, Mi
>
> **********************************************************************
> This e-mail and any files transmitted with it are confidential and may
> be legally privileged or otherwise exempt from disclosure under
> applicable law. This e-mail and its files are intended solely for
> the individual or entity to whom they are addressed and their content
> is the property of Smiths Aerospace.  If you are not the intended
> recipient, please do not read, copy, use or disclose this communication.
> If you have received this e-mail in error please notify the e-mail
> administrator at [log in to unmask] and then delete this e-mail, its
> files and any copies.
>
> This footnote also confirms that this e-mail message has been scanned
> for the presence of known computer viruses.
> ***********************************************************************
>
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------

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=========================================================================
Date:         Mon, 14 Jan 2002 23:51:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Peter Lee <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Peter Lee <[log in to unmask]>
Subject:      RF Shield Plating
In-Reply-To:  <001401c19d8b$13452c80$4bc9d7cc@davidfis>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Hi,

Does anyone know what is the most common plating finish specified on the
PCB RF shielding? I have seen poor solderability on shields with nickel
finish compared with tin finish after SMT reflow soldering.

Should the RF performance a concern when selecting the proper plating
material?


Rgds,
Peter



_________________________________________________________
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=========================================================================
Date:         Tue, 15 Jan 2002 10:21:58 +0100
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Matthias Mansfeld <[log in to unmask]>
Organization: Matthias Mansfeld Elektronik
Subject:      OT good E-Mail clients, was: Re: [TN] Virus and Reply-To issues
In-Reply-To:  <9268B357A320D511B61A0002A507CE5E024CE0FF@FGMAIL01>
MIME-Version: 1.0
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On 14 Jan 2002 at 15:30, and earlier Mcmaster, Michael et al. wrote:

> There's not much left, is there?
[...]
> > It also doesn't work in Outlook.
[...]
> > It doesn't work in Exchange either.
> >
[...]
> > > Just so you know, the Reply to All function does not work in Lotus
> > > Notes.
> > > All my off line replies have to be manually entered.
...
If you can choose freely, perhaps consider under any Windows using a REAL e-
mail client like Pegasus. It is freeware, has many options to select the adress of a
reply (no need to reenter manually any of the original adresses) and BTW it seems
not to be able to run any of the virus containing stuff. A lot of normally executable
file extensions are hardcoded as "only save to disk allowed". And it has it's own
HTML-viewer for formatted mails, thus is doesn't suffer from the IE/Outlook
(Express) safety holes which made the spreading of the latest worms possible.

URL is http://www.pmail.com

Regards
Matthias Mansfeld

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Date:         Tue, 15 Jan 2002 05:22:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: hand lotion
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Stewart, some of the old original hand lotions smelled like cow poop, but
the newer ones have a more pleasing fragrance. Try "IC Lotion" and some of
the newer types.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Stuart Korringa [mailto:[log in to unmask]]
                Sent:   Monday, January 14, 2002 14:49 PM
                To:     [log in to unmask]
                Subject:        [TN] hand lotion

                What are some acceptable hand lotions that could be
purchased by my company for
                distribution to the assembly areas? There must be something
that is not
                repugnant and would make the operators be happy to use.

                Thanks,

                Stu Korringa

                Smiths Electronic Systems
                Grand Rapids, Mi



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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2652.35">
<TITLE>RE: [TN] hand lotion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Stewart, some of the old original hand =
lotions smelled like cow poop, but the newer ones have a more pleasing =
fragrance. Try "IC Lotion" and some of the newer types.</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Stuart Korringa =
[<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>=
]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Monday, January 14, 2002 14:49 PM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">[TN] hand lotion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">What are some acceptable hand lotions =
that could be purchased by my company for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">distribution to the assembly areas? =
There must be something that is not</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">repugnant and would make the =
operators be happy to use.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Stu Korringa</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Smiths Electronic Systems</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Grand Rapids, Mi</FONT>
</P>
<BR>

<P><FONT SIZE=3D2 =
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<BR><FONT SIZE=3D2 FACE=3D"Arial">This e-mail and any files transmitted =
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<BR><FONT SIZE=3D2 FACE=3D"Arial">the individual or entity to whom they =
are addressed and their content</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">is the property of Smiths =
Aerospace.&nbsp; If you are not the intended</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">recipient, please do not read, copy, =
use or disclose this communication.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">If you have received this e-mail in =
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Date:         Tue, 15 Jan 2002 05:02:49 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: finish
X-To:         "David H. Fish" <[log in to unmask]>

Dave,

Not meaning to offend, but I threw out a little honey there to see how many
flies I could catch. Didn't mean it to be you. That brings to mind - who
said you can catch the most flies with dead squirels?

Winter, are you serious? Hell, I came out of my hole for a peek expecting to
see a frozen wasteland. Just saw the waste. They have huge "land" fills here
in Michigan and folks from Canada even dump here. When finished, these waste
piles are sometimes turnned into ski slopes. Thought I'd seen it all.

Actually, I was dangling my hook for someone in the AOI industry to come
forward and smash my comments about how immature the current equipment and
process is. I said the stuff was only good determining attributes instead of
variables. What I want to know the state of art/science concerning this
technology and how it could be used in the DFM process if capable of
providing hard data correlating findings to reliability requirements, or
some such thing.

Anyone have the latest on AOI and/or where it is headed?

Enjoy the Spring without ever having had Winter,

Earl

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Date:         Tue, 15 Jan 2002 05:10:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: finish
X-To:         "<Rudy Sedlak>" <[log in to unmask]>

Thanks Rudy for making me realize I wasn't dreaming. I mean that stuff
almost changed my mind about HASL. Not quite, however.

I now remember where I saw it ONCE. It was at Gary's old shop in
Connecticut. What was its name again? Besides the excellent surface finish,
they never allowed 7628 glass style material to face anything but higher
resin content materials. My heroes but for their lab and lack of SPC.

Going back underground for a bit expecting summer fun next peek outside
(probably within days) - unless, of course, something more exciting, but no
less less important, than the subject of hand lotions shows up

MoonMan

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Date:         Tue, 15 Jan 2002 05:17:00 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         Peter Lee <[log in to unmask]>

Peter,

You have to have solderable surfaces. Ni, most often, is not one. Often,
these shields, fences, mode blocks, or R/F barriers by other names are
formed of other materials as well. German silver, or so it's called, often
is used and it is a total bitch to solder without very active OA flux
application. We sure don't want that.

Pre-tinned surfaces often do well. Using bolted aluminum mode blocks work
better but for size. I know you're at your customer's mercy here so you
should try fluxing the tabs and tinning them before attempting installation.
Only problem there might be the limited slot sizes.

Earl Moon

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Date:         Tue, 15 Jan 2002 07:54:54 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

It seems like the consensus is not to use "plated shut" vias in my design
(thermal vias, if you recall), but to fill the vias with a thermally
conductive adhesive (CB10?) and copper plate over the top.  Now the
questions are, what other conductive adhesives are out there that can be
plated over, and which board shops can do this (low volume, class 3)?  I
know that ALL board shops CAN do everything, but I'm really interested in
those who HAVE done this with good success.

Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   Don Vischulis [SMTP:[log in to unmask]]
        Sent:   Thursday, January 10, 2002 5:18 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        Jim

        IMO you should avoid true plated shut vias.  As holes plate in an
        electrolytic process, the outer portion of the hole plates faster
than the
        portion of the barrel that is near the center of board (dog bone
plating).
        This can result in trapped chemicals in the barrel of the hole.  As
an
        alternative you might consider plugging the holes with a conductive
epoxy
        such as DuPont's CB100.  A .021 dia hole in a .062 thick board is
within the
        capability of several board shops.  You will most likely find this
        capability with shops that build high reliability products.

        The holes are plugged before the final finish is applied, and they
should
        provide a flat final surface on the finished board.

        Don Vischulis

        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
        Sent: Thursday, January 10, 2002 3:55 PM
        To: [log in to unmask]
        Subject: [TN] VIAS PLATED CLOSED


        Good day technet:

        We're considering designing a multilayer polyimide PWB with a number
of vias
        (approximately .021" diameter holes, .062" thick PWB) that are
plated shut,
        for thermal reasons.  Can anyone comment on pitfalls regarding the
fab
        process?  How about voids in the solid copper via?  Entrapped
plating
        solution?

        All comments are appreciated.  Thanks in advance...

        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879


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Date:         Tue, 15 Jan 2002 08:23:56 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Oh, one more thing, the board shop has to have experience with CIC voltage
and ground planes.
Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   Marsico, James
        Sent:   Tuesday, January 15, 2002 7:55 AM
        To:     'TechNet E-Mail Forum.'
        Subject:        RE: [TN] VIAS PLATED CLOSED

        It seems like the consensus is not to use "plated shut" vias in my
design (thermal vias, if you recall), but to fill the vias with a thermally
conductive adhesive (CB10?) and copper plate over the top.  Now the
questions are, what other conductive adhesives are out there that can be
plated over, and which board shops can do this (low volume, class 3)?  I
know that ALL board shops CAN do everything, but I'm really interested in
those who HAVE done this with good success.

        Thanks again,
        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879

                -----Original Message-----
                From:   Don Vischulis [SMTP:[log in to unmask]]
                Sent:   Thursday, January 10, 2002 5:18 PM
                To:     [log in to unmask]
                Subject:        Re: [TN] VIAS PLATED CLOSED

                Jim

                IMO you should avoid true plated shut vias.  As holes plate
in an
                electrolytic process, the outer portion of the hole plates
faster than the
                portion of the barrel that is near the center of board (dog
bone plating).
                This can result in trapped chemicals in the barrel of the
hole.  As an
                alternative you might consider plugging the holes with a
conductive epoxy
                such as DuPont's CB100.  A .021 dia hole in a .062 thick
board is within the
                capability of several board shops.  You will most likely
find this
                capability with shops that build high reliability products.

                The holes are plugged before the final finish is applied,
and they should
                provide a flat final surface on the finished board.

                Don Vischulis

                -----Original Message-----
                From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico,
James
                Sent: Thursday, January 10, 2002 3:55 PM
                To: [log in to unmask]
                Subject: [TN] VIAS PLATED CLOSED


                Good day technet:

                We're considering designing a multilayer polyimide PWB with
a number of vias
                (approximately .021" diameter holes, .062" thick PWB) that
are plated shut,
                for thermal reasons.  Can anyone comment on pitfalls
regarding the fab
                process?  How about voids in the solid copper via?
Entrapped plating
                solution?

                All comments are appreciated.  Thanks in advance...

                Jim Marsico
                Senior Engineer
                Production Engineering
                EDO Electronics Systems Group
                [log in to unmask] <mailto:[log in to unmask]>
                631-595-5879


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Date:         Tue, 15 Jan 2002 13:40:50 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are you
building to drawing or is there a clause that says process improvements that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
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Date:         Tue, 15 Jan 2002 08:58:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Alcorn, Brent" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Alcorn, Brent" <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----_=_NextPart_001_01C19DCC.B5DA5B00"

This message is in MIME format. Since your mail reader does not understand
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------_=_NextPart_001_01C19DCC.B5DA5B00
Content-Type: text/plain;
        charset="iso-8859-1"

In a previous life we used Staticide from Static Control Components,
Inc.  It is non-contaminating and worked well.

-Brent

BM__MailData

 -----Original Message-----
From:   Stuart Korringa [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent:   Monday, January 14, 2002 14:49 PM
To:     [log in to unmask]
Subject:        [TN] hand lotion

        What are some acceptable hand lotions that could be purchased by
my company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

        Thanks,

        Stu Korringa

        Smiths Electronic Systems
Grand Rapids, Mi



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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>

<TITLE>RE: [TN] hand lotion</TITLE>

<META content="MSHTML 5.50.4807.2300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=320585513-15012002><FONT face=Arial color=#0000ff size=2>In a
previous life&nbsp;we&nbsp;used Staticide from Static Control Components,
Inc.&nbsp; It is non-contaminating and worked well.&nbsp;</FONT></SPAN></DIV>
<DIV><SPAN class=320585513-15012002></SPAN><FONT face=Arial color=#0000ff
size=2><SPAN class=320585513-15012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=320585513-15012002>-Brent</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=320585513-15012002></SPAN></FONT>&nbsp;</DIV>
<DIV><A name=_MailData><FONT face=Arial color=#0000ff size=2></FONT>&nbsp;</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial><FONT size=2><SPAN
class=320585513-15012002>&nbsp;</SPAN>-----Original
Message-----</FONT></FONT></A> <BR><B><FONT face=Arial size=2>From:&nbsp;&nbsp;
Stuart Korringa [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT></B>
<BR><B><FONT face=Arial size=2>Sent:&nbsp;&nbsp;</FONT></B> <FONT face=Arial
size=2>Monday, January 14, 2002 14:49 PM</FONT> <BR><B><FONT face=Arial
size=2>To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT face=Arial
size=2>[log in to unmask]</FONT> <BR><B><FONT face=Arial
size=2>Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT
face=Arial size=2>[TN] hand lotion</FONT> </DIV>
<BLOCKQUOTE>
  <UL>
    <UL>
      <P><FONT face=Arial size=2>What are some acceptable hand lotions that
      could be purchased by my company for</FONT> <BR><FONT face=Arial
      size=2>distribution to the assembly areas? There must be something that is
      not</FONT> <BR><FONT face=Arial size=2>repugnant and would make the
      operators be happy to use.</FONT> </P>
      <P><FONT face=Arial size=2>Thanks,</FONT> </P>
      <P><FONT face=Arial size=2>Stu Korringa</FONT> </P>
      <P><FONT face=Arial size=2>Smiths Electronic Systems</FONT> <BR><FONT
      face=Arial size=2>Grand Rapids, Mi</FONT> </P><BR>
      <P><FONT face=Arial
      size=2>**********************************************************************</FONT>
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      intended</FONT> <BR><FONT face=Arial size=2>recipient, please do not read,
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Date:         Tue, 15 Jan 2002 13:59:15 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Diamond, Pat" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Diamond, Pat" <[log in to unmask]>
Subject:      Re: Anodised Aluminium wire
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Phil & Steven

thanks for your reponses, in answer to your questions, this product is used
in a speed probe on the Eurofighter engine to measure the speed of the high
pressure turbine.  The probe will typically see temperatures of around 300
degrees C at the front end, therefore we cannot use other high temp.
coatings such as polyimide.

We terminate this wire by skeining it 5 times and inserting into an
aluminium sleeve. We then fit a Stainless Steel sleeve over the aluminium
one, crimp it all together and resistance weld this assembly.  The welding
process then breaks down the anodising at the connection area.


regards

Pat Diamond

-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 2:02 PM
To: [log in to unmask]
Subject: Re: [TN] Anodised Aluminium wire


Pat,

Not knowing what your end use is, I am intrigued by anodized aluminum wire.
Anodizing, by definition, is an insulator. I would understand irridite as a
coating for aluminum.

How would this be used, terminated, etc.?

Phil Nutting

-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 3:29 AM
To: [log in to unmask]
Subject: [TN] Anodised Aluminium wire


I am looking for information on a supplier for anodised aluminium wire, the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Tue, 15 Jan 2002 08:21:27 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      OLD TIME MIL STD FOLKS ONLY, OR NOT

Old folks, besides Ron D and me, which MIL-STD-217 doc is which. Everything
has been cancelled as we all know. Is 217 the "How To Write" document or?

MoonMan

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Date:         Tue, 15 Jan 2002 09:44:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tempea, Ioan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
MIME-Version: 1.0
Content-Type: text/plain

Hi Earl,
if you go at http://astimage.daps.dla.mil/quicksearch/ and type 217 in the
Document number box, here's what you get "MIL-STD-217, PREPARATION OF
MANUSCRIPT (FINAL-TYPED) FOR TECHNICAL MANUALS (S/S BY MIL-STD-218)".
This does not mean that I have your so many years in the business, but only
that I diligently bookmark all the interesting links this super forum comes
up with.
Regards,
Ioan


> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Tuesday, January 15, 2002 9:21 AM
> To:   [log in to unmask]
> Subject:      [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT
>
> Old folks, besides Ron D and me, which MIL-STD-217 doc is which.
> Everything
> has been cancelled as we all know. Is 217 the "How To Write" document or?
>
> MoonMan
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
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Date:         Tue, 15 Jan 2002 08:39:41 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         Ioan Tempea <[log in to unmask]>

Ioan,

Without aging a bit, you are a splendid repository of imense knowledge and
wisdom beyond your years. However, been there and done that.

217 has bee SS'd but by what? Can you find that answer for me?

MoonMan

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Date:         Tue, 15 Jan 2002 10:23:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Creswick, Steven" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Creswick, Steven" <[log in to unmask]>
Subject:      Re: Anodised Aluminium wire
X-To:         "Diamond, Pat" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Pat,

Will just plain (self passivating) aluminum wire work?

Steve Creswick - Gentex

-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 8:59 AM
To: [log in to unmask]
Subject: Re: [TN] Anodised Aluminium wire


Phil & Steven

thanks for your reponses, in answer to your questions, this product is used
in a speed probe on the Eurofighter engine to measure the speed of the high
pressure turbine.  The probe will typically see temperatures of around 300
degrees C at the front end, therefore we cannot use other high temp.
coatings such as polyimide.

We terminate this wire by skeining it 5 times and inserting into an
aluminium sleeve. We then fit a Stainless Steel sleeve over the aluminium
one, crimp it all together and resistance weld this assembly.  The welding
process then breaks down the anodising at the connection area.


regards

Pat Diamond

-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 2:02 PM
To: [log in to unmask]
Subject: Re: [TN] Anodised Aluminium wire


Pat,

Not knowing what your end use is, I am intrigued by anodized aluminum wire.
Anodizing, by definition, is an insulator. I would understand irridite as a
coating for aluminum.

How would this be used, terminated, etc.?

Phil Nutting

-----Original Message-----
From: Diamond, Pat [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 3:29 AM
To: [log in to unmask]
Subject: [TN] Anodised Aluminium wire


I am looking for information on a supplier for anodised aluminium wire, the
problem is that the wire must be between 005" and 006" in diameter.

Can anyone help?

regards,

Pat Diamond

Weston Aerospace

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Date:         Tue, 15 Jan 2002 10:56:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Creswick, Steven" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Creswick, Steven" <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Earl,

I am quite sure that Mil-Std 217 - Preparation of Manuscript for Tech
Manuals, or some such similar title, was superceeded by Mil-Std 218.  I also
recall that 218 was a 3 'parter', but do not recall if it is still active or
not.  Been quite a while!

Mil-Hdbk-217 is on Reliability Prediction

Not sure where to get either one at the moment.  Would have to do some web
searching, etc.


Now that you know this, we may have to shoot you.  :-)

Steve Creswick - Gentex Corp

-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 9:21 AM
To: [log in to unmask]
Subject: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT


Old folks, besides Ron D and me, which MIL-STD-217 doc is which. Everything
has been cancelled as we all know. Is 217 the "How To Write" document or?

MoonMan

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Date:         Tue, 15 Jan 2002 08:22:19 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         Peter Lee <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT

We use thousands of Rf shields per month, our shields are not plated in
general. We use an alloy 770 (or alloy 752) half hard temper as the base
material. Both have excellent solderability, and in general good electrical
spec. the thermal coefficients are also good for electronics. Since the
material is silver by nature no plate is required, and the shelf life of the
finish is indefinite.

Hope this helps.
Dan
P.S.:
Alloy 770; 55%Cu, 27%Zn, 18%Ni, seems to be most common in domestic sources.
Alloy 752; 69%Cu, 17%Zn, 18%Ni, seems to be most common with Asian sources.

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Date:         Tue, 15 Jan 2002 08:30:11 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              JaMi Smith <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         JaMi Smith <[log in to unmask]>
Subject:      Re: hand lotion
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

I don't know how well this would go over with the gals out on the line,
but I have found myself pulling double duty as either a Development
Technician or an RF Technician for these past several years, where I
would do a lot of prototype assembly and PCB mod work in an "open bench
environment", and the one thing that I have found that is indispensable
in fighting static (especially at this time of the year) is using
"Vitalus" in my hair so that I don't build up any static charges in the
first place

JaMi Smith

-----Original Message-----
From: Stuart Korringa [mailto:[log in to unmask]]=20
Sent: Monday, January 14, 2002 11:49 AM
To: [log in to unmask]
Subject: [TN] hand lotion

What are some acceptable hand lotions that could be purchased by my
company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


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Date:         Tue, 15 Jan 2002 10:24:51 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         "Dan R. Johnson" <[log in to unmask]>

Dan,

Can't thank you enough. I'm sure Peter thanks you as well. His problems
seems a bit different with the Ni finish. Any suggestions?

The German silver thing occurred using shields on R/F filters. It happened
several times so I contacted someone at HAC and they recommended the "pink
death" flux that did the job but not without regrets.

Thanks again,

Earl Moon

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Date:         Tue, 15 Jan 2002 10:27:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         S Creswick <[log in to unmask]>

Steve,

Again, thanks. I think this may be a handbook thing as well. The request was
somewhat vague. I'll theck it out as I really don't want another writing
lesson though most think it necessary.

Earl

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Date:         Tue, 15 Jan 2002 11:45:53 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Micro-BGA definition?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello technetters,

How is micro-BGA defined in the industry? By body size, pitch and/or ball
size?

What is the IPC referring document for this definition?

Thanks in advance,

Alain Savard
QA - PCB
CAE Inc.

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Date:         Tue, 15 Jan 2002 10:49:55 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Actually the cracked vias I have witnessed in the inter barrell tend to start at
the intersection of the copper planes. A corner or stress riser starts the crack
during thermal shock tests. Don't understand how the extra non- connected pads
could help barrell, if so then there is no hope for a 2 sided board.







"Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]> on 01/15/2002
07:40:50 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      "Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]>








 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Remove unused "dead" pads on internal
           layers








Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are you
building to drawing or is there a clause that says process improvements that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
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=========================================================================
Date:         Tue, 15 Jan 2002 10:52:15 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: hand lotion
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

You can also use Vaseline in your hair as well....getting it out may be a =
problem, though.

Jason

>>> [log in to unmask] 01/15/02 10:30AM >>>
I don't know how well this would go over with the gals out on the line,
but I have found myself pulling double duty as either a Development
Technician or an RF Technician for these past several years, where I
would do a lot of prototype assembly and PCB mod work in an "open bench
environment", and the one thing that I have found that is indispensable
in fighting static (especially at this time of the year) is using
"Vitalus" in my hair so that I don't build up any static charges in the
first place

JaMi Smith

-----Original Message-----
From: Stuart Korringa [mailto:[log in to unmask]]=20
Sent: Monday, January 14, 2002 11:49 AM
To: [log in to unmask]
Subject: [TN] hand lotion

What are some acceptable hand lotions that could be purchased by my
company for
distribution to the assembly areas? There must be something that is not
repugnant and would make the operators be happy to use.

Thanks,

Stu Korringa

Smiths Electronic Systems
Grand Rapids, Mi


**********************************************************************
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Date:         Tue, 15 Jan 2002 11:54:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              James TerVeen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         James TerVeen <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

In a past life we used brass shields that were tin/lead plated.  They were
a few mils thick and were etched and with forming grooves for the operator
to bend at installation.  This worked very well and never had a soldering
problem.



                    Earl Moon
                    <[log in to unmask]       To:     [log in to unmask]
                    .COM>                cc:
                    Sent by:             Subject:     Re: [TN] RF Shield Plating
                    TechNet
                    <[log in to unmask]
                    RG>


                    01/15/02 11:24
                    AM
                    Please respond
                    to "TechNet
                    E-Mail
                    Forum.";
                    Please respond
                    to Earl Moon






Dan,

Can't thank you enough. I'm sure Peter thanks you as well. His problems
seems a bit different with the Ni finish. Any suggestions?

The German silver thing occurred using shields on R/F filters. It happened
several times so I contacted someone at HAC and they recommended the "pink
death" flux that did the job but not without regrets.

Thanks again,

Earl Moon

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Date:         Tue, 15 Jan 2002 08:59:34 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         Earl Moon <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT

The only flux I have had any success with on nickel also was used for
stainless, and removing auto finishes ;). Earls approach is probably best
for existing inventory, but switching over to another alloy would be my
first choice, git rid of the root cause, etc. blah,blah.
Dan

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Date:         Tue, 15 Jan 2002 09:37:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: RF Shield Plating
X-To:         James TerVeen <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT

The advantage of nickel silver is you skip a plate process, and you don't
have to worry about scratches. We use a few brass shields that are "bright
tin" plated. Not really sure what the spec for "bright" is but when it was
omitted on a PO the parts we got looked like they were galvanized. In
general the look's of the plated parts aren't as good.
Dan

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Date:         Tue, 15 Jan 2002 09:26:39 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Debbie Goodwin <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Debbie Goodwin <[log in to unmask]>
Subject:      Re: Micro-BGA definition?
X-To:         Alain Savard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

MicroBGA is a package name that is Trademarked by Tessera.  Packages that
are sold as microBGA must be either made by Tessera or licensed by Tessera
to build microBGA.

These packages vary in body size, lead count, and lead pitch.  The micro BGA
packages are used for flash memory and Rambus memory devices, to name a few.

The technology of the package and how it is built defines microBGA.  I would
check with Tessera (www.tessera.com) for more information.

Sincerely,

Debbie Goodwin
Account Representative
10867 Portal Dr
Los Alamitos, CA 90720
Phone = (714) 252-0010
Fax = (714) 252-0026
PLEASE NOTE - Effective Immediately New e-mail address is:
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-----Original Message-----
From: Alain Savard [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 8:46 AM
To: [log in to unmask]
Subject: [TN] Micro-BGA definition?


Hello technetters,

How is micro-BGA defined in the industry? By body size, pitch and/or ball
size?

What is the IPC referring document for this definition?

Thanks in advance,

Alain Savard
QA - PCB
CAE Inc.

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Date:         Tue, 15 Jan 2002 12:35:47 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Steve Underwood <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Can someone/anyone please send me or direct me to a study that concluded
that removing "a land that is not connected electrically to the conductive
pattern on its layer" decreased reliability in any way?  How about a study
that concluded a maintained or increased reliability by keeping or adding
non-functional pads?  ...I cannot find anything in the IPC specifications
discouraging the removal of non-functional pads.

From practical fabrication experience, removing a non-functional pad does
provide benefits:
1) It is easier to drill through less copper, causing less wear on the bit,
thereby increasing the potential quality of the hole.
2) Most importantly, removing the pads does not change connectivity but does
reduce/eliminate a real potential to short to adjacent connections.

Other effects:
1) Apparently, removing all non-functional pads within the via reduces the
overall capacitance of the via (see
http://www.qsl.net/wb6tpu/si-list/0687.html).
2) For some non-plated holes, if the pads are left on and it is drilled
after etch, the land/pad may be ripped off of the surface if there is not
enough ring to anchor the pad.  This only happens on the outer layers.
3) For some applications, a land may be used to anchor the hole connection
to the material (PTFE, flex)
4) Are there other effects?  Thermal, impedance, pth reliability?




-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Tuesday, January 15, 2002 8:41 AM
To: [log in to unmask]
Subject: Re: [TN] Remove unused "dead" pads on internal layers


Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are you
building to drawing or is there a clause that says process improvements that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution
or
other use is prohibited.  If you received this e-mail in error, please
notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Tue, 15 Jan 2002 17:43:34 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hey Warren,

Granted, Drill isn't my specialty but I've always heard that additional pads
in the drilled stack can help.  I'll hazard a guess, since Coombs isn't
readily available, the additional metal gives the bit something to dig into
being softer than the surrounding glass fiber & epoxy resin.   What would be
the benefit of softer layers in a drill stack?  Could that improve hole wall
quality?  Reduce drill wander/wobble?  I'm assuming the right feed, speed
and chip load have been used.  Somebody steer me in the right direction here
- I'm learning.

Obviously, a double sided board doesn't have inner layers and they tend to
be a bit thinner than the high layer count boards I'm used to processing.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 11:50 AM
To: TechNet E-Mail Forum.; Hinners Hans M Civ WRALC/LUGE
Subject: Re: [TN] Remove unused "dead" pads on internal layers




Actually the cracked vias I have witnessed in the inter barrell tend to
start at
the intersection of the copper planes. A corner or stress riser starts the
crack
during thermal shock tests. Don't understand how the extra non- connected
pads
could help barrell, if so then there is no hope for a 2 sided board.







"Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]> on 01/15/2002
07:40:50 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to
      "Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]>











 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Remove unused "dead" pads on internal
           layers








Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are you
building to drawing or is there a clause that says process improvements that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution
or
other use is prohibited.  If you received this e-mail in error, please
notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Tue, 15 Jan 2002 13:03:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Joseph Fjelstad <[log in to unmask]>
Subject:      Re: Micro-BGA definition?
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_d7.11af66c1.2975c8e1_boundary"

--part1_d7.11af66c1.2975c8e1_boundary
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en

Hello Alain,

MicroBGA and uBGA
 are actually registered trademarks of Tessera.=20

The generic term many folks use is "Area Array CSP"=20

There are several definitions floating about

The original definition was:

A packaged IC with a footprint not greater than 1.2x the size of the die

To that have been added...

A packaged IC chip not greater than 1.5 X the volume of the die

A minimally packaged IC chip with a lead pitch of 1.0mm and a size not=20
greater than the die by 1.0mm on each edge

A minimally packaged IC

IPC/ ANSI J-STD- 012 =E2=80=9CImplementation of Flip Chip and Chip Scale Tec=
hnology=E2=80=9D
is a good general reference.

Hope this helps.

Kind regards,=20
Joe

--part1_d7.11af66c1.2975c8e1_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en

<HTML><FONT FACE=3Darial,helvetica><FONT  SIZE=3D2>Hello Alain,
<BR>
<BR>MicroBGA and uBGA
<BR> are actually registered trademarks of Tessera.=20
<BR>
<BR>The generic term many folks use is "Area Array CSP"=20
<BR>
<BR>There are several definitions floating about
<BR>
<BR>The original definition was:
<BR>
<BR>A packaged IC with a footprint not greater than 1.2x the size of the die
<BR>
<BR>To that have been added...
<BR>
<BR>A packaged IC chip not greater than 1.5 X the volume of the die
<BR>
<BR>A minimally packaged IC chip with a lead pitch of 1.0mm and a size not g=
reater than the die by 1.0mm on each edge
<BR>
<BR>A minimally packaged IC
<BR>
<BR>IPC/ ANSI J-STD- 012 =E2=80=9CImplementation of Flip Chip and Chip Scale=
 Technology=E2=80=9D
<BR>is a good general reference.
<BR>
<BR>Hope this helps.
<BR>
<BR>Kind regards,=20
<BR>Joe</FONT></HTML>

--part1_d7.11af66c1.2975c8e1_boundary--

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Date:         Tue, 15 Jan 2002 12:16:59 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Neel, Robert" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Neel, Robert" <[log in to unmask]>
Subject:      Nickel Plating Snarl
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----_=_NextPart_001_01C19DF0.D2A40140"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01C19DF0.D2A40140
Content-Type: text/plain;
        charset="iso-8859-1"

Folks,

Can someone explain to me why all my PCB houses are suddenly having
"spectacular cows" over this pcb plating spec:

"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, MINIMUM
40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

This pcb is the substrate for some snap-acting domes and I need a hard and
conductive bearing surface for the dome feet.  The plating spec comes from
the dome manufacturer.

Is it the "electroless"?  Is it the thickness? Is it the hardness
requirement? Is it the "nickel" vs "nickle"?  (Funny thing is, though,
everyone is very happy to do gold rather than nickel.)

What gives?

Robert

------_=_NextPart_001_01C19DF0.D2A40140
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>Nickel Plating Snarl</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Folks,</FONT>
</P>

<P><FONT SIZE=3D2>Can someone explain to me why all my PCB houses are =
suddenly having &quot;spectacular cows&quot; over this pcb plating =
spec:</FONT>
</P>

<P><FONT SIZE=3D2>&quot;CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, =
50 MILLIONTHS THICK, MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH =
KNOOP PROCESS @ 100 GRAMS&quot;</FONT></P>

<P><FONT SIZE=3D2>This pcb is the substrate for some snap-acting domes =
and I need a hard and conductive bearing surface for the dome =
feet.&nbsp; The plating spec comes from the dome =
manufacturer.</FONT></P>

<P><FONT SIZE=3D2>Is it the &quot;electroless&quot;?&nbsp; Is it the =
thickness? Is it the hardness requirement? Is it the &quot;nickel&quot; =
vs &quot;nickle&quot;?&nbsp; (Funny thing is, though, everyone is very =
happy to do gold rather than nickel.)</FONT></P>

<P><FONT SIZE=3D2>What gives?</FONT>
</P>

<P><FONT SIZE=3D2>Robert</FONT>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01C19DF0.D2A40140--

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Date:         Tue, 15 Jan 2002 12:28:40 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ted Tontis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ted Tontis <[log in to unmask]>
Subject:      VIA in pad
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

        We are working on a new design that might be a candidate for HDI. I
have never had the opportunity to do such a design, but have read plenty of
articles regarding this approach. The main concern is that the engineers
want to place a  8-10 mil VIA's in the pads. I have explained to them that
this will cause soldering problems not mention contamination problems. What
is the cost benefit over laser drilled micro VIA's vs. conductive epoxy
filled vias in pads. Can a VIA survive the reflow and still be defect free?
Are there other concerns that I should be addressing besides the above
mentioned. Your input is greatly appreciated.

Regards,

Ted Tontis C.I.D.
Engage Networks
316 N. Milwaukee Street
Suite 214
Milwaukee WI, 53202
PH 414-273-7600 ext. 7607
FX 414-273-7601

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Date:         Tue, 15 Jan 2002 13:21:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Well drilling is not my thing either, but doing the mechanics the idea that
.0014" thick (1oz) typical, of copper can even affect the drilling is a stretch,
the total glass is about .060 thick and is stacked up many boards thick at a
time in drilling. Glass is harder and much more damaging to metal drills that
very thin copper films. Also the gumming of the epoxies loading the bits would
affect the drilling. All of this can be accounted for in the (hit count) on bits
and they are change automatically.

The amount of copper thickness provided by the inter layer planes is very little
compared to the other materials. However it does make for stress risers at their
intersection with the hole plating. Another place you can see the stress risers
starting cracks is on the "knee" if the PTH, there is a pad there with plating
flowing over it.

The thickness of 2 sided boards is relative and can be .015 to .125 easily the
same as MLBs.

Maybe Susan M. @ Robisan can way in, or Werner can set us all strait.








"Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]> on 01/15/2002
11:43:34 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      "Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]>








 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Remove unused "dead" pads on internal
           layers








Hey Warren,

Granted, Drill isn't my specialty but I've always heard that additional pads
in the drilled stack can help.  I'll hazard a guess, since Coombs isn't
readily available, the additional metal gives the bit something to dig into
being softer than the surrounding glass fiber & epoxy resin.   What would be
the benefit of softer layers in a drill stack?  Could that improve hole wall
quality?  Reduce drill wander/wobble?  I'm assuming the right feed, speed
and chip load have been used.  Somebody steer me in the right direction here
- I'm learning.

Obviously, a double sided board doesn't have inner layers and they tend to
be a bit thinner than the high layer count boards I'm used to processing.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 11:50 AM
To: TechNet E-Mail Forum.; Hinners Hans M Civ WRALC/LUGE
Subject: Re: [TN] Remove unused "dead" pads on internal layers




Actually the cracked vias I have witnessed in the inter barrell tend to
start at
the intersection of the copper planes. A corner or stress riser starts the
crack
during thermal shock tests. Don't understand how the extra non- connected
pads
could help barrell, if so then there is no hope for a 2 sided board.







"Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]> on 01/15/2002
07:40:50 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to
      "Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]>











 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Remove unused "dead" pads on internal
           layers








Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are you
building to drawing or is there a clause that says process improvements that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution
or
other use is prohibited.  If you received this e-mail in error, please
notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Tue, 15 Jan 2002 13:25:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Nickel Plating Snarl
In-Reply-To:  <49395D2122DBD311890A00C04F01A124AA520B@si-exchange>
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Nickel Plating SnarlRobert,

I don't have the hardness spec for electroless nickel at hand, so I don't
know if there is a potential problem there.  The hardness specification is
something I would question upon reviewing the note.  I don't believe that
there is an effective method for measuring the hardness of a 50 microinch
thick coating using a 100 gram load in a conventional hardness tester.

My recommendation is that you specify the nickel purity (actually percent
phosphorus) if published data indicate that nickel purity affects the
hardness.  Otherwise a straight callout for electroless nickel should be
sufficient. BTW is 50 microinches of nickel sufficient for the life of your
product?

Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Neel, Robert
Sent: Tuesday, January 15, 2002 12:17 PM
To: [log in to unmask]
Subject: [TN] Nickel Plating Snarl


Folks,

Can someone explain to me why all my PCB houses are suddenly having
"spectacular cows" over this pcb plating spec:

"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, MINIMUM
40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

This pcb is the substrate for some snap-acting domes and I need a hard and
conductive bearing surface for the dome feet.  The plating spec comes from
the dome manufacturer.

Is it the "electroless"?  Is it the thickness? Is it the hardness
requirement? Is it the "nickel" vs "nickle"?  (Funny thing is, though,
everyone is very happy to do gold rather than nickel.)

What gives?

Robert


------=_NextPart_000_000C_01C19DC8.16AD4A00
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Nickel Plating Snarl</TITLE>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D652441819-15012002>Robert,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D652441819-15012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D652441819-15012002>I=20
don't have the hardness spec for electroless nickel at hand, so I don't =
know if=20
there is a potential problem there.&nbsp; The hardness specification is=20
something I would question upon reviewing the note.&nbsp; I don't =
believe that=20
there is an effective method for measuring the hardness of a 50 =
microinch thick=20
coating using a 100 gram load in a conventional hardness=20
tester.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D652441819-15012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D652441819-15012002>My=20
recommendation is that you specify the nickel purity (actually percent=20
phosphorus) if published data indicate that nickel purity affects the=20
hardness.&nbsp; Otherwise a straight callout for electroless nickel =
should be=20
sufficient. BTW is 50 microinches of nickel sufficient for the life of =
your=20
product?</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D652441819-15012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D652441819-15012002>Don=20
Vischulis</SPAN></FONT></DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Neel, Robert<BR><B>Sent:</B> =

Tuesday, January 15, 2002 12:17 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Nickel Plating=20
Snarl<BR><BR></FONT></DIV>
<P><FONT size=3D2>Folks,</FONT> </P>
<P><FONT size=3D2>Can someone explain to me why all my PCB houses are =
suddenly=20
having "spectacular cows" over this pcb plating spec:</FONT> </P>
<P><FONT size=3D2>"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 =
MILLIONTHS=20
THICK, MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 =

GRAMS"</FONT></P>
<P><FONT size=3D2>This pcb is the substrate for some snap-acting domes =
and I need=20
a hard and conductive bearing surface for the dome feet.&nbsp; The =
plating spec=20
comes from the dome manufacturer.</FONT></P>
<P><FONT size=3D2>Is it the "electroless"?&nbsp; Is it the thickness? Is =
it the=20
hardness requirement? Is it the "nickel" vs "nickle"?&nbsp; (Funny thing =
is,=20
though, everyone is very happy to do gold rather than =
nickel.)</FONT></P>
<P><FONT size=3D2>What gives?</FONT> </P>
<P><FONT size=3D2>Robert</FONT> </P></BODY></HTML>

------=_NextPart_000_000C_01C19DC8.16AD4A00--

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Date:         Tue, 15 Jan 2002 11:27:08 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         David Ricketts <[log in to unmask]>
Subject:      Re: Nickel Plating Snarl
In-Reply-To:  <49395D2122DBD311890A00C04F01A124AA520B@si-exchange>
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Nickel Plating SnarlElectroless plating is soft. Electrolytic plating is
hard. You may want to investigate carbon ink as a cost effective
alternative.
David Ricketts

Pertek Engineering
Voice: 949-475-4485
Fax:   949-475-4493

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Neel, Robert
Sent: Tuesday, January 15, 2002 10:17 AM
To: [log in to unmask]
Subject: [TN] Nickel Plating Snarl


 Folks,

Can someone explain to me why all my PCB houses are suddenly having
"spectacular cows" over this pcb plating spec:

"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, MINIMUM
40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

This pcb is the substrate for some snap-acting domes and I need a hard and
conductive bearing surface for the dome feet.  The plating spec comes from
the dome manufacturer.

Is it the "electroless"?  Is it the thickness? Is it the hardness
requirement? Is it the "nickel" vs "nickle"?  (Funny thing is, though,
everyone is very happy to do gold rather than nickel.)

What gives?

Robert


------=_NextPart_000_002D_01C19DB7.9146D940
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Nickel Plating Snarl</TITLE>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D520441219-15012002>Electroless plating is soft. =
Electrolytic=20
plating is hard. You may want to investigate carbon ink as a cost =
effective=20
alternative.</SPAN></DIV>
<P>David Ricketts<BR><BR>Pertek Engineering<BR>Voice:=20
949-475-4485<BR>Fax:&nbsp;&nbsp; 949-475-4493 </P>
<P><FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Neel, Robert<BR><B>Sent:</B> =

Tuesday, January 15, 2002 10:17 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Nickel Plating =
Snarl<BR></FONT><FONT=20
size=3D2><SPAN class=3D520441219-15012002><FONT=20
size=3D3>&nbsp;</FONT></SPAN></FONT></P>
<P><FONT size=3D2><SPAN =
class=3D520441219-15012002>&nbsp;</SPAN>Folks,</FONT> </P>
<P><FONT size=3D2>Can someone explain to me why all my PCB houses are =
suddenly=20
having "spectacular cows" over this pcb plating spec:</FONT> </P>
<P><FONT size=3D2>"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 =
MILLIONTHS=20
THICK, MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 =

GRAMS"</FONT></P>
<P><FONT size=3D2>This pcb is the substrate for some snap-acting domes =
and I need=20
a hard and conductive bearing surface for the dome feet.&nbsp; The =
plating spec=20
comes from the dome manufacturer.</FONT></P>
<P><FONT size=3D2>Is it the "electroless"?&nbsp; Is it the thickness? Is =
it the=20
hardness requirement? Is it the "nickel" vs "nickle"?&nbsp; (Funny thing =
is,=20
though, everyone is very happy to do gold rather than =
nickel.)</FONT></P>
<P><FONT size=3D2>What gives?</FONT> </P>
<P><FONT size=3D2>Robert</FONT> </P></BODY></HTML>

------=_NextPart_000_002D_01C19DB7.9146D940--

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Date:         Tue, 15 Jan 2002 14:05:07 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              MAURY HARRIS <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         MAURY HARRIS <[log in to unmask]>
Subject:      PWB Moisture
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Anyone,

What is the max absorbed moisture a PWB may have prior to reflow soldering?
Also, what IPC or Mil-Spec addresses PWB moisture?

Thank you,

Maury Harris
EFTC-SCO Engineering
602 282-5179
[log in to unmask]

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Date:         Tue, 15 Jan 2002 15:33:18 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: PWB Moisture
Mime-Version: 1.0
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Is there a spec for this? Besides, how do (or would) you measure moisture =
levels? Can it effectively be measured by weight? Got me on that one!

Jason

>>> [log in to unmask] 01/15/02 02:05PM >>>
Anyone,

What is the max absorbed moisture a PWB may have prior to reflow soldering?=

Also, what IPC or Mil-Spec addresses PWB moisture?

Thank you,

Maury Harris
EFTC-SCO Engineering
602 282-5179
[log in to unmask]

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Date:         Tue, 15 Jan 2002 13:42:11 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         Jason Gregory <[log in to unmask]>
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Maybe you could measure conductance? Like a wood moisture meter.
Dan

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Date:         Tue, 15 Jan 2002 16:42:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guy Ramsey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         MAURY HARRIS <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Clasification for Plastic
Integrated Circuit Surface Mount Devices

IPC/JEDEC J-STD-033 Standard for handling, Packing, Shipping and Use of
Moisture/Reflow Sensitive Surface Mount Devices

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of MAURY HARRIS
> Sent: Tuesday, January 15, 2002 3:05 PM
> To: [log in to unmask]
> Subject: [TN] PWB Moisture
>
>
> Anyone,
>
> What is the max absorbed moisture a PWB may have prior to reflow
> soldering?
> Also, what IPC or Mil-Spec addresses PWB moisture?
>
> Thank you,
>
> Maury Harris
> EFTC-SCO Engineering
> 602 282-5179
> [log in to unmask]
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
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>

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Date:         Tue, 15 Jan 2002 16:04:51 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              MAURY HARRIS <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         MAURY HARRIS <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         "Dan R. Johnson" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dan,

Moisture content of a PWB is measured by weighing the PWB,
typically to within .00 gram.  I started by weighing PWB as
received from supplier, oven baked and weighed again.  Then,
I compared difference. Now I need to know what is allowable
and document that addresses PWB moisture prior to reflow.

Thank you,

Maury Harris

-----Original Message-----
From: Dan R. Johnson [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 2:42 PM
To: [log in to unmask]
Subject: Re: [TN] PWB Moisture


Maybe you could measure conductance? Like a wood moisture meter.
Dan

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Date:         Tue, 15 Jan 2002 16:15:11 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              MAURY HARRIS <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         MAURY HARRIS <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         Jason Gregory <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Jason,

PWB moisture content can be weighed to within .000 gram.
However, .00 gram is a good measurement. First, weigh PWB
at ambient environment to determine weight. Then bake dry.
Recommended time and temperature is 5 hours @ 120C. Then
weigh dry weight and compare difference. Trick is to know
acceptable moisture content prior to reflow.

Thank you,

Maury Harris


-----Original Message-----
From: Jason Gregory [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 2:33 PM
To: [log in to unmask]
Subject: Re: [TN] PWB Moisture


Is there a spec for this? Besides, how do (or would) you measure moisture
levels? Can it effectively be measured by weight? Got me on that one!

Jason

>>> [log in to unmask] 01/15/02 02:05PM >>>
Anyone,

What is the max absorbed moisture a PWB may have prior to reflow soldering?
Also, what IPC or Mil-Spec addresses PWB moisture?

Thank you,

Maury Harris
EFTC-SCO Engineering
602 282-5179
[log in to unmask]

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Date:         Tue, 15 Jan 2002 17:20:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: PWB Moisture
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I don't think there is any value given for "allowable" moisture prior to
reflow.

Perhaps whoever said to bake 5 hrs at 120C to determine moisture content
would be the one to determine a value.

I have seen some boards that had many layers and ground planes that needed a
much longer bake - with vacuum to get
the moisture out so as not to degrade during assembly.

Susan Mansilla
Robisan Lab

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Date:         Tue, 15 Jan 2002 17:22:33 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
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Hi Warren,
You write:
<< The amount of copper thickness provided by the inter layer planes is very
little
compared to the other materials. However it does make for stress risers at
their
intersection with the hole plating. Another place you can see the stress
risers
starting cracks is on the "knee" if the PTH, there is a pad there with plating
flowing over it. >>
A: The problems are not so much that they are 'stress risers', but locations
of maximum loading.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Tue, 15 Jan 2002 17:22:32 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         [log in to unmask]
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Hi 'sdu,'
In a message dated 01/15/2002 13:38:05, [log in to unmask] writes:
<< Can someone/anyone please send me or direct me to a study that concluded

that removing "a land that is not connected electrically to the conductive

pattern on its layer" decreased reliability in any way?  How about a study

that concluded a maintained or increased reliability by keeping or adding

non-functional pads?  ...I cannot find anything in the IPC specifications

discouraging the removal of non-functional pads. >>
I guess you have not been looking very hard. IPC-D-279 refers to IPC-TR-579
where it was found that "functional and nonfunctional lands appear to improve
reliability". IPC-TR-579 concentrated on barrel cracking and thus on
small-diameter holes; the most benefit from nonfunctional lands comes in the
prevention of innerlayer separation [ILS--formerly know as post-separation],
which of course plagues larger diameter holes more than small-diameter holes
[see IPC-TR-486].
<< From practical fabrication experience, removing a non-functional pad does

provide benefits:

1) It is easier to drill through less copper, causing less wear on the bit,

thereby increasing the potential quality of the hole.

2) Most importantly, removing the pads does not change connectivity but does

reduce/eliminate a real potential to short to adjacent connections.>>
A: both true


<< Other effects:

2) For some non-plated holes, if the pads are left on and it is drilled

after etch, the land/pad may be ripped off of the surface if there is not

enough ring to anchor the pad.  This only happens on the outer layers.>>
A: why would anybody have lands of any kind in non-plated holes?


<< 3) For some applications, a land may be used to anchor the hole connection

to the material (PTFE, flex)>>
A: That is the main effect in MLBs as well--it prevents ILS as well as
hole-wall separation.


<< 4) Are there other effects?  Thermal, impedance, pth reliability? >>
A: It prevents ILS as well as hole-wall separation, and to a lesser degree
replaces resin with copper thereby reducing the z-direction thermal expansion
mismatch [a small effect]

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Wed, 16 Jan 2002 11:34:59 +1300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Michael Bell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Bell <[log in to unmask]>
Subject:      BGA Rework Stations
MIME-Version: 1.0
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Hi all,

I am just evaluating a number of BGA rework stations and was hoping for a
wee bit of feed-back on what everyone prefers.  I have evaluated the Ersa
rework bench and it seems to be my preference so far, what are everyones
experiences with this unit?  I have also looked at the Zephyrtronics
benchtop BGA rework station, but I haven't heard anyone else's opinion of
this brand, any comments????  Is anyone actually using this system????

Thanks

Mike Bell
Process Engineer

GPC Electronics
New Zealand

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Date:         Tue, 15 Jan 2002 17:50:53 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         "Creswick, Steven" <[log in to unmask]>
MIME-Version: 1.0
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--------------EB27B09C8C34DF1D397D45D9
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Steve,

RE: MIL-Hdbk-217

FYI I recieved the following copy of an e-mail about 2 months ago


I received this e-mail and I am glad to see that someone is working a
replacement for Mil Hdbk 217. As you  may know, the DSIC made a decision
several years ago to let Mil Hdbk 217 "die a natural death". This is still
the current OSD position i.e. we will not support any updates/revisions to
Mil Hdbk 217.

George Desiderio, Deputy Director
Systems Engineering
OUSD(AT&L)/Interoperability
Tel: 703/695-2300
Fax: 703/614-9884
Cell: 703/582-7644
eMail: [log in to unmask]

David A. Douthit
Manager
LoCan LLC

"Creswick, Steven" wrote:

> Earl,
>
> I am quite sure that Mil-Std 217 - Preparation of Manuscript for Tech
> Manuals, or some such similar title, was superceeded by Mil-Std 218.  I also
> recall that 218 was a 3 'parter', but do not recall if it is still active or
> not.  Been quite a while!
>
> Mil-Hdbk-217 is on Reliability Prediction
>
> Not sure where to get either one at the moment.  Would have to do some web
> searching, etc.
>
> Now that you know this, we may have to shoot you.  :-)
>
> Steve Creswick - Gentex Corp
>
> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: Tuesday, January 15, 2002 9:21 AM
> To: [log in to unmask]
> Subject: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT
>
> Old folks, besides Ron D and me, which MIL-STD-217 doc is which. Everything
> has been cancelled as we all know. Is 217 the "How To Write" document or?
>
> MoonMan
>
> ----------------------------------------------------------------------------
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>
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Steve,
<p>RE: MIL-Hdbk-217
<p>FYI I recieved the following copy of an e-mail about 2 months ago
<br>&nbsp;
<p><i>I received this e-mail and I am glad to see that someone is working
a</i>
<br><i>replacement for Mil Hdbk 217. As you&nbsp; may know, the DSIC made
a decision</i>
<br><i>several years ago to let Mil Hdbk 217 "die a natural death". This
is still</i>
<br><i>the current OSD position i.e. we will not support any updates/revisions
to</i>
<br><i>Mil Hdbk 217.</i><i></i>
<p><i>George Desiderio, Deputy Director</i>
<br><i>Systems Engineering</i>
<br><i>OUSD(AT&amp;L)/Interoperability</i>
<br><i>Tel: 703/695-2300</i>
<br><i>Fax: 703/614-9884</i>
<br><i>Cell: 703/582-7644</i>
<br><i>eMail: [log in to unmask]</i><i></i>
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>"Creswick, Steven" wrote:
<blockquote TYPE=CITE>Earl,
<p>I am quite sure that Mil-Std 217 - Preparation of Manuscript for Tech
<br>Manuals, or some such similar title, was superceeded by Mil-Std 218.&nbsp;
I also
<br>recall that 218 was a 3 'parter', but do not recall if it is still
active or
<br>not.&nbsp; Been quite a while!
<p>Mil-Hdbk-217 is on Reliability Prediction
<p>Not sure where to get either one at the moment.&nbsp; Would have to
do some web
<br>searching, etc.
<p>Now that you know this, we may have to shoot you.&nbsp; :-)
<p>Steve Creswick - Gentex Corp
<p>-----Original Message-----
<br>From: Earl Moon [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: Tuesday, January 15, 2002 9:21 AM
<br>To: [log in to unmask]
<br>Subject: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT
<p>Old folks, besides Ron D and me, which MIL-STD-217 doc is which. Everything
<br>has been cancelled as we all know. Is 217 the "How To Write" document
or?
<p>MoonMan
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Date:         Wed, 16 Jan 2002 10:09:51 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
MIME-Version: 1.0
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Hi,

Actually these "unused" pads are replicates of the hole "rules" created for
the surface layers. Most routing packages, or routers, seem to do this by
default for each layer to save manual replication where traces, etc are to
be connected. (At least PADS, Alegro and Mentor do). On the grounds that
it's always easier to destroy than to build, it's easier to delete pad data
than to create it, so it's put in by default as there's a good chance it
will be needed.

I still say you should consider hole barrel strength/support issues before
just deleting them - e.g. they can constrain the "resin recession" and hole
wall pull-away that have been recent threads on this forum. Think of the
"unused" pads as 'wall ties' holding the copper at frequent intervals to
the hole wall. Copper bulging or pull-away in the event of recession or
whatever is reduced.

Peter Duncan




                    Hinners Hans M Civ
                    WRALC/LUGE                To:     [log in to unmask]
                    <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    NS.AF.MIL>                Aero/ST Group)
                    Sent by: TechNet          Subject:     Re: [TN] Remove unused "dead" pads on
                    <[log in to unmask]>         internal layers


                    01/15/02 09:40 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Hinners
                    Hans M Civ
                    WRALC/LUGE






Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
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Date:         Tue, 15 Jan 2002 21:10:31 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      LPI Soldermask discoloration...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi All!

Another weird one again, I'll post a picture tomorrow when I get back into
work. But a preface to the picture, is that we built a board that was wave
soldered, and after post wave cleaning, you could see a faint outline of
where masking was applied over holes, we use water soluble dots over holes
etc...I've seen that before, but it usually isn't so noticable that it's a
big deal.

However, on this particular board we're doing some jumper wires that go from
the bottomside up to the top, this is done after wave and everything else.
The operators soldered the wires to where they needed to go, and then needed
to clean the boards prior to tak-pak'ing them to the board. So before sending
them to the cleaner, they used kapton tape to secure the wires to the board
so they didn't flop around in the cleaner...makes good sense to me. When they
got the boards back outta the cleaner and removed the tape, there were all
these dark spots in the mask beneath where the tape was...it looks kinda'
bad. But the mask is intact as far as I can see, there is no degradation at
all...it just looks bad...almost looks like something deeper, but I'm sure
it's just mask discoloration...

I baked the boards to see if that would change anything, but it didn't. The
mask is a LPI, don't know the brand. I'll post a picture tomorrow morning.
But have you ever run across LPI masks lightening or darkening, showing
outlines of masking materials after wave soldering, or cleaning (kapton
tapes, preformed dots, etc..)?

What causes that?

Thanks everybody!

-Steve Gregory-

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Date:         Wed, 16 Jan 2002 10:28:33 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         [log in to unmask]
MIME-Version: 1.0
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Two-sided boards aren't so thick - they don't need to be beyond rigidity
requirements -  and don't have the high internal level of resin that MLB's
do, so the unsupported length of plated barrel is relatively short, and
resin recession doesn't occur so much, if at all.

I agree with the observation that the right angled corners between barrel
and pad are a focus for stress fractures, but if there is differential
movement between pad and barrel to cause this fatigue, how much worse or
how much more quickly would it occur if, say, only top and bottom layer
pads were connected to the barrel? (Rhet.) Fewer points across which to
disperse the load.

Peter Duncan




                    Warren_Crow@I
                    -O.COM               To:     [log in to unmask]
                    Sent by:             cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    TechNet              Aero/ST Group)
                    <[log in to unmask]        Subject:     Re: [TN] Remove unused "dead" pads on
                    ORG>                 internal layers


                    01/16/02
                    12:49 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    Warren_Crow






Actually the cracked vias I have witnessed in the inter barrell tend to
start at
the intersection of the copper planes. A corner or stress riser starts the
crack
during thermal shock tests. Don't understand how the extra non- connected
pads
could help barrell, if so then there is no hope for a 2 sided board.







"Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]> on 01/15/2002
07:40:50 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to
      "Hinners Hans M Civ WRALC/LUGE" <[log in to unmask]>








 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Remove unused "dead" pads on internal
           layers








Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat
This e-mail may contain SEL confidential information.  The opinions
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Date:         Tue, 15 Jan 2002 21:46:35 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: BGA Rework Stations
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_89.11f9512f.2976438b_boundary"

--part1_89.11f9512f.2976438b_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Mike!

Just to let you know about another system out there (that I'm looking into)
is a system that uses focused IR beams, it's called PDR. The link to their
page is at:

http://www.smtrework.com/

We currently have a OK Systems BGA-3000 system, and it has worked fine for
us, the person that I talked with at PDR readily acknowledges that the system
we have is a good system, but the reason that I called and talked with PDR is
because of some very unusual rework requirements that we face here...it's
with some RF assemblies that are bonded inside a very heavy metal chassis.

I haven't been able to rework the RF components after it's in the chassis in
the Ok systems machine unless I remove 4-bolts for the head, turn it around
180-degrees (so I can put a laboratory hot plate beneath the head to heat the
chassis up).

The bottomside preheater in the machine is fine for regular boards with the
OK system, but for these beasts with the metal chassis, it ain't enough.

So, when our customer said they had a PDR system, and it worked great, I've
been looking at it...I like what I see so far. Don't need scores of nozzles
for all the different packages, just a few lenses...non-contact, real-time,
temperature measurements (No thermocouples to mess with), self profiling
software, split-mirror placement for BGA's...sounding more and more like a
nice system...just something else to look at.

-Steve Gregory-


> Hi all,
>
> I am just evaluating a number of BGA rework stations and was hoping for a
> wee bit of feed-back on what everyone prefers.  I have evaluated the Ersa
> rework bench and it seems to be my preference so far, what are everyones
> experiences with this unit?  I have also looked at the Zephyrtronics
> benchtop BGA rework station, but I haven't heard anyone else's opinion of
> this brand, any comments????  Is anyone actually using this system????
>
> Thanks
>
> Mike Bell
> Process Engineer
>
> GPC Electronics
> New Zealand
>


--part1_89.11f9512f.2976438b_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Mike!<BR>
<BR>
Just to let you know about another system out there (that I'm looking into) is a system that uses focused IR beams, it's called PDR. The link to their page is at:<BR>
<BR>
http://www.smtrework.com/<BR>
<BR>
We currently have a OK Systems BGA-3000 system, and it has worked fine for us, the person that I talked with at PDR readily acknowledges that the system we have is a good system, but the reason that I called and talked with PDR is because of some very unusual rework requirements that we face here...it's with some RF assemblies that are bonded inside a very heavy metal chassis.<BR>
<BR>
I haven't been able to rework the RF components after it's in the chassis in the Ok systems machine unless I remove 4-bolts for the head, turn it around 180-degrees (so I can put a laboratory hot plate beneath the head to heat the chassis up). <BR>
<BR>
The bottomside preheater in the machine is fine for regular boards with the OK system, but for these beasts with the metal chassis, it ain't enough.<BR>
<BR>
So, when our customer said they had a PDR system, and it worked great, I've been looking at it...I like what I see so far. Don't need scores of nozzles for all the different packages, just a few lenses...non-contact, real-time, temperature measurements (No thermocouples to mess with), self profiling software, split-mirror placement for BGA's...sounding more and more like a nice system...just something else to look at.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,<BR>
<BR>
I am just evaluating a number of BGA rework stations and was hoping for a<BR>
wee bit of feed-back on what everyone prefers.&nbsp; I have evaluated the Ersa<BR>
rework bench and it seems to be my preference so far, what are everyones<BR>
experiences with this unit?&nbsp; I have also looked at the Zephyrtronics<BR>
benchtop BGA rework station, but I haven't heard anyone else's opinion of<BR>
this brand, any comments????&nbsp; Is anyone actually using this system????<BR>
<BR>
Thanks<BR>
<BR>
Mike Bell<BR>
Process Engineer<BR>
<BR>
GPC Electronics<BR>
New Zealand<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_89.11f9512f.2976438b_boundary--

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Date:         Wed, 16 Jan 2002 12:43:55 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         MAURY HARRIS <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

This isn't a very useful response, perhaps, but the question is an
interesting one. I offer some additional considerations/mind benders when
contemplating the answer to this:

1) Moisture absorbtion depends on the material(s) the board is made from,
and the overall amount of moisture absorbed will be related to the volume
of the materials used.
2) The material volume depends on the board design and is therefore a bit
variable.
3) Opportunity to absorb moisture depends on humidity, temperature and
time.
4) Tracking moisture exposure depends on having an army of arithmeticians
or alternatively a tracking system such as our friend Francois Monette has
to offer.

What we need here is some way of determining a Moisture Sensitivity
Category for the various materials and their combinations, as used by
component manufacturers and a means of determining the rate of moisture
take-up for any given design - quite a career for somebody.

On the other hand, you can simply pursuade your fab house to pack your
nice, new, dry boards in individual sealed bags with some desiccant that
you don't open until the moment you need them (or reseal properly after
in-coming inspection) on the line. If the boards have been lying around for
a year or so (in their sealed bags), and/or you're in any doubt about how
dry the boards are, you can then bake them out for about 2 hours at 90 deg
C just prior to use. This last has been common practice for many years,
although I object on principle to having to do this - one more thermal
excursion too many for the board.

Call me old-fashioned, but why look for ways to make life so complicated,
when a little management and control can save a lot of unnecessary effort
and cost? (Sorry, Francois!).

Peter Duncan




                    MAURY HARRIS
                    <MAURY_HARRIS        To:     [log in to unmask]
                    @EFTC.COM>           cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:             Aero/ST Group)
                    TechNet              Subject:     [TN] PWB Moisture
                    <[log in to unmask]
                    ORG>


                    01/16/02
                    04:05 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    MAURY HARRIS






Anyone,

What is the max absorbed moisture a PWB may have prior to reflow soldering?
Also, what IPC or Mil-Spec addresses PWB moisture?

Thank you,

Maury Harris
EFTC-SCO Engineering
602 282-5179
[log in to unmask]

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Date:         Wed, 16 Jan 2002 12:46:06 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Guy,

These specs govern electronic devices, and do not/are not intended to cover
PCB's. See my other posting for my 2 cents worth.

Peter




                    Guy Ramsey
                    <gramsey@ACIU        To:     [log in to unmask]
                    SA.ORG>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by:             Aero/ST Group)
                    TechNet              Subject:     Re: [TN] PWB Moisture
                    <[log in to unmask]
                    ORG>


                    01/16/02
                    05:42 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    Guy Ramsey






IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Clasification for Plastic
Integrated Circuit Surface Mount Devices

IPC/JEDEC J-STD-033 Standard for handling, Packing, Shipping and Use of
Moisture/Reflow Sensitive Surface Mount Devices

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of MAURY HARRIS
> Sent: Tuesday, January 15, 2002 3:05 PM
> To: [log in to unmask]
> Subject: [TN] PWB Moisture
>
>
> Anyone,
>
> What is the max absorbed moisture a PWB may have prior to reflow
> soldering?
> Also, what IPC or Mil-Spec addresses PWB moisture?
>
> Thank you,
>
> Maury Harris
> EFTC-SCO Engineering
> 602 282-5179
> [log in to unmask]
>
> ------------------------------------------------------------------
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Date:         Wed, 16 Jan 2002 08:15:37 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Braime, Justin" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Braime, Justin" <[log in to unmask]>
Subject:      Re: BGA Rework Stations
X-To:         Michael Bell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Hi Mike,
We've had our ERSA BGA rework station for around four months now and we are
very happy with it. I have changed all manner of BGA devices, including
ceramic, and metal cased devices with great success.  I have also
successfully reworked some large SMT connectors with the ERSA unit .The main
advantage you would get with a more expensive IR system (such as the PDR)
would be better control of the heating profile, as these units tend to have
a PC and profiling software included in the package.

Justin Braime
Senior Production Engineer

Racal Instruments Ltd
480 Bath Rd, Slough
Berkshire, SL1 6BE
England

Tel: +44 (0)1628 604455
Fax: +44 (0)1628 662017
E-mail: [log in to unmask]

> -----Original Message-----
> From: Michael Bell [SMTP:[log in to unmask]]
> Sent: 15 January 2002 22:35
> To:   [log in to unmask]
> Subject:      [TN] BGA Rework Stations
>
> Hi all,
>
> I am just evaluating a number of BGA rework stations and was hoping for a
> wee bit of feed-back on what everyone prefers.  I have evaluated the Ersa
> rework bench and it seems to be my preference so far, what are everyones
> experiences with this unit?  I have also looked at the Zephyrtronics
> benchtop BGA rework station, but I haven't heard anyone else's opinion of
> this brand, any comments????  Is anyone actually using this system????
>
> Thanks
>
> Mike Bell
> Process Engineer
>
> GPC Electronics
> New Zealand
>
> --------------------------------------------------------------------------
> -------
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Date:         Wed, 16 Jan 2002 03:11:32 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mark Julstrom <[log in to unmask]>
Subject:      rework
MIME-Version: 1.0
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Broken tents caused NPT holes to be plated.   Re-work occurred back at drill
to remove the copper from the hole wall, using a drill slightly larger than
the original hole diameter. A thin layer of copper remains on the hole wall
in some holes.  The drill size cannot be increased any further without
violating spec.  Inspection will use an exacto knife to scrape out the
remaining copper.  Are any better methods recommended for this type of
rework?  There are approximately 20 panels, 10 holes per panel need to be
scraped with exacto knife.

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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Broken tents caused NPT holes to be plated. &nbsp;&nbsp;Re-work occurred back at drill to remove the copper from the hole wall, using a drill slightly larger than the original hole diameter. A thin layer of copper remains on the hole wall in some holes. &nbsp;The drill size cannot be increased any further without violating spec. &nbsp;Inspection will use an exacto knife to scrape out the remaining copper. &nbsp;Are any better methods recommended for this type of rework? &nbsp;There are approximately 20 panels, 10 holes per panel need to be scraped with exacto knife. &nbsp;&nbsp;</FONT></HTML>

--part1_95.15fabb74.29768fb4_boundary--

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Date:         Wed, 16 Jan 2002 06:58:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: PWB Moisture
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Just for your information, one of our board suppliers recommends baking for
2 hours for every month of storage (up to 24 hours) at a temperature above
boiling.  They even suggest a vacuum bake, if available!

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   <Peter George Duncan> [SMTP:[log in to unmask]]
        Sent:   Tuesday, January 15, 2002 11:44 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] PWB Moisture

        This isn't a very useful response, perhaps, but the question is an
        interesting one. I offer some additional considerations/mind benders
when
        contemplating the answer to this:

        1) Moisture absorbtion depends on the material(s) the board is made
from,
        and the overall amount of moisture absorbed will be related to the
volume
        of the materials used.
        2) The material volume depends on the board design and is therefore
a bit
        variable.
        3) Opportunity to absorb moisture depends on humidity, temperature
and
        time.
        4) Tracking moisture exposure depends on having an army of
arithmeticians
        or alternatively a tracking system such as our friend Francois
Monette has
        to offer.

        What we need here is some way of determining a Moisture Sensitivity
        Category for the various materials and their combinations, as used
by
        component manufacturers and a means of determining the rate of
moisture
        take-up for any given design - quite a career for somebody.

        On the other hand, you can simply pursuade your fab house to pack
your
        nice, new, dry boards in individual sealed bags with some desiccant
that
        you don't open until the moment you need them (or reseal properly
after
        in-coming inspection) on the line. If the boards have been lying
around for
        a year or so (in their sealed bags), and/or you're in any doubt
about how
        dry the boards are, you can then bake them out for about 2 hours at
90 deg
        C just prior to use. This last has been common practice for many
years,
        although I object on principle to having to do this - one more
thermal
        excursion too many for the board.

        Call me old-fashioned, but why look for ways to make life so
complicated,
        when a little management and control can save a lot of unnecessary
effort
        and cost? (Sorry, Francois!).

        Peter Duncan




                            MAURY HARRIS
                            <MAURY_HARRIS        To:     [log in to unmask]
                            @EFTC.COM>           cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                            Sent by:             Aero/ST Group)
                            TechNet              Subject:     [TN] PWB
Moisture
                            <[log in to unmask]
                            ORG>


                            01/16/02
                            04:05 AM
                            Please
                            respond to
                            "TechNet
                            E-Mail
                            Forum.";
                            Please
                            respond to
                            MAURY HARRIS






        Anyone,

        What is the max absorbed moisture a PWB may have prior to reflow
soldering?
        Also, what IPC or Mil-Spec addresses PWB moisture?

        Thank you,

        Maury Harris
        EFTC-SCO Engineering
        602 282-5179
        [log in to unmask]


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Date:         Wed, 16 Jan 2002 05:57:33 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: rework
X-To:         Mark Julstrom <[log in to unmask]>

Know your situation. HP and Celestica, for most smart customers, had a
rework plan, and proof of its capability, as part of DFM.

For Cray, on one project with which I was involved, we had a 42 layer board
made for purposes of proving 24 rework requirements involving 1200 I/O
CCGA's and 3400 I/O MCM's. I bring this up as you mentioned meeting spec.
Are you talking to 7711 and/or 7721 requirements (whichever is the rework
guideline) or other?

One of our rework processes involved using a fairly accurate overhead drill
machine, with micromoter adjustments and microscope, to remove copper from
holes in the test board mentioned above. I was crappy at it, but once shown
to quality operators (the best folks on the planet), the just did it and
inserted very fine gauge wire and soldered each side as if it was a breeze.

Anyway, the only way I know to get the copper out, is to drill it. Wish I
could help more after the deed (design) is done, but without benefit of up
front planning, via DFM/CE, it can be tough.

Hell, MoonMan isn't on that rant again. Earl Moon says it sure sounds that
way but maybe there's someting there for next time.

MoonMan, or is it Earl Moon, or who cares?

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Date:         Wed, 16 Jan 2002 07:19:14 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I haven't been following this thread, so forgive me if this information was
already given.  According to Assist Online, an official web for DoD specs
and standards, MIL-STD-217 was replaced by MIL-STD-218.  MIL-STD-218 is
described as "document exists only as a reference in data base" with the
status as being "unknown".  Parts 1, 2 and 3 of this document
(MIL-STD-217/1, 2 or 3) were in fact cancelled without replacement. Take
this for what it's worth.

        -----Original Message-----
        From:   David Douthit [SMTP:[log in to unmask]]
        Sent:   Tuesday, January 15, 2002 7:51 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT

        Steve,

        RE: MIL-Hdbk-217

        FYI I recieved the following copy of an e-mail about 2 months ago


        I received this e-mail and I am glad to see that someone is working
a
        replacement for Mil Hdbk 217. As you  may know, the DSIC made a
decision
        several years ago to let Mil Hdbk 217 "die a natural death". This is
still
        the current OSD position i.e. we will not support any
updates/revisions to
        Mil Hdbk 217.

        George Desiderio, Deputy Director
        Systems Engineering
        OUSD(AT&L)/Interoperability
        Tel: 703/695-2300
        Fax: 703/614-9884
        Cell: 703/582-7644
        eMail: [log in to unmask]

        David A. Douthit
        Manager
        LoCan LLC

        "Creswick, Steven" wrote:

                Earl,

                I am quite sure that Mil-Std 217 - Preparation of Manuscript
for Tech
                Manuals, or some such similar title, was superceeded by
Mil-Std 218.  I also
                recall that 218 was a 3 'parter', but do not recall if it is
still active or
                not.  Been quite a while!

                Mil-Hdbk-217 is on Reliability Prediction

                Not sure where to get either one at the moment.  Would have
to do some web
                searching, etc.

                Now that you know this, we may have to shoot you.  :-)

                Steve Creswick - Gentex Corp

                -----Original Message-----
                From: Earl Moon [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
                Sent: Tuesday, January 15, 2002 9:21 AM
                To: [log in to unmask]
                Subject: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT

                Old folks, besides Ron D and me, which MIL-STD-217 doc is
which. Everything
                has been cancelled as we all know. Is 217 the "How To Write"
document or?

                MoonMan


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Date:         Wed, 16 Jan 2002 06:14:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         "Marsico, James" <[log in to unmask]>

Polyimide boards, as an example, are more hygroscopic than most other
board/material types at about .5% whereas epoxies are about half that. I
believe better specs are available than your shop's recommendations. Boiling
just doesn't get it for me. Also, supplier dessication is a good idea as
well as pre-baking at your site, if the supplier doesn't, then sealing and
dessicating until use. Upon climb out, cruise at altitude, and descent, the
boards will be tested severely enough without time for baking - unless in
Afghanastan in the summer months.

MoonMan

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Date:         Wed, 16 Jan 2002 07:11:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT

Been down the 217/218 road now awhile. You've got the "how to write it
stuff" that matters little to me. Then, there's:

Document ID:     MIL-HDBK-217F(2)    Title:     RELIABILITY PREDICTION OF
ELECTRONIC EQUIPMENT     Scope:     The purpose of this handbook is to
establish and maintain consistant and uniform methods for estimating the
inherent reliability (i.e., the reliability of a mature design) of military
electronic equipment and systems. It provides a common basis for reliability
predictions during acquisition programs for military electronic systems and
equipment. It also establishes a common basis for comparing and evaluating
reliability predictions of related or competitive designs. The handbook is
intended to be used as a tool to increase the reliability of the equipment
being designed.

I like this one because it kind of points to DFM/CE through SPC, if so
applied. Anyone have experience using this document and applying all/some of
its porported requirements? Is there a "concise" IPC counterpart or is it a
combination of several?

MoonMan

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Date:         Wed, 16 Jan 2002 08:38:58 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

We are aware on no replacement for 217.  "Obsoletion / No Replacement" has
some people in a froth.

Various IPC documents have sampling tables.  For instance, IPC-6012A -
Qualification & Performance For Rigid Printed Boards has a C=0 table.

Dave Fish

----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 16, 2002 5:11 AM
Subject: Re: [TN] OLD TIME MIL STD FOLKS ONLY, OR NOT


> Been down the 217/218 road now awhile. You've got the "how to write it
> stuff" that matters little to me. Then, there's:
>
> Document ID:     MIL-HDBK-217F(2)    Title:     RELIABILITY PREDICTION OF
> ELECTRONIC EQUIPMENT     Scope:     The purpose of this handbook is to
> establish and maintain consistant and uniform methods for estimating the
> inherent reliability (i.e., the reliability of a mature design) of
military
> electronic equipment and systems. It provides a common basis for
reliability
> predictions during acquisition programs for military electronic systems
and
> equipment. It also establishes a common basis for comparing and evaluating
> reliability predictions of related or competitive designs. The handbook is
> intended to be used as a tool to increase the reliability of the equipment
> being designed.
>
> I like this one because it kind of points to DFM/CE through SPC, if so
> applied. Anyone have experience using this document and applying all/some
of
> its porported requirements? Is there a "concise" IPC counterpart or is it
a
> combination of several?
>
> MoonMan
>
> --------------------------------------------------------------------------
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>

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Date:         Wed, 16 Jan 2002 08:46:52 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
MIME-Version: 1.0
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Hi MoonMan,
One of the reasons why they let MIL-HDBK-217 die is that it contains too many
technically false assumptions. The F-revision was an attempt to fix this to
some degree, but a square peg just does not fit properly into a round
hole--so to speak. MIL-HDBK-217 is based solely on statistical data--many of
them flawed--and ignores the physical damage mechanisms [physics-of-failure]
at work.
And no, there is/are not "concise" IPC counterparts or a combination of
several documents, nor should there be.

Werner

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Date:         Wed, 16 Jan 2002 07:54:55 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         Werner Engelmaier <[log in to unmask]>

Werner and Dave,

Thanks for the input. The froth I'm not yet displaying concerns how the DoD
folks keep asking for compliance with the standard/spec. There are some
still asking for use of statistical methods, FMEA processes, and use of 217.
What's with this? Also, though not asking Werner to give up any secrets
about his reliability consultancy, what are we "civilians" using as
prediction methods/standards? I know some, but seems a target rich
environment beyond past histories, especially concerning "breakthrough"
technologies, let alone evolutionary types.

All the disk drive manufacturers, as but one minor example, state a MTBF
number usually around 300,000 hours or more. I've been involved with them
from a DFM standpoint and some simply have "great" warranty/exchange
programs. Hope my latest Maxtors hold up for another 300 hours. Sure hope
"old Jim M's" stuff flies well, as well, oh well.

Reminds me of a Waylon song with verse as my front tracks are headed for a
cold water well and my back tracks are covered with snow. Willie was part of
this as well. What comes around?

MoonMan

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Date:         Wed, 16 Jan 2002 08:12:06 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: Nickel Plating Snarl
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable

Hi Neal!  I am just guessing but the problem may be using 100 grams to
measure a 50 mil thick plating layer - get a copy of the ASTM E384 and =
ASTM
E18 specifications - the restrictions/requirments for test load versus
plating thickness should be listed. Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




"Neel, Robert" <[log in to unmask]>@ipc.org> on 01/15/2002
12:16:59 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please res=
pond
      to "Neel, Robert" <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] Nickel Plating Snarl

Folks,

Can someone explain to me why all my PCB houses are suddenly having
"spectacular cows" over this pcb plating spec:

"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, MIN=
IMUM
40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

This pcb is the substrate for some snap-acting domes and I need a hard =
and
conductive bearing surface for the dome feet.=A0 The plating spec comes=
 from
the dome manufacturer.

Is it the "electroless"?=A0 Is it the thickness? Is it the hardness
requirement? Is it the "nickel" vs "nickle"?=A0 (Funny thing is, though=
,
everyone is very happy to do gold rather than nickel.)

What gives?

Robert

=

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Date:         Wed, 16 Jan 2002 13:57:59 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Oliver Barlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Oliver Barlow <[log in to unmask]>
Subject:      IPC-SM-817
MIME-Version: 1.0
Content-Type: text/plain

To all at Technet,

I recently tried to order a copy of IPC-SM-817, General Requirements for
Dielectric Surface Mount Adhesives, only to be told that the document has
been made obsolete.

Can anyone tell if there is a replacement standard or an alternative?

Thanks to all in advance
Oliver
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
Oliver Barlow
Dynamix Technology Ltd, Oxfordshire, England
[log in to unmask]
www.dynamixtechnology.com
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

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Date:         Wed, 16 Jan 2002 09:19:33 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: LPI Soldermask discoloration...Picture is up.
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_7f.200b4032.2976e5f5_boundary"

--part1_7f.200b4032.2976e5f5_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Mornin' everybody!

I've got the picture up of the dark spots on the mask I talked about last
night. Go to:

http://www.stevezeva.homestead.com

and look at "Spots On Mask". Funny thing is, we built 20 assemblies and only
4 or 5 show this problem. The mask seems intact, passes a tape test, it just
has these ugly looking dark spots. I need to try and find out what would
cause this so I can explain it to our customer.

Thanks again!!!

-Steve Gregory-

--part1_7f.200b4032.2976e5f5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Mornin' everybody!
<BR>
<BR>I've got the picture up of the dark spots on the mask I talked about last night. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>and look at "Spots On Mask". Funny thing is, we built 20 assemblies and only 4 or 5 show this problem. The mask seems intact, passes a tape test, it just has these ugly looking dark spots. I need to try and find out what would cause this so I can explain it to our customer.
<BR>
<BR>Thanks again!!!
<BR>
<BR>-Steve Gregory-</FONT></HTML>

--part1_7f.200b4032.2976e5f5_boundary--

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Date:         Wed, 16 Jan 2002 14:13:07 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Geoff Layhe <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Geoff Layhe <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Just had to comment on this one. I can remember making 12 layer boards in
the mid 1980's and removing the unused pads to give a smoother hole and
reduce smear, nail heading etc on pads which were connected.- It worked for
us..

The thinking was that as the drill goes through a copper pad a lot of heat
is generated if the pad is connected to a large copper area then some of the
heat is dissipated but if the pad is unused then the heat has nowhere to go
and builds up in the drill leading to poor hole quality.
Anybody else ever remove unused pads for this reason?

Geoff Layhe



Private & Confidential:
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Date:         Wed, 16 Jan 2002 08:23:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Goldman, Patricia J." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Goldman, Patricia J." <[log in to unmask]>
Subject:      Re: rework
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Mark,
Is there an etch resist (such as tin or tin-lead) plated also?  If so, can you re-work before final etch (after resist strip, I suppose)?  The re-work drilling should easily remove the etch resist, then the copper should completely etch out without a problem.

Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]


-----Original Message-----
From: Mark Julstrom [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 3:12 AM
To: [log in to unmask]
Subject: [TN] rework


Broken tents caused NPT holes to be plated.   Re-work occurred back at drill to remove the copper from the hole wall, using a drill slightly larger than the original hole diameter. A thin layer of copper remains on the hole wall in some holes.  The drill size cannot be increased any further without violating spec.  Inspection will use an exacto knife to scrape out the remaining copper.  Are any better methods recommended for this type of rework?  There are approximately 20 panels, 10 holes per panel need to be scraped with exacto knife.

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Date:         Wed, 16 Jan 2002 10:00:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Goldman, Patricia J." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Goldman, Patricia J." <[log in to unmask]>
Subject:      Re: Nickel Plating Snarl
X-To:         "Neel, Robert" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I used to have my supplier of our gold bath measure the hardness of our gold.  They did it by taking a sample of our bath and plating it to sufficient thickness to do the Knoop hardness procedure.  The same thing should be able to be done for nickel.   There is a certain minimum thickness required to do the test properly, obviously greater than what our typical plated gold thickness was.

Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]


-----Original Message-----
From: Neel, Robert [mailto:[log in to unmask]]
Sent: Tuesday, January 15, 2002 1:17 PM
To: [log in to unmask]
Subject: [TN] Nickel Plating Snarl



Folks,

Can someone explain to me why all my PCB houses are suddenly having "spectacular cows" over this pcb plating spec:

"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

This pcb is the substrate for some snap-acting domes and I need a hard and conductive bearing surface for the dome feet.  The plating spec comes from the dome manufacturer.

Is it the "electroless"?  Is it the thickness? Is it the hardness requirement? Is it the "nickel" vs "nickle"?  (Funny thing is, though, everyone is very happy to do gold rather than nickel.)

What gives?

Robert

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Date:         Wed, 16 Jan 2002 10:17:57 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Joseph Spicuzza <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      QA System
MIME-Version: 1.0
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              boundary="----=_NextPart_000_001D_01C19E77.12068AC0"

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        charset="iso-8859-1"
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Hello TechNet
I'm looking for any "free" info. Subject: Setting up an ISO compliant QA =
dept. in an R&D group.
I'm quite familiar with the ISO 1994 series and have been an IPC member =
for over 20 years.
Just feels like I'm stuck in the mud on this one. Any ideas?
=20
Joseph Spicuzza
Quality Assurance Supervisor
Advanced Interconnect Products Division
Compunetics, Inc.
PH: 412 858-6166
FX:  412 373-8060
[log in to unmask]

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hello TechNet</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I'm looking for any "free" info. =
Subject: Setting=20
up an ISO compliant QA dept. in an R&amp;D group.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I'm quite familiar with the ISO 1994 =
series and=20
have been an IPC member for over 20 years.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Just feels like&nbsp;I'm stuck in the =
mud on this=20
one. Any ideas?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Joseph Spicuzza<BR>Quality Assurance=20
Supervisor<BR>Advanced Interconnect Products Division<BR>Compunetics,=20
Inc.<BR>PH: 412 858-6166<BR>FX:&nbsp; 412 373-8060<BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></=
FONT></DIV></BODY></HTML>

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=========================================================================
Date:         Wed, 16 Jan 2002 09:30:37 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: QA System
X-To:         Joe Spicuzza <[log in to unmask]>

R&D should bring some interesting comments from "creative" folks. Certainly
can't hinder those only concerned with one time results.

You've a world of experience over the past years, as you say. The 94 ISO
version wasn't as specific as the 2000 "update." 7.3 says it all for me in
that it simply requires, through the shall statements, something shall be
done from concept to customer acceptance, or not. It does not address R&D as
such - leaving you some lattitude.

Your company's business plan certainly addresses R&D as part of its G&A
section in the proforma arena. In this section, you should be able to
correlate research development, its time line, its costs, and when the Phd
types will be able to release a "working" model to engineering for
additional development and NPI.

The only thing ISO requires is you say what you do and do what you say. In
the R&D area, what do you really need to say? It's up to you though you must
provide product at some point.

MoonMan

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Date:         Wed, 16 Jan 2002 08:36:32 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Popielarski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Popielarski <[log in to unmask]>
Subject:      Re: Micro-BGA definition?
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Hi all,

You might want to check out JDEC's site, as they call it "Fine Pitch". =
Go to http://www.jedec.org/download/default.cfm and search for document =
MO-205.


Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618

Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578

WWW.QTA.NET

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>You might want to check out JDEC's =
site, as they=20
call it "Fine Pitch". Go to <A=20
href=3D"http://www.jedec.org/download/default.cfm">http://www.jedec.org/d=
ownload/default.cfm</A>&nbsp;and=20
search for document MO-205.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>

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=========================================================================
Date:         Wed, 16 Jan 2002 11:23:12 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jack Crawford <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jack Crawford <[log in to unmask]>
Subject:      Re: IPC-SM-817 truly IS available
X-To:         [log in to unmask]
X-cc:         Customer Service <[log in to unmask]>,
              Larry Crane <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Oliver, I extend our apologies for the ordering difficulty you encountered.=
 Please contact customer service directly at either [log in to unmask] or =
[log in to unmask] and they can quote you cost and shipping charges.

Background: IPC-SM-817 is an older document that had reached the end of =
its ANSI approval life. When it was offered to the committee for reaffirmat=
ion the committee makeup had changed because of invovlement with new =
technology. The members knowledgeable of the SM-817 technology replied =
that everything is still current.  We made a decision to continue to =
provide this important standard to industry but have experienced some =
difficulties with the product database that created the problem you =
encoutered.

Again, I apologize and reiterate that this document is available if you =
contact Customer Service directly.

Cordially,
Jack

>>> [log in to unmask] 01/16/02 07:57AM >>>
To all at Technet,

I recently tried to order a copy of IPC-SM-817, General Requirements for
Dielectric Surface Mount Adhesives, only to be told that the document has
been made obsolete.

Can anyone tell if there is a replacement standard or an alternative?

Thanks to all in advance
Oliver
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
Oliver Barlow
Dynamix Technology Ltd, Oxfordshire, England
[log in to unmask]
www.dynamixtechnology.com=20
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

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=========================================================================
Date:         Wed, 16 Jan 2002 10:41:27 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Rick Howieson <[log in to unmask]>
Subject:      BGA/Vias
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We have a board with a BGA that has quite a few vias on the board located
under the BGA. My question is...Should there be a limit of vias on the board
located under the BGA? When we need to rework the BGA that area of the board
seems to "sink" causing more problems, not to mention the integrity of the
vias.
Thanks,
Rick Howieson
Delta Group Electronics, Inc.

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=========================================================================
Date:         Wed, 16 Jan 2002 12:53:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: LPI Soldermask discoloration...Picture is up.
X-To:         [log in to unmask]
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Seems to be a sharp correlation between the spots on the mask and the =
"goop" holding the jumper wire in place, eh?

Dave Fish
  ----- Original Message -----=20
  From: Stephen Gregory=20
  To: [log in to unmask]
  Sent: Wednesday, January 16, 2002 6:19 AM
  Subject: Re: [TN] LPI Soldermask discoloration...Picture is up.


  Mornin' everybody!=20

  I've got the picture up of the dark spots on the mask I talked about =
last night. Go to:=20

  http://www.stevezeva.homestead.com=20

  and look at "Spots On Mask". Funny thing is, we built 20 assemblies =
and only 4 or 5 show this problem. The mask seems intact, passes a tape =
test, it just has these ugly looking dark spots. I need to try and find =
out what would cause this so I can explain it to our customer.=20

  Thanks again!!!=20

  -Steve Gregory-=20

------=_NextPart_000_001E_01C19E8C.DDD94BA0
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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Seems to be a sharp correlation between =
the spots=20
on the mask and the "goop" holding the jumper wire in place, =
eh?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Dave Fish</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>Stephen =
Gregory</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, January 16, =
2002 6:19=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] LPI =
Soldermask=20
  discoloration...Picture is up.</DIV>
  <DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Mornin' =
everybody!=20
  <BR><BR>I've got the picture up of the dark spots on the mask I talked =
about=20
  last night. Go to: <BR><BR><A=20
  =
href=3D"http://www.stevezeva.homestead.com">http://www.stevezeva.homestea=
d.com</A>=20
  <BR><BR>and look at "Spots On Mask". Funny thing is, we built 20 =
assemblies=20
  and only 4 or 5 show this problem. The mask seems intact, passes a =
tape test,=20
  it just has these ugly looking dark spots. I need to try and find out =
what=20
  would cause this so I can explain it to our customer. <BR><BR>Thanks =
again!!!=20
  <BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_001E_01C19E8C.DDD94BA0--

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Date:         Wed, 16 Jan 2002 10:17:26 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              My Nguyen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Way too many Product Oven Profiles
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Good morning Techneters,

I am working on oven profiler consolidation project.
Currently, we have 540 Product Profile for each oven.
For 13 oven machine, we have 7020 profiles.  That is
way too many for a memory manufacture!

We currently use water-soluble solder and no clean
solder.  We know that for each product, the pre-heat
zone, soak-zone, re-flow zone, and temperature could
be a bit different from one Solder Paste Manufacture
to other, or from one Solder Paste type to others, or
even from single side, to double side.

HOWEVER, for memory, the width, length, thickness, and
number of ICs, resisters, capacitors, and others are
limited to a certain number, i.e, PCB height is less
than 1.7 inches; PCB thickness is equal or less than
0.05 inch; PCB length follow the spec. of 5.25” for
DIMM, DDR, RIMM, 2.66” for SODIMM, 4.25” for 72 Pin
SIMM, etc.

I have heard that out there, there is a way to reduce
from 1000s down to 10-100 oven profiles based on
Mass/Density.  And of course, there are many other
scientific ways that I have not heard of.  Please help
me! What would be the best method you recommend or you
have successfully tried to reduce the number of oven
profiles down to a control/reasonable numbers?

Your advice and suggestion are greatly appreciated.

Stacy


__________________________________________________
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Send FREE video emails in Yahoo! Mail!
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Date:         Wed, 16 Jan 2002 11:05:36 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Barry Gallegos <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Centroid extraction from Gerbers.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Good day T'netters

Question?
        is there a program other than GC Place or Circuit Cam that can do
Centroid Extraction.


Barry.

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Date:         Wed, 16 Jan 2002 13:36:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guy Ramsey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: BGA/Vias
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In-Reply-To:  <71417DD0BB76D311B68300104B8FDEE83C784B@SUPERVISOR>
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It's probably not the vias under the BGA causing the board to sink. You are
seeing the response of the board to isolated expansion caused by heating a
small portion of the board. Try preheating a larger portion of the bottom
side of the board. It is very common to have vias under the BGA, they
provide escapes for the I/O in the array.

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
> Sent: Wednesday, January 16, 2002 12:41 PM
> To: [log in to unmask]
> Subject: [TN] BGA/Vias
>
>
> We have a board with a BGA that has quite a few vias on the board located
> under the BGA. My question is...Should there be a limit of vias
> on the board
> located under the BGA? When we need to rework the BGA that area
> of the board
> seems to "sink" causing more problems, not to mention the integrity of the
> vias.
> Thanks,
> Rick Howieson
> Delta Group Electronics, Inc.
>
> ------------------------------------------------------------------
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> additional
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>

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Date:         Wed, 16 Jan 2002 12:30:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
X-To:         My Nguyen <[log in to unmask]>

Did a bunch during focused IR days. None worked. Have no more than three I
carry with me now but for one "flexible" save my butt one.

MoonMan

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Date:         Wed, 16 Jan 2002 13:46:18 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guy Ramsey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
X-To:         My Nguyen <[log in to unmask]>
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MIME-Version: 1.0
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It should be possible but, we would be messing with a very important process
step in your manufacturing cycle. We may be able to help but we would need
much more information. Please call the EMPF Helpline. 610 362-1320

Guy Ramsey
American Competitiveness Institute
One International Plaza Suite 600
Philadelphia PA
610 362-1200 ext. 107

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of My Nguyen
> Sent: Wednesday, January 16, 2002 1:17 PM
> To: [log in to unmask]
> Subject: [TN] Way too many Product Oven Profiles
>
>
> Good morning Techneters,
>
> I am working on oven profiler consolidation project.
> Currently, we have 540 Product Profile for each oven.
> For 13 oven machine, we have 7020 profiles.  That is
> way too many for a memory manufacture!
>
> We currently use water-soluble solder and no clean
> solder.  We know that for each product, the pre-heat
> zone, soak-zone, re-flow zone, and temperature could
> be a bit different from one Solder Paste Manufacture
> to other, or from one Solder Paste type to others, or
> even from single side, to double side.
>
> HOWEVER, for memory, the width, length, thickness, and
> number of ICs, resisters, capacitors, and others are
> limited to a certain number, i.e, PCB height is less
> than 1.7 inches; PCB thickness is equal or less than
> 0.05 inch; PCB length follow the spec. of 5.25” for
> DIMM, DDR, RIMM, 2.66” for SODIMM, 4.25” for 72 Pin
> SIMM, etc.
>
> I have heard that out there, there is a way to reduce
> from 1000s down to 10-100 oven profiles based on
> Mass/Density.  And of course, there are many other
> scientific ways that I have not heard of.  Please help
> me! What would be the best method you recommend or you
> have successfully tried to reduce the number of oven
> profiles down to a control/reasonable numbers?
>
> Your advice and suggestion are greatly appreciated.
>
> Stacy
>
>
> __________________________________________________
> Do You Yahoo!?
> Send FREE video emails in Yahoo! Mail!
> http://promo.yahoo.com/videomail/
>
> ------------------------------------------------------------------
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Wed, 16 Jan 2002 12:44:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dunn, Dwayne" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dunn, Dwayne" <[log in to unmask]>
Subject:      Re: Centroid extraction from Gerbers.
X-To:         Barry Gallegos <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Gerbcam from Tecnomatix-Unicam.

http://www.unicam.com/


Circuit Cam

http://www.aiscorp.com/



Dwayne





-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 12:06 PM
To: [log in to unmask]
Subject: [TN] Centroid extraction from Gerbers.


Good day T'netters

Question?
        is there a program other than GC Place or Circuit Cam that can do
Centroid Extraction.


Barry.

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Date:         Wed, 16 Jan 2002 11:30:26 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Re: Centroid extraction from Gerbers.
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Barry,

Unicam has the GerbCAM module. Pretty simple to use, of great help if you
are a Unicam user.

Jorge

-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 11:06 AM
To: [log in to unmask]
Subject: [TN] Centroid extraction from Gerbers.


Good day T'netters

Question?
        is there a program other than GC Place or Circuit Cam that can do
Centroid Extraction.


Barry.

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Date:         Wed, 16 Jan 2002 12:36:08 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         Guy Ramsey <[log in to unmask]>

Agree with that. Without board reaching equillibrium (spelling?) top to
bottom, no even solder joint formation (in the case of BGA's - ball
collapse) possible. Uneven "sinking" (collapse) bound to occur but usually
within nanoseconds of others - depending on thermal conditions.

MoonMan

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Date:         Wed, 16 Jan 2002 10:50:52 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Anderson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Anderson <[log in to unmask]>
Subject:      BGA rework
MIME-Version: 1.0
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TechNetters,

I am sure there has been some discussion on this subject in the past, but I
need to ask a fairly simple question (I hope).  Is there a limit to the
number of times BGA packages can be attached to and removed from a BGA
before the integrity of the board is compromised?  Is it in a spec
someplace?
Thanks in advance

Don Anderson
Compunetics, Inc.

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Date:         Wed, 16 Jan 2002 11:45:29 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Steve Babiuch <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Babiuch <[log in to unmask]>
Subject:      Resin Recession
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Howdy folks,
I just reviewed the December discussion about resin recession vs hole
wall pull away. I think the failure mechanism is clear, lack of adhesion
between the dielectric and the electroless copper. How the failure shows
up and is described is influenced by many factors.  Aside from the
failure mechanism there remains a question of whether this is truly a
defect. I am concerned about the hole wall in press fit holes, where a
fracturing or push out of the separated copper can result in flakes of
copper material in/on the assembly. IPC does not address this in their
specs. Any comments ?

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<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Howdy folks,<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>I just reviewed the December discussion about resin
recession <span class=3DSpellE>vs</span> <span class=3DGramE>hole</span> =
wall pull
away. I think the failure mechanism is clear, lack of adhesion between =
the
dielectric and the <span class=3DSpellE>electroless</span> copper. How =
the failure
shows up and is described is influenced by many factors. <span
style=3D'mso-spacerun:yes'>&nbsp;</span>Aside from the failure mechanism =
there remains
a question of whether this is truly a defect. I am concerned about the =
<span
class=3DGramE>hole</span> wall in press fit holes, where a fracturing or =
push out
of the separated copper can result in flakes of copper material in/on =
the
assembly. IPC does not address this in their specs. Any <span =
class=3DGramE>comments
?</span><o:p></o:p></span></font></p>

</div>

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Date:         Wed, 16 Jan 2002 14:11:08 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: LPI Soldermask discoloration...Picture is up.
X-To:         [log in to unmask]
MIME-Version: 1.0
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Hi Dave!

Yep sure does, the spots are around where the jumper wires are routed. The
operators who performed the jumper wires said that the spots appeared under
where they had applied the kapton tape before they did any bonding...and I
did just confirm that, there are a couple of boards still WIP that have the
wires attached, the kapton tape still on the wires, and no tak-pak has been
done. Sure enough, there are spots on the mask. What's even more confusing is
that the spots don't appear under every place that there's kapton tape...it's
just random places?!?!

The mask seems to be perfectly intact, I did a tape test on the areas...no
problems.
the thickness is fine, and the surface of the mask is as smooth as the rest
of the board...it's just discolored in those certain areas. There's only a
few boards out of the 20 that we built that have this problem, and they were
all processed exactly the same.

Really baffled by this one...

-Steve Gregory-



Seems to be a sharp correlation between the spots on the mask and the "goop"
holding the jumper wire in place, eh?

Dave Fish


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Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Dave!
<BR>
<BR>Yep sure does, the spots are around where the jumper wires are routed. The operators who performed the jumper wires said that the spots appeared under where they had applied the kapton tape before they did any bonding...and I did just confirm that, there are a couple of boards still WIP that have the wires attached, the kapton tape still on the wires, and no tak-pak has been done. Sure enough, there are spots on the mask. What's even more confusing is that the spots don't appear under every place that there's kapton tape...it's just random places?!?!
<BR>
<BR>The mask seems to be perfectly intact, I did a tape test on the areas...no problems.
<BR>the thickness is fine, and the surface of the mask is as smooth as the rest of the board...it's just discolored in those certain areas. There's only a few boards out of the 20 that we built that have this problem, and they were all processed exactly the same.
<BR>
<BR>Really baffled by this one...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR>Seems to be a sharp correlation between the spots on the mask and the "goop" holding the jumper wire in place, eh?
<BR>
<BR>Dave Fish
<BR></FONT></HTML>

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Date:         Wed, 16 Jan 2002 14:10:11 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Roger M. Stoops" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

I have been following this thread with interest.  When I asked a pcb vendor
about having non-functional pads in the inner layers, they said it was not
a good idea, that the unattached pads/lands would move around, or "float,"
and cause potential mfg problems, such as shorts to other copper.
Question:  Is there any truth to this statement, or is this just an old
husband's tale?
TIA,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]


Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511



                    "<Peter
                    George               To:     [log in to unmask]
                    Duncan>"             cc:
                    Sent by:             Subject:     Re: [TN] Remove unused "dead" pads on internal layers
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/15/02
                    09:09 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    peter.duncan





Hi,

Actually these "unused" pads are replicates of the hole "rules" created for
the surface layers. Most routing packages, or routers, seem to do this by
default for each layer to save manual replication where traces, etc are to
be connected. (At least PADS, Alegro and Mentor do). On the grounds that
it's always easier to destroy than to build, it's easier to delete pad data
than to create it, so it's put in by default as there's a good chance it
will be needed.

I still say you should consider hole barrel strength/support issues before
just deleting them - e.g. they can constrain the "resin recession" and hole
wall pull-away that have been recent threads on this forum. Think of the
"unused" pads as 'wall ties' holding the copper at frequent intervals to
the hole wall. Copper bulging or pull-away in the event of recession or
whatever is reduced.

Peter Duncan




                    Hinners Hans M Civ
                    WRALC/LUGE                To:     [log in to unmask]
                    <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    NS.AF.MIL>                Aero/ST Group)
                    Sent by: TechNet          Subject:     Re: [TN] Remove
unused "dead" pads on
                    <[log in to unmask]>         internal layers


                    01/15/02 09:40 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Hinners
                    Hans M Civ
                    WRALC/LUGE






Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat

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Date:         Wed, 16 Jan 2002 14:15:19 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Resin Recession
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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We see boards from many, many board shops and 95% of them have little if any
resin recession or hole wall pullaway in their boards prior to or after
thermal stress.

With today's laminate systems and plating systems the condition should not
exist.

Many years ago I had this discussion with a friend in the industry, Terry
Kingston, now in another industry and he acused me of wanting a perfect
board.  My reasoning is that if I have two board shops - one with good hole
wall adhesion and one with little hole wall adhesion - I am going to buy from
the one with good adhesion.  The other boards may be spec compliant, but they
are just not as robust - all other attributes being equal.

I can see where insertion of pins could result in peeling if the hole wall
was not attached and that is a concern.

My two cents

Susan Mansilla
Robisan Lab

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Date:         Wed, 16 Jan 2002 14:32:51 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Truit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Truit <[log in to unmask]>
Organization: RBB Systems Inc.
Subject:      Aqueous cleaning of surface mount potentiometers
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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I wanted to hear how fellow Technet people are processing surface mount
potentiometers.

I have experienced some field failures recently in this area.  Water has
leaked into a "Sealed" potentiometer.  When power is applied an
alternate circuit grows inside the pot causing the part to fail.

We are processing this part using an OA solder paste through a normal
pick and place operation.  Reflow profile takes this through a normal
reflow curve Max. Peak temperature of 195-205 degrees C with a Ramp rate
of 2-2.5 Degrees C.  We then add on a few through hole parts through
progressive assembly then  wave solder and clean the assembly.

We are utilizing an Electrovert Aquastorm 100.  We process the boards
through at 4 feet per minute.  Water temperature is 145 degrees F.

We have been cleaning boards (and potentiometers) for over eight years
with never a problem.  This one has sure surprised me.  Just wondering
if anyone else has had any experience with this and what they have done
to fix this other than hand soldering the pot on in final.


--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH  44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]

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Date:         Wed, 16 Jan 2002 11:33:28 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              My Nguyen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
X-To:         "Krug, Dick" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Technetters,

Firstly, thanks so much for your input!

We use:

- Heller Oven Profiles, most of them are 8-9 zones.
- Solder Paste Type: Water Soluble, Sn63Pb37 - P3
type.
- Board: 6 layers; thickness is equal or less than
0.05"

I agree with Mr. Krug that we should look for a
nominal oven profile that would satisfy about 80% of
the product profiles.  However, to short through 7000
of them, it would be A LOT.

Also, there will be so much resistance to this change,
Q.A. will blame on different outcome, Production would
do the same thing until ... they reach a comfortable
zone.  By having a scientific method, I may be able to
convince them and have them cooperated much easier
than shorting through 7000 to find the commonalities
among them.

A typical profile at here is:
100 - 140 - 160 - 175 - 170 - 190 -235 -255
where process windows are:
30-150 degree: 50 - 140 sec.
150-183: 50-120 sec
above 183: 40-80 sec

Depending on the products and panel layout (maximum
panel size: 7" x 12")the temperature for each zone can
be changed +/-20.

Again, I am looking for a scientific way that will not
only satisfy the product quality requirement (all
class 2) but also acceptable from strict people base
on what they called: Logical/scientific thinking.

Thanks,

Stacy


--- "Krug, Dick" <[log in to unmask]> wrote:
> I have seen the same issues and have reduced the
> number of different
> profiles dramatically.  When working for an OEM
> which had similar PWB layer
> counts, similar component densities and only one
> solder paste, we got down
> to 1 profile per oven model.  Now in the contract
> world, we are up to only 7
> oven profiles after over a year of our reduced
> profile initiative; RMA
> Standard, RMA Heavy, RMA Light, RMA Standard
> Nitrogen, RMA Heavy Nitrogen,
> RMA Medium Heavy and Cure.  We use the same profile
> on RMA paste and WS
> paste, and both the Sn63Pb37 and Sn62Pb36Ag2 alloys.
>
>
> Using our paste suppliers' "nominal" profiles and a
> "typical" (obviously a
> judgment call) assembly, we defined the profile we
> wanted to match.  After
> several iterations (because we wanted an "exact"
> match) we had our RMA
> Standard profile which is used on ~80% of all
> assemblies.  All other
> profiles are variations because RMA Standard is not
> acceptable.
>
> Each oven model has different zone settings and
> speeds, but the same profile
> name.
>
> The profile we "matched" is as follows:
> Time  Temp
> (sec) (deg C)
> 0     25
> 30    49
> 60    73
> 90    97
> 120   121
> 150   145
> 180   169
> 210   184
> 240   215
> 270   183
> 300   120
> 330   60
>
> Dick Krug
> Sypris Electronics
>
> -----Original Message-----
> From: My Nguyen [mailto:[log in to unmask]]
> Sent: Wednesday, January 16, 2002 1:17 PM
> To: [log in to unmask]
> Subject: [TN] Way too many Product Oven Profiles
>
>
> Good morning Techneters,
>
> I am working on oven profiler consolidation project.
> Currently, we have 540 Product Profile for each
> oven.
> For 13 oven machine, we have 7020 profiles.  That is
> way too many for a memory manufacture!
>
> We currently use water-soluble solder and no clean
> solder.  We know that for each product, the pre-heat
> zone, soak-zone, re-flow zone, and temperature could
> be a bit different from one Solder Paste Manufacture
> to other, or from one Solder Paste type to others,
> or
> even from single side, to double side.
>
> HOWEVER, for memory, the width, length, thickness,
> and
> number of ICs, resisters, capacitors, and others are
> limited to a certain number, i.e, PCB height is less
> than 1.7 inches; PCB thickness is equal or less than
> 0.05 inch; PCB length follow the spec. of 5.25" for
> DIMM, DDR, RIMM, 2.66" for SODIMM, 4.25" for 72 Pin
> SIMM, etc.
>
> I have heard that out there, there is a way to
> reduce
> from 1000s down to 10-100 oven profiles based on
> Mass/Density.  And of course, there are many other
> scientific ways that I have not heard of.  Please
> help
> me! What would be the best method you recommend or
> you
> have successfully tried to reduce the number of oven
> profiles down to a control/reasonable numbers?
>
> Your advice and suggestion are greatly appreciated.
>
> Stacy
>
>
> __________________________________________________
> Do You Yahoo!?
> Send FREE video emails in Yahoo! Mail!
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>
>
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=========================================================================
Date:         Wed, 16 Jan 2002 14:41:01 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: hand lotion
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This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

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        charset="iso-8859-1"

Stewart, in addition to the IC Lotion we also use Tech Spay Zero Charge
Anti-Static Hand Lotion Stock # 1702-8L. PO Box 949 Amarillo, TX79105.

Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]

                -----Original Message-----
                From:   Stuart Korringa [mailto:[log in to unmask]]
                Sent:   Monday, January 14, 2002 14:49 PM
                To:     [log in to unmask]
                Subject:        [TN] hand lotion

                What are some acceptable hand lotions that could be
purchased by my company for
                distribution to the assembly areas? There must be something
that is not
                repugnant and would make the operators be happy to use.

                Thanks,

                Stu Korringa

                Smiths Electronic Systems
                Grand Rapids, Mi



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charset=3Diso-8859-1">
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5.5.2652.35">
<TITLE>RE: [TN] hand lotion</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">Stewart, in addition to the IC Lotion =
we also use Tech Spay Zero Charge Anti-Static Hand Lotion Stock # =
1702-8L. PO Box 949 Amarillo, TX79105.</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From:&nbsp;&nbsp; Stuart Korringa =
[<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>=
]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent:&nbsp;&nbsp;</FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Monday, January 14, 2002 14:49 PM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To:&nbsp;&nbsp;&nbsp;&nbsp;</FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">[TN] hand lotion</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">What are some acceptable hand lotions =
that could be purchased by my company for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">distribution to the assembly areas? =
There must be something that is not</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">repugnant and would make the =
operators be happy to use.</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Stu Korringa</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Smiths Electronic Systems</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Grand Rapids, Mi</FONT>
</P>
<BR>

<P><FONT SIZE=3D2 =
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files are intended solely for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">the individual or entity to whom they =
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<BR><FONT SIZE=3D2 FACE=3D"Arial">is the property of Smiths =
Aerospace.&nbsp; If you are not the intended</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">recipient, please do not read, copy, =
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Date:         Wed, 16 Jan 2002 12:40:58 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Rick Howieson <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I probably didn't make myself clear. The problem is the board itself
collapses/sinks/"potato chips"...in the area being heated, i.e. BGA
location.
Rick

-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 11:36 AM
To: [log in to unmask]
Subject: Re: [TN] BGA/Vias


Agree with that. Without board reaching equillibrium (spelling?) top to
bottom, no even solder joint formation (in the case of BGA's - ball
collapse) possible. Uneven "sinking" (collapse) bound to occur but usually
within nanoseconds of others - depending on thermal conditions.

MoonMan

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Date:         Wed, 16 Jan 2002 11:49:09 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Denis Lefebvre <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Denis Lefebvre <[log in to unmask]>
Subject:      Re: Centroid extraction from Gerbers.
X-To:         Barry Gallegos <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

CAM350 will do it... IF you have the FULL version.

At 11:05 AM 1/16/2002 -0700, you wrote:
>Good day T'netters
>
>Question?
>         is there a program other than GC Place or Circuit Cam that can do
>Centroid Extraction.
>
>
>Barry.
>
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Date:         Wed, 16 Jan 2002 14:54:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Francois Monette <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Francois Monette <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         [log in to unmask]
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Peter,

No need to apologize, I totally agree with your input. Keep things dry until
needed is the best way to stay clear of all moisture-related problems, for
boards as well as for moisture sensitive devices.

The only caveat is that things can get a little more complicated on a real
production line with any significant amount of changeovers. This is when the
proper management and control can turn into a logistical nightmare for a
normal human being. As you explained so well, moisture diffusion is a
complex phenomenon and moisture-sensitive components that have already been
exposed to ambient conditions are not necessarily protected by simply
placing them back in a dry environment for a while.

Automating the control of materials is only a practical approach to resolve
this issue and to make sure that you mimize the frequency and duration of
any bake cycle. The philosophy is "Make things as simple as possible, but
not more". I could also add "To get high yields and high quality, remove the
human factor from your process control".

Since there is a meeting of the joint IPC/JEDEC committee next week, I can
try to find out if anyone has been thinking about a standard for PWB
moisture control. I'll keep you posted.

Francois Monette
Cogiscan Inc.


Date:    Wed, 16 Jan 2002 12:43:55 +0800
From:    "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: PWB Moisture

This isn't a very useful response, perhaps, but the question is an
interesting one. I offer some additional considerations/mind benders when
contemplating the answer to this:

1) Moisture absorbtion depends on the material(s) the board is made from,
and the overall amount of moisture absorbed will be related to the volume
of the materials used.
2) The material volume depends on the board design and is therefore a bit
variable.
3) Opportunity to absorb moisture depends on humidity, temperature and
time.
4) Tracking moisture exposure depends on having an army of arithmeticians
or alternatively a tracking system such as our friend Francois Monette has
to offer.

What we need here is some way of determining a Moisture Sensitivity
Category for the various materials and their combinations, as used by
component manufacturers and a means of determining the rate of moisture
take-up for any given design - quite a career for somebody.

On the other hand, you can simply pursuade your fab house to pack your
nice, new, dry boards in individual sealed bags with some desiccant that
you don't open until the moment you need them (or reseal properly after
in-coming inspection) on the line. If the boards have been lying around for
a year or so (in their sealed bags), and/or you're in any doubt about how
dry the boards are, you can then bake them out for about 2 hours at 90 deg
C just prior to use. This last has been common practice for many years,
although I object on principle to having to do this - one more thermal
excursion too many for the board.

Call me old-fashioned, but why look for ways to make life so complicated,
when a little management and control can save a lot of unnecessary effort
and cost? (Sorry, Francois!).

Peter Duncan

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Date:         Wed, 16 Jan 2002 15:13:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tempea, Ioan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Stacy,

check ECD's website, first for the interesting point of view on robust
profiles, http://www.ecd.com/emfg/instruments/papers/rookspaper.htm, then to
download their profile planner at
http://www.ecd.com/emfg/instruments/download.asp?action=form&file=ProfilePla
nner1_07b.EXE.

Then I would go for a group technology approach, that is:
- group your 8000 boards according to their thermal masses, and be tough,
don't make more than 5 groups
- try to see if you can't transfer the boards from a certain group to others
by having a DFM (panelizing, redesign, etc) input that would alter the
thermall masses enough to make them transferrable
- develop your robust profile according to the paste you use and tweak it a
little so that the boards from your medium thermal mass group come out OK
- use the previously profile for all the groups with inferior thermal mass,
watch for exceptions
- develop another profile by bumping up the robust profile, so that your
highest thermal mass boards solder well

Like this, ideally you have 2 reference profiles that should cover 90% of
your needs.

Keep in mind that you must assess each assembly according to the IPC-610,
judging the joints that you obtain. If they are OK, don't bother profiling
each board, because you will never get the perfect distribution you get with
your 8000 custom profiles. However, keep a keen eye on the first batches of
each assembly. If they have touchy components, profile them and try to be
under 225 celsius in the spike zone on the top of the BGAs.

Then, be ready for the exceptions, but there shouldn't be too many.

This is my point of view as 100% no-clean user. But, if it can be done on
no-clean, WS should be easier, isn't it?

Regards,
Ioan

> -----Original Message-----
> From: My Nguyen [SMTP:[log in to unmask]]
> Sent: Wednesday, January 16, 2002 2:33 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Way too many Product Oven Profiles
>
> Technetters,
>
> Firstly, thanks so much for your input!
>
> We use:
>
> - Heller Oven Profiles, most of them are 8-9 zones.
> - Solder Paste Type: Water Soluble, Sn63Pb37 - P3
> type.
> - Board: 6 layers; thickness is equal or less than
> 0.05"
>
> I agree with Mr. Krug that we should look for a
> nominal oven profile that would satisfy about 80% of
> the product profiles.  However, to short through 7000
> of them, it would be A LOT.
>
> Also, there will be so much resistance to this change,
> Q.A. will blame on different outcome, Production would
> do the same thing until ... they reach a comfortable
> zone.  By having a scientific method, I may be able to
> convince them and have them cooperated much easier
> than shorting through 7000 to find the commonalities
> among them.
>
> A typical profile at here is:
> 100 - 140 - 160 - 175 - 170 - 190 -235 -255
> where process windows are:
> 30-150 degree: 50 - 140 sec.
> 150-183: 50-120 sec
> above 183: 40-80 sec
>
> Depending on the products and panel layout (maximum
> panel size: 7" x 12")the temperature for each zone can
> be changed +/-20.
>
> Again, I am looking for a scientific way that will not
> only satisfy the product quality requirement (all
> class 2) but also acceptable from strict people base
> on what they called: Logical/scientific thinking.
>
> Thanks,
>
> Stacy
>
>
> --- "Krug, Dick" <[log in to unmask]> wrote:
> > I have seen the same issues and have reduced the
> > number of different
> > profiles dramatically.  When working for an OEM
> > which had similar PWB layer
> > counts, similar component densities and only one
> > solder paste, we got down
> > to 1 profile per oven model.  Now in the contract
> > world, we are up to only 7
> > oven profiles after over a year of our reduced
> > profile initiative; RMA
> > Standard, RMA Heavy, RMA Light, RMA Standard
> > Nitrogen, RMA Heavy Nitrogen,
> > RMA Medium Heavy and Cure.  We use the same profile
> > on RMA paste and WS
> > paste, and both the Sn63Pb37 and Sn62Pb36Ag2 alloys.
> >
> >
> > Using our paste suppliers' "nominal" profiles and a
> > "typical" (obviously a
> > judgment call) assembly, we defined the profile we
> > wanted to match.  After
> > several iterations (because we wanted an "exact"
> > match) we had our RMA
> > Standard profile which is used on ~80% of all
> > assemblies.  All other
> > profiles are variations because RMA Standard is not
> > acceptable.
> >
> > Each oven model has different zone settings and
> > speeds, but the same profile
> > name.
> >
> > The profile we "matched" is as follows:
> > Time  Temp
> > (sec) (deg C)
> > 0     25
> > 30    49
> > 60    73
> > 90    97
> > 120   121
> > 150   145
> > 180   169
> > 210   184
> > 240   215
> > 270   183
> > 300   120
> > 330   60
> >
> > Dick Krug
> > Sypris Electronics
> >
> > -----Original Message-----
> > From: My Nguyen [mailto:[log in to unmask]]
> > Sent: Wednesday, January 16, 2002 1:17 PM
> > To: [log in to unmask]
> > Subject: [TN] Way too many Product Oven Profiles
> >
> >
> > Good morning Techneters,
> >
> > I am working on oven profiler consolidation project.
> > Currently, we have 540 Product Profile for each
> > oven.
> > For 13 oven machine, we have 7020 profiles.  That is
> > way too many for a memory manufacture!
> >
> > We currently use water-soluble solder and no clean
> > solder.  We know that for each product, the pre-heat
> > zone, soak-zone, re-flow zone, and temperature could
> > be a bit different from one Solder Paste Manufacture
> > to other, or from one Solder Paste type to others,
> > or
> > even from single side, to double side.
> >
> > HOWEVER, for memory, the width, length, thickness,
> > and
> > number of ICs, resisters, capacitors, and others are
> > limited to a certain number, i.e, PCB height is less
> > than 1.7 inches; PCB thickness is equal or less than
> > 0.05 inch; PCB length follow the spec. of 5.25" for
> > DIMM, DDR, RIMM, 2.66" for SODIMM, 4.25" for 72 Pin
> > SIMM, etc.
> >
> > I have heard that out there, there is a way to
> > reduce
> > from 1000s down to 10-100 oven profiles based on
> > Mass/Density.  And of course, there are many other
> > scientific ways that I have not heard of.  Please
> > help
> > me! What would be the best method you recommend or
> > you
> > have successfully tried to reduce the number of oven
> > profiles down to a control/reasonable numbers?
> >
> > Your advice and suggestion are greatly appreciated.
> >
> > Stacy
> >
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Send FREE video emails in Yahoo! Mail!
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> >
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Date:         Wed, 16 Jan 2002 15:27:32 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Howard Watson <[log in to unmask]>
Subject:      Al Electrolytic Capacitors leaking
MIME-Version: 1.0
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Technetters,

Please help!  I have some Aluminum Electrolytic Capacitors that are
leaking fluid on the top of the can after reflow.  My peak temperature on
the top of the can is 218C, with a time above 183 at 53 seconds, which
seem to be appropriate.  The manufacturer recommends the time above 200C
to be 20 seconds maximum, which is too little on these boards to get good
solder on all the components.  The boards are reflowed in a Vitronics 10
zone convection oven.  The part is Nichicon #2309369R25.  Is anyone
familiar with this type of problem, and if so any suggestions will be
greatly appreciated!   Are these type of parts prone to failure at high
temperatures?

Howard Watson
Manufacturing Engineer
AMETEK/Dixson
--=_alternative 00704CC187256B43_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Technetters,</font>
<br>
<br><font size=2 face="sans-serif">Please help! &nbsp;I have some Aluminum Electrolytic Capacitors that are leaking fluid on the top of the can after reflow. &nbsp;My peak temperature on the top of the can is 218C, with a time above 183 at 53 seconds, which seem to be appropriate. &nbsp;The manufacturer recommends the time above 200C to be 20 seconds maximum, which is too little on these boards to get good solder on all the components. &nbsp;The boards are reflowed in a Vitronics 10 zone convection oven. &nbsp;The part is Nichicon #2309369R25. &nbsp;Is anyone familiar with this type of problem, and if so any suggestions will be greatly appreciated! &nbsp; Are these type of parts prone to failure at high temperatures?</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
--=_alternative 00704CC187256B43_=--

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Date:         Wed, 16 Jan 2002 15:50:34 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: LPI Soldermask discoloration...Picture is up.
X-To:         [log in to unmask]
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Steve

So, are these spots are an adhesive res that:
* Pilled-up mature rolls of tape?
* Stuck to the board in areas where exuberently applied?

We have had res problems with some versions of "Kapton" Tape".  They =
are:
* Not all created the same, regardless of their name.
* Shelf life limited.
* Affected by the shop environment

Dave Fish

----- Original Message -----=20
  From: Stephen Gregory=20
  To: [log in to unmask]
  Sent: Wednesday, January 16, 2002 11:11 AM
  Subject: Re: [TN] LPI Soldermask discoloration...Picture is up.


  Hi Dave!=20

  Yep sure does, the spots are around where the jumper wires are routed. =
The operators who performed the jumper wires said that the spots =
appeared under where they had applied the kapton tape before they did =
any bonding...and I did just confirm that, there are a couple of boards =
still WIP that have the wires attached, the kapton tape still on the =
wires, and no tak-pak has been done. Sure enough, there are spots on the =
mask. What's even more confusing is that the spots don't appear under =
every place that there's kapton tape...it's just random places?!?!=20

  The mask seems to be perfectly intact, I did a tape test on the =
areas...no problems.=20
  the thickness is fine, and the surface of the mask is as smooth as the =
rest of the board...it's just discolored in those certain areas. There's =
only a few boards out of the 20 that we built that have this problem, =
and they were all processed exactly the same.=20

  Really baffled by this one...=20

  -Steve Gregory-=20



  Seems to be a sharp correlation between the spots on the mask and the =
"goop" holding the jumper wire in place, eh?=20

  Dave Fish=20


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Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Steve</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>So, are these spots are an adhesive res =

that:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>* Pilled-up mature rolls of =
tape?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>* Stuck to the board in areas where =
exuberently=20
applied?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>We have had res problems with some =
versions of=20
"Kapton" Tape".&nbsp; They are:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>* Not all created the same, regardless =
of their=20
name.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>* Shelf life limited.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>* Affected by the shop =
environment</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Dave Fish</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>Stephen =
Gregory</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, January 16, =
2002 11:11=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] LPI =
Soldermask=20
  discoloration...Picture is up.</DIV>
  <DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Hi Dave! =
<BR><BR>Yep=20
  sure does, the spots are around where the jumper wires are routed. The =

  operators who performed the jumper wires said that the spots appeared =
under=20
  where they had applied the kapton tape before they did any =
bonding...and I did=20
  just confirm that, there are a couple of boards still WIP that have =
the wires=20
  attached, the kapton tape still on the wires, and no tak-pak has been =
done.=20
  Sure enough, there are spots on the mask. What's even more confusing =
is that=20
  the spots don't appear under every place that there's kapton =
tape...it's just=20
  random places?!?! <BR><BR>The mask seems to be perfectly intact, I did =
a tape=20
  test on the areas...no problems. <BR>the thickness is fine, and the =
surface of=20
  the mask is as smooth as the rest of the board...it's just discolored =
in those=20
  certain areas. There's only a few boards out of the 20 that we built =
that have=20
  this problem, and they were all processed exactly the same. =
<BR><BR>Really=20
  baffled by this one... <BR><BR>-Steve Gregory- <BR><BR><BR><BR>Seems =
to be a=20
  sharp correlation between the spots on the mask and the "goop" holding =
the=20
  jumper wire in place, eh? <BR><BR>Dave Fish=20
<BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>

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Date:         Wed, 16 Jan 2002 16:26:29 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jon Moore <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
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One good way to optimize your profile for several different boards and still
guarantee that they all will be in spec is to use the new Slim KIC 2000 and
dits software.  It does a great job of exactly that type of application.

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Date:         Wed, 16 Jan 2002 16:42:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guy Ramsey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         [log in to unmask]
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No, I understood you. Some boards will do this. Sometimes they crown instead
of sag. I have not studied why. But increasing the size of the area subject
to preheat may help. In a worst case scenario you may have to reflow the
entire board in an oven.

Sometimes, as the MoonMan mentions, the BGAs like to curl up on the corners
or down on the corners as well. This is do to CTE mismatches in the package
itself. Then you just have to slow the process down and use as low a topside
heat as you can.

An old axiom worth remembering, when in doubt go low and slow. I give credit
to an old mentor, Ken Lindsey, for this rule. Hope he is doing well.

Guy Ramsey



> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
> Sent: Wednesday, January 16, 2002 2:41 PM
> To: [log in to unmask]
> Subject: Re: [TN] BGA/Vias
>
>
> I probably didn't make myself clear. The problem is the board itself
> collapses/sinks/"potato chips"...in the area being heated, i.e. BGA
> location.
> Rick
>
>

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Date:         Wed, 16 Jan 2002 16:52:41 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: VIA in pad
X-To:         Ted Tontis <[log in to unmask]>
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Ted

Check the Technet Archives.  There's been ample discussion on the topic
there.  Further, Jim Blankenhorne published an article on the topic in
"Printed Circuit Design" 10/98.

Dave Fish
----- Original Message -----
From: "Ted Tontis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 15, 2002 10:28 AM
Subject: [TN] VIA in pad


>         We are working on a new design that might be a candidate for HDI.
I
> have never had the opportunity to do such a design, but have read plenty
of
> articles regarding this approach. The main concern is that the engineers
> want to place a  8-10 mil VIA's in the pads. I have explained to them that
> this will cause soldering problems not mention contamination problems.
What
> is the cost benefit over laser drilled micro VIA's vs. conductive epoxy
> filled vias in pads. Can a VIA survive the reflow and still be defect
free?
> Are there other concerns that I should be addressing besides the above
> mentioned. Your input is greatly appreciated.
>
> Regards,
>
> Ted Tontis C.I.D.
> Engage Networks
> 316 N. Milwaukee Street
> Suite 214
> Milwaukee WI, 53202
> PH 414-273-7600 ext. 7607
> FX 414-273-7601
>
> --------------------------------------------------------------------------
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Date:         Wed, 16 Jan 2002 17:17:09 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kevin Strel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kevin Strel <[log in to unmask]>
Subject:      Re: What is the going price companies buy your tugnsten carbide
              scrap?

To reply to this old message,

We can buy old PCB drill and router bits (Stainless or Carbide).  They can
be completely used up, and totally unusable for boards, but they do need to
be mostly unbroken.

I think we're the only ones buying old stainless drills.

Thank you
Kevin Strel

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Date:         Wed, 16 Jan 2002 15:45:10 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
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From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: Al Electrolytic Capacitors leaking
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hi,

definitely sounds like a job for hand soldering after mass reflow.  oh, and definitely, these parts are prone to failure at high temperature.  isn't everything?

phil

-----Original Message-----
From: Howard Watson [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 12:28 PM
To: [log in to unmask]
Subject: [TN] Al Electrolytic Capacitors leaking



Technetters,

Please help!  I have some Aluminum Electrolytic Capacitors that are leaking fluid on the top of the can after reflow.  My peak temperature on the top of the can is 218C, with a time above 183 at 53 seconds, which seem to be appropriate.  The manufacturer recommends the time above 200C to be 20 seconds maximum, which is too little on these boards to get good solder on all the components.  The boards are reflowed in a Vitronics 10 zone convection oven.  The part is Nichicon #2309369R25.  Is anyone familiar with this type of problem, and if so any suggestions will be greatly appreciated!   Are these type of parts prone to failure at high temperatures?

Howard Watson
Manufacturing Engineer
AMETEK/Dixson


------_=_NextPart_001_01C19EE7.D5FC72D0
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<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=044174223-16012002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=044174223-16012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=044174223-16012002><FONT face=Arial color=#0000ff
size=2>definitely sounds like a job for hand soldering after mass reflow.&nbsp;
oh, and definitely, these parts are prone to failure at high temperature.&nbsp;
isn't everything?</FONT></SPAN></DIV>
<DIV><SPAN class=044174223-16012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=044174223-16012002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Howard Watson
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, January 16, 2002
  12:28 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Al Electrolytic
  Capacitors leaking<BR><BR></FONT></DIV><BR><FONT face=sans-serif
  size=2>Technetters,</FONT> <BR><BR><FONT face=sans-serif size=2>Please help!
  &nbsp;I have some Aluminum Electrolytic Capacitors that are leaking fluid on
  the top of the can after reflow. &nbsp;My peak temperature on the top of the
  can is 218C, with a time above 183 at 53 seconds, which seem to be
  appropriate. &nbsp;The manufacturer recommends the time above 200C to be 20
  seconds maximum, which is too little on these boards to get good solder on all
  the components. &nbsp;The boards are reflowed in a Vitronics 10 zone
  convection oven. &nbsp;The part is Nichicon #2309369R25. &nbsp;Is anyone
  familiar with this type of problem, and if so any suggestions will be greatly
  appreciated! &nbsp; Are these type of parts prone to failure at high
  temperatures?</FONT> <BR><BR><FONT face=sans-serif size=2>Howard
  Watson<BR>Manufacturing
Engineer<BR>AMETEK/Dixson</FONT></BLOCKQUOTE></BODY></HTML>

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Date:         Wed, 16 Jan 2002 17:27:20 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
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Werner,

As a follow up, here is a paragraph from "2001-08-06_ARP 5890 - DRAFT2" from the SAE.
This document has been proposed by the IEC as a replacement for Hdbk-217F. In their version
this paragraph was deleted. I do have an electronic copy of the SAE document.

BTW this SAE document is intended for electronic equipment attached to aircraft engines!


Reliability assessment results should be viewed as objective evidence
that the product reliability requirements, goals, or expectations will
be satisfied.  As such, they may used, for example, to authorize
advancement to the next step in product development, or to authorize
progress payments, or to proceed with delivery and acceptance of
products.  Reliability assessment results should never be used to
support a claim that the reliability requirements, goals, or
expectations have been satisfied, in the face of clear evidence to the
contrary from in-service experience.

David A. Douthit
Manager
LoCan LLC



Werner Engelmaier wrote:

> Hi MoonMan,
> One of the reasons why they let MIL-HDBK-217 die is that it contains too many
> technically false assumptions. The F-revision was an attempt to fix this to
> some degree, but a square peg just does not fit properly into a round
> hole--so to speak. MIL-HDBK-217 is based solely on statistical data--many of
> them flawed--and ignores the physical damage mechanisms [physics-of-failure]
> at work.
> And no, there is/are not "concise" IPC counterparts or a combination of
> several documents, nor should there be.
>
> Werner
>
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--------------09E81A54968336C0ECF88E90
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Werner,
<p>As a follow up, here is a paragraph from "2001-08-06_ARP 5890 - DRAFT2"
from the SAE.
<br>This document has been proposed by the IEC as a replacement for Hdbk-217F.
In their version
<br>this paragraph was deleted. I do have an electronic copy of the SAE
document.
<p>BTW this SAE document is intended for electronic equipment attached
to aircraft engines!
<br>&nbsp;
<p><i>Reliability assessment results should be viewed as objective evidence</i>
<br><i>that the product reliability requirements, goals, or expectations
will</i>
<br><i>be satisfied.&nbsp; As such, they may used, for example, to authorize</i>
<br><i>advancement to the next step in product development, or to authorize</i>
<br><i>progress payments, or to proceed with delivery and acceptance of</i>
<br><i>products.&nbsp; Reliability assessment results should never be used
to</i>
<br><i>support a claim that the reliability requirements, goals, or</i>
<br><i>expectations have been satisfied, in the face of clear evidence
to the</i>
<br><i>contrary from in-service experience.</i><i></i>
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<br><i></i>&nbsp;
<br>&nbsp;
<p>Werner Engelmaier wrote:
<blockquote TYPE=CITE>Hi MoonMan,
<br>One of the reasons why they let MIL-HDBK-217 die is that it contains
too many
<br>technically false assumptions. The F-revision was an attempt to fix
this to
<br>some degree, but a square peg just does not fit properly into a round
<br>hole--so to speak. MIL-HDBK-217 is based solely on statistical data--many
of
<br>them flawed--and ignores the physical damage mechanisms [physics-of-failure]
<br>at work.
<br>And no, there is/are not "concise" IPC counterparts or a combination
of
<br>several documents, nor should there be.
<p>Werner
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Date:         Wed, 16 Jan 2002 18:23:18 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
              x-mac-creator="4D4F5353"
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Earl,

A large part of the problem is the use of MTBF. It does not reflect
real world reliability issues.The primary problem is that it does not
cover intermittent/soft failures. In other words when does a "failure" occur?

Documenting any and all anomalies is required to get a clearer picture.

David A. Douthit
Manager
LoCan LLC

Earl Moon wrote:

> Werner and Dave,
>
> Thanks for the input. The froth I'm not yet displaying concerns how the DoD
> folks keep asking for compliance with the standard/spec. There are some
> still asking for use of statistical methods, FMEA processes, and use of 217.
> What's with this? Also, though not asking Werner to give up any secrets
> about his reliability consultancy, what are we "civilians" using as
> prediction methods/standards? I know some, but seems a target rich
> environment beyond past histories, especially concerning "breakthrough"
> technologies, let alone evolutionary types.
>
> All the disk drive manufacturers, as but one minor example, state a MTBF
> number usually around 300,000 hours or more. I've been involved with them
> from a DFM standpoint and some simply have "great" warranty/exchange
> programs. Hope my latest Maxtors hold up for another 300 hours. Sure hope
> "old Jim M's" stuff flies well, as well, oh well.
>
> Reminds me of a Waylon song with verse as my front tracks are headed for a
> cold water well and my back tracks are covered with snow. Willie was part of
> this as well. What comes around?
>
> MoonMan
>
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=========================================================================
Date:         Wed, 16 Jan 2002 20:26:28 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Nickel Plating Snarl
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_001C_01C19ECC.1426F920"

This is a multi-part message in MIME format.

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        charset="iso-8859-1"
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Nickel Plating SnarlSupporting David's comment ...

Electrolytic nickel: Typical hardness range of 28 Rockwell C.

High [10-12%] phosphorous electroless nickel: Typical hardness range of =
as deposited, 48 to 50 Rockwell C with heat treatment, hardenable to =
over 68 Rockwell C. =20

Medium [6-9%] phosphorous electroless nickel: can be hardened from 45 =
Rockwell C to as high as 68 Rockwell C scale with heat treatment.

Low [1-3%] phosphorous electroless nickel (Hard Nickel): Typically has =
an after plating range from 58-62 on the Rockwell C scale, heat =
treatable to 70 Rockwell C. =20

Dave Fish
  ----- Original Message -----=20
  From: David Ricketts=20
  To: [log in to unmask]
  Sent: Tuesday, January 15, 2002 11:27 AM
  Subject: Re: [TN] Nickel Plating Snarl


  Electroless plating is soft. Electrolytic plating is hard. You may =
want to investigate carbon ink as a cost effective alternative.
  David Ricketts

  Pertek Engineering
  Voice: 949-475-4485
  Fax:   949-475-4493=20

  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Neel, Robert
  Sent: Tuesday, January 15, 2002 10:17 AM
  To: [log in to unmask]
  Subject: [TN] Nickel Plating Snarl
  =20

   Folks,=20

  Can someone explain to me why all my PCB houses are suddenly having =
"spectacular cows" over this pcb plating spec:=20

  "CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 MILLIONTHS THICK, =
MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ 100 GRAMS"

  This pcb is the substrate for some snap-acting domes and I need a hard =
and conductive bearing surface for the dome feet.  The plating spec =
comes from the dome manufacturer.

  Is it the "electroless"?  Is it the thickness? Is it the hardness =
requirement? Is it the "nickel" vs "nickle"?  (Funny thing is, though, =
everyone is very happy to do gold rather than nickel.)

  What gives?=20

  Robert=20


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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Nickel Plating Snarl</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Supporting David's comment =
...</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Electrolytic nickel: Typical hardness =
range of 28=20
Rockwell C.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>High [10-12%] phosphorous electroless =
nickel:=20
Typical hardness range of as deposited, 48 to 50 Rockwell C with heat =
treatment,=20
hardenable to over 68 Rockwell C.&nbsp; </FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Medium [6-9%] phosphorous electroless =
nickel: can=20
be hardened from 45 Rockwell C to as high as 68 Rockwell C scale with =
heat=20
treatment.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Low [1-3%] phosphorous electroless =
nickel (Hard=20
Nickel): Typically has an after plating range from 58-62 on the Rockwell =
C=20
scale, heat treatable to 70 Rockwell C.&nbsp; <BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Dave Fish</DIV></FONT>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>David Ricketts</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, January 15, 2002 =
11:27=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Nickel =
Plating=20
  Snarl</DIV>
  <DIV><BR></DIV>
  <DIV><SPAN class=3D520441219-15012002>Electroless plating is soft. =
Electrolytic=20
  plating is hard. You may want to investigate carbon ink as a cost =
effective=20
  alternative.</SPAN></DIV>
  <P>David Ricketts<BR><BR>Pertek Engineering<BR>Voice:=20
  949-475-4485<BR>Fax:&nbsp;&nbsp; 949-475-4493 </P>
  <P><FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B> TechNet=20
  [<A href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<B>On =
Behalf Of=20
  </B>Neel, Robert<BR><B>Sent:</B> Tuesday, January 15, 2002 10:17=20
  AM<BR><B>To:</B> <A=20
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><B>Subject:</B> =
[TN]=20
  Nickel Plating Snarl<BR></FONT><FONT size=3D2><SPAN=20
  class=3D520441219-15012002><FONT =
size=3D3>&nbsp;</FONT></SPAN></FONT></P>
  <P><FONT size=3D2><SPAN =
class=3D520441219-15012002>&nbsp;</SPAN>Folks,</FONT> </P>
  <P><FONT size=3D2>Can someone explain to me why all my PCB houses are =
suddenly=20
  having "spectacular cows" over this pcb plating spec:</FONT> </P>
  <P><FONT size=3D2>"CONTACT PATTERN FINISH IS ELECTROLESS NICKEL, 50 =
MILLIONTHS=20
  THICK, MINIMUM 40 ROCKWELL C HARDNESS, MEASURED WITH KNOOP PROCESS @ =
100=20
  GRAMS"</FONT></P>
  <P><FONT size=3D2>This pcb is the substrate for some snap-acting domes =
and I=20
  need a hard and conductive bearing surface for the dome feet.&nbsp; =
The=20
  plating spec comes from the dome manufacturer.</FONT></P>
  <P><FONT size=3D2>Is it the "electroless"?&nbsp; Is it the thickness? =
Is it the=20
  hardness requirement? Is it the "nickel" vs "nickle"?&nbsp; (Funny =
thing is,=20
  though, everyone is very happy to do gold rather than =
nickel.)</FONT></P>
  <P><FONT size=3D2>What gives?</FONT> </P>
  <P><FONT size=3D2>Robert</FONT> </P></BLOCKQUOTE></BODY></HTML>

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Date:         Wed, 16 Jan 2002 19:23:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Taylor <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Taylor <[log in to unmask]>
Subject:      Track resistance Calculator
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I've seen a number of people asking for a track resistance calculator. I'm
delighted to say that, responsive to your needs, as ever . . .  Polar
Instruments has produced a free, no strings track resistance calculator
which you can download from www.polarinstruments.com beginning today.


We'd like you to you tell us who you are, but don't demand it.
We'd also like you to browse our site and take a look at our application
notes and products for PCB test and controlled impedance design and
measurement. Again, you don't have to.
We'd love to receive your comments and suggestions on any aspect of our work.
Enjoy the calculator, I hope it makes work easier for everyone.

Cheers, Ken

Ken Taylor
Polar Instruments, Portland, OR

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Date:         Thu, 17 Jan 2002 09:31:46 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Aqueous cleaning of surface mount potentiometers
X-To:         Paul Truit <[log in to unmask]>
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Paul

There are two questions to consider here:
1. the quality of the components (it is not unknown for unsealed
components to be supplied, in place of sealed ones -- with all due
respect, purchasing guys are often unaware of the difference and they
see that there are physically identical units available at 5 cents less,
each. This is a constant problem with pots and, if the supplier
guarantees that they are designed to withstand cleaning, then it must be
taken up with him. If he doesn't, then change the supplier.)
2. the cleaning process (it is useful to know that it is better to have
each stage about 5°C hotter than the previous one, to create an
environment where the air in the component expands throughout the
process. It has been found that a very small drop in temperature can
sometimes contract the air sufficiently that water is drawn in, past the
O-ring. Also, make sure that wash chemicals, such as saponifiers, are
compatible with the O-ring material.)

Brian

Paul Truit wrote:
>
> I wanted to hear how fellow Technet people are processing surface mount
> potentiometers.
>
> I have experienced some field failures recently in this area.  Water has
> leaked into a "Sealed" potentiometer.  When power is applied an
> alternate circuit grows inside the pot causing the part to fail.
>
> We are processing this part using an OA solder paste through a normal
> pick and place operation.  Reflow profile takes this through a normal
> reflow curve Max. Peak temperature of 195-205 degrees C with a Ramp rate
> of 2-2.5 Degrees C.  We then add on a few through hole parts through
> progressive assembly then  wave solder and clean the assembly.
>
> We are utilizing an Electrovert Aquastorm 100.  We process the boards
> through at 4 feet per minute.  Water temperature is 145 degrees F.
>
> We have been cleaning boards (and potentiometers) for over eight years
> with never a problem.  This one has sure surprised me.  Just wondering
> if anyone else has had any experience with this and what they have done
> to fix this other than hand soldering the pot on in final.
>
> --
> Paul Truit, Mfg. Eng.
> RBB Systems, Inc.
> 4265C E. Lincolnway
> Wooster, OH  44691
> Ph. (330) 567-2906 ext 514
> Fax (330) 263-5324
> Email: [log in to unmask]
>
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Date:         Thu, 17 Jan 2002 10:48:23 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "d. terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
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Hi Stacy,

Assuming you have a modern full forced convection oven, with your maximum =
boardthickness of 1.27 mm you should be able to work with one ovensetting. =
Start with an average setting for your oven, and measure the temperature =
on the heaviest component of your heaviest board, and on the base material =
of your lightest board.  If the temperature difference between these two =
extremes is less than 30 degrees Celcius than it is very likely that you =
can do everything with one profile.
Then tweak the ovensettings until you reach at least 200 degrees on the =
heavy board, and check on the light board that the temperature doesn't =
exceed 230 or 235 degrees. Now this becomes your new profile....
Of course there several other things you have to think about when setting =
up a profile, check the literature  (with the technical-articles search-eng=
ine on my webpage http://www.smtinfo.net/smtlinks.html you should be able =
to track some good webpages about this).
For every new board you have to decide if the design fits between the =
heavy and the light board that you used during setting up the recipe. You =
can do this by measurements, but after some time you'll be able to predict =
the results.
One final remark: pay some extra attention to the BGA's, if there's any on =
your boards.=20

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

>>> My Nguyen <[log in to unmask]> 01/16 7:17 pm >>>
Good morning Techneters,

I am working on oven profiler consolidation project.
Currently, we have 540 Product Profile for each oven.
For 13 oven machine, we have 7020 profiles.  That is
way too many for a memory manufacture!

We currently use water-soluble solder and no clean
solder.  We know that for each product, the pre-heat
zone, soak-zone, re-flow zone, and temperature could
be a bit different from one Solder Paste Manufacture
to other, or from one Solder Paste type to others, or
even from single side, to double side.

HOWEVER, for memory, the width, length, thickness, and
number of ICs, resisters, capacitors, and others are
limited to a certain number, i.e, PCB height is less
than 1.7 inches; PCB thickness is equal or less than
0.05 inch; PCB length follow the spec. of 5.25=F6 for
DIMM, DDR, RIMM, 2.66=F6 for SODIMM, 4.25=F6 for 72 Pin
SIMM, etc.

I have heard that out there, there is a way to reduce
from 1000s down to 10-100 oven profiles based on
Mass/Density.  And of course, there are many other
scientific ways that I have not heard of.  Please help
me! What would be the best method you recommend or you
have successfully tried to reduce the number of oven
profiles down to a control/reasonable numbers?

Your advice and suggestion are greatly appreciated.

Stacy


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Date:         Thu, 17 Jan 2002 06:01:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         "David A. Douthit" <[log in to unmask]>

David,

Thanks and I do understand. More for marketing reasons, and few other terms
to express predicted reliability, OEM's use MTBF. It's a term/acronym best
understood by the "ordinary" buyers - not at all like you and me.

Earl

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Date:         Thu, 17 Jan 2002 06:18:53 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OLD TIME MIL STD FOLKS ONLY, OR NOT
X-To:         "David A. Douthit" <[log in to unmask]>

David,

I find your post of great interest for several reasons. One is Werner's
accurate comment about physics of failure rings true and loud.

In this post, I find concern, again in light of Werner's other partucular
comment about "nor should there be" as it references predicting reliability
based on a replacement for 217. Hope I got that right.

Though some very significant/large military subs still rely on a document
obololeted over 5 years ago. I mention this because I have been contacted,
again, and many times before concerning using this type material with
"advanced" software packages in an attempt to predict reliability of
whatever device or system.

Not long ago, I worked on a contract wherein I set out to not only do
thermal analysis of an R/F system - from the component level out to the
housing cooling fins. I approached the task from a finite element analysys
standpoint determining what got hot, and how hot, as well as using
engineering principles to effect increased thermal efficiency. The short of
a very long story.

At the same time, management had hired an outside "predictability"
consultant, not to my knowledge by interesting non the less later, using an
"advanced" thermal software modeling package.

Again, to make the story short, I got the job done and the software based
folks came in way out in left field.

I'm not saying I was better, though I got the required results with a design
that worked. I'm saying there may be very good predictability capabilities
out there, but I haven't seen one work as well as HARD WORK.

This brings me to your posting and 217's replacement, or conversion. While I
have no problem with attempting to do considerable "up-front" through DFM/CE
(I think I've expressed this before) while using all possible USEFUL tools
and documentation, I am a reliability persone based on evolutionary, PROVEN
technology. I'm not dispariging those seeking breakthrough as do R&D folks.
It's just that I do most of my work relying on already proven technology and
the data to support its reliability. Of course, I also get the opportunity
to derive that data from experminents and F/A

Earl

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Date:         Thu, 17 Jan 2002 09:18:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Kevin M. Bair" <[log in to unmask]>
Subject:      D-Pak 2nd side reflow issues
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

We are having problems with bottom side d-paks falling off when the top
side of the board is being reflowed.  Has anyone had this problem, and if
so, what have you done to correct it?

Thanks for your help,

Kevin Bair
Assembly Engineer
Teradyne, Inc.

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Date:         Thu, 17 Jan 2002 09:50:00 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Charlie Pitarys <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Charlie Pitarys <[log in to unmask]>
Subject:      Scrap solder paste
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Hello,
I have accumulated a lot of solder paste from past cleaning evaluations. I
wonder if anybody knows of someone in the Northeast that will retrieve this
old paste for scrap value, recycling, etc. versus hauling away as a Haz
waste?

Thank you,

Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com <http://www.kyzen.com/>







------_=_NextPart_001_01C19F66.3D69A9A0
Content-Type: text/html;
        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT face="MS Serif"><SPAN
class=020004514-17012002>Hello,</SPAN></FONT></DIV>
<DIV><FONT face="MS Serif"><SPAN class=020004514-17012002>I have accumulated a
lot of solder paste from past cleaning evaluations. I wonder if anybody knows of
someone in the Northeast that will retrieve this old paste for scrap value,
recycling, etc. versus hauling away as a Haz waste?</SPAN></FONT></DIV>
<DIV><FONT face="MS Serif"><SPAN
class=020004514-17012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="MS Serif"><SPAN class=020004514-17012002>Thank
you,</SPAN></FONT></DIV>
<P><FONT size=2>Charlie Pitarys<BR>Director of Application
Technologies<BR>603.622.2900 X-115<BR><A
href="http://www.kyzen.com/">www.kyzen.com</A> </FONT></P><FONT size=2>
<P>&nbsp;</P></FONT>
<P>&nbsp;</P>
<DIV>&nbsp;</DIV></BODY></HTML>

------_=_NextPart_001_01C19F66.3D69A9A0--

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Date:         Thu, 17 Jan 2002 10:07:17 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: Scrap solder paste
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              boundary="----_=_NextPart_001_01C19F68.A762059E"

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I have a similar issue with left over RA core solder that we no longer =
use due to a switch over to OA flux core solder.  The manufacturer will =
"buy it back for about $0.10 on the dollar".  Wow, big deal!  Many of =
the rolls of solder are still in the original package, unused.
=20
Phil Nutting
Kaiser Systems, Inc.

-----Original Message-----
From: Charlie Pitarys [mailto:[log in to unmask]]
Sent: Thursday, January 17, 2002 9:50 AM
To: [log in to unmask]
Subject: [TN] Scrap solder paste


Hello,
I have accumulated a lot of solder paste from past cleaning evaluations. =
I wonder if anybody knows of someone in the Northeast that will retrieve =
this old paste for scrap value, recycling, etc. versus hauling away as a =
Haz waste?
=20
Thank you,

Charlie Pitarys
Director of Application Technologies
603.622.2900 X-115
www.kyzen.com <http://www.kyzen.com/> =20

=20

=20

=20


------_=_NextPart_001_01C19F68.A762059E
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">


<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D988550415-17012002><FONT face=3DArial color=3D#0000ff =
size=3D2>I have=20
a similar issue with left over RA core solder that we no longer use due =
to a=20
switch over to OA flux core solder.&nbsp; The manufacturer will "buy it =
back for=20
about $0.10 on the dollar".&nbsp; Wow, big deal!&nbsp; Many of the rolls =
of=20
solder are still in the original package, unused.</FONT></SPAN></DIV>
<DIV><SPAN class=3D988550415-17012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D988550415-17012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Phil=20
Nutting</FONT></SPAN></DIV>
<DIV><SPAN class=3D988550415-17012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Kaiser=20
Systems, Inc.</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> Charlie Pitarys=20
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, January =
17, 2002=20
  9:50 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Scrap =
solder=20
  paste<BR><BR></FONT></DIV>
  <DIV><FONT face=3D"MS Serif"><SPAN=20
  class=3D020004514-17012002>Hello,</SPAN></FONT></DIV>
  <DIV><FONT face=3D"MS Serif"><SPAN class=3D020004514-17012002>I have =
accumulated a=20
  lot of solder paste from past cleaning evaluations. I wonder if =
anybody knows=20
  of someone in the Northeast that will retrieve this old paste for =
scrap value,=20
  recycling, etc. versus hauling away as a Haz =
waste?</SPAN></FONT></DIV>
  <DIV><FONT face=3D"MS Serif"><SPAN=20
  class=3D020004514-17012002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT face=3D"MS Serif"><SPAN class=3D020004514-17012002>Thank=20
  you,</SPAN></FONT></DIV>
  <P><FONT size=3D2>Charlie Pitarys<BR>Director of Application=20
  Technologies<BR>603.622.2900 X-115<BR><A=20
  href=3D"http://www.kyzen.com/">www.kyzen.com</A> </FONT></P><FONT =
size=3D2>
  <P>&nbsp;</P></FONT>
  <P>&nbsp;</P>
  <DIV>&nbsp;</DIV></BLOCKQUOTE></BODY></HTML>

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Date:         Thu, 17 Jan 2002 10:09:14 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Howard Watson <[log in to unmask]>
Subject:      Re: Al Electrolytic Capacitors leaking
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Thanks Phil.  I am wondering if the 218C is too high of a peak temperature
for these type of components.  We use a lot of them, so hand soldering is
not a popular recommendation here.  Can they get damaged without any
visible defect?  I have isolated the problem to a specific lot, but then
maybe it will show up again in the future.

Howard Watson
Manufacturing Engineer
AMETEK/Dixson




"Crepeau, Phil" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
01/16/02 04:45 PM
Please respond to "TechNet E-Mail Forum."; Please respond to "Crepeau,
Phil"


        To:     [log in to unmask]
        cc:
        Subject:        Re: [TN] Al Electrolytic Capacitors leaking


hi,

definitely sounds like a job for hand soldering after mass reflow.  oh,
and definitely, these parts are prone to failure at high temperature.
isn't everything?

phil
-----Original Message-----
From: Howard Watson [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 12:28 PM
To: [log in to unmask]
Subject: [TN] Al Electrolytic Capacitors leaking


Technetters,

Please help!  I have some Aluminum Electrolytic Capacitors that are
leaking fluid on the top of the can after reflow.  My peak temperature on
the top of the can is 218C, with a time above 183 at 53 seconds, which
seem to be appropriate.  The manufacturer recommends the time above 200C
to be 20 seconds maximum, which is too little on these boards to get good
solder on all the components.  The boards are reflowed in a Vitronics 10
zone convection oven.  The part is Nichicon #2309369R25.  Is anyone
familiar with this type of problem, and if so any suggestions will be
greatly appreciated!   Are these type of parts prone to failure at high
temperatures?

Howard Watson
Manufacturing Engineer
AMETEK/Dixson


--=_alternative 0053262B87256B44_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Thanks Phil. &nbsp;I am wondering if the 218C is too high of a peak temperature for these type of components. &nbsp;We use a lot of them, so hand soldering is not a popular recommendation here. &nbsp;Can they get damaged without any visible defect? &nbsp;I have isolated the problem to a specific lot, but then maybe it will show up again in the future. &nbsp;</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>&quot;Crepeau, Phil&quot; &lt;[log in to unmask]&gt;</b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet &lt;[log in to unmask]&gt;</font>
<p><font size=1 face="sans-serif">01/16/02 04:45 PM</font>
<br><font size=1 face="sans-serif">Please respond to &quot;TechNet E-Mail Forum.&quot;; Please respond to &quot;Crepeau, Phil&quot;</font>
<br>
<td><font size=1 face="Arial">&nbsp; &nbsp; &nbsp; &nbsp; </font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; To: &nbsp; &nbsp; &nbsp; &nbsp;[log in to unmask]</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; cc: &nbsp; &nbsp; &nbsp; &nbsp;</font>
<br><font size=1 face="sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Subject: &nbsp; &nbsp; &nbsp; &nbsp;Re: [TN] Al Electrolytic Capacitors leaking</font></table>
<br>
<br>
<br><font size=2 color=blue face="Arial">hi,</font>
<br><font size=3 face="Times New Roman">&nbsp;</font>
<br><font size=2 color=blue face="Arial">definitely sounds like a job for hand soldering after mass reflow. &nbsp;oh, and definitely, these parts are prone to failure at high temperature. &nbsp;isn't everything?</font>
<br><font size=3 face="Times New Roman">&nbsp;</font>
<br><font size=2 color=blue face="Arial">phil</font>
<br><font size=2 face="Tahoma">-----Original Message-----<b><br>
From:</b> Howard Watson [mailto:[log in to unmask]]<b><br>
Sent:</b> Wednesday, January 16, 2002 12:28 PM<b><br>
To:</b> [log in to unmask]<b><br>
Subject:</b> [TN] Al Electrolytic Capacitors leaking<br>
</font>
<br><font size=2 face="sans-serif"><br>
Technetters,</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
Please help! &nbsp;I have some Aluminum Electrolytic Capacitors that are leaking fluid on the top of the can after reflow. &nbsp;My peak temperature on the top of the can is 218C, with a time above 183 at 53 seconds, which seem to be appropriate. &nbsp;The manufacturer recommends the time above 200C to be 20 seconds maximum, which is too little on these boards to get good solder on all the components. &nbsp;The boards are reflowed in a Vitronics 10 zone convection oven. &nbsp;The part is Nichicon #2309369R25. &nbsp;Is anyone familiar with this type of problem, and if so any suggestions will be greatly appreciated! &nbsp; Are these type of parts prone to failure at high temperatures?</font><font size=3 face="Times New Roman"> <br>
</font><font size=2 face="sans-serif"><br>
Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
--=_alternative 0053262B87256B44_=--

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Date:         Thu, 17 Jan 2002 09:27:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Aqueous cleaning of surface mount potentiometers
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Is the wash a spray over spray?  I had a problem similar and we found the =
spray over spray pressures were the cause but when we used a spray over =
immersion the problem went away. =20

Kathy=20

--=_6A371D95.D2B3DEE4
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style="MARGIN-TOP: 2px; FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px">
<DIV>Is the wash a spray over spray?&nbsp; I had a problem similar and we found
the spray over spray pressures were the cause but when we used a spray over
immersion the problem went away.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

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Date:         Thu, 17 Jan 2002 11:04:55 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: BGA/Vias
MIME-Version: 1.0
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Hi Rick,
You are still not clear. When you say "sink" do you mean the resin between
the PTHs relative to thr PTHs? If yes, the explanation is that on heating the
resin expands--primarily in the z-direction--causing palstic deformation by
stretching of the copper barrels as well dishing of the PTH pads. On cooling
the resin contracts to its initial volume, but the PYHs are plastically
deformed, thus giving the appearance of the PCB "sinking" around the P:THs.
I hope this helps.

Werner Engelmaier

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Date:         Thu, 17 Jan 2002 11:04:57 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Way too many Product Oven Profiles
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi Stacy,
First, get your self a copy of IPC-7530 "Guidelines for Temperature Profilin=
g=20
for Mass Soldering Processes (Reflow & Wave)."
Second, part of your problem is the sloppy language that is being used in ou=
r=20
industry.
What you are referring to as "reflow profiles" are actually "oven recipes."=20=
A=20
given 'oven recipe' on a given machine will result in many differrent 'reflo=
w=20
profiles' at the solder joints of components with different thermal masses=20
and construction. You definitely want to have a 'reflow profile' for each=20
assembly code based on the component in the assembly with the solder joints=20
heating up the slowest. To achieve this 'reflow profile' for a code may=20
require a different 'oven recipes' for each of your reflow ovens--you will=20
know this only after monitoring the 'profiles' resulting from a given=20
'recipe' for these diffent codes.
Third, the number of your 'recipes' sure does sound excessive.=20
Fourth, "above 183: 40-80 sec" is irrelevant. You need to be at least about=20=
5=20
seconds above (Liquidus for you solder + 25=B0C) [that is 208=B0C for eutect=
ic=20
Sn/Pb] for any solder joint in your assembly to assure proper wetting on a=20
consistent basis.=20
Fifth, remember, the object of the whole excercise is to make sure ALL solde=
r=20
joints in an assembly receive adequate heat during reflow.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com=20

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Date:         Thu, 17 Jan 2002 11:43:23 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Truit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Truit <[log in to unmask]>
Organization: RBB Systems Inc.
Subject:      Re: Aqueous cleaning of surface mount potentiometers
X-To:         Kathy Kuhlow <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Kathy

We have the The Hurricane Jet option from Electrovert that
 "produces a coherent sheet of high-pressure water across the entire
width of the conveyor belt." According to their literature.

What I have found so far is the manufacturer of the "sealed"
potentiometer recommends that we turn down the water pressure to less
than 60 PSI.  We had been running at around 80 PSI.

I am not familiar with the "Spray over Spray" term.  Can you define
this?

Did you turn down your pressure setting for any project or do you set
the pressure settings if the project has potentiometers on it and then
turn it back up?

Thanks for your response.

Paul
--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH  44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]

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Date:         Thu, 17 Jan 2002 12:36:49 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Scrap solder paste
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              boundary="part1_194.137e4d0.297865b1_boundary"

--part1_194.137e4d0.297865b1_boundary
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Hi Charlie,

Go to:

http://www.ipc.org/html/RECYCLE1.htm

AIM Inc. in Rhode Island takes scrap paste, and Bow Electronic Solders in New
Jersey does as well...

-Steve Gregory-


> Hello,
> I have accumulated a lot of solder paste from past cleaning evaluations. I
> wonder if anybody knows of someone in the Northeast that will retrieve this
> old paste for scrap value, recycling, etc. versus hauling away as a Haz
> waste?
>
> Thank you,
> Charlie Pitarys
> Director of Application Technologies
> 603.622.2900 X-115
> <A HREF="http://www.kyzen.com/">www.kyzen.com</A>
>



--part1_194.137e4d0.297865b1_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Charlie,
<BR>
<BR>Go to:
<BR>
<BR>http://www.ipc.org/html/RECYCLE1.htm
<BR>
<BR>AIM Inc. in Rhode Island takes scrap paste, and Bow Electronic Solders in New Jersey does as well...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello,
<BR>I have accumulated a lot of solder paste from past cleaning evaluations. I wonder if anybody knows of someone in the Northeast that will retrieve this old paste for scrap value, recycling, etc. versus hauling away as a Haz waste?
<BR>
<BR>Thank you,
<BR>Charlie Pitarys
<BR>Director of Application Technologies
<BR>603.622.2900 X-115
<BR><A HREF="http://www.kyzen.com/">www.kyzen.com</A>
<BR></BLOCKQUOTE>
<BR>
<BR></FONT></HTML>

--part1_194.137e4d0.297865b1_boundary--

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Date:         Thu, 17 Jan 2002 12:45:00 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Tim Devaul <[log in to unmask]>
Subject:      Sign off
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Please remove me from the IPC tech net forum I am leaving my current employer and will ask to be reinstated once I am settled in.

Thanks,

Tim DeVaul
Quality Assurance Training and Audit Supervisor
Philips Broadband Networks, Inc.
100 Fairgrounds Dr.
Manlius, New York 13104
Tel: (315) 682-9105 Ext. 2403
Fax: (315)682-9006
Email: [log in to unmask]

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Date:         Thu, 17 Jan 2002 09:42:13 -0800
Reply-To:     Greg Jones <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Greg Jones <[log in to unmask]>
Subject:      Way too many oven profiles
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My apologies for Phil Kazmierowicz's "commercial" response to this query.
He was responding to the original technet email I had forwarded to our R&D
department and did not realize that his response would be posted.  That
said, his proposed solution is a very efficient one.

Best regards,

Greg Jones Ph.D.
Special Projects Manager
775.322.0158
KIC--Innovation That Works
www.kicthermal.com

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Date:         Thu, 17 Jan 2002 12:45:38 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Becerra Alejandro <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Becerra Alejandro <[log in to unmask]>
Subject:      Thermocouples for SuperMole
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------_=_NextPart_001_01C19F7E.C680F3C0
Content-Type: text/plain;
        charset="iso-8859-1"

Hello to All,
Could you please tell me any vendor for Thermocouples for SuperMole
profiler?

Thanks,

Alejandro Becerra

------_=_NextPart_001_01C19F7E.C680F3C0
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        charset="iso-8859-1"

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<TITLE>Thermocouples for SuperMole</TITLE>
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<P><FONT SIZE=2 FACE="Arial">Hello to All,</FONT>
<BR><FONT SIZE=2 FACE="Arial">Could you please tell me any vendor for Thermocouples for SuperMole profiler?</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial">Thanks,</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial">Alejandro Becerra</FONT>
</P>

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Date:         Thu, 17 Jan 2002 09:51:19 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
MIME-Version: 1.0
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One thing I'd like to warn against is expecting a big increase in thermal
conduction of the hole by filling with CB-100.  Do the math comparing the
thermal conductivity of CB-100 and copper and the relative cross sectional
areas of the two materials.  For a 20 mil drilled hole with 1 mil of copper,
the CB-100 has 4x the cross-sectional area but only increases the heat
transfer by ~4%.  And this assumes the via is 100% filled.  But if you just
double the copper thickness in the barrel you get an almost 100% increase.
If you need the via fill for other reasons, for instance to avoid solder
loss down the barrel, then you should use it.  But for improved heat
conduction, I don't see the value.  We've used the technique of increasing
the copper thickness in thermal vias on many designs, some of which also
have the vias filled.

Just don't take adding the extra plating to the extreme and try to plate
them closed.  I agree with everyone else that's a bad idea.

> ----------
> From:         <Peter George Duncan>[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Sunday, January 13, 2002 4:21 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] VIAS PLATED CLOSED
>
> Hi, James,
>
> Hearing of what you're trying to do, I furrow my brow in anxiety. If
> you're
> plating the entire hole closed, what surface copper weight are you
> expecting as a result, especially with 21 mil diameter holes? My estimate
> is about 8 oz. What trace widths and spacings are involved? If they're
> fairly fine, the undercut from the etching process will probably sever
> them
> from the board, or make them extremely weak. It is possible to grind
> excess
> copper of the board surface, but this is a brutal and risky process as
> well, since if the board isn't dead flat, you can take off traces and pads
> adn go through to the substrate material.
>
>  If it's only the thermal holes you're trying to plate shut, how are you
> going to prevent the other holes in the board from being filled as well
> without a lot of selective masking? Also, I suspect that the holes will
> close at the top and bottom first, leaving a void in the centre that will
> contain plating solutions and cause all kinds of corrosive and expansion
> problems.
>
> This is not a good idea!!! My strong recommendation is that you use silver
> loaded epoxy to fill the thermal via holes prior to final plating. It's
> thermal conductivity is not as good as that of copper, but is relatively a
> lot less hassle and will be a lot cheaper than all that plating. There are
> a number of epoxies  available, though Dupont's CB100 is one that is
> commonly cited. It has a thermal conductivity value of 5.23 W/mK, so is
> pretty good for this type of material. Other makes are similar.
>
> Let us know how it goes. Good luck!!
>
> Peter
>
>
>
>
>                     "Marsico, James"
>                     <James.Marsico@D        To:     [log in to unmask]
>                     P.AIL.COM>              cc:     (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
>                     Sent by: TechNet        Aero/ST Group)
>                     <[log in to unmask]        Subject:     Re: [TN] VIAS
> PLATED CLOSED
>                     >
>
>
>                     01/11/02 08:09
>                     PM
>                     Please respond
>                     to "TechNet
>                     E-Mail Forum."
>
>
>
>
>
>
> Hi, Peter, thanks for the response.
>
> Let me try to explain further.  We're using ceramic leadless chip carriers
> which give off a lot of heat.  In an effort to dissipate the heat to the
> ground planes, we're placing thermal vias underneath.  We wanted the
> thermal
> vias to be plated closed, resulting in a solid plug of copper, which we
> then
> can deposit solder paste on top which would contact the bottom of the
> ceramic package.  The heat path would be from the component through the
> solder bumps on the thermal vias through the solid copper via.  Our board
> supplier claims that he can plate the vias closed, but when I asked about
> voids and entrapped plating chemicals, he said he was never asked that
> before and would have to look into it.  I'm getting concerned with this
> design, thinking that an epoxy-filled via which is plated over on top
> would
> be better.  I now need recommendations for a THERMALLY conductive
> adhesive,
> it doesn't have to be electrically conductive but I don't really care.
>
> Thanks again,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>         -----Original Message-----
>         From:   <Peter George Duncan> [SMTP:[log in to unmask]]
>         Sent:   Thursday, January 10, 2002 9:28 PM
>         To:     [log in to unmask]
>         Subject:        Re: [TN] VIAS PLATED CLOSED
>
>         Hi, James,
>
>         I'm trying to picture your "thermal reasons" and how plating over
> the holes
>         will help, reliably. I haven't encountered a process for plating
> over
>         holes, and 21 mils seems quite a canyon to bridge. I'ld be very
> interested
>         to know how this is done.
>
>         I'm very involved with conduction-cooled MLB's 60 mils thk, that
> require a
>         lot of thermal management. 'Thermal' via holes are punched through
> the
>         board and plated to internal thermal planes. To improve the
> conductive
>         cross-sectional area of these holes, I had them filled with
> silver-loaded
>         epoxy, which was then Cu-plated over. This process also served the
>         secondary purpose of filling holes that otherwise, as you suggest,
> would
>         contain entrapped plating solutions.
>
>         Depending on your substrate material and operating environment, I
> could
>         imagine a plated 'cap' splitting over time through temp cycling
> and
>         mechanical stresses, assuming it survives the hot assembly
> processes
> with
>         the expansion of entrapped gasses. Not serious, thermally,
> perhaps,
> but it
>         would allow the outside atmosphere to circulate inside the holes
> as
> well,
>         which might not be so good inteh long run.
>
>         Peter
>
>
>
>
>                             "Marsico, James"
>                             <James.Marsico@D        To:
> [log in to unmask]
>                             P.AIL.COM>              cc:     (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
>                             Sent by: TechNet        Aero/ST Group)
>                             <[log in to unmask]        Subject:     [TN] VIAS
> PLATED CLOSED
>                             >
>
>
>                             01/11/02 05:55
>                             AM
>                             Please respond
>                             to "TechNet
>                             E-Mail Forum."
>
>
>
>
>
>
>         Good day technet:
>
>         We're considering designing a multilayer polyimide PWB with a
> number
> of
>         vias
>         (approximately .021" diameter holes, .062" thick PWB) that are
> plated shut,
>         for thermal reasons.  Can anyone comment on pitfalls regarding the
> fab
>         process?  How about voids in the solid copper via?  Entrapped
> plating
>         solution?
>
>         All comments are appreciated.  Thanks in advance...
>
>         Jim Marsico
>         Senior Engineer
>         Production Engineering
>         EDO Electronics Systems Group
>         [log in to unmask] <mailto:[log in to unmask]>
>         631-595-5879
>
>
> --------------------------------------------------------------------------
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Date:         Thu, 17 Jan 2002 13:05:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McGlaughlin, Jeffrey A" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject:      Scorching Temp for FR4
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Tech-sters

Does anyone know of a reference that gives approximate temperatures for
discoloration (scorching) of FR4 material?
We have a scorched board and would like a ballpark figure on how hot it was
before failure.

Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]

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Date:         Thu, 17 Jan 2002 13:13:59 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: VIAS PLATED CLOSED
X-To:         "Mcmaster, Michael" <[log in to unmask]>
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I already realized that!  The CB-100 material is negligible, with respect to
the copper, especially if you use 2 mils of plating.  What I really need is
a via fill material that can be successfully applied and plated over on top.
I know that virtually any material can be plated, but I'd like success
stories.

        -----Original Message-----
        From:   Mcmaster, Michael [SMTP:[log in to unmask]]
        Sent:   Thursday, January 17, 2002 12:51 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] VIAS PLATED CLOSED

        One thing I'd like to warn against is expecting a big increase in
thermal
        conduction of the hole by filling with CB-100.  Do the math
comparing the
        thermal conductivity of CB-100 and copper and the relative cross
sectional
        areas of the two materials.  For a 20 mil drilled hole with 1 mil of
copper,
        the CB-100 has 4x the cross-sectional area but only increases the
heat
        transfer by ~4%.  And this assumes the via is 100% filled.  But if
you just
        double the copper thickness in the barrel you get an almost 100%
increase.
        If you need the via fill for other reasons, for instance to avoid
solder
        loss down the barrel, then you should use it.  But for improved heat
        conduction, I don't see the value.  We've used the technique of
increasing
        the copper thickness in thermal vias on many designs, some of which
also
        have the vias filled.

        Just don't take adding the extra plating to the extreme and try to
plate
        them closed.  I agree with everyone else that's a bad idea.

        > ----------
        > From:         <Peter George Duncan>[SMTP:[log in to unmask]]
        > Reply To:     TechNet E-Mail Forum.
        > Sent:         Sunday, January 13, 2002 4:21 PM
        > To:   [log in to unmask]
        > Subject:      Re: [TN] VIAS PLATED CLOSED
        >
        > Hi, James,
        >
        > Hearing of what you're trying to do, I furrow my brow in anxiety.
If
        > you're
        > plating the entire hole closed, what surface copper weight are you
        > expecting as a result, especially with 21 mil diameter holes? My
estimate
        > is about 8 oz. What trace widths and spacings are involved? If
they're
        > fairly fine, the undercut from the etching process will probably
sever
        > them
        > from the board, or make them extremely weak. It is possible to
grind
        > excess
        > copper of the board surface, but this is a brutal and risky
process as
        > well, since if the board isn't dead flat, you can take off traces
and pads
        > adn go through to the substrate material.
        >
        >  If it's only the thermal holes you're trying to plate shut, how
are you
        > going to prevent the other holes in the board from being filled as
well
        > without a lot of selective masking? Also, I suspect that the holes
will
        > close at the top and bottom first, leaving a void in the centre
that will
        > contain plating solutions and cause all kinds of corrosive and
expansion
        > problems.
        >
        > This is not a good idea!!! My strong recommendation is that you
use silver
        > loaded epoxy to fill the thermal via holes prior to final plating.
It's
        > thermal conductivity is not as good as that of copper, but is
relatively a
        > lot less hassle and will be a lot cheaper than all that plating.
There are
        > a number of epoxies  available, though Dupont's CB100 is one that
is
        > commonly cited. It has a thermal conductivity value of 5.23 W/mK,
so is
        > pretty good for this type of material. Other makes are similar.
        >
        > Let us know how it goes. Good luck!!
        >
        > Peter
        >
        >
        >
        >
        >                     "Marsico, James"
        >                     <James.Marsico@D        To:
[log in to unmask]
        >                     P.AIL.COM>              cc:     (bcc: DUNCAN
        > Peter/Asst Prin Engr/ST
        >                     Sent by: TechNet        Aero/ST Group)
        >                     <[log in to unmask]        Subject:     Re: [TN]
VIAS
        > PLATED CLOSED
        >                     >
        >
        >
        >                     01/11/02 08:09
        >                     PM
        >                     Please respond
        >                     to "TechNet
        >                     E-Mail Forum."
        >
        >
        >
        >
        >
        >
        > Hi, Peter, thanks for the response.
        >
        > Let me try to explain further.  We're using ceramic leadless chip
carriers
        > which give off a lot of heat.  In an effort to dissipate the heat
to the
        > ground planes, we're placing thermal vias underneath.  We wanted
the
        > thermal
        > vias to be plated closed, resulting in a solid plug of copper,
which we
        > then
        > can deposit solder paste on top which would contact the bottom of
the
        > ceramic package.  The heat path would be from the component
through the
        > solder bumps on the thermal vias through the solid copper via.
Our board
        > supplier claims that he can plate the vias closed, but when I
asked about
        > voids and entrapped plating chemicals, he said he was never asked
that
        > before and would have to look into it.  I'm getting concerned with
this
        > design, thinking that an epoxy-filled via which is plated over on
top
        > would
        > be better.  I now need recommendations for a THERMALLY conductive
        > adhesive,
        > it doesn't have to be electrically conductive but I don't really
care.
        >
        > Thanks again,
        >
        > Jim Marsico
        > Senior Engineer
        > Production Engineering
        > EDO Electronics Systems Group
        > [log in to unmask] <mailto:[log in to unmask]>
        > 631-595-5879
        >
        >         -----Original Message-----
        >         From:   <Peter George Duncan>
[SMTP:[log in to unmask]]
        >         Sent:   Thursday, January 10, 2002 9:28 PM
        >         To:     [log in to unmask]
        >         Subject:        Re: [TN] VIAS PLATED CLOSED
        >
        >         Hi, James,
        >
        >         I'm trying to picture your "thermal reasons" and how
plating over
        > the holes
        >         will help, reliably. I haven't encountered a process for
plating
        > over
        >         holes, and 21 mils seems quite a canyon to bridge. I'ld be
very
        > interested
        >         to know how this is done.
        >
        >         I'm very involved with conduction-cooled MLB's 60 mils
thk, that
        > require a
        >         lot of thermal management. 'Thermal' via holes are punched
through
        > the
        >         board and plated to internal thermal planes. To improve
the
        > conductive
        >         cross-sectional area of these holes, I had them filled
with
        > silver-loaded
        >         epoxy, which was then Cu-plated over. This process also
served the
        >         secondary purpose of filling holes that otherwise, as you
suggest,
        > would
        >         contain entrapped plating solutions.
        >
        >         Depending on your substrate material and operating
environment, I
        > could
        >         imagine a plated 'cap' splitting over time through temp
cycling
        > and
        >         mechanical stresses, assuming it survives the hot assembly
        > processes
        > with
        >         the expansion of entrapped gasses. Not serious, thermally,
        > perhaps,
        > but it
        >         would allow the outside atmosphere to circulate inside the
holes
        > as
        > well,
        >         which might not be so good inteh long run.
        >
        >         Peter
        >
        >
        >
        >
        >                             "Marsico, James"
        >                             <James.Marsico@D        To:
        > [log in to unmask]
        >                             P.AIL.COM>              cc:     (bcc:
DUNCAN
        > Peter/Asst Prin Engr/ST
        >                             Sent by: TechNet        Aero/ST Group)
        >                             <[log in to unmask]        Subject:
[TN] VIAS
        > PLATED CLOSED
        >                             >
        >
        >
        >                             01/11/02 05:55
        >                             AM
        >                             Please respond
        >                             to "TechNet
        >                             E-Mail Forum."
        >
        >
        >
        >
        >
        >
        >         Good day technet:
        >
        >         We're considering designing a multilayer polyimide PWB
with a
        > number
        > of
        >         vias
        >         (approximately .021" diameter holes, .062" thick PWB) that
are
        > plated shut,
        >         for thermal reasons.  Can anyone comment on pitfalls
regarding the
        > fab
        >         process?  How about voids in the solid copper via?
Entrapped
        > plating
        >         solution?
        >
        >         All comments are appreciated.  Thanks in advance...
        >
        >         Jim Marsico
        >         Senior Engineer
        >         Production Engineering
        >         EDO Electronics Systems Group
        >         [log in to unmask] <mailto:[log in to unmask]>
        >         631-595-5879
        >
        >
        >
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Date:         Thu, 17 Jan 2002 13:22:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guy Ramsey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Re: Scorching Temp for FR4
X-To:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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My experience has been that they start to discolor around 260°C. I'm sure
this varies. The board will be charcol by 350°.

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of McGlaughlin, Jeffrey
> A
> Sent: Thursday, January 17, 2002 1:06 PM
> To: [log in to unmask]
> Subject: [TN] Scorching Temp for FR4
>
>
> Tech-sters
>
> Does anyone know of a reference that gives approximate temperatures for
> discoloration (scorching) of FR4 material?
> We have a scorched board and would like a ballpark figure on how
> hot it was
> before failure.
>
> Jeffrey A. McGlaughlin CID
> Sr. Designer
> Battelle Memorial Institute
> Columbus Ohio
> [log in to unmask]
>
> ------------------------------------------------------------------
> ---------------
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> ------------------------------------------------------------------
> ---------------
>

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Date:         Thu, 17 Jan 2002 12:30:53 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Rougeux, Scott" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Rougeux, Scott" <[log in to unmask]>
Subject:      Re: Thermocouples for SuperMole
X-To:         Becerra Alejandro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

try Omega

> -----Original Message-----
> From: Becerra Alejandro [SMTP:[log in to unmask]]
> Sent: Thursday, January 17, 2002 11:46 AM
> To:   [log in to unmask]
> Subject:      [TN] Thermocouples for SuperMole
>
> Hello to All,
> Could you please tell me any vendor for Thermocouples for SuperMole
> profiler?
>
> Thanks,
>
> Alejandro Becerra
>

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Date:         Thu, 17 Jan 2002 13:12:49 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tostevin, Bruce" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tostevin, Bruce" <[log in to unmask]>
Subject:      Re: Aqueous cleaning of surface mount potentiometers
X-To:         Paul Truit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Paul,

Check if your part is considered aqueous compatible by the manufacturer.  If
it's not, you're off to a tough start.  We've seen the problem Brian
mentioned - cooling air inside the pots sucking in moisture past the 0-ring.
You may be vulnerable to this if you take hot boards directly out of wave /
reflow and toss them right into the cleaner.

A basic leak test and dissection of leaking parts will lead you to the
whereabouts of the water intrusion.  I've seen parts with poor or incomplete
ultrasonic welds that make them prone to leaking, primarily near the
corners.  We've also seen parts with an excessive percentage of "reground"
plastic in the case, which contributed to poor dimensional stability and
watertight integrity.

Sometimes, despite your best efforts, a few random parts may still get water
forced into them - especially along the edge of the board where they're
directly exposed to the high pressure spray nozzles.  In those situations
you can fabricate temporary spray shields to clip over the pots, prior to
aqueous.  Make sure that the shield lets the water slosh freely around the
areas you must clean.

Bruce Tostevin
Benchmark Electronics
Hudson, NH


> -----Original Message-----
> From: Paul Truit [SMTP:[log in to unmask]]
> Sent: Wednesday, January 16, 2002 2:33 PM
> To:   [log in to unmask]
> Subject:      [TN] Aqueous cleaning of surface mount potentiometers
>
> I wanted to hear how fellow Technet people are processing surface mount
> potentiometers.
>
> I have experienced some field failures recently in this area.  Water has
> leaked into a "Sealed" potentiometer.  When power is applied an
> alternate circuit grows inside the pot causing the part to fail.
>
> We are processing this part using an OA solder paste through a normal
> pick and place operation.  Reflow profile takes this through a normal
> reflow curve Max. Peak temperature of 195-205 degrees C with a Ramp rate
> of 2-2.5 Degrees C.  We then add on a few through hole parts through
> progressive assembly then  wave solder and clean the assembly.
>
> We are utilizing an Electrovert Aquastorm 100.  We process the boards
> through at 4 feet per minute.  Water temperature is 145 degrees F.
>
> We have been cleaning boards (and potentiometers) for over eight years
> with never a problem.  This one has sure surprised me.  Just wondering
> if anyone else has had any experience with this and what they have done
> to fix this other than hand soldering the pot on in final.
>
>
> --
> Paul Truit, Mfg. Eng.
> RBB Systems, Inc.
> 4265C E. Lincolnway
> Wooster, OH  44691
> Ph. (330) 567-2906 ext 514
> Fax (330) 263-5324
> Email: [log in to unmask]
>
> --------------------------------------------------------------------------
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Date:         Thu, 17 Jan 2002 13:27:45 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Scorching Temp for FR4
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

Jeffrey

I don't have data to back up this statement, but IMO the discoloration is
has a time variable also.  Back in the old days, I've seen double sided FR-4
start to brown after two or three hours at 175 C.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
Sent: Thursday, January 17, 2002 12:23 PM
To: [log in to unmask]
Subject: Re: [TN] Scorching Temp for FR4


My experience has been that they start to discolor around 260°C. I'm sure
this varies. The board will be charcol by 350°.

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of McGlaughlin, Jeffrey
> A
> Sent: Thursday, January 17, 2002 1:06 PM
> To: [log in to unmask]
> Subject: [TN] Scorching Temp for FR4
>
>
> Tech-sters
>
> Does anyone know of a reference that gives approximate temperatures for
> discoloration (scorching) of FR4 material?
> We have a scorched board and would like a ballpark figure on how
> hot it was
> before failure.
>
> Jeffrey A. McGlaughlin CID
> Sr. Designer
> Battelle Memorial Institute
> Columbus Ohio
> [log in to unmask]
>
> ------------------------------------------------------------------
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Date:         Thu, 17 Jan 2002 17:03:22 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi All,

Now that I think of it we always stuck our nonfunctional pads in places we
didn't have to drill.  But I'm on the list to learn - thanks to Warren,
Werner.

Roger, this sounds very weird - granted I've only been in the industry since
'98.  There are very good reasons to use nonfunctional pads.  Now I know not
to use them in PTHs (& Route areas I imagine).  I wonder if people are
making this more difficult than it has to be - we've always used decent
sized dots so they wouldn't pop off of the core from rough handling or
processing.  We kept them far enough away from traces to avoid etch problems
- we're not talking about something that has to have a critical feature
size.  They may have been struggling with metallic contamination but
non-functional pads should be a fixable problem - no?

If they were truly having  problems with non-functional pads then they must
have had the same trouble with the functional pads?  Houston . . . . we've
had a problem.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Roger M. Stoops [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 2:10 PM
To: [log in to unmask]
Subject: Re: [TN] Remove unused "dead" pads on internal layers


I have been following this thread with interest.  When I asked a pcb vendor
about having non-functional pads in the inner layers, they said it was not
a good idea, that the unattached pads/lands would move around, or "float,"
and cause potential mfg problems, such as shorts to other copper.
Question:  Is there any truth to this statement, or is this just an old
husband's tale?
TIA,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]


Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511



                    "<Peter
                    George               To:     [log in to unmask]
                    Duncan>"             cc:
                    Sent by:             Subject:     Re: [TN] Remove unused
"dead" pads on internal layers
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/15/02
                    09:09 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    peter.duncan





Hi,

Actually these "unused" pads are replicates of the hole "rules" created for
the surface layers. Most routing packages, or routers, seem to do this by
default for each layer to save manual replication where traces, etc are to
be connected. (At least PADS, Alegro and Mentor do). On the grounds that
it's always easier to destroy than to build, it's easier to delete pad data
than to create it, so it's put in by default as there's a good chance it
will be needed.

I still say you should consider hole barrel strength/support issues before
just deleting them - e.g. they can constrain the "resin recession" and hole
wall pull-away that have been recent threads on this forum. Think of the
"unused" pads as 'wall ties' holding the copper at frequent intervals to
the hole wall. Copper bulging or pull-away in the event of recession or
whatever is reduced.

Peter Duncan




                    Hinners Hans M Civ
                    WRALC/LUGE                To:     [log in to unmask]
                    <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    NS.AF.MIL>                Aero/ST Group)
                    Sent by: TechNet          Subject:     Re: [TN] Remove
unused "dead" pads on
                    <[log in to unmask]>         internal layers


                    01/15/02 09:40 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Hinners
                    Hans M Civ
                    WRALC/LUGE






Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat

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=========================================================================
Date:         Thu, 17 Jan 2002 16:21:55 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Genny Gibbard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Fascinating stuff.  We had a board vendor at one point that wanted us to put
pads on all the layers of a PTH.  I thought the reason given was to help the
hole plating process.  Our standard block for multilayer boards
automatically puts pads on all layers and if not a ground via, it also
clears the ground plane away around it on all layers.  I've never heard of
any of the problems mentioned over the last few days.
It's kind of funny, the amount of things I hear about on this forum that
question things or dispute things that we've never really paid much
attention to in our own layouts makes me fascinated that this co. has gotten
as much product out the door working as it has over the last dozen years.  I
guess Murphy's law isn't always on duty.

-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: January 17, 2002 4:03 PM
To: [log in to unmask]
Subject: Re: [TN] Remove unused "dead" pads on internal layers


Hi All,

Now that I think of it we always stuck our nonfunctional pads in places we
didn't have to drill.  But I'm on the list to learn - thanks to Warren,
Werner.

Roger, this sounds very weird - granted I've only been in the industry since
'98.  There are very good reasons to use nonfunctional pads.  Now I know not
to use them in PTHs (& Route areas I imagine).  I wonder if people are
making this more difficult than it has to be - we've always used decent
sized dots so they wouldn't pop off of the core from rough handling or
processing.  We kept them far enough away from traces to avoid etch problems
- we're not talking about something that has to have a critical feature
size.  They may have been struggling with metallic contamination but
non-functional pads should be a fixable problem - no?

If they were truly having  problems with non-functional pads then they must
have had the same trouble with the functional pads?  Houston . . . . we've
had a problem.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Roger M. Stoops [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 2:10 PM
To: [log in to unmask]
Subject: Re: [TN] Remove unused "dead" pads on internal layers


I have been following this thread with interest.  When I asked a pcb vendor
about having non-functional pads in the inner layers, they said it was not
a good idea, that the unattached pads/lands would move around, or "float,"
and cause potential mfg problems, such as shorts to other copper.
Question:  Is there any truth to this statement, or is this just an old
husband's tale?
TIA,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]


Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511



                    "<Peter
                    George               To:     [log in to unmask]
                    Duncan>"             cc:
                    Sent by:             Subject:     Re: [TN] Remove unused
"dead" pads on internal layers
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/15/02
                    09:09 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    peter.duncan





Hi,

Actually these "unused" pads are replicates of the hole "rules" created for
the surface layers. Most routing packages, or routers, seem to do this by
default for each layer to save manual replication where traces, etc are to
be connected. (At least PADS, Alegro and Mentor do). On the grounds that
it's always easier to destroy than to build, it's easier to delete pad data
than to create it, so it's put in by default as there's a good chance it
will be needed.

I still say you should consider hole barrel strength/support issues before
just deleting them - e.g. they can constrain the "resin recession" and hole
wall pull-away that have been recent threads on this forum. Think of the
"unused" pads as 'wall ties' holding the copper at frequent intervals to
the hole wall. Copper bulging or pull-away in the event of recession or
whatever is reduced.

Peter Duncan




                    Hinners Hans M Civ
                    WRALC/LUGE                To:     [log in to unmask]
                    <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    NS.AF.MIL>                Aero/ST Group)
                    Sent by: TechNet          Subject:     Re: [TN] Remove
unused "dead" pads on
                    <[log in to unmask]>         internal layers


                    01/15/02 09:40 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Hinners
                    Hans M Civ
                    WRALC/LUGE






Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat

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=========================================================================
Date:         Thu, 17 Jan 2002 18:02:00 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: D-Pak 2nd side reflow issues
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hummm, surprising.

DPAK are fairly light [~ 0.300 gm] and have a relatively huge solderable
surface [~ 47mm^2/0.07in^2].  This weight to solderable area 6.3mgm/mm^2
[4.1gm/in^2] is well within both
* "Zarro Limit" of 30 gm/in^2.
* "Willis Limit" of 44gm/in^2.

From this perspective, DPAK numbers are similar to a mini-MELF and to a
SOIC16.

Are you soldering the tab?  If so, how about:
* Loctite 3609 or equivalent
* Conveying the board differently
* Turning-down your bottom-side fans

Dave Fish


----- Original Message -----
From: "Kevin M. Bair" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, January 17, 2002 6:18 AM
Subject: [TN] D-Pak 2nd side reflow issues


> We are having problems with bottom side d-paks falling off when the top
> side of the board is being reflowed.  Has anyone had this problem, and if
> so, what have you done to correct it?
>
> Thanks for your help,
>
> Kevin Bair
> Assembly Engineer
> Teradyne, Inc.
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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SET Technet NOMAIL
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
-------
>

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=========================================================================
Date:         Thu, 17 Jan 2002 16:29:51 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Bergman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Bergman <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="------------15284F793746A4916277BCA3"

--------------15284F793746A4916277BCA3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I cannot resist this one....

From a board manufacturer's point of view,  inner layer and outer layer pad concerns are completely
different.

The process of  imaging  and etching an inner layer involves: the photoresist being applied to an
undrilled core material, then the exposing and developing of it. This positive image is then put through
an etcher and this is the inner layer image, without holes. Then the cores are laminated and the board
is drilled. If a board has 4,000 holes, and 50 traces on an inner layer signal layer, I would rather
deal with 50 traces only, than 50 traces and 4,000+ pads. When the board is completed, a hole with no
pads on the innerlayers would be no different (or have no less integrity) than a hole on a
non-multilayer board. If the processes are under control, there should be no problem with the holes. The
material used in making a double sided board is manufactured in the same was as a multilayer board is
built, with prepreg and foil (basically).

As far as the outer layers go, small (< .150, say) non plated holes with pads that are intentional, must
be processed differently (an extra step) than non plated holes without pads. AND, if you have a large
non plated hole with small pad (<.015 per side over hole size), the pads can randomly pop off, for
various reasons.

I think the general opinion of most fab houses is this: Data comes in from so many different systems, it
is hard to know if there were restrictions on the data output, or if many of the situations are
intentional. If the fab house has a strong front end system all issues are addressed, and the boards are
built to the customer's  requirements. I can say that from a yeild point of view, though, most all
builders of PCB's would rather delete unused pads on inner layers, and have no pads on outer layer Npth
holes.

Regards,
K Bergman

Genny Gibbard wrote:

> Fascinating stuff.  We had a board vendor at one point that wanted us to put
> pads on all the layers of a PTH.  I thought the reason given was to help the
> hole plating process.  Our standard block for multilayer boards
> automatically puts pads on all layers and if not a ground via, it also
> clears the ground plane away around it on all layers.  I've never heard of
> any of the problems mentioned over the last few days.
> It's kind of funny, the amount of things I hear about on this forum that
> question things or dispute things that we've never really paid much
> attention to in our own layouts makes me fascinated that this co. has gotten
> as much product out the door working as it has over the last dozen years.  I
> guess Murphy's law isn't always on duty.
>
> -----Original Message-----
> From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
> Sent: January 17, 2002 4:03 PM
> To: [log in to unmask]
> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>
> Hi All,
>
> Now that I think of it we always stuck our nonfunctional pads in places we
> didn't have to drill.  But I'm on the list to learn - thanks to Warren,
> Werner.
>
> Roger, this sounds very weird - granted I've only been in the industry since
> '98.  There are very good reasons to use nonfunctional pads.  Now I know not
> to use them in PTHs (& Route areas I imagine).  I wonder if people are
> making this more difficult than it has to be - we've always used decent
> sized dots so they wouldn't pop off of the core from rough handling or
> processing.  We kept them far enough away from traces to avoid etch problems
> - we're not talking about something that has to have a critical feature
> size.  They may have been struggling with metallic contamination but
> non-functional pads should be a fixable problem - no?
>
> If they were truly having  problems with non-functional pads then they must
> have had the same trouble with the functional pads?  Houston . . . . we've
> had a problem.
>
> Hans
>
> Integrity First  -  Service Before Self  -  Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax:   (478) 926 - 4911
> DSN Prefix: 468
>
> -----Original Message-----
> From: Roger M. Stoops [mailto:[log in to unmask]]
> Sent: Wednesday, January 16, 2002 2:10 PM
> To: [log in to unmask]
> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>
> I have been following this thread with interest.  When I asked a pcb vendor
> about having non-functional pads in the inner layers, they said it was not
> a good idea, that the unattached pads/lands would move around, or "float,"
> and cause potential mfg problems, such as shorts to other copper.
> Question:  Is there any truth to this statement, or is this just an old
> husband's tale?
> TIA,
> Roger M. Stoops, C.I.D., PCB Designer
> [log in to unmask]
>
> Trimble
> Engineering and Construction Division
> 5475 Kellenburger Rd.
> Dayton, OH 45424-1099 USA
> Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
> Fax: +01 937.233.7511
>
>                     "<Peter
>                     George               To:     [log in to unmask]
>                     Duncan>"             cc:
>                     Sent by:             Subject:     Re: [TN] Remove unused
> "dead" pads on internal layers
>                     TechNet
>                     <[log in to unmask]
>                     ORG>
>
>                     01/15/02
>                     09:09 PM
>                     Please
>                     respond to
>                     "TechNet
>                     E-Mail
>                     Forum.";
>                     Please
>                     respond to
>                     peter.duncan
>
> Hi,
>
> Actually these "unused" pads are replicates of the hole "rules" created for
> the surface layers. Most routing packages, or routers, seem to do this by
> default for each layer to save manual replication where traces, etc are to
> be connected. (At least PADS, Alegro and Mentor do). On the grounds that
> it's always easier to destroy than to build, it's easier to delete pad data
> than to create it, so it's put in by default as there's a good chance it
> will be needed.
>
> I still say you should consider hole barrel strength/support issues before
> just deleting them - e.g. they can constrain the "resin recession" and hole
> wall pull-away that have been recent threads on this forum. Think of the
> "unused" pads as 'wall ties' holding the copper at frequent intervals to
> the hole wall. Copper bulging or pull-away in the event of recession or
> whatever is reduced.
>
> Peter Duncan
>
>                     Hinners Hans M Civ
>                     WRALC/LUGE                To:     [log in to unmask]
>                     <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
>                     NS.AF.MIL>                Aero/ST Group)
>                     Sent by: TechNet          Subject:     Re: [TN] Remove
> unused "dead" pads on
>                     <[log in to unmask]>         internal layers
>
>                     01/15/02 09:40 PM
>                     Please respond to
>                     "TechNet E-Mail
>                     Forum."; Please
>                     respond to Hinners
>                     Hans M Civ
>                     WRALC/LUGE
>
> Hi Patrick,
>
> As others have said, I don't think the class of board matters for "unused"
> pads.  It all depends on what your procurement documentation states, are
> you
> building to drawing or is there a clause that says process improvements
> that
> do not affect functionality are permissible.
>
> "Are they really unused pads?"
>
> They may be electrically nonfunctioning but they are there for a reason -
> better lamination quality (avoiding low pressure areas or excessive prepreg
> flow), better hole wall quality, better plating quality (esp. for any
> isolated traces), reduced loading of your etch solution or better thermal
> loading during assembly.
>
> Hans
>
> Integrity First  -  Service Before Self  -  Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax:   (478) 926 - 4911
> DSN Prefix: 468
>
> -----Original Message-----
> From: Patrick Lam [mailto:[log in to unmask]]
> Sent: Friday, January 11, 2002 5:12 PM
> To: [log in to unmask]
> Subject: [TN] Remove unused "dead" pads on internal layers
>
> Hi TechNetters,
>
> For class 3 boards, is it acceptable to have unused pads removed on
> interanal
> layers.
>
> Thanks,
> Pat
>
> ----------------------------------------------------------------------------
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<html>
I cannot resist this one....
<p>From a board manufacturer's point of view,&nbsp; inner layer and outer
layer pad concerns are completely different.
<p>The process of&nbsp; imaging&nbsp; and etching an inner layer involves:
the photoresist being applied to an undrilled core material, then the exposing
and developing of it. This positive image is then put through an etcher
and this is the inner layer image, without holes. Then the cores are laminated
and the board is drilled. If a board has 4,000 holes, and 50 traces on
an inner layer signal layer, I would rather deal with 50 traces <u>only,</u>
than 50 traces <u>and</u> 4,000+ pads. When the board is completed, a hole
with no pads on the innerlayers would be no different (or have no less
integrity) than a hole on a non-multilayer board. If the processes are
under control, there should be no problem with the holes. The material
used in making a double sided board is manufactured in the same was as
a multilayer board is built, with prepreg and foil (basically).
<p>As far as the outer layers go, small (&lt; .150, say) non plated holes
with pads that are intentional, must be processed differently (an extra
step) than non plated holes without pads. AND, if you have a large non
plated hole with small pad (&lt;.015 per side over hole size), the pads
can randomly pop off, for various reasons.
<p>I think the general opinion of most fab houses is this: Data comes in
from so many different systems, it is hard to know if there were restrictions
on the data output, or if many of the situations are intentional. If the
fab house has a strong front end system all issues are addressed, and the
boards are built to the customer's&nbsp; requirements. I can say that from
a yeild point of view, though, most all builders of PCB's would rather
delete unused pads on inner layers, and have no pads on outer layer Npth
holes.
<p>Regards,
<br>K Bergman
<p>Genny Gibbard wrote:
<blockquote TYPE=CITE>Fascinating stuff.&nbsp; We had a board vendor at
one point that wanted us to put
<br>pads on all the layers of a PTH.&nbsp; I thought the reason given was
to help the
<br>hole plating process.&nbsp; Our standard block for multilayer boards
<br>automatically puts pads on all layers and if not a ground via, it also
<br>clears the ground plane away around it on all layers.&nbsp; I've never
heard of
<br>any of the problems mentioned over the last few days.
<br>It's kind of funny, the amount of things I hear about on this forum
that
<br>question things or dispute things that we've never really paid much
<br>attention to in our own layouts makes me fascinated that this co. has
gotten
<br>as much product out the door working as it has over the last dozen
years.&nbsp; I
<br>guess Murphy's law isn't always on duty.
<p>-----Original Message-----
<br>From: Hinners Hans M Civ WRALC/LUGE [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: January 17, 2002 4:03 PM
<br>To: [log in to unmask]
<br>Subject: Re: [TN] Remove unused "dead" pads on internal layers
<p>Hi All,
<p>Now that I think of it we always stuck our nonfunctional pads in places
we
<br>didn't have to drill.&nbsp; But I'm on the list to learn - thanks to
Warren,
<br>Werner.
<p>Roger, this sounds very weird - granted I've only been in the industry
since
<br>'98.&nbsp; There are very good reasons to use nonfunctional pads.&nbsp;
Now I know not
<br>to use them in PTHs (&amp; Route areas I imagine).&nbsp; I wonder if
people are
<br>making this more difficult than it has to be - we've always used decent
<br>sized dots so they wouldn't pop off of the core from rough handling
or
<br>processing.&nbsp; We kept them far enough away from traces to avoid
etch problems
<br>- we're not talking about something that has to have a critical feature
<br>size.&nbsp; They may have been struggling with metallic contamination
but
<br>non-functional pads should be a fixable problem - no?
<p>If they were truly having&nbsp; problems with non-functional pads then
they must
<br>have had the same trouble with the functional pads?&nbsp; Houston .
. . . we've
<br>had a problem.
<p>Hans
<p>Integrity First&nbsp; -&nbsp; Service Before Self&nbsp; -&nbsp; Excellence
in All We Do
<br>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
<br>Hans M. Hinners
<br>Electronics Engineer
<br>Warner Robins - Air Logistics Center (WR-ALC/LUGE)
<br>226 Cochran Street
<br>Robins AFB GA 31098-1622
<p><a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
<p>Com: (478) 926 - 5224
<br>Fax:&nbsp;&nbsp; (478) 926 - 4911
<br>DSN Prefix: 468
<p>-----Original Message-----
<br>From: Roger M. Stoops [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: Wednesday, January 16, 2002 2:10 PM
<br>To: [log in to unmask]
<br>Subject: Re: [TN] Remove unused "dead" pads on internal layers
<p>I have been following this thread with interest.&nbsp; When I asked
a pcb vendor
<br>about having non-functional pads in the inner layers, they said it
was not
<br>a good idea, that the unattached pads/lands would move around, or "float,"
<br>and cause potential mfg problems, such as shorts to other copper.
<br>Question:&nbsp; Is there any truth to this statement, or is this just
an old
<br>husband's tale?
<br>TIA,
<br>Roger M. Stoops, C.I.D., PCB Designer
<br>[log in to unmask]
<p>Trimble
<br>Engineering and Construction Division
<br>5475 Kellenburger Rd.
<br>Dayton, OH 45424-1099 USA
<br>Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
<br>Fax: +01 937.233.7511
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
"&lt;Peter
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
George&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
To:&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Duncan>"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
cc:
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Sent by:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Subject:&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Remove unused
<br>"dead" pads on internal layers
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
TechNet
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&lt;[log in to unmask]
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ORG>
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
01/15/02
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
09:09 PM
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Please
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
respond to
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
"TechNet
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
E-Mail
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Forum.";
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Please
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
respond to
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
peter.duncan
<p>Hi,
<p>Actually these "unused" pads are replicates of the hole "rules" created
for
<br>the surface layers. Most routing packages, or routers, seem to do this
by
<br>default for each layer to save manual replication where traces, etc
are to
<br>be connected. (At least PADS, Alegro and Mentor do). On the grounds
that
<br>it's always easier to destroy than to build, it's easier to delete
pad data
<br>than to create it, so it's put in by default as there's a good chance
it
<br>will be needed.
<p>I still say you should consider hole barrel strength/support issues
before
<br>just deleting them - e.g. they can constrain the "resin recession"
and hole
<br>wall pull-away that have been recent threads on this forum. Think of
the
<br>"unused" pads as 'wall ties' holding the copper at frequent intervals
to
<br>the hole wall. Copper bulging or pull-away in the event of recession
or
<br>whatever is reduced.
<p>Peter Duncan
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Hinners Hans M Civ
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
WRALC/LUGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
To:&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&lt;Hans.Hinners@ROBI&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cc:&nbsp;&nbsp;&nbsp;&nbsp;
(bcc: DUNCAN
<br>Peter/Asst Prin Engr/ST
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
NS.AF.MIL>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Aero/ST Group)
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Sent by: TechNet&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Subject:&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Remove
<br>unused "dead" pads on
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&lt;[log in to unmask]>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; internal
layers
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
01/15/02 09:40 PM
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Please respond to
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
"TechNet E-Mail
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Forum."; Please
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
respond to Hinners
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Hans M Civ
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
WRALC/LUGE
<p>Hi Patrick,
<p>As others have said, I don't think the class of board matters for "unused"
<br>pads.&nbsp; It all depends on what your procurement documentation states,
are
<br>you
<br>building to drawing or is there a clause that says process improvements
<br>that
<br>do not affect functionality are permissible.
<p>"Are they really unused pads?"
<p>They may be electrically nonfunctioning but they are there for a reason
-
<br>better lamination quality (avoiding low pressure areas or excessive
prepreg
<br>flow), better hole wall quality, better plating quality (esp. for any
<br>isolated traces), reduced loading of your etch solution or better thermal
<br>loading during assembly.
<p>Hans
<p>Integrity First&nbsp; -&nbsp; Service Before Self&nbsp; -&nbsp; Excellence
in All We Do
<br>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
<br>Hans M. Hinners
<br>Electronics Engineer
<br>Warner Robins - Air Logistics Center (WR-ALC/LUGE)
<br>226 Cochran Street
<br>Robins AFB GA 31098-1622
<p><a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
<p>Com: (478) 926 - 5224
<br>Fax:&nbsp;&nbsp; (478) 926 - 4911
<br>DSN Prefix: 468
<p>-----Original Message-----
<br>From: Patrick Lam [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: Friday, January 11, 2002 5:12 PM
<br>To: [log in to unmask]
<br>Subject: [TN] Remove unused "dead" pads on internal layers
<p>Hi TechNetters,
<p>For class 3 boards, is it acceptable to have unused pads removed on
<br>interanal
<br>layers.
<p>Thanks,
<br>Pat
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=========================================================================
Date:         Thu, 17 Jan 2002 19:47:27 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Charles McMahon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Charles McMahon <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Kathy Bergman <[log in to unmask]>
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Ms. Bergman is correct.
The more features to deal with, the more opportunity for defects.
It only makes sense to eliminate non-functional components within a design.
This requires the end user to consider advising the designer to perform
the function of optimization.
I have found they will not do so except under extreme social pressure.
Was this type of scenario not the precursor to the need for DFM?

Lastly, as a provider of pcb's, I would be less inclined to have the FAB
shop make modifcations of this type to the data as a matter of process.
I would encourage instead that the customer have their designer do these
optimizations to avoid any mis-understandings.
The goal of course is to do it right the first time to increase yields
and lower costs to the customer.

Sincerely,
Charlie McMahon



Kathy Bergman wrote:

> I cannot resist this one....
>
> From a board manufacturer's point of view,  inner layer and outer
> layer pad concerns are completely different.
>
> The process of  imaging  and etching an inner layer involves: the
> photoresist being applied to an undrilled core material, then the
> exposing and developing of it. This positive image is then put through
> an etcher and this is the inner layer image, without holes. Then the
> cores are laminated and the board is drilled. If a board has 4,000
> holes, and 50 traces on an inner layer signal layer, I would rather
> deal with 50 traces only, than 50 traces and 4,000+ pads. When the
> board is completed, a hole with no pads on the innerlayers would be no
> different (or have no less integrity) than a hole on a non-multilayer
> board. If the processes are under control, there should be no problem
> with the holes. The material used in making a double sided board is
> manufactured in the same was as a multilayer board is built, with
> prepreg and foil (basically).
>
> As far as the outer layers go, small (< .150, say) non plated holes
> with pads that are intentional, must be processed differently (an
> extra step) than non plated holes without pads. AND, if you have a
> large non plated hole with small pad (<.015 per side over hole size),
> the pads can randomly pop off, for various reasons.
>
> I think the general opinion of most fab houses is this: Data comes in
> from so many different systems, it is hard to know if there were
> restrictions on the data output, or if many of the situations are
> intentional. If the fab house has a strong front end system all issues
> are addressed, and the boards are built to the customer's
> requirements. I can say that from a yeild point of view, though, most
> all builders of PCB's would rather delete unused pads on inner layers,
> and have no pads on outer layer Npth holes.
>
> Regards,
> K Bergman
>
> Genny Gibbard wrote:
>
>> Fascinating stuff.  We had a board vendor at one point that wanted us
>> to put
>> pads on all the layers of a PTH.  I thought the reason given was to
>> help the
>> hole plating process.  Our standard block for multilayer boards
>> automatically puts pads on all layers and if not a ground via, it also
>> clears the ground plane away around it on all layers.  I've never
>> heard of
>> any of the problems mentioned over the last few days.
>> It's kind of funny, the amount of things I hear about on this forum that
>> question things or dispute things that we've never really paid much
>> attention to in our own layouts makes me fascinated that this co. has
>> gotten
>> as much product out the door working as it has over the last dozen
>> years.  I
>> guess Murphy's law isn't always on duty.
>>
>> -----Original Message-----
>> From: Hinners Hans M Civ WRALC/LUGE [
>> mailto:[log in to unmask] ]
>> Sent: January 17, 2002 4:03 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>>
>> Hi All,
>>
>> Now that I think of it we always stuck our nonfunctional pads in
>> places we
>> didn't have to drill.  But I'm on the list to learn - thanks to Warren,
>> Werner.
>>
>> Roger, this sounds very weird - granted I've only been in the
>> industry since
>> '98.  There are very good reasons to use nonfunctional pads.  Now I
>> know not
>> to use them in PTHs (& Route areas I imagine).  I wonder if people are
>> making this more difficult than it has to be - we've always used decent
>> sized dots so they wouldn't pop off of the core from rough handling or
>> processing.  We kept them far enough away from traces to avoid etch
>> problems
>> - we're not talking about something that has to have a critical feature
>> size.  They may have been struggling with metallic contamination but
>> non-functional pads should be a fixable problem - no?
>>
>> If they were truly having  problems with non-functional pads then
>> they must
>> have had the same trouble with the functional pads?  Houston . . . .
>> we've
>> had a problem.
>>
>> Hans
>>
>> Integrity First  -  Service Before Self  -  Excellence in All We Do
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> Hans M. Hinners
>> Electronics Engineer
>> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
>> 226 Cochran Street
>> Robins AFB GA 31098-1622
>>
>> mailto:[log in to unmask]
>>
>> Com: (478) 926 - 5224
>> Fax:   (478) 926 - 4911
>> DSN Prefix: 468
>>
>> -----Original Message-----
>> From: Roger M. Stoops [mailto:[log in to unmask] ]
>> Sent: Wednesday, January 16, 2002 2:10 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>>
>> I have been following this thread with interest.  When I asked a pcb
>> vendor
>> about having non-functional pads in the inner layers, they said it
>> was not
>> a good idea, that the unattached pads/lands would move around, or
>> "float,"
>> and cause potential mfg problems, such as shorts to other copper.
>> Question:  Is there any truth to this statement, or is this just an old
>> husband's tale?
>> TIA,
>> Roger M. Stoops, C.I.D., PCB Designer
>> [log in to unmask]
>>
>> Trimble
>> Engineering and Construction Division
>> 5475 Kellenburger Rd.
>> Dayton, OH 45424-1099 USA
>> Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
>> Fax: +01 937.233.7511
>>
>>                     "<Peter
>>                     George               To:     [log in to unmask]
>>                     Duncan>"             cc:
>>                     Sent by:             Subject:     Re: [TN] Remove
>> unused
>> "dead" pads on internal layers
>>                     TechNet
>>                     <[log in to unmask]
>>                     ORG>
>>
>>                     01/15/02
>>                     09:09 PM
>>                     Please
>>                     respond to
>>                     "TechNet
>>                     E-Mail
>>                     Forum.";
>>                     Please
>>                     respond to
>>                     peter.duncan
>>
>> Hi,
>>
>> Actually these "unused" pads are replicates of the hole "rules"
>> created for
>> the surface layers. Most routing packages, or routers, seem to do
>> this by
>> default for each layer to save manual replication where traces, etc
>> are to
>> be connected. (At least PADS, Alegro and Mentor do). On the grounds that
>> it's always easier to destroy than to build, it's easier to delete
>> pad data
>> than to create it, so it's put in by default as there's a good chance it
>> will be needed.
>>
>> I still say you should consider hole barrel strength/support issues
>> before
>> just deleting them - e.g. they can constrain the "resin recession"
>> and hole
>> wall pull-away that have been recent threads on this forum. Think of the
>> "unused" pads as 'wall ties' holding the copper at frequent intervals to
>> the hole wall. Copper bulging or pull-away in the event of recession or
>> whatever is reduced.
>>
>> Peter Duncan
>>
>>                     Hinners Hans M Civ
>>                     WRALC/LUGE                To:     [log in to unmask]
>>                     <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
>> Peter/Asst Prin Engr/ST
>>                     NS.AF.MIL>                Aero/ST Group)
>>                     Sent by: TechNet          Subject:     Re: [TN]
>> Remove
>> unused "dead" pads on
>>                     <[log in to unmask]>         internal layers
>>
>>                     01/15/02 09:40 PM
>>                     Please respond to
>>                     "TechNet E-Mail
>>                     Forum."; Please
>>                     respond to Hinners
>>                     Hans M Civ
>>                     WRALC/LUGE
>>
>> Hi Patrick,
>>
>> As others have said, I don't think the class of board matters for
>> "unused"
>> pads.  It all depends on what your procurement documentation states, are
>> you
>> building to drawing or is there a clause that says process improvements
>> that
>> do not affect functionality are permissible.
>>
>> "Are they really unused pads?"
>>
>> They may be electrically nonfunctioning but they are there for a
>> reason -
>> better lamination quality (avoiding low pressure areas or excessive
>> prepreg
>> flow), better hole wall quality, better plating quality (esp. for any
>> isolated traces), reduced loading of your etch solution or better
>> thermal
>> loading during assembly.
>>
>> Hans
>>
>> Integrity First  -  Service Before Self  -  Excellence in All We Do
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> Hans M. Hinners
>> Electronics Engineer
>> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
>> 226 Cochran Street
>> Robins AFB GA 31098-1622
>>
>> mailto:[log in to unmask]
>>
>> Com: (478) 926 - 5224
>> Fax:   (478) 926 - 4911
>> DSN Prefix: 468
>>
>> -----Original Message-----
>> From: Patrick Lam [mailto:[log in to unmask] ]
>> Sent: Friday, January 11, 2002 5:12 PM
>> To: [log in to unmask]
>> Subject: [TN] Remove unused "dead" pads on internal layers
>>
>> Hi TechNetters,
>>
>> For class 3 boards, is it acceptable to have unused pads removed on
>> interanal
>> layers.
>>
>> Thanks,
>> Pat
>>
>> ----------------------------------------------------------------------------
>>
>> -----
>> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
>> To unsubscribe, send a message to [log in to unmask] with following
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>> To receive ONE mailing per day of all the posts: send e-mail to
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>> Please visit IPC web site (http://www.ipc.org/html/forum.htm ) for
>> additional
>> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>> ext.5315
>> ----------------------------------------------------------------------------
>>
>> -----
>>
>> ----------------------------------------------------------------------------
>>
>> -----
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>> To unsubscribe, send a message to [log in to unmask] with following
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>> Technet NOMAIL
>> To receive ONE mailing per day of all the posts: send e-mail to
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>> Databases >
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>> Please visit IPC web site (http://www.ipc.org/html/forum.htm ) for
>> additional
>> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>> ext.5315
>> ----------------------------------------------------------------------------
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>> -----
>>
>> ---------------------------------------------------------------------------------
>>
>> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
>> To unsubscribe, send a message to [log in to unmask] with following
>> text in
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>> To temporarily halt delivery of Technet send e-mail to
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>> To receive ONE mailing per day of all the posts: send e-mail to
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>> Please visit IPC web site (http://www.ipc.org/html/forum.htm ) for
>> additional
>> information, or contact Keach Sasamori at [log in to unmask] or
>> 847-509-9700 ext.5315
>> ---------------------------------------------------------------------------------
>>


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<html>
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<body>
Ms. Bergman is correct.<br>
The more features to deal with, the more opportunity for defects.<br>
It only makes sense to eliminate non-functional components within a design.<br>
This requires the end user to consider advising the designer to perform the
function of optimization.<br>
I have found they will not do so except under extreme social pressure. <br>
Was this type of scenario not the precursor to the need for DFM?<br>
<br>
Lastly, as a provider of pcb's, I would be less inclined to have the FAB
shop make modifcations of this type to the data as a matter of process. <br>
I would encourage instead that the customer have their designer do these
optimizations to avoid any mis-understandings.<br>
The goal of course is to do it right the first time to increase yields and
lower costs to the customer.<br>
<br>
Sincerely,<br>
Charlie McMahon<br>
<br>
&nbsp;<br>
<br>
Kathy Bergman wrote:<br>
<blockquote type="cite" cite="mid:[log in to unmask]"> I
cannot resist this one....
  <p>From a board manufacturer's point of view,&nbsp; inner layer and outer layer
pad concerns are completely different. </p>
  <p>The process of&nbsp; imaging&nbsp; and etching an inner layer involves: the photoresist
being applied to an undrilled core material, then the exposing and developing
of it. This positive image is then put through an etcher and this is the
inner layer image, without holes. Then the cores are laminated and the board
is drilled. If a board has 4,000 holes, and 50 traces on an inner layer signal
layer, I would rather deal with 50 traces <u>only,</u> than 50 traces <u>
and</u> 4,000+ pads. When the board is completed, a hole with no pads on
the innerlayers would be no different (or have no less integrity) than a
hole on a non-multilayer board. If the processes are under control, there
should be no problem with the holes. The material used in making a double
sided board is manufactured in the same was as a multilayer board is built,
with prepreg and foil (basically). </p>
  <p>As far as the outer layers go, small (&lt; .150, say) non plated holes
with pads that are intentional, must be processed differently (an extra step)
than non plated holes without pads. AND, if you have a large non plated hole
with small pad (&lt;.015 per side over hole size), the pads can randomly
pop off, for various reasons. </p>
  <p>I think the general opinion of most fab houses is this: Data comes in
from so many different systems, it is hard to know if there were restrictions
on the data output, or if many of the situations are intentional. If the fab
house has a strong front end system all issues are addressed, and the boards
are built to the customer's&nbsp; requirements. I can say that from a yeild point
of view, though, most all builders of PCB's would rather delete unused pads
on inner layers, and have no pads on outer layer Npth holes. </p>
  <p>Regards, <br>
K Bergman </p>
  <p>Genny Gibbard wrote: </p>
  <blockquote type="CITE">Fascinating stuff.&nbsp; We had a board vendor at one
point that wanted us to put <br>
pads on all the layers of a PTH.&nbsp; I thought the reason given was to help
the <br>
hole plating process.&nbsp; Our standard block for multilayer boards <br>
automatically puts pads on all layers and if not a ground via, it also <br>
clears the ground plane away around it on all layers.&nbsp; I've never heard of
    <br>
any of the problems mentioned over the last few days. <br>
It's kind of funny, the amount of things I hear about on this forum that <br>
question things or dispute things that we've never really paid much <br>
attention to in our own layouts makes me fascinated that this co. has gotten
    <br>
as much product out the door working as it has over the last dozen years.&nbsp;
I <br>
guess Murphy's law isn't always on duty.
    <p>-----Original Message----- <br>
From: Hinners Hans M Civ WRALC/LUGE [<a href="mailto:[log in to unmask]">
mailto:[log in to unmask]</a>
] <br>
Sent: January 17, 2002 4:03 PM <br>
To: <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> <br>
Subject: Re: [TN] Remove unused "dead" pads on internal layers </p>
    <p>Hi All, </p>
    <p>Now that I think of it we always stuck our nonfunctional pads in places
we <br>
didn't have to drill.&nbsp; But I'm on the list to learn - thanks to Warren, <br>
Werner. </p>
    <p>Roger, this sounds very weird - granted I've only been in the industry
since <br>
'98.&nbsp; There are very good reasons to use nonfunctional pads.&nbsp; Now I know
not <br>
to use them in PTHs (&amp; Route areas I imagine).&nbsp; I wonder if people are
    <br>
making this more difficult than it has to be - we've always used decent <br>
sized dots so they wouldn't pop off of the core from rough handling or <br>
processing.&nbsp; We kept them far enough away from traces to avoid etch problems
    <br>
- we're not talking about something that has to have a critical feature <br>
size.&nbsp; They may have been struggling with metallic contamination but <br>
non-functional pads should be a fixable problem - no? </p>
    <p>If they were truly having&nbsp; problems with non-functional pads then they
must <br>
have had the same trouble with the functional pads?&nbsp; Houston . . . . we've
    <br>
had a problem. </p>
    <p>Hans </p>
    <p>Integrity First&nbsp; -&nbsp; Service Before Self&nbsp; -&nbsp; Excellence in All We Do
    <br>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ <br>
Hans M. Hinners <br>
Electronics Engineer <br>
Warner Robins - Air Logistics Center (WR-ALC/LUGE) <br>
226 Cochran Street <br>
Robins AFB GA 31098-1622 </p>
    <p><a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
    </p>
    <p>Com: (478) 926 - 5224 <br>
Fax:&nbsp;&nbsp; (478) 926 - 4911 <br>
DSN Prefix: 468 </p>
    <p>-----Original Message----- <br>
From: Roger M. Stoops [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
] <br>
Sent: Wednesday, January 16, 2002 2:10 PM <br>
To: <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> <br>
Subject: Re: [TN] Remove unused "dead" pads on internal layers </p>
    <p>I have been following this thread with interest.&nbsp; When I asked a pcb
vendor <br>
about having non-functional pads in the inner layers, they said it was not
    <br>
a good idea, that the unattached pads/lands would move around, or "float,"
    <br>
and cause potential mfg problems, such as shorts to other copper. <br>
Question:&nbsp; Is there any truth to this statement, or is this just an old <br>
husband's tale? <br>
TIA, <br>
Roger M. Stoops, C.I.D., PCB Designer <br>
<a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> </p>
    <p>Trimble <br>
Engineering and Construction Division <br>
5475 Kellenburger Rd. <br>
Dayton, OH 45424-1099 USA <br>
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288 <br>
Fax: +01 937.233.7511 </p>
    <p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&lt;Peter <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; George&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp;&nbsp;&nbsp;&nbsp; <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Duncan&gt;"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cc: <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent by:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject:&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Remove unused
    <br>
"dead" pads on internal layers <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TechNet <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;<a class="moz-txt-link-abbreviated" href="mailto:TechNet@IPC">TechNet@IPC</a>. <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ORG&gt; </p>
    <p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 01/15/02 <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 09:09 PM <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; respond to <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "TechNet <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; E-Mail <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Forum."; <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; respond to <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; peter.duncan </p>
    <p>Hi, </p>
    <p>Actually these "unused" pads are replicates of the hole "rules" created
for <br>
the surface layers. Most routing packages, or routers, seem to do this by
    <br>
default for each layer to save manual replication where traces, etc are to
    <br>
be connected. (At least PADS, Alegro and Mentor do). On the grounds that <br>
it's always easier to destroy than to build, it's easier to delete pad data
    <br>
than to create it, so it's put in by default as there's a good chance it <br>
will be needed. </p>
    <p>I still say you should consider hole barrel strength/support issues
before <br>
just deleting them - e.g. they can constrain the "resin recession" and hole
    <br>
wall pull-away that have been recent threads on this forum. Think of the <br>
"unused" pads as 'wall ties' holding the copper at frequent intervals to <br>
the hole wall. Copper bulging or pull-away in the event of recession or <br>
whatever is reduced. </p>
    <p>Peter Duncan </p>
    <p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hinners Hans M Civ <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WRALC/LUGE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp;&nbsp;&nbsp;&nbsp; <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;<a class="moz-txt-link-abbreviated" href="mailto:Hans.Hinners@ROBI&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;">Hans.Hinners@ROBI&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</a> cc:&nbsp;&nbsp;&nbsp;&nbsp; (bcc: DUNCAN <br>
Peter/Asst Prin Engr/ST <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NS.AF.MIL&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Aero/ST Group) <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent by: TechNet&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject:&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Remove
    <br>
unused "dead" pads on <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a class="moz-txt-link-rfc2396E" href="mailto:[log in to unmask]">&lt;[log in to unmask]&gt;</a>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; internal layers </p>
    <p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 01/15/02 09:40 PM <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please respond to <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "TechNet E-Mail <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Forum."; Please <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; respond to Hinners <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hans M Civ <br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; WRALC/LUGE </p>
    <p>Hi Patrick, </p>
    <p>As others have said, I don't think the class of board matters for
"unused" <br>
pads.&nbsp; It all depends on what your procurement documentation states, are <br>
you <br>
building to drawing or is there a clause that says process improvements <br>
that <br>
do not affect functionality are permissible. </p>
    <p>"Are they really unused pads?" </p>
    <p>They may be electrically nonfunctioning but they are there for a reason
- <br>
better lamination quality (avoiding low pressure areas or excessive prepreg
    <br>
flow), better hole wall quality, better plating quality (esp. for any <br>
isolated traces), reduced loading of your etch solution or better thermal
    <br>
loading during assembly. </p>
    <p>Hans </p>
    <p>Integrity First&nbsp; -&nbsp; Service Before Self&nbsp; -&nbsp; Excellence in All We Do
    <br>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ <br>
Hans M. Hinners <br>
Electronics Engineer <br>
Warner Robins - Air Logistics Center (WR-ALC/LUGE) <br>
226 Cochran Street <br>
Robins AFB GA 31098-1622 </p>
    <p><a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
    </p>
    <p>Com: (478) 926 - 5224 <br>
Fax:&nbsp;&nbsp; (478) 926 - 4911 <br>
DSN Prefix: 468 </p>
    <p>-----Original Message----- <br>
From: Patrick Lam [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>
] <br>
Sent: Friday, January 11, 2002 5:12 PM <br>
To: <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> <br>
Subject: [TN] Remove unused "dead" pads on internal layers </p>
    <p>Hi TechNetters, </p>
    <p>For class 3 boards, is it acceptable to have unused pads removed on
    <br>
interanal <br>
layers. </p>
    <p>Thanks, <br>
Pat </p>
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Date:         Thu, 17 Jan 2002 17:13:51 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: Al Electrolytic Capacitors leaking
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----_=_NextPart_001_01C19FBD.63B7CDB0"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01C19FBD.63B7CDB0
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hi,

there may be no easy solution.  if indeed it is a defect associated with a specific lot, you should be able to come up with a test that would filter out subsequent parts at receiving inspection.  you may also need to create a specification control drawing to add this requirement to the vendor's specification.

this leaves you with a task of identifying and replacing those parts from the suspect lot that you have already attached.

can you consider a two stage reflow process?  the first stage would be your normal process without the capacitors.  the second stage would be a reflow process in which a low termperature solder is used.

good luck.

phil

-----Original Message-----
From: Howard Watson [mailto:[log in to unmask]]
Sent: Thursday, January 17, 2002 7:09 AM
To: [log in to unmask]
Subject: Re: [TN] Al Electrolytic Capacitors leaking



Thanks Phil.  I am wondering if the 218C is too high of a peak temperature for these type of components.  We use a lot of them, so hand soldering is not a popular recommendation here.  Can they get damaged without any visible defect?  I have isolated the problem to a specific lot, but then maybe it will show up again in the future.

Howard Watson
Manufacturing Engineer
AMETEK/Dixson



        "Crepeau, Phil" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>


01/16/02 04:45 PM
Please respond to "TechNet E-Mail Forum."; Please respond to "Crepeau, Phil"



        To:        [log in to unmask]
        cc:
        Subject:        Re: [TN] Al Electrolytic Capacitors leaking



hi,

definitely sounds like a job for hand soldering after mass reflow.  oh, and definitely, these parts are prone to failure at high temperature.  isn't everything?

phil
-----Original Message-----
From: Howard Watson [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 12:28 PM
To: [log in to unmask]
Subject: [TN] Al Electrolytic Capacitors leaking


Technetters,

Please help!  I have some Aluminum Electrolytic Capacitors that are leaking fluid on the top of the can after reflow.  My peak temperature on the top of the can is 218C, with a time above 183 at 53 seconds, which seem to be appropriate.  The manufacturer recommends the time above 200C to be 20 seconds maximum, which is too little on these boards to get good solder on all the components.  The boards are reflowed in a Vitronics 10 zone convection oven.  The part is Nichicon #2309369R25.  Is anyone familiar with this type of problem, and if so any suggestions will be greatly appreciated!   Are these type of parts prone to failure at high temperatures?

Howard Watson
Manufacturing Engineer
AMETEK/Dixson




------_=_NextPart_001_01C19FBD.63B7CDB0
Content-Type: text/html;
        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff size=2>there
may be no easy solution.&nbsp; if indeed it is a defect associated with a
specific lot, you should be able to come up with a test that would filter out
subsequent parts at receiving inspection.&nbsp; you may also need to create a
specification control drawing to add this requirement to the vendor's
specification.</FONT></SPAN></DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff size=2>this
leaves you with a task of identifying and replacing those parts from the suspect
lot that you have already attached.</FONT></SPAN></DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff size=2>can
you consider a two stage reflow process?&nbsp; the first stage would be your
normal process without the capacitors.&nbsp; the second stage would be a reflow
process in which a low termperature solder is used.</FONT></SPAN></DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff size=2>good
luck.</FONT></SPAN></DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=213000101-18012002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Howard Watson
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, January 17, 2002
  7:09 AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Al
  Electrolytic Capacitors leaking<BR><BR></FONT></DIV><BR><FONT face=sans-serif
  size=2>Thanks Phil. &nbsp;I am wondering if the 218C is too high of a peak
  temperature for these type of components. &nbsp;We use a lot of them, so hand
  soldering is not a popular recommendation here. &nbsp;Can they get damaged
  without any visible defect? &nbsp;I have isolated the problem to a specific
  lot, but then maybe it will show up again in the future. &nbsp;</FONT>
  <BR><BR><FONT face=sans-serif size=2>Howard Watson<BR>Manufacturing
  Engineer<BR>AMETEK/Dixson</FONT> <BR><BR><BR>
  <TABLE width="100%">
    <TBODY>
    <TR vAlign=top>
      <TD>
      <TD><FONT face=sans-serif size=1><B>"Crepeau, Phil"
        &lt;[log in to unmask]&gt;</B></FONT> <BR><FONT face=sans-serif
        size=1>Sent by: TechNet &lt;[log in to unmask]&gt;</FONT>
        <P><FONT face=sans-serif size=1>01/16/02 04:45 PM</FONT> <BR><FONT
        face=sans-serif size=1>Please respond to "TechNet E-Mail Forum."; Please
        respond to "Crepeau, Phil"</FONT> <BR></P>
      <TD><FONT face=Arial size=1>&nbsp; &nbsp; &nbsp; &nbsp; </FONT><BR><FONT
        face=sans-serif size=1>&nbsp; &nbsp; &nbsp; &nbsp; To: &nbsp; &nbsp;
        &nbsp; &nbsp;[log in to unmask]</FONT> <BR><FONT face=sans-serif
        size=1>&nbsp; &nbsp; &nbsp; &nbsp; cc: &nbsp; &nbsp; &nbsp;
        &nbsp;</FONT> <BR><FONT face=sans-serif size=1>&nbsp; &nbsp; &nbsp;
        &nbsp; Subject: &nbsp; &nbsp; &nbsp; &nbsp;Re: [TN] Al Electrolytic
        Capacitors leaking</FONT></TR></TBODY></TABLE><BR><BR><BR><FONT face=Arial
  color=blue size=2>hi,</FONT> <BR><FONT face="Times New Roman"
  size=3>&nbsp;</FONT> <BR><FONT face=Arial color=blue size=2>definitely sounds
  like a job for hand soldering after mass reflow. &nbsp;oh, and definitely,
  these parts are prone to failure at high temperature. &nbsp;isn't
  everything?</FONT> <BR><FONT face="Times New Roman" size=3>&nbsp;</FONT>
  <BR><FONT face=Arial color=blue size=2>phil</FONT> <BR><FONT face=Tahoma
  size=2>-----Original Message-----<B><BR>From:</B> Howard Watson
  [mailto:[log in to unmask]]<B><BR>Sent:</B> Wednesday, January 16, 2002
  12:28 PM<B><BR>To:</B> [log in to unmask]<B><BR>Subject:</B> [TN] Al Electrolytic
  Capacitors leaking<BR></FONT><BR><FONT face=sans-serif
  size=2><BR>Technetters,</FONT><FONT face="Times New Roman" size=3>
  <BR></FONT><FONT face=sans-serif size=2><BR>Please help! &nbsp;I have some
  Aluminum Electrolytic Capacitors that are leaking fluid on the top of the can
  after reflow. &nbsp;My peak temperature on the top of the can is 218C, with a
  time above 183 at 53 seconds, which seem to be appropriate. &nbsp;The
  manufacturer recommends the time above 200C to be 20 seconds maximum, which is
  too little on these boards to get good solder on all the components. &nbsp;The
  boards are reflowed in a Vitronics 10 zone convection oven. &nbsp;The part is
  Nichicon #2309369R25. &nbsp;Is anyone familiar with this type of problem, and
  if so any suggestions will be greatly appreciated! &nbsp; Are these type of
  parts prone to failure at high temperatures?</FONT><FONT
  face="Times New Roman" size=3> <BR></FONT><FONT face=sans-serif
  size=2><BR>Howard Watson<BR>Manufacturing Engineer<BR>AMETEK/Dixson</FONT>
  <BR><BR></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C19FBD.63B7CDB0--

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Date:         Fri, 18 Jan 2002 14:32:01 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: PWB Moisture
X-To:         "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Sounds a bit like he's treating it a bit like a plastic-bodied component to
the old J-STD - bake for 24 hours at 125 deg. Maybe he's hoping he can get
orders for replacement boards every few months once you've finished
oxidising the previous supply.

What does your supplier expect to happen to the boards if they're left
alone, and maybe baked out once just prior to use? What has he packaged the
boards in for you, if they're so prone to moisture absorbtion? Methinks you
need to have a word with him ... and maybe yourself as well (no offense
intended to you)!

Peter




                    "Marsico, James"
                    <James.Marsico@D        To:     [log in to unmask]
                    P.AIL.COM>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet        Aero/ST Group)
                    <[log in to unmask]        Subject:     Re: [TN] PWB Moisture
                    >


                    01/16/02 07:58
                    PM
                    Please respond
                    to "TechNet
                    E-Mail Forum.";
                    Please respond
                    to "Marsico,
                    James"






Just for your information, one of our board suppliers recommends baking for
2 hours for every month of storage (up to 24 hours) at a temperature above
boiling.  They even suggest a vacuum bake, if available!

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

        -----Original Message-----
        From:   <Peter George Duncan> [SMTP:[log in to unmask]]
        Sent:   Tuesday, January 15, 2002 11:44 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] PWB Moisture

        This isn't a very useful response, perhaps, but the question is an
        interesting one. I offer some additional considerations/mind
benders
when
        contemplating the answer to this:

        1) Moisture absorbtion depends on the material(s) the board is made
from,
        and the overall amount of moisture absorbed will be related to the
volume
        of the materials used.
        2) The material volume depends on the board design and is therefore
a bit
        variable.
        3) Opportunity to absorb moisture depends on humidity, temperature
and
        time.
        4) Tracking moisture exposure depends on having an army of
arithmeticians
        or alternatively a tracking system such as our friend Francois
Monette has
        to offer.

        What we need here is some way of determining a Moisture Sensitivity
        Category for the various materials and their combinations, as used
by
        component manufacturers and a means of determining the rate of
moisture
        take-up for any given design - quite a career for somebody.

        On the other hand, you can simply pursuade your fab house to pack
your
        nice, new, dry boards in individual sealed bags with some desiccant
that
        you don't open until the moment you need them (or reseal properly
after
        in-coming inspection) on the line. If the boards have been lying
around for
        a year or so (in their sealed bags), and/or you're in any doubt
about how
        dry the boards are, you can then bake them out for about 2 hours at
90 deg
        C just prior to use. This last has been common practice for many
years,
        although I object on principle to having to do this - one more
thermal
        excursion too many for the board.

        Call me old-fashioned, but why look for ways to make life so
complicated,
        when a little management and control can save a lot of unnecessary
effort
        and cost? (Sorry, Francois!).

        Peter Duncan




                            MAURY HARRIS
                            <MAURY_HARRIS        To:     [log in to unmask]
                            @EFTC.COM>           cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                            Sent by:             Aero/ST Group)
                            TechNet              Subject:     [TN] PWB
Moisture
                            <[log in to unmask]
                            ORG>


                            01/16/02
                            04:05 AM
                            Please
                            respond to
                            "TechNet
                            E-Mail
                            Forum.";
                            Please
                            respond to
                            MAURY HARRIS






        Anyone,

        What is the max absorbed moisture a PWB may have prior to reflow
soldering?
        Also, what IPC or Mil-Spec addresses PWB moisture?

        Thank you,

        Maury Harris
        EFTC-SCO Engineering
        602 282-5179
        [log in to unmask]


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Date:         Fri, 18 Jan 2002 14:43:08 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Rick,

You will, of course require one via per BGA ball, and the only places to
put them are either adjacent to the pad or in the pad itself. There just
ain't no room to do surface fanout to the outside of the foot print.
Conversely, there ain't enough room to put other vias inside the footprint,
other than the ball interconnect vias, 'coz all the space is taken up.

Or am I missing something here?

Peter




                    Rick Howieson
                    <RHowieson@DELTAGRO        To:     [log in to unmask]
                    UPINC.COM>                 cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet           Aero/ST Group)
                    <[log in to unmask]>          Subject:     [TN] BGA/Vias


                    01/17/02 01:41 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to
                    RHowieson






We have a board with a BGA that has quite a few vias on the board located
under the BGA. My question is...Should there be a limit of vias on the
board
located under the BGA? When we need to rework the BGA that area of the
board
seems to "sink" causing more problems, not to mention the integrity of the
vias.
Thanks,
Rick Howieson
Delta Group Electronics, Inc.

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Date:         Fri, 18 Jan 2002 15:01:19 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Methinks it's an Old Husband's tale, unless your pcb vendor in question
produces uncured boards. If the unused pads are free to move about, so is
everything else (though perhaps a little less freely if they're anchored to
other features).

I can understand the argument when it comes to drilling holes. The extra
copper might well hasten the degradation of a drill's sharpness, and blunt
drills cause copper smear which could connect one layer to another layer
when you don't want it to. "If the pads ain't there to start with, there
ain't nought to smear." BUT I think that's penny-pinching by the fab houses
and not in the best interest of boards, particularly class 3 boards, where
the extra support offered by the unused pads is valuable. If nice sharp
drills are used, at the right speed and feed, you should get nice clean
holes, no?

Rgds

Peter




                    "Roger M. Stoops"
                    <rstoops@SPECTRAPRECISI        To:     [log in to unmask]
                    ONDAY.COM>                     cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet               Aero/ST Group)
                    <[log in to unmask]>              Subject:     Re: [TN] Remove unused "dead" pads on
                                                   internal layers

                    01/17/02 03:10 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please respond
                    to rstoops






I have been following this thread with interest.  When I asked a pcb vendor
about having non-functional pads in the inner layers, they said it was not
a good idea, that the unattached pads/lands would move around, or "float,"
and cause potential mfg problems, such as shorts to other copper.
Question:  Is there any truth to this statement, or is this just an old
husband's tale?
TIA,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]


Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511



                    "<Peter
                    George               To:     [log in to unmask]
                    Duncan>"             cc:
                    Sent by:             Subject:     Re: [TN] Remove
unused "dead" pads on internal layers
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/15/02
                    09:09 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    peter.duncan





Hi,

Actually these "unused" pads are replicates of the hole "rules" created for
the surface layers. Most routing packages, or routers, seem to do this by
default for each layer to save manual replication where traces, etc are to
be connected. (At least PADS, Alegro and Mentor do). On the grounds that
it's always easier to destroy than to build, it's easier to delete pad data
than to create it, so it's put in by default as there's a good chance it
will be needed.

I still say you should consider hole barrel strength/support issues before
just deleting them - e.g. they can constrain the "resin recession" and hole
wall pull-away that have been recent threads on this forum. Think of the
"unused" pads as 'wall ties' holding the copper at frequent intervals to
the hole wall. Copper bulging or pull-away in the event of recession or
whatever is reduced.

Peter Duncan




                    Hinners Hans M Civ
                    WRALC/LUGE                To:     [log in to unmask]
                    <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    NS.AF.MIL>                Aero/ST Group)
                    Sent by: TechNet          Subject:     Re: [TN] Remove
unused "dead" pads on
                    <[log in to unmask]>         internal layers


                    01/15/02 09:40 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Hinners
                    Hans M Civ
                    WRALC/LUGE






Hi Patrick,

As others have said, I don't think the class of board matters for "unused"
pads.  It all depends on what your procurement documentation states, are
you
building to drawing or is there a clause that says process improvements
that
do not affect functionality are permissible.

"Are they really unused pads?"

They may be electrically nonfunctioning but they are there for a reason -
better lamination quality (avoiding low pressure areas or excessive prepreg
flow), better hole wall quality, better plating quality (esp. for any
isolated traces), reduced loading of your etch solution or better thermal
loading during assembly.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Friday, January 11, 2002 5:12 PM
To: [log in to unmask]
Subject: [TN] Remove unused "dead" pads on internal layers


Hi TechNetters,

For class 3 boards, is it acceptable to have unused pads removed on
interanal
layers.

Thanks,
Pat

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=========================================================================
Date:         Fri, 18 Jan 2002 15:08:23 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Rick,

Do you happen to have uneven copper balance throughout the thickness of the
board - maybe some heavy-weight copper towards one outside layer and no
counterbalance in the corresponding layer on the other side? Are you using
top and bottom heating? Are you heating too fast - bear in mind how long it
takes to heat the BGA contacts under all that sunshade (aka BGA component
body).

To me, it could be that you're heating too quickly at too-high a
temperature. Reduce the heat, but have a longer soak and see if that helps
keep the board flat.

Peter




                    Rick Howieson
                    <RHowieson@DELTAGRO        To:     [log in to unmask]
                    UPINC.COM>                 cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet           Aero/ST Group)
                    <[log in to unmask]>          Subject:     Re: [TN] BGA/Vias


                    01/17/02 03:40 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to
                    RHowieson






I probably didn't make myself clear. The problem is the board itself
collapses/sinks/"potato chips"...in the area being heated, i.e. BGA
location.
Rick

-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Wednesday, January 16, 2002 11:36 AM
To: [log in to unmask]
Subject: Re: [TN] BGA/Vias


Agree with that. Without board reaching equillibrium (spelling?) top to
bottom, no even solder joint formation (in the case of BGA's - ball
collapse) possible. Uneven "sinking" (collapse) bound to occur but usually
within nanoseconds of others - depending on thermal conditions.

MoonMan

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=========================================================================
Date:         Fri, 18 Jan 2002 15:16:41 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Al Electrolytic Capacitors leaking
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Howard,

From past experience, electrolytics do not like exposure to high
temperatures, as, yes, they do leak. You cannot exceed the manufacturer's
specs with impunity just because your process won't give you the solder
joint quality you're looking for within component spec.

You will need to find another process (hand soldering, wave soldering or
IR) that is a bit kinder to these wee fellows and still give you the joints
you need.

Best rgds

Peter




                    Howard Watson
                    <Howard.Watson@A        To:     [log in to unmask]
                    METEK.COM>              cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet        Aero/ST Group)
                    <[log in to unmask]        Subject:     [TN] Al Electrolytic Capacitors
                    >                       leaking


                    01/17/02 04:27
                    AM
                    Please respond
                    to "TechNet
                    E-Mail Forum.";
                    Please respond
                    to Howard.Watson







Technetters,

Please help!  I have some Aluminum Electrolytic Capacitors that are leaking
fluid on the top of the can after reflow.  My peak temperature on the top
of the can is 218C, with a time above 183 at 53 seconds, which seem to be
appropriate.  The manufacturer recommends the time above 200C to be 20
seconds maximum, which is too little on these boards to get good solder on
all the components.  The boards are reflowed in a Vitronics 10 zone
convection oven.  The part is Nichicon #2309369R25.  Is anyone familiar
with this type of problem, and if so any suggestions will be greatly
appreciated!   Are these type of parts prone to failure at high
temperatures?

Howard Watson
Manufacturing Engineer
AMETEK/Dixson



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Date:         Fri, 18 Jan 2002 10:39:02 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Genny Gibbard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Sorry, must disagree with you, on this one as both ex-fab and
ex-assembler guy, or, at least, qualify your remarks.

In particular, it is essential when the inner layers have more than 35
um copper to have "dummy pads" or when there may be high voltage or high
impedance tracks in proximity to the hole barrels, even respecting the
design rules. Furthermore, although dummy pads take up inner layer real
estate there is no risk, with most CAD systems, of a track-to-pad
violation. With the tolerance of positioning the inner layer and the
hole drilling position, plus the ingress of metallising solution into
the surface micrometres of the hole barrel, this cannot always be
guaranteed without the pads. Finally, my practical experience has shown
that the "loose" lamination without pads is much more prone to produce
conductive anodic filaments than the "tight" build-up with pads.

My recommendation each time is to have inner layer "dummy pads". Their
diameter should be such that, with the accumulation of tolerances, the
"crown" will always be intact after drilling. Under any of the
circumstances outlined at the beginning of the last paragraph, this
recommendation becomes quasi-mandatory.

Finally, for your thoughts: I know of no CAD autorouter or design rules
system that modifies the design rules so that the spacing from the
nominal hole barrel to a track takes into account the mechanical
tolerances of the hole diameter, position and layer position. This means
that the general spacing rules must be set more generous than would
otherwise be necessary, resulting in more practical loss of real estate
than with dummy pads. The only way round this dilemma would be to do the
autorouting with copper inner pads and then to remove them subsequently.

Brian

Genny Gibbard wrote:
>
> Fascinating stuff.  We had a board vendor at one point that wanted us to put
> pads on all the layers of a PTH.  I thought the reason given was to help the
> hole plating process.  Our standard block for multilayer boards
> automatically puts pads on all layers and if not a ground via, it also
> clears the ground plane away around it on all layers.  I've never heard of
> any of the problems mentioned over the last few days.
> It's kind of funny, the amount of things I hear about on this forum that
> question things or dispute things that we've never really paid much
> attention to in our own layouts makes me fascinated that this co. has gotten
> as much product out the door working as it has over the last dozen years.  I
> guess Murphy's law isn't always on duty.
>
> -----Original Message-----
> From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
> Sent: January 17, 2002 4:03 PM
> To: [log in to unmask]
> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>
> Hi All,
>
> Now that I think of it we always stuck our nonfunctional pads in places we
> didn't have to drill.  But I'm on the list to learn - thanks to Warren,
> Werner.
>
> Roger, this sounds very weird - granted I've only been in the industry since
> '98.  There are very good reasons to use nonfunctional pads.  Now I know not
> to use them in PTHs (& Route areas I imagine).  I wonder if people are
> making this more difficult than it has to be - we've always used decent
> sized dots so they wouldn't pop off of the core from rough handling or
> processing.  We kept them far enough away from traces to avoid etch problems
> - we're not talking about something that has to have a critical feature
> size.  They may have been struggling with metallic contamination but
> non-functional pads should be a fixable problem - no?
>
> If they were truly having  problems with non-functional pads then they must
> have had the same trouble with the functional pads?  Houston . . . . we've
> had a problem.
>
> Hans
>
> Integrity First  -  Service Before Self  -  Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax:   (478) 926 - 4911
> DSN Prefix: 468
>
> -----Original Message-----
> From: Roger M. Stoops [mailto:[log in to unmask]]
> Sent: Wednesday, January 16, 2002 2:10 PM
> To: [log in to unmask]
> Subject: Re: [TN] Remove unused "dead" pads on internal layers
>
> I have been following this thread with interest.  When I asked a pcb vendor
> about having non-functional pads in the inner layers, they said it was not
> a good idea, that the unattached pads/lands would move around, or "float,"
> and cause potential mfg problems, such as shorts to other copper.
> Question:  Is there any truth to this statement, or is this just an old
> husband's tale?
> TIA,
> Roger M. Stoops, C.I.D., PCB Designer
> [log in to unmask]
>
> Trimble
> Engineering and Construction Division
> 5475 Kellenburger Rd.
> Dayton, OH 45424-1099 USA
> Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
> Fax: +01 937.233.7511
>
>                     "<Peter
>                     George               To:     [log in to unmask]
>                     Duncan>"             cc:
>                     Sent by:             Subject:     Re: [TN] Remove unused
> "dead" pads on internal layers
>                     TechNet
>                     <[log in to unmask]
>                     ORG>
>
>                     01/15/02
>                     09:09 PM
>                     Please
>                     respond to
>                     "TechNet
>                     E-Mail
>                     Forum.";
>                     Please
>                     respond to
>                     peter.duncan
>
> Hi,
>
> Actually these "unused" pads are replicates of the hole "rules" created for
> the surface layers. Most routing packages, or routers, seem to do this by
> default for each layer to save manual replication where traces, etc are to
> be connected. (At least PADS, Alegro and Mentor do). On the grounds that
> it's always easier to destroy than to build, it's easier to delete pad data
> than to create it, so it's put in by default as there's a good chance it
> will be needed.
>
> I still say you should consider hole barrel strength/support issues before
> just deleting them - e.g. they can constrain the "resin recession" and hole
> wall pull-away that have been recent threads on this forum. Think of the
> "unused" pads as 'wall ties' holding the copper at frequent intervals to
> the hole wall. Copper bulging or pull-away in the event of recession or
> whatever is reduced.
>
> Peter Duncan
>
>                     Hinners Hans M Civ
>                     WRALC/LUGE                To:     [log in to unmask]
>                     <Hans.Hinners@ROBI        cc:     (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
>                     NS.AF.MIL>                Aero/ST Group)
>                     Sent by: TechNet          Subject:     Re: [TN] Remove
> unused "dead" pads on
>                     <[log in to unmask]>         internal layers
>
>                     01/15/02 09:40 PM
>                     Please respond to
>                     "TechNet E-Mail
>                     Forum."; Please
>                     respond to Hinners
>                     Hans M Civ
>                     WRALC/LUGE
>
> Hi Patrick,
>
> As others have said, I don't think the class of board matters for "unused"
> pads.  It all depends on what your procurement documentation states, are
> you
> building to drawing or is there a clause that says process improvements
> that
> do not affect functionality are permissible.
>
> "Are they really unused pads?"
>
> They may be electrically nonfunctioning but they are there for a reason -
> better lamination quality (avoiding low pressure areas or excessive prepreg
> flow), better hole wall quality, better plating quality (esp. for any
> isolated traces), reduced loading of your etch solution or better thermal
> loading during assembly.
>
> Hans
>
> Integrity First  -  Service Before Self  -  Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax:   (478) 926 - 4911
> DSN Prefix: 468
>
> -----Original Message-----
> From: Patrick Lam [mailto:[log in to unmask]]
> Sent: Friday, January 11, 2002 5:12 PM
> To: [log in to unmask]
> Subject: [TN] Remove unused "dead" pads on internal layers
>
> Hi TechNetters,
>
> For class 3 boards, is it acceptable to have unused pads removed on
> interanal
> layers.
>
> Thanks,
> Pat
>
> ----------------------------------------------------------------------------
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Date:         Fri, 18 Jan 2002 17:02:55 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Charles McMahon <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

I would still like more feedback/opinion concerning the mechanical function
of these 'non-functional' pads. I am very much of the opinion that they act
as 'wall ties' to better secure the plated barrels to the wall of the
holes, thus reducing the tendency or severity of deformation through
pull-away or resin recession, especially during temperature cycling and
vibration. For PTH components, I know that the extra keying afforded by
these pads reduces the incidence of barrels being ripped out during rework
by ham-fisted operators.

Are the stated fab problems actually of major significance or is a mole
hill becoming a mountain under this magnifying glass of a forum?

Peter




                    Charles
                    McMahon               To:     [log in to unmask]
                    <cmcmahon@EART        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    HLINK.NET>            Aero/ST Group)
                    Sent by:              Subject:     Re: [TN] Remove unused "dead" pads on
                    TechNet               internal layers
                    <[log in to unmask]
                    RG>


                    01/18/02 08:47
                    AM
                    Please respond
                    to "TechNet
                    E-Mail
                    Forum.";
                    Please respond
                    to Charles
                    McMahon






Ms. Bergman is correct.
The more features to deal with, the more opportunity for defects.
It only makes sense to eliminate non-functional components within a design.
This requires the end user to consider advising the designer to perform the
function of optimization.
I have found they will not do so except under extreme social pressure.
Was this type of scenario not the precursor to the need for DFM?

Lastly, as a provider of pcb's, I would be less inclined to have the FAB
shop make modifcations of this type to the data as a matter of process.
I would encourage instead that the customer have their designer do these
optimizations to avoid any mis-understandings.
The goal of course is to do it right the first time to increase yields and
lower costs to the customer.

Sincerely,
Charlie McMahon



Kathy Bergman wrote:
     I cannot resist this one....


     From a board manufacturer's point of view,  inner layer and outer
     layer pad concerns are completely different.


     The process of  imaging  and etching an inner layer involves: the
     photoresist being applied to an undrilled core material, then the
     exposing and developing of it. This positive image is then put through
     an etcher and this is the inner layer image, without holes. Then the
     cores are laminated and the board is drilled. If a board has 4,000
     holes, and 50 traces on an inner layer signal layer, I would rather
     deal with 50 traces only, than 50 traces and 4,000+ pads. When the
     board is completed, a hole with no pads on the innerlayers would be no
     different (or have no less integrity) than a hole on a non-multilayer
     board. If the processes are under control, there should be no problem
     with the holes. The material used in making a double sided board is
     manufactured in the same was as a multilayer board is built, with
     prepreg and foil (basically).


     As far as the outer layers go, small (< .150, say) non plated holes
     with pads that are intentional, must be processed differently (an
     extra step) than non plated holes without pads. AND, if you have a
     large non plated hole with small pad (<.015 per side over hole size),
     the pads can randomly pop off, for various reasons.


     I think the general opinion of most fab houses is this: Data comes in
     from so many different systems, it is hard to know if there were
     restrictions on the data output, or if many of the situations are
     intentional. If the fab house has a strong front end system all issues
     are addressed, and the boards are built to the customer's
     requirements. I can say that from a yeild point of view, though, most
     all builders of PCB's would rather delete unused pads on inner layers,
     and have no pads on outer layer Npth holes.


     Regards,
     K Bergman


     Genny Gibbard wrote:


          Fascinating stuff.  We had a board vendor at one point that
          wanted us to put
          pads on all the layers of a PTH.  I thought the reason given was
          to help the
          hole plating process.  Our standard block for multilayer boards
          automatically puts pads on all layers and if not a ground via, it
          also
          clears the ground plane away around it on all layers.  I've never
          heard of
          any of the problems mentioned over the last few days.
          It's kind of funny, the amount of things I hear about on this
          forum that
          question things or dispute things that we've never really paid
          much
          attention to in our own layouts makes me fascinated that this co.
          has gotten
          as much product out the door working as it has over the last
          dozen years.  I
          guess Murphy's law isn't always on duty.


          -----Original Message-----
          From: Hinners Hans M Civ WRALC/LUGE [
          mailto:[log in to unmask] ]
          Sent: January 17, 2002 4:03 PM
          To: [log in to unmask]
          Subject: Re: [TN] Remove unused "dead" pads on internal layers


          Hi All,


          Now that I think of it we always stuck our nonfunctional pads in
          places we
          didn't have to drill.  But I'm on the list to learn - thanks to
          Warren,
          Werner.


          Roger, this sounds very weird - granted I've only been in the
          industry since
          '98.  There are very good reasons to use nonfunctional pads.  Now
          I know not
          to use them in PTHs (& Route areas I imagine).  I wonder if
          people are
          making this more difficult than it has to be - we've always used
          decent
          sized dots so they wouldn't pop off of the core from rough
          handling or
          processing.  We kept them far enough away from traces to avoid
          etch problems
          - we're not talking about something that has to have a critical
          feature
          size.  They may have been struggling with metallic contamination
          but
          non-functional pads should be a fixable problem - no?


          If they were truly having  problems with non-functional pads then
          they must
          have had the same trouble with the functional pads?  Houston . .
          . . we've
          had a problem.


          Hans


          Integrity First  -  Service Before Self  -  Excellence in All We
          Do
          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          Hans M. Hinners
          Electronics Engineer
          Warner Robins - Air Logistics Center (WR-ALC/LUGE)
          226 Cochran Street
          Robins AFB GA 31098-1622


          mailto:[log in to unmask]


          Com: (478) 926 - 5224
          Fax:   (478) 926 - 4911
          DSN Prefix: 468


          -----Original Message-----
          From: Roger M. Stoops [mailto:[log in to unmask] ]
          Sent: Wednesday, January 16, 2002 2:10 PM
          To: [log in to unmask]
          Subject: Re: [TN] Remove unused "dead" pads on internal layers


          I have been following this thread with interest.  When I asked a
          pcb vendor
          about having non-functional pads in the inner layers, they said
          it was not
          a good idea, that the unattached pads/lands would move around, or
          "float,"
          and cause potential mfg problems, such as shorts to other copper.

          Question:  Is there any truth to this statement, or is this just
          an old
          husband's tale?
          TIA,
          Roger M. Stoops, C.I.D., PCB Designer
          [log in to unmask]


          Trimble
          Engineering and Construction Division
          5475 Kellenburger Rd.
          Dayton, OH 45424-1099 USA
          Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
          Fax: +01 937.233.7511


                              "<Peter
                              George               To:     [log in to unmask]
                              Duncan>"             cc:
                              Sent by:             Subject:     Re: [TN]
          Remove unused
          "dead" pads on internal layers
                              TechNet
                              <[log in to unmask]
                              ORG>


                              01/15/02
                              09:09 PM
                              Please
                              respond to
                              "TechNet
                              E-Mail
                              Forum.";
                              Please
                              respond to
                              peter.duncan


          Hi,


          Actually these "unused" pads are replicates of the hole "rules"
          created for
          the surface layers. Most routing packages, or routers, seem to do
          this by
          default for each layer to save manual replication where traces,
          etc are to
          be connected. (At least PADS, Alegro and Mentor do). On the
          grounds that
          it's always easier to destroy than to build, it's easier to
          delete pad data
          than to create it, so it's put in by default as there's a good
          chance it
          will be needed.


          I still say you should consider hole barrel strength/support
          issues before
          just deleting them - e.g. they can constrain the "resin
          recession" and hole
          wall pull-away that have been recent threads on this forum. Think
          of the
          "unused" pads as 'wall ties' holding the copper at frequent
          intervals to
          the hole wall. Copper bulging or pull-away in the event of
          recession or
          whatever is reduced.


          Peter Duncan


                              Hinners Hans M Civ
                              WRALC/LUGE                To:
          [log in to unmask]
                              <Hans.Hinners@ROBI        cc:     (bcc:
          DUNCAN
          Peter/Asst Prin Engr/ST
                              NS.AF.MIL>                Aero/ST Group)
                              Sent by: TechNet          Subject:     Re:
          [TN] Remove
          unused "dead" pads on
                              <[log in to unmask]>         internal layers


                              01/15/02 09:40 PM
                              Please respond to
                              "TechNet E-Mail
                              Forum."; Please
                              respond to Hinners
                              Hans M Civ
                              WRALC/LUGE


          Hi Patrick,


          As others have said, I don't think the class of board matters for
          "unused"
          pads.  It all depends on what your procurement documentation
          states, are
          you
          building to drawing or is there a clause that says process
          improvements
          that
          do not affect functionality are permissible.


          "Are they really unused pads?"


          They may be electrically nonfunctioning but they are there for a
          reason -
          better lamination quality (avoiding low pressure areas or
          excessive prepreg
          flow), better hole wall quality, better plating quality (esp. for
          any
          isolated traces), reduced loading of your etch solution or better
          thermal
          loading during assembly.


          Hans


          Integrity First  -  Service Before Self  -  Excellence in All We
          Do
          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          Hans M. Hinners
          Electronics Engineer
          Warner Robins - Air Logistics Center (WR-ALC/LUGE)
          226 Cochran Street
          Robins AFB GA 31098-1622


          mailto:[log in to unmask]


          Com: (478) 926 - 5224
          Fax:   (478) 926 - 4911
          DSN Prefix: 468


          -----Original Message-----
          From: Patrick Lam [mailto:[log in to unmask] ]
          Sent: Friday, January 11, 2002 5:12 PM
          To: [log in to unmask]
          Subject: [TN] Remove unused "dead" pads on internal layers


          Hi TechNetters,


          For class 3 boards, is it acceptable to have unused pads removed
          on
          interanal
          layers.


          Thanks,
          Pat


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Date:         Fri, 18 Jan 2002 04:16:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         "<Peter George Duncan>" <[log in to unmask]>

I vote for mole hill becoming mountain with cave in it for MoonMan (Werner
now calls me MoonCaveMan). I think this outlaw bit has done got outa hand.

Sure a lot of newer (to me) respondants with some good opinions. Mine
probably is not so good but never cared one way or another about these pads.
Mostly eliminated them using CAD or CAM. I do like that plating "anchor"
thing (just seems cool but for what) though I've never seen failures without
them (what's to fail), except when processes mis-managed, using test coupon
x-sectional analysis, as received or after thermal stress, or when
destroying perfectly good boards, or not.

As fars as pads moving, they sure do during relamination and a lot too.
However, so does everything else on the inners. I'm still a pad only outer
and non-functional inner pad removal guy. Just call me old fashioned or -

MoonCaveMan

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Date:         Fri, 18 Jan 2002 06:48:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Re: D-Pak 2nd side reflow issues
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

I agree with Dave, just want to add one: check the conveyor for vibration.

regards

Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215

>>> [log in to unmask] 01/17/02 10:02PM >>>
Hummm, surprising.

DPAK are fairly light [~ 0.300 gm] and have a relatively huge solderable
surface [~ 47mm^2/0.07in^2].  This weight to solderable area 6.3mgm/mm^2
[4.1gm/in^2] is well within both
* "Zarro Limit" of 30 gm/in^2.
* "Willis Limit" of 44gm/in^2.

From this perspective, DPAK numbers are similar to a mini-MELF and to a
SOIC16.

Are you soldering the tab?  If so, how about:
* Loctite 3609 or equivalent
* Conveying the board differently
* Turning-down your bottom-side fans

Dave Fish


----- Original Message -----
From: "Kevin M. Bair" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, January 17, 2002 6:18 AM
Subject: [TN] D-Pak 2nd side reflow issues


> We are having problems with bottom side d-paks falling off when the top
> side of the board is being reflowed.  Has anyone had this problem, and =
if
> so, what have you done to correct it?
>
> Thanks for your help,
>
> Kevin Bair
> Assembly Engineer
> Teradyne, Inc.
>
> -------------------------------------------------------------------------=
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Date:         Fri, 18 Jan 2002 10:56:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Safavi-Bayat Shahed <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Safavi-Bayat Shahed <[log in to unmask]>
Subject:      Net list Converter
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi All
I would like to know if there is a tool out there that can convert a
different format
of net list into another one.
More over, I like to know if anybody can tell me how to convert a net list
generated
by View Logic into OrCad net list(*.MNL). Has anybody done this before?

Thank You,


Shahed

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Date:         Fri, 18 Jan 2002 11:11:00 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Charlie,
The optimuization needs to be done from a systems point-of-view, not just a
pcb manufacture point-of-view. Just because some internal pads are
electricelly non-functional does not make them non-functional in other
respects.
Hi Peter,
You are right on the money.
Hi MoonCaveMan,
You are too categorical.
IMHO:
1. 'Non-functional' lands can make pcb manufacture slightly more
difficult--depending on complexity and process controls;
2. 'Non-functional' lands do provide a 'wall achor' [as Peter terms them]
reducing the possibility of hole wall separation and innerlayer separation
after solder temperature excursions;
3. 'Non-functional' lands for many less complex PCBs make no measurable
reliability impact; for thicker MLBs with larger diameter holes they do.
Back to skiing,
Werner Engelmaier

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Date:         Fri, 18 Jan 2002 11:20:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tempea, Ioan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: Net list Converter
MIME-Version: 1.0
Content-Type: text/plain

Hi,

check this out: http://www.edaxchange.com/

Regards,
Ioan

> -----Original Message-----
> From: Safavi-Bayat Shahed [SMTP:[log in to unmask]]
> Sent: Friday, January 18, 2002 10:57 AM
> To:   [log in to unmask]
> Subject:      [TN] Net list Converter
>
> Hi All
> I would like to know if there is a tool out there that can convert a
> different format
> of net list into another one.
> More over, I like to know if anybody can tell me how to convert a net list
> generated
> by View Logic into OrCad net list(*.MNL). Has anybody done this before?
>
> Thank You,
>
>
> Shahed
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> the BODY (NOT the subject field): SIGNOFF Technet
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------

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=========================================================================
Date:         Fri, 18 Jan 2002 11:03:45 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ron Olinyk <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ron Olinyk <[log in to unmask]>
Subject:      Re: Net list Converter
X-To:         Safavi-Bayat Shahed <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

You can try the Conversion Factors people http://www.confac.com/ -they have
translators for different Cad packages, PCB, scm and netlist.
Cadence has a free ViewDraw reader for Capture -not sure if it will gen a
netlist though -worth a try perhaps.
Ron O.

At 10:56 AM 1/18/02 -0500, you wrote:
>Hi All
>I would like to know if there is a tool out there that can convert a
>different format
>of net list into another one.
>More over, I like to know if anybody can tell me how to convert a net list
>generated
>by View Logic into OrCad net list(*.MNL). Has anybody done this before?
>
>Thank You,
>
>
>Shahed
>
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Date:         Fri, 18 Jan 2002 11:24:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Hargreaves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Hargreaves <[log in to unmask]>
Subject:      IPC-4101/23 vs /24
MIME-Version: 1.0
Content-Type: text/plain

Hi All,
Does type GF/GFG material (IPC-4101 / 24) meet the requirements of type GH
material (IPC-4101 / 23) ?

Our customer is requesting type GH.  We stock type GF/GFG and would like to
use it instead.

(I hope I've phrased this properly.  4101 is a little over my head)

Many Thanks,
Mark Hargreaves

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Date:         Fri, 18 Jan 2002 11:24:16 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              tony steinke <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         tony steinke <[log in to unmask]>
Subject:      via laser drilling
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Greetings,
Does any one have experience or knowledge of a company that provides
laser drilling  of blind vias as a subcontract service. Please contact =
me
offline. Thanks ahead of time.
[log in to unmask]

------=_NextPart_000_0021_01C1A012.A9F2C640
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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#fff8e0>
<DIV><FONT face=3DArial size=3D2>Greetings,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Does any one have experience or =
knowledge of a=20
company that provides</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>laser drilling&nbsp; of blind vias as a =
subcontract=20
service. Please contact me</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>offline. Thanks ahead of =
time.</FONT></DIV>
<DIV><FONT face=3DArial=20
size=3D2>[log in to unmask]</FONT>&nbsp;</DIV></BODY></HTML>

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Date:         Fri, 18 Jan 2002 10:35:34 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Werner,

Before you hit the slopes - two last questions.

In point #2, do you mean exactly what is written: that the non-functional
pads reduce the possibility of hole wall separation?  Or do you mean that
the presence of additional anchors reduces the propagation or magnitude of
separation when it occurs?

How does the presence of additional pads reduce the possibility of inner
layer separation?  My understanding is that the adhesion of b-stage to
c-stage is greater than the adhesion of polymer to copper.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Werner Engelmaier
Sent: Friday, January 18, 2002 10:11 AM
To: [log in to unmask]
Subject: Re: [TN] Remove unused "dead" pads on internal layers


snip----------
2. 'Non-functional' lands do provide a 'wall achor' [as Peter terms them]
reducing the possibility of hole wall separation and innerlayer separation
after solder temperature excursions;
snip--------

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Date:         Fri, 18 Jan 2002 11:41:41 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Mechanical Specifications for VME boards...
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YAY! It's Friday!!

Does anybody know where I can get VME board mechanical spec's (dimensions,
etc.)?

Thanks!

-Steve Gregory-


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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>YAY! It's Friday!!
<BR>
<BR>Does anybody know where I can get VME board mechanical spec's (dimensions, etc.)?
<BR>
<BR>Thanks!
<BR>
<BR>-Steve Gregory-
<BR></FONT></HTML>

--part1_24.1f779dcb.2979aa45_boundary--

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Date:         Fri, 18 Jan 2002 08:42:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Popielarski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Popielarski <[log in to unmask]>
Subject:      Re: Scrap solder paste
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Hi all,

You might want to contact Patricia Mealey with Alpha-Fry Technology at=20
800-742-1074 or   [log in to unmask] . They buy back =
material at fair market value based on volume. Also, she's very familiar =
with EPA manifesting regulations.=20


Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618

Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578

WWW.QTA.NET

------=_NextPart_000_002A_01C19FFC.0710C8C0
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>You might want to contact Patricia =
Mealey with=20
Alpha-Fry Technology at </FONT></DIV>
<DIV><FONT face=3DArial size=3D2>800-742-1074 or&nbsp;&nbsp; <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]
ookson.com</A>&nbsp;.=20
They buy back material at fair market value based on volume. Also, she's =
very=20
familiar with EPA manifesting regulations. </FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>

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Date:         Fri, 18 Jan 2002 11:39:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Genny Gibbard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Silver component contamination
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Happy Friday! (tappity, tappity - doing the Friday dance)
We have ceramic resonators with silver coating on several products.  We
started handling those OEM boards with gloves during our test processes
because the customer expressed concern with skin oil contamination.
At times these components have been marked in house, for various reasons,
with a standard sharpie marker.  In fact, at an early point in the
production schedule, the CM we were using at the time was marking them on
their own, because the resonators are so close in size they were having
trouble telling them apart and getting them installed in the right locations
(due to tight time requirements, we got a shipment of bulk parts that were
being placed by hand).  The marks looked like they were marker applied and
used a variety of dot and line patterns in various colours.  We have never
noticed any harmful effect on their response, although build quantities were
low.
Now someone on our production floor is asking whether the ink may be a
contamination that we should avoid.  We have easily cleaned this marker off
of other surfaces with board wash.  They wanted to know if they should clean
the components with board wash.  I think that if the marker is already on
there and a contaminant, don't compound it by rubbing board wash on it.
From what I can tell, from the MSDS on the marker website, the ink is
primarily propanol/butanol/alcohol based.  The board wash is alcohol based.
Chemistry is my weak subject.  Is alcohol - related substances on silver
coated components a concern?

Genny Gibbard (mailto:[log in to unmask])
Product Transition and Support
Wavecom Electronics Inc.
202 Cardinal Crescent
Saskatoon, SK, Canada
ph:     (306) 955-7075 ext. 229
fax:    (306)384-0086

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Date:         Fri, 18 Jan 2002 13:05:10 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lou Hart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Re: Silver component contamination
X-To:         Genny Gibbard <[log in to unmask]>

Genny, FYI, Mostek (if anyone remembers them) years ago had a problem that
arose from marking bad dice on wafers with a red marker.  The ink contained
chlorine, some of which migrated to good dice, leading to corrosion of the
aluminium metallization while in operation.  Lou Hart

-----Original Message-----
From:   Genny Gibbard [SMTP:[log in to unmask]]
Sent:   Friday, January 18, 2002 12:39 PM
To:     [log in to unmask]
Subject:        [TN] Silver component contamination

Happy Friday! (tappity, tappity - doing the Friday dance)
We have ceramic resonators with silver coating on several products.  We
started handling those OEM boards with gloves during our test processes
because the customer expressed concern with skin oil contamination.
At times these components have been marked in house, for various reasons,
with a standard sharpie marker.  In fact, at an early point in the
production schedule, the CM we were using at the time was marking them on
their own, because the resonators are so close in size they were having
trouble telling them apart and getting them installed in the right
locations
(due to tight time requirements, we got a shipment of bulk parts that were
being placed by hand).  The marks looked like they were marker applied and
used a variety of dot and line patterns in various colours.  We have never
noticed any harmful effect on their response, although build quantities
were
low.
Now someone on our production floor is asking whether the ink may be a
contamination that we should avoid.  We have easily cleaned this marker off
of other surfaces with board wash.  They wanted to know if they should
clean
the components with board wash.  I think that if the marker is already on
there and a contaminant, don't compound it by rubbing board wash on it.
>From what I can tell, from the MSDS on the marker website, the ink is
primarily propanol/butanol/alcohol based.  The board wash is alcohol based.
Chemistry is my weak subject.  Is alcohol - related substances on silver
coated components a concern?

Genny Gibbard (mailto:[log in to unmask])
Product Transition and Support
Wavecom Electronics Inc.
202 Cardinal Crescent
Saskatoon, SK, Canada
ph:     (306) 955-7075 ext. 229
fax:    (306)384-0086

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Date:         Fri, 18 Jan 2002 11:30:09 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Via Hole Size for 062 boards
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

What would be the standard via hole size for a 4-6 layer/0.062" board? This
would be without pushing the technology to the edge or incurring on extra
cost, just the industry standard.

Thanks for your comments

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Fri, 18 Jan 2002 14:33:42 -0400
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              John Maxwell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         John Maxwell <[log in to unmask]>
Subject:      Re: Silver component contamination
X-To:         Lou Hart <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Actually most aluminium corrosion on IC die is due to excessive phosphorus
in the glass passivation/getter layer that protects surface metallization
from damage. Chlorine has a nasty habit of being mobile and causing
threshold voltage shift on individual transistors on the chip typically
causing long term reliability problems. All very ugly.

John Maxwell

At 01:05 PM 1/18/02 -0500, you wrote:
>Genny, FYI, Mostek (if anyone remembers them) years ago had a problem that
>arose from marking bad dice on wafers with a red marker.  The ink contained
>chlorine, some of which migrated to good dice, leading to corrosion of the
>aluminium metallization while in operation.  Lou Hart
>
>-----Original Message-----
>From:   Genny Gibbard [SMTP:[log in to unmask]]
>Sent:   Friday, January 18, 2002 12:39 PM
>To:     [log in to unmask]
>Subject:        [TN] Silver component contamination
>
>Happy Friday! (tappity, tappity - doing the Friday dance)
>We have ceramic resonators with silver coating on several products.  We
>started handling those OEM boards with gloves during our test processes
>because the customer expressed concern with skin oil contamination.
>At times these components have been marked in house, for various reasons,
>with a standard sharpie marker.  In fact, at an early point in the
>production schedule, the CM we were using at the time was marking them on
>their own, because the resonators are so close in size they were having
>trouble telling them apart and getting them installed in the right
>locations
>(due to tight time requirements, we got a shipment of bulk parts that were
>being placed by hand).  The marks looked like they were marker applied and
>used a variety of dot and line patterns in various colours.  We have never
>noticed any harmful effect on their response, although build quantities
>were
>low.
>Now someone on our production floor is asking whether the ink may be a
>contamination that we should avoid.  We have easily cleaned this marker off
>of other surfaces with board wash.  They wanted to know if they should
>clean
>the components with board wash.  I think that if the marker is already on
>there and a contaminant, don't compound it by rubbing board wash on it.
> >From what I can tell, from the MSDS on the marker website, the ink is
>primarily propanol/butanol/alcohol based.  The board wash is alcohol based.
>Chemistry is my weak subject.  Is alcohol - related substances on silver
>coated components a concern?
>
>Genny Gibbard (mailto:[log in to unmask])
>Product Transition and Support
>Wavecom Electronics Inc.
>202 Cardinal Crescent
>Saskatoon, SK, Canada
>ph:     (306) 955-7075 ext. 229
>fax:    (306)384-0086
>
>------------------------------------------------------------------------
>---------
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>To unsubscribe, send a message to [log in to unmask] with following text in
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>[log in to unmask]: SET Technet Digest
>Search previous postings at: www.ipc.org > On-Line Resources & Databases >
>E-mail Archives
>Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
>additional
>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>------------------------------------------------------------------------
>---------
>
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Date:         Fri, 18 Jan 2002 13:39:30 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McMullen, Kerry" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McMullen, Kerry" <[log in to unmask]>
Subject:      Re: Via Hole Size for 062 boards
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

.012" +0.000 / -.012" finished would not be a cost adder.  Aspect Ratio
would only be about 4.5.

-----Original Message-----
From: Jorge Rodriguez [mailto:[log in to unmask]]
Sent: Friday, January 18, 2002 1:30 PM
To: [log in to unmask]
Subject: [TN] Via Hole Size for 062 boards


What would be the standard via hole size for a 4-6 layer/0.062" board? This
would be without pushing the technology to the edge or incurring on extra
cost, just the industry standard.

Thanks for your comments

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Fri, 18 Jan 2002 13:55:07 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Michael Kuczynski <[log in to unmask]>
Subject:      Re: Via Hole Size for 062 boards
X-To:         [log in to unmask]
MIME-Version: 1.0
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This is a multipart message in MIME format.
--=_alternative 0067C7FE85256B45_=
Content-Type: text/plain; charset="us-ascii"

.013 finished drill - .032 outer pads

Michael Kuczynski                            Sr. Designer/Librarian
Philips Components                           LCoS Project
345 Scarborough Rd.                       1-914-945-6346 (Ph)
Briarcliff Manor, NY 10510-2099       1-914-945-6798 (Fax)
[log in to unmask]
--=_alternative 0067C7FE85256B45_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">.013 finished drill - .032 outer pads<br>
<br>
Michael Kuczynski &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Sr. Designer/Librarian<br>
Philips Components &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; LCoS Project<br>
345 Scarborough Rd. &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 1-914-945-6346 (Ph) <br>
Briarcliff Manor, NY 10510-2099 &nbsp; &nbsp; &nbsp; 1-914-945-6798 (Fax)<br>
[log in to unmask]</font>
--=_alternative 0067C7FE85256B45_=--

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Date:         Fri, 18 Jan 2002 14:08:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Apex 2000 - Lunch on Thursday
Mime-Version: 1.0
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Hi TechNet
Well - not much reply to my question about TechNetter's going to Apex.  I =
guess SteveZeva is the big draw!!!  :-)

In any case - Ed Popielarski and I are meeting for lunch on Thursday, any =
TechNet folks out there are welcome to join us.  We are meeting (for the =
first time in person) at the IPC booth (#5749)  at 12:00.  Anyone =
interested in coming along is welcome to make an appearance there and join =
us.

Moonman - leave the cave and come on out for some fresh air...

Hope to meet some of you folks.


regards

Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215

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Date:         Fri, 18 Jan 2002 13:50:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Keach Sasamori <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Keach Sasamori <[log in to unmask]>
Subject:      IPC Listserv forums will be down Wed Jan 23
X-To:         [log in to unmask], [log in to unmask], [log in to unmask],
              [log in to unmask], [log in to unmask]
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IPC will be transferring all forums on our Listserv server to a faster, =
more powerful machine on Wednesday January 23rd. The process should take a =
few hours. Any mail sent to any of the IPC forums will eventually make =
their way to the new Listserv and be posted. You may receive some warning =
messages that mail has been delayed, but they will be posted eventually.

After the transition, all settings and URLs will remain the same, just =
faster hardware.

Thank you for your cooperation.

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Date:         Fri, 18 Jan 2002 12:22:23 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject:      Re: Via Hole Size for 062 boards
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Typically it would be  a  .013 dia finish hole, Manufacture drill would probably be .018 dia.
So if you add .014 too .018  you get an .032 dia pad.  This you then adjust depending
on trace width technology and many other factors, like via pitch, gnd and power plane webbing
between vias.  .032 minus .050 = .018.  If your anti pad is plus 5 or 6 mils per side then
your left with .008 and .006 of copper webbing on your planes.

hope this helps

Greg Scott
Cray Inc.


Jorge Rodriguez wrote:

> What would be the standard via hole size for a 4-6 layer/0.062" board? This
> would be without pushing the technology to the edge or incurring on extra
> cost, just the industry standard.
>
> Thanks for your comments
>
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> 615 South River Drive
> Tempe, AZ 85281
> Phone: (480) 968-6790 X 4258
> Fax: (480) 829-4000
> E-mail: [log in to unmask]
>
> ---------------------------------------------------------------------------------
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------

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Date:         Fri, 18 Jan 2002 15:29:38 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Apex 2000 - Lunch on Thursday
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

(...Blushing...) didn't know I was so popular...hehehe. Wish I could come out
this year, but it's only fair to take turns...

Seeing how today is Friday, I thought I would share this true story that
comes from Michigan, up where Earl is. They don't mention any names in the
story but I just wonder if Earl had anything to do with this? Remember he
said he likes things that go BOOM!

-Steve Gregory-

Goodbye, Lincoln Navigator

This is from a radio program, a true report of an
incident in Michigan: A guy buys a brand new Lincoln
Navigator for $42,500 and has $560 monthly payments.
He and a friend go duck hunting in winter, and of
course all the lakes are frozen.

These two guys go out on the lake with the guns, the
dog, and of course the new vehicle. They drive out
onto the lake ice and get ready. Now, they want to
make some kind of a natural landing area for the
ducks, something for the decoys to float on. In order
to make a hole large enough to look like something a
wandering duck would fly down and land on, it is going
to take a little more effort than an ice hole drill.
So, out of the back of the new Navigator comes a stick
of dynamite with a short, 40-second fuse.

Now these two Rocket Scientists do take into
consideration that they want to place the stick of
dynamite on the ice at a location far from where they
are standing (and the new Navigator), because they
don't want to take the risk of slipping on the ice
when they run from the burning fuse and possibly go up
in smoke with the resulting blast. They light the
40-second fuse and throw the dynamite. Remember a
couple of paragraphs back when I mentioned the
vehicle, the guns and the dog?

Let's talk about the dog: A highly trained Black Lab
used for RETRIEVING. Especially things thrown by the
owner. You guessed it, the dog takes off at a high
rate of doggy speed on the ice and captures the stick
of dynamite with the burning 40-second fuse about the
time it hits the ice.

The two men yell, scream, wave their arms and wonder
what to do now. The dog, cheered on, keeps coming. One
of the guys grabs the shotgun and shoots the dog. The
shotgun is loaded with # 8 shot, hardly big enough to stop
a Black Lab.

The dog stops for a moment, slightly confused, but
continues on. Another shot and this time the dog,
still standing, becomes really confused and of course
terrified, thinking these two geniuses have gone
insane. The dog takes off to find cover, under the
brand new Navigator.

 ----BOOM!----

Dog and Navigator are blown to bits and sink to the
bottom of the lake in a very large hole, leaving the
two idiots standing there with this "I can't believe
this happened" look on their faces.

The insurance company says that sinking a vehicle in a
lake by illegal use of explosives is not covered. He still
had yet to make the first of those $560 a month payments!!

And you thought your day was not going well?


Poor dog to have such a stupid owner.




--part1_103.f4870e9.2979dfb2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>(...Blushing...) didn't know I was so popular...hehehe. Wish I could come out this year, but it's only fair to take turns...
<BR>
<BR>Seeing how today is Friday, I thought I would share this true story that comes from Michigan, up where Earl is. They don't mention any names in the story but I just wonder if Earl had anything to do with this? Remember he said he likes things that go BOOM!
<BR>
<BR>-Steve Gregory-
<BR>
<BR>Goodbye, Lincoln Navigator
<BR>
<BR>This is from a radio program, a true report of an
<BR>incident in Michigan: A guy buys a brand new Lincoln
<BR>Navigator for $42,500 and has $560 monthly payments.
<BR>He and a friend go duck hunting in winter, and of
<BR>course all the lakes are frozen.
<BR>
<BR>These two guys go out on the lake with the guns, the
<BR>dog, and of course the new vehicle. They drive out
<BR>onto the lake ice and get ready. Now, they want to
<BR>make some kind of a natural landing area for the
<BR>ducks, something for the decoys to float on. In order
<BR>to make a hole large enough to look like something a
<BR>wandering duck would fly down and land on, it is going
<BR>to take a little more effort than an ice hole drill.
<BR>So, out of the back of the new Navigator comes a stick
<BR>of dynamite with a short, 40-second fuse.
<BR>
<BR>Now these two Rocket Scientists do take into
<BR>consideration that they want to place the stick of
<BR>dynamite on the ice at a location far from where they
<BR>are standing (and the new Navigator), because they
<BR>don't want to take the risk of slipping on the ice
<BR>when they run from the burning fuse and possibly go up
<BR>in smoke with the resulting blast. They light the
<BR>40-second fuse and throw the dynamite. Remember a
<BR>couple of paragraphs back when I mentioned the
<BR>vehicle, the guns and the dog?
<BR>
<BR>Let's talk about the dog: A highly trained Black Lab
<BR>used for RETRIEVING. Especially things thrown by the
<BR>owner. You guessed it, the dog takes off at a high
<BR>rate of doggy speed on the ice and captures the stick
<BR>of dynamite with the burning 40-second fuse about the
<BR>time it hits the ice.
<BR>
<BR>The two men yell, scream, wave their arms and wonder
<BR>what to do now. The dog, cheered on, keeps coming. One
<BR>of the guys grabs the shotgun and shoots the dog. The
<BR>shotgun is loaded with # 8 shot, hardly big enough to stop
<BR>a Black Lab.
<BR>
<BR>The dog stops for a moment, slightly confused, but
<BR>continues on. Another shot and this time the dog,
<BR>still standing, becomes really confused and of course
<BR>terrified, thinking these two geniuses have gone
<BR>insane. The dog takes off to find cover, under the
<BR>brand new Navigator.
<BR>
<BR> ----BOOM!----
<BR>
<BR>Dog and Navigator are blown to bits and sink to the
<BR>bottom of the lake in a very large hole, leaving the
<BR>two idiots standing there with this "I can't believe
<BR>this happened" look on their faces.
<BR>
<BR>The insurance company says that sinking a vehicle in a
<BR>lake by illegal use of explosives is not covered. He still
<BR>had yet to make the first of those $560 a month payments!!
<BR>
<BR>And you thought your day was not going well?
<BR>
<BR>
<BR>Poor dog to have such a stupid owner.
<BR>
<BR>
<BR></FONT></HTML>

--part1_103.f4870e9.2979dfb2_boundary--

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=========================================================================
Date:         Fri, 18 Jan 2002 15:50:18 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hiteshew, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hiteshew, Michael" <[log in to unmask]>
Subject:      Re: Mechanical Specifications for VME boards...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-version: 1.0
Content-type: multipart/alternative;
              boundary="Boundary_(ID_BI9MMQmbfJv38c6HPA6eeg)"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

--Boundary_(ID_BI9MMQmbfJv38c6HPA6eeg)
Content-type: text/plain
Content-transfer-encoding: 7BIT

Steve,

Here's the spec I've used:  ANSI / IEEE STD 1014-1987 .        ~MH

 -----Original Message-----
From: Stephen Gregory [mailto:[log in to unmask]]
Sent: Friday, January 18, 2002 11:42 AM
To: [log in to unmask]
Subject: [TN] Mechanical Specifications for VME boards...



YAY! It's Friday!!

Does anybody know where I can get VME board mechanical spec's (dimensions,
etc.)?

Thanks!

-Steve Gregory-



--Boundary_(ID_BI9MMQmbfJv38c6HPA6eeg)
Content-type: text/html
Content-transfer-encoding: 7BIT

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">


<META content="MSHTML 5.50.4522.1800" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=071192420-18012002><FONT
color=#ff0000>Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=071192420-18012002><FONT
color=#ff0000></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=071192420-18012002><FONT color=#ff0000>Here's the spec I've
used:&nbsp; ANSI / IEEE STD 1014-1987
<EM>.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </EM></FONT></SPAN><FONT
face=Tahoma size=2><SPAN class=071192420-18012002><FONT face="Times New Roman"
color=#ff0000 size=3>~MH</FONT></SPAN></DIV>
<DIV><SPAN class=071192420-18012002><FONT face="Times New Roman" color=#ff0000
size=3></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=071192420-18012002>&nbsp;</SPAN>-----Original
Message-----<BR><B>From:</B> Stephen Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, January 18, 2002 11:42
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Mechanical
Specifications for VME boards...<BR><BR></DIV></FONT>
<BLOCKQUOTE><FONT face=arial,helvetica><FONT size=2>YAY! It's Friday!!
  <BR><BR>Does anybody know where I can get VME board mechanical spec's
  (dimensions, etc.)? <BR><BR>Thanks! <BR><BR>-Steve Gregory-
<BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>

--Boundary_(ID_BI9MMQmbfJv38c6HPA6eeg)--

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Date:         Fri, 18 Jan 2002 12:59:56 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Denis Lefebvre <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Denis Lefebvre <[log in to unmask]>
Subject:      Re: Apex 2000 - Lunch on Thursday
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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Sounds like prime candidates for the "Darwin" award.

At 03:29 PM 1/18/2002 -0500, you wrote:
>(...Blushing...) didn't know I was so popular...hehehe. Wish I could come
>out this year, but it's only fair to take turns...
>
>Seeing how today is Friday, I thought I would share this true story that
>comes from Michigan, up where Earl is. They don't mention any names in the
>story but I just wonder if Earl had anything to do with this? Remember he
>said he likes things that go BOOM!
>
>-Steve Gregory-
>
>Goodbye, Lincoln Navigator
>
>This is from a radio program, a true report of an
>incident in Michigan: A guy buys a brand new Lincoln
>Navigator for $42,500 and has $560 monthly payments.
>He and a friend go duck hunting in winter, and of
>course all the lakes are frozen.
>
>These two guys go out on the lake with the guns, the
>dog, and of course the new vehicle. They drive out
>onto the lake ice and get ready. Now, they want to
>make some kind of a natural landing area for the
>ducks, something for the decoys to float on. In order
>to make a hole large enough to look like something a
>wandering duck would fly down and land on, it is going
>to take a little more effort than an ice hole drill.
>So, out of the back of the new Navigator comes a stick
>of dynamite with a short, 40-second fuse.
>
>Now these two Rocket Scientists do take into
>consideration that they want to place the stick of
>dynamite on the ice at a location far from where they
>are standing (and the new Navigator), because they
>don't want to take the risk of slipping on the ice
>when they run from the burning fuse and possibly go up
>in smoke with the resulting blast. They light the
>40-second fuse and throw the dynamite. Remember a
>couple of paragraphs back when I mentioned the
>vehicle, the guns and the dog?
>
>Let's talk about the dog: A highly trained Black Lab
>used for RETRIEVING. Especially things thrown by the
>owner. You guessed it, the dog takes off at a high
>rate of doggy speed on the ice and captures the stick
>of dynamite with the burning 40-second fuse about the
>time it hits the ice.
>
>The two men yell, scream, wave their arms and wonder
>what to do now. The dog, cheered on, keeps coming. One
>of the guys grabs the shotgun and shoots the dog. The
>shotgun is loaded with # 8 shot, hardly big enough to stop
>a Black Lab.
>
>The dog stops for a moment, slightly confused, but
>continues on. Another shot and this time the dog,
>still standing, becomes really confused and of course
>terrified, thinking these two geniuses have gone
>insane. The dog takes off to find cover, under the
>brand new Navigator.
>
>----BOOM!----
>
>Dog and Navigator are blown to bits and sink to the
>bottom of the lake in a very large hole, leaving the
>two idiots standing there with this "I can't believe
>this happened" look on their faces.
>
>The insurance company says that sinking a vehicle in a
>lake by illegal use of explosives is not covered. He still
>had yet to make the first of those $560 a month payments!!
>
>And you thought your day was not going well?
>
>
>Poor dog to have such a stupid owner.
>

--=====================_26231989==_.ALT
Content-Type: text/html; charset="us-ascii"

<html>
Sounds like prime candidates for the &quot;Darwin&quot; award.<br><br>
At 03:29 PM 1/18/2002 -0500, you wrote:<br>
<blockquote type=cite class=cite cite><font face="arial" size=2>(...Blushing...)
didn't know I was so popular...hehehe. Wish I could come out this year,
but it's only fair to take turns... <br><br>
Seeing how today is Friday, I thought I would share this true story that
comes from Michigan, up where Earl is. They don't mention any names in
the story but I just wonder if Earl had anything to do with this?
Remember he said he likes things that go BOOM! <br><br>
-Steve Gregory- <br><br>
Goodbye, Lincoln Navigator <br><br>
This is from a radio program, a true report of an <br>
incident in Michigan: A guy buys a brand new Lincoln <br>
Navigator for $42,500 and has $560 monthly payments. <br>
He and a friend go duck hunting in winter, and of <br>
course all the lakes are frozen. <br><br>
These two guys go out on the lake with the guns, the <br>
dog, and of course the new vehicle. They drive out <br>
onto the lake ice and get ready. Now, they want to <br>
make some kind of a natural landing area for the <br>
ducks, something for the decoys to float on. In order <br>
to make a hole large enough to look like something a <br>
wandering duck would fly down and land on, it is going <br>
to take a little more effort than an ice hole drill. <br>
So, out of the back of the new Navigator comes a stick <br>
of dynamite with a short, 40-second fuse. <br><br>
Now these two Rocket Scientists do take into <br>
consideration that they want to place the stick of <br>
dynamite on the ice at a location far from where they <br>
are standing (and the new Navigator), because they <br>
don't want to take the risk of slipping on the ice <br>
when they run from the burning fuse and possibly go up <br>
in smoke with the resulting blast. They light the <br>
40-second fuse and throw the dynamite. Remember a <br>
couple of paragraphs back when I mentioned the <br>
vehicle, the guns and the dog? <br><br>
Let's talk about the dog: A highly trained Black Lab <br>
used for RETRIEVING. Especially things thrown by the <br>
owner. You guessed it, the dog takes off at a high <br>
rate of doggy speed on the ice and captures the stick <br>
of dynamite with the burning 40-second fuse about the <br>
time it hits the ice. <br><br>
The two men yell, scream, wave their arms and wonder <br>
what to do now. The dog, cheered on, keeps coming. One <br>
of the guys grabs the shotgun and shoots the dog. The <br>
shotgun is loaded with # 8 shot, hardly big enough to stop <br>
a Black Lab. <br><br>
The dog stops for a moment, slightly confused, but <br>
continues on. Another shot and this time the dog, <br>
still standing, becomes really confused and of course <br>
terrified, thinking these two geniuses have gone <br>
insane. The dog takes off to find cover, under the <br>
brand new Navigator. <br><br>
----BOOM!---- <br><br>
Dog and Navigator are blown to bits and sink to the <br>
bottom of the lake in a very large hole, leaving the <br>
two idiots standing there with this &quot;I can't believe <br>
this happened&quot; look on their faces. <br><br>
The insurance company says that sinking a vehicle in a <br>
lake by illegal use of explosives is not covered. He still <br>
had yet to make the first of those $560 a month payments!! <br><br>
And you thought your day was not going well? <br><br>
<br>
Poor dog to have such a stupid owner. <br><br>
</font></blockquote></html>

--=====================_26231989==_.ALT--

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Date:         Fri, 18 Jan 2002 15:03:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Baking of Assemblies?
Mime-Version: 1.0
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This should be good fodder! We wash PWAs in a water hurricane type machine, with
a hot air blower at the end of cycle. We noticed some components mainly elect.
alum. capacitors have high capacitance. After research on cap. we were
instructed to bake assemblies 20 mins @ 100c to dry them. The long term effect
of the moisture in the cap would cause electrical leakage then failure due to
corrosion.
Well this idea expanded into a question should we bake all assemblies because
many other items such as transformers, pots., coils are not hermetically sealed.
And then there is the issue with pwb material its self.

My question to the forum is, Does anyone bake after wash as a standard? All
points of view are welcome.

Thanks!

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Date:         Fri, 18 Jan 2002 13:36:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject:      via hole size for 062 boards
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Typically it would be  a  .013 dia finish hole, Manufacture drill would
probably be .018 dia.
So if you add .014 too .018  you get an .032 dia pad.  This you then
adjust depending
on trace width technology and many other factors, like via pitch, gnd
and power plane webbing
between vias.  .032 minus .050 = .018.  If your anti pad is plus 5 or 6
mils per side then
your left with .008 and .006 of copper webbing on your planes.

hope this helps

Greg Scott
Cray Inc.

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Date:         Fri, 18 Jan 2002 16:41:50 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Baking of Assemblies?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Warren,

Well sorta.  We had a Bake after Aqueous Cleaning (in a Tooltronics Ultra
Clean 2) before Wave Flow Soldering.  Assemblies are stored in dry nitrogen
when not in process and that pulls moisture out as well.  Your baking temp.
seems kinda low at 100 degrees C. Is there a reason why 125C wouldn't be
acceptable?  The in-line cleaner could remove surface moisture but didn't do
very well on tall connectors.  You might run an archive search, baking is a
recurring topic.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, January 18, 2002 4:04 PM
To: [log in to unmask]
Subject: [TN] Baking of Assemblies?


This should be good fodder! We wash PWAs in a water hurricane type machine,
with
a hot air blower at the end of cycle. We noticed some components mainly
elect.
alum. capacitors have high capacitance. After research on cap. we were
instructed to bake assemblies 20 mins @ 100c to dry them. The long term
effect
of the moisture in the cap would cause electrical leakage then failure due
to
corrosion.
Well this idea expanded into a question should we bake all assemblies
because
many other items such as transformers, pots., coils are not hermetically
sealed.
And then there is the issue with pwb material its self.

My question to the forum is, Does anyone bake after wash as a standard? All
points of view are welcome.

Thanks!

----------------------------------------------------------------------------
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Technet NOMAIL
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Date:         Fri, 18 Jan 2002 16:49:40 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Mechanical Specifications for VME boards...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0016_01C1A040.1F68D680"

This is a multi-part message in MIME format.

------=_NextPart_000_0016_01C1A040.1F68D680
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

=20
Look here http://map.web.cern.ch/Atlas/GROUPS/FRONTEND/VMEbus/
=20
Several points on VME are:
* The definitive VME specification is IEEE1014-1987 [IEC821] - IEEE =
Standard for a Versatile Backplane Bus: VMEbus [ =
http://standards.ieee.org/catalog/olis/busarch.html ].
* Form factor background =
http://www.mcg.mot.com/cfm/templates/formfactor.cfm?PageID=3D559&FormFact=
orID=3D1
* Background information is http://www.vita.com/vmefaq/
=20
Dave Fish
  ----- Original Message -----=20
  From: Stephen Gregory=20
  To: [log in to unmask]
  Sent: Friday, January 18, 2002 8:41 AM
  Subject: [TN] Mechanical Specifications for VME boards...


  YAY! It's Friday!!=20

  Does anybody know where I can get VME board mechanical spec's =
(dimensions, etc.)?=20

  Thanks!=20

  -Steve Gregory-=20


------=_NextPart_000_0016_01C1A040.1F68D680
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>&nbsp;</FONT></DIV>
<DIV class=3DMsoNormal><SPAN style=3D"FONT-FAMILY: Arial"><FONT =
size=3D2>Look here=20
</FONT><A =
href=3D"http://map.web.cern.ch/Atlas/GROUPS/FRONTEND/VMEbus/"><FONT=20
size=3D2>http://map.web.cern.ch/Atlas/GROUPS/FRONTEND/VMEbus/</FONT></A><=
?xml:namespace=20
prefix =3D o ns =3D "urn:schemas-microsoft-com:office:office"=20
/><o:p></o:p></SPAN></DIV>
<DIV class=3DMsoNormal><FONT size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial">&nbsp;<o:p></o:p></SPAN></FONT></DIV>
<DIV class=3DMsoNormal><FONT size=3D2><SPAN style=3D"FONT-FAMILY: =
Arial">Several=20
points on VME are:<o:p></o:p></SPAN></FONT></DIV>
<DIV class=3DMsoNormal><FONT size=3D2><SPAN style=3D"FONT-FAMILY: =
Arial">* The=20
definitive VME specification is IEEE1014-1987 [IEC821] - IEEE Standard =
for a=20
Versatile Backplane Bus: VMEbus [=20
http://standards.ieee.org/catalog/olis/busarch.html=20
].<o:p></o:p></SPAN></FONT></DIV>
<DIV class=3DMsoNormal><SPAN style=3D"FONT-FAMILY: Arial"><FONT =
size=3D2>* Form factor=20
background </FONT><A=20
href=3D"http://www.mcg.mot.com/cfm/templates/formfactor.cfm?PageID=3D559&=
amp;FormFactorID=3D1"><FONT=20
size=3D2>http://www.mcg.mot.com/cfm/templates/formfactor.cfm?PageID=3D559=
&amp;FormFactorID=3D1</FONT></A><o:p></o:p></SPAN></DIV>
<DIV class=3DMsoNormal><SPAN style=3D"FONT-FAMILY: Arial"><FONT =
size=3D2>* Background=20
information is </FONT><A href=3D"http://www.vita.com/vmefaq/"><FONT=20
size=3D2>http://www.vita.com/vmefaq/</FONT></A><o:p></o:p></SPAN></DIV>
<DIV class=3DMsoNormal><FONT size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial">&nbsp;</SPAN></FONT></DIV>
<DIV class=3DMsoNormal><FONT size=3D2><SPAN style=3D"FONT-FAMILY: =
Arial">Dave=20
Fish<o:p></o:p></SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>Stephen =
Gregory</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 18, 2002 =
8:41=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Mechanical =
Specifications=20
  for VME boards...</DIV>
  <DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>YAY! It's =
Friday!!=20
  <BR><BR>Does anybody know where I can get VME board mechanical spec's=20
  (dimensions, etc.)? <BR><BR>Thanks! <BR><BR>-Steve Gregory-=20
<BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>

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Date:         Fri, 18 Jan 2002 17:29:10 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lee Whiteman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lee Whiteman <[log in to unmask]>
Subject:      Re: Baking of Assemblies?
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Warren,

In a prior life, I had to bake out some hardware after aqueous cleaning.
This was primarily due to the hardware being used in a space application,
and Engineering / Program Management was afraid that the moisture from the
aqueous cleaning process would out gas in the vacuum of space (even with
conformal coating).

Certain components did have to be baked out after aqueous cleaning. Other
components could not be cleaned in an aqueous cleaner due to material
incompatibilities. To avoid this, we would put these parts and components on
after cleaning, and locally clean those components with IPA. I know the
arguments against local cleaning with IPA (moving / diluting the flux around
the soldered component vs. removing it), but for our application it worked
fine.

I would also suggest that if you could replace these components with
something more robust, it may remove the baking operation after cleaning.

Hope this helps.

Good Luck.

Lee Whiteman
Senior Manufacturing Engineer
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x208
Fax: (610) 362-1290



> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
> Sent: Friday, January 18, 2002 4:04 PM
> To: [log in to unmask]
> Subject: [TN] Baking of Assemblies?
>
>
> This should be good fodder! We wash PWAs in a water hurricane
> type machine, with
> a hot air blower at the end of cycle. We noticed some components
> mainly elect.
> alum. capacitors have high capacitance. After research on cap. we were
> instructed to bake assemblies 20 mins @ 100c to dry them. The
> long term effect
> of the moisture in the cap would cause electrical leakage then
> failure due to
> corrosion.
> Well this idea expanded into a question should we bake all
> assemblies because
> many other items such as transformers, pots., coils are not
> hermetically sealed.
> And then there is the issue with pwb material its self.
>
> My question to the forum is, Does anyone bake after wash as a
> standard? All
> points of view are welcome.
>
> Thanks!
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> To receive ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources &
> Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Fri, 18 Jan 2002 14:50:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Smith, Russell (US LA)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Smith, Russell (US LA)" <[log in to unmask]>
Subject:      Re: Thermocouples for SuperMole
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

If you use the standard super mole with the yellow connectors , then
Omega has off the shelf t/c assemblies and miniature connectors, If you
have the super mole gold , with the black connectors, (female
connectors) then the connector body is proprietary, you need to buy them
from ECD .
=20
However, if you have the black plastic connectors from existing T/C=20
=20
Then you can build your own., you can order thermocouples from Omega
engineering( omega.com) , you will need to also purchase the miniature
crimp connectors, they are omega part # SMTC-CH-S these are the Chromel
contacts for the yellow or positive side of type K , the other are part
number SMTC-AL-S for the Alumel  (red ,negative) side of the type K T/C.

  =20
Russ Smith=20
=20
Vantico. Inc.   =20
=20

-----Original Message-----
From: Becerra Alejandro [mailto:[log in to unmask]]
Sent: Thu, January 17, 2002 9:46 AM
To: [log in to unmask]
Subject: [TN] Thermocouples for SuperMole



Hello to All,=20
Could you please tell me any vendor for Thermocouples for SuperMole
profiler?=20

Thanks,=20

Alejandro Becerra=20

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Date:         Fri, 18 Jan 2002 22:19:30 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
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Hi Don,
You write:
>Before you hit the slopes - two last questions.
>In point #2, do you mean exactly what is written: that the non-functional
>pads reduce the possibility of hole wall separation?  Or do you mean that
>the presence of additional anchors reduces the propagation or magnitude
>of separation when it occurs?
>How does the presence of additional pads reduce the possibility of inner
>layer separation?  My understanding is that the adhesion of b-stage to
>c-stage is greater than the adhesion of polymer to copper.
A: I mean that the non-functional pads prevent the occurrance, not the
propagation or magnitude, of hole wall separation. You need to understand
what the mechanism causing hole wall separation is. Hole wall separation has
little to do with adhesion. Hole wall separation is caused by the PCB resin
expanding towards the hole center during heating. The higher the resin
content (prepreg layer has mor than the laminate layer) the more this
expansion. The larger the drilled hole diameter, the thinner the plated
copper barrel, the longer the compressed cylinder (PCB thickness), the fewer
cylinder reinforcement ribs (read: functional and non-functional lands), the
easier the expanding resin is capable of buckling the PTH hole wall inwards.
Too much inwards movement will cause plastic deformation of the copper
cylinder. Thus, on cooling the resin returns to its former volume and
position; so will the PTH wall if the copper barrel is only elastically
deformed. However, if the copper barrel is only plastically deformed, it will
stay where it is--voila, you have hole wall separation.

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Date:         Sat, 19 Jan 2002 10:20:47 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Silver component contamination
X-To:         Genny Gibbard <[log in to unmask]>
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Genny

The innocuousness or otherwise of markers is a subject that comes up
from time to time. The alcohols you mention are of no concern as they
evaporate completely. It is what is left behind that may be. This
consists of some form of polymer, dyes and pigments. As a rule, most
polymers are probably fairly benign unless they are hygroscopic (as can
happen). As for the pigments, I'd be rather wary of black markers,
because the pigment is almost surely carbon black (a form of very fine
soot formed by burning petroleum derived gases/vapours under controlled
conditions without admixture of oxygen). The same carbon black is also
used for making cheap and nasty resistors - need I say more? Pigments
derived from natural earths are usually harmless. Synthetic ones and
dyes may be less so, especially if they are not chemically or physically
stable. There is therefore a risk in using any marker and their use must
be qualified after practical lab trials - and never change the
manufacturer or type without requalification.

As for cleaning marker marks: again qualification is the only way of
finding out whether a process is safe. Remember that you may remove some
components of the ink yet leave others, which may be invisible but
electrically malign. Above all, remember that some markers will actually
penetrate the surface of some items, especially polymers, making it
impossible to clean away.

Conclusion: test and see, but be mistrustful.

Brian

Genny Gibbard wrote:
>
> Happy Friday! (tappity, tappity - doing the Friday dance)
> We have ceramic resonators with silver coating on several products.  We
> started handling those OEM boards with gloves during our test processes
> because the customer expressed concern with skin oil contamination.
> At times these components have been marked in house, for various reasons,
> with a standard sharpie marker.  In fact, at an early point in the
> production schedule, the CM we were using at the time was marking them on
> their own, because the resonators are so close in size they were having
> trouble telling them apart and getting them installed in the right locations
> (due to tight time requirements, we got a shipment of bulk parts that were
> being placed by hand).  The marks looked like they were marker applied and
> used a variety of dot and line patterns in various colours.  We have never
> noticed any harmful effect on their response, although build quantities were
> low.
> Now someone on our production floor is asking whether the ink may be a
> contamination that we should avoid.  We have easily cleaned this marker off
> of other surfaces with board wash.  They wanted to know if they should clean
> the components with board wash.  I think that if the marker is already on
> there and a contaminant, don't compound it by rubbing board wash on it.
> >From what I can tell, from the MSDS on the marker website, the ink is
> primarily propanol/butanol/alcohol based.  The board wash is alcohol based.
> Chemistry is my weak subject.  Is alcohol - related substances on silver
> coated components a concern?
>
> Genny Gibbard (mailto:[log in to unmask])
> Product Transition and Support
> Wavecom Electronics Inc.
> 202 Cardinal Crescent
> Saskatoon, SK, Canada
> ph:     (306) 955-7075 ext. 229
> fax:    (306)384-0086
>
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Date:         Sat, 19 Jan 2002 13:13:18 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              ryan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         ryan <[log in to unmask]>
Subject:      Re: Via Hole Size for 062 boards
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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.0135 drill, .008 +.003/-.008 finished hole size, with .028 outer layer,
.026 inner layer and a .038 antipad.

Ron

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jorge Rodriguez
Sent: Friday, January 18, 2002 1:30 PM
To: [log in to unmask]
Subject: [TN] Via Hole Size for 062 boards

What would be the standard via hole size for a 4-6 layer/0.062" board? This
would be without pushing the technology to the edge or incurring on extra
cost, just the industry standard.

Thanks for your comments

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Sun, 20 Jan 2002 06:16:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Werner Engelmaier <[log in to unmask]>

Werner and all interested,

Too catagorical? It must be something I picked up in the jungle. I?ll seek
help. However, in my only post on this subject, I was reporting MY
observations over the years concerning thousands of boards I have worked on
and with.

Werner, as always, makes good points and better explanations in his latest
retort concerning what causes hole wall separation and why non-functional
pads help prevent it?s occurrence though not magnitude or propagation, or
some such thing. However, If magnitude is synonomous with amount or degree,
I would argue this point later based on what you say about resin amount. As
for propagation, something has to be there in the first place for it to
propagate.

In this post, I would point out that resin recession and hole wall
separation can be, and usually is, minimized in most higher layer count
MLB?s compared with some time ago. I don?t know if Werner is old enough to
remember the days when defense board suppliers were required to build MLB?s
with two plies of prepreg minimum in each dielectric thickness. If so, I?m
sure he had something to do with the practice?s demise.  I?m equally sure
everyone knows why but, if not, it was required to ?prevent? shorting
between two conductive layers via a glass strand that might somehow become
conductive.

In more recent times, the two ply requirement gave way to single ply
constructions. Therefore, there is less resin per ply, when boards are
?properly? constructed. This especially is true considering 12 layer and
over designs beyond a thickness of .062?. The primary reasons for this are
impedance and associated dielectric thickness requirements most often
requiring 50 ohms.

Again, in the good old days, to construct, say, a 10 layer type, because of
the two ply requirement, usually it was made up of two plies of 1080 core
and prepreg material (I used one ply 106 with one of 2113 to add more
dimensional stability though the 106 was about 70% resin ? very juicy) to
make its overall thickness .062?. 1080 glass style material is, as everyone
knows, very resin rich. Therefore, the phenomenon Werner describes,
concerning resin expanding, contracting, and expanding again was much more
common than now with single ply constructions that are not nearly as resin
rich. There?s a long story to all this but it should be unnecessary to
discuss it now.

So, in a 16 layer board, as one example, requiring 50 ohms impedance, the
whole structure can be made up of  single and two ply 2116 material with a
Dk of about 4.0 ? 4.3. 2116 material is very well balanced concerning its
resin to glass ratio at about 53%. This provides much less resin to expand
in any direction but for its CTE. However, the resin does not move so much
it can cause recession or separation. Of course, in any event, good plating
adhesion is required.

All this brings me to: You don?t need no dummy pads to prevent the
aforementioned problem. There?s obviously much more to this story and I
think folks have written extensively about it. Werner has written so much
stuff it will take me another life to read it all.

Earl Moon

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Date:         Sun, 20 Jan 2002 09:46:47 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Joseph Fjelstad <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
MIME-Version: 1.0
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              boundary="part1_178.262aeb7.297c3257_boundary"

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Hi Earl,

I am certain you also recall that there was at least one other historical
reason for using two plies of prepreg and that was to improve flow and ensure
full encapsulation of the circuit detail. The increased use of lighter weight
foils and more resin rich prepregs facilitated movement to and use of
single-ply layer separation constructions.

Best regards,
Joe

--part1_178.262aeb7.297c3257_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Earl,
<BR>
<BR>I am certain you also recall that there was at least one other historical reason for using two plies of prepreg and that was to improve flow and ensure full encapsulation of the circuit detail. The increased use of lighter weight foils and more resin rich prepregs facilitated movement to and use of single-ply layer separation constructions.
<BR>
<BR>Best regards,
<BR>Joe </FONT></HTML>

--part1_178.262aeb7.297c3257_boundary--

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Date:         Sun, 20 Jan 2002 14:47:59 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Remove unused "dead" pads on internal layers
X-To:         Joseph Fjelstad <[log in to unmask]>

Joe,

I appreciate the mrmory trip. I just liked the shorting explanation best.
Ever see or hear about any shorting?

Earl

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Date:         Mon, 21 Jan 2002 08:34:51 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Mechanical Specifications for VME boards...
X-To:         [log in to unmask]
MIME-Version: 1.0
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Yeah, me!

The spec you want is IEEE Std 1101.2-1992, but I don't think it's
free-downloadable. The board is 9.187+0.0000/-0.012 ins x 6.299 ins x
0.063+/-0.008 ins. A clearance of 0.098 ins at each side is specified to
permit the board to fit any VME standard chassis, and there is an overall
max height envelope from the board centreline on the component side of
0.571 ins (or 0.421 ins if you're using the permitted reduced chassis card
guide width). A similar dimension for the solder side of the board is 0.129
ins max.

There's a bunch of other stuff as well. The spec is very specific in
certain areas, but leaves a lot of room for designers' freedom of
expression as well. It's only a 9 page document, and if you need any other
details from it, do contact me off-line. I only have a paper copy of it
myself.

Peter




                    Stephen
                    Gregory              To:     [log in to unmask]
                    <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    L.COM>               Aero/ST Group)
                    Sent by:             Subject:     [TN] Mechanical Specifications for
                    TechNet              VME boards...
                    <[log in to unmask]
                    ORG>


                    01/19/02
                    12:41 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






YAY! It's Friday!!

Does anybody know where I can get VME board mechanical spec's (dimensions,
etc.)?

Thanks!

-Steve Gregory-



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Date:         Mon, 21 Jan 2002 08:45:03 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Baking of Assemblies?
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Yep! Our assmebly house bakes the boards for about 3 hours at 90 deg C to
dry them out after a wash.

Peter



                    Warren_Crow@I
                    -O.COM               To:     [log in to unmask]
                    Sent by:             cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    TechNet              Aero/ST Group)
                    <[log in to unmask]        Subject:     [TN] Baking of Assemblies?
                    ORG>


                    01/19/02
                    05:03 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    Warren_Crow






This should be good fodder! We wash PWAs in a water hurricane type machine,
with
a hot air blower at the end of cycle. We noticed some components mainly
elect.
alum. capacitors have high capacitance. After research on cap. we were
instructed to bake assemblies 20 mins @ 100c to dry them. The long term
effect
of the moisture in the cap would cause electrical leakage then failure due
to
corrosion.
Well this idea expanded into a question should we bake all assemblies
because
many other items such as transformers, pots., coils are not hermetically
sealed.
And then there is the issue with pwb material its self.

My question to the forum is, Does anyone bake after wash as a standard? All
points of view are welcome.

Thanks!

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Date:         Mon, 21 Jan 2002 09:04:25 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Prasad An <[log in to unmask]>
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From:         Prasad An <[log in to unmask]>
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Hi Technetter

Does any one let me know the correct way of measuring the Specific gravity
of No-Clean flux while using it in Wave soldering m/c.


Thanks

Prasad

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Date:         Mon, 21 Jan 2002 09:55:52 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re:
X-To:         Prasad An <[log in to unmask]>
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Prasad

I assume by "no-clean", you are using this synonymously with
"low-solids". IMHO, SG is not the correct way of measuring solids
content with low-solids. A little water in an alcohol-based one, for any
reason (and it happens) and you are up the greasy pole. In a water-based
one, SG is totally meaningless, as there is almost no difference between
the solvent and the solute. Consult your supplier for their
recommendations. Better still, use a spray fluxer that uses only virgin
flux, straight from the can, so that you have no maintenance to do.

Brian

Prasad An wrote:
>
> Hi Technetter
>
> Does any one let me know the correct way of measuring the Specific gravity
> of No-Clean flux while using it in Wave soldering m/c.
>
> Thanks
>
> Prasad
>
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Date:         Mon, 21 Jan 2002 07:43:51 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
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From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      FW: Cannon balls
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Earl, I thought you might like to include this bit of wisdom in your book.

Ron

Subject: Cannon balls


THIS IS YOUR HISTORY LESSON FOR THE DAY

In the heyday of sailing ships, all war ships and many freighters carried
cannons.  Those cannon fired round iron cannon balls.  It was necessary to
keep a good supply near the cannon, but prevent them from rolling about the
deck.

The best storage method devised was a square-based pyramid with one ball on
top, resting on four resting on nine, which rested on sixteen. Thus, a
supply of thirty cannon balls could be stacked in a small area right next
to the cannon.

There was only one problem - how to prevent the bottom layer from
sliding/rolling from under the others.
The solution was a metal plate called a "Monkey," with sixteen round
indentations.  If this plate was made of iron, the iron balls would quickly
rust to it due to the salt water.  The solution to the rusting problem was
to make, "Brass Monkeys."  Few landlubbers realize that brass contracts much
more and much faster than iron when chilled.  Consequently, when the
temperature dropped too far,  the brass indentations would contract  so much
that the cannon balls would roll off the monkey.  Thus we have the origin of
"Cold enough to freeze the balls off a brass monkey"

GEEZ, thought you would never ask!


Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]



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<BODY bgColor=#ffffff>
<DIV><FONT face=Arial color=#0000ff><SPAN class=710264212-21012002>Earl, I
thought you might like to include this bit of wisdom in your
book.</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff><SPAN
class=710264212-21012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=Arial color=#0000ff><SPAN
class=710264212-21012002>Ron</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff><SPAN
class=710264212-21012002></SPAN></FONT>&nbsp;</DIV>
<DIV style="FONT: 10pt arial">
<DIV><B>Subject:</B> Cannon balls</DIV></DIV>
<DIV><FONT face=Arial color=#0000ff></FONT><BR></DIV>
<DIV><FONT size=2><FONT size=2>THIS IS YOUR HISTORY LESSON FOR THE DAY<BR><BR>In
the heyday of sailing ships, all war ships and many freighters carried
cannons.&nbsp; Those cannon fired round iron cannon balls.&nbsp; It was
necessary to keep a good supply near the cannon, but prevent them from rolling
about the deck.</FONT></DIV>
<DIV>
<DIV><STRONG><FONT face=Papyrus color=#800080
size=4></FONT></STRONG>&nbsp;</DIV>
<DIV><FONT size=2>The best storage method devised was a square-based pyramid
with one ball on&nbsp;top, resting on four resting on nine, which rested
</FONT><FONT size=2>on sixteen. Thus, a supply of thirty cannon balls could be
stacked in a small area right next&nbsp; to the cannon.<BR><BR>There was only
one problem - how to prevent the bottom layer from&nbsp;sliding/rolling from
under the others.<BR>The solution was a metal plate called a</FONT><FONT size=2>
"Monkey," with sixteen round indentations.&nbsp; If this plate was made of iron,
the iron balls would quickly&nbsp;rust to it due to the salt water.&nbsp; The
solution to the rusting problem was to make, "Brass Monkeys."&nbsp; Few
landlubbers realize that brass contracts much more and much faster than iron
when chilled.&nbsp; Consequently, when the temperature dropped too
far,&nbsp;&nbsp;the brass indentations would contract</FONT><FONT size=2>&nbsp;
so much that the cannon balls woul</FONT><FONT size=2>d roll off the monkey.
&nbsp;Thus we have the origin of "Cold enough to freeze the balls off a brass
monkey"<BR><BR>GEEZ, thought you would never ask!</FONT></DIV>
<DIV><FONT size=2></FONT>&nbsp;</DIV></FONT></DIV>
<P><FONT face=Arial size=2>Ron Dieselberg</FONT> <BR><FONT face=Arial
size=2>Trainer/Auditor</FONT> <BR><FONT face=Arial size=2>CMC ELECTRONICS</FONT>
<BR><FONT face=Arial size=2>CINCINNATI</FONT> <BR><FONT face=Arial
size=2>[log in to unmask]</FONT> </P><BR></BODY></HTML>

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Date:         Mon, 21 Jan 2002 08:00:41 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rob Legg <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rob Legg <[log in to unmask]>
Subject:      FR4 power module SMC coplanarity
MIME-Version: 1.0
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Recent release of power modules constructed on FR4 substrate are designed
for
reflow soldering, but tend not to specify their coplanarity.

Given that a device is measurably coplanar before reflow on a large system
card,
will this coplanarity be maintained through the reflow temperature profile?

What's to stop it from curling like a piece of bacon when its coplanarity is
actually needed?

Previous versions of these parts were either on ceramic substrate, or
terminated with through-hole leads.

Any advice on this?

R Legg
[log in to unmask]

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Date:         Mon, 21 Jan 2002 13:10:26 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Dawson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Dawson <[log in to unmask]>
Subject:      Re: FW: Cannon balls
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Also known as suitable conditions for the cryogenic castration of
non-ferrous anthropoids.
Regards
Eric Dawson

> -----Original Message-----
> From: Dieselberg, Ron [SMTP:[log in to unmask]]
> Sent: Monday, January 21, 2002 12:44 PM
> To:   [log in to unmask]
> Subject:      [TN] FW: Cannon balls
>
> Earl, I thought you might like to include this bit of wisdom in your book.
>
> Ron
>
> Subject: Cannon balls
>
>
> THIS IS YOUR HISTORY LESSON FOR THE DAY
>
> In the heyday of sailing ships, all war ships and many freighters carried
> cannons.  Those cannon fired round iron cannon balls.  It was necessary to
> keep a good supply near the cannon, but prevent them from rolling about
> the deck.
>
> The best storage method devised was a square-based pyramid with one ball
> on top, resting on four resting on nine, which rested on sixteen. Thus, a
> supply of thirty cannon balls could be stacked in a small area right next
> to the cannon.
>
> There was only one problem - how to prevent the bottom layer from
> sliding/rolling from under the others.
> The solution was a metal plate called a "Monkey," with sixteen round
> indentations.  If this plate was made of iron, the iron balls would
> quickly rust to it due to the salt water.  The solution to the rusting
> problem was to make, "Brass Monkeys."  Few landlubbers realize that brass
> contracts much more and much faster than iron when chilled.  Consequently,
> when the temperature dropped too far,  the brass indentations would
> contract  so much that the cannon balls would roll off the monkey.  Thus
> we have the origin of "Cold enough to freeze the balls off a brass monkey"
>
> GEEZ, thought you would never ask!
>
>
> Ron Dieselberg
> Trainer/Auditor
> CMC ELECTRONICS
> CINCINNATI
> [log in to unmask]
>
>

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Date:         Mon, 21 Jan 2002 07:10:48 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: FW: Cannon balls
X-To:         Ron Dieselberg <[log in to unmask]>

Ron,

That little bit of non-information definitely is going in the book.
Outstanding, and to think a whole new technology was developed for balls of
this type. My future ex girlfriend will never know of this fact. She has
that John Wayne Bobbit look in her eyes some times. Almost a scary as hole
wall separation.

I'm in beautiful Cleveland for a short time. The story sure fits me here.

MoonMan

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Date:         Mon, 21 Jan 2002 07:24:12 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: FR4 power module SMC coplanarity
X-To:         R Legg <[log in to unmask]>

First let me say Eric must know the lady about whom I speak. Ouch!

Concerning a more vital, doubt it, issue, there is no reason to expect the
PCB version, on whatever material, will go out of whack like a potato chip.
BGA's are built on BT based boards and they stay reasonably flat.

You know it depends on how well the design was effected. You know - balance,
construction, etc.

Just have to try them and see. If they do warp, what are your options?

MoonMan

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Date:         Mon, 21 Jan 2002 15:42:37 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: FW: Cannon balls
X-To:         "Dieselberg, Ron" <[log in to unmask]>
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Ron

Are you trying to make a monkey out of us by monkeying around with
nautical terms? I'll bet you a monkey/500 that your explanation ain't
right. Why? a) the balls weren't brought up on deck until they were
needed, lest they rust together; b) the precision of the balls'
diameters was roughly +/- 1 cm, and I doubt whether your brass plate was
adjusted to the diameters of individual balls; c) there would be more
corrosion with iron in contact with brass than iron-to-iron; d) I doubt
whether a cannon would survive shooting 30 balls one after the other
without exploding in the face of the matelots, so why have a dangerous
pile of 30 balls? e) the word 'monkey' was used nautically, that is
sure, but as an adjective for a jury-rigged temporary device - e.g., a
monkey foresail was an ad hoc one that was lashed up to replace a torn
one; f) I have seen piles of balls next to cannons on museum-style ships
but I think they were always retained by simple wooden battens, which,
incidentally would be the correct term (batten was also used nautically
for the strip of wood or iron which held a tarpaulin over an opening -
"batten down the hatches").

I was recently sent a list of the "origins" of a number of sayings, each
one more apocryphal than the others and, being a doubting Thomas, I take
everything like this with a pinch of the salt that would rust the balls
together. Sorry to put a monkey wrench in the works! :-)

Brian

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Date:         Mon, 21 Jan 2002 07:45:10 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: FW: Cannon balls
X-To:         Brian Ellis <[log in to unmask]>

Brian,

I have to go with Ron's stuff because it's so simple to the point of being
cold. I do trust your competence in these matters, as you know, but I need a
good "little" story in the book. Besides, I quit monkeying around years ago,
but for my latest "romantic efforts."

I'm guessing this is about IPC will allow so I won't continue with my other
story concerning large versus small balls. I think I did that before anyway.

MoonMan

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Date:         Mon, 21 Jan 2002 08:18:39 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
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From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re:
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Use a hydrometer and a large vial.  We fill the vial up and then put the =
hydrometer into the solution.  We can then tell specific gravity from that =
and we may possibly thin or add more flux depending on the reading.  We =
use the acceptable ranges per the flux manufacturer.  Record the results =
of the readings and the actions taken. This info is extremely important =
and wil give you some very good trend analysis. =20
Kathy=20

--=_772A0A4C.94F5989E
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<BODY
style="MARGIN-TOP: 2px; FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px">
<DIV>Use a hydrometer and a large vial.&nbsp; We fill the vial up and then put
the hydrometer into the solution.&nbsp; We&nbsp;can then tell specific gravity
from that and we may possibly thin&nbsp;or add more flux depending on the
reading.&nbsp; We use the acceptable ranges per the flux manufacturer.&nbsp;
Record the results of the readings and the actions taken. This info is extremely
important and wil give you some very good trend analysis.&nbsp; </DIV>
<DIV>Kathy </DIV></BODY></HTML>

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Date:         Mon, 21 Jan 2002 12:35:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Creswick, Steven" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Creswick, Steven" <[log in to unmask]>
Subject:      Re: Silver component contamination
X-To:         Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

And to top it off, just how consisent is the batch to batch mix of chemicals
going into the markers?  If I qualify a marker today, does that mean nothing
has changed 6 months from now??

I agree with Brian's "trust, but verify"

Steven Creswick - Gentex Corp

-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Saturday, January 19, 2002 3:21 AM
To: [log in to unmask]
Subject: Re: [TN] Silver component contamination


Genny

The innocuousness or otherwise of markers is a subject that comes up
from time to time. The alcohols you mention are of no concern as they
evaporate completely. It is what is left behind that may be. This
consists of some form of polymer, dyes and pigments. As a rule, most
polymers are probably fairly benign unless they are hygroscopic (as can
happen). As for the pigments, I'd be rather wary of black markers,
because the pigment is almost surely carbon black (a form of very fine
soot formed by burning petroleum derived gases/vapours under controlled
conditions without admixture of oxygen). The same carbon black is also
used for making cheap and nasty resistors - need I say more? Pigments
derived from natural earths are usually harmless. Synthetic ones and
dyes may be less so, especially if they are not chemically or physically
stable. There is therefore a risk in using any marker and their use must
be qualified after practical lab trials - and never change the
manufacturer or type without requalification.

As for cleaning marker marks: again qualification is the only way of
finding out whether a process is safe. Remember that you may remove some
components of the ink yet leave others, which may be invisible but
electrically malign. Above all, remember that some markers will actually
penetrate the surface of some items, especially polymers, making it
impossible to clean away.

Conclusion: test and see, but be mistrustful.

Brian

Genny Gibbard wrote:
>
> Happy Friday! (tappity, tappity - doing the Friday dance)
> We have ceramic resonators with silver coating on several products.  We
> started handling those OEM boards with gloves during our test processes
> because the customer expressed concern with skin oil contamination.
> At times these components have been marked in house, for various reasons,
> with a standard sharpie marker.  In fact, at an early point in the
> production schedule, the CM we were using at the time was marking them on
> their own, because the resonators are so close in size they were having
> trouble telling them apart and getting them installed in the right
locations
> (due to tight time requirements, we got a shipment of bulk parts that were
> being placed by hand).  The marks looked like they were marker applied and
> used a variety of dot and line patterns in various colours.  We have never
> noticed any harmful effect on their response, although build quantities
were
> low.
> Now someone on our production floor is asking whether the ink may be a
> contamination that we should avoid.  We have easily cleaned this marker
off
> of other surfaces with board wash.  They wanted to know if they should
clean
> the components with board wash.  I think that if the marker is already on
> there and a contaminant, don't compound it by rubbing board wash on it.
> >From what I can tell, from the MSDS on the marker website, the ink is
> primarily propanol/butanol/alcohol based.  The board wash is alcohol
based.
> Chemistry is my weak subject.  Is alcohol - related substances on silver
> coated components a concern?
>
> Genny Gibbard (mailto:[log in to unmask])
> Product Transition and Support
> Wavecom Electronics Inc.
> 202 Cardinal Crescent
> Saskatoon, SK, Canada
> ph:     (306) 955-7075 ext. 229
> fax:    (306)384-0086
>
>
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Date:         Mon, 21 Jan 2002 12:04:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Silver component contamination
X-To:         S Creswick <[log in to unmask]>

I'll go with evaluate, qualify, and re-evaluate. Trust, never.

MoonMan

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Date:         Mon, 21 Jan 2002 11:45:30 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      WS Solder Mask for Stencil Applications
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Fellow Technetters,

        I am looking for a water soluble solder mask that can be compatible
with stencil applications. We do quite a lot of solder mask applications
with a dispensing machine, but I am really looking into using a stencil
since it would speed up the process and help the ability to apply thinner SM
layers. I tried to do it with the one we use on the dispensing machines, but
it's too liquid and starts to cure at ambient temperature after 30 minutes,
so it was not possible.

        Ha anybody accomplished this? Would there be a special WS solder
mask for stencil applications?


        Any comments would be appreciated

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 21 Jan 2002 11:59:03 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Vertefeuille, Russell (AZ77)"
              <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Vertefeuille, Russell (AZ77)"
              <[log in to unmask]>
Subject:      Re: WS Solder Mask for Stencil Applications
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Jorge, have you considered using a UV curable mask?

Russ Vertefeuille

Supplier Quality & Development Engineer

Honeywell International
Business, Regional & General Aviation
5353 West Bell Road
Glendale, AZ 85308

602-436-5434  Phone
602-436-7600  Fax
602-549-1417  Cell


-----Original Message-----
From: Jorge Rodriguez [mailto:[log in to unmask]]
Sent: Monday, January 21, 2002 11:46 AM
To: [log in to unmask]
Subject: [TN] WS Solder Mask for Stencil Applications


Fellow Technetters,

        I am looking for a water soluble solder mask that can be compatible
with stencil applications. We do quite a lot of solder mask applications
with a dispensing machine, but I am really looking into using a stencil
since it would speed up the process and help the ability to apply thinner SM
layers. I tried to do it with the one we use on the dispensing machines, but
it's too liquid and starts to cure at ambient temperature after 30 minutes,
so it was not possible.

        Ha anybody accomplished this? Would there be a special WS solder
mask for stencil applications?


        Any comments would be appreciated

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 21 Jan 2002 12:43:27 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Barry Gallegos <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Label Applications
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Good Day,

I have been tasked to par-take in a team effort to identify different
application methods for
labeling. any directions or help would be appreciated.

Barry.

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Date:         Mon, 21 Jan 2002 12:58:50 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Re: Label Applications
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Barry,

        Amistar has a automatic label placer, Dataplace 100LP, you may want
to take a look at that.

Jorge

-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Monday, January 21, 2002 12:43 PM
To: [log in to unmask]
Subject: [TN] Label Applications


Good Day,

I have been tasked to par-take in a team effort to identify different
application methods for
labeling. any directions or help would be appreciated.

Barry.

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Date:         Mon, 21 Jan 2002 15:06:47 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Label Applications
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_bd.1aa3e834.297dced7_boundary"

--part1_bd.1aa3e834.297dced7_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Barry!

I notice that you have Universal and Fuji pick and place machines, so you are
in luck!
Go to:

http://www.hoverdavis.com/HDpages1/labelfeedindex.html

and you'll see that they make a label feeder that goes into your pick and
place machines...pretty cool. I've seen them at trade shows, they do indeed
work!

I just wish they made them for Philips...er, I mean Assembleon machines.

-Steve Gregory-


> Good Day,
>
> I have been tasked to par-take in a team effort to identify different
> application methods for
> labeling. any directions or help would be appreciated.
>
> Barry.
>



--part1_bd.1aa3e834.297dced7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Barry!
<BR>
<BR>I notice that you have Universal and Fuji pick and place machines, so you are in luck!
<BR>Go to:
<BR>
<BR>http://www.hoverdavis.com/HDpages1/labelfeedindex.html
<BR>
<BR>and you'll see that they make a label feeder that goes into your pick and place machines...pretty cool. I've seen them at trade shows, they do indeed work!
<BR>
<BR>I just wish they made them for Philips...er, I mean Assembleon machines.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Good Day,
<BR>
<BR>I have been tasked to par-take in a team effort to identify different
<BR>application methods for
<BR>labeling. any directions or help would be appreciated.
<BR>
<BR>Barry.
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_bd.1aa3e834.297dced7_boundary--

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Date:         Mon, 21 Jan 2002 15:49:23 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Danny W. Harkins" <[log in to unmask]>
Subject:      Parts with 100% Tin finish
MIME-Version: 1.0
Content-Type: multipart/mixed;
              boundary="----=_NextPartTM-000-f3f57565-0ea9-11d6-b131-00508be26895"

This is a multipart message in MIME format.
------=_NextPartTM-000-f3f57565-0ea9-11d6-b131-00508be26895
Content-Type: multipart/alternative;
        boundary="=_alternative 0071CEAB85256B48_="

--=_alternative 0071CEAB85256B48_=
Content-Type: text/plain; charset="us-ascii"


Greetings,

I have a concern and would like your feedback. Analog Devices is
switching over to Lead-Free finishes (100%Sn) on their SOIC parts. We
are using a 63/37 no clean and I am curious about what type of problems
might occur if any. Is anyone currently using any Tin plated parts with
their 63/37 solder process? Did you have to change the paste or reflow?
Thanks,

Danny Harkins
CSI

--=_alternative 0071CEAB85256B48_=
Content-Type: text/html; charset="us-ascii"


<br><font size=2 face="sans-serif">Greetings,</font>
<br>
<br><font size=2 face="sans-serif">I have a concern and would like your feedback. Analog Devices is switching over to Lead-Free finishes (100%Sn) on their SOIC parts. We are using a 63/37 no clean and I am curious about what type of problems might occur if any. Is anyone currently using any Tin plated parts with their 63/37 solder process? Did you have to change the paste or reflow?</font>
<br><font size=2 face="sans-serif">Thanks,</font>
<br>
<br><font size=2 face="sans-serif">Danny Harkins</font>
<br><font size=2 face="sans-serif">CSI</font>
--=_alternative 0071CEAB85256B48_=--

------=_NextPartTM-000-f3f57565-0ea9-11d6-b131-00508be26895--

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Date:         Mon, 21 Jan 2002 14:18:43 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Barmuta, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Barmuta, Mike" <[log in to unmask]>
Subject:      Re: WS Solder Mask for Stencil Applications
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Jorge: We apply water soluble temporary soldermask (TSR)using screen
printing instead of true stencils. The screens are about 1/10 the cost of a
stencil so you don't tie up a lot of dollars in stencil inventory. Unlike
stencils which are permanent the image can be washed out and the screen
re-imaged if there is a rev change or if you just want to use it on a
different P/N.

We use a contract service to mount/stretch and image the screens, most can
work from Gerber or film.

The screens use an aluminum chase with a 60 mesh polyester screen fabric.

The TSR is applied using a 60 durometer urethane squeegee.

Curing can be done at room temp 6-12hrs or accelerated be baking, 130C 5
mins.

The TSR material is supplied by Saati America 800-766-3676. The product name
is Dorn Temporary Solder Mask.
It is actually manufactured by Cerulean Blue Ltd. 206-525-8992. This used to
be an Alpha Metals product called HV-110 which was the screenable version of
there 110 water soluble TSR product family.

The TSR does not contain insoluble fillers such as clay, fumed silica etc,
which can clog wash nozzles build up in tank sumps or wear out pump seals on
aqueous washers.


Regards

Michael Barmuta

Staff Engineer

Fluke Corp.

Everett WA

425-446-6076
-----Original Message-----
From: Jorge Rodriguez [mailto:[log in to unmask]]
Sent: Monday, January 21, 2002 10:46 AM
To: [log in to unmask]
Subject: [TN] WS Solder Mask for Stencil Applications


Fellow Technetters,

        I am looking for a water soluble solder mask that can be compatible
with stencil applications. We do quite a lot of solder mask applications
with a dispensing machine, but I am really looking into using a stencil
since it would speed up the process and help the ability to apply thinner SM
layers. I tried to do it with the one we use on the dispensing machines, but
it's too liquid and starts to cure at ambient temperature after 30 minutes,
so it was not possible.

        Ha anybody accomplished this? Would there be a special WS solder
mask for stencil applications?


        Any comments would be appreciated

Jorge Rodriguez
Process Engineer
Varian Electronics Manufacturing
615 South River Drive
Tempe, AZ 85281
Phone: (480) 968-6790 X 4258
Fax: (480) 829-4000
E-mail: [log in to unmask]

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Date:         Mon, 21 Jan 2002 17:22:59 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McCabe, Chris" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McCabe, Chris" <[log in to unmask]>
Subject:      Re: Label Applications
X-To:         Barry Gallegos <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Barry,

Questions that would help us:

        What information is on the label (data/human readable)
        What step in the process are you going to apply the label? (If you
want to read the label at the beginning of the process, you are looking at a
material like kapton, etc)
        Size - do you have room for a 1D label, or will you use 2D (Data
Matrix)
Are you labeling panelized boards? If so, will you serialize the panel and
each individual board?
Are you open to other technologies, like Laser-etch, laser-bonding,
Continuous Ink Jet, etc

We evaluated several serialization options and have chosen to go with laser
etching a 2D data matrix serial number on our boards.

Regards,
Chris

 -----Original Message-----
From:   Barry Gallegos [mailto:[log in to unmask]]
Sent:   Monday, January 21, 2002 2:43 PM
To:     [log in to unmask]
Subject:        [TN] Label Applications

Good Day,

I have been tasked to par-take in a team effort to identify different
application methods for
labeling. any directions or help would be appreciated.

Barry.

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=========================================================================
Date:         Tue, 22 Jan 2002 09:16:33 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Parts with 100% Tin finish
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Danny

We don't run a production. However, in our project LEADFREE we tried =
SnPb36Ag2 in convection and SnPb37 in wave with tin plated components on =
pure tin PCB's and we didn't see any problems when using the standard =
profile our industrial partners suggested.
From the point of reliability I don't see any problem since you don't =
bring any new material into the solder joint and the amount of tin added =
to the solder is not a big deal.

Best regards

Guenter

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Tue, 22 Jan 2002 08:53:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Schwarzkopf, Todd" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Schwarzkopf, Todd" <[log in to unmask]>
Subject:      Smoky Mountain IPC Designer's Council January Meeting
X-To:         [log in to unmask]
X-cc:         [log in to unmask]
MIME-Version: 1.0
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Smoky Mountain IPC Designer's Council January Meeting:
Our next meeting will be January 24th.  It will be held at Philips
(directions below).  The speaker and sponsor will be Bob Hoffman with
Amitron Corporation.  Take a look at their web site at www.amitroncorp.com
<http://www.amitroncorp.com>  <http://www.amitroncorp.com
<http://www.amitroncorp.com> > .
Here is a list of topics:
                Eductor Plating Technology
                Ionic Contamination on Bare Boards
                Liquid Photo-Mask Applications for BGAs and/or QFPs
                Aluminum Bonded Heat Sink Substrates
                10 - 18 Multi-Layer PCB Construction

Agenda:
        6:00pm to 7:00pm - Dinner (pizza) and social hour.
        7:00pm - 9:00pm - Chapter business followed by a presentation by Bob
Hoffman from Amitron.

This should be a very informative meeting.  I hope to see you there.

Directions from Knoxville,
        I-40 East (toward Asheville)
        Take Strawberry Plains Pike Exit (Exit 398)
        Turn right on Strawberry Plains Pike
        Go .37 miles to One Philips Drive.
                There will be a security gate. State your name and business.
The guard will open the gate.
                Someone will meet you in the main lobby.




Please RSVP to me by Email by Wednesday at the latest.


Todd Schwarzkopf, C.I.D.
PCB Designer
AMETEK
Advanced Measurement Technology
801 S. Illinois Ave.
Oak Ridge, TN  37831-0895
[log in to unmask]
Voice:  (865) 481-2427
Fax:     (865) 481-2438

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Date:         Tue, 22 Jan 2002 08:12:09 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Barry Gallegos <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Wire Harness & Cable Standards.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.


Barry.

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Date:         Tue, 22 Jan 2002 07:55:22 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

let me refer you to an email from j. crawford that should help you.  i've copied and pasted it below.

phil


IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness Assemblies is progressing well.  It is projected to be circulated as a Proposed Standard within a week pending some last minute tweaks. The goal is still to have it published this year.

You can download review files from the IPC public FTP site using a standard browser (but NOT the AOL built-in browser).  Just launch your Netscape or Internet Explorer (if using AOL, log on first, THEN launch one of the browsers and everything will work fine).  In the URL Address line, put ONLY the following numbers.  DO NOT PUT ANY LETTERS like www or anything:  216.203.210.37

You'll see a folder called 620-WireDocs.  Open it and you'll see the files.  Start with 620-01 for an index and document scope.  Send comments to me directly (OFF NET). Some chapters have both high and low resolution illustrations.  Content is the same, high resolution files have better quality pictures but take longer to download with a slow modem connection.

Hope this helps.
Jack

-----Original Message-----
From: Barry Gallegos [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 7:12 AM
To: [log in to unmask]
Subject: [TN] Wire Harness & Cable Standards.


Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.


Barry.

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=========================================================================
Date:         Tue, 22 Jan 2002 10:59:35 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Sauer, Steven T." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Sauer, Steven T." <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
X-To:         Barry Gallegos <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Barry,
NASA-STD-8739.4 dtd February 1998 (replaced NAS 5300.4(3G-1))
IPC/WHMA-A-620 (which is under development but a good reference)
SAE AS4461 (I have rev A dtd 12/30/92)
Hope this helps!

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.


Barry.

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=========================================================================
Date:         Tue, 22 Jan 2002 08:13:35 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: WS Solder Mask for Stencil Applications
X-To:         [log in to unmask]
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT

I have used Wondermask from Techspray, #2207-p. It is billed as a screenable
water soluble mask. I used a standard stencil, .005" thick, after curing for
30 min at 150F the solder paste was stenciled onto the assembly. After
reflow the assemblies were washed and the I/O pins hand soldered, no
problems with solderability.
Dan

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=========================================================================
Date:         Tue, 22 Jan 2002 11:54:36 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Sauer, Steven T." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Sauer, Steven T." <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
X-To:         "Crepeau, Phil" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed.  Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week.  I have the
620 files dated Mar-01.  To your knowledge, what are the revision/date of
the latest released working drafts?  Thanks in advance.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well.  It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal is
still to have it published this year.

You can download review files from the IPC public FTP site using a standard
browser (but NOT the AOL built-in browser).  Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine).  In the URL Address line, put ONLY
the following numbers.  DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37

You'll see a folder called 620-WireDocs.  Open it and you'll see the files.
Start with 620-01 for an index and document scope.  Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations.  Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.

---------------------------------------------------------------------------------
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=========================================================================
Date:         Tue, 22 Jan 2002 12:10:54 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Truit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Truit <[log in to unmask]>
Organization: RBB Systems Inc.
Subject:      Solder fill of via's and reliability
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.

I am seeing more and more designs with the vias covered.  Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA?  Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process?  Expecting .001" but getting
.0007-.0008" copper plating.

Should via's be left uncovered?

Respectfully

Paul


--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH  44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]

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=========================================================================
Date:         Tue, 22 Jan 2002 11:38:29 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jorge Rodriguez <[log in to unmask]>
Subject:      Re: Solder fill of via's and reliability
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Paul,

        The need of solder mask when dealing with wave solder and SMT is to
prevent flux entrapment. This can happen when vias are found underneath SMT
devices. The other concern is the heat transfer to the top side under the
same conditions. We are currently facing a problem with a customer that
likes to use 25 mils vias under fine pitch devices. This is causing some
issues at the wave solder operation, the QFPs re-melt again creating solder
opens. The alternative of reducing the temperature at the preheaters doesn't
solve the problem since we face another one, flux doesn't get activated and
we end up with solder balls on the top side, solvents get entrapped on the
vias and explode at the wave like a volcano.

Jorge

-----Original Message-----
From: Paul Truit [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 10:11 AM
To: [log in to unmask]
Subject: [TN] Solder fill of via's and reliability


I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.

I am seeing more and more designs with the vias covered.  Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA?  Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process?  Expecting .001" but getting
.0007-.0008" copper plating.

Should via's be left uncovered?

Respectfully

Paul


--
Paul Truit, Mfg. Eng.
RBB Systems, Inc.
4265C E. Lincolnway
Wooster, OH  44691
Ph. (330) 567-2906 ext 514
Fax (330) 263-5324
Email: [log in to unmask]

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=========================================================================
Date:         Tue, 22 Jan 2002 14:02:57 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Sauer, Steven T." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Sauer, Steven T." <[log in to unmask]>
Subject:      Re: Solder fill of via's and reliability
X-To:         Paul Truit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Paul,
Years ago, the military high reliability soldering standards required PTHs
to be filled with a solder plug (wave soldered only, 25% recession
acceptable) or wire (swaged stud or clinched "C" or "Z" form) soldered in
the holes of type of 2 and 3 printed wiring boards.
After extensive testing and evaluation (data was also presented to the
military folks by industry), it was determined that the via holes could be
left unsoldered without compromising reliability of the interconnection.
The one drawback is partial fill of these via holes, when subjected to
stress and strain, the forces imparted on the PTH structure are not equally
distributed.  As such, this can cause the PTH to fail prematurely.  As such,
it is better to either fully fill the hole or leave the hold unfilled.
With respect to tenting of vias, I look at the following factors:
        gasketing during in-circuit testing
        minimize the amount of exposed conductive circuitry
                - shorting potential
                - cleaning challenges
In light of the above, it all depends on your end item application and
environment.  If you're worried about the reliability of your holes with
respect to wall thickness, I would specify what you want to your supplier
and then verify.  As Moonman says, "specify, verify and never trust".  The
only time that I would leave PTHs uncovered would be for test purposes, but
I would normally specify pads/targets for test points.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
I am interested in hearing others views in regard to allowing the wave
soldering process to fill the vias with solder or tenting the vias with
soldermask and how this relates to reliability.

I am seeing more and more designs with the vias covered.  Wouldn't
allowing the vias to fill with solder increase the reliability of the
PCA?  Or is this a matter of covering for the "sins" of the bare board
manufacturer's plating process?  Expecting .001" but getting
.0007-.0008" copper plating.

Should via's be left uncovered?

---------------------------------------------------------------------------------
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=========================================================================
Date:         Tue, 22 Jan 2002 15:00:43 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rob Legg <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rob Legg <[log in to unmask]>
Subject:      Re: Solder fill of via's and reliability
X-To:         Paul Truit <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Vias may rob adjacent SJ if not masked.

That's the only justifiable beef I've had that forces masking. Unmasked vias
are just artifacts of CAD SW, unless used for ICT points.

RL

----- Original Message -----
From: Paul Truit <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 22, 2002 9:10 AM
Subject: [TN] Solder fill of via's and reliability


> I am interested in hearing others views in regard to allowing the wave
> soldering process to fill the vias with solder or tenting the vias with
> soldermask and how this relates to reliability.
>
> I am seeing more and more designs with the vias covered.  Wouldn't
> allowing the vias to fill with solder increase the reliability of the
> PCA?  Or is this a matter of covering for the "sins" of the bare board
> manufacturer's plating process?  Expecting .001" but getting
> .0007-.0008" copper plating.
>
> Should via's be left uncovered?
>
> Respectfully
>
> Paul
>
>
> --
> Paul Truit, Mfg. Eng.
> RBB Systems, Inc.
> 4265C E. Lincolnway
> Wooster, OH  44691
> Ph. (330) 567-2906 ext 514
> Fax (330) 263-5324
> Email: [log in to unmask]
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>

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=========================================================================
Date:         Tue, 22 Jan 2002 13:03:29 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Barry Gallegos <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
X-To:         "Sauer, Steven T." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Thank you All for your help.

Barry.

-----Original Message-----
From: Sauer, Steven T. [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 9:55 AM
To: [log in to unmask]
Subject: Re: [TN] Wire Harness & Cable Standards.


Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed.  Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week.  I have the
620 files dated Mar-01.  To your knowledge, what are the revision/date of
the latest released working drafts?  Thanks in advance.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well.  It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal is
still to have it published this year.

You can download review files from the IPC public FTP site using a standard
browser (but NOT the AOL built-in browser).  Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine).  In the URL Address line, put ONLY
the following numbers.  DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37

You'll see a folder called 620-WireDocs.  Open it and you'll see the files.
Start with 620-01 for an index and document scope.  Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations.  Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.

----------------------------------------------------------------------------
-----
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=========================================================================
Date:         Tue, 22 Jan 2002 16:02:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rob Legg <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rob Legg <[log in to unmask]>
Subject:      Re: FR4 power module SMC coplanarity
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Any option must be known good before hardware is designed. I don't design
for the trash can.

Am aware of BT material option. We are currently ceramic with no problems,
with much push from high-priced-help to migrate to FR4 ' like everybody
else'. Of course there are no concrete examples of SMD in FR4 forthcoming,
but that doesn't reduce push from above. They would need a documented
disaster story to decide that they knew, all along, it was a bad idea.

Question is to actual performance of FR4 modules with dims equal to or
exceeding 2inches on one side. Any feedback of simple successes/niggling
problems?

Is 0.1millimeter/ .004inch achievable and how?

RL
----- Original Message -----
From: Earl Moon <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, January 21, 2002 5:24 AM
Subject: Re: [TN] FR4 power module SMC coplanarity


> First let me say Eric must know the lady about whom I speak. Ouch!
>
> Concerning a more vital, doubt it, issue, there is no reason to expect the
> PCB version, on whatever material, will go out of whack like a potato
chip.
> BGA's are built on BT based boards and they stay reasonably flat.
>
> You know it depends on how well the design was effected. You know -
balance,
> construction, etc.
>
> Just have to try them and see. If they do warp, what are your options?
>
> MoonMan
>
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Date:         Tue, 22 Jan 2002 15:54:43 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mike Manwell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mike Manwell <[log in to unmask]>
Subject:      Solder Analysis

Hello folks,

Im looking for a facility that does solder sample analysis.
Im aware of Alpha Analytical Laboratories but before signing up, cant help
but wonder if there are others out there.
Any suggestions?

Thanks,
Mike Manwell
Integrex Inc.

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Date:         Tue, 22 Jan 2002 17:42:15 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: FR4 power module SMC coplanarity
X-To:         R Legg <[log in to unmask]>

I hope we're on the same page. I agree FR4 material should be adequate. BT
offers higher Tg but other characteristice remain the same. That doesn't
matter but for longer z axis expansion duration before delam and total
failure. From a warpage standpoint, is what I'm talking about as I thought
you were. No offense intended. I was trying to back you up.

MoonMan

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Date:         Tue, 22 Jan 2002 17:44:46 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Solder fill of via's and reliability
X-To:         R Legg <[log in to unmask]>

I'm currently going down this path - especially pertaining to BGA's, ICT,
and functional testing requirements. Everyone thoroubhly read the test
requirements in 2221?

MoonMan

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Date:         Tue, 22 Jan 2002 17:48:07 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      ASSEMBLED BOARD IPC TEST REQUIREMENTS

Never would I question the IPC wisdom concerning anything. I would question
how the heck does one find specific guidelines cocnerning assembled board
requirements? The search engine just didn't get it for me.

What is the guideline, beyond 2221, for loaded board testing as ICT and
functional test requirements?

MoonMan

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Date:         Tue, 22 Jan 2002 19:14:59 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Solder Analysis
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_179.286a608.297f5a83_boundary"

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Content-Type: text/plain; charset="US-ASCII"
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Mike,
       I know that besides Alpha, Shipley does and so does my company,
Florida CirTech.  All companies provide a high quality bar solder and should
provide free analysis.  The price of tin is down now so you should see prices
for bar solder around the low $2/lb or less depending on usage.

Steve Wentz

--part1_179.286a608.297f5a83_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Mike,
<BR> &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;I know that besides Alpha, Shipley does and so does my company, Florida CirTech. &nbsp;All companies provide a high quality bar solder and should provide free analysis. &nbsp;The price of tin is down now so you should see prices for bar solder around the low $2/lb or less depending on usage.
<BR>
<BR>Steve Wentz</FONT></HTML>

--part1_179.286a608.297f5a83_boundary--

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Date:         Wed, 23 Jan 2002 08:27:05 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
X-To:         Barry Gallegos <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Barry,

Don't know your required standard, but the two specs I know of are
MIL-C-45224 (General Spec for Cables and Assemblies, Electrical Missile
System) [This extends to other equipment wiring as well], and MIL-W-5088L
(Wiring, Aerospace Vehicle) [which deals more specifically with aircraft
wiring systems].

Hope this is of some use.

Peter




                    Barry Gallegos
                    <barryg@WESTERNELECTR        To:     [log in to unmask]
                    ONICS.COM>                   cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet             Aero/ST Group)
                    <[log in to unmask]>            Subject:     [TN] Wire Harness & Cable Standards.


                    01/22/02 11:12 PM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Barry
                    Gallegos






Is there any one that can point me in the direction of standards for Wire
Harnessing & Cabling.


Barry.

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Date:         Tue, 22 Jan 2002 16:21:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Thorup, John" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: Solder Analysis
X-To:         Mike Manwell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

among others, the Kester mail in kits are available from any Kester
distributor.  You choose your desired level of analysis, pay for it, and
receive a mailer pack with a coupon to submit your sample.  A certified
computerized analysis is returned in a week to 10 days.

> -----Original Message-----
> From: Mike Manwell [SMTP:[log in to unmask]]
> Sent: Tuesday, January 22, 2002 1:55 PM
> To:   [log in to unmask]
> Subject:      [TN] Solder Analysis
>
> Hello folks,
>
> Im looking for a facility that does solder sample analysis.
> Im aware of Alpha Analytical Laboratories but before signing up, cant help
> but wonder if there are others out there.
> Any suggestions?
>
> Thanks,
> Mike Manwell
> Integrex Inc.
>
> --------------------------------------------------------------------------
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Date:         Tue, 22 Jan 2002 19:33:07 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards.
Mime-Version: 1.0
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Hi Phil / Steve / Barry
The IPC 620 document is released. I'm standing about 100 feet from the IPC =
booth and just checked it out, going to buy a copy but I already have the =
400 lb proceedings book to carry around today.

>>> [log in to unmask] 01/22/02 12:56 PM >>>
Hi Phil,
I just followed the FTP connection and the 620-Wiredocs directory (or
anything similar) isn't listed.  Not sure what happened but maybe Jack can
shed some light on the subject after his escapades this week.  I have the
620 files dated Mar-01.  To your knowledge, what are the revision/date of
the latest released working drafts?  Thanks in advance.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
IPC/WHMA-A-620 Acceptability and Requirements for Cable/Wire Harness
Assemblies is progressing well.  It is projected to be circulated as a
Proposed Standard within a week pending some last minute tweaks. The goal =
is
still to have it published this year.

You can download review files from the IPC public FTP site using a =
standard
browser (but NOT the AOL built-in browser).  Just launch your Netscape or
Internet Explorer (if using AOL, log on first, THEN launch one of the
browsers and everything will work fine).  In the URL Address line, put =
ONLY
the following numbers.  DO NOT PUT ANY LETTERS like www or anything:
216.203.210.37

You'll see a folder called 620-WireDocs.  Open it and you'll see the =
files.
Start with 620-01 for an index and document scope.  Send comments to me
directly (OFF NET). Some chapters have both high and low resolution
illustrations.  Content is the same, high resolution files have better
quality pictures but take longer to download with a slow modem connection.

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---------------------------------------------------------------------------=
------

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Date:         Wed, 23 Jan 2002 11:53:42 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Colin Weber <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Colin Weber <[log in to unmask]>
Subject:      D-Range & EMI
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Folks,

Does anyone know of any D-Range connectors with in-built, In line RF filtering?

Regards,

Colin Weber

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Date:         Tue, 22 Jan 2002 20:17:33 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: Wire Harness & Cable Standards...and APEX stuff
MIME-Version: 1.0
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              boundary="part1_46.2143abeb.297f692d_boundary"

--part1_46.2143abeb.297f692d_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hey Graham!

Do they have all the computers along the wall that you can check your email
with (like last year)?

I think Mike Sewell told me that he was going to try and make the lunch with
you and Ed on Thursday (he's one of the lucky guys that was able to attend
this year from our plant). Ed is real familiar with us in Tulsa,
"Okra-homie", we bought a Treiber 700B wave solder from him, he came out to
help with the installation...ask him about it. There's a REALLY good story
there!

If you run into Mike Sewell, tell him that Steve said he should be glad he's
not here in Tulsa now, and enjoy the time he has away from the
plant...(hehehe).

Wish I was there, maybe next year...

-Steve Gregory-






> Hi Phil / Steve / Barry
> The IPC 620 document is released. I'm standing about 100 feet from the IPC
> booth and just checked it out, going to buy a copy but I already have the
> 400 lb proceedings book to carry around today.
>


--part1_46.2143abeb.297f692d_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hey Graham!<BR>
<BR>
Do they have all the computers along the wall that you can check your email with (like last year)?<BR>
<BR>
I think Mike Sewell told me that he was going to try and make the lunch with you and Ed on Thursday (he's one of the lucky guys that was able to attend this year from our plant). Ed is real familiar with us in Tulsa, "Okra-homie", we bought a Treiber 700B wave solder from him, he came out to help with the installation...ask him about it. There's a REALLY good story there!<BR>
<BR>
If you run into Mike Sewell, tell him that Steve said he should be glad he's not here in Tulsa now, and enjoy the time he has away from the plant...(hehehe).<BR>
<BR>
Wish I was there, maybe next year...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BR>
 <BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Phil / Steve / Barry<BR>
The IPC 620 document is released. I'm standing about 100 feet from the IPC booth and just checked it out, going to buy a copy but I already have the 400 lb proceedings book to carry around today.<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_46.2143abeb.297f692d_boundary--

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Date:         Tue, 22 Jan 2002 17:24:23 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: D-Range & EMI
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

don't know 'd-range', but if that's the same as 'd-subminiature' try the following:

http://www.ittcannon.com/products/products.asp?pid=1005

phil

-----Original Message-----
From: Colin Weber [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] D-Range & EMI


Folks,

Does anyone know of any D-Range connectors with in-built, In line RF filtering?

Regards,

Colin Weber

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=========================================================================
Date:         Tue, 22 Jan 2002 21:41:52 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      VME stuff again...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hey all ya'll!

VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.

Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will comply
with VME  spec's.

This board is 16-layers, within .063" without Stablecor, if we use 2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
far as thermal dissapation and CTE solutions), it will increase .030-.035".

This Stablcor material sounds like a really good solution for thermal and CTE
solutions, but has a hard time staying within the dimensional spec's that are
called out in the VME spec's...trying to change these spec's I know is an act
of God...it's there, and it's done.

Just wondering if anybody else has explored this material, and have come to a
dead-end like I have....because of the reasons like I have.

-Steve Gregory-

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=========================================================================
Date:         Tue, 22 Jan 2002 21:07:55 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hugh Day <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hugh Day <[log in to unmask]>
Subject:      Re: Solder Analysis
X-To:         Mike Manwell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Mike,
Here is a real sleeper company that has been around for 100 years,
literally, the name of the company is Nathan Trotter & Co., Inc.
specializing in electronic grade alloys, tin products, and solder analysis.
The phone # is 610-524-1440
ask for Peter Morris.
----- Original Message -----
From: Mike Manwell <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 22, 2002 3:54 PM
Subject: [TN] Solder Analysis


> Hello folks,
>
> Im looking for a facility that does solder sample analysis.
> Im aware of Alpha Analytical Laboratories but before signing up, cant help
> but wonder if there are others out there.
> Any suggestions?
>
> Thanks,
> Mike Manwell
> Integrex Inc.
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>

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=========================================================================
Date:         Wed, 23 Jan 2002 11:36:34 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VME stuff again...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Steve,

We ran into the same problem (more or less) - thermal management
requirements and solutions conflicted with the VME spec (which spec did you
go with, by the way?).

One solution we considered, but didn't implement owing to expense, is to
"step" the PCB so that it's the right thickness at the card guide edges and
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
know. Makes routing traces to the connectors a bit circuitous too (pun
intended). The board thickness outwith these areas is not important, as
long as it, plus the component height, doesn't exceed the envelope max.

You'll need some pretty light-weight copper and very thin separation layers
to fit 16 layers into the spec'd thickness. Good luck!

Peter




                    Stephen
                    Gregory              To:     [log in to unmask]
                    <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    L.COM>               Aero/ST Group)
                    Sent by:             Subject:     [TN] VME stuff again...
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/23/02
                    10:41 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hey all ya'll!

VME stuff again. Pretty strict standard. Gotta new technology out there
called Stablcor from Thermalworks, problem that we're seeing is that board
thickness is going to increase, which violates the VME spec's. Not just
from
the card-guide aspects, but will change the dimension where the P1 and P2
connectors interface with the backplane on a standard VME card cage.

Just wondering if anybody has anything out there (connectors, etc.), that
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
comply
with VME  spec's.

This board is 16-layers, within .063" without Stablecor, if we use 2-layers
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
far as thermal dissapation and CTE solutions), it will increase .030-.035".

This Stablcor material sounds like a really good solution for thermal and
CTE
solutions, but has a hard time staying within the dimensional spec's that
are
called out in the VME spec's...trying to change these spec's I know is an
act
of God...it's there, and it's done.

Just wondering if anybody else has explored this material, and have come to
a
dead-end like I have....because of the reasons like I have.

-Steve Gregory-

---------------------------------------------------------------------------------

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---------------------------------------------------------------------------------
=========================================================================
Date:         Tue, 22 Jan 2002 23:19:10 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Stephen Gregory <[log in to unmask]>
Subject:      Re: VME stuff again...
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_da.12886cfe.297f93be_boundary"

--part1_da.12886cfe.297f93be_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Peter!

The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.

From a personal view, I think that VITA established the standards prematurely
without considering how the the technology was going to evolove. As you know,
VME assemblies are extremely dense, basically single board computers.

The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so far
from the BOM).

Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...

Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat dissipation,
and CTE  issues, but can't use it because of the VME spec...this is one of
what came first, "The chicken or the egg?" huh?

-Steve Gregory-


> Hi, Steve,
>
> We ran into the same problem (more or less) - thermal management
> requirements and solutions conflicted with the VME spec (which spec did you
> go with, by the way?).
>
> One solution we considered, but didn't implement owing to expense, is to
> "step" the PCB so that it's the right thickness at the card guide edges and
> at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
> know. Makes routing traces to the connectors a bit circuitous too (pun
> intended). The board thickness outwith these areas is not important, as
> long as it, plus the component height, doesn't exceed the envelope max.
>
> You'll need some pretty light-weight copper and very thin separation layers
> to fit 16 layers into the spec'd thickness. Good luck!
>
> Peter
>
>
>
>
>                     Stephen
>                     Gregory              To:     [log in to unmask]
>                     <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
>                     L.COM>               Aero/ST Group)
>                     Sent by:             Subject:     [TN] VME stuff
> again...
>                     TechNet
>                     <[log in to unmask]
>                     ORG>
>
>
>                     01/23/02
>                     10:41 AM
>                     Please
>                     respond to
>                     "TechNet
>                     E-Mail
>                     Forum.";
>                     Please
>                     respond to
>                     SteveZeva
>
>
>
>
>
>
> Hey all ya'll!
>
> VME stuff again. Pretty strict standard. Gotta new technology out there
> called Stablcor from Thermalworks, problem that we're seeing is that board
> thickness is going to increase, which violates the VME spec's. Not just
> from
> the card-guide aspects, but will change the dimension where the P1 and P2
> connectors interface with the backplane on a standard VME card cage.
>
> Just wondering if anybody has anything out there (connectors, etc.), that
> will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
> comply
> with VME  spec's.
>
> This board is 16-layers, within .063" without Stablecor, if we use 2-layers
> Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as
> far as thermal dissapation and CTE solutions), it will increase .030-.035".
>
> This Stablcor material sounds like a really good solution for thermal and
> CTE
> solutions, but has a hard time staying within the dimensional spec's that
> are
> called out in the VME spec's...trying to change these spec's I know is an
> act
> of God...it's there, and it's done.
>
> Just wondering if anybody else has explored this material, and have come to
> a
> dead-end like I have....because of the reasons like I have.
>
> -Steve Gregory-
>


--part1_da.12886cfe.297f93be_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Peter!<BR>
<BR>
The spec that you quoted, is what is being followed. I'm going to purchase the spec so that we have it here...since it appears that we're getting into the business of "ruggedizing" commercial VME assemblies.<BR>
<BR>
From a personal view, I think that VITA established the standards prematurely without considering how the the technology was going to evolove. As you know, VME assemblies are extremely dense, basically single board computers. <BR>
<BR>
The assembly that I'm looking at is double-sided SMT, fine pitch on both sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so far from the BOM).<BR>
<BR>
Not sure if establishing these restrictions are a good thing, so that everything will fit as established, or if it's better to stay fluid so that you can adjust to adapt to changes in the technology...I suppose there's arguments on both sides...<BR>
<BR>
Just know now that we have an assembly that can take advantage of some new substrate technology, that sounds very promising as far as heat dissipation, and CTE&nbsp; issues, but can't use it because of the VME spec...this is one of what came first, "The chicken or the egg?" huh?<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi, Steve,<BR>
<BR>
We ran into the same problem (more or less) - thermal management<BR>
requirements and solutions conflicted with the VME spec (which spec did you<BR>
go with, by the way?).<BR>
<BR>
One solution we considered, but didn't implement owing to expense, is to<BR>
"step" the PCB so that it's the right thickness at the card guide edges and<BR>
at the P1/P2 connector areas. Is that possible with Stablcor? - I don't<BR>
know. Makes routing traces to the connectors a bit circuitous too (pun<BR>
intended). The board thickness outwith these areas is not important, as<BR>
long as it, plus the component height, doesn't exceed the envelope max.<BR>
<BR>
You'll need some pretty light-weight copper and very thin separation layers<BR>
to fit 16 layers into the spec'd thickness. Good luck!<BR>
<BR>
Peter<BR>
<BR>
<BR>
<BR>
<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Stephen<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Gregory&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;SteveZeva@AO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cc:&nbsp;&nbsp;&nbsp;&nbsp; (bcc: DUNCAN Peter/Asst Prin Engr/ST<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; L.COM&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Aero/ST Group)<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent by:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject:&nbsp;&nbsp;&nbsp;&nbsp; [TN] VME stuff again...<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; TechNet<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;[log in to unmask]<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ORG&gt;<BR>
<BR>
<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 01/23/02<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 10:41 AM<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; respond to<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "TechNet<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; E-Mail<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Forum.";<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; respond to<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SteveZeva<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
Hey all ya'll!<BR>
<BR>
VME stuff again. Pretty strict standard. Gotta new technology out there<BR>
called Stablcor from Thermalworks, problem that we're seeing is that board<BR>
thickness is going to increase, which violates the VME spec's. Not just<BR>
from<BR>
the card-guide aspects, but will change the dimension where the P1 and P2<BR>
connectors interface with the backplane on a standard VME card cage.<BR>
<BR>
Just wondering if anybody has anything out there (connectors, etc.), that<BR>
will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will<BR>
comply<BR>
with VME&nbsp; spec's.<BR>
<BR>
This board is 16-layers, within .063" without Stablecor, if we use 2-layers<BR>
Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best, as<BR>
far as thermal dissapation and CTE solutions), it will increase .030-.035".<BR>
<BR>
This Stablcor material sounds like a really good solution for thermal and<BR>
CTE<BR>
solutions, but has a hard time staying within the dimensional spec's that<BR>
are<BR>
called out in the VME spec's...trying to change these spec's I know is an<BR>
act<BR>
of God...it's there, and it's done.<BR>
<BR>
Just wondering if anybody else has explored this material, and have come to<BR>
a<BR>
dead-end like I have....because of the reasons like I have.<BR>
<BR>
-Steve Gregory-<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_da.12886cfe.297f93be_boundary--

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---------------------------------------------------------------------------------
=========================================================================
Date:         Wed, 23 Jan 2002 12:51:26 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: VME stuff again...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi, Steve,

Sounds like you're having fun with this one, and I would be most interested
in being allowed to share your evolving experiences with trying to use
Stablcor. I flagged this material up to our designers when I first heard of
it (being simple souls, they'd designed our boards with good ol' FR4), but
we haven't had the excuse to look into using it yet.

The specs are now aging, and you're right about how densely packed the
boards have become, with folks trying to pack as much functionality into
each as humanly, or inhumanly, possible. I look at it as a cocoon within
which, and from which, any number of beautiful butterflies can grow and
emerge. (What DID that girl put in my coffee?) We have two boards on the go
that are a distillation of the functionality of five slots previously.
They've given me a folicular race between going grey or bald (it's neck and
neck at the moment).

The one thing we had to give serious priority to after the component
selection stage was layout to balance thermal mass around the board,
placing hotter components closest to the best thermal path through the
board, and particularly putting the hottest ones on the component side
where there was Max Headroom (remember him? I loved that guy). That way, if
the thermal path through the board is still not enough, you have some scope
for taking the heat out over the top with nice chunks of metal and thermal
pads. Pity there's no room for Pentium 4 style heatsinks here! There's no
room at all for overhead heat sinks on the solder side.

My sincerest sympathies!

Peter




                    Stephen
                    Gregory              To:     [log in to unmask]
                    <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    L.COM>               Aero/ST Group)
                    Sent by:             Subject:     Re: [TN] VME stuff again...
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/23/02
                    12:19 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hi Peter!

The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.

From a personal view, I think that VITA established the standards
prematurely without considering how the the technology was going to
evolove. As you know, VME assemblies are extremely dense, basically single
board computers.

The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so
far from the BOM).

Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...

Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat
dissipation, and CTE  issues, but can't use it because of the VME
spec...this is one of what came first, "The chicken or the egg?" huh?

-Steve Gregory-


 Hi, Steve,

 We ran into the same problem (more or less) - thermal management
 requirements and solutions conflicted with the VME spec (which spec did
 you
 go with, by the way?).

 One solution we considered, but didn't implement owing to expense, is to
 "step" the PCB so that it's the right thickness at the card guide edges
 and
 at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
 know. Makes routing traces to the connectors a bit circuitous too (pun
 intended). The board thickness outwith these areas is not important, as
 long as it, plus the component height, doesn't exceed the envelope max.

 You'll need some pretty light-weight copper and very thin separation
 layers
 to fit 16 layers into the spec'd thickness. Good luck!

 Peter




                     Stephen
                     Gregory              To:     [log in to unmask]
                     <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst
 Prin Engr/ST
                     L.COM>               Aero/ST Group)
                     Sent by:             Subject:     [TN] VME stuff
 again...
                     TechNet
                     <[log in to unmask]
                     ORG>


                     01/23/02
                     10:41 AM
                     Please
                     respond to
                     "TechNet
                     E-Mail
                     Forum.";
                     Please
                     respond to
                     SteveZeva






 Hey all ya'll!

 VME stuff again. Pretty strict standard. Gotta new technology out there
 called Stablcor from Thermalworks, problem that we're seeing is that board
 thickness is going to increase, which violates the VME spec's. Not just
 from
 the card-guide aspects, but will change the dimension where the P1 and P2
 connectors interface with the backplane on a standard VME card cage.

 Just wondering if anybody has anything out there (connectors, etc.), that
 will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
 comply
 with VME  spec's.

 This board is 16-layers, within .063" without Stablecor, if we use
 2-layers
 Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best,
 as
 far as thermal dissapation and CTE solutions), it will increase
 .030-.035".

 This Stablcor material sounds like a really good solution for thermal and
 CTE
 solutions, but has a hard time staying within the dimensional spec's that
 are
 called out in the VME spec's...trying to change these spec's I know is an
 act
 of God...it's there, and it's done.

 Just wondering if anybody else has explored this material, and have come
 to
 a
 dead-end like I have....because of the reasons like I have.

 -Steve Gregory-





[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date:         Wed, 23 Jan 2002 09:12:43 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Solder Analysis
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
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Mike

What kind of analysis, what region (US, GB...)


Best regards

Guenter

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Wed, 23 Jan 2002 08:11:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Sauer, Steven T." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Sauer, Steven T." <[log in to unmask]>
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Morning Earl,
The only thing I could find that remotely has to do with test is, IPC-6018A
"Microwave End Product Board Inspection and Test".  I'll keep looking and
forward what I find something that more closely matches your needs.
So you're going to add DFT to your DFM/CE?  Makes sense to be able to test
the darned thing after you've been able to manufacture the thing cost
effectively!!
I thought HP, GenRad, Everett Charles, etc., published testability design
guidelines -- some of which are pie in the sky (i.e. .080" target with .050"
clearance)?
Hope this helps.

Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron

-----Original Message-----
What is the guideline, beyond 2221, for loaded board testing as ICT and
functional test requirements?

MoonMan

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Date:         Wed, 23 Jan 2002 07:49:31 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         Steve Sauer <[log in to unmask]>

Steve,

Thanks, thought I was loosing it again not finding anything IPC related.

Yes about DFT as, to me, it is an integral part of DFM/CE.

I will use the test equipment recommendations only if IPC doesn't have
anything but what is in 2221.

Enjoy,

Earl

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Date:         Wed, 23 Jan 2002 07:40:55 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ahne Oosterhof <[log in to unmask]>
Subject:      Re: VME stuff again...
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

All this talk about getting rid of heat sounds scary. If I remember right,
these bus type frames, of which VME is only one, have a limited amount of
power available per card slot. If you exceed that, the other slots go
hungry, or you find yourself with a long-term power supply reliability
problem. To paint a blacker picture, most of the power supplies in these
boxes have specs that indicate they can deliver lots of power and they can
work at the resulting higher temperatures, but often they cannot do both
simultaneously!!
And a worse result is that all that input power turns into output heat. From
my experience heat is a serious problem in these boxes. It is a problem in
19" rackmount card cages in the first place to get the heat away from the
VME card, secondly to get it out of the VME box and in the third place to
get it out of the 19" rack (or where ever you put it).
A last thought: heat is often not a problem for today, it lets its presence
known in the future, so you end up with field failures: RELIABILITY.

Good luck with your investigations,
Ahne.

-----Original Message-----
From:   TechNet [mailto:[log in to unmask]] On Behalf Of <Peter George Duncan>
Sent:   Tuesday, January 22, 2002 20:51
To:     [log in to unmask]
Subject:        Re: [TN] VME stuff again...

Hi, Steve,

Sounds like you're having fun with this one, and I would be most interested
in being allowed to share your evolving experiences with trying to use
Stablcor. I flagged this material up to our designers when I first heard of
it (being simple souls, they'd designed our boards with good ol' FR4), but
we haven't had the excuse to look into using it yet.

The specs are now aging, and you're right about how densely packed the
boards have become, with folks trying to pack as much functionality into
each as humanly, or inhumanly, possible. I look at it as a cocoon within
which, and from which, any number of beautiful butterflies can grow and
emerge. (What DID that girl put in my coffee?) We have two boards on the go
that are a distillation of the functionality of five slots previously.
They've given me a folicular race between going grey or bald (it's neck and
neck at the moment).

The one thing we had to give serious priority to after the component
selection stage was layout to balance thermal mass around the board,
placing hotter components closest to the best thermal path through the
board, and particularly putting the hottest ones on the component side
where there was Max Headroom (remember him? I loved that guy). That way, if
the thermal path through the board is still not enough, you have some scope
for taking the heat out over the top with nice chunks of metal and thermal
pads. Pity there's no room for Pentium 4 style heatsinks here! There's no
room at all for overhead heat sinks on the solder side.

My sincerest sympathies!

Peter




                    Stephen
                    Gregory              To:     [log in to unmask]
                    <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst
Prin Engr/ST
                    L.COM>               Aero/ST Group)
                    Sent by:             Subject:     Re: [TN] VME stuff
again...
                    TechNet
                    <[log in to unmask]
                    ORG>


                    01/23/02
                    12:19 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hi Peter!

The spec that you quoted, is what is being followed. I'm going to purchase
the spec so that we have it here...since it appears that we're getting into
the business of "ruggedizing" commercial VME assemblies.

>From a personal view, I think that VITA established the standards
prematurely without considering how the the technology was going to
evolove. As you know, VME assemblies are extremely dense, basically single
board computers.

The assembly that I'm looking at is double-sided SMT, fine pitch on both
sides, 0402's, 18+ BGA's on the top side (313 balls, the max I've seen so
far from the BOM).

Not sure if establishing these restrictions are a good thing, so that
everything will fit as established, or if it's better to stay fluid so that
you can adjust to adapt to changes in the technology...I suppose there's
arguments on both sides...

Just know now that we have an assembly that can take advantage of some new
substrate technology, that sounds very promising as far as heat
dissipation, and CTE  issues, but can't use it because of the VME
spec...this is one of what came first, "The chicken or the egg?" huh?

-Steve Gregory-


 Hi, Steve,

 We ran into the same problem (more or less) - thermal management
 requirements and solutions conflicted with the VME spec (which spec did
 you
 go with, by the way?).

 One solution we considered, but didn't implement owing to expense, is to
 "step" the PCB so that it's the right thickness at the card guide edges
 and
 at the P1/P2 connector areas. Is that possible with Stablcor? - I don't
 know. Makes routing traces to the connectors a bit circuitous too (pun
 intended). The board thickness outwith these areas is not important, as
 long as it, plus the component height, doesn't exceed the envelope max.

 You'll need some pretty light-weight copper and very thin separation
 layers
 to fit 16 layers into the spec'd thickness. Good luck!

 Peter




                     Stephen
                     Gregory              To:     [log in to unmask]
                     <SteveZeva@AO        cc:     (bcc: DUNCAN Peter/Asst
 Prin Engr/ST
                     L.COM>               Aero/ST Group)
                     Sent by:             Subject:     [TN] VME stuff
 again...
                     TechNet
                     <[log in to unmask]
                     ORG>


                     01/23/02
                     10:41 AM
                     Please
                     respond to
                     "TechNet
                     E-Mail
                     Forum.";
                     Please
                     respond to
                     SteveZeva






 Hey all ya'll!

 VME stuff again. Pretty strict standard. Gotta new technology out there
 called Stablcor from Thermalworks, problem that we're seeing is that board
 thickness is going to increase, which violates the VME spec's. Not just
 from
 the card-guide aspects, but will change the dimension where the P1 and P2
 connectors interface with the backplane on a standard VME card cage.

 Just wondering if anybody has anything out there (connectors, etc.), that
 will allow you to "shoe-horn" ten-pounds, inna 1-pound bag, that will
 comply
 with VME  spec's.

 This board is 16-layers, within .063" without Stablecor, if we use
 2-layers
 Stablcor, it will increase .020-.025", with 3-layers Stablcor (the best,
 as
 far as thermal dissapation and CTE solutions), it will increase
 .030-.035".

 This Stablcor material sounds like a really good solution for thermal and
 CTE
 solutions, but has a hard time staying within the dimensional spec's that
 are
 called out in the VME spec's...trying to change these spec's I know is an
 act
 of God...it's there, and it's done.

 Just wondering if anybody else has explored this material, and have come
 to
 a
 dead-end like I have....because of the reasons like I have.

 -Steve Gregory-





[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]

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Date:         Wed, 23 Jan 2002 10:57:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Safavi-Bayat Shahed <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Safavi-Bayat Shahed <[log in to unmask]>
Subject:      Tarnished Surface
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi everyone,
We recently had a board fabricated with silver finish.
After it came back from assembly house the exposed silver finish is been
tarnish(color changed to brown)during assembly.
Does any one here has seen this before? The assembly done manually and the
tarnishing
happened after they washed the board.
I appreciate any comment on this.

Thank You

Shahed

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Date:         Wed, 23 Jan 2002 18:21:53 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Tarnished Surface
X-To:         Safavi-Bayat Shahed <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Shahed

Because your board is clean, the silver is exposed to the atmosphere.
There are trace amounts of sulfur dioxide and hydrogen sulfide in the
air, derived mostly from burning fossil fuels, but also from volcanic
activity. Silver has an affinity for sulfur and forms silver sulfide,
which is the brownish film you are seeing. Electrically, its presence
will be perfectly benign: it is only cosmetically that it is
disagreeable.

There is no way of preventing it, but its onset may be delayed but,
frankly, I don't recommend it because it means using products which may
degrade the electrical performance, just to gain a few month's
brilliance. If it is really a problem, a clear acrylic conformal coating
is about all you can do.

Brian

Safavi-Bayat Shahed wrote:
>
> Hi everyone,
> We recently had a board fabricated with silver finish.
> After it came back from assembly house the exposed silver finish is been
> tarnish(color changed to brown)during assembly.
> Does any one here has seen this before? The assembly done manually and the
> tarnishing
> happened after they washed the board.
> I appreciate any comment on this.
>
> Thank You
>
> Shahed
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------

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Date:         Wed, 23 Jan 2002 08:30:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Frank L Norman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Frank L Norman <[log in to unmask]>
Subject:      Re: Tarnished Surface
X-To:         Safavi-Bayat Shahed <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

It sounds like the damage was done during the washing process. If so you
may have an issue with your D.I. water quality, i.e. mix bed may be
exhausted...

Frank Norman

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Date:         Wed, 23 Jan 2002 13:59:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
Comments:     This message was delivered by an evaluation copy of LSMTP(TM)
Comments:     running on listserv.ipc.org. L-Soft did not author, review
Comments:     nor edit the present message and therefore assumes no
Comments:     responsibility for its content. LSMTP evaluation kits are made
Comments:     available for testing purposes, on the assumption that they will
Comments:     only be used to deliver information requested by its recipients.
From:         Phil Nutting <[log in to unmask]>
Subject:      Off Topic - Hershey's Kisses [Evaluation - see full header]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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A week or two ago the name for the Hershey's Kiss was explained in this =
forum as the appearance the machine was "kissing" the conveyor belt to =
generate each candy.  Well, times have changes.  I just finished the =
last two Kisses from my bag of "Christmas Kisses" and noticed that the =
candies no longer have that curved bottom edge of the past.  It looks =
like with the advent of the Hershey's "Hugs" that they went to a molding =
process rather than the "squirting" process.  Sigh!  Some things sadly =
change with time.

Phil Nutting

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Date:         Wed, 23 Jan 2002 08:51:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
Comments:     This message was delivered by an evaluation copy of LSMTP(TM)
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Comments:     available for testing purposes, on the assumption that they will
Comments:     only be used to deliver information requested by its recipients.
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: IPC-4101/23 vs /24 [Evaluation - see full header]
X-To:         Mark Hargreaves <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

I'm not an expert on this either but looking at the spec sheets for the two
different materials, I'd say you'd have to prove that the /24 will comply
with the requirements for /23. There are a number of differences between the
two.  Just looking at the descriptions:
(This is supposed to be a table with columns separated by "|")

/23                     |       /24
Epoxy                   |       Majority Epoxy
FR5                     |       FR4
Hot Strength Retention  |       N/A
Tg 135-175              |       Tg 150-200

You can find more comments about the difference between FR4 and FR5 in the
Technet Archives.  Fr-5 is typically used in applications with high
operating temperatures.

In addition to the different descriptions, the laminate requirements table
shows that /23 has higher requirements for peel strength, volume and surface
resistivity, dielectric breakdown and arc-resistance.

Perhaps with some of the improvements in FR4 materials, they now comply with
the higher standards for /23, but you or your material supplier would have
to prove that.

> ----------
> From:         Mark Hargreaves[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Mark Hargreaves
> Sent:         Friday, January 18, 2002 8:24 AM
> To:   [log in to unmask]
> Subject:      [TN] IPC-4101/23 vs /24
>
> Hi All,
> Does type GF/GFG material (IPC-4101 / 24) meet the requirements of type GH
> material (IPC-4101 / 23) ?
>
> Our customer is requesting type GH.  We stock type GF/GFG and would like
> to
> use it instead.
>
> (I hope I've phrased this properly.  4101 is a little over my head)
>
> Many Thanks,
> Mark Hargreaves
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
> -------
>

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Date:         Wed, 23 Jan 2002 15:47:17 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Blomberg, Rainer (FL51)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Blomberg, Rainer (FL51)" <[log in to unmask]>
Subject:      Re: Baking of Assemblies?
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We use a semi-aqueous process with final water rinse followed by IPA spray
and then bake 30 minutes at 150 deg. F.  Later, we dry out further with 6 hr
vac bake at 200 deg. F prior to conformal coating all our polyamide boards.

 Rainer G. Blomberg
 Honeywell -Space Systems Clearwater
 Staff Production Engineer
 13350 US Hwy 19 N MS 802-3
 Clearwater, FL 33764-7290
(727) 539-5534 Phone
(727) 790-8738 Pager
(727) 539-4469 Fax
e-mail: [log in to unmask]



-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, January 18, 2002 4:04 PM
To: [log in to unmask]
Subject: [TN] Baking of Assemblies?


This should be good fodder! We wash PWAs in a water hurricane type machine,
with
a hot air blower at the end of cycle. We noticed some components mainly
elect.
alum. capacitors have high capacitance. After research on cap. we were
instructed to bake assemblies 20 mins @ 100c to dry them. The long term
effect
of the moisture in the cap would cause electrical leakage then failure due
to
corrosion.
Well this idea expanded into a question should we bake all assemblies
because
many other items such as transformers, pots., coils are not hermetically
sealed.
And then there is the issue with pwb material its self.

My question to the forum is, Does anyone bake after wash as a standard? All
points of view are welcome.

Thanks!

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Date:         Wed, 23 Jan 2002 15:35:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Keach Sasamori <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Keach Sasamori <[log in to unmask]>
Subject:      OT-Test posting to Listserv
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This is a test to various lists on the new  Listserv.  We have moved the =
Listserv to a new blazing fast Windows 2000 system with lots of RAM.

You may want to clear your internet cache to clear any old setting =
pointing to the old server. The archives were not available earlier today =
but should be operational now.

Thank you

______________
Keach Sasamori
IS Administrator
IPC
2215 Sanders Rd.
Northbrook, IL 60062
Ph: (847) 790-5315=20
Fax: (847) 504-2315
e-mail: [log in to unmask]

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Date:         Wed, 23 Jan 2002 13:59:21 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Barmuta, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Barmuta, Mike" <[log in to unmask]>
Subject:      Re: Solder Analysis
X-To:         Mike Manwell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Mike:
 What is it that you are looking for? Are you looking for an independent lab
to cross check analysis? Is it that you don't care for Alpha for some
reason? Do you want someone locally, faster turn times, etc?
There are some good independent labs locally that can supply you with a full
analysis, Sn/Pb and trace metals. However, you are going to have to pay
whereas if you go with your solder supplier they normally offer this free,
typically once a month.
Let me know if you need the names of qualified labs in the Greater Seattle
area.


Regards

Michael Barmuta

Staff Engineer

Fluke Corp.

Everett WA

425-446-6076

-----Original Message-----
From: Mike Manwell [mailto:[log in to unmask]]
Sent: Tuesday, January 22, 2002 1:55 PM
To: [log in to unmask]
Subject: [TN] Solder Analysis


Hello folks,

Im looking for a facility that does solder sample analysis.
Im aware of Alpha Analytical Laboratories but before signing up, cant help
but wonder if there are others out there.
Any suggestions?

Thanks,
Mike Manwell
Integrex Inc.

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Date:         Wed, 23 Jan 2002 17:03:24 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: BGA/Vias
X-To:         Guy Ramsey <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

There could possibly be an interaction with the via pattern under the BGA.
The dense drilled hole grid perforates the glass reinforcement matrix and
reduces the mechanical integrity of that section of the board.  You can
actually see a localized increase in the CTE of the material because of the
loss of reinforcement.

> ----------
> From:         Guy Ramsey[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Guy Ramsey
> Sent:         Wednesday, January 16, 2002 1:42 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] BGA/Vias
>
> No, I understood you. Some boards will do this. Sometimes they crown
> instead
> of sag. I have not studied why. But increasing the size of the area
> subject
> to preheat may help. In a worst case scenario you may have to reflow the
> entire board in an oven.
>
> Sometimes, as the MoonMan mentions, the BGAs like to curl up on the
> corners
> or down on the corners as well. This is do to CTE mismatches in the
> package
> itself. Then you just have to slow the process down and use as low a
> topside
> heat as you can.
>
> An old axiom worth remembering, when in doubt go low and slow. I give
> credit
> to an old mentor, Ken Lindsey, for this rule. Hope he is doing well.
>
> Guy Ramsey
>
>
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
> > Sent: Wednesday, January 16, 2002 2:41 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] BGA/Vias
> >
> >
> > I probably didn't make myself clear. The problem is the board itself
> > collapses/sinks/"potato chips"...in the area being heated, i.e. BGA
> > location.
> > Rick
> >
> >
>
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>

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Date:         Wed, 23 Jan 2002 22:35:04 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         Earl Moon <[log in to unmask]>
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Earl,

It's worse than just using the test equipment guidelines.  Along with that,
you have to deal with each of the test fixture makers' preferences as well.
What this boils down to is a negotiation with each CM's test engineering
group as to what is testable.  They are not even slightly embarrassed asking
for 100% bottom side only coverage with 0.040" square test pads on 0.100"
centers (on a grid, of course) for a board with 6/6 mil line/space, 8/18 mil
via hole/pad and 0.8mm BGA's.  I guess it's a good bargaining tactic, but
I'd like to think we're at least on the same team.  Those are the same ICT
rules we were using fifteen years ago.  But typical PCB design rules have
shrunk considerably during that time.

Lately, I've had reasonable luck arguing for the first two of the three
following design rules (all test pads are round):

   nail size    test pad dia.    center-to-center
   ---------    -------------    ----------------
     0.100"         0.035"            0.085"
     0.075"         0.035"            0.057"
     0.050"         0.025"            0.044"

To get the third rule, which is the one you really need on a high-density
board, be prepared for battle.  From what I'm told, the problem is that the
50 mil test nails are fragile, and for the closer center-to-center spacings,
they can't be socketed.  So when they wear out or bend, the test engineer
has to carefully replace a press-fit test nail.  My basic response to this
serious problem is "So what", but NEVER SAY THIS or you will be testing the
boards yourself!

There is also the approximately 0.200" border required for the vacuum test
fixture seal.  One shop I work with has mostly changed from vacuum fixtures
to over-clamped fixtures.  It avoids the problems with leaky gaskets and
vias and gives the border space back to the PCB.  The fixture does cost a
bit more but it is a minimal one-time cost.  Most CM's I have worked with do
prefer the vacuum fixtures, so I assume there is a throughput difference,
but I don't know.

Are there any test engineers out there who can comment on whether the above
ICT design rules are typical for fixture fabricators today?  Are the smaller
test nails and pads really that much more expensive and troublesome?
Sometimes I can allocate more board area for testing.  However, in many
cases, increasing board area is not an option so we either give up test
coverage, rework the circuit to reduce components or use clamshell fixtures.
In these cases, I usually feel the trade off was not cost effective, but as
the circuit designer, I don't have all the information.

I didn't really mean to rant, but it's all over now.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966

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Date:         Wed, 23 Jan 2002 23:15:34 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: VME stuff again...
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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Hi Steve,

I don't have the VITA VME standard, but I have IEEE 1101.1-1998, "IEEE
Standard for Mechanical Core Specifications for Microcomputers Using IEC
60603-2 Connectors", upon which the VME standards are based.  There are a
couple of references to thicker boards in here.  The bottom line is pretty
much what Peter said:  you can have a thicker board, but you have to mill it
down for the card guides.  However, since everything is dimensioned from the
center of an 0.063" board, the board can get thicker in the direction of the
bottom side without disturbing the connector locations.  This is true as
long as you reduce the thickness from the bottom side back to the reference
0.063" at the card guides.  In this case, you can have the full thickness
board under the connectors.  This is explained in the notes to figure 15 of
this standard on page 26.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966

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Date:         Thu, 24 Jan 2002 00:53:01 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
MIME-Version: 1.0
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Hi MoonCaveMan,
Try IPC-9701published January 2002.

Werner

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Date:         Thu, 24 Jan 2002 06:05:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: BGA/Vias
X-To:         [log in to unmask]

Michael,

Can I "assume" delamination/blistering can be effected by this condition?
I'm seeing some in/under some .8 mm CSP'S.

Earl Moon

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Date:         Thu, 24 Jan 2002 06:11:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         [log in to unmask]

Seth,

Absolutely great stuff. I've been down this road too many times with
designers, and good ones at that, and share their frustration over what you
have said. I sure agree, we have to get on the same page at some point
though, as you say, the ICT folks have to start the discussion somewhere.

I hope Werner's suggestion about the new IPC 7091 provides some
standardization guidelines for all industry participants. I'm ordering it
today provided I can find it in the catalogue.

Earl

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Date:         Thu, 24 Jan 2002 06:26:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      VERY INTERESTING, TO ME, BGA/CSP STUFF

Folks,

First a finding of interest to be sharred (one or two r's, never get this
right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
clue how to spell that). Witnessed the strangest electronic packaging thing
ever in my young and tender life the other day.

A small, but very much on the rise non-manufacturing oriented telecom
company (how about that for irony in these times), with whom I'm currently
consulting, demonstrated a new way to assure circuit continuity. Boards are
suspect and assemblies don't seem much better (why I'm here). Finger
pressure on BGA device top and electrons flow and circuit "works." Finger
gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
work. Electrons flow. Just thought few of you could top this story.

I do love this work so.

This brings to mind another request. I have associations with several good
fab shops. Hope Glynn Shaw is looking in and would like to build some quick
turn 12 layer boards. Don't know a single good PCBA capability wanting to
do protos and medium volume production assemblies with .8 csp's and a
couple of FPGA's as one a perimeter and another a full array metal top
variety (you all know the ones. If anyone knows of this type assembler, in
the northern Ohio area, please let me know. I am a born again "HARD"
supplier qualifier, however.

Earl Moon ---- and don't leave home without your c clamps and a little wood
for top and bottom insulators. I think balsa is best. Maybe IPC has this
covered.

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Date:         Thu, 24 Jan 2002 06:35:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         [log in to unmask]

Thanks Werner,

I am having the folks here order 9791, or is it 9701 or 7091, just kidding,
this morning. From where do these numbers come and from who? You have
something to do with this pub, Werner?

MoonCaveMan on a warm spring day in Ohio? Ohio? Ohio? It's a job after all
and nice folks too.

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Date:         Thu, 24 Jan 2002 08:04:39 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      J-STD-001 AND IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Good day Technet.

Once again, we're considering changing from military workmanship
specifications (MIL-STD-2000) to industry standards (IPC).  The question:
Do both 001 and 610 need to be referenced in our quality manuals and on our
drawings?  Could either be stand-alone?  If acceptability requirements are
in 001, why have 610?

Thanks for your continued help,

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Thu, 24 Jan 2002 07:40:14 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McFaddin, Wade" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McFaddin, Wade" <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain

Hey Earl,

Loved your C-clamp story!   I knew there had to be a good reason to keep all
that hardware in the tool box.   As far as you looking for someone to build
your 12-layer boards with .8 CSPs in proto and medium volume, that sounds
like it's right up our alley.  Give me a call and I can put you in touch
with someone that can talk nuts and bolts (not c-clamps) it you want, or
check out our webpage at http://www.nextekinc.com/.

Thanks,
Wade McFaddin
Nextek Inc.
(256) 772-1995  ext. 1064

> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, January 24, 2002 6:26 AM
> To:   [log in to unmask]
> Subject:      [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Folks,
>
> First a finding of interest to be sharred (one or two r's, never get this
> right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
> clue how to spell that). Witnessed the strangest electronic packaging
> thing
> ever in my young and tender life the other day.
>
> A small, but very much on the rise non-manufacturing oriented telecom
> company (how about that for irony in these times), with whom I'm currently
> consulting, demonstrated a new way to assure circuit continuity. Boards
> are
> suspect and assemblies don't seem much better (why I'm here). Finger
> pressure on BGA device top and electrons flow and circuit "works." Finger
> gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
> work. Electrons flow. Just thought few of you could top this story.
>
> I do love this work so.
>
> This brings to mind another request. I have associations with several good
> fab shops. Hope Glynn Shaw is looking in and would like to build some
> quick
> turn 12 layer boards. Don't know a single good PCBA capability wanting to
> do protos and medium volume production assemblies with .8 csp's and a
> couple of FPGA's as one a perimeter and another a full array metal top
> variety (you all know the ones. If anyone knows of this type assembler, in
> the northern Ohio area, please let me know. I am a born again "HARD"
> supplier qualifier, however.
>
> Earl Moon ---- and don't leave home without your c clamps and a little
> wood
> for top and bottom insulators. I think balsa is best. Maybe IPC has this
> covered.
>
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Date:         Thu, 24 Jan 2002 14:31:15 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rajkumar <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rajkumar <[log in to unmask]>
Subject:      Electronic Manufacturing Conference in New Zealand
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_007A_01C1A4E3.C776AEE0"

This is a multi-part message in MIME format.

------=_NextPart_000_007A_01C1A4E3.C776AEE0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hello

As anyone has any information (e.g. website) about electronic =
manufacturing conference in New Zealand?

THanx

Rajkumar Durairaj
Electronics Manufacturing Engineering Research Group
School of Aeronautical, Civil and Mechanical Engineering
University of Salford
http://www.acme.salford.ac.uk/emerg
Salford, UK, M5 4WT
Tel: +44-161-2954696
Fax: +44-161-2955575/5060



------=_NextPart_000_007A_01C1A4E3.C776AEE0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hello</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>As anyone has any information (e.g.=20
website)&nbsp;about electronic manufacturing conference in New=20
Zealand?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>THanx</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Rajkumar Durairaj<BR>Electronics =
Manufacturing=20
Engineering Research Group<BR>School of Aeronautical, Civil and =
Mechanical=20
Engineering<BR>University of Salford<BR><A=20
href=3D"http://www.acme.salford.ac.uk/emerg">http://www.acme.salford.ac.u=
k/emerg</A><BR>Salford,=20
UK, M5 4WT<BR>Tel: +44-161-2954696<BR>Fax: =
+44-161-2955575/5060</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV></BODY></HTML>

------=_NextPart_000_007A_01C1A4E3.C776AEE0--

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Date:         Thu, 24 Jan 2002 10:29:45 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Matt Eubank <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Matt Eubank <[log in to unmask]>
Subject:      center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.

Thanks
Matt

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Date:         Thu, 24 Jan 2002 11:23:51 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Masking for Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello again...

Looking for suggestions for removing masking material (tape or liquid) which
is applied to mask areas from conformal coating.  The way we do it now, the
operator masks off the area (usually tape), sprays the board, cures the
coating, scores the coating around the tape, then removes the tape.  We're
trying to eliminate the scoring of the coating since this has potential of
cutting through traces.  Removal of the coating prior to curing doesn't work
because the coating runs during the heat cure process.  I'm trying to avoid
room temperature cure since this is very time consuming.  Ant suggestions?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Thu, 24 Jan 2002 16:37:44 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Braime, Justin" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Braime, Justin" <[log in to unmask]>
Subject:      Re: Electronic Manufacturing Conference in New Zealand
X-To:         Rajkumar <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Hi Rajkumar,
Electronics manufacturing conferences in New Zealand are sometimes organised
by the SMCBA (Surface Mount & Circuit Board Association), which is the
Australasian equivalent of IPC / SMART Group / etc. The SMCBA office is
based in the state of Victoria, Australia. Website is at:
http://www.smcba.asn.au/

J.

> -----Original Message-----
> From: Rajkumar [SMTP:[log in to unmask]]
> Sent: 24 January 2002 14:31
> To:   [log in to unmask]
> Subject:      [TN] Electronic Manufacturing Conference in New Zealand
>
> Hello
>
> As anyone has any information (e.g. website) about electronic
> manufacturing conference in New Zealand?
>
> THanx
>
> Rajkumar Durairaj
> Electronics Manufacturing Engineering Research Group
> School of Aeronautical, Civil and Mechanical Engineering
> University of Salford
> <http://www.acme.salford.ac.uk/emerg>
> Salford, UK, M5 4WT
> Tel: +44-161-2954696
> Fax: +44-161-2955575/5060
>
>


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Date:         Thu, 24 Jan 2002 11:09:51 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Genny Gibbard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Re: center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Can't find any neat and tidy formula off the top of my head, but some basic
geometry and trig should handle it.  A right triangle always fits in a
semi-circle.  You know the diameter (this is your hypotenuse), you can find
the distance between the two arc points in a straight line.  This gives you
two sides of the triangle, and one angle (right angle).  You can find every
other piece of information about the triangle with this knowledge.  Then you
just have to find the coordinates of the midpoint of your hypotenuse to know
the center of your circle.
You might find some helpful info here if you've forgotten you're trig
definitions.
http://www.math2.org/index.xml

-----Original Message-----
From: Matt Eubank [mailto:[log in to unmask]]
Sent: January 24, 2002 9:30 AM
To: [log in to unmask]
Subject: [TN] center of a arc


Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.

Thanks
Matt

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Date:         Thu, 24 Jan 2002 09:11:18 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              peter lee <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         peter lee <[log in to unmask]>
Subject:      Noclean process chemistry loss
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello,

We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.

So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.

My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.

Rgds,
Peter

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Thu, 24 Jan 2002 11:25:57 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      OK Industries BGA-3000 Rework Unit

Folks,

Anyone have experience or anything to say, one way or another, about OK
Industries BGA-3000 Rework Unit. I have experience on SRT, AirVac, and
Conceptronic equiptment only.

Thanks,

MoonMan

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Date:         Thu, 24 Jan 2002 11:37:22 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]

Wade, and all off-line repliers, thanks for the input. Before I go outside
driving distance from the Akron/Cleveland area, I will continue searching
there. Alabama is nice this time of year though what with all the balmy
weather. Not too far either.

Earl

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Date:         Thu, 24 Jan 2002 10:44:52 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]
MIME-version: 1.0
Content-type: text/plain; charset=Windows-1252
Content-transfer-encoding: 7BIT

I saw something similar early in my career, the design engineer was showing
the boss how a circuit worked when he put his finger "just here". Boss said
that was great we could ship at least 10 units.          I don't think he
was called back on the floor til there was a solution.
Dan

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Date:         Thu, 24 Jan 2002 13:58:43 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Julien Bouchard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Julien Bouchard <[log in to unmask]>
Subject:      Re: BGA rework
X-To:         Don Anderson <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hi,
        Here we allow to change a BGA to a maximum of three times. But I don't
think it's based on any standards or spec. It's just a number time that give
us good balance between the board integrity and the cost of rework.

Julien Bouchard
Matrox Electronis Systems

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Don Anderson
Sent: 16-Jan-02 13:51
To: [log in to unmask]
Subject: [TN] BGA rework


TechNetters,

I am sure there has been some discussion on this subject in the past, but I
need to ask a fairly simple question (I hope).  Is there a limit to the
number of times BGA packages can be attached to and removed from a BGA
before the integrity of the board is compromised?  Is it in a spec
someplace?
Thanks in advance

Don Anderson
Compunetics, Inc.

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Date:         Fri, 25 Jan 2002 08:02:19 +1300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Michael Bell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Bell <[log in to unmask]>
Subject:      Re: center of a arc
X-To:         Matt Eubank <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

To find the centre all you have to do is draw two lines crossing two sides
of the circle, not to close to the centre (the closer to the edge of the
circle is best), and then bisect them with a protractor.  The two bisecting
lines will then cross each other at the centre.

Cheers

-----Original Message-----
From: Matt Eubank [mailto:[log in to unmask]]
Sent: Friday, 25 January 2002 04:30
To: [log in to unmask]
Subject: [TN] center of a arc


Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.

Thanks
Matt

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Date:         Fri, 25 Jan 2002 08:05:13 +1300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Michael Bell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Bell <[log in to unmask]>
Subject:      Re: Masking for Conformal Coating
X-To:         "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

James,

Have you considered using a laser cut or milled steel/aluminium hat that
sits ontop of the PCB.  Any clearance for components can be milled out from
the underside, and the weight of it forms a good enough seal around the
bottom.  We used this idea ffor a long time for PCB's that were panelized.
The hats were made into a large spider web style with hats adjointing to it.
You simply dropped it over the respective components and in one go, we
masked about 30 components/connectors etc.

Cheers

Mike

-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, 25 January 2002 05:24
To: [log in to unmask]
Subject: [TN] Masking for Conformal Coating


Hello again...

Looking for suggestions for removing masking material (tape or liquid) which
is applied to mask areas from conformal coating.  The way we do it now, the
operator masks off the area (usually tape), sprays the board, cures the
coating, scores the coating around the tape, then removes the tape.  We're
trying to eliminate the scoring of the coating since this has potential of
cutting through traces.  Removal of the coating prior to curing doesn't work
because the coating runs during the heat cure process.  I'm trying to avoid
room temperature cure since this is very time consuming.  Ant suggestions?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Thu, 24 Jan 2002 19:21:52 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Noclean process chemistry loss
X-To:         peter lee <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Peter,

Kyzen and I have fought that battle in the past on an old Tooltronics
UltraClean II and a Triton with Aquanox XJN.  We went from making a gallon
add daily to four gallons/day before we solved it.  (20 gallons was a
complete charge of the system.)  Kyzen was very responsive and their
regional tech rep. showed up to help within days.

We did the same stuff you've done in your trouble shooting - blocked the
overflow drain & killed the auto refill (that was murder in the beginning).
We also checked for any solution overflow into down stream chambers - look
for scum rings on the tank walls.  We also checked for evaporation and
considered buying a vapor recovery system but it turns out we didn't need
it.  When the wash sump is idle the chemistry losses due to evaporation are
very low - the stuff's heavier than water and sinks to the sump's bottom.
You do lose water though.  We were running at 130 F and 30 psi.

In the UltraClean II case, the operators were manually overfilling the wash
sump with water and then making the chemistry add.  Pure Chemistry was
overflowing into the isolation chamber and going straight to Drain.  They
were also placing product on the conveyor very close together that
drastically increase solution dragout.  We had to retrain everybody to
follow the procedures and show them what was happening to make it stick.

In the Triton case, the rinse drain & overfill were scaled shut (from the
previous chemistry) and the rinse water cascaded back into the wash sump,
overfilling and draining.  We had to replace the drain & overflow piping in
the Rinse Sections - way too much buildup to descale.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: peter lee [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 12:11 PM
To: [log in to unmask]
Subject: [TN] Noclean process chemistry loss


Hello,

We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.

So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.

My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.

Rgds,
Peter

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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=========================================================================
Date:         Thu, 24 Jan 2002 11:30:34 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: center of a arc
X-To:         Matt Eubank <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Assuming the two points on the arc are the endpoints, construct a line
between the two points.  Find the midpoint of that line.  A line drawn
through the midpoint and the center of the circle will pass through the
center of the arc at the radius of the circle.

> ----------
> From:         Matt Eubank[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Matt Eubank
> Sent:         Thursday, January 24, 2002 7:29 AM
> To:   [log in to unmask]
> Subject:      [TN] center of a arc
>
> Need some help.
> What is the equation for finding the center of a arc given the radius and
> 2
> points on the arc.
>
> Thanks
> Matt
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>

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=========================================================================
Date:         Thu, 24 Jan 2002 13:23:02 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Barry Gallegos <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Re: OK Industries BGA-3000 Rework Unit
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

MoonMan,
We are using a Ok-3500 and are pretty well pleased with it. How ever you
would best be able to make a decision by having the rep. bring one in and
demonstrating the machine. Look at things like your board size coupled with
edge connectors and the like.

Barry.

-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 10:26 AM
To: [log in to unmask]
Subject: [TN] OK Industries BGA-3000 Rework Unit


Folks,

Anyone have experience or anything to say, one way or another, about OK
Industries BGA-3000 Rework Unit. I have experience on SRT, AirVac, and
Conceptronic equiptment only.

Thanks,

MoonMan

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=========================================================================
Date:         Thu, 24 Jan 2002 14:45:05 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: ASSEMBLED BOARD IPC TEST REQUIREMENTS
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Earl,

Thanks for the encouragement.  I received one off-line note from someone who
uses the same design rules I gave.  However a sample of two is pretty sparse
data.  Would other folks be willing to share the design rules they use for
ICT?  If you're not comfortable replying on-line due to company
confidentiality or any other reason, I will keep off-line responses
confidential and just summarize the design rules that people used.  I'd
really like to hear from some test engineers to learn why things are the way
they are and figure out how to better dovetail your requirements and
restrictions with those of designers.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
> Sent: Thursday, January 24, 2002 6:11 AM
> To: [log in to unmask]
> Subject: Re: [TN] ASSEMBLED BOARD IPC TEST REQUIREMENTS
>
>
> Seth,
>
> Absolutely great stuff. I've been down this road too many times with
> designers, and good ones at that, and share their frustration
> over what you
> have said. I sure agree, we have to get on the same page at some point
> though, as you say, the ICT folks have to start the discussion somewhere.
>
> I hope Werner's suggestion about the new IPC 7091 provides some
> standardization guidelines for all industry participants. I'm ordering it
> today provided I can find it in the catalogue.
>
> Earl
>
> ------------------------------------------------------------------
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Thu, 24 Jan 2002 16:00:21 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Lead replacement solder alloys
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_17.221b13aa.2981cfe5_boundary"

--part1_17.221b13aa.2981cfe5_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Who is the procurement source for a couple of the newer Sn 63 like solders
that have somewhat better properties than Sn63.  Specifically they are the
SnAgCuSb and SnAgCuZn alloys.

Thanks
Phil Hinton

--part1_17.221b13aa.2981cfe5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Who is the procurement source for a couple of the newer Sn 63 like solders that have somewhat better properties than Sn63. &nbsp;Specifically they are the SnAgCuSb and SnAgCuZn alloys.
<BR>
<BR>Thanks
<BR>Phil Hinton </FONT></HTML>

--part1_17.221b13aa.2981cfe5_boundary--

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Date:         Thu, 24 Jan 2002 16:16:46 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi MoonCaveMan,
Missed you at APEX, together with alot of other folks. "9/11&economy" have a
gruesome impact.
The IPC document numbers came from Dieter--I think; I, among others in the
TAEC protested the change from numbers like IPC-SM-785 [Surface Mount],
IPC-MF-150 [Metal Foil], IPC-D-279 [Design] to such non-descript entiies as
IPC-7901, IPC-2222, etc., but as you can see to no avail.
Among all of the IPC documents, my exhaustive search found no standards on
either balsa wood orC-clamps. Now, if you would make the C-clamps out of
copper, you would have a nice heat sink. Would you want to chair a committee
on this subject?
Seriously, though, your "small, but very much on the rise non-manufacturing
oriented telecom
company" will not be rising much farther, if they assemble BGAs/PWAs this
way. I do not think you reallllly need any help with this.
Can I top this story? Would this qualify? At Bell Labs--the former vibrant
Bell Labs, not the current empty shell--one guy tried to pattent the idea of
putting a screw in the center of the package and fasteninng it to the PCB
through a hole with a nut.

Werner

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Date:         Thu, 24 Jan 2002 16:20:16 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: Masking for Conformal Coating
X-To:         Michael Bell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Thanks Mike, this sounds like a good idea.  One question though, when do you
remove the mask, before or after cure?  If before, doesn't the coating run
when heated?  If after, how do you separate the tool from the coating?  (OK,
three questions)

Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879


        -----Original Message-----
        From:   Michael Bell [SMTP:[log in to unmask]]
        Sent:   Thursday, January 24, 2002 2:05 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Masking for Conformal Coating

        James,

        Have you considered using a laser cut or milled steel/aluminium hat
that
        sits ontop of the PCB.  Any clearance for components can be milled
out from
        the underside, and the weight of it forms a good enough seal around
the
        bottom.  We used this idea ffor a long time for PCB's that were
panelized.
        The hats were made into a large spider web style with hats
adjointing to it.
        You simply dropped it over the respective components and in one go,
we
        masked about 30 components/connectors etc.

        Cheers

        Mike

        -----Original Message-----
        From: Marsico, James [mailto:[log in to unmask]]
        Sent: Friday, 25 January 2002 05:24
        To: [log in to unmask]
        Subject: [TN] Masking for Conformal Coating


        Hello again...

        Looking for suggestions for removing masking material (tape or
liquid) which
        is applied to mask areas from conformal coating.  The way we do it
now, the
        operator masks off the area (usually tape), sprays the board, cures
the
        coating, scores the coating around the tape, then removes the tape.
We're
        trying to eliminate the scoring of the coating since this has
potential of
        cutting through traces.  Removal of the coating prior to curing
doesn't work
        because the coating runs during the heat cure process.  I'm trying
to avoid
        room temperature cure since this is very time consuming.  Ant
suggestions?

        Jim Marsico
        Senior Engineer
        Production Engineering
        EDO Electronics Systems Group
        [log in to unmask] <mailto:[log in to unmask]>
        631-595-5879


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Date:         Thu, 24 Jan 2002 16:35:21 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Leo Lambert <[log in to unmask]>
Subject:      Re: Noclean process chemistry loss
X-To:         peter lee <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hi Peter, I would check the venting system and how much draw you are getting
to pull off the fumes. With the wash tank at 135F and with a good venting
system it's not improbable to draw the material out of the wash tank. The
other item I would look at would be the drag out by the product as it is
going through the system.

Not knowing the product configuration, lots of connectors could be a cause
of this lost.

Good Luck

Leo Lambert
EPTAC Corp.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of peter lee
Sent: Thursday, January 24, 2002 12:11 PM
To: [log in to unmask]
Subject: [TN] Noclean process chemistry loss


Hello,

We are trouble shooting our Stolting in-line cleaning
machine and no-clean washing process. We have been
seeing significant solvent (Kyzen) and water loss
(~3.5 gallon per hr) in the wash tank. The wash tank
was running @135F/75 psi. Chemistry concentration
remains relatively constant after wash.

So far we have tried the following to eliminate
possibilities of leakage and drainage: shutting off
all overflow drain valves/ Air knifes were installed
to isolate the wash tank from both sides. Auto
refilling was cutoff during measurement run.

My question: Has anyone experienced and trouble shot
this problem before? How significant is the loss due
to evaporation? Any suggestion would be appreciated.

Rgds,
Peter

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Thu, 24 Jan 2002 16:44:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      solder waste from hand solder/de-solder
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi all,

With the TRI program from the EPA and other factors it comes to mind =
that we have more than dross from the wave solder system or solder pot.  =
We have solder from solder suckers and de-soldering systems, soiled =
solder sponges and (should I add) component lead trimmings that =
presently don't make it into a dross bucket.  What are you folks using =
for a system (procedure, policy) regarding these wastes containing lead?

Thanks in advance,

Phil Nutting

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Date:         Thu, 24 Jan 2002 20:20:48 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: solder waste from hand solder/de-solder
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_ce.207540dd.29820cf0_boundary"

--part1_ce.207540dd.29820cf0_boundary
Content-Type: text/plain; charset="US-ASCII"
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Hi Phil!

You bring up some very good points that show what a nightmare this is going
to be!!

We recycle all our dross, but along with the items that you mention, what
about almost empty solder paste jars and tubes, used stencil cleaning rolls
from the screen cleaning systems in the printers nowdays, the wipes that are
used to clean spatulas after depositing paste onto the stencils?

We put these items into a special container for hazardous waste and dispose
of that properly. But we really don't have any real idea of how much lead is
contained within that waste...

I suppose one could do some math caculations that would yield some sort of
figure, but is that real?

Just shows how full of holes this legislation is....and as somebody
brought-up in the past, are the hunting enthusiasts that do their own
reloading going to have to report? How about the fishing nut that make his
own sinkers? It would be easy for anyone of these guys to go through 100-lbs.
of lead in a year...

-Steve Gregory-


> Hi all,
>
> With the TRI program from the EPA and other factors it comes to mind that
> we have more than dross from the wave solder system or solder pot.  We have
> solder from solder suckers and de-soldering systems, soiled solder sponges
> and (should I add) component lead trimmings that presently don't make it
> into a dross bucket.  What are you folks using for a system (procedure,
> policy) regarding these wastes containing lead?
>
> Thanks in advance,
>
> Phil Nutting
>


--part1_ce.207540dd.29820cf0_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Phil!<BR>
<BR>
You bring up some very good points that show what a nightmare this is going to be!!<BR>
<BR>
We recycle all our dross, but along with the items that you mention, what about almost empty solder paste jars and tubes, used stencil cleaning rolls from the screen cleaning systems in the printers nowdays, the wipes that are used to clean spatulas after depositing paste onto the stencils?<BR>
<BR>
We put these items into a special container for hazardous waste and dispose of that properly. But we really don't have any real idea of how much lead is contained within that waste...<BR>
<BR>
I suppose one could do some math caculations that would yield some sort of figure, but is that real?<BR>
<BR>
Just shows how full of holes this legislation is....and as somebody brought-up in the past, are the hunting enthusiasts that do their own reloading going to have to report? How about the fishing nut that make his own sinkers? It would be easy for anyone of these guys to go through 100-lbs. of lead in a year...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,<BR>
<BR>
With the TRI program from the EPA and other factors it comes to mind that we have more than dross from the wave solder system or solder pot.&nbsp; We have solder from solder suckers and de-soldering systems, soiled solder sponges and (should I add) component lead trimmings that presently don't make it into a dross bucket.&nbsp; What are you folks using for a system (procedure, policy) regarding these wastes containing lead?<BR>
<BR>
Thanks in advance,<BR>
<BR>
Phil Nutting<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_ce.207540dd.29820cf0_boundary--

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Date:         Thu, 24 Jan 2002 19:41:09 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Lefebvre, Scott" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Lefebvre, Scott" <[log in to unmask]>
Subject:      Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

I recently read an article concerning board finishes. One of the finishes specified was Electroplated Tin/Lead.  I have not heard of this process before, I'm only familiar with Electroplated Tin.  What I read is that it is vary flat and works well with Fine Pitch and BGA components.

Does any one out their have any information they could share concerning this issue.  What are the pros and cons of this board finish.


Scott Lefebvre
Mfg. Engineer
ADC
530-265-1041
[log in to unmask] <[log in to unmask]>

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Date:         Thu, 24 Jan 2002 18:22:03 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Frank L Norman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Frank L Norman <[log in to unmask]>
Subject:      Water soluble solder mask
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi all,

Looking for insight about using water soluble solder mask.

We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.

Frank Norman
Raytheon

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Date:         Thu, 24 Jan 2002 21:44:44 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Water soluble solder mask
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_162.7aa806a.2982209c_boundary"

--part1_162.7aa806a.2982209c_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Frank!

Question: Are you closed-loop with your water?

-Steve Gregory-


> Hi all,
>
> Looking for insight about using water soluble solder mask.
>
> We are currently using a latex solder mask made by Litton. But now the
> question as been asked if water soluble mask could be used instead. Note,
> batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
> Frank Norman
> Raytheon
>


--part1_162.7aa806a.2982209c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Frank!<BR>
<BR>
Question: Are you closed-loop with your water?<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,<BR>
<BR>
Looking for insight about using water soluble solder mask.<BR>
<BR>
We are currently using a latex solder mask made by Litton. But now the<BR>
question as been asked if water soluble mask could be used instead. Note,<BR>
batch washer(Aqueous Tech. Washer) is used to clean PWAs.<BR>
<BR>
Frank Norman<BR>
Raytheon<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_162.7aa806a.2982209c_boundary--

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Date:         Thu, 24 Jan 2002 22:38:04 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Lemme butt in with some theoretical stuff, that I have seen evidence of.

The subject is galvanic corrosion, or what happens when you have two metals
(like Tin and Lead) electrically in contact with each other, and with the
corrosive material.

When this is the case, the more readily attacked of the two metals (in this
case Tin) is MUCH more readily attacked, while the less readily attacked
metal is protected.  This is why galvanized pails do not rust as easily as a
bare steel pail would, that is why you "galvanize."

However, in this case, you are trying to protect the entire exposed surface,
both Tin and Lead, and keep the surface solderable.  So, this is not such a
good idea, as the presence of the Lead should/would accelerate attack on the
Tin.  Or, what I am suggesting is that by this theory, Tin/Lead should be
LESS protective than pure Tin.

(All of the above advice goes out the window if you fuse or "reflow" the
Tin/Lead deposit, in which case the plated metals form a true alloy, instead
of discrete crystals of Tin and crystals of Lead, and thus act like a single
metal.)

Remember, free advice is often not worth what you paid for it....:-)

Rudy Sedlak
RD Chemical Company

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Date:         Fri, 25 Jan 2002 08:40:44 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Dawson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Dawson <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
MIME-Version: 1.0
Content-Type: text/plain

Hi,
Sounds like you have cracked joints on your bga.s.
This can happen if you reflow the bga side then wave solder the bottom side.
Try a board with thermocouples under the bga when it goes over the wave, you
will probably frighten yourself. The formally good bga joints can reach 180
to 200 Celsius which is enough to disturb the joints as the board flexes
with heat, but not enough to reflow them back into a consolidated joint.
If this is the case, go double sided reflow.
If it isn't, check your reflow conditions.
You cannot see these cracks with a standard transmission X ray equipment
because they are very narrow, which is why slight finger pressure will cause
the component to start working again.
It had me going when I first saw it, I thought it was an aerial effect.
Hope this helps
Regards
Eric Dawson

> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Thursday, January 24, 2002 12:26 PM
> To:   [log in to unmask]
> Subject:      [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Folks,
>
> First a finding of interest to be sharred (one or two r's, never get this
> right - and I'm writing a book!) with all BGA/CSP officianados (haven't a
> clue how to spell that). Witnessed the strangest electronic packaging
> thing
> ever in my young and tender life the other day.
>
> A small, but very much on the rise non-manufacturing oriented telecom
> company (how about that for irony in these times), with whom I'm currently
> consulting, demonstrated a new way to assure circuit continuity. Boards
> are
> suspect and assemblies don't seem much better (why I'm here). Finger
> pressure on BGA device top and electrons flow and circuit "works." Finger
> gets hot and tired. Engineer uses woodworking "C" clamp to do the finger's
> work. Electrons flow. Just thought few of you could top this story.
>
> I do love this work so.
>
> This brings to mind another request. I have associations with several good
> fab shops. Hope Glynn Shaw is looking in and would like to build some
> quick
> turn 12 layer boards. Don't know a single good PCBA capability wanting to
> do protos and medium volume production assemblies with .8 csp's and a
> couple of FPGA's as one a perimeter and another a full array metal top
> variety (you all know the ones. If anyone knows of this type assembler, in
> the northern Ohio area, please let me know. I am a born again "HARD"
> supplier qualifier, however.
>
> Earl Moon ---- and don't leave home without your c clamps and a little
> wood
> for top and bottom insulators. I think balsa is best. Maybe IPC has this
> covered.
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
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Date:         Fri, 25 Jan 2002 09:19:51 -0000
Reply-To:     Dougal Stewart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dougal Stewart <[log in to unmask]>
Subject:      Re: Electroplated Tin/Lead
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Well it's a strange thing how what goes around, comes around. Electroplated
tin lead was (and still is in some companies) the subsequent process step to
electroplate copper, and acts as the etch resist through ammoniacal etchant.
Before the days of HASL, this was then reflowed, and the surface finish of
fused tin lead was commonplace, so much so that all the accelerated ageing
tests were based on fused tin lead finish. With HASL, OSP, ENIG, Immersion
Tin, Immersion Silver finishes, the electroplated tin lead is stripped after
etch, hence the term soldermask over bare copper, and then the final finish
applied.
In my past, we converted a board finish from HASL to reflowed tin lead (but
3-5um, not 8-12um), so that the customer had a perfectly flat finish for
assembling RF cans, and it improved their first pass yield from 86% to 98%.
Unfortunately for the competition, they had thrown out their IR reflow, and
converted the tin lead baths to tin, so couldn't offer the finish !
Concerns over intermetallic growth prior to assembly were proven to be
unjustified, probably due to the short time between manufacture and
assembly - JIT works in some companies - and the commercial advantage was
significant as it reduced process steps, and increased assembly yield.
Dougal Stewart

email:  [log in to unmask]
phone: +44 1896 822204
mob:    +44 7984 629667


----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 3:38 AM
Subject: Re: [TN] Electroplated Tin/Lead


> Lemme butt in with some theoretical stuff, that I have seen evidence of.
>
> The subject is galvanic corrosion, or what happens when you have two
metals
> (like Tin and Lead) electrically in contact with each other, and with the
> corrosive material.
>
> When this is the case, the more readily attacked of the two metals (in
this
> case Tin) is MUCH more readily attacked, while the less readily attacked
> metal is protected.  This is why galvanized pails do not rust as easily as
a
> bare steel pail would, that is why you "galvanize."
>
> However, in this case, you are trying to protect the entire exposed
surface,
> both Tin and Lead, and keep the surface solderable.  So, this is not such
a
> good idea, as the presence of the Lead should/would accelerate attack on
the
> Tin.  Or, what I am suggesting is that by this theory, Tin/Lead should be
> LESS protective than pure Tin.
>
> (All of the above advice goes out the window if you fuse or "reflow" the
> Tin/Lead deposit, in which case the plated metals form a true alloy,
instead
> of discrete crystals of Tin and crystals of Lead, and thus act like a
single
> metal.)
>
> Remember, free advice is often not worth what you paid for it....:-)
>
> Rudy Sedlak
> RD Chemical Company
>
> --------------------------------------------------------------------------
-------
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> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------

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Date:         Fri, 25 Jan 2002 09:56:21 -0000
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Fenner <[log in to unmask]>
Subject:      Re: Lead replacement solder alloys
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Lead free alloys come in 2 types: generic and proprietary/patented.  The
more alloying additions the more likely the alloy is to fall into the second
category.
Generic alloys are available from just about any recognised solder
manufacturer, proprietary alloys are available from the patent holder and
any licensees.
If the alloy has actual or perceived merit for general industry use then it
is likely you will find that other manufacturers have licensed it and you
can again obtain it from just about any recognised manufacturer

Kind Regards

Mike Fenner

Applications Engineer, European Operations
Indium Corporation
 T: + 44 1908 580 400
M: + 44 7810 526 317
 F: + 44 1908 580 411
 E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com

  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
  Sent: Thursday, January 24, 2002 9:00 PM
  To: [log in to unmask]
  Subject: [TN] Lead replacement solder alloys


  Who is the procurement source for a couple of the newer Sn 63 like solders
that have somewhat better properties than Sn63.  Specifically they are the
SnAgCuSb and SnAgCuZn alloys.

  Thanks
  Phil Hinton

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">


<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>Lead free=20
alloys come in&nbsp;2 types: generic and =
proprietary/patented.&nbsp;&nbsp;The=20
more alloying additions the more likely the alloy is to fall into the =
second=20
category. </FONT></SPAN></DIV>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>Generic=20
alloys are available from&nbsp;just about any recognised solder =
manufacturer,=20
proprietary alloys are available from the patent holder and any=20
licensees.</FONT></SPAN></DIV>
<DIV><SPAN class=3D919224509-25012002><FONT face=3DArial =
color=3D#0000ff>If the alloy=20
has actual or perceived merit for general industry&nbsp;use&nbsp;then it =
is=20
likely you will find that other manufacturers have licensed it and you =
can again=20
obtain it from just about any recognised =
manufacturer</FONT></SPAN></DIV>
<DIV>&nbsp;</DIV>
<P><FONT face=3DArial color=3D#0000ff>Kind Regards</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Mike Fenner</FONT> </P>
<P><FONT face=3DArial color=3D#0000ff>Applications Engineer, European=20
Operations</FONT> <BR><B><FONT face=3DArial color=3D#0000ff>Indium=20
Corporation</FONT></B> <BR><FONT face=3DArial color=3D#0000ff>&nbsp;T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial color=3D#0000ff>M: + 44 7810 526 =
317</FONT>=20
<BR><FONT face=3DArial color=3D#0000ff>&nbsp;F: + 44 1908 580 411</FONT> =
<BR><FONT=20
face=3DArial color=3D#0000ff>&nbsp;E: [log in to unmask]</FONT> =
<BR><FONT face=3DArial=20
color=3D#0000ff>W:<U> www.indium.com</U>&nbsp; </FONT><BR><FONT =
face=3DArial=20
color=3D#0000ff>Leadfree:</FONT><U> <FONT face=3DArial=20
color=3D#0000ff>www.Pb-Free.com</FONT></U> </P>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
  Thursday, January 24, 2002 9:00 PM<BR><B>To:</B>=20
  [log in to unmask]<BR><B>Subject:</B> [TN] Lead replacement solder=20
  alloys<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Who is the=20
  procurement source for a couple of the newer Sn 63 like solders that =
have=20
  somewhat better properties than Sn63. &nbsp;Specifically they are the =
SnAgCuSb=20
  and SnAgCuZn alloys. <BR><BR>Thanks <BR>Phil Hinton=20
</FONT></FONT></BLOCKQUOTE></BODY></HTML>

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Date:         Fri, 25 Jan 2002 07:13:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]

Eric,

I agree with you. Seen it a few times but only from non-qualified/capable
assembly houses. Another thing I've seen are hole wall opens, as cracks and
delam in boards from the same type fab shops.

Earl

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Date:         Fri, 25 Jan 2002 07:21:49 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      NEED "GOOD" ASSEMBLY HOUSE

Folks,

I am much in need of a "GOOD" assembly house to do some assemblies. How
about that for irony?

The board is about 10" square, 12 layers, 7 CSP's on .8 mm centers, one
full array ceramic BGA on 1mm centers, 1 perimeter BGA on 1 mm, couple of
20 mil pitch QFP's, and some other "normal" stuff as well as just a few
through hole things and a few passives on the bottom side.

Again, I'd like to have a house in or near northern Ohio but I'll consider
others as needed. How about Steve's house or Dave Fish's fine eatery?

Please get back to me soon concerning this wonderful opportunity.

Earl Moon

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Date:         Fri, 25 Jan 2002 07:23:45 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]

Amazing how that works Dan. Really builds confidence as well.

MoonMan

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Date:         Fri, 25 Jan 2002 07:28:00 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         [log in to unmask]

Werner,

Thanks for the numbering info. Thanks as well for the rest. Your following
deserves a reply:

Seriously, though, your "small, but very much on the rise non-manufacturing
oriented telecom
company" will not be rising much farther, if they assemble BGAs/PWAs this
way. I do not think you reallllly need any help with this.

Well, it's up to me to show them the light and error of their ways. So far,
so good.

Can I top this story? Would this qualify? At Bell Labs--the former vibrant
Bell Labs, not the current empty shell--one guy tried to pattent the idea of
putting a screw in the center of the package and fasteninng it to the PCB
through a hole with a nut.

I hesitate to say that idea was brought up in a meeting yesterday. Unreal?

Earl

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Date:         Fri, 25 Jan 2002 09:26:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Electroplated Tin/Lead
MIME-Version: 1.0
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Scott

no pun intened - but your e-mail did say "vary" flat, and yes - you are right
- it does vary. one thing to consider - that when metal is electroplated -
whether it be an alloy or not - now we get into a totally new dimension of
things.

electroplating has to deal with metal distribution across the surface of the
board - if a spec of 300 microinches or so of solder is called for - you
would have to worry about the distribution of the metal across the surface of
the circuity. your low current areas maybe right on the money - but now the
high current areas might be off by as much as 20 to 40% - alldepending on the
set up of the electroplating tank - or vice versa.

if you do decide to go with such a finish - i would suggest having a few
pieces protoed with this finish anf check for the distribution across the
surface of the board.
then there is the "galvanic effect " to contend with as Rudy mentioned in his
e-mail.

a third scenario to contend with is that the working bath is in optimum
operating condition - or the alloy will be way off the 60/40 deposit - (plus
or minus a few percent). in the days of fused solder - keeping that bath in
optimum plating conditions was a nightmare for some fab shops - too high a
current - the higher the tin deposit - too low a current - the higher the
lead deposit.

as i mentioned earlier - find a fab shop or plating shop - and have a few
boards finished with the solder first.

regards

Rich Fudalewski

Florida Cirtech Inc

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Scott
<BR>
<BR>no pun intened - but your e-mail did say "vary" flat, and yes - you are right - it does vary. one thing to consider - that when metal is electroplated - whether it be an alloy or not - now we get into a totally new dimension of things.
<BR>
<BR>electroplating has to deal with metal distribution across the surface of the board - if a spec of 300 microinches or so of solder is called for - you would have to worry about the distribution of the metal across the surface of the circuity. your low current areas maybe right on the money - but now the high current areas might be off by as much as 20 to 40% - alldepending on the set up of the electroplating tank - or vice versa.
<BR>
<BR>if you do decide to go with such a finish - i would suggest having a few pieces protoed with this finish anf check for the distribution across the surface of the board.
<BR>then there is the "galvanic effect " to contend with as Rudy mentioned in his e-mail.
<BR>
<BR>a third scenario to contend with is that the working bath is in optimum operating condition - or the alloy will be way off the 60/40 deposit - (plus or minus a few percent). in the days of fused solder - keeping that bath in optimum plating conditions was a nightmare for some fab shops - too high a current - the higher the tin deposit - too low a current - the higher the lead deposit.
<BR>
<BR>as i mentioned earlier - find a fab shop or plating shop - and have a few boards finished with the solder first.
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>
<BR>Florida Cirtech Inc</FONT></HTML>

--part1_8d.12e552ef.2982c505_boundary--

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Date:         Fri, 25 Jan 2002 08:30:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Robisan Labs and need for x-sectioning

If Susan is out there, I need a couple of x-sections as received and after
thermal stress. Could you reply so we can trade info?

Earl Moon

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Date:         Fri, 25 Jan 2002 15:03:33 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Dawson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Dawson <[log in to unmask]>
Subject:      Re: VERY INTERESTING, TO ME, BGA/CSP STUFF
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

A nut eh?
Surely a self tapping screw, driven home using the theta drive on the pick
and place head would be more efficient?
Regards
Eric Dawson

> -----Original Message-----
> From: Earl Moon [SMTP:[log in to unmask]]
> Sent: Friday, January 25, 2002 1:28 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] VERY INTERESTING, TO ME, BGA/CSP STUFF
>
> Werner,
>
> Thanks for the numbering info. Thanks as well for the rest. Your following
> deserves a reply:
>
> Seriously, though, your "small, but very much on the rise
> non-manufacturing
> oriented telecom
> company" will not be rising much farther, if they assemble BGAs/PWAs this
> way. I do not think you reallllly need any help with this.
>
> Well, it's up to me to show them the light and error of their ways. So
> far,
> so good.
>
> Can I top this story? Would this qualify? At Bell Labs--the former vibrant
> Bell Labs, not the current empty shell--one guy tried to pattent the idea
> of
> putting a screw in the center of the package and fasteninng it to the PCB
> through a hole with a nut.
>
> I hesitate to say that idea was brought up in a meeting yesterday. Unreal?
>
> Earl
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> SET Technet NOMAIL
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> [log in to unmask]: SET Technet Digest
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------

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Date:         Fri, 25 Jan 2002 07:28:17 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Frank L Norman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Frank L Norman <[log in to unmask]>
Subject:      Re: Water soluble solder mask
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Steve,

The batch washer is just like your dishwasher at home. It washes with a
saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
monitored), draining and filling with fresh DI water each time.

Frank Norman
Raytheon
[log in to unmask]
805-879-2745




                    SteveZeva@AOL
                    .COM                 To:     [log in to unmask]
                    Sent by:             cc:
                    TechNet              Subject:     Re: [TN] Water soluble solder mask
                    <[log in to unmask]
                    ORG>


                    01/24/02
                    06:44 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hi Frank!

Question: Are you closed-loop with your water?

-Steve Gregory-


 Hi all,

 Looking for insight about using water soluble solder mask.

 We are currently using a latex solder mask made by Litton. But now the
 question as been asked if water soluble mask could be used instead. Note,
 batch washer(Aqueous Tech. Washer) is used to clean PWAs.

 Frank Norman
 Raytheon

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Date:         Thu, 24 Jan 2002 15:47:38 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ahne Oosterhof <[log in to unmask]>
Subject:      Re: center of a arc
X-To:         Matt Eubank <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

To construct this on paper is real easy. Draw a straight line between two
points on the arc (called a chord). Then use your compass and draw two
circles each with the same radius as the arc, centered on the end points of
the chord. Where these two circles intersect each other is the center of the
arc. (You can choose which one of the two intersections is the correct one.)
To calculate it with geometry is a little more involved:
You know the two points on the arc: x1,y1 and x2,y2. The centerpoint of the
chord is (x1-x2)/2, (y1-y2)/2, or x3,y3. Half the length of the chord is
h=((x3-x1)^2 +(y3-y1)^2)^0.5. This is one side of the right triangle, of
which the hypotenuse is the arc radius and the third side is the distance
from the center of the chord to the center of the arc. Use Pythagorean
theorem once more: (r^2-h^2)^0.5, and you end up where you want to be.

Regards,
Ahne.



-----Original Message-----
From:   TechNet [mailto:[log in to unmask]] On Behalf Of Matt Eubank
Sent:   Thursday, January 24, 2002 07:30
To:     [log in to unmask]
Subject:        [TN] center of a arc

Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.

Thanks
Matt

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Date:         Fri, 25 Jan 2002 11:09:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Water soluble solder mask
X-To:         Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Frank,
What, I believe, Steve is asking is: regarding your washer wastes do you:
* Go to drain
* Reclaim

He is asking you this because some washable temporary solder masks contain
fillers, like clay, that ruin carbon filters used in washer waste
reclaimation systems.

Dave Fish

----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 7:28 AM
Subject: Re: [TN] Water soluble solder mask


> Steve,
>
> The batch washer is just like your dishwasher at home. It washes with a
> saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> monitored), draining and filling with fresh DI water each time.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
>                     SteveZeva@AOL
>                     .COM                 To:     [log in to unmask]
>                     Sent by:             cc:
>                     TechNet              Subject:     Re: [TN] Water
soluble solder mask
>                     <[log in to unmask]
>                     ORG>
>
>
>                     01/24/02
>                     06:44 PM
>                     Please
>                     respond to
>                     "TechNet
>                     E-Mail
>                     Forum.";
>                     Please
>                     respond to
>                     SteveZeva
>
>
>
>
>
>
> Hi Frank!
>
> Question: Are you closed-loop with your water?
>
> -Steve Gregory-
>
>
>  Hi all,
>
>  Looking for insight about using water soluble solder mask.
>
>  We are currently using a latex solder mask made by Litton. But now the
>  question as been asked if water soluble mask could be used instead. Note,
>  batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
>  Frank Norman
>  Raytheon
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
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>

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Date:         Fri, 25 Jan 2002 10:25:28 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Genny Gibbard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Re: center of a arc
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Ahne gets you almost all the way there mathematically.  You now know the
distance from the center of the chord to the center of the circle.  You
don't yet know the actual coordinates of the center.  Apply the Pythagorean
theorem a couple more times and solve the simultaneous equations and you got
it.
From Ahne:
(r^2-h^2)^0.5= d, distance from x3,y3 to x4,y4 (the circle center) we need
to find x4,y4
d^2=(x4-x3)^2 + (y4-y3)^2       two unknowns (x4,y4), one equation
we also know:
r^2=(x4-x1)^2 + (y4-y1)^2       two equations, two unknowns, a little
algebra and it's solved

Whew, it is much easier just with a compass and a ruler!!!

-----Original Message-----
From: Ahne Oosterhof [mailto:[log in to unmask]]
Sent: January 24, 2002 5:48 PM
To: [log in to unmask]
Subject: Re: [TN] center of a arc


To construct this on paper is real easy. Draw a straight line between two
points on the arc (called a chord). Then use your compass and draw two
circles each with the same radius as the arc, centered on the end points of
the chord. Where these two circles intersect each other is the center of the
arc. (You can choose which one of the two intersections is the correct one.)
To calculate it with geometry is a little more involved:
You know the two points on the arc: x1,y1 and x2,y2. The centerpoint of the
chord is (x1-x2)/2, (y1-y2)/2, or x3,y3. Half the length of the chord is
h=((x3-x1)^2 +(y3-y1)^2)^0.5. This is one side of the right triangle, of
which the hypotenuse is the arc radius and the third side is the distance
from the center of the chord to the center of the arc. Use Pythagorean
theorem once more: (r^2-h^2)^0.5, and you end up where you want to be.

Regards,
Ahne.



-----Original Message-----
From:   TechNet [mailto:[log in to unmask]] On Behalf Of Matt Eubank
Sent:   Thursday, January 24, 2002 07:30
To:     [log in to unmask]
Subject:        [TN] center of a arc

Need some help.
What is the equation for finding the center of a arc given the radius and 2
points on the arc.

Thanks
Matt

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=========================================================================
Date:         Fri, 25 Jan 2002 08:39:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Popielarski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Popielarski <[log in to unmask]>
Subject:      Lunch at Apex (NTC)
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_001C_01C1A57B.C4CE4F20"

This is a multi-part message in MIME format.

------=_NextPart_000_001C_01C1A57B.C4CE4F20
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi all,

Just wanted to drop a line to let everyone know that the Apex lunch =
thing did happen. We met at the IPC booth, and coincidentally, Mr. Bev =
Christian, Ph.D. was browsing the bookstand. Also in attendance was =
Graham Collins, Kathy and Joe Palumbo with their sales folks, Arlene and =
Evie (not technetters), Don Roy and Scott Kramer and myself. We =
"invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" =
The rudest, most irreverent service this side of the Mississippi. It was =
a pleasure to meet these folks in person, and I urge that next year, we =
do the same. Maybe a few more of the infamous technet participants will =
show up (nudge, nudge, Steve and Earl!)=20

Have a great weekend!

Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618

Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578

WWW.QTA.NET

------=_NextPart_000_001C_01C1A57B.C4CE4F20
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Just wanted to drop a line to let =
everyone know=20
that the Apex lunch thing did happen. We met at the IPC booth, and=20
coincidentally, Mr. Bev Christian, Ph.D. was browsing the bookstand. =
Also in=20
attendance was Graham Collins, Kathy and Joe Palumbo with their sales =
folks,=20
Arlene and Evie (not technetters), Don Roy and Scott Kramer and myself. =
We=20
"invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" =
The=20
rudest, most irreverent service this side of the Mississippi. It was a =
pleasure=20
to meet these folks in person, and I urge that next year, we do the =
same. Maybe=20
a few more of the infamous technet participants will show up (nudge, =
nudge,=20
Steve and Earl!) </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Have a great weekend!</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>

------=_NextPart_000_001C_01C1A57B.C4CE4F20--

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=========================================================================
Date:         Fri, 25 Jan 2002 16:49:07 -0000
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Fenner <[log in to unmask]>
Subject:      Re: Water soluble solder mask
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

The concern would be that some masks have a very fine powder filler. This
might raise some concerns, for example it could accumulate in closed loop
systems.

Kind Regards

Mike Fenner

Applications Engineer, European Operations
Indium Corporation
 T: + 44 1908 580 400
M: + 44 7810 526 317
 F: + 44 1908 580 411
 E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Frank L Norman
Sent: Friday, January 25, 2002 3:28 PM
To: [log in to unmask]
Subject: Re: [TN] Water soluble solder mask


Steve,

The batch washer is just like your dishwasher at home. It washes with a
saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
monitored), draining and filling with fresh DI water each time.

Frank Norman
Raytheon
[log in to unmask]
805-879-2745




                    SteveZeva@AOL
                    .COM                 To:     [log in to unmask]
                    Sent by:             cc:
                    TechNet              Subject:     Re: [TN] Water soluble
solder mask
                    <[log in to unmask]
                    ORG>


                    01/24/02
                    06:44 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hi Frank!

Question: Are you closed-loop with your water?

-Steve Gregory-


 Hi all,

 Looking for insight about using water soluble solder mask.

 We are currently using a latex solder mask made by Litton. But now the
 question as been asked if water soluble mask could be used instead. Note,
 batch washer(Aqueous Tech. Washer) is used to clean PWAs.

 Frank Norman
 Raytheon

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Date:         Fri, 25 Jan 2002 09:00:32 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Frank L Norman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Frank L Norman <[log in to unmask]>
Subject:      Re: Water soluble solder mask
X-To:         David Fish <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Steve,

Goes to drain.

Frank Norman
Raytheon
[log in to unmask]
805-879-2745




                    "David Fish"
                    <dfish@icubed        To:     "TechNet E-Mail Forum." <[log in to unmask]>, "Frank L Norman"
                    .com>                <[log in to unmask]>
                                         cc:
                    01/25/02             Subject:     Re:      Re: [TN] Water soluble solder mask
                    11:09 AM






Frank,
What, I believe, Steve is asking is: regarding your washer wastes do you:
* Go to drain
* Reclaim

He is asking you this because some washable temporary solder masks contain
fillers, like clay, that ruin carbon filters used in washer waste
reclaimation systems.

Dave Fish

----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 7:28 AM
Subject: Re: [TN] Water soluble solder mask


> Steve,
>
> The batch washer is just like your dishwasher at home. It washes with a
> saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> monitored), draining and filling with fresh DI water each time.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
>                     SteveZeva@AOL
>                     .COM                 To:     [log in to unmask]
>                     Sent by:             cc:
>                     TechNet              Subject:     Re: [TN] Water
soluble solder mask
>                     <[log in to unmask]
>                     ORG>
>
>
>                     01/24/02
>                     06:44 PM
>                     Please
>                     respond to
>                     "TechNet
>                     E-Mail
>                     Forum.";
>                     Please
>                     respond to
>                     SteveZeva
>
>
>
>
>
>
> Hi Frank!
>
> Question: Are you closed-loop with your water?
>
> -Steve Gregory-
>
>
>  Hi all,
>
>  Looking for insight about using water soluble solder mask.
>
>  We are currently using a latex solder mask made by Litton. But now the
>  question as been asked if water soluble mask could be used instead.
Note,
>  batch washer(Aqueous Tech. Washer) is used to clean PWAs.
>
>  Frank Norman
>  Raytheon
>
>
--------------------------------------------------------------------------
-------
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> To unsubscribe, send a message to [log in to unmask] with following text in
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> Search previous postings at: www.ipc.org > On-Line Resources & Databases
>
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
>
--------------------------------------------------------------------------
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>

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Date:         Fri, 25 Jan 2002 12:22:16 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Water soluble solder mask
X-To:         Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Frank,
Try:
* Alpha 110 HV
* Techspray Wondermask  2207G

Both 110 and Wondermask are highly ionic and are "SIR killers" [Doug
'Do-The-Do' Pauls' words], but since you're aqueous processing these boards
it may not be BIG concern.

Dave Fish

----- Original Message -----
From: "Frank L Norman" <[log in to unmask]>
To: "David Fish" <[log in to unmask]>
Cc: "TechNet E-Mail Forum." <[log in to unmask]>
Sent: Friday, January 25, 2002 9:00 AM
Subject: Re: Re: [TN] Water soluble solder mask


>
> Steve,
>
> Goes to drain.
>
> Frank Norman
> Raytheon
> [log in to unmask]
> 805-879-2745
>
>
>
>
>                     "David Fish"
>                     <dfish@icubed        To:     "TechNet E-Mail Forum."
<[log in to unmask]>, "Frank L Norman"
>                     .com>                <[log in to unmask]>
>                                          cc:
>                     01/25/02             Subject:     Re:      Re: [TN]
Water soluble solder mask
>                     11:09 AM
>
>
>
>
>
>
> Frank,
> What, I believe, Steve is asking is: regarding your washer wastes do you:
> * Go to drain
> * Reclaim
>
> He is asking you this because some washable temporary solder masks contain
> fillers, like clay, that ruin carbon filters used in washer waste
> reclaimation systems.
>
> Dave Fish
>
> ----- Original Message -----
> From: "Frank L Norman" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Friday, January 25, 2002 7:28 AM
> Subject: Re: [TN] Water soluble solder mask
>
>
> > Steve,
> >
> > The batch washer is just like your dishwasher at home. It washes with a
> > saponifier for 9 minutes then preforms about 10 rinse cycles(resistivity
> > monitored), draining and filling with fresh DI water each time.
> >
> > Frank Norman
> > Raytheon
> > [log in to unmask]
> > 805-879-2745
> >
> >
> >
> >
> >                     SteveZeva@AOL
> >                     .COM                 To:     [log in to unmask]
> >                     Sent by:             cc:
> >                     TechNet              Subject:     Re: [TN] Water
> soluble solder mask
> >                     <[log in to unmask]
> >                     ORG>
> >
> >
> >                     01/24/02
> >                     06:44 PM
> >                     Please
> >                     respond to
> >                     "TechNet
> >                     E-Mail
> >                     Forum.";
> >                     Please
> >                     respond to
> >                     SteveZeva
> >
> >
> >
> >
> >
> >
> > Hi Frank!
> >
> > Question: Are you closed-loop with your water?
> >
> > -Steve Gregory-
> >
> >
> >  Hi all,
> >
> >  Looking for insight about using water soluble solder mask.
> >
> >  We are currently using a latex solder mask made by Litton. But now the
> >  question as been asked if water soluble mask could be used instead.
> Note,
> >  batch washer(Aqueous Tech. Washer) is used to clean PWAs.
> >
> >  Frank Norman
> >  Raytheon
> >
> >
> --------------------------------------------------------------------------
> -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
> SET Technet NOMAIL
> > To receive ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> > Search previous postings at: www.ipc.org > On-Line Resources & Databases
> >
> E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> >
> --------------------------------------------------------------------------
> -------
> >
>
>
>
>
>
>

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=========================================================================
Date:         Fri, 25 Jan 2002 10:56:51 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Barmuta, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Barmuta, Mike" <[log in to unmask]>
Subject:      Re: Water soluble solder mask
X-To:         Frank L Norman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Frank: Some things to consider for temporary water soluble solder mask:

1. Method of application: screen print, auto-dispense XY system, hand
application, etc.
Board volume and feature complexity can influence choice of application.

2. Type of material: filled, unfilled, water base, alcohol base etc .
Method of application, type of cure, dissolution rate, type of washing
equipment/chemistry, assembly compatibility SMT-wavesolder-mixed technology
need to be considered for material choice.

3.Board features to be masked: large features, cut-outs, melting metals etc.

These types of masks usually don't do well over large areas or spanning
cut-outs larger than about 0.300 - 0.400", they can also have a tendency to
flake or crack when used on Sn/Pb when subject to melting temperatures.

4. Applied mask shelflife and storage: masked board storage conditions,
method of storage, hold times prior to use etc.
The humidity, how boards are stored ie wrapped-unwrapped-slip sheets-flat
stacked-edge stacked, hold times greater than three to six months can all
influence the ability of the material to perform correctly.



Michael Barmuta

Staff Engineer

Fluke Corp.

Everett WA

425-446-6076

-----Original Message-----
From: Frank L Norman [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 6:22 PM
To: [log in to unmask]
Subject: [TN] Water soluble solder mask


Hi all,

Looking for insight about using water soluble solder mask.

We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.

Frank Norman
Raytheon

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Date:         Fri, 25 Jan 2002 14:08:23 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Creative Engineering and Manufacturing Methods..
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_16b.7b88968.29830727_boundary"

--part1_16b.7b88968.29830727_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi all!

Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments   B^}

-Steve Gregory-

--part1_16b.7b88968.29830727_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi all!
<BR>
<BR>Earl sent me a photo showing a fine example of Creative Engineering and Manufacturing methods, and invites any comments &nbsp;&nbsp;B^}
<BR>
<BR>-Steve Gregory-</FONT></HTML>

--part1_16b.7b88968.29830727_boundary--

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Date:         Fri, 25 Jan 2002 14:21:36 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Water soluble solder mask
X-To:         "Barmuta, Mike" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Frank:

Two more considerations:
   UV curable water-soluble (in lieu of waiting 30-60 minutes to cure the
   mask)
   Water-soluble tape or tape dots for large holes.

Al Kreplick
Sr. Mfg. Eng.
Teradyne, Inc.
North Reading, MA
978-370-1726



 (Embedded
 image moved   TechNet <[log in to unmask]>
 to file:      01/25/2002 01:56 PM
 pic27666.pcx)




Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
      to "Barmuta, Mike" <[log in to unmask]>

To:   [log in to unmask]
cc:
Subject:  Re: [TN] Water soluble solder mask


Frank: Some things to consider for temporary water soluble solder mask:

1. Method of application: screen print, auto-dispense XY system, hand
application, etc.
Board volume and feature complexity can influence choice of application.

2. Type of material: filled, unfilled, water base, alcohol base etc .
Method of application, type of cure, dissolution rate, type of washing
equipment/chemistry, assembly compatibility SMT-wavesolder-mixed technology
need to be considered for material choice.

3.Board features to be masked: large features, cut-outs, melting metals
etc.

These types of masks usually don't do well over large areas or spanning
cut-outs larger than about 0.300 - 0.400", they can also have a tendency to
flake or crack when used on Sn/Pb when subject to melting temperatures.

4. Applied mask shelflife and storage: masked board storage conditions,
method of storage, hold times prior to use etc.
The humidity, how boards are stored ie wrapped-unwrapped-slip sheets-flat
stacked-edge stacked, hold times greater than three to six months can all
influence the ability of the material to perform correctly.



Michael Barmuta

Staff Engineer

Fluke Corp.

Everett WA

425-446-6076

-----Original Message-----
From: Frank L Norman [mailto:[log in to unmask]]
Sent: Thursday, January 24, 2002 6:22 PM
To: [log in to unmask]
Subject: [TN] Water soluble solder mask


Hi all,

Looking for insight about using water soluble solder mask.

We are currently using a latex solder mask made by Litton. But now the
question as been asked if water soluble mask could be used instead. Note,
batch washer(Aqueous Tech. Washer) is used to clean PWAs.

Frank Norman
Raytheon

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Date:         Fri, 25 Jan 2002 13:05:58 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              My Nguyen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      How to convert a .dwg to .pdf
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello all,

Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.

Is there any way for it?  Please advise!

You all have a great weekend!

M.N

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Fri, 25 Jan 2002 22:19:41 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "D.Terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0020_01C1A5EE.625DD2C0"

This is a multi-part message in MIME format.

------=_NextPart_000_0020_01C1A5EE.625DD2C0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I had already heard about IPC class 0 (that's when the components come =
separate,  in a box). I suppose this is IPC class =BD ?  The product =
works, but it's supplied with some extra's to keep it that way......

Daan Terstegge
http://www.smtinfo.net

  ----- Original Message -----=20
  From: [log in to unmask]
  To: [log in to unmask]
  Sent: Friday, January 25, 2002 8:08 PM
  Subject: [TN] Creative Engineering and Manufacturing Methods..


  Hi all!=20

  Earl sent me a photo showing a fine example of Creative Engineering =
and Manufacturing methods, and invites any comments   B^}=20

  -Steve Gregory-=20

------=_NextPart_000_0020_01C1A5EE.625DD2C0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I had already heard about IPC class 0 =
(that's when=20
the&nbsp;components&nbsp;come separate,&nbsp; in a box). I suppose this =
is IPC=20
class&nbsp;=BD ?&nbsp; The product works, but it's supplied with some =
extra's to=20
keep it that way......</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Daan Terstegge</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>http://<A=20
href=3D"http://www.smtinfo.net">www.smtinfo.net</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, 2002 =
8:08=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Creative =
Engineering and=20
  Manufacturing Methods..</DIV>
  <DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Hi all! =
<BR><BR>Earl=20
  sent me a photo showing a fine example of Creative Engineering and=20
  Manufacturing methods, and invites any comments &nbsp;&nbsp;B^} =
<BR><BR>-Steve=20
  Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_0020_01C1A5EE.625DD2C0--

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=========================================================================
Date:         Fri, 25 Jan 2002 16:55:47 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

You will need a full copy of Adobe Acrobat. (street price about $218.00) =
 Adobe Acrobat Reader will not convert the files.

Once Adobe Acrobat is installed, from AutoCAD, print the drawing like =
you normally would, but select the "Adobe Distiller" as your printing =
device.

All other users who are viewing your output PDF files will need a copy =
of Adobe Acrobat Reader installed. This is a free download from =
www.adobe.com.

Happy converting.

Phil Nutting

-----Original Message-----
From: My Nguyen [mailto:[log in to unmask]]
Sent: Friday, January 25, 2002 4:06 PM
To: [log in to unmask]
Subject: [TN] How to convert a .dwg to .pdf


Hello all,

Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.

Is there any way for it?  Please advise!

You all have a great weekend!

M.N

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

-------------------------------------------------------------------------=
--------
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To unsubscribe, send a message to [log in to unmask] with following text =
in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to [log in to unmask]: =
SET Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to =
[log in to unmask]: SET Technet Digest
Search previous postings at: www.ipc.org > On-Line Resources & Databases =
> E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 =
ext.5315
-------------------------------------------------------------------------=
--------

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Date:         Fri, 25 Jan 2002 16:33:30 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0002_01C1A5BE.05C720F0"

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Oh my goodness!  Earl told us, but a picture is worth a thousand words.  I
wonder if there is a torque specification for that thar adjustable
continuity mak'in device.

I've seen lab types do similar stuff before and ask if the added "fix" can
be applied to production to get their design shipped because the project is
behind schedule.

Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 1:08 PM
To: [log in to unmask]
Subject: [TN] Creative Engineering and Manufacturing Methods..


Hi all!

Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments   B^}

-Steve Gregory-

------=_NextPart_000_0002_01C1A5BE.05C720F0
Content-Type: text/html;
        charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>Oh my=20
goodness!&nbsp; Earl told us, but a picture is worth a thousand =
words.&nbsp; I=20
wonder if there is a torque specification for that thar adjustable =
continuity=20
mak'in device.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D910312822-25012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>I've=20
seen lab types do similar stuff before and ask if the added&nbsp;"fix" =
can be=20
applied to production to get their design shipped because the project is =
behind=20
schedule.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D910312822-25012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D910312822-25012002>Don=20
Vischulis</SPAN></FONT></DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Friday, January 25, 2002 1:08 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Creative Engineering and =
Manufacturing=20
Methods..<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi all!=20
<BR><BR>Earl sent me a photo showing a fine example of Creative =
Engineering and=20
Manufacturing methods, and invites any comments &nbsp;&nbsp;B^} =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BODY></HTML>

------=_NextPart_000_0002_01C1A5BE.05C720F0--

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=========================================================================
Date:         Fri, 25 Jan 2002 16:50:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]

Daan,

As usual astute as ever. I like it and propose you propose the class to IPC.
Hell, It's a happening. You saw it here first.

Earl

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Date:         Fri, 25 Jan 2002 16:53:08 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]

Yes sir,

Specified torque values are currently being developed relative to final
reliability studies. I want us to hire Werner, and all other volunteers, to
perform the studies.

MoonMan

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Date:         Fri, 25 Jan 2002 16:56:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Genny Gibbard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Genny Gibbard <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
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        charset="iso-8859-1"

It's a standing joke around here that one of the RnD projects is to design a
'simulated finger' material.  For our purposes, it usually isn't a lot of
pressure that is needed.  So I envision a foam type product with an adhesive
on one side that you cut pieces to the size and shape you desire to place on
that unstable RF oscillator...


-----Original Message-----
From: Don Vischulis [mailto:[log in to unmask]]
Sent: January 25, 2002 4:34 PM
To: [log in to unmask]
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..


Oh my goodness!  Earl told us, but a picture is worth a thousand words.  I
wonder if there is a torque specification for that thar adjustable
continuity mak'in device.

I've seen lab types do similar stuff before and ask if the added "fix" can
be applied to production to get their design shipped because the project is
behind schedule.

Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 1:08 PM
To: [log in to unmask]
Subject: [TN] Creative Engineering and Manufacturing Methods..


Hi all!

Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments   B^}

-Steve Gregory-


------_=_NextPart_001_01C1A5F3.8E4ECF10
Content-Type: text/html;
        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 5.00.3315.2870" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=723325222-25012002>It's a
standing joke around here that one of the RnD projects is to design a 'simulated
finger' material.&nbsp; For our purposes, it usually isn't a lot of pressure
that is needed.&nbsp; So I envision a foam type product with an adhesive on one
side that you cut pieces to the size and shape you desire to place on that
unstable RF oscillator...</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=723325222-25012002></SPAN></FONT>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Don Vischulis
  [mailto:[log in to unmask]]<BR><B>Sent:</B> January 25, 2002 4:34
  PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Creative
  Engineering and Manufacturing Methods..<BR><BR></DIV></FONT>
  <DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>Oh
  my goodness!&nbsp; Earl told us, but a picture is worth a thousand
  words.&nbsp; I wonder if there is a torque specification for that thar
  adjustable continuity mak'in device.</SPAN></FONT></DIV>
  <DIV><FONT color=#0000ff face=Arial size=2><SPAN
  class=910312822-25012002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>I've
  seen lab types do similar stuff before and ask if the added&nbsp;"fix" can be
  applied to production to get their design shipped because the project is
  behind schedule.</SPAN></FONT></DIV>
  <DIV><FONT color=#0000ff face=Arial size=2><SPAN
  class=910312822-25012002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT color=#0000ff face=Arial size=2><SPAN class=910312822-25012002>Don
  Vischulis</SPAN></FONT></DIV>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> TechNet
  [mailto:[log in to unmask]]<B>On Behalf Of </B>[log in to unmask]<BR><B>Sent:</B>
  Friday, January 25, 2002 1:08 PM<BR><B>To:</B>
  [log in to unmask]<BR><B>Subject:</B> [TN] Creative Engineering and Manufacturing
  Methods..<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi all!
  <BR><BR>Earl sent me a photo showing a fine example of Creative Engineering
  and Manufacturing methods, and invites any comments &nbsp;&nbsp;B^}
  <BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C1A5F3.8E4ECF10--

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Date:         Fri, 25 Jan 2002 15:02:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Snyder <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Snyder <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         My Nguyen <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

You need to buy Adobe Acrobat. The reader is free but if you want to make
pdf's, you need to buy Acrobat (List $249 USD).

Dave Snyder
Manf. Eng. Manager
HM Electronics, Inc.

 -----Original Message-----
From:   My Nguyen [mailto:[log in to unmask]]
Sent:   Friday, January 25, 2002 1:06 PM
To:     [log in to unmask]
Subject:        [TN] How to convert a .dwg to .pdf

Hello all,

Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.

Is there any way for it?  Please advise!

You all have a great weekend!

M.N

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Fri, 25 Jan 2002 15:12:26 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Carl VanWormer <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Carl VanWormer <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         My Nguyen <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

There is a free PDF conversion process at
http://www.webxd.com/zipguy/frpdfdl.htm that is a bit of a pain to set up,
but I've been using for a year with very good results.




Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR  97006
Phone (503)-617-7447    Fax (503)-617-6550

 -----Original Message-----
From:   My Nguyen [mailto:[log in to unmask]]
Sent:   Friday, January 25, 2002 1:06 PM
To:     [log in to unmask]
Subject:        [TN] How to convert a .dwg to .pdf

Hello all,

Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.

Is there any way for it?  Please advise!

You all have a great weekend!

M.N

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Fri, 25 Jan 2002 15:13:15 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Denis Lefebvre <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Denis Lefebvre <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         My Nguyen <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

It simply requires that you have Adobe Acrobat [full version, not just the
reader] installed on your PC.
With Acrobat installed, simply go to print and select the Acrobat PDF
Writer as your printer. VIOLA! A PDF file!

Denis Lefebvre, C.I.D.
Senior PCB Designer
Salinas, CA 93906

At 01:05 PM 1/25/2002 -0800, you wrote:
>Hello all,
>
>Not all my company have Autocad 2000, thus, they
>wanted me to convert my drawings into pdf format.
>Unfortunately, I don't know how.
>
>Is there any way for it?  Please advise!
>
>You all have a great weekend!
>
>M.N
>
>__________________________________________________
>Do You Yahoo!?
>Great stuff seeking new owners in Yahoo! Auctions!
>http://auctions.yahoo.com
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
>

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Date:         Fri, 25 Jan 2002 17:21:09 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]

Genny,

A little askew but some folks at HAC, years ago, designed some impedence
controlled flex stuff with styrofoam to emulate the Dk of air. Didn't work
but thought I'd bring this up because without such a low dielectric constant
broadband is history.

MoonMan

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Date:         Fri, 25 Jan 2002 17:23:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         [log in to unmask]

Denis,

Thanks for the good input. My printer here defaults to .pdf. I'm going to
use it soon.

Earl

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Date:         Fri, 25 Jan 2002 18:18:59 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ron Olinyk <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ron Olinyk <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         My Nguyen <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

m.n.
Probably the easiest way is to install the PDFWriter printer driver from
Adobe then set this as your printer in Acad, printing the dwg as you
normally would. If you don't have Adobe Acrobat, you can setup a PS printer
driver like AppleWriter, print to file as a PS then use a PS to PDF utility
like with Ghostscript to gen the PDF doc.
Ron O.
At 01:05 PM 1/25/02 -0800, you wrote:
>Hello all,
>
>Not all my company have Autocad 2000, thus, they
>wanted me to convert my drawings into pdf format.
>Unfortunately, I don't know how.
>
>Is there any way for it?  Please advise!
>
>You all have a great weekend!
>
>M.N
>
>__________________________________________________
>Do You Yahoo!?
>Great stuff seeking new owners in Yahoo! Auctions!
>http://auctions.yahoo.com
>
>---------------------------------------------------------------------------------
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>ext.5315
>---------------------------------------------------------------------------------

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Date:         Fri, 25 Jan 2002 20:11:57 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Creative Engineering and Manufacturing Methods..
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Just realized that I didn't post the URL...here it is:

http://www.stevezeva.homestead.com/

-Steve Gregory-

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Date:         Fri, 25 Jan 2002 20:42:11 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Lunch at Apex (NTC)
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_139.8516436.29836373_boundary"

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Hi Ed!

From the phone-call that we had, sounds like Dick's Last Resort is one fun
place!

Maybe next year it'll be my turn...scratch that, I'll go no matter what. I'll
take PTO (Personal Time Off) and pay for things myself if the trip isn't
funded. San Diego ain't a bad place to take a vacation anyway...

One thing from your post that interests me, and it always had me wondering
(hoping that Kathy has her TechNet ears on), is that I served with a Aviation
Ordnanceman with the last name Palumbo...I think his first name was Michael,
but not really sure...been a while ago...maybe a relative of theirs.

One thing about being in the military, you remember military people that you
served with by their last names...the people that you got close with, you
learned their first names.

Just curious if there's any connection. The Palumbo guy and me served in
Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in
1985...

-Steve Gregory-


> Hi all,
>
> Just wanted to drop a line to let everyone know that the Apex lunch thing
> did happen. We met at the IPC booth, and coincidentally, Mr. Bev Christian,
> Ph.D. was browsing the bookstand. Also in attendance was Graham Collins,
> Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not
> technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's Last
> Resort and everyone agreed that it was "a hoot!" The rudest, most
> irreverent service this side of the Mississippi. It was a pleasure to meet
> these folks in person, and I urge that next year, we do the same. Maybe a
> few more of the infamous technet participants will show up (nudge, nudge,
> Steve and Earl!)
>
> Have a great weekend!
>
> Regards,
>
> Ed Popielarski
> QTA Machine
> 10 Mc Laren, Ste D
> Irvine, Ca. 92618
>
> Phone:949-581-6601
> Fax: 949-581-2448
> Cel: 949-337-2578
>
> <A HREF="http://www.qta.net/">WWW.QTA.NET</A>
>


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Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Ed!<BR>
<BR>
From the phone-call that we had, sounds like Dick's Last Resort is one fun place!<BR>
<BR>
Maybe next year it'll be my turn...scratch that, I'll go no matter what. I'll take PTO (Personal Time Off) and pay for things myself if the trip isn't funded. San Diego ain't a bad place to take a vacation anyway...<BR>
<BR>
One thing from your post that interests me, and it always had me wondering (hoping that Kathy has her TechNet ears on), is that I served with a Aviation Ordnanceman with the last name Palumbo...I think his first name was Michael, but not really sure...been a while ago...maybe a relative of theirs.<BR>
<BR>
One thing about being in the military, you remember military people that you served with by their last names...the people that you got close with, you learned their first names.<BR>
<BR>
Just curious if there's any connection. The Palumbo guy and me served in Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in 1985...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Just wanted to drop a line to let everyone know that the Apex lunch thing did happen. We met at the IPC booth, and coincidentally, Mr. Bev Christian, Ph.D. was browsing the bookstand. Also in attendance was Graham Collins, Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's Last Resort and everyone agreed that it was "a hoot!" The rudest, most irreverent service this side of the Mississippi. It was a pleasure to meet these folks in person, and I urge that next year, we do the same. Maybe a few more of the infamous technet participants will show up (nudge, nudge, Steve and Earl!) </FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Have a great weekend!</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Regards,</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Ed Popielarski<BR>
QTA Machine<BR>
10 Mc Laren, Ste D<BR>
Irvine, Ca. 92618</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Phone:949-581-6601<BR>
Fax: 949-581-2448<BR>
Cel: 949-337-2578</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
 <BR>
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Date:         Fri, 25 Jan 2002 20:12:41 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]org>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
In-Reply-To:  <[log in to unmask]>
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Hey Earl

This is telecom, right?  Doesn't GR78 become one of the governing docs?
Better start testing the balsa wood for SIR and ionics.  Inner layers too if
the balsa is laminated.

Don Vischulis

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Friday, January 25, 2002 7:12 PM
To: [log in to unmask]
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..


Just realized that I didn't post the URL...here it is:

http://www.stevezeva.homestead.com/

-Steve Gregory-

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Date:         Sat, 26 Jan 2002 01:52:15 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]

Don,

Notwithstanding your serious concerns, ESD is an issue as well. I have
recommended a move away from balsa to a more electrically friendly type wood.

Soon, I will be traveling to Brazil to talk with an enture tribe of
technically astute Amazon ladies who have started a new venture for what
they see as a growth industry focused on users like me. In this light, we
will work very closely together developing new offspring of currently
available arborial saplings providing the characteristics required to
neutralize current deficiencies.

I hope you and all our friends out there realize such dedication and
creativism is born out of DFM/CE and the hard, fast rules making it
possible. Also, realize the "C" clamp business will find new prosperity.
This brings to mind trememdous investment possibilties for all those having
lost their money and asses, not withstanding gunshot wounds to the head, at
Enron.

Kind Regards and wish me well as I do you all,

MoonSapMan

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Date:         Sat, 26 Jan 2002 09:23:01 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "D.Terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
X-To:         My Nguyen <[log in to unmask]>
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An alternative is JAWS PDF Creator. It's been said that it's better than =
Acrobat, and it sure is cheaper.
At  http://www.jawssystems.com/ you can download a free trial version.

Daan
http://www.smtinfo.net
  ----- Original Message -----=20
  From: My Nguyen=20
  To: [log in to unmask]
  Sent: Friday, January 25, 2002 10:05 PM
  Subject: [TN] How to convert a .dwg to .pdf


  Hello all,

  Not all my company have Autocad 2000, thus, they
  wanted me to convert my drawings into pdf format.
  Unfortunately, I don't know how.

  Is there any way for it?  Please advise!

  You all have a great weekend!

  M.N

  __________________________________________________
  Do You Yahoo!?
  Great stuff seeking new owners in Yahoo! Auctions!
  http://auctions.yahoo.com

  =
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charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>
<DIV><FONT face=3DArial size=3D2>An alternative is JAWS PDF Creator. =
It's been said=20
that it's better than Acrobat, and it sure is cheaper.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>At&nbsp; <A=20
href=3D"http://www.jawssystems.com/">http://www.jawssystems.com/</A>&nbsp=
;you can=20
download a free trial version.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Daan</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV></=
DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask] =
href=3D"mailto:[log in to unmask]">My=20
  Nguyen</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, 2002 =
10:05=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] How to convert a =
.dwg to=20
  .pdf</DIV>
  <DIV><BR></DIV>Hello all,<BR><BR>Not all my company have Autocad 2000, =
thus,=20
  they<BR>wanted me to convert my drawings into pdf =
format.<BR>Unfortunately, I=20
  don't know how.<BR><BR>Is there any way for it?&nbsp; Please=20
  advise!<BR><BR>You all have a great=20
  =
weekend!<BR><BR>M.N<BR><BR>______________________________________________=
____<BR>Do=20
  You Yahoo!?<BR>Great stuff seeking new owners in Yahoo! =
Auctions!<BR><A=20
  =
href=3D"http://auctions.yahoo.com">http://auctions.yahoo.com</A><BR><BR>-=
-------------------------------------------------------------------------=
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Date:         Sat, 26 Jan 2002 08:52:48 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
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I love the K-Mart [plastic] bag in the background of the pix.

Dave Fish
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, January 25, 2002 5:11 PM
Subject: Re: [TN] Creative Engineering and Manufacturing Methods..


> Just realized that I didn't post the URL...here it is:
>
> http://www.stevezeva.homestead.com/
>
> -Steve Gregory-
>
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Date:         Sat, 26 Jan 2002 08:37:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]

What you see came not from my favorite store - the one you put me on to
about two years ago when I needed a bottom side board heater (turned out to
be a pancake griddle as a blue light special) - that I have not been in
since. Gonna miss those folks. Very smart business people. The bag is one
for toting my six pack, from a highly respected Armenian deli, near work and
my palacial suite high above the Cayahoga river and sewage outlet.

Ok, so ESD isn't a big issue around my desk (out back in the bleachers).
However, it will be soon.

For Brian, the folks at this company are some of the brightest, most
creative people I've met in some time. They have the unrestrained freedom to
develop and build product any way they see fit.

The standing joke is "quality system - what a unique concept." Yes folks,
I'm starting at the bottom (whale shit is above my level kinda like an IMC
layer) with this one but one needs a measure of job security in these
trying, economically compromised times. This little project should take no
more than a year or so - then back to my social club in BF Montana.

MoonBagMan

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Date:         Sat, 26 Jan 2002 13:30:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      (OT) Earl Moon Endowment Fund...
MIME-Version: 1.0
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I know Earl is a man of many, many talents, but I didn't know that he had a
college sponsoring tuitions in his name...I think they've been a little
premature saying that it's a "Memorial Endowment Fund" though...he's alive
and kicking as far as we know?

Check this out:

http://www.spebsqsa.org/HCDC/earlmoon.htm

hehehe...

-Steve Gregory-

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Date:         Sat, 26 Jan 2002 15:22:07 -0800
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Date:         Sat, 26 Jan 2002 19:27:54 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: (OT) Earl Moon Endowment Fund...
X-To:         [log in to unmask]

Steve,

As with most things in which you take interest, this didn't escape your
sharp eye and keen inquisitiveness. It is true I'm not yet departed, but
this is the point.

All of you out there may take advantage of a secret told me by a very wise
person many years ago. You too may find it advantageous to set up a college
endowment before your time is at an end.

For a small stipend, I will share this fabulous secret that will make you
rich, though not in dollars, beyond your fondest dreams. Simply send me a
large self addressed box, capable of holding many pounds of electronic waste
(produced by creative minds without constraint or rules and no DFM/CE
program) and a few dollars, and I'll send you the effect of that creativity.

Yes folks, you can make it big and bad by allowing me to take the pressure
off your consciences allowing you to run amuck much as most of my clients.
Why be different. Go for it. You may not become successful or rich (leave
that to me), but think of the freedom you'll enjoy without creative constraint.

I look forward to your responses (make cashier's checks payable to MoonMan).

MoonEndowedMan

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Date:         Sun, 27 Jan 2002 16:28:09 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              hsinsun <[log in to unmask]>
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Subject:      886-2-27924598   Design &
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; E – Coating, Painting Plating`s Peripherals & Equipments E-Mail :[log in to unmask]        [log in to unmask] Web Site: http:// www.john-young.com.tw          http:// johnyoung.tisnet.net.tw/   .

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Date:         Sat, 26 Jan 2002 12:51:50 +0000
Reply-To:     Roger Bilham <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Roger Bilham <[log in to unmask]>
Subject:      Re: Lead replacement solder alloys
In-Reply-To:  <002b01c1a586$8bbcc710$f502a8c0@ukomfenner>
MIME-Version: 1.0
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Mike,

I would like to add a third type of lead free alloy, namely allegedly
patented. There are a lot of patent applications out there that will
never make it to being granted patents and a number of patents granted
but invalid! No names, no pack drill.

Roger

In article <002b01c1a586$8bbcc710$f502a8c0@ukomfenner>, Mike Fenner
<[log in to unmask]> writes
>    Lead free alloys come in 2 types: generic and
>    proprietary/patented.  The more alloying additions the more likely
>    the alloy is to fall into the second category.
>    Generic alloys are available from just about any recognised solder
>    manufacturer, proprietary alloys are available from the patent
>    holder and any licensees.
>    If the alloy has actual or perceived merit for general
>    industry use then it is likely you will find that other
>    manufacturers have licensed it and you can again obtain it from
>    just about any recognised manufacturer
>
>
>    Kind Regards
>
>    Mike Fenner
>
>    Applications Engineer, European Operations
>    Indium Corporation
>     T: + 44 1908 580 400
>    M: + 44 7810 526 317
>     F: + 44 1908 580 411
>     E: [log in to unmask]
>    W: www.indium.com
>    Leadfree: www.Pb-Free.com
>
>>       -----Original Message-----
>>       From: TechNet [mailto:[log in to unmask]]On Behalf Of
>>       [log in to unmask]
>>       Sent: Thursday, January 24, 2002 9:00 PM
>>       To: [log in to unmask]
>>       Subject: [TN] Lead replacement solder alloys
>
>>       Who is the procurement source for a couple of the newer Sn 63
>>       like solders that have somewhat better properties than Sn63.
>>        Specifically they are the SnAgCuSb and SnAgCuZn alloys.
>
>>       Thanks
>>       Phil Hinton

--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446

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Date:         Sun, 27 Jan 2002 08:47:50 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      ENVIRONMENT AND TERMITES

As I'm very happy many folks are joining and offering to the EnvironNet, I
would like to offer the following though I'm, thankfully to all, not joining in:

Termites were, before the rain forests were destroyed, by far the largest
methane gas producers on this planet. Maybe they are still.

MoonMan

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Date:         Sun, 27 Jan 2002 18:53:29 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: ENVIRONMENT AND TERMITES
X-To:         Earl Moon <[log in to unmask]>
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Earl

The largest single methane gas producer in the animal kingdom is almost
certainly the elephant :-) The most important methane emitter, in recent
years, in the animal kingdom is man, but mostly from fossil sources
(even taking into account baked beans).

Termites do produce methane, but a very small part of the total. Of
course, the two major sources of methane are swampland and rice paddies,
counting for over 50% of the total (I have the figures in a book which I
can't seem to lay my hands on, just now).

However, this intervention should most certainly have gone on EnviroNet.

Best regards,

Brian
Earl Moon wrote:
>
> As I'm very happy many folks are joining and offering to the EnvironNet, I
> would like to offer the following though I'm, thankfully to all, not joining in:
>
> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
> MoonMan
>
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Date:         Sun, 27 Jan 2002 12:23:16 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ENVIRONMENT AND TERMITES
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Hi Earl,

While I have no argument about termites being here for some time, they have
also been kept in check by the balance of nature. I am certain that you
realize that termites and methane are not the only subjects discussed at
EnviroNet. (The forum was not established just for termites and methane
anyway, termites would likely have little interest in the discussions and
methane can't read ;-)

The discussions were, however, meant for humans who, as a species, seem to be
prone to believe either that we can fully master and control nature or that
we are not having any effect or that because we are a product of nature that
what ever we do is, de facto, natural including the ultimate consequences
whatever they may be.

Your wit, intelligence and experience are a delight to this forum and while
they would be welcome in the EnviroNet forum, you are, of course, welcome to
opt out and exclude yourself from the discussions and information on the
EnviroNet. There are no compulsory forums.

The discussions are, however, wide ranging and most interesting and all
welcome to join in and advance their understanding and education on the
environment and share their thoughts, experiences and findings.

If we had done something like this earlier such contentious issues as
lead-free and halogen-free (which have been asserted to be environmentally
friendly without proof) would perhaps not be weighing down the industry at
this time.

Kind regards,
Joe

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Earl,
<BR>
<BR>While I have no argument about termites being here for some time, they have also been kept in check by the balance of nature. I am certain that you realize that termites and methane are not the only subjects discussed at EnviroNet. (The forum was not established just for termites and methane anyway, termites would likely have little interest in the discussions and methane can't read ;-)
<BR>
<BR>The discussions were, however, meant for humans who, as a species, seem to be prone to believe either that we can fully master and control nature or that we are not having any effect or that because we are a product of nature that what ever we do is, de facto, natural including the ultimate consequences whatever they may be. &nbsp;&nbsp;
<BR>
<BR>Your wit, intelligence and experience are a delight to this forum and while they would be welcome in the EnviroNet forum, you are, of course, welcome to opt out and exclude yourself from the discussions and information on the EnviroNet. There are no compulsory forums.
<BR>
<BR>The discussions are, however, wide ranging and most interesting and all welcome to join in and advance their understanding and education on the environment and share their thoughts, experiences and findings.
<BR>
<BR>If we had done something like this earlier such contentious issues as lead-free and halogen-free (which have been asserted to be environmentally friendly without proof) would perhaps not be weighing down the industry at this time.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>

--part1_3c.18458459.29859184_boundary--

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Date:         Sun, 27 Jan 2002 14:55:00 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ENVIRONMENT AND TERMITES
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In a message dated 1/27/02 9:26:48 AM Pacific Standard Time,
[log in to unmask] writes:

> because we are a product of nature that
>  what ever we do is, de facto, natural including the ultimate consequences
>  whatever they may be.

The above, of course, is undeniably true...but like cobra venom, and other
wonderful "natural" things, like Anthrax, Black Death, Typhus, and AIDS,
everything natural is not wonderful...at least to the specie it decimates....

Rudy Sedlak

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Date:         Sun, 27 Jan 2002 15:41:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: ENVIRONMENT AND TERMITES
X-To:         [log in to unmask]

Joe,

Love to join you all but am incompetent only at one thing at a time. While
very interested in human survival, I believe we will opt for money down to
the last man/woman left on earth. There is nothing the human condition will
change but itself dependent on green and that ain't nothing but money.

MoonMan

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Date:         Sun, 27 Jan 2002 18:39:32 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ENVIRONMENT AND TERMITES
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Hi Rudy and Earl,

Rudy, I cannot but agree with the notion that not all in nature is wonderful
to see but it is at least natural. However, when a species sets about
decimating itself it seems to me that such action is unnatural...Or could it
be that our species is unconsciously looking to the lemmings for inspiration.
;-)

Earl, I appreciate your comments. You have live long enough and seen enough
to be cynical. I have put in my years also and have my cynical side as well
but I still feel compelled to continue the struggle no matter the odds or how
low the apparent interest of others. I was taught in the Army and learned in
Viet Nam that the struggle was not for ourselves but more immediately for one
another and ultimately (hopefully) for a distant future, a future in which we
will play no part, except that we are now setting the stage for those who
follow.

"Life is a series of collisions with the future; it is not the sum of what we
have been, but what we yearn to be." -Jose Ortega y Gasset

I just don't have it in me to turn my back and walk away.

This philosophical discussion like many others would be best held over a
pitcher of beer... ;-)

Very best!
Joe


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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Rudy and Earl,
<BR>
<BR>Rudy, I cannot but agree with the notion that not all in nature is wonderful to see but it is at least natural. However, when a species sets about decimating itself it seems to me that such action is unnatural...Or could it be that our species is unconsciously looking to the lemmings for inspiration. ;-)
<BR>
<BR>Earl, I appreciate your comments. You have live long enough and seen enough to be cynical. I have put in my years also and have my cynical side as well but I still feel compelled to continue the struggle no matter the odds or how low the apparent interest of others. I was taught in the Army and learned in Viet Nam that the struggle was not for ourselves but more immediately for one another and ultimately (hopefully) for a distant future, a future in which we will play no part, except that we are now setting the stage for those who follow.
<BR>
<BR>"Life is a series of collisions with the future; it is not the sum of what we have been, but what we yearn to be." -Jose Ortega y Gasset </FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>I just don't have it in me to turn my back and walk away.
<BR>
<BR>This philosophical discussion like many others would be best held over a pitcher of beer... ;-)
<BR>
<BR>Very best!
<BR>Joe
<BR></FONT></HTML>

--part1_69.21222f6f.2985e9b4_boundary--

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Date:         Sun, 27 Jan 2002 23:06:45 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Source for SnAgCuZn solder
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Hi

Since I did not get any answers to my earlier inquiry after all of the smart
guys have returned from Apex.

Does any one have a supplier source for a solder, Sn96.3/Ag2.5/Cu0.7/Zn 0.5

Thanks

Phil Hinton

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi
<BR>
<BR>Since I did not get any answers to my earlier inquiry after all of the smart guys have returned from Apex.
<BR>
<BR>Does any one have a supplier source for a solder, Sn96.3/Ag2.5/Cu0.7/Zn 0.5
<BR>
<BR>Thanks &nbsp;
<BR>
<BR>Phil Hinton &nbsp;&nbsp;&nbsp;</FONT></HTML>

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Date:         Sun, 27 Jan 2002 23:20:00 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From:         [log in to unmask]
Subject:      Correction
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After rereading e-mail that I sent last Thursday,  I see why I got no
answers, since I typed in a enquiry on Sn63 solder when I met a Sn96 with Ag,
Cu, and Zn.

Phil Hinton

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>After rereading e-mail that I sent last Thursday, &nbsp;I see why I got no answers, since I typed in a enquiry on Sn63 solder when I met a Sn96 with Ag, Cu, and Zn.
<BR>
<BR>Phil Hinton &nbsp;&nbsp;</FONT></HTML>

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Date:         Sun, 27 Jan 2002 23:39:40 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From:         [log in to unmask]
Subject:      Re: ENVIRONMENT AND TERMITES
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In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time,
[log in to unmask] writes:


> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
>

Did I miss the news that the rain forests were gone? Funny, I read last year
that the founder of the Sierra Club did a fly over and proclaimed that they
were at least 90% in tact.....?? Guess I better start paying more attention.

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<HTML><FONT FACE=arial,helvetica><FONT  COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time, [log in to unmask] writes:
<BR>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Termites were, before the rain forests were destroyed, by far the largest
<BR>methane gas producers on this planet. Maybe they are still.
<BR>
<BR></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">
<BR>Did I miss the news that the rain forests were gone? Funny, I read last year that the founder of the Sierra Club did a fly over and proclaimed that they were at least 90% in tact.....?? Guess I better start paying more attention.</FONT></HTML>

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Date:         Mon, 28 Jan 2002 13:42:41 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Creative Engineering and Manufacturing Methods..
X-To:         [log in to unmask]
MIME-Version: 1.0
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Ouch! All them pressures and leverages and stresses and .... what the hell
kind of chassis does that assemblage fit? Who's the thermal engineer on
this one? - 'coz I don't think much of his thermal pads between chips and
G-clamp. Intel have got the jump on this fellow with their P4 solution,
though it's about as chunky.

What can one say, seriously? Hope it doesn't crop up in anything I buy.

Peter




                    SteveZeva@AOL
                    .COM                 To:     [log in to unmask]
                    Sent by:             cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    TechNet              Aero/ST Group)
                    <[log in to unmask]        Subject:     [TN] Creative Engineering and
                    ORG>                 Manufacturing Methods..


                    01/26/02
                    03:08 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    SteveZeva






Hi all!

Earl sent me a photo showing a fine example of Creative Engineering and
Manufacturing methods, and invites any comments   B^}

-Steve Gregory-



[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date:         Mon, 28 Jan 2002 15:36:58 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From:         [log in to unmask]
Subject:      Basic Board Cleaner
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I am looking for a basic board cleaner and ask for your recommendations -
makes and models. I have in mind the old dish washer style of thing with a
resin bed attached for treating incoming water, but you may have more up to
date ideas than I.

We use a CM for assembling boards, so all the flux removal and heavier duty
cleaning is done by them. What I need is a cheap water wash machine that
can dump to drain after filtering out any harmful chemicals and residues
from rework/repair soldering, handling contamination and stripping of
humiseal coating. If you consider closed-loop systems to be better, I'm
open to suggestions, but low cost is the driving factor I have to live
with.

I have searched the net, but so far have only found fairly high-tech (ergo
expesive) machinery that goes beyond my needs.

Any and all help, as ever, is much appreciated.

Peter

[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date:         Mon, 28 Jan 2002 08:21:45 +0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
Subject:      new photos from my party!

------------------  Virus Warning Message (on the network)

Found virus WORM_MYPARTY.A in file www.myparty.yahoo.com
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---------------------------------------------------------

Hello!

My party... It was absolutely amazing!
I have attached my web page with new photos!
If you can please make color prints of my photos. Thanks!



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Date:         Mon, 28 Jan 2002 08:23:00 +0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tran Tien Phat (PCBA-ME)" <[log in to unmask]>
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Subject:      new photos from my party!

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Hello!

My party... It was absolutely amazing!
I have attached my web page with new photos!
If you can please make color prints of my photos. Thanks!



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Date:         Mon, 28 Jan 2002 11:06:23 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Source for SnAgCuZn solder
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Phil

I have a source for SnZn9 and Sn ZnBi ( don't know the composition right =
now) where we get the stuff for research:

Showa Denko
489 fifth Avenue 18th floor
New York, NY 10017
Phone: 1-212-370-0033
Fax: 1-212-370-4566

or in Japan:

13-9 Shiba Daimon 1-Chome
Minato- ku
Tokyo 105-8518

Solder is pretty cheap. However shipping from Japan costs an arm and a =
leg.

Have a great day

Guenter

.

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Mon, 28 Jan 2002 15:41:27 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Anil Kher <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Anil Kher <[log in to unmask]>
Subject:      Black color thin laminates
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mipl1mighty grateful if u can send me offline contacts for manufacturers =
of black color base copper clad laminate - G-10 - thin laminates of =
0.4mm and lesser.
Thanks
Anil Kher

micro interconnexion pvt. ltd.
D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India - =
403110
Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
E-mail :- [log in to unmask]
LEADERS IN GOLD PLATED PCBS

------=_NextPart_000_0059_01C1A812.3F982DA0
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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>mipl1</TITLE><Bass=20
href=3D"file://C:\Program Files\Common Files\Microsoft =
Shared\Stationery\">
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR>
<META content=3D"C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot" =
name=3DTemplate>
<STYLE></STYLE>
</HEAD>
<BODY vLink=3D#800080 link=3D#0000ff bgColor=3D#c0c0c0>
<DIV>mighty grateful if u can send me offline contacts for manufacturers =
of=20
black color base copper clad laminate - G-10 - thin laminates of 0.4mm =
and=20
lesser.</DIV>
<DIV>Thanks</DIV>
<DIV>Anil Kher</DIV><B>
<ADDRESS><FONT size=3D2>&nbsp;</ADDRESS></FONT>
<ADDRESS>micro interconnexion pvt. ltd.</ADDRESS>
<ADDRESS>D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , =
India &#8211;=20
403110</ADDRESS>
<ADDRESS>Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 /=20
285271.</ADDRESS>
<ADDRESS>E-mail :- [log in to unmask]</ADDRESS></B><FONT =
color=3D#ffff00>
<ADDRESS>LEADERS IN GOLD PLATED PCBS</ADDRESS></FONT></BODY></HTML>

------=_NextPart_000_0059_01C1A812.3F982DA0--

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Date:         Mon, 28 Jan 2002 12:36:43 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Basic Board Cleaner
X-To:         [log in to unmask]
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Peter

I do not advise "dishwasher" type models for high-tech cleaning, as
their efficiency is not good, they are heavy consumers of water and
electricity per m2 of cleaned assemblies and they are bad at drying
because you have to dry the residual water in the machine as well as on
the assemblies. I know -- I made such machines from 1975 to 1978 and
stopped their manufacture exactly because of these reasons. They were
later replaced by much more efficient batch models, in every respect,
but there was a gap of several years when my company, of that time, did
not offer cleaners, while we sussed these problems out. Of course, the
later machines were more expensive in capital expenditure, but the lower
operating costs compensated in a reasonable amortisation period.

For small equipment, closed circuit operation is rarely worth-while. The
problem is that the wide range of contaminants require many treatments.
A typical sequence may be fine mechanical filtration, single stage
reverse osmosis, two stages of active carbon to remove residual
organics, resp. large and small molecule sizes, either double bed +
mixed bed or two large mixed bed DI column and UV treatment to kill
accumulated micro-organisms that proliferate in the DI columns. In the
smallest system, the cost of this (capital and operating) is more than
that of the machine!

It may interest you to know that I recently visited two factories in
China with three "dishwasher" type machines, between them for defluxing.
These were operating in closed circuit with just carbon and mixed-bed DI
columns. They were not satisfied with the results, the operating costs
were horrendous, they had to buy a separate drying oven and they paid an
arm and a leg for the equipment (I think, if I remember correctly, it
was about $80,000 each). They also had problems at a technical level in
that, in all three cases, the manufacturer had not fool-proofed the
system and the machines became unserviceable within the first few hours.
It took several months before the manufacturer (European) had sorted the
problem out.

If you want more info, please contact me off-line and I'll give you the
name of a Chinese company who may be able to help you, and some others.

Brian



[log in to unmask] wrote:
>
> I am looking for a basic board cleaner and ask for your recommendations -
> makes and models. I have in mind the old dish washer style of thing with a
> resin bed attached for treating incoming water, but you may have more up to
> date ideas than I.
>
> We use a CM for assembling boards, so all the flux removal and heavier duty
> cleaning is done by them. What I need is a cheap water wash machine that
> can dump to drain after filtering out any harmful chemicals and residues
> from rework/repair soldering, handling contamination and stripping of
> humiseal coating. If you consider closed-loop systems to be better, I'm
> open to suggestions, but low cost is the driving factor I have to live
> with.
>
> I have searched the net, but so far have only found fairly high-tech (ergo
> expesive) machinery that goes beyond my needs.
>
> Any and all help, as ever, is much appreciated.
>
> Peter
>
> [This e-mail is confidential and may also be privileged. If you are not the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
>
> ---------------------------------------------------------------------------------
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> the BODY (NOT the subject field): SIGNOFF Technet
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------

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=========================================================================
Date:         Mon, 28 Jan 2002 11:44:11 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Christison <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject:      Re: Black color thin laminates
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

I'd be interested too....................

[log in to unmask] wrote:

> mighty grateful if u can send me offline contacts for manufacturers of
> black color base copper clad laminate - G-10 - thin laminates of 0.4mm
> and lesser.ThanksAnil Kher
>
> micro interconnexion pvt. ltd.
> D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India –
> 403110
> Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
> E-mail :- [log in to unmask]
> LEADERS IN GOLD PLATED PCBS
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF

Tel: (0)131 336 6165
Fax: (0)131 336 6001

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Date:         Mon, 28 Jan 2002 09:06:39 +0000
Reply-To:     Roger Bilham <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Roger Bilham <[log in to unmask]>
Subject:      Re: Source for SnAgCuZn solder
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain;charset=iso-8859-1

Phil

I believe that Soldertec http://www.lead-free.org keeps a directory of
lead free products, which may help you.

Patents covering the composition you give have been applied for by
Matsushita, Sony and Siegfried Pfyffer (and probably others by now), who
may be able to supply information.

Have fun.
Roger Bilham

In article <[log in to unmask]>, [log in to unmask] writes
>    Hi
>
>    Since I did not get any answers to my earlier inquiry after all of
>    the smart guys have returned from Apex.
>
>    Does any one have a supplier source for a solder,
>    Sn96.3/Ag2.5/Cu0.7/Zn 0.5
>
>    Thanks
>
>    Phil Hinton

--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446

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Date:         Mon, 28 Jan 2002 07:17:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Heller and MPM

Folks,

Could all you Heller fans give me a note about reflow and their ovens. I'm
particularly interested in the 1700WN model and how robust it might be for
fairly high thermal mass boards using Kester's 562R solder paste. Kester's
profile looks straight forward enough but one of our suppliers seems to be
having trouble hitting it consistently. By the way, who owns Heller now?

Also, about 7 years ago, I bought a few MPM 2000 printers. They were great
for what we did then. Can someone tell me how they might perform on extra
fine pitch devices as QFP's and .8mm CSP's today?

Thanks,

Earl Moon

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=========================================================================
Date:         Mon, 28 Jan 2002 08:23:58 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Safavi-Bayat Shahed <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Safavi-Bayat Shahed <[log in to unmask]>
Subject:      Re: How to convert a .dwg to .pdf
MIME-Version: 1.0
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You should first install "ghostscript" utility and then in AutoCAD make post
script
files from *.dwg files and with ghostcript convert *.plt or *.ps file to
pdf.

Shahed

----- Original Message -----
From: My  <mailto:[log in to unmask]> Nguyen
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, January 25, 2002 10:05 PM
Subject: [TN] How to convert a .dwg to .pdf

Hello all,

Not all my company have Autocad 2000, thus, they
wanted me to convert my drawings into pdf format.
Unfortunately, I don't know how.

Is there any way for it?  Please advise!

You all have a great weekend!

M.N

__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com <http://auctions.yahoo.com>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">


<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN =
class=3D542182613-28012002>You=20
should first install "ghostscript" utility and then in AutoCAD make =
post=20
script</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN =
class=3D542182613-28012002>files=20
from *.dwg files and&nbsp;with ghostcript convert *.plt or *.ps file to =

pdf.</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN=20
class=3D542182613-28012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" color=3D#0000ff><SPAN=20
class=3D542182613-28012002>Shahed</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <BLOCKQUOTE=20
  style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
    <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
    <DIV=20
    style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
    <A [log in to unmask] =
href=3D"mailto:[log in to unmask]">My=20
    Nguyen</A> </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 25, =
2002 10:05=20
    PM</DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] How to convert =
a .dwg to=20
    .pdf</DIV>
    <DIV><BR></DIV>Hello all,<BR><BR>Not all my company have Autocad =
2000, thus,=20
    they<BR>wanted me to convert my drawings into pdf =
format.<BR>Unfortunately,=20
    I don't know how.<BR><BR>Is there any way for it?&nbsp; Please=20
    advise!<BR><BR>You all have a great=20
    =
weekend!<BR><BR>M.N<BR><BR>_____________________________________________=
_____<BR>Do=20
    You Yahoo!?<BR>Great stuff seeking new owners in Yahoo! =
Auctions!<BR><A=20
    =
href=3D"http://auctions.yahoo.com">http://auctions.yahoo.com</A><BR><BR>=
------------------------------------------------------------------------=
---------<BR>Technet=20
    Mail List provided as a free service by IPC using LISTSERV =
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    Digest<BR>Search previous postings at: <A=20
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    =
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum=
.htm</A>)=20
    for additional<BR>information, or contact Keach Sasamori at <A=20
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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Date:         Mon, 28 Jan 2002 07:52:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: Lunch at Apex (NTC)
X-To:         [log in to unmask]
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Steve,
You're in Tulsa, right? Come on down to Austin and you and I will drive to =
San Antonio. There's a Dick's Last Resort right on the Riverwalk. (Yes, it =
is a "cuh-razy" place. I'll show you first hand.


Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508  Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]

>>> [log in to unmask] 01/25/02 07:42PM >>>
Hi Ed!

From the phone-call that we had, sounds like Dick's Last Resort is one fun
place!

Maybe next year it'll be my turn...scratch that, I'll go no matter what. =
I'll
take PTO (Personal Time Off) and pay for things myself if the trip isn't
funded. San Diego ain't a bad place to take a vacation anyway...

One thing from your post that interests me, and it always had me wondering
(hoping that Kathy has her TechNet ears on), is that I served with a =
Aviation
Ordnanceman with the last name Palumbo...I think his first name was =
Michael,
but not really sure...been a while ago...maybe a relative of theirs.

One thing about being in the military, you remember military people that =
you
served with by their last names...the people that you got close with, you
learned their first names.

Just curious if there's any connection. The Palumbo guy and me served in
Patrol Squadron-50 and did a deployment to "Dodge" (Deigo Garcia) back in
1985...

-Steve Gregory-


> Hi all,
>
> Just wanted to drop a line to let everyone know that the Apex lunch =
thing
> did happen. We met at the IPC booth, and coincidentally, Mr. Bev =
Christian,
> Ph.D. was browsing the bookstand. Also in attendance was Graham Collins,
> Kathy and Joe Palumbo with their sales folks, Arlene and Evie (not
> technetters), Don Roy and Scott Kramer and myself. We "invaded" Dick's =
Last
> Resort and everyone agreed that it was "a hoot!" The rudest, most
> irreverent service this side of the Mississippi. It was a pleasure to =
meet
> these folks in person, and I urge that next year, we do the same. Maybe =
a
> few more of the infamous technet participants will show up (nudge, =
nudge,
> Steve and Earl!)
>
> Have a great weekend!
>
> Regards,
>
> Ed Popielarski
> QTA Machine
> 10 Mc Laren, Ste D
> Irvine, Ca. 92618
>
> Phone:949-581-6601
> Fax: 949-581-2448
> Cel: 949-337-2578
>
> <A HREF=3D"http://www.qta.net/">www.QTA.NET</A>
>

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Date:         Mon, 28 Jan 2002 08:17:34 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: Heller and MPM
X-To:         [log in to unmask]
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MoonMan,
How the heck are ya?=20
Thought I'd answer what I could on your question. First off, I absolutely =
love Heller ovens had a 1700, Nitrogen-inerted, with high-temp heaters =
(for high-lead, no-lead, 80%gold, 20% tin, etc., etc. stuff). Loved the =
consistency. As far as MPM 2000's. loved them as well. Here's a little =
info that may help you. Printers are printers, and options only enhance =
your printing experience. MPM has shown through the years that their =
products are rugged, dependable, well-thought-out, etc. Try this, K&J =
Marketing sells a kapton stencil. It is marketed as "Kepoch". The kapton =
"melts" as it's laser-cut, leaving an ultra-smooth aperture wall. Release =
problems are sayonara. This works  especially well on extra-fine pitch =
parts and epoxy screening. As far as CSP, I can only imagine the further =
benefits. THey cost roughly the same as SS stencils and their turnaround =
time is unparalelled. Here is their info:

KJ Marketing Services
115 Thirtieth Street
Toronto, Ontario=20
M8W 3C1=20
Canada=20
Phone (416) 252 1061=20
fax (416) 253 1687=20

Hope this helps (somewhat).


Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508  Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]

>>> [log in to unmask] 01/28/02 07:17AM >>>
Folks,

Could all you Heller fans give me a note about reflow and their ovens. I'm
particularly interested in the 1700WN model and how robust it might be for
fairly high thermal mass boards using Kester's 562R solder paste. Kester's
profile looks straight forward enough but one of our suppliers seems to be
having trouble hitting it consistently. By the way, who owns Heller now?

Also, about 7 years ago, I bought a few MPM 2000 printers. They were great
for what we did then. Can someone tell me how they might perform on extra
fine pitch devices as QFP's and .8mm CSP's today?

Thanks,

Earl Moon

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Date:         Mon, 28 Jan 2002 08:14:31 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: (OT) Earl Moon Endowment Fund...
Mime-Version: 1.0
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Would I be purchasing the Kmart bag and the clamp? =20

Kathy=20

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<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Would I be purchasing the Kmart bag and the clamp?&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

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Date:         Mon, 28 Jan 2002 09:08:50 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: (OT) Earl Moon Endowment Fund...
X-To:         [log in to unmask]

For you my dear, anything you want - but it ain't no Kmart bag. It's from
Joe's deli and termite emporium.

Haven't been contacted by your sales people yet.

Enjoy,

Earl

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Date:         Mon, 28 Jan 2002 09:12:51 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Heller and MPM
X-To:         [log in to unmask]

Jason,

Thanks for the input. I was just a bit concerned about the possibility of
"amatures" not being able to run our fairly high thermal mass boards in an
oven with only 6 zones. I also am a bit concerned with print characteristics
if the printer hasn't been upgraded over the years.

What the heck are you doing in the software side of things? Hell man, you
belong on the floor where all the action is.

Enjoy,

Earl

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Date:         Mon, 28 Jan 2002 10:57:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain

Help!  Emergency!

We have a completed assembly (top assembly with many boards, hybrids, etc.)
ready for shipment to our customer (space product).  The last operation was
to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The assembly was
put in an oven at 150 C for two hours.  After hours of reviewing all of the
materials and bill of material, component by component (component data,
supplier phone calls, etc.), the only item that is not rated for 150 C is
the polyurethane conformal coating, which turned yellow/brown in color.  Can
anyone explain what actually happened to the coating and if it can be used
as is?

Thanks,

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879

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Date:         Mon, 28 Jan 2002 11:01:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Heller and MPM
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Earl,

I used the Heller four zone oven (thinks its a five) to float .190 inch thick
16 layer (double sided SM) with an active .060 thick CIC slab in the center.
The oven worked great.  By the way I used the RF SuperMole on each run and
used a fairly large sheet steel fixture... talk about thermal profiling!
This was all compliant to the MIL-STD-2000 spec and a tough QA group.  Later
a larger volume went through the Conceptronic oven without incident.
[Success was a function of dummy parts and teaming process controls... hence
its not all the oven.]  Major reason for the fixture: boards got very heavy
after a few of them...

Coretec's Boston Brad

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Date:         Mon, 28 Jan 2002 10:13:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Heller and MPM
X-To:         [log in to unmask]

Thanks BB,

I sure agree with you on the concurrent thing and the profiling. One of our
suppliers has had a few problems, as evidenced by the "C" clamp fiasco. Just
want to remove all the varialbes as possible bad boards, paste, printer, and
oven/profile.

MoonMan

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Date:         Mon, 28 Jan 2002 10:22:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Skinny Stencil

Though I kinda like the look of the solder joints, I do believe they may be
a little light on the solder paste volume having been printed using a 5 mil
thick stencil. The thickness is fine for .8 mm stuff and xfine pitch QFP's.
However, I have used step down foils, from 6.5 mils to 5 mils, to ensure
specified paste volume for all parts to accomodate the 1206 types as well.

Also, as previously discussed, I reduce BGA pad sizes 20% from device ball
sizes. For my current design, with a 5 mil thick stencil, I'm printing one
to one with the pad size.

Can I hear an Ahmen from all you SMT brethren out there or am I in purgatory
about to face eternal damnation?

MoonMan

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Date:         Mon, 28 Jan 2002 12:17:31 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Enviromental Stress Testing-----Benefits and Drawbacks
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_23.18472e70.2986e1ab_boundary"

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Content-Type: text/plain; charset="US-ASCII"
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To All Technetters,

Being from purchasing, I have been asked to rationalize the inherent cost for
demanding quality standards that my company now prescribes to.

Below, I have outlined our company's test criteria for environmental stress
testing:

Panel Allocation                             Test Description
Thermal Cycle -55C / 150C    X1            15 Min x 2 x 100; Test PC boards
without components
Humidity 85/85                   X2            7 Days; Test complete units

150C Bake                          X3              7 Days
Hot Plate/ Oil Temp Shock    X4            10 Sec x 20  0C-100C Water Dip

Via Current                            X5              7 Days / 14 cycles @
25C & 125C

Below, I have outlined several questions so that I can attain a richer
understanding of the intent, benefit and drawbacks of environmental stress
testing:

a.  How would moisture absorption effect results of environmental stress
testing?
b.  How would soldermask adhesion be effected by environmental stress testing?
c.  How is oxidation formed; is it a function of water
absorption/environmental exposure?
d.  What could cause via current test (the via are burnt and opened) after
environmental stress testing?
e.  If our product is not exposed to any harsh environmental conditions, what
is the benefit for this type of testing?

I would appreciate any and all comments and feedback all of you have to offer.

Regards,


--part1_23.18472e70.2986e1ab_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>To All Technetters,
<BR>
<BR>Being from purchasing, I have been asked to rationalize the inherent cost for demanding quality standards that my company now prescribes to. &nbsp;
<BR>
<BR>Below, I have outlined our company's test criteria for environmental stress testing: &nbsp;
<BR>
<BR>Panel Allocation                 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Test Description
<BR>Thermal Cycle -55C / 150C    X1      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;15 Min x 2 x 100; Test PC boards without components
<BR>Humidity 85/85       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;X2      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7 Days; Test complete units
<BR>150C Bake        &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;X3        &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7 Days
<BR>Hot Plate/ Oil Temp Shock    X4      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;10 Sec x 20 &nbsp;0C-100C Water Dip
<BR>Via Current          &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;X5        &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7 Days / 14 cycles @ 25C &amp; 125C
<BR>
<BR>Below, I have outlined several questions so that I can attain a richer understanding of the intent, benefit and drawbacks of environmental stress testing:
<BR>
<BR>a. &nbsp;How would moisture absorption effect results of environmental stress testing?
<BR>b. &nbsp;How would soldermask adhesion be effected by environmental stress testing?
<BR>c. &nbsp;How is oxidation formed; is it a function of water absorption/environmental exposure? &nbsp;
<BR>d. &nbsp;What could cause via current test (the via are burnt and opened) after environmental stress testing?
<BR>e. &nbsp;If our product is not exposed to any harsh environmental conditions, what is the benefit for this type of testing?
<BR>
<BR>I would appreciate any and all comments and feedback all of you have to offer.
<BR>
<BR>Regards,
<BR></FONT></HTML>

--part1_23.18472e70.2986e1ab_boundary--

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Date:         Mon, 28 Jan 2002 13:58:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
MIME-Version: 1.0
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So we're not the only one having trouble with the C vs. F on ovens .... what
does the coating manufacturer say, they can probably make the strongest
argument for use-as-is or rework.

Mike

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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#ffffff"><FONT  style="BACKGROUND-COLOR: #ffffff" SIZE=2>So we're not the only one having trouble with the C vs. F on ovens .... what does the coating manufacturer say, they can probably make the strongest argument for use-as-is or rework.<BR>
<BR>
Mike</FONT></HTML>

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Date:         Mon, 28 Jan 2002 14:27:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      ODB++
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

From: Paul M Fly

My employer is in the process of buying a couple seats of Valor. Naturally
the
question should we give our vendors ODB++ rather than Gerber came up. I
would
be very interested in hearing about some of your experiences in this
matter. In
particular I would like to hear from some fabricators. How many PCB fab
shops
really prefer ODB++? I did a quick look at our preferred vendors web site
and did not
find a word one way or the other.

Thanks,
************************************
          Paul Fly

Eastman Kodak Company
Engineering Technology Center - PEDT
2nd Fl.  Bld. 205  K.P.
2400 Mt. Read Blvd.
Rochester, New York 14650-3007
Phone: (716) 726-5670
Fax: (716) 726-0275
E-mail: [log in to unmask]
************************************

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Date:         Mon, 28 Jan 2002 14:31:45 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Enviromental Stress Testing-----Benefits and Drawbacks
MIME-Version: 1.0
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Hi "Regards,"
First, we normally put names at the bottom of our messages.
You, in a message dated 01/28/2002 13:22:10, [log in to unmask] write:
>Being from purchasing, I have been asked to rationalize the inherent cost for
>demanding quality standards that my company now prescribes to.
>Below, I have outlined our company's test criteria for environmental stress
testing:
A: You do not tell us what the purpose of your "environmental stress testing"
is supposed to be; nor are you telling us on what units [proptotypes,
coupons, scrp samples, etc.] these tests are to be performed or any test
details; nor are you giving us any design details--consequently, it is very
difficult to say anything pertinent about your tests and your product. You
also do not tell us what the cryptic X1 through X5 means--number of cycles,
sequence?

>Panel Allocation                             Test Description
>Thermal Cycle -55C / 150C    X1            15 Min x 2 x 100; Test PC boards
without components
>Humidity 85/85                     X2            7 Days; Test complete units
>150C Bake                            X3              7 Days
>Hot Plate/ Oil Temp Shock     X4            10 Sec x 20  0C-100C Water Dip
>Via Current                           X5              7 Days / 14 cycles @
25C & 125C
>
>Below, I have outlined several questions so that I can attain a richer
>understanding of the intent, benefit and drawbacks of environmental stress
testing:
>a.  How would moisture absorption effect results of environmental stress
testing?
A: Which test?
>b.  How would soldermask adhesion be effected by environmental stress
testing?
>c.  How is oxidation formed; is it a function of water
absorption/environmental exposure?
>d.  What could cause via current test (the via are burnt and opened) after
environmental stress testing?
A: not enough details.
>e.  If our product is not exposed to any harsh environmental conditions, what
>is the benefit for this type of testing?
A: None.
Generally speaking, your tests are extreme--without stated details and
purposes general statements are meaningless.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Mon, 28 Jan 2002 13:35:37 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: ODB++
X-To:         [log in to unmask]

Paul,

As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.

By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.


Earl

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=========================================================================
Date:         Mon, 28 Jan 2002 16:11:32 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Earl Moon <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

HEY EARL I WOULD LIKE TO SEE THAT BEING A NEW USER OF VALOR

*GOD BLESS AMERICA*



William W. DeCray III
Waytec Electronics Corp
CAD/CAM & Engineering Services Manager
PHONE:(434) 237-6391 ext 115
CELL:   (804) 851-6115
FAX:    (434) 237-1324
E-mail:<[log in to unmask]>
Web http://www.waytec.com <http://www.waytec.com/>
FTP  ftp://ftp.waytec.com <ftp://ftp.waytec.com/>



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Monday, January 28, 2002 2:36 PM
To: [log in to unmask]
Subject: Re: [TN] ODB++


Paul,

As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.

By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.


Earl

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Date:         Mon, 28 Jan 2002 15:28:17 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: ODB++
X-To:         [log in to unmask]

Bill and all,

I don't think this free offer will be in the proportions of the DFM/CE
checklist thing. If it is, we have a problem. I told a few folks I would try
shipping the stuff out via my work T1 line. However, the four files total
about 60 mb. If it doesn't work, you will have to send a self addressed,
stamped envelop and a blank CD so I can burn and return the files to you. I
don't know if Daan wants to put up with this again.

Earl

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Date:         Mon, 28 Jan 2002 23:11:44 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "D.Terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0010_01C1A851.271094E0"

This is a multi-part message in MIME format.

------=_NextPart_000_0010_01C1A851.271094E0
Content-Type: text/plain;
        charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable

I have another question about changing from Gerber to filetypes like =
ODB++ (or many other formats). How do you folks out there think about =
sending such data, which may include almost complete design information, =
to the outside world ? I mean with Gerber your stencil vendor or bare =
board vendor may learn some things about mechanical characteristics of =
your designs (so what ?), but isn't it a risk with formats like ODB++ =
that someone steals a major part of your design and your companies =
knowhow ?

Daan Terstegge
http://www.smtinfo.net =20
  ----- Original Message -----=20
  From: Earl Moon=20
  To: [log in to unmask]
  Sent: Monday, January 28, 2002 8:35 PM
  Subject: Re: [TN] ODB++


  Paul,

  As a thoroughly experienced and long time Valor user, first I can say =
it's a
  great package though a bit tough to learn. Concerning ODB++, most all =
my fab
  suppliers use the convention. CAM350 and most CAM packages also output =
ODB
  as "smart" data instead of "dumb" Gerber.

  By the way, I have a set of procedures that cut through the exhaustive =
Valor
  documentation. When you're ready, I'll send them to you. Mostly they =
are
  actual photos of nearly every screen used in the Valor program.


  Earl

  =
-------------------------------------------------------------------------=
--------
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1.8d
  To unsubscribe, send a message to [log in to unmask] with following text =
in
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[log in to unmask]: SET Technet NOMAIL
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1252">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>I have another question about changing from Gerber =
to&nbsp;filetypes like=20
ODB++ (or many&nbsp;other&nbsp;formats). How do you folks out there =
think about=20
sending&nbsp;such data, which may include almost complete design =
information, to=20
the outside world ? I mean with Gerber your stencil vendor or bare board =

vendor&nbsp;may learn some things about&nbsp;mechanical characteristics =
of your=20
designs (so what ?),&nbsp;but isn't it&nbsp;a risk with&nbsp;formats =
like=20
ODB++&nbsp;that someone&nbsp;steals a major part of your=20
design&nbsp;and&nbsp;your companies&nbsp;knowhow ?</DIV>
<DIV>&nbsp;</DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A>&nbsp;&nbsp;</D=
IV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, January 28, 2002 =
8:35=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
  <DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long time =
Valor=20
  user, first I can say it's a<BR>great package though a bit tough to =
learn.=20
  Concerning ODB++, most all my fab<BR>suppliers use the convention. =
CAM350 and=20
  most CAM packages also output ODB<BR>as "smart" data instead of "dumb" =

  Gerber.<BR><BR>By the way, I have a set of procedures that cut through =
the=20
  exhaustive Valor<BR>documentation. When you're ready, I'll send them =
to you.=20
  Mostly they are<BR>actual photos of nearly every screen used in the =
Valor=20
  =
program.<BR><BR><BR>Earl<BR><BR>-----------------------------------------=
----------------------------------------<BR>Technet=20
  Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
  unsubscribe, send a message to <A=20
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  Digest<BR>Search previous postings at: <A=20
  href=3D"http://www.ipc.org">www.ipc.org</A> &gt; On-Line Resources =
&amp;=20
  Databases &gt; E-mail Archives<BR>Please visit IPC web site (<A=20
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href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
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Date:         Mon, 28 Jan 2002 14:09:28 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Steele <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Steele <[log in to unmask]>
Subject:      Re: ODB++
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Paul,


I work for Toppan Electronics in San Diego, we are a
fab house.

We strongly prefer ODB data. I tell our Sales people
to beg for it!

For the past 2 years we have tracked type of data
(274D, 274X and ODB) and problems with that data such
as bad aperture lists, missing layers, incorrect
filename identification, etc, etc, etc.

For example, for the last 226 jobs we have input we had
41 issues with gerber, 0 for ODB. That's a lot of phone
calls and time spent just getting the data INTO our Genesis
system. We allocate 5 min to get the data and import an
ODB job, 30-40 for gerber (sometimes it takes hours for
gerber, that happens about once a month...)

I realize not everyone uses Genesis as their CAM system, but
I would wager that a majority of the bigger fab houses do.

So, yes, PLEASE generate ODB as a first choice and only send
out gerber if asked too...

Of course that's just my opinion, I could be wrong...



Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]




>-----Original Message-----
>From: [log in to unmask] [mailto:[log in to unmask]]
>Sent: Monday, January 28, 2002 11:28 AM
>To: [log in to unmask]
>Subject: [TN] ODB++
>
>
>From: Paul M Fly
>
>My employer is in the process of buying a couple seats of
>Valor. Naturally
>the
>question should we give our vendors ODB++ rather than Gerber came up. I
>would
>be very interested in hearing about some of your experiences in this
>matter. In
>particular I would like to hear from some fabricators. How many PCB fab
>shops
>really prefer ODB++? I did a quick look at our preferred
>vendors web site
>and did not
>find a word one way or the other.
>
>Thanks,
>************************************
>          Paul Fly
>
>Eastman Kodak Company
>Engineering Technology Center - PEDT
>2nd Fl.  Bld. 205  K.P.
>2400 Mt. Read Blvd.
>Rochester, New York 14650-3007
>Phone: (716) 726-5670
>Fax: (716) 726-0275
>E-mail: [log in to unmask]
>************************************

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=========================================================================
Date:         Mon, 28 Jan 2002 17:16:23 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kirk Kosel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kirk Kosel <[log in to unmask]>
Subject:      Solder pot analysis
Mime-Version: 1.0
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This is a MIME message. If you are reading this text, you may want to
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--=_1E437AC4.0E6F0299
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Hi everyone.

Any chance that someone knows the analytical method used to test the =
solder in a HASL for impurities?  If possible, I would like to do it =
in-house to save time and money.  We have an ICP, which you'd think could =
check for copper and other impurities.  Perhaps IPC has a standard =
procedure to go by?  If so, tell me where to find it.

Thanks in advance for your help.

Kirk

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>
<META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1>Hi everyone.</FONT></DIV>
<DIV><FONT size=3D1></FONT>&nbsp;</DIV>
<DIV><FONT size=3D1>Any chance that someone knows the analytical method =
used to=20
test the solder in a HASL for impurities?&nbsp; If possible, I would like =
to do=20
it in-house to save time and money.&nbsp; We have an ICP, which you'd =
think=20
could check for copper and other impurities.&nbsp; Perhaps IPC has a =
standard=20
procedure to go by?&nbsp; If so, tell me where to find it.</FONT></DIV>
<DIV><FONT size=3D1></FONT>&nbsp;</DIV>
<DIV><FONT size=3D1>Thanks in advance for your help.</FONT></DIV>
<DIV><FONT size=3D1></FONT>&nbsp;</DIV>
<DIV><FONT size=3D1>Kirk</FONT></DIV></BODY></HTML>

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Date:         Mon, 28 Jan 2002 17:48:50 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         "Marsico, James" <[log in to unmask]>
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Jim,

You have chemically altered the polymer. It will no longer perform it's designed function.

David A. Douthit
Manager
LoCan LLC

"Marsico, James" wrote:

> Help!  Emergency!
>
> We have a completed assembly (top assembly with many boards, hybrids, etc.)
> ready for shipment to our customer (space product).  The last operation was
> to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The assembly was
> put in an oven at 150 C for two hours.  After hours of reviewing all of the
> materials and bill of material, component by component (component data,
> supplier phone calls, etc.), the only item that is not rated for 150 C is
> the polyurethane conformal coating, which turned yellow/brown in color.  Can
> anyone explain what actually happened to the coating and if it can be used
> as is?
>
> Thanks,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> ---------------------------------------------------------------------------------
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Date:         Mon, 28 Jan 2002 18:06:13 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: Enviromental Stress Testing-----Benefits and Drawbacks
X-To:         [log in to unmask]
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Werner,

This looks like something someone "made up" without any reasoning to it.

David A. Douthit
Manager
LoCan LLC

[log in to unmask] wrote:

> Hi "Regards,"
> First, we normally put names at the bottom of our messages.
> You, in a message dated 01/28/2002 13:22:10, [log in to unmask] write:
> >Being from purchasing, I have been asked to rationalize the inherent cost for
> >demanding quality standards that my company now prescribes to.
> >Below, I have outlined our company's test criteria for environmental stress
> testing:
> A: You do not tell us what the purpose of your "environmental stress testing"
> is supposed to be; nor are you telling us on what units [proptotypes,
> coupons, scrp samples, etc.] these tests are to be performed or any test
> details; nor are you giving us any design details--consequently, it is very
> difficult to say anything pertinent about your tests and your product. You
> also do not tell us what the cryptic X1 through X5 means--number of cycles,
> sequence?
>
> >Panel Allocation                             Test Description
> >Thermal Cycle -55C / 150C    X1            15 Min x 2 x 100; Test PC boards
> without components
> >Humidity 85/85                     X2            7 Days; Test complete units
> >150C Bake                            X3              7 Days
> >Hot Plate/ Oil Temp Shock     X4            10 Sec x 20  0C-100C Water Dip
> >Via Current                           X5              7 Days / 14 cycles @
> 25C & 125C
> >
> >Below, I have outlined several questions so that I can attain a richer
> >understanding of the intent, benefit and drawbacks of environmental stress
> testing:
> >a.  How would moisture absorption effect results of environmental stress
> testing?
> A: Which test?
> >b.  How would soldermask adhesion be effected by environmental stress
> testing?
> >c.  How is oxidation formed; is it a function of water
> absorption/environmental exposure?
> >d.  What could cause via current test (the via are burnt and opened) after
> environmental stress testing?
> A: not enough details.
> >e.  If our product is not exposed to any harsh environmental conditions, what
> >is the benefit for this type of testing?
> A: None.
> Generally speaking, your tests are extreme--without stated details and
> purposes general statements are meaningless.
>
> Werner Engelmaier
> Engelmaier Associates, L.C.
> Electronic Packaging, Interconnection and Reliability Consulting
> 7 Jasmine Run
> Ormond Beach, FL  32174  USA
> Phone: 904-437-8747, Fax: 904-437-8737
> E-mail: [log in to unmask], Website: www.engelmaier.com
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------

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=========================================================================
Date:         Mon, 28 Jan 2002 20:27:54 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Mark Steele <[log in to unmask]>
In-Reply-To:  <B136A0C653FCD311ABA400508B60DAB19C4BA6@EXCHANGE>
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Hi Mark,

From the design engineer's perspective, supporting two different formats
does create a problem.  When you release a design to production, it is not
supposed to be specific to one particular vendor (unless you have a captive
fab shop and NEVER go outside).  Unfortunately, not all fab shops support
ODB++.  If purchasing would be willing to limit themselves to fab shops that
supported ODB++, that would be fine, but since that limits their options it
is unlikely.  So in order to be universal, we would have to generate both
ODB++ and Gerber.  This is easy to do but can create subtle problems that
could take lots of time and money to run down.  The problem is how do you
insure that both sets of output data are identical in every way?  While some
programs allow you to import both data sets and compare, as a practical
matter, assuring that they are identical is not possible.  Since there will
undoubtedly be subtle differences between the two, which one controls?
Don't we also have to verify and validate both versions by building up both
assemblies?  And when problems inevitably arise between boards from two
different vendors using different data files, who 'ya gonna call?  Those
dumb design engineers who created the problem, of course.

I don't doubt for an instant that ODB++ saves fabricators time and money.
Do we as customers get a significant discount for making the fabricators job
easier with this superior data format?  I've asked several fabricators and
no one has agreed yet.  This is the part I don't get.  Since it will
increase the cost of design to support dual formats for every job, we'd be
irresponsible to do this without concomitant savings.  If you really want to
make any of the competing Gerber replacements widely accepted, get a
significant number of fabricators to offer a discount for designs submitted
in that format.  Things will take care of themselves very quickly after
that.  Purchasing agents will be after designers to provide the new format,
designers will be after EDA vendors to generate the new format and
fabricators who don't support it will be forced to do so rapidly.  But
please, just pick one.  We don't need to experience the VHS vs. Beta
scenario again.

I would strongly recommend a format that is under the control of an industry
standards-making body rather than a single vendor to discourage
Microsoft-style abuse of competitors, but that is a separate issue.  It's
clear that Gerber should be replaced with something smarter that saves us
ALL money, which would be a real win-win situation.  But until it saves
money for the fabricators' customers, we'll all be stuck with Gerber and we
all lose.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mark Steele
> Sent: Monday, January 28, 2002 4:09 PM
> To: [log in to unmask]
> Subject: Re: [TN] ODB++
>
>
> Hi Paul,
>
>
> I work for Toppan Electronics in San Diego, we are a
> fab house.
>
> We strongly prefer ODB data. I tell our Sales people
> to beg for it!
>
> For the past 2 years we have tracked type of data
> (274D, 274X and ODB) and problems with that data such
> as bad aperture lists, missing layers, incorrect
> filename identification, etc, etc, etc.
>
> For example, for the last 226 jobs we have input we had
> 41 issues with gerber, 0 for ODB. That's a lot of phone
> calls and time spent just getting the data INTO our Genesis
> system. We allocate 5 min to get the data and import an
> ODB job, 30-40 for gerber (sometimes it takes hours for
> gerber, that happens about once a month...)
>
> I realize not everyone uses Genesis as their CAM system, but
> I would wager that a majority of the bigger fab houses do.
>
> So, yes, PLEASE generate ODB as a first choice and only send
> out gerber if asked too...
>
> Of course that's just my opinion, I could be wrong...
>
>
>
> Mark Steele
> CAM Automation Engineer
> Toppan Electronics, Inc.
> 858.695.2222
> [log in to unmask]
>
>
>
>
> >-----Original Message-----
> >From: [log in to unmask] [mailto:[log in to unmask]]
> >Sent: Monday, January 28, 2002 11:28 AM
> >To: [log in to unmask]
> >Subject: [TN] ODB++
> >
> >
> >From: Paul M Fly
> >
> >My employer is in the process of buying a couple seats of
> >Valor. Naturally
> >the
> >question should we give our vendors ODB++ rather than Gerber came up. I
> >would
> >be very interested in hearing about some of your experiences in this
> >matter. In
> >particular I would like to hear from some fabricators. How many PCB fab
> >shops
> >really prefer ODB++? I did a quick look at our preferred
> >vendors web site
> >and did not
> >find a word one way or the other.
> >
> >Thanks,
> >************************************
> >          Paul Fly
> >
> >Eastman Kodak Company
> >Engineering Technology Center - PEDT
> >2nd Fl.  Bld. 205  K.P.
> >2400 Mt. Read Blvd.
> >Rochester, New York 14650-3007
> >Phone: (716) 726-5670
> >Fax: (716) 726-0275
> >E-mail: [log in to unmask]
> >************************************
>
> ------------------------------------------------------------------
> ---------------
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> additional
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>

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Date:         Tue, 29 Jan 2002 10:07:18 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Julian Coates <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Julian Coates <[log in to unmask]>
Subject:      Re: ODB++
X-To:         "D.Terstegge" <[log in to unmask]>
In-Reply-To:  <001301c1a848$c64f9320$b9ce86c2@gompie>
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Hi Daan,

Depending on the software tool which produces the ODB++ data, the user can
select whether to take certain information out of the file before sending
the data to another company. For example, in general it is possible to
remove the netlist data, component layers etc., if required. To put it
another way, ODB++ can be used to define as much or as little of the product
as you want. Having said that, a bare-board vendor would not thank you for
removing the netlist!

Hope this helps,

Julian Coates
Valor
  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of D.Terstegge
  Sent: 28 January 2002 22:12
  To: [log in to unmask]
  Subject: Re: [TN] ODB++


  I have another question about changing from Gerber to filetypes like ODB++
(or many other formats). How do you folks out there think about sending such
data, which may include almost complete design information, to the outside
world ? I mean with Gerber your stencil vendor or bare board vendor may
learn some things about mechanical characteristics of your designs (so what
?), but isn't it a risk with formats like ODB++ that someone steals a major
part of your design and your companies knowhow ?

  Daan Terstegge
  http://www.smtinfo.net
    ----- Original Message -----
    From: Earl Moon
    To: [log in to unmask]
    Sent: Monday, January 28, 2002 8:35 PM
    Subject: Re: [TN] ODB++


    Paul,

    As a thoroughly experienced and long time Valor user, first I can say
it's a
    great package though a bit tough to learn. Concerning ODB++, most all my
fab
    suppliers use the convention. CAM350 and most CAM packages also output
ODB
    as "smart" data instead of "dumb" Gerber.

    By the way, I have a set of procedures that cut through the exhaustive
Valor
    documentation. When you're ready, I'll send them to you. Mostly they are
    actual photos of nearly every screen used in the Valor program.


    Earl

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<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dwindows-1252">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Hi=20
Daan,</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =

size=3D2>Depending on the software tool which produces the ODB++ data, =
the user=20
can select whether to take certain information out of the file before =
sending=20
the data to another company. For example, in general it is possible to =
remove=20
the netlist data, component layers etc., if required. To put it another =
way,=20
ODB++ can be used to define as much or as little of the product as you =
want.=20
Having said that, a bare-board vendor would not thank you for removing =
the=20
netlist!</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Hope=20
this helps,</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Julian=20
Coates</FONT></SPAN></DIV>
<DIV><SPAN class=3D370550110-29012002><FONT face=3DArial color=3D#0000ff =

size=3D2>Valor</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of =
</B>D.Terstegge<BR><B>Sent:</B> 28=20
  January 2002 22:12<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> =
Re: [TN]=20
  ODB++<BR><BR></FONT></DIV>
  <DIV>I have another question about changing from Gerber =
to&nbsp;filetypes like=20
  ODB++ (or many&nbsp;other&nbsp;formats). How do you folks out there =
think=20
  about sending&nbsp;such data, which may include almost complete design =

  information, to the outside world ? I mean with Gerber your stencil =
vendor or=20
  bare board vendor&nbsp;may learn some things about&nbsp;mechanical=20
  characteristics of your designs (so what ?),&nbsp;but isn't it&nbsp;a =
risk=20
  with&nbsp;formats like ODB++&nbsp;that someone&nbsp;steals a major =
part of=20
  your design&nbsp;and&nbsp;your companies&nbsp;knowhow ?</DIV>
  <DIV>&nbsp;</DIV>
  <DIV>Daan Terstegge</DIV>
  <DIV><A=20
  =
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A>&nbsp;&nbsp;</D=
IV>
  <BLOCKQUOTE=20
  style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
    <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
    <DIV=20
    style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
    <A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
    </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, January 28, =
2002 8:35=20
    PM</DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
    <DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long =
time Valor=20
    user, first I can say it's a<BR>great package though a bit tough to =
learn.=20
    Concerning ODB++, most all my fab<BR>suppliers use the convention. =
CAM350=20
    and most CAM packages also output ODB<BR>as "smart" data instead of =
"dumb"=20
    Gerber.<BR><BR>By the way, I have a set of procedures that cut =
through the=20
    exhaustive Valor<BR>documentation. When you're ready, I'll send them =
to you.=20
    Mostly they are<BR>actual photos of nearly every screen used in the =
Valor=20
    =
program.<BR><BR><BR>Earl<BR><BR>-----------------------------------------=
----------------------------------------<BR>Technet=20
    Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
    unsubscribe, send a message to <A=20
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    halt delivery of Technet send e-mail to <A=20
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
    NOMAIL<BR>To receive ONE mailing per day of all the posts: send =
e-mail to <A=20
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
    Digest<BR>Search previous postings at: <A=20
    href=3D"http://www.ipc.org">www.ipc.org</A> &gt; On-Line Resources =
&amp;=20
    Databases &gt; E-mail Archives<BR>Please visit IPC web site (<A=20
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href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
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Date:         Tue, 29 Jan 2002 07:25:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: Conformal Coating
MIME-Version: 1.0
Content-Type: text/plain

Thanks for the response, Dave, but could you elaborate?  Will the
permeability be affected?  How about the Modulus?  Will the TCE change?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879


        -----Original Message-----
        From:   David Douthit [SMTP:[log in to unmask]]
        Sent:   Monday, January 28, 2002 7:49 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Conformal Coating

        Jim,

        You have chemically altered the polymer. It will no longer perform
it's designed function.

        David A. Douthit
        Manager
        LoCan LLC

        "Marsico, James" wrote:

        > Help!  Emergency!
        >
        > We have a completed assembly (top assembly with many boards,
hybrids, etc.)
        > ready for shipment to our customer (space product).  The last
operation was
        > to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The
assembly was
        > put in an oven at 150 C for two hours.  After hours of reviewing
all of the
        > materials and bill of material, component by component (component
data,
        > supplier phone calls, etc.), the only item that is not rated for
150 C is
        > the polyurethane conformal coating, which turned yellow/brown in
color.  Can
        > anyone explain what actually happened to the coating and if it can
be used
        > as is?
        >
        > Thanks,
        >
        > Jim Marsico
        > Senior Engineer
        > Production Engineering
        > EDO Electronics Systems Group
        > [log in to unmask] <mailto:[log in to unmask]>
        > 631-595-5879
        >
        >
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Date:         Tue, 29 Jan 2002 06:55:48 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      HOW TO GET THE ODB ++ FILES

All those contacting me about the how to Valor destructions I believe may
now download them from Seth's FTP site. I hope this is true and the reason
I'm posting here is my email has gone down in flames.

If you do get the files, Section one was, of course, the first written and
was a little rough at the edges. The subsequent three sections smoothed out
a bit. If you have any questions, email me.

If Julian is looking in out there, I would like to talk with you via email.
I have my laptop setup here and don't have your contact information with me.

Thanks all,

Earl

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Date:         Tue, 29 Jan 2002 08:57:14 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Legend Inks
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Good morning all,

I am dutifully trying to finish many action items from the recent IPC
meetings at Apex.  The solder mask task group, chaired by Roger Landolt,
Enthone, has been asked to address the issues of legend and marking inks
that go on solder masks.  At the Fall meeting (2001) in Orlando, there was
support for forming a small task group focused on Legend Inks, though no
one stepped forward to volunteer to lead the effort, unfortunately.

So, I ask this august group, are there individuals out there who would like
to participate in such an activity and more importantly, is there someone
out there who would LEAD such an activity.

If you have not had the opportunity to lead an IPC task group, I would tell
you from my own experience that it is very rewarding.  If you have travel
restrictions, as most of us do now, more and more work is being done
electronically with no travel.

If you have an interest or questions, please respond to either myself
([log in to unmask]), Roger Landolt ([log in to unmask]), or
Cassandra Cummings( [log in to unmask]).

Doug Pauls
Rockwell Collins
Vice Chair, Solder Mask Task Group

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Date:         Tue, 29 Jan 2002 15:22:40 -0000
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Fenner <[log in to unmask]>
Subject:      Re: Solder pot analysis
X-To:         Kirk Kosel <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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Usually Wet chemical or gravimetric for tin, spectrograph for impurities. or
spectrograph for everything.
However I would think you could set up a deal with your bar supplier which
would include a number of free analyses if you get  replenishment and
exchange  solder from them.

Kind Regards

Mike Fenner
Applications Engineer, European Operations
Indium Corporation
 T: + 44 1908 580 400
M: + 44 7810 526 317
 F: + 44 1908 580 411
 E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com

  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Kirk Kosel
  Sent: Monday, January 28, 2002 11:16 PM
  To: [log in to unmask]
  Subject: [TN] Solder pot analysis


  Hi everyone.

  Any chance that someone knows the analytical method used to test the
solder in a HASL for impurities?  If possible, I would like to do it
in-house to save time and money.  We have an ICP, which you'd think could
check for copper and other impurities.  Perhaps IPC has a standard procedure
to go by?  If so, tell me where to find it.

  Thanks in advance for your help.

  Kirk

------=_NextPart_000_0041_01C1A8D8.CAED82D0
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        charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">


<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><SPAN class=3D670201615-29012002><FONT face=3DArial color=3D#0000ff =

size=3D3>Usually Wet chemical or gravimetric for tin, spectrograph for =
impurities.=20
or spectrograph for everything.</FONT></SPAN></DIV>
<DIV><SPAN class=3D670201615-29012002><FONT face=3DArial color=3D#0000ff =

size=3D3>However&nbsp;I would think you could set up a deal with your =
bar supplier=20
which would include a number of free analyses&nbsp;if you&nbsp;get&nbsp; =

replenishment and exchange&nbsp; solder from them. </FONT></SPAN></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D3></FONT>&nbsp;</DIV>
<DIV><FONT size=3D3><FONT face=3DArial color=3D#0000ff>Kind Regards=20
</FONT></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D3></FONT>&nbsp;</DIV>
<DIV><FONT size=3D3><FONT size=3D1><FONT face=3DArial><FONT =
color=3D#0000ff><FONT=20
size=3D3>Mik<SPAN class=3D670201615-29012002>e=20
Fenner</SPAN></FONT></FONT></FONT></FONT> </FONT></DIV>
<P><FONT size=3D3><FONT face=3DArial color=3D#0000ff>Applications =
Engineer, European=20
Operations</FONT> <BR><B><FONT face=3DArial color=3D#0000ff>Indium=20
Corporation</FONT></B> <BR><FONT face=3DArial color=3D#0000ff>&nbsp;T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial color=3D#0000ff>M: + 44 7810 526 =
317</FONT>=20
<BR><FONT face=3DArial color=3D#0000ff>&nbsp;F: + 44 1908 580 411</FONT> =
<BR><FONT=20
face=3DArial color=3D#0000ff>&nbsp;E: [log in to unmask]</FONT> =
<BR><FONT face=3DArial=20
color=3D#0000ff>W:<U> www.indium.com</U>&nbsp; </FONT><BR><FONT =
face=3DArial=20
color=3D#0000ff>Leadfree:</FONT><U> <FONT face=3DArial=20
color=3D#0000ff>www.Pb-Free.com</FONT></U> </FONT></P>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D3>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of </B>Kirk Kosel<BR><B>Sent:</B> =
Monday,=20
  January 28, 2002 11:16 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B>=20
  [TN] Solder pot analysis<BR><BR></FONT></DIV>
  <DIV><FONT size=3D3>Hi everyone.</FONT></DIV>
  <DIV><FONT size=3D3></FONT>&nbsp;</DIV>
  <DIV><FONT size=3D3>Any chance that someone knows the analytical =
method used to=20
  test the solder in a HASL for impurities?&nbsp; If possible, I would =
like to=20
  do it in-house to save time and money.&nbsp; We have an ICP, which =
you'd think=20
  could check for copper and other impurities.&nbsp; Perhaps IPC has a =
standard=20
  procedure to go by?&nbsp; If so, tell me where to find =
it.</FONT></DIV>
  <DIV><FONT size=3D3></FONT>&nbsp;</DIV>
  <DIV><FONT size=3D3>Thanks in advance for your help.</FONT></DIV>
  <DIV><FONT size=3D3></FONT>&nbsp;</DIV>
  <DIV><FONT size=3D3>Kirk</FONT></DIV></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_0041_01C1A8D8.CAED82D0--

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Date:         Tue, 29 Jan 2002 09:33:40 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kirk Kosel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kirk Kosel <[log in to unmask]>
Subject:      Re: Solder pot analysis
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Thanks for the responses.  One more question, any idea on how to get the =
solder (and impurities) in solution for ICP analysis? =20

Thanks again for your help,

Kirk

--=_257842E7.51305E38
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
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<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1></FONT>Thanks for the responses.&nbsp; One more =
question, any=20
idea on how to get the solder (and impurities) in solution for ICP=20
analysis?&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Thanks again for your help,</DIV>
<DIV>&nbsp;</DIV>
<DIV>Kirk<FONT face=3D"MS Sans Serif" size=3D1></DIV></FONT></BODY></HTML>

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Date:         Tue, 29 Jan 2002 10:37:30 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Subject:      Re: Legend Inks
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Doug,
How are you?
We don't mark over solder masks.We mark first and then cover in some
cases,but in most cases we leave a keep-out area for marking.I am moving
toward having a standard defined keep-out area in the solder mask where a
label will be placed in lieu of the standard marking inks.I will help all I
can on this,if you think it will help.
Dewey

> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Tuesday, January 29, 2002 7:57 AM
> To:   [log in to unmask]
> Subject:      [TN] Legend Inks
>
> Good morning all,
>
> I am dutifully trying to finish many action items from the recent IPC
> meetings at Apex.  The solder mask task group, chaired by Roger Landolt,
> Enthone, has been asked to address the issues of legend and marking inks
> that go on solder masks.  At the Fall meeting (2001) in Orlando, there was
> support for forming a small task group focused on Legend Inks, though no
> one stepped forward to volunteer to lead the effort, unfortunately.
>
> So, I ask this august group, are there individuals out there who would
> like
> to participate in such an activity and more importantly, is there someone
> out there who would LEAD such an activity.
>
> If you have not had the opportunity to lead an IPC task group, I would
> tell
> you from my own experience that it is very rewarding.  If you have travel
> restrictions, as most of us do now, more and more work is being done
> electronically with no travel.
>
> If you have an interest or questions, please respond to either myself
> ([log in to unmask]), Roger Landolt ([log in to unmask]), or
> Cassandra Cummings( [log in to unmask]).
>
> Doug Pauls
> Rockwell Collins
> Vice Chair, Solder Mask Task Group
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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Date:         Tue, 29 Jan 2002 09:57:43 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Steele <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Steele <[log in to unmask]>
Subject:      Re: ODB++
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Hi Daan,

I agree with Julian. We as a fab house have no use for some of the data
that comes along with the ODB data. Sometimes this even creates problems.

We would prefer our customers to delete their component layers, forms,
checklists
and temp layers (but please leave in the netlist!). Although I and some CAM
operators
sometimes take a look at the forms that come in with some jobs (I've even
learned a
thing or two) we would prefer not to have them.

Now if there was an established collaboration and coordination between us,
we
COULD use the customers forms and checklists as part of a larger process.
This
seems to be on the horizon for us at Toppan.



Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]



-----Original Message-----
From: Julian Coates [mailto:[log in to unmask]]
Sent: Tuesday, January 29, 2002 2:07 AM
To: [log in to unmask]
Subject: Re: [TN] ODB++


Hi Daan,

Depending on the software tool which produces the ODB++ data, the user can
select whether to take certain information out of the file before sending
the data to another company. For example, in general it is possible to
remove the netlist data, component layers etc., if required. To put it
another way, ODB++ can be used to define as much or as little of the product
as you want. Having said that, a bare-board vendor would not thank you for
removing the netlist!

Hope this helps,

Julian Coates
Valor

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of D.Terstegge
Sent: 28 January 2002 22:12
To: [log in to unmask]
Subject: Re: [TN] ODB++


I have another question about changing from Gerber to filetypes like ODB++
(or many other formats). How do you folks out there think about sending such
data, which may include almost complete design information, to the outside
world ? I mean with Gerber your stencil vendor or bare board vendor may
learn some things about mechanical characteristics of your designs (so what
?), but isn't it a risk with formats like ODB++ that someone steals a major
part of your design and your companies knowhow ?

Daan Terstegge
http://www.smtinfo.net <http://www.smtinfo.net>

----- Original Message -----
From: Earl Moon <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, January 28, 2002 8:35 PM
Subject: Re: [TN] ODB++

Paul,

As a thoroughly experienced and long time Valor user, first I can say it's a
great package though a bit tough to learn. Concerning ODB++, most all my fab
suppliers use the convention. CAM350 and most CAM packages also output ODB
as "smart" data instead of "dumb" Gerber.

By the way, I have a set of procedures that cut through the exhaustive Valor
documentation. When you're ready, I'll send them to you. Mostly they are
actual photos of nearly every screen used in the Valor program.


Earl

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<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>Hi
Daan,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>I agree
with Julian. We as a fab house have no use for some of the data
</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>that comes
along with&nbsp;the ODB data. Sometimes this even creates
problems.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>We would
prefer our customers to delete their component layers, forms,
checklists</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>and temp
layers </SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>(but please leave in the netlist!). Although I and some
CAM operators</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>sometimes
</SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>take a look at the forms that come in with some jobs
(I've even learned a </SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>thing or
</SPAN></FONT><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>two) we would prefer not to have
them.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>Now if
there was an established collaboration and coordination between us,
we</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN
class=480525017-29012002>COULD&nbsp;use the customers forms and checklists as
part of a larger process. This</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Garamond><SPAN class=480525017-29012002>seems to
be on the horizon for us at Toppan.</SPAN></FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><BR>
<P><FONT face=Arial size=2>Mark Steele</FONT> <BR><FONT face=Arial size=2>CAM
Automation Engineer</FONT> <BR><B><I><FONT face="Times New Roman" size=2>Toppan
Electronics, Inc.</FONT></I></B> <BR><FONT face=Arial size=2>858.695.2222</FONT>
<BR><FONT face=Arial size=2>[log in to unmask]</FONT> </P></DIV>
<DIV>&nbsp;</DIV>
<BLOCKQUOTE dir=ltr
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Julian Coates
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, January 29, 2002 2:07
  AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
  ODB++<BR><BR></DIV></FONT>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial size=2>Hi
  Daan,</FONT></SPAN></DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2></FONT></SPAN>&nbsp;</DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2>Depending on the software tool which produces the ODB++ data, the user
  can select whether to take certain information out of the file before sending
  the data to another company. For example, in general it is possible to remove
  the netlist data, component layers etc., if required. To put it another way,
  ODB++ can be used to define as much or as little of the product as you want.
  Having said that, a bare-board vendor would not thank you for removing the
  netlist!</FONT></SPAN></DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2></FONT></SPAN>&nbsp;</DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial size=2>Hope
  this helps,</FONT></SPAN></DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2></FONT></SPAN>&nbsp;</DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2>Julian Coates</FONT></SPAN></DIV>
  <DIV><SPAN class=370550110-29012002><FONT color=#0000ff face=Arial
  size=2>Valor</FONT></SPAN></DIV>
  <BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
    <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
    size=2>-----Original Message-----<BR><B>From:</B> TechNet
    [mailto:[log in to unmask]]<B>On Behalf Of </B>D.Terstegge<BR><B>Sent:</B> 28
    January 2002 22:12<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
    ODB++<BR><BR></FONT></DIV>
    <DIV>I have another question about changing from Gerber to&nbsp;filetypes
    like ODB++ (or many&nbsp;other&nbsp;formats). How do you folks out there
    think about sending&nbsp;such data, which may include almost complete design
    information, to the outside world ? I mean with Gerber your stencil vendor
    or bare board vendor&nbsp;may learn some things about&nbsp;mechanical
    characteristics of your designs (so what ?),&nbsp;but isn't it&nbsp;a risk
    with&nbsp;formats like ODB++&nbsp;that someone&nbsp;steals a major part of
    your design&nbsp;and&nbsp;your companies&nbsp;knowhow ?</DIV>
    <DIV>&nbsp;</DIV>
    <DIV>Daan Terstegge</DIV>
    <DIV><A
    href="http://www.smtinfo.net">http://www.smtinfo.net</A>&nbsp;&nbsp;</DIV>
    <BLOCKQUOTE
    style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
      <DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
      <DIV
      style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
      <A href="mailto:[log in to unmask]" [log in to unmask]>Earl Moon</A>
      </DIV>
      <DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
      [log in to unmask]>[log in to unmask]</A> </DIV>
      <DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, January 28, 2002 8:35
      PM</DIV>
      <DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] ODB++</DIV>
      <DIV><BR></DIV>Paul,<BR><BR>As a thoroughly experienced and long time
      Valor user, first I can say it's a<BR>great package though a bit tough to
      learn. Concerning ODB++, most all my fab<BR>suppliers use the convention.
      CAM350 and most CAM packages also output ODB<BR>as "smart" data instead of
      "dumb" Gerber.<BR><BR>By the way, I have a set of procedures that cut
      through the exhaustive Valor<BR>documentation. When you're ready, I'll
      send them to you. Mostly they are<BR>actual photos of nearly every screen
      used in the Valor
      program.<BR><BR><BR>Earl<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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      Databases &gt; E-mail Archives<BR>Please visit IPC web site (<A
      href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</A>)
      for additional<BR>information, or contact Keach Sasamori at <A
      href="mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700
      ext.5315<BR>---------------------------------------------------------------------------------</BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>

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Date:         Tue, 29 Jan 2002 12:15:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ted Stern <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ted Stern <[log in to unmask]>
Subject:      Re: Solder pot analysis
X-To:         Kirk Kosel <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Kirk:

It has been some time since performing this test, but if memory serves
tin is measured chemically by ASTM E46; impurities (including copper,
gold, cadmium, zinc, aluminum, antimony, iron, arsenic, bismuth, silver,
and nickel), are measured spectrometrically (AA) by ASTM E663; and lead
is reported as the  "balance".

I am unsure of the ASTM designation for ICP determination, but the
general digestion method described in E663 may be the same for ICP.  If
silver is being determined, keep in mind aqua regia (HCl/HNO(3)) cannot
be employed as to dissolve the sample.

As previously mentioned, your current solder supplier should perform
this test for you AND provide you a copy of the method employed.

Regards,
Ted Stern

Kirk Kosel wrote:

>  Thanks for the responses.  One more question, any idea on how to get
> the solder (and impurities) in solution for ICP analysis? Thanks again
> for your help, Kirk

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Date:         Tue, 29 Jan 2002 13:10:41 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      ODB FILES ON SETH'S FTP SITE

For all you folks wanting my Valor destructions, my new best friend Seth
Goodman has set up a site and I think I was able to copy the files there.
Also included is a small presentation used to justify, to management, the
investment in the product.

The following is how to get the files:


log into ftp.GoodmanAssociates.com

Tell your users to log into the same site anonymously.  They will see a
directory called "Earl's files" that contain all your stuff.  They can then
download to their heart's content.

Let me know if you get the files successfully,

Earl

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Date:         Tue, 29 Jan 2002 16:10:48 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Test Coupons
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi To All
I am stumped - where are the words that say "if a coupon from a panel fails
to meet the specification requirements - all associated boards from that
panel are rejected"?

I know it, but I sure can't find it.

Thanks
Susan Mansilla

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Date:         Tue, 29 Jan 2002 15:00:27 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Doug Pogatetz <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Doug Pogatetz <[log in to unmask]>
Subject:      Minimum bend radius calculation in a flex circuit

I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.

I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?

Thanks.

Doug

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=========================================================================
Date:         Tue, 29 Jan 2002 14:37:58 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Whittaker, Dewey (AZ75)" <[log in to unmask]>
Subject:      Re: Minimum bend radius calculation in a flex circuit
X-To:         Doug Pogatetz <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

A starting rule is 12 times the thickness.
Dewey

> -----Original Message-----
> From: Doug Pogatetz [SMTP:[log in to unmask]]
> Sent: Tuesday, January 29, 2002 2:00 PM
> To:   [log in to unmask]
> Subject:      [TN] Minimum bend radius calculation in a flex circuit
>
> I am on project that requires that I determine the minimum bend radius of
> a
> flex circuit. I have not been able to find out any formulas or
> calculations
> to help out.
>
> I am a mechanical design engineer, so I am not up on all the terminology.
> It will of the class "Flex to Install", and will be of the adhesiveless
> type. Can anyone help out?
>
> Thanks.
>
> Doug
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> the BODY (NOT the subject field): SIGNOFF Technet
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> [log in to unmask]: SET Technet Digest
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------

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=========================================================================
Date:         Tue, 29 Jan 2002 15:59:01 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Test Coupons
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_3D605B25.4928454C"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_3D605B25.4928454C
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

Check out IPC-RB-276 section 4.6.2.2  Acceptance

Kathy=20

--=_3D605B25.4928454C
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Check out IPC-RB-276 section 4.6.2.2&nbsp; Acceptance</DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

--=_3D605B25.4928454C--

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Date:         Tue, 29 Jan 2002 18:01:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Minimum bend radius calculation in a flex circuit
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_35.2140995d.298883c7_boundary"

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Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hello Doug,

The answer depends on the construction and the materials used. 1 metal
layer?, 2? ... or more?  Also the thickness of the structure and of the
copper must be accounted for. The smaller the bend radius the greater the
strain and the higher the elongation requirement of the copper. If you need a
very small bend radius, very thin, ductile copper and thin polymer films are
best.

Long standing rules of thumb for 35 micron copper and 25 micron base films
and coverlayers have been:

3-6 times the thickness for single metal layer with coverlayer

6-10 X for 2 metal layers with coverlayers

15 to 20 or more times the thickness for bonded multilayers (Again this is
highly construction dependent.)

Use of a forming mandrel is a good idea if you are getting close ot the limits

Finite element modeling is useful to get a sense of the limits. Simple 2D
models will likely serve.

Keep in mind that shock and vibration can make your static design into a
dynamic one.

Kind regards,
Joe

--part1_35.2140995d.298883c7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hello Doug,
<BR>
<BR>The answer depends on the construction and the materials used. 1 metal layer?, 2? ... or more? &nbsp;Also the thickness of the structure and of the copper must be accounted for. The smaller the bend radius the greater the strain and the higher the elongation requirement of the copper. If you need a very small bend radius, very thin, ductile copper and thin polymer films are best.
<BR>
<BR>Long standing rules of thumb for 35 micron copper and 25 micron base films and coverlayers have been:
<BR>
<BR>3-6 times the thickness for single metal layer with coverlayer
<BR>
<BR>6-10 X for 2 metal layers with coverlayers
<BR>
<BR>15 to 20 or more times the thickness for bonded multilayers (Again this is highly construction dependent.)
<BR>
<BR>Use of a forming mandrel is a good idea if you are getting close ot the limits
<BR>
<BR>Finite element modeling is useful to get a sense of the limits. Simple 2D models will likely serve.
<BR>
<BR>Keep in mind that shock and vibration can make your static design into a dynamic one.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>

--part1_35.2140995d.298883c7_boundary--

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Date:         Tue, 29 Jan 2002 17:11:24 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
              x-mac-creator="4D4F5353"
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Jim,

Unless you are willing to spend a lot of money to test all these factors all you can say is yes to your
questions.
There is no definitive answer as to "how much" the coating has been "affected".

You have more than likely greatly exceeded the Tg of the coating. At that point all bets are off!
Trying to "certify" these boards without extensive testing would be risky at best.

David A. Douthit
manager
LoCan LLC

"Marsico, James" wrote:

> Thanks for the response, Dave, but could you elaborate?  Will the
> permeability be affected?  How about the Modulus?  Will the TCE change?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>         -----Original Message-----
>         From:   David Douthit [SMTP:[log in to unmask]]
>         Sent:   Monday, January 28, 2002 7:49 PM
>         To:     [log in to unmask]
>         Subject:        Re: [TN] Conformal Coating
>
>         Jim,
>
>         You have chemically altered the polymer. It will no longer perform
> it's designed function.
>
>         David A. Douthit
>         Manager
>         LoCan LLC
>
>         "Marsico, James" wrote:
>
>         > Help!  Emergency!
>         >
>         > We have a completed assembly (top assembly with many boards,
> hybrids, etc.)
>         > ready for shipment to our customer (space product).  The last
> operation was
>         > to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The
> assembly was
>         > put in an oven at 150 C for two hours.  After hours of reviewing
> all of the
>         > materials and bill of material, component by component (component
> data,
>         > supplier phone calls, etc.), the only item that is not rated for
> 150 C is
>         > the polyurethane conformal coating, which turned yellow/brown in
> color.  Can
>         > anyone explain what actually happened to the coating and if it can
> be used
>         > as is?
>         >
>         > Thanks,
>         >
>         > Jim Marsico
>         > Senior Engineer
>         > Production Engineering
>         > EDO Electronics Systems Group
>         > [log in to unmask] <mailto:[log in to unmask]>
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Date:         Wed, 30 Jan 2002 08:37:00 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Enviromental Stress Testing-----Benefits and Drawbacks
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

I am taking it that the testing you detailed is a one-off qualification
test and not normal Environmental Stress Screening (ESS), which is done for
each production run?

Environmental Qualification Test (EQT) is designed to prove through
accelerated aging, that your product will function reliably throughout its
intended lifespan in its normal operating environment. ESS is a mini
version of this to weed out any early life failures in conjunction with a
burn-in programme, but should not significantly shorten the life of the
survivors.

To comment on your questions:

a) Moisture absorbtion/transpiration is a natural part of boards and board
assemblies. To try to eliminate it in, or for, environmental testing will
provide a false result, unless that elimination is required in order to
match the intended operating environment of the finished product.
b) If you (or your fab house) has chosen the correct soldermask & hardener
for your application, mask adhesion must be unaffected by the the testing
or your product will have failed the test.
c) Oxidation is formed in the presense of oxygen (air) and moisture. The
degree of oxidation depends on exposure to these factors and also
temperature. Better chemists than I can explain this better, or you can
trawl the TechNet archives for more info. There was a sizeable thread on
oxidation (a.k.a. rust, tarnish, etc).
d) Did the burning to your vias occur during bare board testing or to the
finished assembly? Was the board under power at the time? If the board was
under power during temperature cycling, and it wasn't conformally coated,
then you've probably had a short circuit at the 'dew point', when any
moisture in the chamber air surrounding the boards has condensed onto the
board surface and given you a conductive path you didn't intend. Was the
via a power via?
e) If your product is not to be exposed to any harsh environment (extremes
of temperature, dust abrasion, salty air, vibration, shock, chemicals,
high/low pressures, and so on), then the degree of testing being carried
out is excessive. I wouldn't say unnecessary, because some form of EQT
and/or ESS is useful for product reliability. I'll re-state what I said at
the beginning of this response - the tests must be designed to prove that
your product will function reliably throughout its intended lifespan in its
normal operating environment.

Hope this helps a bit.

Peter Duncan




                    CircuitekAsia
                    @AOL.COM             To:     [log in to unmask]
                    Sent by:             cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    TechNet              Aero/ST Group)
                    <[log in to unmask]        Subject:     [TN] Enviromental Stress
                    ORG>                 Testing-----Benefits and Drawbacks


                    01/29/02
                    01:17 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    CircuitekAsia






To All Technetters,

Being from purchasing, I have been asked to rationalize the inherent cost
for demanding quality standards that my company now prescribes to.

Below, I have outlined our company's test criteria for environmental stress
testing:

Panel Allocation             Test Description
Thermal Cycle -55C / 150C X1       15 Min x 2 x 100; Test PC boards without
components
Humidity 85/85             X2       7 Days; Test complete units
150C Bake                   X3       7 Days
Hot Plate/ Oil Temp Shock X4       10 Sec x 20  0C-100C Water Dip
Via Current                   X5       7 Days / 14 cycles @ 25C & 125C

Below, I have outlined several questions so that I can attain a richer
understanding of the intent, benefit and drawbacks of environmental stress
testing:

a.  How would moisture absorption effect results of environmental stress
testing?
b.  How would soldermask adhesion be effected by environmental stress
testing?
c.  How is oxidation formed; is it a function of water
absorption/environmental exposure?
d.  What could cause via current test (the via are burnt and opened) after
environmental stress testing?
e.  If our product is not exposed to any harsh environmental conditions,
what is the benefit for this type of testing?

I would appreciate any and all comments and feedback all of you have to
offer.

Regards,



[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]

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Date:         Wed, 30 Jan 2002 02:09:54 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Adam Seychell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Adam Seychell <[log in to unmask]>
Subject:      pulse plating - without additives

Hello platers.  I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems  that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.

Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
 increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.

A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:

forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2

The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?

If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.

regards,

Adam Seychell.

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Date:         Wed, 30 Jan 2002 09:44:19 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Christison <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject:      Re: Minimum bend radius calculation in a flex circuit
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Doug,

You don't say whether the bend is a permanent, once only bend or a dynamic bend.

If it's a once only then that's dead easy for a mechanical engineer to calculate. Figure out where the
neutral axis is going to be (probably the outside of the coverlay on the inside of the bend) and from
there work out the strain on the copper. Then you have to figure out what the allowable strain is. For
rolled annealed (you'll have to ask the manufacturer) my unreliable memory tells me 10% is a
conservative figure.

If the flex is undergoing dynamic bending then the problem is one of fatigue. So in this case bend
radius (= stress) and number of cycles are both important. Generally it's regarded as a bad idea to
subject multilayer flexes to dynamic bending. For a single layer a rule of thumb is minimum bend radius
> 20 X thickness.

There are also a number of good design guides on the web whose addresses alas, I have also forgotten.
However you could start by looking for a flex manufacturer called Rogers I vaguely remember they had
some good stuff.

Hope this helps,



[log in to unmask] wrote:

> I am on project that requires that I determine the minimum bend radius of a
> flex circuit. I have not been able to find out any formulas or calculations
> to help out.
>
> I am a mechanical design engineer, so I am not up on all the terminology.
> It will of the class "Flex to Install", and will be of the adhesiveless
> type. Can anyone help out?
>
> Thanks.
>
> Doug
>
> ---------------------------------------------------------------------------------
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--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF

Tel: (0)131 336 6165
Fax: (0)131 336 6001

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Date:         Wed, 30 Jan 2002 07:47:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Robert Peterson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Robert Peterson <[log in to unmask]>
Subject:      Re: pulse plating - without additives
X-To:         Adam Seychell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html

Hope this helps

Bob Peterson
Alternate Final Finishes, Inc.

-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives


Hello platers.  I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems  that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.

Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
 increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.

A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:

forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2

The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?

If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.

regards,

Adam Seychell.

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Date:         Wed, 30 Jan 2002 08:36:35 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Steve Kelly <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Kelly <[log in to unmask]>
Subject:      Re: Minimum bend radius calculation in a flex circuit
X-To:         Doug Pogatetz <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

General rule is 10 to 12 times the thickness of the circuit. This rule holds
well for most circuits up to 4 layers. For simple flex to install you can
actually crease the circuit as long as it is not creased and uncreased in
the engineering phase.
Regards Steve Kelly

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Doug Pogatetz
Sent: Tuesday, January 29, 2002 4:00 PM
To: [log in to unmask]
Subject: [TN] Minimum bend radius calculation in a flex circuit


I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.

I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?

Thanks.

Doug

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Date:         Wed, 30 Jan 2002 08:28:25 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Afri Singh <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Afri Singh <[log in to unmask]>
Subject:      Re: Black color thin laminates
X-To:         Eric Christison <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Try Electroply in California

-----Original Message-----
From: Eric Christison [mailto:[log in to unmask]]
Sent: Monday, January 28, 2002 6:44 AM
To: [log in to unmask]
Subject: Re: [TN] Black color thin laminates


I'd be interested too....................

[log in to unmask] wrote:

> mighty grateful if u can send me offline contacts for manufacturers of
> black color base copper clad laminate - G-10 - thin laminates of 0.4mm
> and lesser.ThanksAnil Kher
>
> micro interconnexion pvt. ltd.
> D3-12 A , Corlim Industrial Estate , Corlim , Ilhas , Goa , India -
> 403110
> Tel : 00-91-832-284209 / 284337. Fax : 00-91-832-284209 / 285271.
> E-mail :- [log in to unmask]
> LEADERS IN GOLD PLATED PCBS
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF

Tel: (0)131 336 6165
Fax: (0)131 336 6001

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Date:         Wed, 30 Jan 2002 13:48:28 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Olivia Mc Dermott <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Olivia Mc Dermott <[log in to unmask]>
Subject:      Flux residue with a no-clean process
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Is it OK to have flux residue on assemblies when the process is no clean. We
have assemblies that are failing in the field and the customer thinks this
flux residue may be an issue. They think the assembly has been wet.
What do you think???? All help appreciated.

_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail.
http://www.hotmail.com

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Date:         Wed, 30 Jan 2002 08:50:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Joseph Spicuzza <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Spicuzza <[log in to unmask]>
Subject:      Re: Test Coupons
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="Windows-1252"
Content-Transfer-Encoding: 7bit

Susan,
MIL-PRF-55110, section 3.1 only verified compliant boards
also A4.6.1.3 and A4.6.2.3, is that what you were looking for?
Joe

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Tuesday, January 29, 2002 4:11 PM
To: [log in to unmask]
Subject: [TN] Test Coupons


Hi To All
I am stumped - where are the words that say "if a coupon from a panel fails
to meet the specification requirements - all associated boards from that
panel are rejected"?

I know it, but I sure can't find it.

Thanks
Susan Mansilla

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Date:         Wed, 30 Jan 2002 09:10:18 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              bbarr <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         bbarr <[log in to unmask]>
Subject:      TBGA
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Engineering here is looking at a TBGA600 for a project (tape ball grid
array). We have been working with PBGAs for years, but I am not familiar
with a TBGA. Is there anything unique about the TBGA as far as processing on
the assembly line as opposed to a PBGA? The package size is 40mm square and
1.55mm high, .75mm dia. balls on 1.27mm centers.

Thanks,

Bob

==========================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679

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Date:         Wed, 30 Jan 2002 08:19:46 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_08556105.23422F27"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_08556105.23422F27
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

IPC-610 has no-clean residues as acceptable.  Is it possible that flux may =
have been mixed with a washable?  Washing a no-clean off is more detrimenta=
l than leaving it alone. =20

Is the assembly conformally coated?  Is the application intended to be in =
a wet or high humidity/moisture enviroment?

Kathy=20

--=_08556105.23422F27
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>IPC-610 has no-clean residues as acceptable.&nbsp; Is it possible that flux
may have been mixed with a washable?&nbsp; Washing a no-clean off is more
detrimental than leaving it alone.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Is the assembly conformally coated?&nbsp; Is the application intended to be
in a wet or high humidity/moisture enviroment?</DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

--=_08556105.23422F27--

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Date:         Wed, 30 Jan 2002 15:15:30 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              =?ISO-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         =?ISO-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
Subject:      Re: pulse plating - without additives
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

Adam,

You may also be inspired by this article:

http://www.circuitree.com/CDA/ArticleInformation/features/BNP__Features__Ite
m/0,2133,24954,00.html

regards

Torben Oesteraa
Printca AS


-----Original Message-----
From: Robert Peterson [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 1:47 PM
To: [log in to unmask]
Subject: Re: [TN] pulse plating - without additives


Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html

Hope this helps

Bob Peterson
Alternate Final Finishes, Inc.

-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives


Hello platers.  I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems  that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.

Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
 increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.

A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:

forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2

The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?

If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.

regards,

Adam Seychell.

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=========================================================================
Date:         Wed, 30 Jan 2002 09:32:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McMullen, Kerry" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McMullen, Kerry" <[log in to unmask]>
Subject:      Re: TBGA
X-To:         bbarr <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Been placing and convection reflowing these (along with the PBGA's ) for
over 2 years with no change to my profiles.

-----Original Message-----
From: bbarr [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 9:10 AM
To: [log in to unmask]
Subject: [TN] TBGA


Engineering here is looking at a TBGA600 for a project (tape ball grid
array). We have been working with PBGAs for years, but I am not familiar
with a TBGA. Is there anything unique about the TBGA as far as processing on
the assembly line as opposed to a PBGA? The package size is 40mm square and
1.55mm high, .75mm dia. balls on 1.27mm centers.

Thanks,

Bob

==========================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679

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Date:         Wed, 30 Jan 2002 14:41:39 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Olivia Mc Dermott <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Olivia Mc Dermott <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Kathy,
The assembly is not conformally coated. It is a meter display in which we
build the PCB and then box build & system test. It is for distribution
around the UK.


>From: Kathy Kuhlow <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,   Kathy Kuhlow
><[log in to unmask]>
>To: [log in to unmask]
>Subject: Re: [TN] Flux residue with a no-clean process
>Date: Wed, 30 Jan 2002 08:19:46 -0600
>
>IPC-610 has no-clean residues as acceptable.  Is it possible that flux may
>have been mixed with a washable?  Washing a no-clean off is more
>detrimental than leaving it alone.
>
>Is the assembly conformally coated?  Is the application intended to be in a
>wet or high humidity/moisture enviroment?
>
>Kathy
><< TEXT.htm >>


_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail.
http://www.hotmail.com

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Date:         Wed, 30 Jan 2002 16:05:36 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Flux residue with a no-clean process
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Kathy,

I am very interested in this as we have the following processes:

1.      No clean smt - no clean wave solder - saponified wash
2.      No clean smt - clean wave solder - aqueous wash.

Could you please advise why this would be detrimental. Would this affect the
reliability of the joints and if so is there a paper on this.

Thanks for your help.

Best regards

Marc.
-----Original Message-----
From:   Kathy Kuhlow [mailto:[log in to unmask]]
Sent:   Wednesday, January 30, 2002 2:20 PM
To:     [log in to unmask]
Subject:        Re: [TN] Flux residue with a no-clean process

 << File: TEXT.htm >> IPC-610 has no-clean residues as acceptable.  Is it
possible that flux may have been mixed with a washable?  Washing a no-clean
off is more detrimental than leaving it alone.

Is the assembly conformally coated?  Is the application intended to be in a
wet or high humidity/moisture enviroment?

Kathy

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Date:         Wed, 30 Jan 2002 07:18:18 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: pulse plating - without additives
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

have you tried the 'american electroplaters society'?  their web page is:

http://www.aesf.org/

phil

-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 12:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives


Hello platers.  I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems  that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.

Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
 increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.

A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:

forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2

The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?

If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.

regards,

Adam Seychell.

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=========================================================================
Date:         Wed, 30 Jan 2002 10:18:41 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Goldman, Patricia J." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Goldman, Patricia J." <[log in to unmask]>
Subject:      Re: pulse plating - without additives
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Adam,
In late 1999 there was a TechNet thread on pulse plating.  You should be able to pick it up in the archives on IPC's website.  They may contain some useful info for you.

Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]


-----Original Message-----
From: Robert Peterson [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 7:47 AM
To: [log in to unmask]
Subject: Re: [TN] pulse plating - without additives


Hi,
I've never done it, but there is an article available at
http://dynatronix.com/copper.html

Hope this helps

Bob Peterson
Alternate Final Finishes, Inc.

-----Original Message-----
From: Adam Seychell [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 3:10 AM
To: [log in to unmask]
Subject: [TN] pulse plating - without additives


Hello platers.  I am hoping someone here can share a few words
of wisdom about reverse pulse plating. I'm having difficulty
finding detailed information on the subject, as my local university
library showed to carry almost nothing. It seems  that the
literature on reverse pulse plating is bound to research papers
only (which I latter learned can be quite costly and time
consuming to obtain). What I like to know is a method of plating
"standard" printed circuit boards in acid copper bath *without*
the use of additives. Pulse plating without additives has been
done or so I've been told, however most documents I have
read only talk about baths containing additives.

Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
would produce a rough and grainy deposit, especially when
thickness' become high ( >35 um). The problem is aggravated by
 increasing current density. Even at current densities of
0.5A/dm2 the deposits still remain unacceptable. This is
something I have observed through experimentation.

A test panel was plated using reverse pulse technique to see
what effect it had compared to DC plating at an equivalent
average current density. Not having a proper pulse plating power
supply I constructed my own basic one, using standard DC supply
and an electronic circuit to periodically reverse the output. The
parameters of the plating were:

forward time = 5 ms
reverse time = 1.7 ms
forward & reverse current densities = 3 A/dm2
average current density = 1.5 A/dm2

The pulse plating deposits were only slightly improved over DC
plating. A rough and crystalline surface was clearly visible under a
40X microscope. This does not sound promising and I am hoping
this is due to incorrect characteristics of the current pulse. Most
reverse pulse plating systems tend to use forward/reverse current
ratios of around 3, forward times of 10~20ms and reverse times
1~2ms. Is important for the current reverse pulse to be short and
high ?

If anyone could guide me to right path I'd be greatly thankful. If
there is no such thing as additive free copper plating for PC
fabrication then kindly let me know as this could save me lot of
time doing what others have already attempted.

regards,

Adam Seychell.

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Date:         Wed, 30 Jan 2002 10:34:43 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: pulse plating - without additives??
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At risk of stating the obvious...

You really do not want "just any Copper plating", you want brilliant, smooth,
shiney, flexible, stretchable Copper....good luck getting it with ANY
rectifier without "additives".  Make up a model plating bath that would fill
a hull cell, and check out what you can expect.

Rudy Sedlak

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Date:         Wed, 30 Jan 2002 07:30:03 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Roger Stoops <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Roger Stoops <[log in to unmask]>
Subject:      Re: Minimum bend radius calculation in a flex circuit
X-To:         Doug Pogatetz <[log in to unmask]>
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In addition to the comments of our venerable colleagues, the IPC has some
interesting formulas for determining minimum bend radii.  The specification
in IPC-2223, Sectional Design Standard for Flexible Printed Boards.  In
section 5.2.3.4, formulas for single- and double-sided circuits (with
coverlay) are given.  I made a rough Excel spreadsheet that helped me
determine the min radius for a "Flex to Install" application.

My first design didn't work too well because the circuit was too thick for
the required bend radius.  Using the IPC guideline really helped (gratuitous
pitch for the IPC), likewise with having nice, understanding engineers
(blatant gratuitous compliment) !

I have sent the file to you; if anyone else wants to get a copy, please give
me an e-jingle.
 <<Flex_radius.xls>>
Regards,
Roger M. Stoops, C.I.D.         [log in to unmask]
TRIMBLE NAVIGATION LLC
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH   45424-1099      USA
Telephone:  937 233 8921      800 538 7800      ext. 288
Facsimile:  937 233 7511

http://www.trimble.com


 -----Original Message-----
From:   Doug Pogatetz [mailto:[log in to unmask]]
Sent:   Tuesday, January 29, 2002 4:00 PM
To:     [log in to unmask]
Subject:        [TN] Minimum bend radius calculation in a flex circuit

I am on project that requires that I determine the minimum bend radius of a
flex circuit. I have not been able to find out any formulas or calculations
to help out.

I am a mechanical design engineer, so I am not up on all the terminology.
It will of the class "Flex to Install", and will be of the adhesiveless
type. Can anyone help out?

Thanks.

Doug

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Date:         Wed, 30 Jan 2002 10:45:09 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Hargreaves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Hargreaves <[log in to unmask]>
Subject:      IPC-6011, 6012 testing requirements
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Hi All,
Is the board shop required to make & analyze microsections for every job
fabricated to IPC-6011 & 6012 ?  The spec's seem to indicate this.

Thanks,
Mark Hargreaves

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Date:         Wed, 30 Jan 2002 10:01:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
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Subject:      Re: Flux residue with a no-clean process
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Is it OK to have flux residue on assemblies when the process is no clean.

*That depends entirely on what flux you are using, the amount of flux your
are applying, and the reflow profile you are using. I suggest you get a
copy of IPC-TP-1115, that goes over the things you need to think about when
transitioning to no-clean assembly.  Flux is one of the considerations.

We have assemblies that are failing in the field and the customer thinks
this
flux residue may be an issue. They think the assembly has been wet.

*What is the failure mechanism?  How many assemblies are affected?  What
does your customer mean by "wet"?

What do you think????

*I think we need more information.

Doug Pauls
Rockwell Collins

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Date:         Wed, 30 Jan 2002 11:03:25 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
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Subject:      Re: Flux residue with a no-clean process
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Oliva
We have seen many failures over the last 10 years associated with No Clean
low solids assembly processes.  The failures fall into four general
catigories, electrochemical migration failures, electrical leakage failures,
visible (cosmetic only) residues and insulative failures on contact areas.

It sounds like you are experiencing electrical leakage and electrochemical
migration problems.  These problems typically stem from bare board and
component cleanliness (HASL flux is high in chloride and / or bromide
activators) from fluxes, etchants, rinse water quality.  The other failure
mechanism that we have seen is the flux from hand solder or touch up not
completely heated (complexed means to drive all the carrier from the flux
after it has reacted it's activation temperature, so as not to absorb
moisture).  I would recommend Ion Chromatography analysis on the failed
assemblies and compare this to current production samples. After the failure
analysis is completed and a corrective action plan is put into place I would
suggest a process qualification using a test board built by your fabrication
house and run through your primary (SMT and PTH) processes and your secondary
(hand solder, temporary maskents) processes.  Then subject these test boards
to SIR testing protocol identified in J-STD 001.

I have included information from a recent article that we published on
failures.

Electrochemical Migration  and Leakage Failures
This type of failure occurs when the following key variables are combined.

1st is a voltage differential (power to ground),

2nd is the transfer fluid (e.g. absorbed surface moisture - in micro-droplet
form) and

3rd is a corrosive (conductive residues for leakage failures)) residue that
will create the deplating of the anode and carry the metal salt into solution
and allow plating along the current path.


All three variables must be present in order for the electrochemical
migration failure to occur.  With a power requirement of as little as 1.5
-2.0 volts to drive the dendrite formation, nearly all electronic circuits
are susceptible to this type of failure criteria (as long as the three
conditions exist).  Generally, a failure occurs when the spacing between
power and ground is connected by a thin layer of moisture that combines the
corrosive residues and the voltage to create a metal dendrite that shorts the
circuit. This conductive metal path creates a short circuit on an assembly in
the field, and this assembly is then returned to the manufacturer where a
typical failure analysis is performed.  This typical failure analysis will
often include a SEM/EDX analysis showing the following elements, carbon,
oxygen, tin, lead, and copper.  This elemental investigation provides some
wonderful photos of the dendrite and shows that copper, tin and lead metals
were the metals that created the short, but it doesn't tell us what caused
the dendrite to grow.

We still need to understand the contamination types and levels, as well as
determining the sources and why the assembly surface was absorbing moisture.
Our focus should not be on which metal created the short (it has to be one of
the metals in the area of the failure), but rather, on what corrosive
residues caused the dendrites and where they came from.  We have found that
tools such as Ion Chromatography and SIR testing give us a very detailed
understanding of the specific residue species. The No Clean flux residue is
not encapsulating enough to keep the board fabrication residues away from
absorbed moisture and the circuit voltage.

We have published a number of case studies on these issues and are availble
from our web site.


Terry Munson
CSL Inc.
P 765-457-8095
F 765-457-9033

<A HREF="www.Residues.com">www.Residues.com</A>

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Date:         Wed, 30 Jan 2002 16:37:16 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         Jim Marsico <[log in to unmask]>,
              David Douthit <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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Jim

I know this is a late posting, because I have only just come back on-line
however, what you have encountered is reversion.

The UR materials tend to discolour when exposed to high temperatures, but
this does not generally affect their subsequent performance - if anything it
might improve it because you have ensured a full x-link of the polymer -
fully reacted.

The discoloration may however, be an unacceptable visual condition to your
customer, depending upon their inspection criteria.

Whatever, it will be possible to remove and re-coat if you desire.

You mention that this is a space application, therefore this material will
probably have excellent outgassing characteristics and I can only think of 1
or 2 UR space (NASA / ESA) approved coatings. I am surprised that you have
this reversion, what did their technical staff advise? I would like to know
for my own record.

Regards Graham Naisbitt

[log in to unmask] <mailto:[log in to unmask]>

Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK

www.concoat.co.uk <http://www.concoat.co.uk>

Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
> Sent: 29 January 2002 00:49
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
>
> Jim,
>
> You have chemically altered the polymer. It will no longer
> perform it's designed function.
>
> David A. Douthit
> Manager
> LoCan LLC
>
> "Marsico, James" wrote:
>
> > Help!  Emergency!
> >
> > We have a completed assembly (top assembly with many boards,
> hybrids, etc.)
> > ready for shipment to our customer (space product).  The last
> operation was
> > to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The
> assembly was
> > put in an oven at 150 C for two hours.  After hours of
> reviewing all of the
> > materials and bill of material, component by component (component data,
> > supplier phone calls, etc.), the only item that is not rated
> for 150 C is
> > the polyurethane conformal coating, which turned yellow/brown
> in color.  Can
> > anyone explain what actually happened to the coating and if it
> can be used
> > as is?
> >
> > Thanks,
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
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Date:         Wed, 30 Jan 2002 10:39:05 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Flux residue with a no-clean process
X-To:         [log in to unmask]
Mime-Version: 1.0
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I found an old copy of ipc-tp-1115 "Selection and Implementation Strategy for A
low-residue no-clean process" published Dec. 1998.  Have not read thru it yet
but also have simular interest in implementation of no-clean. If any one has
more referance info i would appreciate.







[log in to unmask] on 01/30/2002 09:05:36 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      [log in to unmask]








 To:       [log in to unmask]

 cc:       (bcc: Warren Crow/US/I-O INC)



 Subject:  Re: [TN] Flux residue with a no-clean process








Hi Kathy,

I am very interested in this as we have the following processes:

1.      No clean smt - no clean wave solder - saponified wash
2.      No clean smt - clean wave solder - aqueous wash.

Could you please advise why this would be detrimental. Would this affect the
reliability of the joints and if so is there a paper on this.

Thanks for your help.

Best regards

Marc.
-----Original Message-----
From:   Kathy Kuhlow [mailto:[log in to unmask]]
Sent:   Wednesday, January 30, 2002 2:20 PM
To:     [log in to unmask]
Subject:        Re: [TN] Flux residue with a no-clean process

 << File: TEXT.htm >> IPC-610 has no-clean residues as acceptable.  Is it
possible that flux may have been mixed with a washable?  Washing a no-clean
off is more detrimental than leaving it alone.

Is the assembly conformally coated?  Is the application intended to be in a
wet or high humidity/moisture enviroment?

Kathy

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Date:         Wed, 30 Jan 2002 19:01:21 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
X-To:         Olivia Mc Dermott <[log in to unmask]>
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I think there is a strong risk of cross-purposes here.

To reply to the first question: if the product has been operating under
adverse climatic conditions, the "no-clean" chemistry is a no-no, unless
extremely careful qualification has been made.

To add something: "no-clean" chemistry has been designed to be as safe
as possible for what it has been designed, i.e., leaving the residues in
situ. Attempting to clean something which has not been designed to be
cleaned MAY work, but it is just as likely to be a helluva sight more
dangerous than not attempting to clean it, at all. NOT to be recommended
for the faint-hearted or ignorant.

Brian



Olivia Mc Dermott wrote:
>
> Is it OK to have flux residue on assemblies when the process is no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
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Date:         Wed, 30 Jan 2002 17:03:30 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
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Olivia

No clean fluxes leave residues.

J-STD-001B (can't quote issue C because I don't have a copy to hand) states:

8.3.5 Flux Residues

Assemblies shall be tested in accordance with IPC-TM-650, Test Method 2.3.27
and shall comply with the following requirements for the maximum allowable
level of flux residues:

Class 1 assemblies less than 200 microgram's/sq cm
Class 2 assemblies less than 100 microgram's/sq cm
Class 3 assemblies less than 40 sq/sq cm


In case you don't know the classifications

Class 3 is safety critical products - e.g. gas meters, military hardware,
ABS, air bag or engine management stuff etc..
Class 2 is service dependant products - UPS systems, process plant control
and stuff that doesn't necessarily endanger life but matters if it breaks!
Class 1 is low consequence product - PC's, phones, toys etc..

As to the failures you mention, flux residues + moisture + electricity =
trouble.

Hope this helps.

Regards Graham Naisbitt

[log in to unmask] <mailto:[log in to unmask]>

Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK

www.concoat.co.uk <http://www.concoat.co.uk>

Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Olivia Mc Dermott
> Sent: 30 January 2002 13:48
> To: [log in to unmask]
> Subject: [TN] Flux residue with a no-clean process
>
>
> Is it OK to have flux residue on assemblies when the process is
> no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
> http://www.hotmail.com
>
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Date:         Wed, 30 Jan 2002 17:17:01 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: 2 Conformal Coating ?'s
In-Reply-To:  <51858C36CF03D311847F00508B2C40B20D0681@INTERTRONICS_01>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding:  7bit

Peter and other Techies,

With apologies for this very tardy response - and I won't bore you with the
why's and where fore's......and no, it wasn't because I couldn't. So, better
late than never and written at 34,000 feet - that's 10,000 meters in new
money:

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Swanson
Sent: 10 December 2001 17:13
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s


Graham,

UV or light curing coatings:
- Solvent free

As are many thermal and moisture curing silicones. The more recent
developments in water based technology also offer a new solution to the
problem (pardon the intended pun).

- Full cure in seconds, on-line

Yes but this is a misleading statement. Conformal Coatings are intended to
be protective envelopes, conforming to the varied geometry of a printed
circuit assembly and should, ideally, be applied under as well as over,
components. This then begs the question of how to ensure the coating is
properly cured in areas where light cannot be readily applied. The method is
generally to incorporate a secondary curing mechanism thus rendering the
material more akin to a 2 part rather than:

- Single part

As I suggest above, these secondary curing agents often influence the pot
life and the shelf life of the end product. This can be a major drawback for
the smaller / lower volume electronic producers.

Virtually all modern conformal coatings are single part products, and
providing long pot and shelf life, not uncommonly around 12 months, is the
norm. This does not always apply to UV curable coatings nor indeed, to most
silicones.

- Non flammable

What do you mean by non-flammable? Are you referring to the liquid or cured
material?

Materials that are qualified / approved to such specifications as
MIL-I-46058 - IPC-CC-830 - Def Std 59/47 issue 4 - UL - etc., must meet
certain "flammability" tests in their cured state. This would not represent
any particular advantage of UV over conventional coatings.

In their liquid state, I frankly doubt that any coating material has any
greater or lesser degree of flammability. Being "resins or polymers" or
otherwise plastic materials, they have a tendency to "burn" in a rather
dramatic way, under the right conditions.

- Can meet MIL I-46058C and UL

Can meet? This is a rather curious term as it implies that many do not meet
such specifications. I am aware of many UV coatings that cannot meet the
requirements of such specifications. This is quite often in respect to their
flexibility at extremely low  temperatures.

I would like to make a point here about such terms as "meets the
requirements of..." or "meets or exceeds...". Either a coating is qualified
/ approved or it is not. It costs a great deal to obtain such qualifications
/ approvals, and is one of the issues delaying the supercession of the MIL
Spec by the IPC-CC-830 - that and the issue regarding independent testing
required under the prevailing MIL spec..

- Good to excellent environmental resistance

Are you suggesting above and beyond conventional materials?

- Can be "rigid" or "flexible" (Shore D80 to Shore D40)

I am not sure that this is a stipulation within the prevailing
specifications. What benefit are you alluding to?

- Can be used on flex

Uniquely? Not in my experience.

- Can have strong fluorescence for inspection, or even be black

A requirement of the MIL Spec and Defence Standards (British) is that the
conformal coating shall not obscure markings on the board and components to
facilitate repair and rework. Whilst this is not usually a requirement for
"commercial" applications, it is fair to say that the addition of pigments
or dye's can greatly influence the performance of the coating under extreme
conditions.

The Military require that qualified coatings contain a UV tracer to aid
inspection. I think it fair to say, that the half-life of the tracer is
affected by its exposure to strong UV light during cure.

There are "black" or indeed other coloured coatings available however, the
addition of such pigments, as I said above, affect performance particularly
in respect to moisture resistance. Such pigments effectively "separate" the
coating molecules leaving space for moisture to more easily migrate in and
out of the film.

Another point - why black or coloured material? It has been my experience
that the customer is often seeking a means of "hiding" the circuit design.
This is not likely to be very successful. Clever use of chemical stripping
agents or mechanical removal of the coating can be easily effected.

They are not suitable for all applications - are better sprayed, not so good
for dipping. If sprayed (say, using PVA or Nordson type selective spray
equipment), then full cure can often be achieved just with light. Otherwise,
secondary cures for shadowed areas may be achieved with heat, anaerobic,
moisture or other mechanisms.

"Horses for courses" is an oft quoted expression - at least by me! UV
curable coatings have many applications: Fibre-optics, LCD's, some
photo-cells, most 2D applications etc.. As we built (probably?) the world's
first in-line dip and UV curing system in 1987, we learnt the hard way, the
many process issues that need to be addressed.

As an example, and as you say Peter, dip coating is not its forte. The
coating area must be separated from the curing zone, no stray light can get
to the tank and no-one should be able to view the light, or it would be the
last thing they saw. Furthermore, the assemblies have to be racked onto the
jigs / carriers face-on, so that the light can shine forth upon the face of
the assembly. This meant that the system has 1/3rd the capacity / throughput
of a conventional cure coating.

Robotic selective coating systems revolutionised the coating business -
thankfully! Yes, these coatings are much more applicable to this method but,
the time it takes to apply the product remains the same whatever the coating
type. Allowing due separation from the application zone, there is not too
much advantage to be gained by using light instead of heat.

To answer Mike Fenner's question, most pcb coatings are acrylic based, which
is a free radical cure. Expose to the correct wavelength/intensity of light
for required time and full cure is achieved. In fact, if the light is taken
away, curing stops. All the coating must be exposed to the light.

There are some coatings (a few) based on epoxy chemistry and a cationic
cure. Some cross linking will continue after the light is removed, but only
for thin sections (i.e. it doesn't propagate far), and just like the free
radical cure, all the coating must be exposed to the light.

You see, its all done with mirrors!

I refuse to be drawn into a discussion on free radicals. People who know me
will know why - I am not a chemist, but the worlds greatest parrot!!

So, an interesting technology which certainly has its place in the panoply
of coatings available for circuit protection. Whilst not a universal
panacea, they can often offer processing speed and simplicity, including
perhaps some environmental and health & safety advantages.

No argument there.

IMHO, they should not be dismissed totally out of hand by competitors to the
technology in an open forum; for one thing, this might insult the many
companies who are successfully using them!

IMHO you are correct. Unlike most suppliers, we offer a comprehensive range
of coatings including UV's.

Regards,
Peter

=========================================================
Peter Swanson            [log in to unmask]
INTERTRONICS                http://www.intertronics.co.uk

INTERTRONICS is dedicated to providing quality material,
  consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
   the highest levels of technical support and customer
                         service.

I hope this will be taken in the spirit in which it is offered and - if you
will pardon the pun: shed more light on the subject. I am sure that I speak
for Peter in inviting comments to the above exchange that may help engineers
decide on the best route for their product.

Regards Graham Naisbitt

[log in to unmask] <mailto:[log in to unmask]>

Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK

www.concoat.co.uk <http://www.concoat.co.uk>

Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121


-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: 09 December 2001 19:01
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s


Peter,

I am semi-comatose now, so please, tell us what exactly are the advantages
of UV curable coatings?

Regards, Graham Naisbitt

[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>

For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>

Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Swanson
Sent: Friday, December 07, 2001 05:51
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s


Graham,

You really must see someone about your delusions over UV cured coatings,
which are successfully used to coat many thousands of pcb's each year. I
know someone who has a nice sofa you can stretch out on whilst you tell him
all about it.... <g>

Suitability for UV has nothing to do with 3D v. 2D, more to do with the
complexity of the assembly geometry and the application methodology. These
will determine if a secondary cure mechanism is needed for the application.
In many instances (and with some of our customers), full cure is achieved
just with light.

Regards,
Peter
--
--------------------------------------------------------
Peter Swanson        [log in to unmask]
INTERTRONICS            http://www.intertronics.co.uk

   INTERTRONICS is dedicated to providing quality
  material, consumable and equipment solutions to the
 electronics manufacturing and other technology based
  industries, with the highest levels of technical
           support and customer service.


-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: 06 December 2001 16:52
To: [log in to unmask]
Subject: Re: [TN] 2 Conformal Coating ?'s


Mike

You would be better to go with a conventional coating. UV is not ideal for
3D objects - works great in 2D, cos you don't have to bend light! :-)

I cannot remember what the operating environment was for your circuit - if
you would care to repeat, I can recommend something - however, I am sure
that a one part AR or UR coating from a reliable supplier will give you the
best overall results - process and operating environment.

Regards, Graham Naisbitt

[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>

For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>

Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121





-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
Sent: Thursday, December 06, 2001 02:41
To: [log in to unmask]
Subject: [TN] 2 Conformal Coating ?'s


Hello,
Thanks in advance if you have taken the time to read this!

#1- Im trying different materials in a spray application. Both are cured
using UV. One material does a "secondary cure" w/ moisture. This is cool
because after 100 hours after UV cure, all material is fully cured.
The other material Im trying uses HEAT for a secondary cure, or, if
shodowed during UV cure, the material wont cure and never will. Obviously I
dont want the stuff dripping or running anywhere, but being new to this
wonderful process, just dont feel good about leaving uncured material on a
product for it's entire life. Iv been told that you can "test" the product
to see if the uncured material is causing a problem but Im not sure what
type of test that would consist of. Any insight?

#2- Has anyone out there ever installed refelctive metal plates in their UV
oven to limit shadowing?

Thanks so much,

Mike Manwell

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Date:         Wed, 30 Jan 2002 09:09:01 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Stop Line Rules
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Production Gurus - was wondering what do you guys use as "stop line" rules
for SMT, Handload, Wave & ICT if you find too many defects - when do you
stop a line and raise a flag? Is there an industry standard? Does IPC have
any guideline? Any information you might have please pass it along.


Regards, Mohit

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Date:         Wed, 30 Jan 2002 09:04:36 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dyane White <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
X-To:         Olivia Mc Dermott <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
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It says "no clean" and therefore one would think that you do not have t=
o clean it.  The IPC standards says that residue from no clean fluxes a=
re acceptable provided it has been qualified and documented by your pro=
cess engineer as benign.  It has been my
experience that some "no clean" fluxes have corrosion issues.  If I wer=
e you I would do some ionic testing.  Check out IPC -TM-650 for test pr=
ocedures.  You might also check the chemical content of the flux you're=
 using.  If it contains halides then you
most likely have a problem.  Good luck!
Dyane White
Technical/Process Trainer
Philips Ultrasound
Bothell, WA


                                                                       =
                                                   =20
                    Olivia Mc Dermott                                  =
                                                   =20
                    <oliviamcdermott01@HO           To:  [log in to unmask]
G                                                  =20
                    TMAIL.COM>                      cc:  (bcc: Dyane Wh=
ite/ATL-BTL/MS/PHILIPS)                            =20
                    Sent by: TechNet                Subject:  [TN] Flux=
 residue with a no-clean process                   =20
                    <[log in to unmask]>                                  =
                                                   =20
                                                    Classification:    =
                                                   =20
                                                                       =
                                                   =20
                    01/30/02 05:48 AM                                  =
                                                   =20
                    Please respond to                                  =
                                                   =20
                    "TechNet E-Mail                                    =
                                                   =20
                    Forum."; Please                                    =
                                                   =20
                    respond to Olivia Mc                               =
                                                   =20
                    Dermott                                            =
                                                   =20
                                                                       =
                                                   =20
                                                                       =
                                                   =20




Is it OK to have flux residue on assemblies when the process is no clea=
n. We
have assemblies that are failing in the field and the customer thinks t=
his
flux residue may be an issue. They think the assembly has been wet.
What do you think???? All help appreciated.

_________________________________________________________________
Join the world's largest e-mail service with MSN Hotmail.
http://www.hotmail.com

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ional
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=

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Date:         Wed, 30 Jan 2002 10:47:24 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ted Edwards <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ted Edwards <[log in to unmask]>
Subject:      Re: Test Coupons
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I think that is probably what IPC-6011 is saying in para 4.3.2.3 when it
says, Acceptance of product for delivery shall be based on product that has
passed the testing requirements shown in the applicable Preformance
Specification and follows that with para 4.3.2.4 on rejected lots which
calls for 100% inspection and disposition of defective units.  IPC-6012A
says shall meet the microsection requirements, if it does not then 6011 on
what you do then should apply

----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, January 29, 2002 2:10 PM
Subject: [TN] Test Coupons


> Hi To All
> I am stumped - where are the words that say "if a coupon from a panel
fails
> to meet the specification requirements - all associated boards from that
> panel are rejected"?
>
> I know it, but I sure can't find it.
>
> Thanks
> Susan Mansilla
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>

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Date:         Wed, 30 Jan 2002 11:54:55 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: IPC-6011, 6012 testing requirements
X-To:         [log in to unmask]

Mark,

The customer specifies requirements OR, depending on several factors, each
supplier lot shall be sectioned and analyzed. For re-qualification to 6012,
the requirements are specified therein.

Back in the good old days, when processes were not nearly as well managed
(nor could the be considering what some of us had to work with) and boards
were complex for the time, we would test small lot sizes. When a board type
was particularly difficult, a lot of one might comprise the it and would be
tested. Obviously, if one board out of a lot of one failed, only one lot was
rejected. There's a lot more to this story and some of the other old timers
can add interest to it.

MoonMan

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Date:         Wed, 30 Jan 2002 12:01:40 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Wave Solder/NoPb Question
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Hi folks! I just extracted myself from a wonderful discussion on the impact
of PbFree solder alloys on the wave solder equipment, specifically the
impact of molten tin "wear" on the solderpot and pumps. My past
conversations with various folks has been that the impact will be minimal
with some of the stainless steel construction materials (e.g. 301 - 304
alloys) have some problems but cast iron, titanium, or ceramic coated
solderpots/pumps will fair reasonably well. SEHO presented a paper at APEX
which showed some wonderful molten tin attack on the wave solder equipment
(well, it was wonderful from a purely metallurgical view point anyway) but
my question to the forum is this: Does anyone have personal experience,
either good or bad, with PbFree solder alloys and wave solder equipment?
(Hey Eric de Kluizenaar - have you experienced any issues with your wave
solder line?). We don't need to discuss "who's" equipment was impacted but
more of a discussion of the alloy/solderpot interactions.


Dave Hillman
Rockwell Collins
[log in to unmask]

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Date:         Wed, 30 Jan 2002 12:06:59 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Wetting Balance Survey
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Hi folks! As chairman of the JSTD-002A and JSTD-003 solderability
committees I have been tasked to get a feel for who is using wetting
balance test equipment and what equipment they are using. The task group
will use this information to assist in improving the wetting balance test
procedure in the specifications by sending draft procedure proposals to
folks for critique. If you are a wetting balance user or use a wetting
balance in your company, could you please email me (off-line so we don't
bombard the TechNet)  your contact information (name, email address) and
what equipment you are using (brand X, homemade, etc.).

Thanks for your assistance!

Dave Hillman
Rockwell Collins
[log in to unmask]

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Date:         Wed, 30 Jan 2002 13:38:50 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         Graham Naisbitt <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

The coating supplier's technical staff stated that the discoloration was
probably due to oxidation of the double bond of the molecules.  He also
stated, as you, that the material may have become somewhat harder due to
further cross linking.

I don't think that moisture permeability is an issue, but what is a concern
is if the modulus increased which might affect chip component reliability,
if coating was actually under some ceramic or glass components.  In your
opinion, would additional cross linking, oxidation, reversion or being at
150C for 2 hours cause the modulus to increase?

As far as stripping the coating, we crossed this path once before and our
customer will not allow us to use any chemical stripping solution to remove
polyurethane coating.  They don't know how it will affect components,
boards, etc.

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879


        -----Original Message-----
        From:   Graham Naisbitt [SMTP:[log in to unmask]]
        Sent:   Wednesday, January 30, 2002 11:37 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] Conformal Coating

        Jim

        I know this is a late posting, because I have only just come back
on-line
        however, what you have encountered is reversion.

        The UR materials tend to discolour when exposed to high
temperatures, but
        this does not generally affect their subsequent performance - if
anything it
        might improve it because you have ensured a full x-link of the
polymer -
        fully reacted.

        The discoloration may however, be an unacceptable visual condition
to your
        customer, depending upon their inspection criteria.

        Whatever, it will be possible to remove and re-coat if you desire.

        You mention that this is a space application, therefore this
material will
        probably have excellent outgassing characteristics and I can only
think of 1
        or 2 UR space (NASA / ESA) approved coatings. I am surprised that
you have
        this reversion, what did their technical staff advise? I would like
to know
        for my own record.

        Regards Graham Naisbitt

        [log in to unmask] <mailto:[log in to unmask]>

        Concoat Limited
        Alasan House, Albany Park
        Camberley GU16 7PH - UK

        www.concoat.co.uk <http://www.concoat.co.uk>

        Phone: +44 1276 691100
        Fax: +44 1276 691227
        Mobile: +44 79 6858 2121


        > -----Original Message-----
        > From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
        > Sent: 29 January 2002 00:49
        > To: [log in to unmask]
        > Subject: Re: [TN] Conformal Coating
        >
        >
        > Jim,
        >
        > You have chemically altered the polymer. It will no longer
        > perform it's designed function.
        >
        > David A. Douthit
        > Manager
        > LoCan LLC
        >
        > "Marsico, James" wrote:
        >
        > > Help!  Emergency!
        > >
        > > We have a completed assembly (top assembly with many boards,
        > hybrids, etc.)
        > > ready for shipment to our customer (space product).  The last
        > operation was
        > > to ink mark a S/N.  The ink is cured at 150 F for 2 hours.  The
        > assembly was
        > > put in an oven at 150 C for two hours.  After hours of
        > reviewing all of the
        > > materials and bill of material, component by component
(component data,
        > > supplier phone calls, etc.), the only item that is not rated
        > for 150 C is
        > > the polyurethane conformal coating, which turned yellow/brown
        > in color.  Can
        > > anyone explain what actually happened to the coating and if it
        > can be used
        > > as is?
        > >
        > > Thanks,
        > >
        > > Jim Marsico
        > > Senior Engineer
        > > Production Engineering
        > > EDO Electronics Systems Group
        > > [log in to unmask] <mailto:[log in to unmask]>
        > > 631-595-5879
        > >
        > >
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Date:         Wed, 30 Jan 2002 12:37:21 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: Stop Line Rules
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_4A17237B.B6D7BAB2"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_4A17237B.B6D7BAB2
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

There is no defect allowed or production allowed to run without all =
defects being investigated and resolved.  This may involve several avenues =
but if a defect is found it is investigated.  We acknowledge that either =
the process has been improved and the process parameters are documented.  =
If a defect can't be removed we build in process control for those =
inherent issues.  Common defects that we consider inherent issues that we =
would build into a secondary op are wave solder skips because of orientatio=
n, sot-23 packages, connector shorts due to wave snapping. =20

All operators must take the initiative and stop.  We also hold those =
accountable for the quality of the product (good or bad).  I am very firm =
about accountability for good and bad workmanship. =20

--=_4A17237B.B6D7BAB2
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>There is no defect allowed or production allowed to run without all defects
being investigated and resolved.&nbsp; This may involve several avenues but if a
defect is found it is investigated.&nbsp;&nbsp;We acknowledge that either the
process has been improved and the process parameters are documented.&nbsp;
If&nbsp;a defect can't be removed we build in process control&nbsp;for those
inherent issues.&nbsp; Common defects that we consider inherent issues that we
would build into a secondary op are&nbsp;wave solder skips because of
orientation, sot-23 packages, connector shorts due to wave snapping.&nbsp;
</DIV>
<DIV>&nbsp;</DIV>
<DIV>All operators must take the initiative and stop.&nbsp; We also hold those
accountable&nbsp;for the quality of the product (good or bad).&nbsp;&nbsp;I am
very firm about accountability for good and bad workmanship.&nbsp;
</DIV></BODY></HTML>

--=_4A17237B.B6D7BAB2--

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Date:         Wed, 30 Jan 2002 12:46:34 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Flux residue with a no-clean process
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Just as a note on Graham Naisbitt's response, the test method he quotes is
residual rosin by UV-Vis spectroscopy.  The pass-fail limits are based on
RA flux from the first IPC Cleaning and Cleanliness Test Program
(IPC-TR-580).  For OA and no-clean fluxes, this test is largely
meaningless.

Doug Pauls
Rockwell Collins

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Date:         Wed, 30 Jan 2002 12:48:22 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      CSP/DSP SOLDERING PROBLEM?

Folks,

Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or some such
thing. I can't imagine there being solderability issues with these things,
but then I didn't think I'd live this long. However, after examining all
other possible process variables, and resolving them to some extent, these
things look to be the last straw.

Solder joints on these parts, mostly, aren't. The "C" clamp thing picture is
holding one of the critters on the board to make electrons flow.

Does anyone have any issues with these parts and their solderability? I do
appreciate the assistance. Steve, these probably are coming your way.

Earl

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Date:         Wed, 30 Jan 2002 12:03:12 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Douthit <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Douthit <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process
X-To:         Olivia Mc Dermott <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854";
              x-mac-creator="4D4F5353"
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Olivia,

You will have to do some testing based on the end use environments.
If this units are exposed to humidity levels above 80% the customer may have
a point.

David A. Douthit
Manager
LoCan LLC

Olivia Mc Dermott wrote:

> Is it OK to have flux residue on assemblies when the process is no clean. We
> have assemblies that are failing in the field and the customer thinks this
> flux residue may be an issue. They think the assembly has been wet.
> What do you think???? All help appreciated.
>
> _________________________________________________________________
> Join the world’s largest e-mail service with MSN Hotmail.
> http://www.hotmail.com
>
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> ---------------------------------------------------------------------------------

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Date:         Wed, 30 Jan 2002 13:56:39 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
MIME-Version: 1.0
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              boundary="part1_155.81ce9f1.29899be7_boundary"

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Would microabrasive blasting of the coating be an alternative to chemical
stripping?

Regards,
Mike Sewell

--part1_155.81ce9f1.29899be7_boundary
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<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#ffffff"><FONT  style="BACKGROUND-COLOR: #ffffff" SIZE=2>Would microabrasive blasting of the coating be an alternative to chemical stripping?<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT></HTML>

--part1_155.81ce9f1.29899be7_boundary--

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Date:         Wed, 30 Jan 2002 11:09:30 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dyane White <[log in to unmask]>
Subject:      Solder removal
MIME-Version: 1.0
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Greetings,

HELP...this question keeps rearing it's ugly head and I can't find where it is documented.  Must you remove solder before attaching or reattaching a component or wire?  This circumstances are....solder in a via or through hole...must the solder be removed
before a jumper wire is attached?  Can you reheat existing solder and add a component or wire to through hole or for that matter surface mount pads and where does it say it is acceptable or not acceptable?

Thanks,

Dyane White
Technical/Process Trainer
Philips Ultrasound
Bothell, WA

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Date:         Wed, 30 Jan 2002 14:34:54 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Laminate Blisters...
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Hi all!

Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.

Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through surface
mount.

I went to the inspector, and sure enough, this is what I saw. Go to:

http://www.stevezeva.homestead.com

They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...

Funny thing is they look like blisters, but the laminate isn't displaced like
you normally would see in a blister...to me, it's more like a sort of
delamination.

I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...

Anybody ever see something like this before?

-Steve Gregory-

--part1_120.a945b9d.2989a4de_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi all!
<BR>
<BR>Got another strange one again (why me?). Ran 70 peices of a double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
<BR>
<BR>Everything seemed to be going fine until the boards got to an inspector just prior to test. I get paged to look at some blisters she said she was seeing. I was pretty suprised because things were fine when they went through surface mount.
<BR>
<BR>I went to the inspector, and sure enough, this is what I saw. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>They appear randomly at one of four plated mounting holes on the board, and it's on random sides of the boards too...and it only happened on 19-assemblies. I can't find out when it happened. These mounting holes are off away from anything that was hand soldered too...
<BR>
<BR>Funny thing is they look like blisters, but the laminate isn't displaced like you normally would see in a blister...to me, it's more like a sort of delamination.
<BR>
<BR>I didn't see anything like that during SMT processing, I mean you can't miss something like that. But if it were due to excessive heat, I would expect to see it on more assemblies. The same thing would apply if it were caused by absorbed moisture wouldn't it? I would expect to see the problem on more assemblies. The fabs are all the same date code by the way...
<BR>
<BR>Anybody ever see something like this before?
<BR>
<BR>-Steve Gregory-</FONT></HTML>

--part1_120.a945b9d.2989a4de_boundary--

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Date:         Wed, 30 Jan 2002 12:10:16 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Mcmaster, Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: Laminate Blisters...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain

At first glimpse, the apparent change in opacity of the soldermask makes it
look like the mask is lifting off the laminate.  Is that what you see?

You said the date codes are all the same.  How old are they?  For moisture
absorption related delamination on FR4 they either have to be pretty old
(months) or been stored in very humid conditions.


> ----------
> From:         [log in to unmask][SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;[log in to unmask]
> Sent:         Wednesday, January 30, 2002 11:34 AM
> To:   [log in to unmask]
> Subject:      [TN] Laminate Blisters...
>
> Hi all!
>
> Got another strange one again (why me?). Ran 70 peices of a double-sided
> SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.
>
> Everything seemed to be going fine until the boards got to an inspector
> just prior to test. I get paged to look at some blisters she said she was
> seeing. I was pretty suprised because things were fine when they went
> through surface mount.
>
> I went to the inspector, and sure enough, this is what I saw. Go to:
>
> http://www.stevezeva.homestead.com
>
> They appear randomly at one of four plated mounting holes on the board,
> and it's on random sides of the boards too...and it only happened on
> 19-assemblies. I can't find out when it happened. These mounting holes are
> off away from anything that was hand soldered too...
>
> Funny thing is they look like blisters, but the laminate isn't displaced
> like you normally would see in a blister...to me, it's more like a sort of
> delamination.
>
> I didn't see anything like that during SMT processing, I mean you can't
> miss something like that. But if it were due to excessive heat, I would
> expect to see it on more assemblies. The same thing would apply if it were
> caused by absorbed moisture wouldn't it? I would expect to see the problem
> on more assemblies. The fabs are all the same date code by the way...
>
> Anybody ever see something like this before?
>
> -Steve Gregory-
>

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Date:         Wed, 30 Jan 2002 15:36:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         "[log in to unmask]" <[log in to unmask]>
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Don't have any experience with micro-blasting, but wouldn't it be difficult
to remove the coating from the entire board, in-between component leads?  If
someone is doing this, how's it working?  What media, what equipment?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879


        -----Original Message-----
        From:   [log in to unmask] [SMTP:[log in to unmask]]
        Sent:   Wednesday, January 30, 2002 1:57 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Conformal Coating

        Would microabrasive blasting of the coating be an alternative to
chemical stripping?

        Regards,
        Mike Sewell

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Date:         Wed, 30 Jan 2002 15:56:16 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: CSP/DSP SOLDERING PROBLEM?
X-To:         Earl Moon <[log in to unmask]>
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This component package is a pain in a spot somewhat below the neck, because
of the slug of metal used for a heat sink in the package. Issues are:
* Process measurement needs to be measured on the solder balls [both at the
inner row and the corner]. The difference in CTE of all the elements of this
package can make it difficult to profile otherwise.
* Process verfication with a common xray machine is close to futile.

Further, in these TI DSP, Dr. Cemel Basaran, SUNY Buffalo, 716-645-2114
X2429, [log in to unmask] has seen:
* Thinner [2 micron] than normal [20-micron ] AuSn4 IMC
* Black pad

Dave Fish



----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 10:48 AM
Subject: [TN] CSP/DSP SOLDERING PROBLEM?


> Folks,
>
> Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or some
such
> thing. I can't imagine there being solderability issues with these things,
> but then I didn't think I'd live this long. However, after examining all
> other possible process variables, and resolving them to some extent, these
> things look to be the last straw.
>
> Solder joints on these parts, mostly, aren't. The "C" clamp thing picture
is
> holding one of the critters on the board to make electrons flow.
>
> Does anyone have any issues with these parts and their solderability? I do
> appreciate the assistance. Steve, these probably are coming your way.
>
> Earl
>
> --------------------------------------------------------------------------
-------
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>

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Date:         Wed, 30 Jan 2002 14:59:20 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: CSP/DSP SOLDERING PROBLEM?
X-To:         [log in to unmask]

Thanks Dave,

My thinking exactly. My observations, at this point can't back my thoughts.
I will pursue this and see where we go from here.

Steve, they are coming your way as is the profile board. Not advertising.
Just preparing.

Earl

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Date:         Wed, 30 Jan 2002 15:02:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Laminate Blisters...
X-To:         [log in to unmask]

Michael and Steve,

Sounds almost right to me. However, it looks like a classic delam/blister
episode possibly brought on by edge condition problems propagating into the
hole. Also, though not being able to see clearly, the hole walls look a bit
rough so is it possible the reverse condition exists. Can't really tell the
"blister" depth.

Earl

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Date:         Wed, 30 Jan 2002 13:16:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Chuck Brummer <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Chuck Brummer <[log in to unmask]>
Subject:      Re: Laminate Blisters...
X-To:         [log in to unmask]
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If the corners are those near the corner of the panel from which these
boards came?  Maybe this is where they had been attached to a rack for
the oxide line and then did not get oxide on the inner layer at that
spot.  Heat then cause a loss of adhesion between the inner copper plane
and the prepreg.  With that you would not get any lift or distortion.
Just what pops into my head.  (Whoops, I think something fell out?)

Chuck Brummer
Acuson.

[log in to unmask] wrote:

> Hi all!
>
> Got another strange one again (why me?). Ran 70 peices of a
> double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is
> hand-soldered.
>
> Everything seemed to be going fine until the boards got to an
> inspector just prior to test. I get paged to look at some blisters she
> said she was seeing. I was pretty suprised because things were fine
> when they went through surface mount.
>
> I went to the inspector, and sure enough, this is what I saw. Go to:
>
> http://www.stevezeva.homestead.com
>
> They appear randomly at one of four plated mounting holes on the
> board, and it's on random sides of the boards too...and it only
> happened on 19-assemblies. I can't find out when it happened. These
> mounting holes are off away from anything that was hand soldered
> too...
>
> Funny thing is they look like blisters, but the laminate isn't
> displaced like you normally would see in a blister...to me, it's more
> like a sort of delamination.
>
> I didn't see anything like that during SMT processing, I mean you
> can't miss something like that. But if it were due to excessive heat,
> I would expect to see it on more assemblies. The same thing would
> apply if it were caused by absorbed moisture wouldn't it? I would
> expect to see the problem on more assemblies. The fabs are all the
> same date code by the way...
>
> Anybody ever see something like this before?
>
> -Steve Gregory-

--------------D2CF672B8DA3809CDD731D72
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
If the corners are those near the corner of the panel from which these
boards came?&nbsp; Maybe this is where they had been attached to a rack
for the oxide line and then did not get oxide on the inner layer at that
spot.&nbsp; Heat then cause a loss of adhesion between the inner copper
plane and the prepreg.&nbsp; With that you would not get any lift or distortion.
<br>Just what pops into my head.&nbsp; (Whoops, I think something fell
out?)
<p>Chuck Brummer
<br>Acuson.
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Hi all!</font></font>
<p><font face="arial,helvetica"><font size=-1>Got another strange one again
(why me?). Ran 70 peices of a double-sided SMT assembly. The board is a
6-layer FR4 board. PTH is hand-soldered.</font></font>
<p><font face="arial,helvetica"><font size=-1>Everything seemed to be going
fine until the boards got to an inspector just prior to test. I get paged
to look at some blisters she said she was seeing. I was pretty suprised
because things were fine when they went through surface mount.</font></font>
<p><font face="arial,helvetica"><font size=-1>I went to the inspector,
and sure enough, this is what I saw. Go to:</font></font>
<p><font face="arial,helvetica"><font size=-1><A HREF="http://www.stevezeva.homestead.com">http://www.stevezeva.homestead.com</A></font></font>
<p><font face="arial,helvetica"><font size=-1>They appear randomly at one
of four plated mounting holes on the board, and it's on random sides of
the boards too...and it only happened on 19-assemblies. I can't find out
when it happened. These mounting holes are off away from anything that
was hand soldered too...</font></font>
<p><font face="arial,helvetica"><font size=-1>Funny thing is they look
like blisters, but the laminate isn't displaced like you normally would
see in a blister...to me, it's more like a sort of delamination.</font></font>
<p><font face="arial,helvetica"><font size=-1>I didn't see anything like
that during SMT processing, I mean you can't miss something like that.
But if it were due to excessive heat, I would expect to see it on more
assemblies. The same thing would apply if it were caused by absorbed moisture
wouldn't it? I would expect to see the problem on more assemblies. The
fabs are all the same date code by the way...</font></font>
<p><font face="arial,helvetica"><font size=-1>Anybody ever see something
like this before?</font></font>
<p><font face="arial,helvetica"><font size=-1>-Steve Gregory-</font></font></blockquote>
</html>

--------------D2CF672B8DA3809CDD731D72--

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Date:         Wed, 30 Jan 2002 15:27:07 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
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MIME-Version: 1.0
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Mike Sewell Suggests:   Would microabrasive blasting of the coating be an
alternative to chemical stripping?

*Just be aware that microabrasive blasting generates a hell of a static
charge.  Enough to kill a static sensitive component.  I think the EMPF did
some work in microabrasion methods relative to ESD in the late 80s early
90s.  Check with the librarian at www.empf.org.

Doug Pauls
Rockwell Collins

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Date:         Wed, 30 Jan 2002 16:40:08 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "PERALTA, Kevin (BREA)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "PERALTA, Kevin (BREA)" <[log in to unmask]>
Subject:      Blacklight Fixture
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Since we've moved to a new facility (w/ a beautiful view of the San Gabriel
Mountain Range), we're in need of purchasing a new blacklight fixture for
our new Conformal Coating Booth. It's not very long, but I was hoping to get
some ideas for the best type of blacklight with a UV rating to put into
place. Can anyone serve up some good suggestions? Thank you!

Kevin L. Peralta
TRW Aeronautical / Lucas Aerospace


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<P><FONT SIZE=3D2 FACE=3D"Arial">Since we've moved to a new facility =
(w/ a beautiful view of the San Gabriel Mountain Range), we're in need =
of purchasing a new blacklight fixture for our new Conformal Coating =
Booth. It's not very long, but I was hoping to get some ideas for the =
best type of blacklight with a UV rating to put into place. Can anyone =
serve up some good suggestions? Thank you!</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Kevin L. Peralta</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">TRW Aeronautical / Lucas =
Aerospace</FONT>
</P>

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Date:         Wed, 30 Jan 2002 22:49:09 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "D.Terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: CSP/DSP SOLDERING PROBLEM?
X-To:         Earl Moon <[log in to unmask]>
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Hope you get this message once, since I had some trouble with sending =
mail (I changed provider, finally broadband !).


Hi Earl,

Couldn't find it on the net,  but could it be the same as the =
TMS320C6201GGP  (a 352 pins 0.8 mm pitch BGA with heatsink) ?
We've done a few, and so far no problems.=20
Perhaps the opens have their root cause in stencil printing ?  =
Stencilling parts like these can be troublesome with incorrect stencil =
or machinesetup (but I don't have to tell you that).

Daan Terstegge
http://www.smtinfo.net =20
  ----- Original Message -----=20
  From: Earl Moon=20
  To: [log in to unmask]
  Sent: Wednesday, January 30, 2002 7:48 PM
  Subject: [TN] CSP/DSP SOLDERING PROBLEM?


  Folks,

  Have some CSP's that are TI DSP's (320c6203 TMX 320C6203 BGLS), or =
some such
  thing. I can't imagine there being solderability issues with these =
things,
  but then I didn't think I'd live this long. However, after examining =
all
  other possible process variables, and resolving them to some extent, =
these
  things look to be the last straw.

  Solder joints on these parts, mostly, aren't. The "C" clamp thing =
picture is
  holding one of the critters on the board to make electrons flow.

  Does anyone have any issues with these parts and their solderability? =
I do
  appreciate the assistance. Steve, these probably are coming your way.

  Earl

  =
-------------------------------------------------------------------------=
--------
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  To unsubscribe, send a message to [log in to unmask] with following text =
in
  the BODY (NOT the subject field): SIGNOFF Technet
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[log in to unmask]: SET Technet NOMAIL
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>Hope you get this message once, since I had some trouble with =
sending mail=20
(I changed provider, finally broadband !).</DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>Hi Earl,</DIV>
<DIV>&nbsp;</DIV>
<DIV>Couldn't find it on the net,&nbsp; but&nbsp;could it be the=20
same&nbsp;as&nbsp;the <FONT color=3D#000000>TMS320C6201GGP&nbsp; (a 352 =
pins 0.8=20
mm pitch BGA with&nbsp;heatsink) ?</FONT></DIV>
<DIV>We've done a few, and so far no problems.&nbsp;</DIV>
<DIV>Perhaps&nbsp;the&nbsp;opens have their root cause&nbsp;in stencil=20
printing&nbsp;?&nbsp; Stencilling parts like these can be troublesome =
with=20
incorrect stencil or machinesetup (but I don't have to tell&nbsp;you=20
that).</DIV>
<DIV>&nbsp;</DIV>
<DIV>Daan Terstegge</DIV>
<DIV>http://<A=20
href=3D"http://www.smtinfo.net">www.smtinfo.net</A>&nbsp;&nbsp;</DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, January 30, =
2002 7:48=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] CSP/DSP SOLDERING =

  PROBLEM?</DIV>
  <DIV><BR></DIV>Folks,<BR><BR>Have some CSP's that are TI DSP's =
(320c6203 TMX=20
  320C6203 BGLS), or some such<BR>thing. I can't imagine there being=20
  solderability issues with these things,<BR>but then I didn't think I'd =
live=20
  this long. However, after examining all<BR>other possible process =
variables,=20
  and resolving them to some extent, these<BR>things look to be the last =

  straw.<BR><BR>Solder joints on these parts, mostly, aren't. The "C" =
clamp=20
  thing picture is<BR>holding one of the critters on the board to make =
electrons=20
  flow.<BR><BR>Does anyone have any issues with these parts and their=20
  solderability? I do<BR>appreciate the assistance. Steve, these =
probably are=20
  coming your=20
  =
way.<BR><BR>Earl<BR><BR>-------------------------------------------------=
--------------------------------<BR>Technet=20
  Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
  unsubscribe, send a message to <A=20
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text=20
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Date:         Wed, 30 Jan 2002 16:24:25 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: CSP/DSP SOLDERING PROBLEM?
X-To:         [log in to unmask]

I hear you Daan. I've examined/audited most everything to the point of
rejection. Only thing I come up with so far is as Dave says. However, I just
"feel" there is something more.

We had problems with TI parts, of the same ilk, concerning ball separation
dued to a too thick IMC layer (their terms). However. this should not affect
the solder joint on the board unless?

Earl

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Date:         Wed, 30 Jan 2002 22:52:23 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Laminate Blisters...
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Hi Steve,

I've seen large and flat blisters like yours from moisture absorption.  Can
you press on them and the laminate moves?  Somebody forgot to bake prior to
IR Reflow.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask] <mailto:[log in to unmask]>

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 2:35 PM
To: [log in to unmask]
Subject: [TN] Laminate Blisters...


Hi all!

Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.

Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through
surface mount.

I went to the inspector, and sure enough, this is what I saw. Go to:

http://www.stevezeva.homestead.com

They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...

Funny thing is they look like blisters, but the laminate isn't displaced
like you normally would see in a blister...to me, it's more like a sort of
delamination.

I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...

Anybody ever see something like this before?

-Steve Gregory-


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Content-Type: text/html;
        charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">


<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>Hi
Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>I've seen large and flat
blisters like yours from moisture absorption.&nbsp; Can you press on them and
the laminate moves?&nbsp; Somebody forgot to bake prior to IR
Reflow.</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=772134722-30012002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=772134722-30012002><FONT
color=#0000ff></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=772134722-30012002>
<P><FONT size=2>Integrity First&nbsp; -&nbsp; Service Before Self&nbsp; -&nbsp;
Excellence in All We Do<BR>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>Hans M.
Hinners<BR>Electronics Engineer<BR>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)<BR>226 Cochran Street<BR>Robins AFB GA 31098-1622<BR><BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR><BR>Com:
(478) 926 - 5224<BR>Fax:&nbsp;&nbsp; (478) 926 - 4911<BR>DSN Prefix:
468<BR></FONT></P></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, January 30, 2002 2:35
  PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Laminate
  Blisters...<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi
  all! <BR><BR>Got another strange one again (why me?). Ran 70 peices of a
  double-sided SMT assembly. The board is a 6-layer FR4 board. PTH is
  hand-soldered. <BR><BR>Everything seemed to be going fine until the boards got
  to an inspector just prior to test. I get paged to look at some blisters she
  said she was seeing. I was pretty suprised because things were fine when they
  went through surface mount. <BR><BR>I went to the inspector, and sure enough,
  this is what I saw. Go to: <BR><BR>http://www.stevezeva.homestead.com
  <BR><BR>They appear randomly at one of four plated mounting holes on the
  board, and it's on random sides of the boards too...and it only happened on
  19-assemblies. I can't find out when it happened. These mounting holes are off
  away from anything that was hand soldered too... <BR><BR>Funny thing is they
  look like blisters, but the laminate isn't displaced like you normally would
  see in a blister...to me, it's more like a sort of delamination. <BR><BR>I
  didn't see anything like that during SMT processing, I mean you can't miss
  something like that. But if it were due to excessive heat, I would expect to
  see it on more assemblies. The same thing would apply if it were caused by
  absorbed moisture wouldn't it? I would expect to see the problem on more
  assemblies. The fabs are all the same date code by the way... <BR><BR>Anybody
  ever see something like this before? <BR><BR>-Steve Gregory-</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C1A9E0.C82263F0--

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=========================================================================
Date:         Wed, 30 Jan 2002 16:52:05 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Adam Seychell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Adam Seychell <[log in to unmask]>
Subject:      Re: pulse plating - without additives

Thanks everyone for your help. The article at
www.circuitree.com "Copper Plating of Electronic
Interconnects without Additives" was very helpful
indeed. By "additives" they are referring to
brighteners and levelers. The bath they described
contained polyethylene glycol.

This article lead me to find two more lnks.

http://www.pcfab.com/db_area/archive/2001/0103/taylor.html

And US patent 6,303,014, which describes the "additive
free" process in greater detail. However, they
also use a "supressor", such as polyethelene
glycol in combination with the chloride ion.

http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1='6,303,014'.WKU.&OS=PN/6,303,014&RS
=PN/6,303,014

In reply to Rudy Sedlak, I beginning to see that
the rectifier cannot be a total solution.

Adam Seychell

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Date:         Wed, 30 Jan 2002 17:28:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Don Vischulis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Don Vischulis <[log in to unmask]>
Subject:      Re: Laminate Blisters...
In-Reply-To:  <[log in to unmask]>
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Content-Transfer-Encoding: 7bit

Steve:

I tend to agree with Mike's comment.  You might give one of the blisters a
probe with a sharp Xacto blade to determine if it's soldermask or laminate.
Different set of causes for each.

Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Wednesday, January 30, 2002 1:35 PM
To: [log in to unmask]
Subject: [TN] Laminate Blisters...


Hi all!

Got another strange one again (why me?). Ran 70 peices of a double-sided SMT
assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.

Everything seemed to be going fine until the boards got to an inspector just
prior to test. I get paged to look at some blisters she said she was seeing.
I was pretty suprised because things were fine when they went through
surface mount.

I went to the inspector, and sure enough, this is what I saw. Go to:

http://www.stevezeva.homestead.com

They appear randomly at one of four plated mounting holes on the board, and
it's on random sides of the boards too...and it only happened on
19-assemblies. I can't find out when it happened. These mounting holes are
off away from anything that was hand soldered too...

Funny thing is they look like blisters, but the laminate isn't displaced
like you normally would see in a blister...to me, it's more like a sort of
delamination.

I didn't see anything like that during SMT processing, I mean you can't miss
something like that. But if it were due to excessive heat, I would expect to
see it on more assemblies. The same thing would apply if it were caused by
absorbed moisture wouldn't it? I would expect to see the problem on more
assemblies. The fabs are all the same date code by the way...

Anybody ever see something like this before?

-Steve Gregory-

------=_NextPart_000_001A_01C1A9B3.822D1FC0
Content-Type: text/html;
        charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =

size=3D2>Steve:</FONT></SPAN></DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2>I tend=20
to agree with Mike's comment.&nbsp; You might give one of the blisters a =
probe=20
with a sharp Xacto blade to determine if it's soldermask or =
laminate.&nbsp;=20
Different set of causes for each.</FONT></SPAN></DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D741132623-30012002><FONT face=3DArial color=3D#0000ff =
size=3D2>Don=20
Vischulis</FONT></SPAN></DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>[log in to unmask]<BR><B>Sent:</B>=20
Wednesday, January 30, 2002 1:35 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Laminate=20
Blisters...<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi all!=20
<BR><BR>Got another strange one again (why me?). Ran 70 peices of a =
double-sided=20
SMT assembly. The board is a 6-layer FR4 board. PTH is hand-soldered.=20
<BR><BR>Everything seemed to be going fine until the boards got to an =
inspector=20
just prior to test. I get paged to look at some blisters she said she =
was=20
seeing. I was pretty suprised because things were fine when they went =
through=20
surface mount. <BR><BR>I went to the inspector, and sure enough, this is =
what I=20
saw. Go to: <BR><BR>http://www.stevezeva.homestead.com <BR><BR>They =
appear=20
randomly at one of four plated mounting holes on the board, and it's on =
random=20
sides of the boards too...and it only happened on 19-assemblies. I can't =
find=20
out when it happened. These mounting holes are off away from anything =
that was=20
hand soldered too... <BR><BR>Funny thing is they look like blisters, but =
the=20
laminate isn't displaced like you normally would see in a blister...to =
me, it's=20
more like a sort of delamination. <BR><BR>I didn't see anything like =
that during=20
SMT processing, I mean you can't miss something like that. But if it =
were due to=20
excessive heat, I would expect to see it on more assemblies. The same =
thing=20
would apply if it were caused by absorbed moisture wouldn't it? I would =
expect=20
to see the problem on more assemblies. The fabs are all the same date =
code by=20
the way... <BR><BR>Anybody ever see something like this before? =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BODY></HTML>

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Date:         Wed, 30 Jan 2002 15:24:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Steele <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Steele <[log in to unmask]>
Subject:      Re: ODB++
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Seth,


I have heard this question before and haven't known how
to respond to it. So I have a question for you, if it
could be shown through real data that the board built
from gerber and the board built from ODB are the "same"
(within a certain tolerance) would you be willing to
generate both sets of data and send them out accordingly?

I assume you are comfortable with your system outputting
gerber, it's ODB that has to "prove" it can duplicate the
gerber.

Here's what I have in mind, an experiment. You asked the
question "The problem is how do you insure that both sets
of output data are identical in every way?" Maybe one way
to test that is to test the input and output capabilities
of Genesis/Enterprise.

Let's translate a set of gerber back and forth with ODB a
certain number of times (10?) and see how the result
compares to the "reference data" (first generation gerber).
They would have to pass two tests, 1, a netlist check of
course and 2, a layer by layer feature comparison. The
netlist check is absolute, it has to pass. The features
could not vary more than (1?) percent. The feature
variation test is something we would have to come up with.
Is 1% to small or to large?

Ideally the 10th generation ODB would match the 1st
generation gerber by some agreed upon amount and pass a
netlist compare of course.

I don't know how sound this hare-brained idea is, I thunk
it up driving to work... But I think your question is valid
and has to be answered in some way.

Who would do the testing and presenting of the results?
Would you trust Valor? Frontline? IPC? NEMI? Maybe Valor,
a designer and a fabricator at the very least. Heck, I
volunteer to play if that's what it takes to get more ODB.



Regards,

Mark Steele
CAM Automation Engineer
Toppan Electronics, Inc.
858.695.2222
[log in to unmask]




>-----Original Message-----
>From: Seth Goodman [mailto:[log in to unmask]]
>Sent: Monday, January 28, 2002 6:28 PM
>To: TechNet E-Mail Forum.; Mark Steele
>Subject: RE: [TN] ODB++
>
>
>Hi Mark,
>
>From the design engineer's perspective, supporting two
>different formats
>does create a problem.  When you release a design to
>production, it is not
>supposed to be specific to one particular vendor (unless you
>have a captive
>fab shop and NEVER go outside).  Unfortunately, not all fab
>shops support
>ODB++.  If purchasing would be willing to limit themselves to
>fab shops that
>supported ODB++, that would be fine, but since that limits
>their options it
>is unlikely.  So in order to be universal, we would have to
>generate both
>ODB++ and Gerber.  This is easy to do but can create subtle
>problems that
>could take lots of time and money to run down.  The problem is
>how do you
>insure that both sets of output data are identical in every
>way?  While some
>programs allow you to import both data sets and compare, as a practical
>matter, assuring that they are identical is not possible.
>Since there will
>undoubtedly be subtle differences between the two, which one controls?
>Don't we also have to verify and validate both versions by
>building up both
>assemblies?  And when problems inevitably arise between boards from two
>different vendors using different data files, who 'ya gonna
>call?  Those
>dumb design engineers who created the problem, of course.


***stuff deleted*** (I would like to respond to that in another email.)

>
>Regards,
>
>Seth Goodman
>Goodman Associates, LLC
>tel 608.833.9933
>fax 608.833.9966
>
>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mark Steele
>> Sent: Monday, January 28, 2002 4:09 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] ODB++
>>
>>
>> Hi Paul,
>>
>>
>> I work for Toppan Electronics in San Diego, we are a
>> fab house.
>>
>> We strongly prefer ODB data. I tell our Sales people
>> to beg for it!
>>
>> For the past 2 years we have tracked type of data
>> (274D, 274X and ODB) and problems with that data such
>> as bad aperture lists, missing layers, incorrect
>> filename identification, etc, etc, etc.
>>
>> For example, for the last 226 jobs we have input we had
>> 41 issues with gerber, 0 for ODB. That's a lot of phone
>> calls and time spent just getting the data INTO our Genesis
>> system. We allocate 5 min to get the data and import an
>> ODB job, 30-40 for gerber (sometimes it takes hours for
>> gerber, that happens about once a month...)
>>
>> I realize not everyone uses Genesis as their CAM system, but
>> I would wager that a majority of the bigger fab houses do.
>>
>> So, yes, PLEASE generate ODB as a first choice and only send
>> out gerber if asked too...
>>
>> Of course that's just my opinion, I could be wrong...
>>
>>
>>
>> Mark Steele
>> CAM Automation Engineer
>> Toppan Electronics, Inc.
>> 858.695.2222
>> [log in to unmask]
>

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Date:         Wed, 30 Jan 2002 16:47:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Crepeau, Phil" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Crepeau, Phil" <[log in to unmask]>
Subject:      Re: Blacklight Fixture
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hi,

in your backyard (upland) is a company called uvp (ne ultraviolet products).  they make a unit called 'blak ray', model b-100a.  it's been around at least since the early sixties.

phil

-----Original Message-----
From: PERALTA, Kevin (BREA) [mailto:[log in to unmask]]
Sent: Wednesday, January 30, 2002 1:40 PM
To: [log in to unmask]
Subject: [TN] Blacklight Fixture



Since we've moved to a new facility (w/ a beautiful view of the San Gabriel Mountain Range), we're in need of purchasing a new blacklight fixture for our new Conformal Coating Booth. It's not very long, but I was hoping to get some ideas for the best type of blacklight with a UV rating to put into place. Can anyone serve up some good suggestions? Thank you!

Kevin L. Peralta
TRW Aeronautical / Lucas Aerospace


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Blacklight Fixture</TITLE>

<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff size=2>in
your backyard (upland) is a company called uvp (ne ultraviolet products).&nbsp;
they make a unit called 'blak ray', model b-100a.&nbsp; it's been around at
least since the early sixties.</FONT></SPAN></DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=220404400-31012002><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> PERALTA, Kevin (BREA)
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, January 30, 2002
  1:40 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Blacklight
  Fixture<BR><BR></FONT></DIV>
  <P><FONT face=Arial size=2>Since we've moved to a new facility (w/ a beautiful
  view of the San Gabriel Mountain Range), we're in need of purchasing a new
  blacklight fixture for our new Conformal Coating Booth. It's not very long,
  but I was hoping to get some ideas for the best type of blacklight with a UV
  rating to put into place. Can anyone serve up some good suggestions? Thank
  you!</FONT></P>
  <P><FONT face=Arial size=2>Kevin L. Peralta</FONT> <BR><FONT face=Arial
  size=2>TRW Aeronautical / Lucas Aerospace</FONT> </P></BLOCKQUOTE></BODY></HTML>

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Date:         Wed, 30 Jan 2002 16:36:20 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Thompson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject:      ENIG Thickness Standard?
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Is there a standard for the plating thickness of the ENIG surface
finish?  I've searched the archives and didn't find anything.  Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches.  What (if anything) is considered standard for this finish?

Thanks for your inputs.


Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Wed, 30 Jan 2002 22:00:04 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      AOI Stuff again...
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Hi all!

Bringing up the topic of AOI again. Read the Glenn Woodhouse summary (which I
think was GREAT by the way) that Daan reposted about the state of the
technology, had a fellow engineer that I work with attend a session at APEX
about AOI, and it seems that things may have become a bit cheaper, but as far
as using AOI for solder joint evaluation, there's still much to be desired...

The situation here is that there is some pressure from those above to get a
system in here that will be a fool-proof method to put a piece of equipment
in place that will eliminate the need for human inspection.

My take on it is that one focuses on making sure that the process is right
from the beginning, and then you don't need to spend a bunch of money on
automated inspection equipment, or depend on humans to inspect each and every
solder joint.

The reason I say that is because we are a low volume, high part number shop.
We may have ongoing business for years, but it maybe 10 assemblies a
month...what we consider high volume is a run of 250 assemblies per work
order...hehehe.

I just have the opinion that spending the big bucks for the AOI equipment
doesn't make a whole lot of sense in our situation...we'll be tweeking
programs during the run and probably won't have all the false calls, or
missed defects ironed-out by the time the work order is built...then a month
or two later on the same assembly, you go through the same drill again...

Any thoughts on this?

-Steve Gregory-

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Date:         Thu, 31 Jan 2002 11:03:53 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ENIG Thickness Standard?
X-To:         Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
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Rick,

I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.

Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.

Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.

Peter




                    Rick Thompson
                    <rthompson@VENTURAELECTR        To:     [log in to unmask]
                    ONICS.COM>                      cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet                Aero/ST Group)
                    <[log in to unmask]>               Subject:     [TN] ENIG Thickness Standard?


                    01/31/02 08:36 AM
                    Please respond to
                    "TechNet E-Mail Forum.";
                    Please respond to Rick
                    Thompson






Is there a standard for the plating thickness of the ENIG surface
finish?  I've searched the archives and didn't find anything.  Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches.  What (if anything) is considered standard for this finish?

Thanks for your inputs.


Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Wed, 30 Jan 2002 23:47:40 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
MIME-Version: 1.0
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Not fond of stripping (either chemical or mechanical removal), both have
pros/cons.  If the chemical is strong enough to remove a cured (overcured) UR
than its not doing the components or substrate any good either... It was just
food for thought - will look it up with EMPF.

Regards,
Mike Sewell

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<HTML><FONT FACE=arial,helvetica><FONT  COLOR="#8080ff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0"><B>Not fond of stripping (either chemical or mechanical removal), both have pros/cons.&nbsp; If the chemical is strong enough to remove a cured (overcured) UR than its not doing the components or substrate any good either... It was just food for thought - will look it up with EMPF.&nbsp; <BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman" LANG="0"></B><BR>
</FONT></HTML>
--part1_28.2161ce21.298a266c_boundary--

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Date:         Wed, 30 Jan 2002 23:48:39 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
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Circuitectctr.com has a good guide on coating removal methods with info re:
each method and a preferred order.

http://www.circuittechctr.com/guides/2-3-1.htm

Regards,
Mike Sewell

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">    <BR>
<BR>
<BR>
</FONT><FONT  COLOR="#8080ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"><B>Circuitectctr.com has a good guide on coating removal methods with info re: each method and a preferred order.<BR>
<BR>
http://www.circuittechctr.com/guides/2-3-1.htm<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"></B><BR>
</FONT></HTML>
--part1_107.c24056e.298a26a7_boundary--

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Date:         Thu, 31 Jan 2002 13:45:32 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Conformal Coating
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Unsubscribe.
Regards,





                    "TechNet
                    E-Mail Forum."       To:     [log in to unmask] AT Internet@ACPPSG
                    <[log in to unmask]       cc:     (bcc: Ken Fong/LU Plaza/HK/Astec)
                    RG> MikeSwll         Subject:     Re: [TN] Conformal Coating

                    01/31/02 01:23
                    PM










Circuitectctr.com has a good guide on coating removal methods with info re:
each method and a preferred order.

http://www.circuittechctr.com/guides/2-3-1.htm

Regards,
Mike Sewell


<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">    <BR>
<BR>
<BR>
</FONT><FONT  COLOR="#8080ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"><B>Circuitectctr.com has
a good guide on coating removal methods with info re: each method and a preferred order.<BR>
<BR>
http://www.circuittechctr.com/guides/2-3-1.htm<BR>
<BR>
Regards,<BR>
Mike Sewell</FONT><FONT  COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SERIF" FACE="Times New Roman Baltic" LANG="0"></B><BR>
</FONT></HTML>

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Date:         Thu, 31 Jan 2002 14:09:29 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              kevinyeah <[log in to unmask]>
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Date:         Thu, 31 Jan 2002 00:24:00 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Mark Steele <[log in to unmask]>
In-Reply-To:  <B136A0C653FCD311ABA400508B60DAB19C4BB8@EXCHANGE>
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Hi Mark,

> I assume you are comfortable with your system outputting
> gerber, it's ODB that has to "prove" it can duplicate the
> gerber.

Thanks for bringing this up.  I'm not suggesting that ODB++ needs to prove
itself, as its' market share among fab shops tells me that it does the job.
Given the choice, I would also opt for ODB++ as it can carry a lot more than
just bare board information.  The problem I have is in archiving any data
object in more than one format for the reasons explained below.


> Here's what I have in mind, an experiment. You asked the
> question "The problem is how do you insure that both sets
> of output data are identical in every way?" Maybe one way
> to test that is to test the input and output capabilities
> of Genesis/Enterprise.

This will test, for one particular data set, the ability of the Valor tool
to translate back and forth between Gerber and ODB++ without accumulating
error.  It really shows that their forward and reverse translators are
accurate inverses of each other.  It doesn't show that the two data files
produce the same board.  Even if we made a test to show that these two data
files were comparable, not very many designers use Valor tools to make their
output files.  Instead, we typically use the data file generators built into
our CAD systems.  If the CAD system doesn't produce ODB++ directly, and most
don't, then we use a third party tool (I use CAM350) to translate into
ODB++, either from the native CAD file or from Gerbers.

Even if the original CAD tool produced both output formats, the problem
remains.  Producing an output file, either Gerber or ODB++, from a native
CAD database is a translation process.  It is more difficult, though
fundamentally similar to translating Gerber into ODB++.  In both cases, some
program looks at a series of data objects and translates them into another
series of data objects of a different format.  That program is written by
human beings and therefore it has bugs.  I have yet to own a piece of
bug-free software.  The software that produces ODB++ is not the same as the
software that produces Gerber.  It most likely has different bugs.  My point
is that the two output files will not be exactly the same.

I know from experience that there are flaws in the Gerber data generators in
most CAD programs.  The nastier ones are history but some subtle ones
remain.  Similarly, different Gerber viewers can display the same data file
differently.  Occasionally, I have to spend a lot of time working with a fab
shop because their Gerber viewers and my Gerber viewers show different
results from the same data.  This is an unfortunate waste of both my time
and theirs, but it has to be done.  Because we don't use the same brand and
version of software, it is unavoidable.

What I want to avoid is dealing with problems in ODB++ data in addition to
Gerber data.  Also, consider that if ODB++ becomes the Gerber replacement,
there will be companies other than Valor writing software for it.  That
means there will be some differences between how a Valor program and someone
else's program interprets the same ODB++ data.  This may not come up very
often, but it will come up, especially when other vendors first start using
ODB++.  Unless Valor achieves a 100% market share, we will all have to deal
with some subtle differences between vendors' software.  This problem could
be lessened if an independent industry group produced a validation suite
that a program would have to pass to call itself ODB++ compliant.

I would be happy to support ODB++ as the single output format for any given
board.  In fact, I would prefer almost any intelligent data format to
Gerber, which is truly a rotten old standard.  But until my customers'
purchasing departments will accept ODB++ only, the only "universal" option
today is Gerber.  Until ODB++ becomes as universally accepted by fab shops
as Gerber, or the fab shops start to give a big enough discount to offset
the extra costs of supporting two data formats, IMO most designers will opt
to stay with Gerber.  If using ODB++ really saves the fab shops money, and
I'm sure it does, all they have to do is pass some of those savings on to
their customers who use it and it will become the de facto standard before
you know it.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966

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=========================================================================
Date:         Thu, 31 Jan 2002 09:15:53 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: [TN] Wave Solder/NoPb Question
Mime-Version: 1.0
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Content-Transfer-Encoding: quoted-printable

Dave

We run trials with folks from ERSA. Actually, due to their knowledge, =
erosion of the solderpot, the wave-nozzle, and the pump are considerable. =
However, new equipment seem to be produced lead-free save with coated =
stainless steel. It seems also as if it is possible to cover the parts in =
danger with a organic coating (paint) which can be done during the =
downtime when a service is done. The coating needs a refreshment every one =
or two years I heard though one line with that coating seems to run now =
three years in 24 hours shift without problems. What we also looked at are =
upgrade kits for older equipment. I am right now writing a cost- evaluation=
.


Guenter


.

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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=========================================================================
Date:         Thu, 31 Jan 2002 09:24:50 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Julian Coates <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Julian Coates <[log in to unmask]>
Subject:      Re: ODB++
X-To:         [log in to unmask]
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Hi All,

I am from Valor, I should state that up front, but I would like to offer two
points for consideration:

1. In the mid-1980's the mainstream PCB manufacturers began to accept Gerber
(instead of film) into their tooling departments. In order to do this, they
had to make capital investments. These investments gave them a competitive
advantage, because they were able to cut costs overall, reduce lot-size due
to faster tooling cycles, and increase quality. Despite this, for many
years, the OEMs (their customers) continued to send the design to the
fabricator in two formats; Gerber, and film. The film was regarded as the
reference and ultimate specification of the design, but the fabricator could
use the Gerber if he so chose (those who could, did). What is going on now
between Gerber and ODB++ is basically the same, a transition of formats
which have uncertainties between them, and for each design somewhere down
the line somebody has to decide which format to believe in and work from. In
the case of Gerber, it took a few years for the average fabricator to have
unconditional confidence in the data rather than the film. These days, they
do not receive films at all, and they just work from the Gerber without a
second thought of what became of the film. In the case of ODB++, many
fabricators already have tools (as do the designers by the way) to compare
the graphics and netlist interconnect of the ODB++ versus the Gerber in an
automated fashion, reducing the risks substantially. The upside (as Mark
points out) is faster throughput and higher quality. The question is: who is
the beneficiary? The ultimate beneficiary of these gains is the consumer
(the designer), via the competitive business model of the
fabrication-outsourcing. From my observation, most fabricators do not
recover their actual tooling costs in the charges they make to the customers
anyway (they bury their tooling costs in their overheads), so it is probably
unrealistic to expect PCB fabricators to give tooling price-cuts to the
customers, since they are running their tooling operations at a loss
already. However, there are gains for the customer, albeit indirect: further
reduction in average delivery times, and higher quality over time; prices
are dropping anyway. To turn it around, if the designers continue to send
Gerber, the level of service received from the manufacturers could not
improve so fast as it can with a smarter interchange format.

2. Seth makes a good point about validation of ODB++ input and output
processors. Currently, ODB++ is not a formal standard, though we believe it
will be in good time (thanks to the industry-driven NEMI process). When the
formal standardization occurs, we hope that some independent
compliance-validation service will be offered by the standards-body. Just as
a side note, independent compliance-proving by an independent body never
happened (as far as I know) with Gerber RS274D, and RS274X never was a
standard anyway, the industry just went ahead and implemented the format
widely, though with considerable variation, as Seth points out. Between now
and formal standardisation of ODB++ or some further-developed version, Valor
offers a service of supporting third parties who implement ODB++, via its
3rd-party cooperation program, the "Open Systems Alliance". We do our best
to offer advice and support for interface testing to all organisations,
competitive or non-competitive, so that the format has the best chance of
practical implementation. Some 3rd-parties opt to stay away from this
service due to competitive reasons, which usually (in our view) results in
sub-standard implementation of the format, which is a pity. Those who join
get full support.

After many years of quasi-stability with Gerber, the industry is in
transition again. I do not sure that there is any clear way of accelerating
the shift to a new CAD/CAM format with price-breaks from the manufacturers
(fabrication or assembly), since they are all bleeding cash right now
anyway. The transition will happen steadily, and be driven top-down by more
subtle, but more powerful, factors such as time and quality.

I hope these comment contribute to the debate in a positive way, as
intended.

Julian Coates
Valor



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Seth Goodman
Sent: 31 January 2002 06:24
To: [log in to unmask]
Subject: Re: [TN] ODB++


Hi Mark,

> I assume you are comfortable with your system outputting
> gerber, it's ODB that has to "prove" it can duplicate the
> gerber.

Thanks for bringing this up.  I'm not suggesting that ODB++ needs to prove
itself, as its' market share among fab shops tells me that it does the job.
Given the choice, I would also opt for ODB++ as it can carry a lot more than
just bare board information.  The problem I have is in archiving any data
object in more than one format for the reasons explained below.


> Here's what I have in mind, an experiment. You asked the
> question "The problem is how do you insure that both sets
> of output data are identical in every way?" Maybe one way
> to test that is to test the input and output capabilities
> of Genesis/Enterprise.

This will test, for one particular data set, the ability of the Valor tool
to translate back and forth between Gerber and ODB++ without accumulating
error.  It really shows that their forward and reverse translators are
accurate inverses of each other.  It doesn't show that the two data files
produce the same board.  Even if we made a test to show that these two data
files were comparable, not very many designers use Valor tools to make their
output files.  Instead, we typically use the data file generators built into
our CAD systems.  If the CAD system doesn't produce ODB++ directly, and most
don't, then we use a third party tool (I use CAM350) to translate into
ODB++, either from the native CAD file or from Gerbers.

Even if the original CAD tool produced both output formats, the problem
remains.  Producing an output file, either Gerber or ODB++, from a native
CAD database is a translation process.  It is more difficult, though
fundamentally similar to translating Gerber into ODB++.  In both cases, some
program looks at a series of data objects and translates them into another
series of data objects of a different format.  That program is written by
human beings and therefore it has bugs.  I have yet to own a piece of
bug-free software.  The software that produces ODB++ is not the same as the
software that produces Gerber.  It most likely has different bugs.  My point
is that the two output files will not be exactly the same.

I know from experience that there are flaws in the Gerber data generators in
most CAD programs.  The nastier ones are history but some subtle ones
remain.  Similarly, different Gerber viewers can display the same data file
differently.  Occasionally, I have to spend a lot of time working with a fab
shop because their Gerber viewers and my Gerber viewers show different
results from the same data.  This is an unfortunate waste of both my time
and theirs, but it has to be done.  Because we don't use the same brand and
version of software, it is unavoidable.

What I want to avoid is dealing with problems in ODB++ data in addition to
Gerber data.  Also, consider that if ODB++ becomes the Gerber replacement,
there will be companies other than Valor writing software for it.  That
means there will be some differences between how a Valor program and someone
else's program interprets the same ODB++ data.  This may not come up very
often, but it will come up, especially when other vendors first start using
ODB++.  Unless Valor achieves a 100% market share, we will all have to deal
with some subtle differences between vendors' software.  This problem could
be lessened if an independent industry group produced a validation suite
that a program would have to pass to call itself ODB++ compliant.

I would be happy to support ODB++ as the single output format for any given
board.  In fact, I would prefer almost any intelligent data format to
Gerber, which is truly a rotten old standard.  But until my customers'
purchasing departments will accept ODB++ only, the only "universal" option
today is Gerber.  Until ODB++ becomes as universally accepted by fab shops
as Gerber, or the fab shops start to give a big enough discount to offset
the extra costs of supporting two data formats, IMO most designers will opt
to stay with Gerber.  If using ODB++ really saves the fab shops money, and
I'm sure it does, all they have to do is pass some of those savings on to
their customers who use it and it will become the de facto standard before
you know it.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966

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=========================================================================
Date:         Thu, 31 Jan 2002 05:40:32 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Julian Coates <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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Hi Julian,

You make some very good points and I hope that ODB++, or something very much
like it eventually replaces Gerber.  Your arguments aren't specific to
Valor, so that's not an issue at all.  I'd like to mention a couple of areas
where we view things a little differently.

In comparing the previous transition from film to Gerber to the imminent
transition from Gerber to an intelligent format, the analogy is not as
strong as you imply.  In the transition from film to Gerber, there were
rarely any differences between the two, at least once people learned how to
take care of their photoplotters.  This is not surprising, since the early
photoplotters came from the same company that wrote the standard!  Even so,
the engineering groups I ran during that period only archived one format of
data.  When we changed over from film to Gerber, only the Gerbers were
archived.  We added the additional process step, as did many groups back
then, of approving the film plots from the board vendor.  This was not to
check for improper interpretation of the Gerber data by the photoplotter, it
was to check that the Gerber data represented the native CAD data properly.
For us, these approval films were really check plots that verified the
Gerber generator in the CAD software.  Many board vendors required the
customer to approve the films before fabrication anyway.  If I recall
correctly, it was a number of years before affordable Gerber viewers
appeared.  After using those for a while, the vendors no longer required our
sign-off on films and we were confident enough to not require it either.

The coming transition is a bit more dicey.  We're talking about changing
from a simple, dumb format to a complex hierarchical one.  The complexity of
the software to generate and read this new format is much higher than for
Gerber.  We can therefore expect more software problems than with the
previous transition.  I would like to know what are the tools many designers
currently have, that you mentioned, to compare Gerber and ODB++.  If they're
affordable, I'd like to try them out.  Obviously the fabricators can do this
task but their software costs more than most CAD packages we use to design
the boards, so that is a barrier.

While we could also use high-end CAM software to improve our design quality
by eliminating slivers, acid traps, etc., the situation is the same as I
mentioned before:  the board vendors already do this for us and are not
offering reduced prices if we take on that part of the job.  The end-product
quality is the same, it's just a question of who does the work.  Likewise,
they are not offering improved turnaround times.  They are not even telling
us they are considering such policies.  This is a very tough sell to top
management who want to know how much it will pay back and when.

Remember that when we switched from film to Gerber, many fabrication shops
bought their own photoplotters and quickly reduced or eliminated
photoplotting charges.  The company I worked for at the time was able to
junk our photoplotter and darkroom, reclaim the space they occupied and put
the operator to better use as a PCB layout person.  Similarly, when we
stopped requiring sign-off on films, our turnaround times improved
instantly.  If an investment of time and money today won't lower our board
prices, shorten the turnaround time or improve quality, it would be more
accurate to call it a donation.

I'm still very much in favor of adopting an intelligent data format.  But it
has to be driven by economics.  The return has to be at least in the
foreseeable future.  The fab shops are apparently not yet able to make it
profitable for us to make the change.  Hopefully, that situation will
change.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966


> -----Original Message-----
> From: Julian Coates [mailto:[log in to unmask]]
> Sent: Thursday, January 31, 2002 3:25 AM
> To: [log in to unmask]; [log in to unmask]
> Subject: RE: [TN] ODB++
>
>
> Hi All,
>
> I am from Valor, I should state that up front, but I would like
> to offer two
> points for consideration:
>
> 1. In the mid-1980's the mainstream PCB manufacturers began to
> accept Gerber
> (instead of film) into their tooling departments. In order to do
> this, they
> had to make capital investments. These investments gave them a competitive
> advantage, because they were able to cut costs overall, reduce
> lot-size due
> to faster tooling cycles, and increase quality. Despite this, for many
> years, the OEMs (their customers) continued to send the design to the
> fabricator in two formats; Gerber, and film. The film was regarded as the
> reference and ultimate specification of the design, but the
> fabricator could
> use the Gerber if he so chose (those who could, did). What is going on now
> between Gerber and ODB++ is basically the same, a transition of formats
> which have uncertainties between them, and for each design somewhere down
> the line somebody has to decide which format to believe in and
> work from. In
> the case of Gerber, it took a few years for the average fabricator to have
> unconditional confidence in the data rather than the film. These
> days, they
> do not receive films at all, and they just work from the Gerber without a
> second thought of what became of the film. In the case of ODB++, many
> fabricators already have tools (as do the designers by the way) to compare
> the graphics and netlist interconnect of the ODB++ versus the Gerber in an
> automated fashion, reducing the risks substantially. The upside (as Mark
> points out) is faster throughput and higher quality. The question
> is: who is
> the beneficiary? The ultimate beneficiary of these gains is the consumer
> (the designer), via the competitive business model of the
> fabrication-outsourcing. From my observation, most fabricators do not
> recover their actual tooling costs in the charges they make to
> the customers
> anyway (they bury their tooling costs in their overheads), so it
> is probably
> unrealistic to expect PCB fabricators to give tooling price-cuts to the
> customers, since they are running their tooling operations at a loss
> already. However, there are gains for the customer, albeit
> indirect: further
> reduction in average delivery times, and higher quality over time; prices
> are dropping anyway. To turn it around, if the designers continue to send
> Gerber, the level of service received from the manufacturers could not
> improve so fast as it can with a smarter interchange format.
>
> 2. Seth makes a good point about validation of ODB++ input and output
> processors. Currently, ODB++ is not a formal standard, though we
> believe it
> will be in good time (thanks to the industry-driven NEMI
> process). When the
> formal standardization occurs, we hope that some independent
> compliance-validation service will be offered by the
> standards-body. Just as
> a side note, independent compliance-proving by an independent body never
> happened (as far as I know) with Gerber RS274D, and RS274X never was a
> standard anyway, the industry just went ahead and implemented the format
> widely, though with considerable variation, as Seth points out.
> Between now
> and formal standardisation of ODB++ or some further-developed
> version, Valor
> offers a service of supporting third parties who implement ODB++, via its
> 3rd-party cooperation program, the "Open Systems Alliance". We do our best
> to offer advice and support for interface testing to all organisations,
> competitive or non-competitive, so that the format has the best chance of
> practical implementation. Some 3rd-parties opt to stay away from this
> service due to competitive reasons, which usually (in our view) results in
> sub-standard implementation of the format, which is a pity. Those who join
> get full support.
>
> After many years of quasi-stability with Gerber, the industry is in
> transition again. I do not sure that there is any clear way of
> accelerating
> the shift to a new CAD/CAM format with price-breaks from the manufacturers
> (fabrication or assembly), since they are all bleeding cash right now
> anyway. The transition will happen steadily, and be driven
> top-down by more
> subtle, but more powerful, factors such as time and quality.
>
> I hope these comment contribute to the debate in a positive way, as
> intended.
>
> Julian Coates
> Valor

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Date:         Thu, 31 Jan 2002 10:46:07 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Peter Swanson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Peter Swanson <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Doug,

I believe that some suppliers of this kind of equipment have dealt
successfully with this issue (conductive media, ionisation, etc). See
http://www.ccrco.com, for example.

Regards,
Peter
--
=========================================================
Peter Swanson            [log in to unmask]
INTERTRONICS                http://www.intertronics.co.uk

INTERTRONICS is dedicated to providing quality material,
  consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
   the highest levels of technical support and customer
                         service.


-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: 30 January 2002 21:27
To: [log in to unmask]
Subject: Re: [TN] Conformal Coating


Mike Sewell Suggests:   Would microabrasive blasting of the coating be an
alternative to chemical stripping?

*Just be aware that microabrasive blasting generates a hell of a static
charge.  Enough to kill a static sensitive component.  I think the EMPF did
some work in microabrasion methods relative to ESD in the late 80s early
90s.  Check with the librarian at www.empf.org.

Doug Pauls
Rockwell Collins

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Date:         Thu, 31 Jan 2002 07:18:28 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      CERAMIC CSP'S and a MoonMan adventure out of the cave again

Folks,

I have been reviewing all the issues/problems that were faced by my host
company and its supplier ? before I arrived. I would like to share some for
comment as well as my observations, if you would be so kind.

We have one board design using seven .8 mm ceramic CSP?s made by TI. The
first issue facing my company was cracking or separation of balls from the
device. I have reports from Rockwell, who did the F/A and from TI both
pointing to the failure mechanism as possible excessive IMC formation as in
the following without the photos, of course:

Attached are four photos:

CSP-1 shows multiple insertions into sockets.
CSP-2 shows x-section of stock unit
CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
appears thick.
CSP-4 shows x-section of device which broke off the PCB - clean break at the
intermetallic layer.

Because of the multiple insertions into sockets, as evidenced by
indentations on the balls, it is considered that multiple thermal excursions
contributed to IMC growth. As the clean break occurred at the IMC interface,
again, this is thought to be the failure mechanism. This may be so, but
other things must be considered as well.

This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
no repeat of this occurrence. No reason is available to me, at least,
concerning the part?s improvement. No matter, there now exist other issues.

I believe, as in a few comment trades, with others (Dave Fish for one), that
our assembler?s inexperience profiling and soldering these devices has been
responsible for poor quality/reliability solder joints. In their defense,
there aren?t/weren?t many suppliers with this experience. Simply, cold
solder joints probably contributed to unacceptability and complete failure
as received ? evidenced by the infamous "C" clamp. The ceramic portion of
the device is extremely massive compared to ball size and the ability to get
required heat to the solder medium and balls to effect acceptable solder
joints. This means, I believe based on past experience, the reflow profile
must be "maxed" out in terms of solder paste performance and joint
formation. I don?t think this was done.

To add to the situation, the CTE mis-match of ceramic and PCB material
certainly has been known to ruin even good solder joints. This may account
to the failure at the IMC interface as well as at the board level.
Therefore, a "too thick" IMC layer probably is/was not the failure
mechanism, or was it?

All solder pads have been re-evaluated and now definitely meet alignment and
size requirements. Stencil apertures are as specified. Solder paste now is
Kester?s 562R, solder volume is acceptable, surface solderability is as
required. What remains is developing a solder reflow profile that will
effect acceptable solder joints for the CSP?s as well as all other devices
on the board.

I realize this should not be a big issue, but having had to go way back to
visit initial failures at the device ball interface, I have some concerns
about whoever builds our next lot of boards. Steve, are you listening.

I would appreciate any comments concerning this small part of the picture. I
would appreciate anyone sharing experiences with what should be another BGA
success story but for what I have presented here.

Thank you all much,

Earl

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Date:         Thu, 31 Jan 2002 08:34:11 -0500
Reply-To:     "[log in to unmask]" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gerard O'Brien <[log in to unmask]>
Organization: Photocircuits Corporation
Subject:      Re: ENIG Thickness Standard?
X-To:         "[log in to unmask]" <[log in to unmask]>

As co-chairman of the 4552 committee, I must take exception to your
comment"  It does not contain a
lot of useful detail". For this specification extensive testing was
performed and data presented , paper appeared in the last issue of IPC
review as well as in the Orlando fall conference. The specification for
ENIG is 2 micro inches minimum Au at  -4 sigma from the mean  and 120 to
240 microinches for the nickel. As a point of note, I tested two days ago
samples from two of the five vendors that supplied samples for wetting
balance testing that were used to generate this specification. The samples
are now 14 months old (they have been lying around my office not protected)
and for the test we had them plated with 1 microinch of gold. THEY STILL
SOLDER AND PASS ALL WETTING BALANCE CRITERIA!!! The degree of porosity at 1
microinch is obviously greater than at 5 microinches however the protection
afforded the underlying nickel is still excellent, solderability testing
was with a ROL0 type flux per j-std 004.
It is intention of the 4552 committee to publish the total data set as a TR
report.
If anyone would like a copy of testing specifics or a copy of a specific
test data set - XRF , wetting balance, contact resistance , please feel
free to contact myself, George Milad -chairman of the committee or Tom
Newton at the IPC
Regards
Gerard O'Brien
Photocircuits Corp.

-----Original Message-----
From:   [log in to unmask] [SMTP:[log in to unmask]]
Sent:   Wednesday, January 30, 2002 10:04 PM
To:     [log in to unmask]
Subject:        Re: [TN] ENIG Thickness Standard?

Rick,

I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.

Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.

Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.

Peter




                    Rick Thompson
                    <rthompson@VENTURAELECTR        To:     [log in to unmask]
                    ONICS.COM>                      cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    Sent by: TechNet                Aero/ST Group)
                    <[log in to unmask]>               Subject:     [TN] ENIG
Thickness Standard?


                    01/31/02 08:36 AM
                    Please respond to
                    "TechNet E-Mail Forum.";
                    Please respond to Rick
                    Thompson






Is there a standard for the plating thickness of the ENIG surface
finish?  I've searched the archives and didn't find anything.  Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches.  What (if anything) is considered standard for this finish?

Thanks for your inputs.


Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Thu, 31 Jan 2002 08:43:14 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marion A. Graybeal" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marion A. Graybeal" <[log in to unmask]>
Subject:      Re: ENIG Thickness Standard?
X-To:         Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Rick,

The IPC spec for ENIG, which is near release, specifies 120-240
microinches of Ni and 2-4 microinches of Au.

Marion Graybeal


----- Original Message -----
From: Rick Thompson <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 7:36 PM
Subject: [TN] ENIG Thickness Standard?


> Is there a standard for the plating thickness of the ENIG surface
> finish?  I've searched the archives and didn't find anything.  Based on
> a customer request we had increased the requirement for the electroless
> nickel to 200u inches. A couple of our board vendors are telling me that
> that is excessive and that anything over 100u inches is overkill. I've
> seen references in the archives for anything from 120u inches to 200u
> inches.  What (if anything) is considered standard for this finish?
>
> Thanks for your inputs.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858   x-304  voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
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>

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Date:         Thu, 31 Jan 2002 08:49:34 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ODB++    ... or GenCAM?
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_a9.22238cfe.298aa56e_boundary"

--part1_a9.22238cfe.298aa56e_boundary
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Good day to all,

It seems that IPC GenCAM is missing from this discussion. 25 years or so of
group effort to develop a generic industry standard sitting on the sidelines
in this dialog.

The following is taken from the forum sponsors website

"...Establishes the capability for a single ANSI STD datafile format to
transfer data to all disciplines in the PCB supply chain.

...Provides for complete transfer of test data and electrical test parameters.

...Can accommodate several BOM descriptions in a single data file.

...Brings your design into close contact with DFM issues."

Has anyone taken it for a lap? Is (are) there a reason(s) for its absence in
this dialog?

Best to all,
Joe

--part1_a9.22238cfe.298aa56e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Good day to all,
<BR>
<BR>It seems that IPC GenCAM is missing from this discussion. 25 years or so of group effort to develop a generic industry standard sitting on the sidelines in this dialog.
<BR>
<BR>The following is taken from the forum sponsors website
<BR>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0">"...Establishes the capability for a single ANSI STD datafile format to transfer data to all disciplines in the PCB supply chain.
<BR>
<BR>...Provides for complete transfer of test data and electrical test parameters.
<BR>
<BR>...Can accommodate several BOM descriptions in a single data file.
<BR>
<BR>...Brings your design into close contact with DFM issues."
<BR>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Has anyone taken it for a lap? Is (are) there a reason(s) for its absence in this dialog? </FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0">&nbsp;
<BR>
<BR>Best to all,
<BR>Joe</FONT></HTML>

--part1_a9.22238cfe.298aa56e_boundary--

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Date:         Thu, 31 Jan 2002 08:19:28 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kathy Kuhlow <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: AOI Stuff again...
Mime-Version: 1.0
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This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_CE93A691.9BFA979C
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I work for a CM with high mix low runs.  We use an AOI right now.  I find =
that one aspect of AOI that has really reduced labor was the first article =
process for component id and placement.  We spend a lot of labor for the =
first board to confirm correct part and alignment from pick and place.  We =
also do the same process if we use a Final Inspection.  Having the machine =
to do this is much, much faster which gives a quicker set-up and run =
approvals. =20

As far as solder joints I agree the AOI leaves a lot to be desired.  It =
does good with shorts but insufficient and no solders are dependent on =
device.  Like a "J" lead or a QFP it just doesn't do well.  But non =
solders on discretes are pretty good. =20

As with most equipment made to make our lives easier and less of us needed =
it has it's limitations but what it can do it does well. =20

Kathy=20

--=_CE93A691.9BFA979C
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I work for a CM with&nbsp;high mix low runs.&nbsp; We use an AOI right
now.&nbsp; I find that one aspect of AOI that has really reduced labor was the
first article process for component id and placement.&nbsp; We spend a lot of
labor for the first board to confirm correct part and alignment from pick and
place.&nbsp; We also do the same process if we use a Final Inspection.&nbsp;
Having the machine to do this is much, much faster which gives a quicker set-up
and run approvals.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>As far as solder joints I agree the AOI leaves a lot to be desired.&nbsp;
It does good with shorts but insufficient and no solders are dependent on
device.&nbsp; Like a "J" lead or a QFP it just doesn't do well.&nbsp; But non
solders on discretes are pretty good.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>As with most equipment made to make our lives easier and less of us needed
it has it's limitations but what it can do it does well.&nbsp; </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

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Date:         Thu, 31 Jan 2002 08:27:18 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: AOI Stuff again...
X-To:         [log in to unmask]
Mime-Version: 1.0
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Aaaaah Steve,
I believe you're in the same boat I was in around two years ago. We were =
building assemblies (down-hole, oilfield & class 3 medical (implantable)) =
and we were having major quality concerns. Products were going out the =
door missing components, being damaged from rework, etc. and it would've =
been a saving grace to have AOI capabilities. Alas, it was not to be. We =
didn't have the money for such elaborate systems. Any way, I don't know =
how to answer your question. You either use your available human eyes or =
buy a machine and hope it can pay for itself. You can also request from =
customers for "golden boards", fully populated, to use for programming =
prior to build. If you need leads on good systems, here's a few:

Agilent (MVT) - Agilent bought MVT and is making a real nice system. Don't =
know much about it, just know MVT had a good system, just not enough cash =
to improve and market it broadly.

Cyberoptics - Don't know much about it. Only that it can configured either =
as a paste inspection machine or post-reflow AOI.

Orbotech - We had a few in Alabama and they're very nice, just a tad =
difficult to program.

Or you can do like me and get an Agilent 5DX and have fun immersing =
yourself in the complex task of programming (it dang sure ain't cost-effect=
ive for your needs, though).

Hope this helps

Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508  Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]

>>> [log in to unmask] 01/30/02 09:00PM >>>
Hi all!

Bringing up the topic of AOI again. Read the Glenn Woodhouse summary =
(which I
think was GREAT by the way) that Daan reposted about the state of the
technology, had a fellow engineer that I work with attend a session at =
APEX
about AOI, and it seems that things may have become a bit cheaper, but as =
far
as using AOI for solder joint evaluation, there's still much to be =
desired...

The situation here is that there is some pressure from those above to get =
a
system in here that will be a fool-proof method to put a piece of =
equipment
in place that will eliminate the need for human inspection.

My take on it is that one focuses on making sure that the process is right
from the beginning, and then you don't need to spend a bunch of money on
automated inspection equipment, or depend on humans to inspect each and =
every
solder joint.

The reason I say that is because we are a low volume, high part number =
shop.
We may have ongoing business for years, but it maybe 10 assemblies a
month...what we consider high volume is a run of 250 assemblies per work
order...hehehe.

I just have the opinion that spending the big bucks for the AOI equipment
doesn't make a whole lot of sense in our situation...we'll be tweeking
programs during the run and probably won't have all the false calls, or
missed defects ironed-out by the time the work order is built...then a =
month
or two later on the same assembly, you go through the same drill again...

Any thoughts on this?

-Steve Gregory-

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Date:         Thu, 31 Jan 2002 08:36:50 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ENIG Thickness Standard?
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Good Morning TechNet! Rick, I have a very different perspective on ENIG
than Peter so here is some food for thought. There is a specification for
ENIG  - IPC-4552 - which is in final ballot and should be release in the
March/May timeframe. I recommend getting a copy.  It's my opinion that the
specification is quite useful considering there is no other specification
available for industry use. The ASTM B488 specification is not a workable
solution for electronics applications. There was a great deal of committee
discussion on the electroless nickel plating thickness. The nickel
thickness is very much viewed as application specific, for example,  RF
designers desire minimal thickness (30-50 uinches) as opposed to connecting
applications which use 200 uinches. Rockwell Collins is successfully using
2-5 uninches for the immersion gold thickness and 50-150 uinches for the
electroless nickel thickness in avionics applications and we intend on
using the IPC-4552 specification in our documentation. Additionally, 50
uinches of electroless nickel is very adequate as a diffusion barrier as
both the nickel/copper and nickel/gold phase diagrams demonstrate a wide
range of immiscibility The only instances I have seen a 50 uinch
electroless nickel thickness not be adequate was for pwbs which were
subjected to repetitive thermal excursions (e.g. lots of rework, or 4
reflow passes). Using an immersion gold thickness of 6 uinches will not
guarantee you solderability - the 4552 committee demonstrated that (by
conducting testing) that 2 uinches of immersion gold can be steam
conditioned and still provide expected solderability coverage. Teaming with
your ENIG vendor, understanding their plating process control practices and
requiring some level of solderability testing is the best way of insuring
solderability.  Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




[log in to unmask]@ipc.org> on 01/30/2002 09:03:53 PM

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      to [log in to unmask]

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  Re: [TN] ENIG Thickness Standard?


Rick,

I went through this pain a while ago, and got a lot of tremendous help from
Ingemar Hernefjord in particular. I believe there is no released standard
for ENIG, though there is an empirical spec IPC-4552. It does not contain a
lot of useful detail, though. I specify 5 microinches (0.12 microns) of
Gold over minimum 235 microinches (6 microns) Nickel for my boards, after
reading a number of studies and failure reports. In fact I was recommended
to use 250 microinches of Nickel, but this would have made our boards too
thick. The thicker gold layer minimises porosity and therefore oxidation to
the underlying Nickel layer.

Older thinking was for around 100 to 120 microinches Nickel, but studies by
Eriksson and others concluded that with the growth of gold flashing through
the Nickel from one side and Cu/Ni intermetallics on the other side of the
plating, that a thicker Nickel layer would offer the boards a longer
solderability shelf life and greater solder joint reliability.

Hope this helps a bit. Certainly, I haven't experienced any problems with
soldering or mounting of components on boards to this spec.

Peter




                    Rick Thompson
                    <rthompson@VENTURAELECTR        To:     [log in to unmask]
                    ONICS.COM>                      cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    Sent by: TechNet                Aero/ST Group)
                    <[log in to unmask]>               Subject:     [TN] ENIG
Thickness Standard?


                    01/31/02 08:36 AM
                    Please respond to
                    "TechNet E-Mail Forum.";
                    Please respond to Rick
                    Thompson






Is there a standard for the plating thickness of the ENIG surface
finish?  I've searched the archives and didn't find anything.  Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches.  What (if anything) is considered standard for this finish?

Thanks for your inputs.


Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Thu, 31 Jan 2002 08:49:20 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Antw: [TN] Wave Solder/NoPb Question
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Hi Guenter! Great information! One additional question - do you know if
the molten tin attack is more severe on base stainless steel alloys such as
the 301-304 alloy series or are the microalloyed 316/321/347 alloy series
equally attacked? Also, I have always made the assumption that titanium
with its tough natural oxide would be pretty immune to molten tin attack
but don't have any experience or data to back that up. I know that some of
the equipment vendors use titanium in the wave equipment but haven't seen
any information of molten tin attack.

Dave




Guenter Grossmann <[log in to unmask]>@ipc.org> on 01/31/2002
02:15:53 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
      to Guenter Grossmann <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] Antw: [TN] Wave Solder/NoPb Question


Dave

We run trials with folks from ERSA. Actually, due to their knowledge,
erosion of the solderpot, the wave-nozzle, and the pump are considerable.
However, new equipment seem to be produced lead-free save with coated
stainless steel. It seems also as if it is possible to cover the parts in
danger with a organic coating (paint) which can be done during the downtime
when a service is done. The coating needs a refreshment every one or two
years I heard though one line with that coating seems to run now three
years in 24 hours shift without problems. What we also looked at are
upgrade kits for older equipment. I am right now writing a cost-
evaluation.


Guenter


.

EMPA
Swiss Federal Institute for Materials Testing and Research
Centre for Reliability
Dipl. Eng. Guenter Grossmann

8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :     xx41 1823 4054
mail:     [log in to unmask]

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Date:         Thu, 31 Jan 2002 15:13:43 -0000
Reply-To:     Dougal Stewart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dougal Stewart <[log in to unmask]>
Subject:      Re: pulse plating - without additives
X-To:         Adam Seychell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I don't know whether this is a cynical remark (as if), but none of the
chemistry suppliers have ever promoted pulse plating with copper without
additives. In all the years I have had experience with acid copper pulse
plating (and Exacta led the way) it has been notable that simpler forms of
plating chemistry (ie with carrier and brightener, but NO leveller) worked
best. I have had long discussions with Jack Josefowicz from Tyco on the
subject, and I would suggest that he would be an authority on whether it is
possible.
Dougal Stewart

email:  [log in to unmask]
phone: +44 1896 822204
mob:    +44 7984 629667
----- Original Message -----
From: "Adam Seychell" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, January 30, 2002 8:09 AM
Subject: [TN] pulse plating - without additives


> Hello platers.  I am hoping someone here can share a few words
> of wisdom about reverse pulse plating. I'm having difficulty
> finding detailed information on the subject, as my local university
> library showed to carry almost nothing. It seems  that the
> literature on reverse pulse plating is bound to research papers
> only (which I latter learned can be quite costly and time
> consuming to obtain). What I like to know is a method of plating
> "standard" printed circuit boards in acid copper bath *without*
> the use of additives. Pulse plating without additives has been
> done or so I've been told, however most documents I have
> read only talk about baths containing additives.
>
> Normally, a pure DC in acid copper (200 g/l H2SO4, 20 g/l Cu)
> would produce a rough and grainy deposit, especially when
> thickness' become high ( >35 um). The problem is aggravated by
>  increasing current density. Even at current densities of
> 0.5A/dm2 the deposits still remain unacceptable. This is
> something I have observed through experimentation.
>
> A test panel was plated using reverse pulse technique to see
> what effect it had compared to DC plating at an equivalent
> average current density. Not having a proper pulse plating power
> supply I constructed my own basic one, using standard DC supply
> and an electronic circuit to periodically reverse the output. The
> parameters of the plating were:
>
> forward time = 5 ms
> reverse time = 1.7 ms
> forward & reverse current densities = 3 A/dm2
> average current density = 1.5 A/dm2
>
> The pulse plating deposits were only slightly improved over DC
> plating. A rough and crystalline surface was clearly visible under a
> 40X microscope. This does not sound promising and I am hoping
> this is due to incorrect characteristics of the current pulse. Most
> reverse pulse plating systems tend to use forward/reverse current
> ratios of around 3, forward times of 10~20ms and reverse times
> 1~2ms. Is important for the current reverse pulse to be short and
> high ?
>
> If anyone could guide me to right path I'd be greatly thankful. If
> there is no such thing as additive free copper plating for PC
> fabrication then kindly let me know as this could save me lot of
> time doing what others have already attempted.
>
> regards,
>
> Adam Seychell.
>
> --------------------------------------------------------------------------
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Date:         Thu, 31 Jan 2002 07:19:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Thompson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject:      Re: AOI Stuff again...
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Steve,

We've been using AOI in a similar environment for about 18 months. While
there is a somewhat constant 'tweaking' effort adjusting for part and
vendor changes, we still have found it more efficient than simply doing
visual inspection. Stepping through and adjusting for false calls and
changes is still significantly faster than visual inspection as well as
being more consistent.  Yes, process control is the obvious way to go,
but stuff happens <g>.  We've seen a significant decrease in customer
return rates since putting it in place.  With the data collection, it
also allows us to pinpoint specific problem areas and address them on
the line, thus improving overall yield.

That said, it did not allow us to eliminate an inspector. For one thing,
you need someone to run the machine and maintain programs.  There's also
the defect classes that aren't readily detectable in AOI. Solder
inspection is still a very 'iffy' area in my opinion. Despite
manufacturer's claims, I haven't seen any solder inspection that's
really effective.  I know there are some vector based systems that
supposedly increase the ability to define and inspect solder joints but
there are so many areas that are difficult or impossible to view
adequately that solder inspection with the AOI systems I've seen is a
hit or miss proposition.  What we have found is that certain types of
solder inspection is useful for verifying product.  The main thing is
that it has allowed our inspectors to concentrate on the areas that
aren't inspectable with AOI, like through-hole parts, connectors, etc.

Regards,

Rick Thompson


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of [log in to unmask]
Sent: Wednesday, January 30, 2002 7:00 PM
To: [log in to unmask]
Subject: [TN] AOI Stuff again...


Hi all!

Bringing up the topic of AOI again. Read the Glenn Woodhouse summary
(which I think was GREAT by the way) that Daan reposted about the state
of the technology, had a fellow engineer that I work with attend a
session at APEX about AOI, and it seems that things may have become a
bit cheaper, but as far as using AOI for solder joint evaluation,
there's still much to be desired...

The situation here is that there is some pressure from those above to
get a system in here that will be a fool-proof method to put a piece of
equipment in place that will eliminate the need for human inspection.

My take on it is that one focuses on making sure that the process is
right from the beginning, and then you don't need to spend a bunch of
money on automated inspection equipment, or depend on humans to inspect
each and every solder joint.

The reason I say that is because we are a low volume, high part number
shop. We may have ongoing business for years, but it maybe 10 assemblies
a month...what we consider high volume is a run of 250 assemblies per
work order...hehehe.

I just have the opinion that spending the big bucks for the AOI
equipment doesn't make a whole lot of sense in our situation...we'll be
tweeking programs during the run and probably won't have all the false
calls, or missed defects ironed-out by the time the work order is
built...then a month or two later on the same assembly, you go through
the same drill again...

Any thoughts on this?

-Steve Gregory-

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Date:         Thu, 31 Jan 2002 08:35:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Denis Lefebvre <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Denis Lefebvre <[log in to unmask]>
Subject:      Re: ODB++  or GenCAM or IPC-350?
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: multipart/alternative;
              boundary="=====================_266668889==_.ALT"

--=====================_266668889==_.ALT
Content-Type: text/plain; charset="us-ascii"; format=flowed

 From a designers point of view:

Even before the advent of GENCAM was IPC's effort with IPC-350. In fact,
that is where CAM350 got it's name. The original intent of that application
was to output the "new" industry standard data format, IPC-350. This later
gave way to GENCAM which has now stepped aside (or- been pushed aside) for
ODB++.

The impetus to develop an industry standard data exchange format has been
around for over a decade.

So, what is standing the way? EDA software companies!

Imagine the convenience designers would experience if there was a data
format that could be easily exchanged between design platforms! Good God,
could this have any effect on market share? I think not.. but I believe
that is the fear held by the EDA vendors. It will surely be a cold day when
a standard data format will be supported by vendors of PCB design
applications. I am convinced this function will continue to be relegated to
applications that are in the CAM arena and will remain a post-processing
function for the designer.

The objectives Joe listed below were shared by the IPC-350 effort as well.

Denis Lefebvre, C.I.D.
Senior PCB Designer
Finisar Corporation
(408)542-3832
http://www.finisar.com

At 08:49 AM 1/31/2002 -0500, you wrote:
>Good day to all,
>
>It seems that IPC GenCAM is missing from this discussion. 25 years or so
>of group effort to develop a generic industry standard sitting on the
>sidelines in this dialog.
>
>The following is taken from the forum sponsors website
>
>"...Establishes the capability for a single ANSI STD datafile format to
>transfer data to all disciplines in the PCB supply chain.
>
>...Provides for complete transfer of test data and electrical test
>parameters.
>
>...Can accommodate several BOM descriptions in a single data file.
>
>...Brings your design into close contact with DFM issues."
>
>Has anyone taken it for a lap? Is (are) there a reason(s) for its absence
>in this dialog?
>
>Best to all,
>Joe

--=====================_266668889==_.ALT
Content-Type: text/html; charset="us-ascii"

<html>
 From a designers point of view:<br><br>
Even before the advent of GENCAM was IPC's effort with IPC-350. In fact,
that is where CAM350 got it's name. The original intent of that
application was to output the &quot;new&quot; industry standard data
format, IPC-350. This later gave way to GENCAM which has now stepped
aside (or- been pushed aside) for ODB++. <br><br>
The impetus to develop an industry standard data exchange format has been
around for over a decade. <br><br>
So, what is standing the way? EDA software companies! <br><br>
Imagine the convenience designers would experience if there was a data
format that could be easily exchanged between design platforms! Good God,
could this have any effect on market share? I think not.. but I believe
that is the fear held by the EDA vendors. It will surely be a cold day
when a standard data format will be supported by vendors of PCB design
applications. I am convinced this function will continue to be relegated
to applications that are in the CAM arena and will remain a
post-processing function for the designer. <br><br>
The objectives Joe listed below were shared by the IPC-350 effort as
well.<br><br>
<font face="arial">Denis Lefebvre, C.I.D.<br>
Senior PCB Designer<br>
Finisar Corporation<br>
(408)542-3832<br>
<a href="http://www.finisar.com/" eudora="autourl">http://www.finisar.com<br><br>
</a></font>At 08:49 AM 1/31/2002 -0500, you wrote:<br>
<blockquote type=cite class=cite cite><font face="Arial, Helvetica" size=2>Good
day to all, <br><br>
It seems that IPC GenCAM is missing from this discussion. 25 years or so
of group effort to develop a generic industry standard sitting on the
sidelines in this dialog. <br><br>
The following is taken from the forum sponsors website <br><br>
</font>&quot;...Establishes the capability for a single ANSI STD datafile
format to transfer data to all disciplines in the PCB supply chain.
<br><br>
...Provides for complete transfer of test data and electrical test
parameters. <br><br>
...Can accommodate several BOM descriptions in a single data file.
<br><br>
...Brings your design into close contact with DFM issues.&quot;
<br><br>
<font face="Arial, Helvetica" size=2>Has anyone taken it for a lap? Is
(are) there a reason(s) for its absence in this dialog? </font>&nbsp;
<br><br>
Best to all, <br>
Joe<font face="arial"> </font></blockquote></html>

--=====================_266668889==_.ALT--

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Date:         Thu, 31 Jan 2002 08:19:56 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ahne Oosterhof <[log in to unmask]>
Subject:      Re: ODB++
X-cc:         Jim <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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Yikes, sorry, wrong button pushed and there went an unfinished
-mail  ------------

Following is a more finished one:

I have been trying to follow the development of new data standards in this
industry. I have listened to the various interested parties make very
interesting claims about the goodness of their products. But at the moment I
hope that the GenCAM type effort is going to win. Even though I have no
reason to wish that Gerber would go away.

The nice things about Gerber are that it is a very simple standard and I can
read and understand the file. Therefore I can check the content of a file
and fix problems with the data. And I have not yet come across images that
cannot be represented by Gerber data.
The unpleasant things that have happened with Gerber is, that there are
always software designers who can and will "improve" things. And now their
"Gerber-like" output cannot be read by input devices that fully comply with
the Gerber Standard.
Then there are software engineers who design input devices and decide that
certain features and rules in the standard are superfluous and exclude those
from their package. The result is of course that their product at times does
not show results that were in the original fully complying data.

With more complex data standards it is hard to believe that these problems
are going away or are going to be easier to deal with. And the reason that I
lean towards GenCAM is that the effort to develop that standard includes
compliance checkers to help users determine that their output or input files
do indeed comply with the standard. The data format is readable so it is
easier to check what is inside the file and there is intent to assure that
all future versions are backwards compatible. So when I store data I don't
have to store interpreters to go with that specific data.

Next question: when is it going to be ready and is it going to be accepted
widely?

And of course a disadvantage of these new all-encompassing data files is
that I only need the layers that have the information needed to make a
stencil and I don't need (and I really don't want) 25Mbyte of data,
including the information on what parts to buy where and how to build and
test the board. We already have received files that include the little note:
Please destroy files after delivery of stencil !!!

Have fun,

Ahne.
A-Laser, Inc.




* I assume you are comfortable with your system outputting gerber, ---

I would also opt for ODB++ as it can carry a lot more than just bare board
information. ---

The problem I have is in archiving any data object in more than one
ormat  ---

how do you insure that both sets of output data are identical in every
way? ---

If the CAD system doesn't produce ODB++ directly, and most don't ----

we use a third party tool (I use CAM350) to translate into ODB++, either
from the native CAD file or from Gerbers. ---

Producing an output file, either Gerber or ODB++, from a native CAD database
is a translation process. ---

I have yet to own a piece of bug-free software. ---

I know from experience that there are flaws in the Gerber data generators in
most CAD programs. ---

Similarly, different Gerber viewers can display the same data file
differently. ---

if an independent industry group produced a validation suite that a program
would have to pass to call itself ODB++ compliant. ---

Gerber, which is truly a rotten old standard. ---

Until ODB++ becomes as universally accepted by fab shops as Gerber ---

Regards,

From Seth Goodman's e-mail.

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Date:         Thu, 31 Jan 2002 10:54:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jeff Ferry <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Ferry <[log in to unmask]>
Subject:      BGA Rework Using Paste vs. No Paste

Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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Date:         Thu, 31 Jan 2002 12:08:48 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: CERAMIC CSP'S and a MoonMan adventure out of the cave again
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_8.2088dbdb.298ad420_boundary"

--part1_8.2088dbdb.298ad420_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hey Everybody!

I've got Earls pictures up on my web page. Go to:

http://www.stevezeva.homestead.com/

Yes, Earl I'm not only listening, but taking notes as well...

-Steve Gregory-


> Folks,
>
> I have been reviewing all the issues/problems that were faced by my host
> company and its supplier ? before I arrived. I would like to share some for
> comment as well as my observations, if you would be so kind.
>
> We have one board design using seven .8 mm ceramic CSP?s made by TI. The
> first issue facing my company was cracking or separation of balls from the
> device. I have reports from Rockwell, who did the F/A and from TI both
> pointing to the failure mechanism as possible excessive IMC formation as in
> the following without the photos, of course:
>
> Attached are four photos:
>
> CSP-1 shows multiple insertions into sockets.
> CSP-2 shows x-section of stock unit
> CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
> appears thick.
> CSP-4 shows x-section of device which broke off the PCB - clean break at the
> intermetallic layer.
>
> Because of the multiple insertions into sockets, as evidenced by
> indentations on the balls, it is considered that multiple thermal excursions
> contributed to IMC growth. As the clean break occurred at the IMC interface,
> again, this is thought to be the failure mechanism. This may be so, but
> other things must be considered as well.
>
> This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
> no repeat of this occurrence. No reason is available to me, at least,
> concerning the part?s improvement. No matter, there now exist other issues.
>
> I believe, as in a few comment trades, with others (Dave Fish for one), that
> our assembler?s inexperience profiling and soldering these devices has been
> responsible for poor quality/reliability solder joints. In their defense,
> there aren?t/weren?t many suppliers with this experience. Simply, cold
> solder joints probably contributed to unacceptability and complete failure
> as received ? evidenced by the infamous "C" clamp. The ceramic portion of
> the device is extremely massive compared to ball size and the ability to get
> required heat to the solder medium and balls to effect acceptable solder
> joints. This means, I believe based on past experience, the reflow profile
> must be "maxed" out in terms of solder paste performance and joint
> formation. I don?t think this was done.
>
> To add to the situation, the CTE mis-match of ceramic and PCB material
> certainly has been known to ruin even good solder joints. This may account
> to the failure at the IMC interface as well as at the board level.
> Therefore, a "too thick" IMC layer probably is/was not the failure
> mechanism, or was it?
>
> All solder pads have been re-evaluated and now definitely meet alignment and
> size requirements. Stencil apertures are as specified. Solder paste now is
> Kester?s 562R, solder volume is acceptable, surface solderability is as
> required. What remains is developing a solder reflow profile that will
> effect acceptable solder joints for the CSP?s as well as all other devices
> on the board.
>
> I realize this should not be a big issue, but having had to go way back to
> visit initial failures at the device ball interface, I have some concerns
> about whoever builds our next lot of boards. Steve, are you listening.
>
> I would appreciate any comments concerning this small part of the picture. I
> would appreciate anyone sharing experiences with what should be another BGA
> success story but for what I have presented here.
>
> Thank you all much,
>
> Earl
>



--part1_8.2088dbdb.298ad420_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hey Everybody!
<BR>
<BR>I've got Earls pictures up on my web page. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com/
<BR>
<BR>Yes, Earl I'm not only listening, but taking notes as well...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Folks,
<BR>
<BR>I have been reviewing all the issues/problems that were faced by my host
<BR>company and its supplier ? before I arrived. I would like to share some for
<BR>comment as well as my observations, if you would be so kind.
<BR>
<BR>We have one board design using seven .8 mm ceramic CSP?s made by TI. The
<BR>first issue facing my company was cracking or separation of balls from the
<BR>device. I have reports from Rockwell, who did the F/A and from TI both
<BR>pointing to the failure mechanism as possible excessive IMC formation as in
<BR>the following without the photos, of course:
<BR>
<BR>Attached are four photos:
<BR>
<BR>CSP-1 shows multiple insertions into sockets.
<BR>CSP-2 shows x-section of stock unit
<BR>CSP-3 shows magnified x-section of stock unit. Ni/Sn intermetallic layer
<BR>appears thick.
<BR>CSP-4 shows x-section of device which broke off the PCB - clean break at the
<BR>intermetallic layer.
<BR>
<BR>Because of the multiple insertions into sockets, as evidenced by
<BR>indentations on the balls, it is considered that multiple thermal excursions
<BR>contributed to IMC growth. As the clean break occurred at the IMC interface,
<BR>again, this is thought to be the failure mechanism. This may be so, but
<BR>other things must be considered as well.
<BR>
<BR>This issue possibly was resolved with TI?s "prototype" parts and we?ve seen
<BR>no repeat of this occurrence. No reason is available to me, at least,
<BR>concerning the part?s improvement. No matter, there now exist other issues.
<BR>
<BR>I believe, as in a few comment trades, with others (Dave Fish for one), that
<BR>our assembler?s inexperience profiling and soldering these devices has been
<BR>responsible for poor quality/reliability solder joints. In their defense,
<BR>there aren?t/weren?t many suppliers with this experience. Simply, cold
<BR>solder joints probably contributed to unacceptability and complete failure
<BR>as received ? evidenced by the infamous "C" clamp. The ceramic portion of
<BR>the device is extremely massive compared to ball size and the ability to get
<BR>required heat to the solder medium and balls to effect acceptable solder
<BR>joints. This means, I believe based on past experience, the reflow profile
<BR>must be "maxed" out in terms of solder paste performance and joint
<BR>formation. I don?t think this was done.
<BR>
<BR>To add to the situation, the CTE mis-match of ceramic and PCB material
<BR>certainly has been known to ruin even good solder joints. This may account
<BR>to the failure at the IMC interface as well as at the board level.
<BR>Therefore, a "too thick" IMC layer probably is/was not the failure
<BR>mechanism, or was it?
<BR>
<BR>All solder pads have been re-evaluated and now definitely meet alignment and
<BR>size requirements. Stencil apertures are as specified. Solder paste now is
<BR>Kester?s 562R, solder volume is acceptable, surface solderability is as
<BR>required. What remains is developing a solder reflow profile that will
<BR>effect acceptable solder joints for the CSP?s as well as all other devices
<BR>on the board.
<BR>
<BR>I realize this should not be a big issue, but having had to go way back to
<BR>visit initial failures at the device ball interface, I have some concerns
<BR>about whoever builds our next lot of boards. Steve, are you listening.
<BR>
<BR>I would appreciate any comments concerning this small part of the picture. I
<BR>would appreciate anyone sharing experiences with what should be another BGA
<BR>success story but for what I have presented here.
<BR>
<BR>Thank you all much,
<BR>
<BR>Earl
<BR></FONT><FONT  COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>

--part1_8.2088dbdb.298ad420_boundary--

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=========================================================================
Date:         Thu, 31 Jan 2002 11:12:20 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: CERAMIC CSP'S and a MoonMan adventure out of the cave again
X-To:         [log in to unmask]

Thanks for the posting of the dirty pictures. Nasty is more like it. Even
got old Werner's interest as he asked me to send them directly to him. Hell,
I sent the whole report. Can't wait to get the facts.

Also, one of our key players is using about 60 of these little muthas on a
board. Kerry McMullin is sending a profile later. Can't wait to see that as
well.

This IS turning out to be an adventure. I do love this stuff.

Earl

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Date:         Thu, 31 Jan 2002 11:15:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>

Jeff,

It's the only way to go. I've been designing, placing, reflowing and
reworking BGA's for nearly 8 years now. It took me five minutes to make the
discovery and, as I've said far too often, I'd use flux only on initial
production if feasible.

Regards and respect,

Earl Moon

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Date:         Thu, 31 Jan 2002 09:22:10 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Popielarski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Popielarski <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process, BGA Reballing
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0019_01C1AA38.C2A26E40"

This is a multi-part message in MIME format.

------=_NextPart_000_0019_01C1AA38.C2A26E40
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi all,

I've found this thread to be very interesting and informative, but would =
like to present a "different twist" to the subject:

I have a client using our Reballing system to recondition all sorts of =
BGA and uBGA for re-use after de-soldering. They are currently using a =
water soluble paste and cleaning with DI, however the residual absorbed =
moisture presents a concern, so the devices are baked after cleaning. =
This increases turnaround time, so they are considering moving to a =
no-clean process.=20

My opinion is that there will be residues and they could possibly be =
incompatible with subsequent platforms utilized by the end user, as well =
as creating aesthetic impact. Cleaning alternatives for no-clean fluxes =
rival the more aggressive (therefore more forgiving) water solubles, so =
the benefit is lost if cleaned.

Any and all opinions, theories, suggestions and experiences are =
welcomed!
=20
Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618

Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578

WWW.QTA.NET

------=_NextPart_000_0019_01C1AA38.C2A26E40
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi all,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>I've found this thread to be very =
interesting and=20
informative, but would like to present a "different twist" to the=20
subject:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>I have a client using our Reballing =
system to=20
recondition all sorts of BGA and uBGA for re-use after de-soldering. =
They are=20
currently using a water soluble paste and cleaning with DI, however the =
residual=20
absorbed moisture presents a concern, so the devices are baked after =
cleaning.=20
This increases turnaround time, so they are considering moving to a =
no-clean=20
process. </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>My opinion is that there&nbsp;will be =
residues and=20
they could possibly be incompatible with subsequent platforms utilized =
by the=20
end user, as well as creating aesthetic impact. Cleaning =
alternatives&nbsp;for=20
no-clean fluxes rival the more aggressive (therefore more forgiving) =
water=20
solubles, so the benefit is lost if cleaned.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Any and all opinions, theories, =
suggestions and=20
experiences are welcomed!</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>

------=_NextPart_000_0019_01C1AA38.C2A26E40--

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Date:         Thu, 31 Jan 2002 12:22:19 -0500
Reply-To:     Mark Charlton <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Charlton <[log in to unmask]>
Organization: MSI of Central Florida, Inc.
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Jeff,

My "rule of thumb" is plastic BGA's with eutectic balls - I use stick flux
only.  For ceramic BGA's with non-eutectic or "hard" balls, I must use a
microscreen and apply solder paste.

Mark

----- Original Message -----
From: "Jeff Ferry" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, January 31, 2002 11:54 AM
Subject: BGA Rework Using Paste vs. No Paste


> Fellow TechNetters,
>
> We nearly always apply solder paste to the circuit board when we replace
> BGA components during rework. Yet, after speaking with a handfull of BGA
> equipment companies at APEX, seems like they all recommend using flux only
> vs. paste, unless the circuit board is used in a high rel application.
>
> What do ya'all do/recommend for BAG rework? Can you point me to any
> studies/reports on the subject?
>
> Thanks,
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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SET Technet NOMAIL
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> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>

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Date:         Thu, 31 Jan 2002 12:27:43 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: ODB++
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It has been an interesting dialogue thus far with many interesting issues
raised.

Going back over the years, we have witnessed many data transfer schemes that
have served many purposes. Gerber has served very well for what it was
original intended to do. As our designs become more complex and demand more
complex fabrication, assembly and testing processes and techniques, we find
ourselves looking for the next generation data transfer vehicle.

In the 1970s IPC created the IPC-D-350 data format to address a more
intelligent transfer of fabrication data. It included hole, outline and other
important information. IPC even established a certification system to ensure
that the data coming from many sources complied to the format rules and would
not generate errors upon read-in. No, the industry did not embrace it as
expected. Why? For several reasons, reasons that are very applicable to this
current discussion.

First, a number of fabricators offered severe discounts to customers sending
350 data. The discounts were applied against the tooling charges, not the
actual fabrication costs of the board. Hmmmm, tooling charges are in the
range of $400 - $500. Even if the fabricators gave the tooling away for free,
it would take an awful lot of orders to justify the cost of the CAD output
software. You see, it has never been in the best interest for a CAD software
supplier to permit intelligent data output. lest the user wish to switch his
CAD software to another supplier. Therefore, some of the CAD suppliers placed
exorbitant fees on the 350 output software. Not doing the user community
justice at all. Therefore, when the designer requested the software update
from his management, he was told that the amount saved was not cost
justified.

Second, fabricators realized several savings when using intelligent data
files. They saved by eliminating a number of data files that invariably
conflicted with each other. It took manpower and time to resolve these
differences before a job could proceed into fabrication. So, fabricators
provided discounts on tooling and requested these intelligent files from
their customers. In some cases insisted upon it only to be told by their
customers "if you can't do the job with what we send you, we'll find someone
who can." Faced with this choice and since the fabricator was comfortable
with the evils of Gerber, he accepted the Gerber files.

Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing the
same issues. Yes, IPC has again provided a compliance test module to verify
the output/input of GenCAM data. Yes, some of the output software is being
offered for free. Yes, companies are offering tooling discounts for
intelligent data files. And yes many companies are using either of the two
formats. Will either format take 100% market share? No! The fact remains that
there will be followers of both formats, followers of new formats, and then a
large group that will do nothing but sit around and wait for who knows what
to happen.

Regards,

Gary Ferrari
Executive Director
IPC Designers Council
860-350-9300
fax 413-771-5386

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">It has been an interesting dialogue thus far with many interesting issues raised.<BR>
<BR>
Going back over the years, we have witnessed many data transfer schemes that have served many purposes. Gerber has served very well for what it was original intended to do. As our designs become more complex and demand more complex fabrication, assembly and testing processes and techniques, we find ourselves looking for the next generation data transfer vehicle.<BR>
<BR>
In the 1970s IPC created the IPC-D-350 data format to address a more intelligent transfer of fabrication data. It included hole, outline and other important information. IPC even established a certification system to ensure that the data coming from many sources complied to the format rules and would not generate errors upon read-in. No, the industry did not embrace it as expected. Why? For several reasons, reasons that are very applicable to this current discussion. <BR>
<BR>
First, a number of fabricators offered severe discounts to customers sending 350 data. The discounts were applied against the tooling charges, not the actual fabrication costs of the board. Hmmmm, tooling charges are in the range of $400 - $500. Even if the fabricators gave the tooling away for free, it would take an awful lot of orders to justify the cost of the CAD output software. You see, it has never been in the best interest for a CAD software supplier to permit intelligent data output. lest the user wish to switch his CAD software to another supplier. Therefore, some of the CAD suppliers placed exorbitant fees on the 350 output software. Not doing the user community justice at all. Therefore, when the designer requested the software update from his management, he was told that the amount saved was not cost justified. <BR>
<BR>
Second, fabricators realized several savings when using intelligent data files. They saved by eliminating a number of data files that invariably conflicted with each other. It took manpower and time to resolve these differences before a job could proceed into fabrication. So, fabricators provided discounts on tooling and requested these intelligent files from their customers. In some cases insisted upon it only to be told by their customers "if you can't do the job with what we send you, we'll find someone who can." Faced with this choice and since the fabricator was comfortable with the evils of Gerber, he accepted the Gerber files.<BR>
<BR>
Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing the same issues. Yes, IPC has again provided a compliance test module to verify the output/input of GenCAM data. Yes, some of the output software is being offered for free. Yes, companies are offering tooling discounts for intelligent data files. And yes many companies are using either of the two formats. Will either format take 100% market share? No! The fact remains that there will be followers of both formats, followers of new formats, and then a large group that will do nothing but sit around and wait for who knows what to happen.<BR>
<BR>
</FONT><FONT  COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
860-350-9300<BR>
fax 413-771-5386</FONT></HTML>

--part1_81.16de019b.298ad88f_boundary--

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Date:         Thu, 31 Jan 2002 10:36:13 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Pahlas <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Pahlas <[log in to unmask]>
Subject:      PCB Hole Diameters for Gold Press-fit
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Hello All,

I am working with a customer to determine the optimal finished hole diameter
for press-fit connectors into a Gold finish PCB. The supplier's data sheet
for the connector specifies .024"+/-.002" HASL plated holes. We have learned
from experience that the connector insertion success rate is greatly
improved when using a slightly larger hole on a gold finish PCB since it is
less compliant with the connector pins than the soft HASL.

So far, the supplier has not given a recommendation on a diameter for gold,
so I am looking for other industry standards to validate our findings.

Any ideas would be greatly appreciated.

Thanks, Dave

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Date:         Thu, 31 Jan 2002 11:37:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jason Gregory <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jason Gregory <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste
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Jeff,
It is my opinion that pasting the board enhances wetting and a superior =
joint.


Jason Gregory
Software Specialist=20
Sanmina-SCI - Tech Center Austin
15508  Bratton Lane
Austin, Tx. 78728
(512)246-5648
[log in to unmask]

>>> [log in to unmask] 01/31/02 10:54AM >>>
Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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Date:         Thu, 31 Jan 2002 11:35:53 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         [log in to unmask]

Mark,

I shouldn't have, but I just assumed eutectic. Shame on the moonman.

I tried the stick stuff, but couldn't get the compliance microstenciled
paste flux gives. It just reaches up and grabs the balls even when
coplanarity isn't perfect.

MoonMan

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Date:         Thu, 31 Jan 2002 11:41:27 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
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From:         Earl Moon <[log in to unmask]>
Subject:      Re: ODB++
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Gary,

Outstanding!

I'm a big fan of ODB because I'm a big fan of Valor. Please understand, I'm
not a sales representative. I just can't do in any other CAM package that
which I can do in Valor.

That's all I've got as it just gets the job done. Don't know what tomorrow
will bring but I ain't sittin' on it or waitin' for it.

Enjoy,

MoonMan

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Date:         Thu, 31 Jan 2002 12:44:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McMullen, Kerry" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McMullen, Kerry" <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>
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Hi Jeff,
For our eutectic PBGA's, we only flux (no clean).  Have only done about 50
or so over the past year with very good (97% yield) results.
Have not seen any studies or papers.  Just worked closely with our CM to
create the profile for each type of BGA.  We use Air-Vac.
Kerry

-----Original Message-----
From: Jeff Ferry [mailto:[log in to unmask]]
Sent: Thursday, January 31, 2002 11:54 AM
To: [log in to unmask]
Subject: [TN] BGA Rework Using Paste vs. No Paste


Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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Date:         Thu, 31 Jan 2002 17:53:00 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Conformal Coating
X-To:         "Marsico, James" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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Jim

Having kicked this around here, the general consensus is that you do NOT
ship the product.

Without knowing the exact coating material, nor your end product, we could
not say how the "overcooked / oxidised" coating will behave. We would figure
that its moisture and chemical resistance might be improved but, its
potentially less flexible nature might over-stress components.

As to removing it, I think that a chemical stripper would probably be safer
but it will have to be done very carefully by hand, a little at a time. I
could not comment upon its effect on components and understand why your
customer would be unhappy with this. This is a space product, and the cost
of launch, much less manufacture, would probably demand that you re-make the
product - it might give all the data acquisition to the Aliens on planet
Tharg.

Sorry, but I don't think we can give you an acceptable alternative. Best of
luck.

Regards Graham Naisbitt

[log in to unmask] <mailto:[log in to unmask]>

Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK

www.concoat.co.uk <http://www.concoat.co.uk>

Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121


> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
> Sent: 30 January 2002 18:39
> To: [log in to unmask]
> Subject: Re: [TN] Conformal Coating
>
>
> The coating supplier's technical staff stated that the discoloration was
> probably due to oxidation of the double bond of the molecules.  He also
> stated, as you, that the material may have become somewhat harder due to
> further cross linking.
>
> I don't think that moisture permeability is an issue, but what is
> a concern
> is if the modulus increased which might affect chip component reliability,
> if coating was actually under some ceramic or glass components.  In your
> opinion, would additional cross linking, oxidation, reversion or being at
> 150C for 2 hours cause the modulus to increase?
>
> As far as stripping the coating, we crossed this path once before and our
> customer will not allow us to use any chemical stripping solution
> to remove
> polyurethane coating.  They don't know how it will affect components,
> boards, etc.
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>
>         -----Original Message-----
>         From:   Graham Naisbitt [SMTP:[log in to unmask]]
>         Sent:   Wednesday, January 30, 2002 11:37 AM
>         To:     [log in to unmask]
>         Subject:        Re: [TN] Conformal Coating
>
>         Jim
>
>         I know this is a late posting, because I have only just come back
> on-line
>         however, what you have encountered is reversion.
>
>         The UR materials tend to discolour when exposed to high
> temperatures, but
>         this does not generally affect their subsequent performance - if
> anything it
>         might improve it because you have ensured a full x-link of the
> polymer -
>         fully reacted.
>
>         The discoloration may however, be an unacceptable visual condition
> to your
>         customer, depending upon their inspection criteria.
>
>         Whatever, it will be possible to remove and re-coat if you desire.
>
>         You mention that this is a space application, therefore this
> material will
>         probably have excellent outgassing characteristics and I can only
> think of 1
>         or 2 UR space (NASA / ESA) approved coatings. I am surprised that
> you have
>         this reversion, what did their technical staff advise? I
> would like
> to know
>         for my own record.
>
>         Regards Graham Naisbitt
>
>         [log in to unmask]
> <mailto:[log in to unmask]>
>
>         Concoat Limited
>         Alasan House, Albany Park
>         Camberley GU16 7PH - UK
>
>         www.concoat.co.uk <http://www.concoat.co.uk>
>
>         Phone: +44 1276 691100
>         Fax: +44 1276 691227
>         Mobile: +44 79 6858 2121
>
>
>         > -----Original Message-----
>         > From: TechNet [mailto:[log in to unmask]]On Behalf Of David Douthit
>         > Sent: 29 January 2002 00:49
>         > To: [log in to unmask]
>         > Subject: Re: [TN] Conformal Coating
>         >
>         >
>         > Jim,
>         >
>         > You have chemically altered the polymer. It will no longer
>         > perform it's designed function.
>         >
>         > David A. Douthit
>         > Manager
>         > LoCan LLC
>         >
>         > "Marsico, James" wrote:
>         >
>         > > Help!  Emergency!
>         > >
>         > > We have a completed assembly (top assembly with many boards,
>         > hybrids, etc.)
>         > > ready for shipment to our customer (space product).  The last
>         > operation was
>         > > to ink mark a S/N.  The ink is cured at 150 F for 2
> hours.  The
>         > assembly was
>         > > put in an oven at 150 C for two hours.  After hours of
>         > reviewing all of the
>         > > materials and bill of material, component by component
> (component data,
>         > > supplier phone calls, etc.), the only item that is not rated
>         > for 150 C is
>         > > the polyurethane conformal coating, which turned yellow/brown
>         > in color.  Can
>         > > anyone explain what actually happened to the coating and if it
>         > can be used
>         > > as is?
>         > >
>         > > Thanks,
>         > >
>         > > Jim Marsico
>         > > Senior Engineer
>         > > Production Engineering
>         > > EDO Electronics Systems Group
>         > > [log in to unmask] <mailto:[log in to unmask]>
>         > > 631-595-5879
>         > >
>         > >
>         >
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Date:         Thu, 31 Jan 2002 10:04:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dan R. Johnson" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: ODB++
X-To:         Mark Steele <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
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Just a thought, wouldn't the gerber be absolute too? Just compare data
rather than the image. I seem to recall an old OS that had a command called
"compare".
Dan

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Date:         Thu, 31 Jan 2002 11:58:06 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      MoonCaveMan cleaning out the cave. Lot's of free stuff.

Yes friends,

The MoonCaveMan has reached a limit. He is making an offer as none other
before. As a kind and giving, though a bit rough around the edges (much like
some of my current solder joints) kinda guy, he's cleaned out his cave and
now is making available a bunch of manufacturing operations procedures.

Some of the stuff is not so good, but most of it ain't too bad. All
procedures, including moisture, stencil printing, rework, wave soldering,
placement, reflow, and a bunch more are photo documents dating way back to
the present.

If Seth still allows, I'm going to place them all on his FTP site within my
folder.

My users may log into ftp.GoodmanAssociates.com anonymously.  They will see a
directory called "Earl's files" that contain all your stuff.  They can then
download to their heart's content.

Happy hunting,

MoonCaveMan

Oh yes, I'll complete the transfer tomorrow so you might want to wait a day
or so.

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Date:         Thu, 31 Jan 2002 13:26:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bev Christian <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Water Drop Test
MIME-Version: 1.0
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Technetters,
Do any of you have the instructions for the water drop test handy?  If so,
could you post it, please.  Thanks.
Bev Christian
Research in Motion

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Date:         Thu, 31 Jan 2002 10:58:49 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Jeff,

We have been working and reworking BGA and Micro BGA for quite sometime.
This is a requirement in a prorotye environment. We tried using micro
stencil when we first attempt to replace the BGAs and found out that using
micro stencil was not a good method. We then tried using no-clean tacky
past fux and applied to both the BGA and the PWB substrates. This process
has been adopted in our process and has been working well for us. Here are
some great benefit of using flux paste only.
     - No micro stencil cost.
     - No cleaning is needed (No-clean flux).
     - No aligning equipment is needed, since we can place the BGA into its
footprints without worry about     smearing the solder paste, and if the
hand alignment if off ( no more than 50%), the liquid tension of the
reflowed solder balls will pull it back.
     - Save time and money. ( stencil cost, cleaning, and aligning).

If the solder balls on the BGA are made of non-eutectic, solder paste is
required.

Tuan Bui
Conexant Systems Inc.
Prototype Process Dev. Eng.



                    Jeff Ferry
                    <jferry@CIRCUITTE        To:     [log in to unmask]
                    CHCTR.COM>               cc:
                    Sent by: TechNet         Subject:     [TN] BGA Rework Using Paste vs.
                    <[log in to unmask]>        No Paste


                    01/31/02 08:54 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Jeff
                    Ferry






Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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Date:         Thu, 31 Jan 2002 11:00:23 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Thompson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject:      Re: ENIG Thickness Standard?
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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Dave,

Thanks for the feedback. I did get some specifics on IPC-4552 proposed
recommendations from the committee co-chair that we're going to put in
our requirements.

Regards,

Rick Thompson


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of
[log in to unmask]
Sent: Thursday, January 31, 2002 6:37 AM
To: [log in to unmask]
Subject: Re: [TN] ENIG Thickness Standard?


Good Morning TechNet! Rick, I have a very different perspective on ENIG
than Peter so here is some food for thought. There is a specification
for ENIG  - IPC-4552 - which is in final ballot and should be release in
the March/May timeframe. I recommend getting a copy.  It's my opinion
that the specification is quite useful considering there is no other
specification available for industry use. The ASTM B488 specification is
not a workable solution for electronics applications. There was a great
deal of committee discussion on the electroless nickel plating
thickness. The nickel thickness is very much viewed as application
specific, for example,  RF designers desire minimal thickness (30-50
uinches) as opposed to connecting applications which use 200 uinches.
Rockwell Collins is successfully using 2-5 uninches for the immersion
gold thickness and 50-150 uinches for the electroless nickel thickness
in avionics applications and we intend on using the IPC-4552
specification in our documentation. Additionally, 50 uinches of
electroless nickel is very adequate as a diffusion barrier as both the
nickel/copper and nickel/gold phase diagrams demonstrate a wide range of
immiscibility The only instances I have seen a 50 uinch electroless
nickel thickness not be adequate was for pwbs which were subjected to
repetitive thermal excursions (e.g. lots of rework, or 4 reflow passes).
Using an immersion gold thickness of 6 uinches will not guarantee you
solderability - the 4552 committee demonstrated that (by conducting
testing) that 2 uinches of immersion gold can be steam conditioned and
still provide expected solderability coverage. Teaming with your ENIG
vendor, understanding their plating process control practices and
requiring some level of solderability testing is the best way of
insuring solderability.  Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




[log in to unmask]@ipc.org> on 01/30/2002 09:03:53 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond
      to [log in to unmask]

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  Re: [TN] ENIG Thickness Standard?


Rick,

I went through this pain a while ago, and got a lot of tremendous help
from Ingemar Hernefjord in particular. I believe there is no released
standard for ENIG, though there is an empirical spec IPC-4552. It does
not contain a lot of useful detail, though. I specify 5 microinches
(0.12 microns) of Gold over minimum 235 microinches (6 microns) Nickel
for my boards, after reading a number of studies and failure reports. In
fact I was recommended to use 250 microinches of Nickel, but this would
have made our boards too thick. The thicker gold layer minimises
porosity and therefore oxidation to the underlying Nickel layer.

Older thinking was for around 100 to 120 microinches Nickel, but studies
by Eriksson and others concluded that with the growth of gold flashing
through the Nickel from one side and Cu/Ni intermetallics on the other
side of the plating, that a thicker Nickel layer would offer the boards
a longer solderability shelf life and greater solder joint reliability.

Hope this helps a bit. Certainly, I haven't experienced any problems
with soldering or mounting of components on boards to this spec.

Peter




                    Rick Thompson
                    <rthompson@VENTURAELECTR        To:
[log in to unmask]
                    ONICS.COM>                      cc:     (bcc: DUNCAN
Peter/Asst Prin Engr/ST
                    Sent by: TechNet                Aero/ST Group)
                    <[log in to unmask]>               Subject:     [TN]
ENIG
Thickness Standard?


                    01/31/02 08:36 AM
                    Please respond to
                    "TechNet E-Mail Forum.";
                    Please respond to Rick
                    Thompson






Is there a standard for the plating thickness of the ENIG surface
finish?  I've searched the archives and didn't find anything.  Based on
a customer request we had increased the requirement for the electroless
nickel to 200u inches. A couple of our board vendors are telling me that
that is excessive and that anything over 100u inches is overkill. I've
seen references in the archives for anything from 120u inches to 200u
inches.  What (if anything) is considered standard for this finish?

Thanks for your inputs.


Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Thu, 31 Jan 2002 14:10:39 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Re: ODB++
X-To:         [log in to unmask]
Mime-Version: 1.0
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Ahne
The last one is a good point!  We do contract manufacturing of military =
products.  Currently when I need a stencil all I'm sending out is the =
paste layer gerber file, and the aperture report.  I'd be nervous sending =
the full design data out, and I'm sure my customer would be unhappy.  =
Either we would have to get vendors cleared for security purposes, or we =
would have to manipulate the data here - which I'd rather avoid doing.   =
Being able to easily send just a layer of the data is very handy.

This is true for many parts of build - getting pwb's made, stencils, wave =
soldering fixtures, test fixtures...  yikes!



regards

Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215

>>> Ahne Oosterhof <[log in to unmask]> 01/31/02 12:19PM >>>
Yikes, sorry, wrong button pushed and there went an unfinished
-mail  ------------

Following is a more finished one:

I have been trying to follow the development of new data standards in this
industry. I have listened to the various interested parties make very
interesting claims about the goodness of their products. But at the moment =
I
hope that the GenCAM type effort is going to win. Even though I have no
reason to wish that Gerber would go away.

The nice things about Gerber are that it is a very simple standard and I =
can
read and understand the file. Therefore I can check the content of a file
and fix problems with the data. And I have not yet come across images that
cannot be represented by Gerber data.
The unpleasant things that have happened with Gerber is, that there are
always software designers who can and will "improve" things. And now their
"Gerber-like" output cannot be read by input devices that fully comply =
with
the Gerber Standard.
Then there are software engineers who design input devices and decide that
certain features and rules in the standard are superfluous and exclude =
those
from their package. The result is of course that their product at times =
does
not show results that were in the original fully complying data.

With more complex data standards it is hard to believe that these problems
are going away or are going to be easier to deal with. And the reason that =
I
lean towards GenCAM is that the effort to develop that standard includes
compliance checkers to help users determine that their output or input =
files
do indeed comply with the standard. The data format is readable so it is
easier to check what is inside the file and there is intent to assure that
all future versions are backwards compatible. So when I store data I don't
have to store interpreters to go with that specific data.

Next question: when is it going to be ready and is it going to be accepted
widely?

And of course a disadvantage of these new all-encompassing data files is
that I only need the layers that have the information needed to make a
stencil and I don't need (and I really don't want) 25Mbyte of data,
including the information on what parts to buy where and how to build and
test the board. We already have received files that include the little =
note:
Please destroy files after delivery of stencil !!!

Have fun,

Ahne.
A-Laser, Inc.




* I assume you are comfortable with your system outputting gerber, ---

I would also opt for ODB++ as it can carry a lot more than just bare board
information. ---

The problem I have is in archiving any data object in more than one
ormat  ---

how do you insure that both sets of output data are identical in every
way? ---

If the CAD system doesn't produce ODB++ directly, and most don't ----

we use a third party tool (I use CAM350) to translate into ODB++, either
from the native CAD file or from Gerbers. ---

Producing an output file, either Gerber or ODB++, from a native CAD =
database
is a translation process. ---

I have yet to own a piece of bug-free software. ---

I know from experience that there are flaws in the Gerber data generators =
in
most CAD programs. ---

Similarly, different Gerber viewers can display the same data file
differently. ---

if an independent industry group produced a validation suite that a =
program
would have to pass to call itself ODB++ compliant. ---

Gerber, which is truly a rotten old standard. ---

Until ODB++ becomes as universally accepted by fab shops as Gerber ---

Regards,

From Seth Goodman's e-mail.

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Date:         Thu, 31 Jan 2002 14:19:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Collins <[log in to unmask]>
Subject:      Re: Flux residue with a no-clean process, BGA Reballing
Mime-Version: 1.0
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Ed
If they do change to no-clean, please give me a name so I know who not to =
use!!!  :-)

Seriously, I'd have some serious issues with this.  There is no way they =
can know what the end use of the part is - unless they ask each time and =
tailor the process to fit.  So someone might end up  with a big hidden =
problem.  Potentially the end user has a no-clean residue in an application=
 that won't tolerate it, or they process the board with a wash and they =
end up with a mystery residue (as has been discussed on TechNet previously)=
.

I have to ask though, can they process them fast enough that they aren't =
worried about moisture from the air? =20

Doesn't sound like a great plan to me...

regards

Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215

>>> [log in to unmask] 01/31/02 01:22PM >>>
Hi all,

I've found this thread to be very interesting and informative, but would =
like to present a "different twist" to the subject:

I have a client using our Reballing system to recondition all sorts of BGA =
and uBGA for re-use after de-soldering. They are currently using a water =
soluble paste and cleaning with DI, however the residual absorbed moisture =
presents a concern, so the devices are baked after cleaning. This =
increases turnaround time, so they are considering moving to a no-clean =
process.=20

My opinion is that there will be residues and they could possibly be =
incompatible with subsequent platforms utilized by the end user, as well =
as creating aesthetic impact. Cleaning alternatives for no-clean fluxes =
rival the more aggressive (therefore more forgiving) water solubles, so =
the benefit is lost if cleaned.

Any and all opinions, theories, suggestions and experiences are welcomed!
=20
Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618

Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578

www.QTA.NET

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Date:         Thu, 31 Jan 2002 11:21:05 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Chad Haima <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Chad Haima <[log in to unmask]>
Subject:      Solder Pallet Material Test
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello all,
We're in the process of evaluating a new solder pallet material and was
wondering if someone out there had a wave machine we could basically "rent"
for a 4-6 month period.  Any correspondence would be appreciated.

Chad Haima
National Sales Manager
S.P. Precision International, Ltd.
1-800-PALLETT
http://www.spprecision.com/

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Date:         Thu, 31 Jan 2002 14:56:39 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Flux residue with a no-clean process, BGA Reballing
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Ed

In answer to your question, yes the benefit can be lost if the component is
cleaned.  We have worked with clients that have experienced problems with BGA
components that were balled using a low solids no clean flux. These units
were assembled with water-soluble solderpaste and cleaned in an aqueous
inline system.  The low solids no clean residue absorbed the activators and
moisture from the assembly process and created a corrosion cell on finished
assemblies.  I would recommend that good cleaning and drying process for the
components that will be subjected to aqueous cleaning of water-soluble
solderpaste.
We found that Ion Chromatography analysis corresponded well to the electrical
performance testing (failures had high chloride levels).



Terry Munson
CSL Inc.
P 765-457-8095
F 765-457-9033

<A HREF="www.Residues.com">www.Residues.com</A>



<<  have a client using our Reballing system to recondition all sorts of BGA
and uBGA for re-use after de-soldering. They are currently using a water
soluble paste and cleaning with DI, however the residual absorbed moisture
presents a concern, so the devices are baked after cleaning. This increases
turnaround time, so they are considering moving to a no-clean process.

 My opinion is that there will be residues and they could possibly be
incompatible with subsequent platforms utilized by the end user, as well as
creating aesthetic impact. Cleaning alternatives for no-clean fluxes rival
the more aggressive (therefore more forgiving) water solubles, so the benefit
is lost if cleaned.

Ed

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Date:         Thu, 31 Jan 2002 13:59:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jeff Ferry <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Ferry <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste

Thanks for the replies (see below) to my original posting (see below).

Seems like several of you are having good luck using flux only vs. solder
paste during BGA rework. The thing I wonder about is the reliability of
reworked BGA solder joints. I thought that proper BGA solder joint volume
was based on the original BGA ball combined with the solder added during
the solder paste screen printing process. Thus, what effect does solder
volume and solder joint height have on the reliability of a BGA solder
joints for plastic BGA components?

Thanks again,

Jeff Ferry
CEO
Circuit Technology Center, Inc.


Some Replies to prior posting included:

---------------------------

My "rule of thumb" is plastic BGA's with eutectic balls - I use stick flux
only.  For ceramic BGA's with non-eutectic or "hard" balls, I must use a
microscreen and apply solder paste.
Mark

---------------------------

For our eutectic PBGA's, we only flux (no clean).  Have only done about 50
or so over the past year with very good (97% yield) results.
Have not seen any studies or papers.  Just worked closely with our CM to
create the profile for each type of BGA.  We use Air-Vac.
Kerry

---------------------------

It's the only way to go. I've been designing, placing, reflowing and
reworking BGA's for nearly 8 years now. It took me five minutes to make the
discovery and, as I've said far too often, I'd use flux only on initial
production if feasible.
Regards and respect,
Earl Moon


---------------------------

We have been working and reworking BGA and Micro BGA for quite sometime.
This is a requirement in a prorotye environment. We tried using micro
stencil when we first attempt to replace the BGAs and found out that using
micro stencil was not a good method. We then tried using no-clean tacky
past fux and applied to both the BGA and the PWB substrates. This process
has been adopted in our process and has been working well for us. Here are
some great benefit of using flux paste only.
     - No micro stencil cost.
     - No cleaning is needed (No-clean flux).
     - No aligning equipment is needed, since we can place the BGA into its
footprints without worry about     smearing the solder paste, and if the
hand alignment if off ( no more than 50%), the liquid tension of the
reflowed solder balls will pull it back.
     - Save time and money. ( stencil cost, cleaning, and aligning).

If the solder balls on the BGA are made of non-eutectic, solder paste is
required.

Tuan Bui
Conexant Systems Inc.
Prototype Process Dev. Eng.

---------------------------

It is my opinion that pasting the board enhances wetting and a superior
joint.
Jason Gregory

---------------------------

On Thu, 31 Jan 2002 10:54:24 -0600, Jeff Ferry <[log in to unmask]>
wrote:

>Fellow TechNetters,
>
>We nearly always apply solder paste to the circuit board when we replace
>BGA components during rework. Yet, after speaking with a handfull of BGA
>equipment companies at APEX, seems like they all recommend using flux only
>vs. paste, unless the circuit board is used in a high rel application.
>
>What do ya'all do/recommend for BAG rework? Can you point me to any
>studies/reports on the subject?
>
>Thanks,
>
>Jeff Ferry
>CEO
>Circuit Technology Center, Inc.
>
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Date:         Thu, 31 Jan 2002 14:24:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>

Jeff,

I know how busy you must be but we (me, Werner, Dave Fisherman, et al.) have
discussed this at some length over time but most recently as well. This is
one of those times where I didn't get my ass kicked too badly.

It all comes down to more isn't necessarily better.

Enjoy,

Earl

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Date:         Fri, 1 Feb 2002 07:52:34 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Colin Weber <[log in to unmask]>
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From:         Colin Weber <[log in to unmask]>
Subject:      Graphics Cards
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Folks,

I know this isn't exactly PCB design but as CAD users I though someone
might be able to share their knowledge.

I am after any experiences with running a dual video card or two individual
cards for dual monitor arrangements under MS Windows 2000.

In particular, I'd like to know what the card(s) are and what cost,
success/failure, perhaps even what CAD packages you run. Also, any
success with OpenGL over the two monitors, 2D & 3D/performance.

Finally, another issue, anyone who runs a 17" to 20" flat panel LCD screen
and how they like/dislike it.

Regards,

Colin Weber

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Date:         Thu, 31 Jan 2002 16:17:37 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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Subject:      Re: ODB++
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Graham,

Formats are formats. The implementor of the output software usually provides
an interface that allows one to select the proper output information. I do
know that the GenCAM data format permits the selection of any specific data
set that is desired to be output.

Regards,

Gary Ferrari
Executive Director
IPC Designers Council
860-350-9300
fax 413-771-5386

--part1_37.220d0629.298b0e71_boundary
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Graham,<BR>
<BR>
Formats are formats. The implementor of the output software usually provides an interface that allows one to select the proper output information. I do know that the GenCAM data format permits the selection of any specific data set that is desired to be output.<BR>
<BR>
</FONT><FONT  COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
860-350-9300<BR>
fax 413-771-5386</FONT></HTML>

--part1_37.220d0629.298b0e71_boundary--

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Date:         Thu, 31 Jan 2002 15:34:25 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
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From:         Earl Moon <[log in to unmask]>
Subject:      Re: Graphics Cards
X-To:         [log in to unmask]

I have had great success with Matrox dual head products up to and including
the "latest" 450 series. There is other product available for "serious" CAD
users but at much higher cost and maybe not such good performance. You may
need a "higher" end card.

I use a ViewSonic 17" flat panel monitor with great results as well. I
really liked the Silicon Graphics stuff but for Silicon Graphics the company
and all its problems.

MoonMan

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Date:         Thu, 31 Jan 2002 13:38:57 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark Steele <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark Steele <[log in to unmask]>
Subject:      Re: ODB++
X-To:         "Dan R. Johnson" <[log in to unmask]>
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Hi Dan,

I'm sure the pads and lines would be identical in both. I was
just thinking of the complex apertures that we sometimes get
in gerber 274X might not be a 100% one-to-one match with the
surfaces that we would end up with ODB++. I don't know that
they would be different but I do think there would be some
kind of difference, but hopefully a very small one.

I guess the question is what kind or tolerance are we going to
have to be considered 'different'. A difference of .000001
doesn't seem to qualify since we could never see it or even
measure it.


Mark



>From: Dan R. Johnson [mailto:[log in to unmask]]
>Sent: Thursday, January 31, 2002 10:05 AM
>To: TechNet E-Mail Forum.; Mark Steele
>Subject: Re: Re: [TN] ODB++
>
>
>Just a thought, wouldn't the gerber be absolute too? Just compare data
>rather than the image. I seem to recall an old OS that had a
>command called
>"compare".
>Dan
>
>

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Date:         Thu, 31 Jan 2002 14:08:02 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Thompson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>
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Jeff,

No studies to cite, but in our admittedly informal internal testing
we've found consistently better yields using paste rather than flux for
BGA replacements.  Some of this may be due to the condition of pcb and
pads on the boards after removal but we really haven't studied it in
detail.

Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858   x-304  voice
+1 (805) 584-1529 fax
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: Thursday, January 31, 2002 8:54 AM
To: [log in to unmask]
Subject: [TN] BGA Rework Using Paste vs. No Paste


Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux
only vs. paste, unless the circuit board is used in a high rel
application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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Date:         Thu, 31 Jan 2002 15:19:42 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "PHC L.L." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "PHC L.L." <[log in to unmask]>
Subject:      PCB Cross-sectional analysis service
MIME-Version: 1.0
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Anyone knows where I can get PCB cross-sectional
analysis service?? with reasonal price?

Thanks


__________________________________________________
Do You Yahoo!?
Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Thu, 31 Jan 2002 17:29:22 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Earl Moon <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: PCB Cross-sectional analysis service
X-To:         [log in to unmask]

Robisan Labs in Indiana - where else. Susan Mansilla. She and the lab owe me
now for some very cost effective sections.

Susan, where are they? Also, give this kind person some direction.

Earl

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Date:         Thu, 31 Jan 2002 18:33:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Leland Woodall <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Leland Woodall <[log in to unmask]>
Subject:      Looking for Dr. Kantesh Doss
MIME-Version: 1.0
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Can anyone assist me in contacting Dr. Kantesh Doss?  I understand he was
working on a PWB cleaning standard for IPC.

I believe he left Siemens Energy and Automation in Johnson City, TN, to go
to work with Nokia in TX, but I haven't spoken with him since.

Thanks for the info,

Leland Woodall
Keihin Carolina System Technology, Inc.
Tarboro, NC

252-212-1565, ext. 2865

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Date:         Thu, 31 Jan 2002 16:36:49 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
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Subject:      Re: PCB Cross-sectional analysis service
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Try these two places:

http://www.aciusa.org
http://www.solderingtech.com/

-----Original Message-----
From: PHC L.L. [mailto:[log in to unmask]]
Sent: Thursday, January 31, 2002 4:20 PM
To: [log in to unmask]
Subject: [TN] PCB Cross-sectional analysis service


Anyone knows where I can get PCB cross-sectional
analysis service?? with reasonal price?

Thanks


__________________________________________________
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Great stuff seeking new owners in Yahoo! Auctions!
http://auctions.yahoo.com

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Date:         Thu, 31 Jan 2002 17:53:48 -0600
Reply-To:     [log in to unmask]
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Gary,

Thanks so much for adding the GenCAM part of the story.  Here are a couple
of questions concerning the points you made:

> Today, with intelligent data such as ODB++ and IPC's GenCAM we are facing
the same issues.
> Yes, IPC has again provided a compliance test module to verify the
output/input of GenCAM data.
> Yes, some of the output software is being offered for free. Yes, companies
are offering tooling
> discounts for intelligent data files. And yes many companies are using
either of the two formats.
  Could you pass on information as to who is offering free output software?
Also, I would like to know about fabrication shops that offer discounts for
use of intelligent tooling.  When you say many companies are using either
format, are you talking about fabrication shops?
> Will either format take 100% market share? No! The fact remains that there
will be followers of
> both formats, followers of new formats, and then a large group that will
do nothing but sit around
> and wait for who knows what to happen.
  This is the real tragedy.  Right now, all fabrication shops accept Gerber,
as far as I know.  The more different intelligent formats we standardize,
the more expensive and complicated the software for the fab shops will
become since they will be forced to deal with multiple formats.  That will
eat up much or all of the possible savings the smart format was intended to
provide.  Consider that a CAM engineer at the fab shop will have to be
conversant in each format as well as be familiar with the bugs, tricks and
workarounds for each format on his/her importing software.  IMHO, one new
format would be a boon to the industry, while several new formats would be a
drain on resources.  In that case, we may be better off turning RS-274X into
a real standard and create a validation suite for it.  I can't believe I
just suggested that in public, but it's better than dealing with a Tower of
Babel due to multiple standards.

  Another issue that I've heard bandied about is the possible merging of
ODB++ and GenCAM.  Can't recall where I heard this, but it is an interesting
idea.  Is this rumor correct and if so, what is the status of that effort?

We can look at the personal computer industry and see examples of how single
and multiple standard solutions fared.  In the early 1980's, IBM released
the workings of the ISA bus.  Though their information was not totally
complete and there was no validation mechanism that I remember, it wasn't
too hard to fill in the blanks and it became the de facto standard for about
10 years.  Even after the initial period of heavy use, motherboard and
software vendors were compelled to provide backward compatibility for this
standard.  Toward the end of the useful life of the ISA bus, it became a
bottleneck for increased performance and there was a huge amount of pressure
to come up with an alternative.  A number of companies extended the ISA
architecture and released the EISA standard.  About the same time, the
industry formed the VESA consortium and came up with an architecture that
gave better access to the processor local bus.  Also around the same time,
IBM released the MicroChannel Architecture because, well, they were IBM.
Despite their technical superiority to ISA, none of these solutions lasted
more than a couple of years.

Enter the PCI special interest group who took the best of MicroChannel, VESA
and EISA and came up with an extensible bus architecture that served the
industry well up through the present.  By the time it is superceded, the PCI
bus will have been useful for about 10 years.  If you look at the period
when ISA, EISA, VESA and MicroChannel coexisted, progress in the industry
was stymied by the multiple standards.  Both hardware and software companies
were hamstrung and tried to hedge their bets by producing the same product
on multiple bus platforms.  In contrast, during both the stable ISA years
and the stable PCI years, technical advancements and total sales took off.
Everyone could work efficiently as there was a single hardware platform and
the market for every product was larger due to the single standard.  The
software situation was not as good because a single company controlled the
de facto standard.  This is not inherently bad, but due to their mindset and
the lack of broader industry control, they made frequent, undocumented
changes to their interfaces and tools that made software development a very
expensive endeavor.  Those with limited resources were slowed to a crawl or
eliminated.

There's a lot we can learn from this.

1) It is to our mutual advantage to select a single standard, even if it is
not optimal.  Having several similar competing solutions will slow down
industry progress.  IMHO, we will do better with a single mediocre standard
than several more advanced but competing approaches.

2) It is dangerous to have a single company in a position to control the
standard.  If their market share is great enough, they could, like
Microsoft, participate in industry standards efforts and sign off on the
results (i.e. HTML, Java), then go ahead and violate the standard so
competing products were not interoperable.  If the standards were not
controlled by a couple of players who had large competitive axes to grind,
this probably wouldn't have happened.  This is not meant as a criticism of
Valor and does not discourage ODB++ from becoming the new standard.  It does
have implications as to how the new standard should be managed.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966


------=_NextPart_000_0016_01C1AA80.3C723CE0
Content-Type: text/html;
        charset="US-ASCII"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>Gary,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>Thanks =
so much for=20
adding the GenCAM part of the story.&nbsp; Here are a couple of =
questions=20
concerning the points you made:</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>&gt; =
Today, with=20
intelligent data such as ODB++ and IPC's GenCAM we are facing the same=20
issues.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>&gt; =
Yes, IPC has=20
again provided a compliance test module to verify the output/input of =
GenCAM=20
data.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>&gt; =
Yes, some of=20
the output software is being offered for free. Yes, companies are =
offering=20
tooling</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D729443522-31012002>&gt; =
discounts for=20
intelligent data files. And yes many companies are using either of the =
two=20
formats.</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <DIV><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>Could you pass on=20
  information as to who is offering free output software?&nbsp; Also, I =
would=20
  like to know about fabrication shops that offer discounts for use of=20
  intelligent tooling.&nbsp; When you say many companies are using =
either=20
  format, are you talking about fabrication=20
shops?</SPAN></FONT></DIV></BLOCKQUOTE>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>&gt; Will=20
either format take 100% market share? No! The fact remains that there =
will be=20
followers of</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>&gt; both=20
formats, followers of new formats, and then a large group that will do =
nothing=20
but sit around</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>&gt;&nbsp;and wait for who knows what to=20
happen.</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
  <DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>This is=20
  the real tragedy.&nbsp; Right now, all fabrication shops accept =
Gerber, as far=20
  as I know.&nbsp; The more different intelligent formats we =
standardize, the=20
  more expensive and complicated the software for the fab shops will =
become=20
  since they will be forced to deal with multiple formats.&nbsp; That =
will eat=20
  up much or all of the possible savings&nbsp;the smart format was =
intended to=20
  provide.&nbsp; Consider that a CAM engineer at the fab shop will have =
to be=20
  conversant in each format as well as be familiar with the bugs, tricks =
and=20
  workarounds for each format on his/her importing software.&nbsp; IMHO, =
one new=20
  format would be a boon to the industry, while several new formats =
would be a=20
  drain on resources.&nbsp; In that case, we may be better off turning =
RS-274X=20
  into a real standard and create a validation suite for it.&nbsp; I =
can't=20
  believe I just suggested that in public, but it's better than dealing =
with a=20
  Tower of Babel due to multiple standards.</SPAN></FONT></DIV>
  <DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
  class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
  <DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
  class=3D729443522-31012002></SPAN></FONT><FONT face=3DArial =
size=3D2><SPAN=20
  class=3D729443522-31012002>Another issue that I've heard bandied about =
is the=20
  possible merging of ODB++ and GenCAM.&nbsp; Can't recall where I heard =
this,=20
  but it is an interesting idea.&nbsp; Is this rumor correct and if so, =
what is=20
  the status of that effort?</SPAN></FONT></DIV></BLOCKQUOTE>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>We can look=20
at the personal computer industry and see examples of how single and =
multiple=20
standard solutions fared.&nbsp; In the early 1980's, IBM released the =
workings=20
of the ISA bus.&nbsp; Though their information was not totally complete =
and=20
there was no validation mechanism that I remember, it wasn't too hard to =
fill in=20
the blanks and it became the de facto standard for about 10 years.&nbsp; =
Even=20
after the initial period of heavy use, motherboard and software vendors =
were=20
compelled to provide backward compatibility for this standard.&nbsp; =
Toward the=20
end of the useful life of the ISA bus, it became a bottleneck for =
increased=20
performance and there was a huge amount of pressure to come up with an=20
alternative.&nbsp; A number of companies extended the ISA architecture =
and=20
released the EISA standard.&nbsp; About the same time, the industry =
formed the=20
VESA consortium and came up with an architecture that gave better access =
to the=20
processor local bus.&nbsp; Also around the same time, IBM released the=20
MicroChannel Architecture because, well, they were IBM.&nbsp; Despite =
their=20
technical superiority to ISA, none of these solutions lasted more than a =
couple=20
of years.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>Enter the=20
PCI special interest group who took the best of MicroChannel, VESA and =
EISA=20
and&nbsp;came up with an extensible bus architecture that served the =
industry=20
well up through the present.&nbsp; By the time it is superceded, the PCI =
bus=20
will have been useful for about 10 years.&nbsp; If you look at the =
period when=20
ISA, EISA, VESA and MicroChannel coexisted, progress in the industry was =
stymied=20
by the multiple standards.&nbsp; Both hardware and software companies =
were=20
hamstrung and tried to hedge their bets by&nbsp;producing the same =
product on=20
multiple bus platforms.&nbsp; In contrast, during both the stable ISA =
years and=20
the stable PCI years,&nbsp;technical advancements and total sales took=20
off.&nbsp; Everyone could work efficiently as there was a single =
hardware=20
platform and the market for&nbsp;every product was larger due to the =
single=20
standard.&nbsp; The software situation was not as good because a single =
company=20
controlled the de facto standard.&nbsp; This is not inherently bad, but =
due to=20
their mindset and the lack of broader industry control, they made =
frequent,=20
undocumented changes to their&nbsp;interfaces and tools that made =
software=20
development a very expensive endeavor.&nbsp; Those with limited =
resources were=20
slowed to a crawl or eliminated.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN =
class=3D729443522-31012002>There's a=20
lot we can learn from this.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>1)&nbsp;<STRONG><EM>It is to our mutual =
advantage to=20
select a single standard, even if it is not optimal.</EM></STRONG>&nbsp; =
Having=20
several similar competing solutions will slow down industry =
progress.&nbsp;=20
IMHO, we will do better with a single mediocre standard than several =
more=20
advanced but competing approaches.</SPAN></FONT></DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002></SPAN></FONT>&nbsp;</DIV>
<DIV dir=3Dltr><FONT face=3DArial size=3D2><SPAN=20
class=3D729443522-31012002>2)&nbsp;<STRONG><EM>It is dangerous to have a =
single=20
company in a position to control the standard.</EM></STRONG>&nbsp; If =
their=20
market share is great enough, they could, like Microsoft, participate in =

industry standards efforts and sign off on&nbsp;the results (i.e. HTML, =
Java),=20
then go ahead and violate the standard so competing products were not=20
interoperable.&nbsp; If the standards were not controlled by a couple of =
players=20
who had large competitive axes to grind, this probably wouldn't have=20
happened.&nbsp; This is not meant as a criticism of Valor and does not=20
discourage ODB++ from becoming the new standard.&nbsp;&nbsp;It does have =

implications as to how the new standard should be =
managed.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,<BR><BR>Seth Goodman<BR>Goodman =
Associates,=20
LLC<BR>tel 608.833.9933<BR>fax =
608.833.9966<BR></FONT></DIV></BODY></HTML>

------=_NextPart_000_0016_01C1AA80.3C723CE0--

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Date:         Thu, 31 Jan 2002 19:13:04 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: PCB Cross-sectional analysis service
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I recommend you try Soldering Technology International in Madison
(Huntsville), Alabama.  Tel:  256-461-9191.
This is the home of the infamous Jim Raby.

Phil Zarrow

ITM Consulting
Durham, NH  USA
www.ITMConsulting.org
T: (603) 868-1754
F: (603) 868-3623
EM:[log in to unmask]

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>I recommend you try Soldering Technology International in Madison (Huntsville), Alabama.&nbsp; Tel:&nbsp; 256-461-9191.<BR>
This is the home of the infamous Jim Raby.<BR>
<BR>
Phil Zarrow<BR>
<BR>
<B>ITM Consulting&nbsp; <BR>
Durham, NH&nbsp; USA<BR>
www.ITMConsulting.org<BR>
T: (603) 868-1754<BR>
F: (603) 868-3623<BR>
EM:[log in to unmask]</B></FONT></HTML>

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Date:         Thu, 31 Jan 2002 19:28:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Dupont CB100  VIA Plug and Delamination
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We have been having a problem with Dupont silver CB100 VIA Plug.  The
boards are 12 layer, .062", FR4, Nickel/Gold plated.
We have a BGA pattern with VIA in hole.  The VIAs are filled with CB100 VIA
plug and then the board is plated.
The VIAs are .010 causing an aspect ratio of 6.2:1.  We are seeing after
solder reflow, inner layer delamination in the area of the
VIA filled BGA patterns.  Has anyone seen this before?  Does anyone use a
similar construction and had success?  There are a few
theories flying around but I wanted to ask the IPC community for any
insight.  Thank you in advance.

Best Regards,

Mike Forrester
Sr. Manufacturing Engineer
[log in to unmask]

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Date:         Sun, 27 Jan 2002 23:39:40 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From:         [log in to unmask]
Subject:      Re: ENVIRONMENT AND TERMITES
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In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time,
[log in to unmask] writes:


> Termites were, before the rain forests were destroyed, by far the largest
> methane gas producers on this planet. Maybe they are still.
>
>

Did I miss the news that the rain forests were gone? Funny, I read last year
that the founder of the Sierra Club did a fly over and proclaimed that they
were at least 90% in tact.....?? Guess I better start paying more attention.

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<HTML><FONT FACE=arial,helvetica><FONT  COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">In a message dated 01/27/2002 9:58:11 AM Eastern Standard Time, [log in to unmask] writes:
<BR>
<BR></FONT><FONT  COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Termites were, before the rain forests were destroyed, by far the largest
<BR>methane gas producers on this planet. Maybe they are still.
<BR>
<BR></BLOCKQUOTE>
<BR></FONT><FONT  COLOR="#060000" SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">
<BR>Did I miss the news that the rain forests were gone? Funny, I read last year that the founder of the Sierra Club did a fly over and proclaimed that they were at least 90% in tact.....?? Guess I better start paying more attention.</FONT></HTML>

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Date:         Fri, 1 Feb 2002 13:28:02 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: BGA Rework Using Paste vs. No Paste
X-To:         Jeff Ferry <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Can't give much of an insight from experience, but I know that PBGA's
solder beautifully simply using flux. Paste is used to mount them during
initial assembly, simply because all the other components require it and
it's difficult to just flux the BGA's alone.

For re-work, though, you can concentrate on the BGA alone. You don't need
mini stencils and little squeegees - you just remove the old component,
clean up the site with a solder sucker (don't use wicks), apply flux to the
component contacts, place and reflow. The experts (Atmel/Thomson) tell me
it works a treat and have it written up as a guideline.

It doesn't work for CBGA's, which have 90/10 solder balls that don't melt
during reflow. These do require solder paste to replace them.

Peter




                    Jeff Ferry
                    <jferry@CIRCUITTE        To:     [log in to unmask]
                    CHCTR.COM>               cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    Sent by: TechNet         Aero/ST Group)
                    <[log in to unmask]>        Subject:     [TN] BGA Rework Using Paste vs. No
                                             Paste

                    02/01/02 12:54 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."; Please
                    respond to Jeff
                    Ferry






Fellow TechNetters,

We nearly always apply solder paste to the circuit board when we replace
BGA components during rework. Yet, after speaking with a handfull of BGA
equipment companies at APEX, seems like they all recommend using flux only
vs. paste, unless the circuit board is used in a high rel application.

What do ya'all do/recommend for BAG rework? Can you point me to any
studies/reports on the subject?

Thanks,

Jeff Ferry
CEO
Circuit Technology Center, Inc.

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