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Date:         Wed, 19 Dec 2001 14:41:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 14:46:01 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alan Kreplick <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hans,

Try Mil-Std-2000A or Mil-Std-2000.  Or their predecessor WS-6536 (my
favorite).

Al Kreplick
Teradyne, Inc.



 (Embedded
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 pic24901.pcx)




Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

To:   [log in to unmask]
cc:
Subject:  [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 13:44:57 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kathy Kuhlow <[log in to unmask]>
Subject:      Re: SMT Test points
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_C499D55E.9DFC91BD"

This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.

--=_C499D55E.9DFC91BD
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline

Try keystone, we have used their sm test points before.  Worked out pretty =
good.  Keystone #5015 or 5016.  We used the 5015 minature version.  =20

Kathy=20

--=_C499D55E.9DFC91BD
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Try keystone, we have used their sm test points before.&nbsp; Worked out
pretty good.&nbsp; Keystone #5015 or 5016.&nbsp; We used the 5015 minature
version.&nbsp;  </DIV>
<DIV>&nbsp;</DIV>
<DIV>Kathy </DIV></BODY></HTML>

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Date:         Wed, 19 Dec 2001 12:52:41 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Barry Gallegos <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Could that may be be MIL-2000A

-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Wednesday, December 19, 2001 12:42 PM
To: [log in to unmask]
Subject: [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 13:55:50 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mike Duggan <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Yes, I believe you are correct.  It's been a few years, but that rings a
bell.

Mike Duggan

-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Wednesday, December 19, 2001 1:42 PM
To: [log in to unmask]
Subject: [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 11:53:35 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: SMT Test points
MIME-Version: 1.0
Content-Type: text/plain

We like the E-Mark TPs in the 0805 size.  They come on 8mm tape and reel and
the machine likes them.  www.E-MarkInc.com

> -----Original Message-----
> From: Danny W. Harkins [SMTP:[log in to unmask]]
> Sent: Wednesday, December 19, 2001 11:29 AM
> To:   [log in to unmask]
> Subject:      [TN] SMT Test points
>
>
> Hello TN
>
> I am needing info on a SMT test pin. We need to be able to clip a scope
> probe to it and prefer to have it placeable by a P&P machine. Is anyone
> using anything of the likes.
>
> Thanks,
> Danny

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Date:         Wed, 19 Dec 2001 15:02:45 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Optimum Method to Apply Solder Paste to PWB's for BGA
              Application s?
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi Dave,
You write:
>As a self-described proponent of flux only mounting of BGA, please help us
>understand the impact on product reliability of reduced solder in these
connections.
I am with the  Moonman on this. SJ reliability is affected by solder joint
height, not very much by solder volume. In fact, data show that
'hour-glass'-shaped SJs have slightly greater reliabiliity than
'barrel'-shaped ones.

Werner Engelmaier

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Date:         Wed, 19 Dec 2001 14:09:58 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Hans
The only standard from the Mil specs that expressly addressed acceptability
like 610 was the DOD-STD-2000, Volume 3.  The other standards like
MIL-STD-2000 and 2000, Rev A included acceptability as would be equivalent
to J-STD-001.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Wednesday, December 19, 2001 11:42 AM
To: [log in to unmask]
Subject: [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 14:12:35 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dupuis, Dave" <[log in to unmask]>
Subject:      Re: SMT Test points
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

At 02:28 PM 12/19/2001 -0500, you wrote:

>Hello TN
>
>I am needing info on a SMT test pin. We need to be able to clip a scope
>probe to it and prefer to have it placeable by a P&P machine. Is anyone
>using anything of the likes.
>
>Thanks,
>Danny

  Take a look at Components Corporation (www.componentscorp.com) They have
some tape and reel test points that might fit your application.
Dave


David DuPuis, Associate Engineer
Rice Lake Weighing Systems

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Date:         Wed, 19 Dec 2001 16:07:58 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello Fellow Techies,

Thanks for the comments!

The original drawings are from the late 80's and we're conformally coating
the assembly instead of using an insulating foam so I get to change/improve
things.
MIL-STD-2000 came out after the drawings (which reference MIL-STD-454).  And
then there's the disconnect when both specs got canceled without an
identified replacement.  I'd rather identify a non-government specification
supporting DOD's decision to get out of the spec. business.  (They had
better solder the thing to J-STD-001 or I've got bigger problems than
getting a good coating.)

Happy Holidays.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468



-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: Wednesday, December 19, 2001 5:10 PM
To: [log in to unmask]
Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


Hans
The only standard from the Mil specs that expressly addressed acceptability
like 610 was the DOD-STD-2000, Volume 3.  The other standards like
MIL-STD-2000 and 2000, Rev A included acceptability as would be equivalent
to J-STD-001.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Wednesday, December 19, 2001 11:42 AM
To: [log in to unmask]
Subject: [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 13:21:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject:      Re: SMT Test points
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="------------A9486A385456B5B36B505A1E"

--------------A9486A385456B5B36B505A1E
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit


Samtec has these, but be careful of 2 pin SMT parts.  They want to break
off during handling.
we findly had to go 4 pin test points and use 2 pin only in center of
board or where protected
by tall components.  Also testpoints atleast Samtec damage anti static
bags that board assemblies are shipped in.

Greg Scott
Cray Inc

"Danny W. Harkins" wrote:

>
> Hello TN
>
> I am needing info on a SMT test pin. We need to be able to clip a
> scope probe to it and prefer to have it placeable by a P&P machine. Is
> anyone using anything of the likes.
>
> Thanks,
> Danny

--------------A9486A385456B5B36B505A1E
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<br>Samtec has these, but be careful of 2 pin SMT parts.&nbsp; They want
to break off during handling.
<br>we findly had to go 4 pin test points and use 2 pin only in center
of board or where protected
<br>by tall components.&nbsp; Also testpoints atleast Samtec damage anti
static bags that board assemblies are shipped in.
<p>Greg Scott
<br>Cray Inc
<p>"Danny W. Harkins" wrote:
<blockquote TYPE=CITE>&nbsp;
<br><font face="sans-serif"><font size=-1>Hello TN</font></font>
<p><font face="sans-serif"><font size=-1>I am needing info on a SMT test
pin. We need to be able to clip a scope probe to it and prefer to have
it placeable by a P&amp;P machine. Is anyone using anything of the likes.</font></font>
<p><font face="sans-serif"><font size=-1>Thanks,</font></font>
<br><font face="sans-serif"><font size=-1>Danny</font></font></blockquote>
</html>

--------------A9486A385456B5B36B505A1E--

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Date:         Wed, 19 Dec 2001 15:30:48 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
In-Reply-To:  <[log in to unmask]>
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Hans
Depending on the exact year, the 454 (Requirement 5?) reference could be to
any number of standards including WS-6536 or 45743, but you are very correct
they were eliminated without any identified replacement.  J-STD-001 has a
recent DoD adoption notice that I can send if you like, or you can get it
from IPC directly.

Mel

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Wednesday, December 19, 2001 1:08 PM
To: [log in to unmask]
Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


Hello Fellow Techies,

Thanks for the comments!

The original drawings are from the late 80's and we're conformally coating
the assembly instead of using an insulating foam so I get to change/improve
things.
MIL-STD-2000 came out after the drawings (which reference MIL-STD-454).  And
then there's the disconnect when both specs got canceled without an
identified replacement.  I'd rather identify a non-government specification
supporting DOD's decision to get out of the spec. business.  (They had
better solder the thing to J-STD-001 or I've got bigger problems than
getting a good coating.)

Happy Holidays.

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468



-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: Wednesday, December 19, 2001 5:10 PM
To: [log in to unmask]
Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


Hans
The only standard from the Mil specs that expressly addressed acceptability
like 610 was the DOD-STD-2000, Volume 3.  The other standards like
MIL-STD-2000 and 2000, Rev A included acceptability as would be equivalent
to J-STD-001.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Wednesday, December 19, 2001 11:42 AM
To: [log in to unmask]
Subject: [TN] Mil Spec Equivalent for IPC-A-610


Hi All,

Can anyone remember the equivalent Mil spec for IPC-A-610?
Is it MIL-STD-454?

Hans

Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468

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Date:         Wed, 19 Dec 2001 13:45:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Patrick Lam <[log in to unmask]>
Subject:      Wave solder 0603
Mime-Version: 1.0
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Hi TechNetters,

I need some advice on putting 0603 parts on the bottom. Should the footprint be
different than the one for reflow? What is the preferred footprint? Is it a good
pratice to use both glue dots and solder paste for wave sodering?

Thanks,
Patrick
This e-mail may contain SEL confidential information.  The opinions expressed
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Date:         Wed, 19 Dec 2001 17:10:43 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brad Saunders <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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The MIL and/or DOD-2000 are the easy answers, I am a "MIL" kinda guy and the
link is with reliability I would go with the J-STD-001 AND watch for ESD;
provided it meets existing process and foremost is in agreement with all
parties especially the Contract.  If the old doc is pre "2000" (the spec not
the year), my guess it is the beloved (and replaced by the 2000) MIL-A-28809.
 The 28809 brought us things like different color wires for rework verses
programmable, number of allowable reworks, double dipping of gold leads, no
conformal coat in the connector, discernible lead, etc...
aaah it was a wonderful life...
The even older weapons spec ~45743 (ish) was the one that stated "vias to be
solder plugged" it was a pretty hefty club for inspectors who woke up on
wrong side of bed.

Regardless of the spec used I recommend the old saying "when in doubt, spell
it out."  Good timing for solid heritage in ISO.

Boston Brad

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Date:         Wed, 19 Dec 2001 14:49:39 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      mesh size
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I am currently using a -325 mesh solder paste, we just started using 0201 components. Will a finer mesh solder give me more uniform solder application with the smaller apertures?
Dan

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<DIV><FONT size=2>I am currently using a -325 mesh solder paste, we just started
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Date:         Wed, 19 Dec 2001 20:24:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Adam Seychell <[log in to unmask]>
Subject:      Re: tin compatalbe etchants

This is good news to hear, Rudy. We are small workshop building PCBs for
prototyping and discovered the alkaline ammonium sulfate some years ago.
The reason for choosing of this etchant was the fact it can be
electrolytically regenerated. However it seems like one of the
slowest etchants around. The boards are all bright tin finish and since
alkaline sulfate is best known etchants for tin resists it'll be best to
stay with what I've got.

     Alkaline ammonium sulfate etching is virtually unheard of in Australian
pcb shops. I think we're the only mob in this country to be using it. Do you
know how common this etchant is used around the world ?

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Date:         Thu, 20 Dec 2001 10:56:57 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Vinit Verma <[log in to unmask]>
Subject:      Re: Wave solder 0603
MIME-Version: 1.0
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Hi Pat,

The footprint for wave soldering is ofcourse diferent than the one for
reflow, the difference being the extra protrusion of the pad outside the
component termination and also the gap between the two pads.

Also to be taken care is the orientation of the chip components. Preferably
they should be perpendicular to the PCB flow direction, thus enabling both
the pads to contact the wave simultaneously. This will have the most visible
effect on the tall bodied ceramic caps. In case the comps are parallel to
the PCB flow direction, for the tall bodied caps you'll see insufficient or
no solder at the trailing pad. However, if you have the dual wave soldering
machine, this effect will be minimized, if not eliminated.

For wave soldering SMTs, you need to glue them in order to hold them in
place during wave soldering. Where does the solder paste come into the
picture? What is your purpose of using the solder paste? Not required!

Hope this info is of use.

Regards
Vinit



-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: Thursday, December 20, 2001 3:16 AM
To: [log in to unmask]
Subject: [TN] Wave solder 0603


Hi TechNetters,

I need some advice on putting 0603 parts on the bottom. Should the footprint
be
different than the one for reflow? What is the preferred footprint? Is it a
good
pratice to use both glue dots and solder paste for wave sodering?

Thanks,
Patrick
This e-mail may contain SEL confidential information.  The opinions
expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution
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other use is prohibited.  If you received this e-mail in error, please
notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Thu, 20 Dec 2001 12:20:27 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         MA Ranganath/SMPLB/SEC/SANMAR <[log in to unmask]>
Subject:      iINFO ON PROCESSING OF MULTILAYER PCB's USING CIC AS CORE /BOND
MIME-Version: 1.0
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dear all,

We are member of the IPC for the last fifteen years and has been very
beneficial and extremely useful for us.

We have also been a manufacturer of  Multilayer PCBs of higher layer counts
(8 to 18 layers) with aluminum

core and thermal bond options .  These are being use for high end
professional end applications in the areas

of Space and Avionics.

We are interested in knowing the following details as per the subject
above.

a) Surface preparation of  CIC material of different grades and
thicknesses.
b) Material and method of  Insulation (electrical) for the different inner
layers and the CIC Core layer
c) Method  of  Insulation and Connectivity for the PTH  with CIC Core and
inner layers including Through,Burried,
    BLIND and Interconnection holes
d)Any specific parameters differences from the normal  CCL/PREPREG-FR4
combination for critical processes
   like electroless.desmear/etchback,drilling etc.,for the CIC  C ORE
Integrated PCBs

Request your valuable feedback to our queries

Regards,

M A Ranganath
GM - Engineering & Quality
Sanmar Micropack Limited
Plot No.16, Jigani Industrial Area,
Bangalore - 562 106. INDIA
Phone: 91 - 80 - 7825223/224/226/389
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Date:         Thu, 20 Dec 2001 13:10:07 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Edward Szpruch <[log in to unmask]>
Subject:      Laser drilled microvias & oxide subsitution
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Hi,
Some days ago I was told,that target pads in YAG laser drilled microvias are
suffering of "like pink-ring" phenomena after permanganate desmear if the
target layer is treated by "oxide substitution" based on peroxide ( such as
Multibond,Cobra bond,Circubond,Alphaprep etc).
What are comments on such statement??
Happy X-mass
Edward

Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel  ++972 3 9395050 , Fax  ++972 3 9309581
e-mail   [log in to unmask]

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Date:         Thu, 20 Dec 2001 06:51:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
MIME-Version: 1.0
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Is the adoption notice available on the IPC web site?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879



        -----Original Message-----
        From:   Mel Parrish [SMTP:[log in to unmask]]
        Sent:   Wednesday, December 19, 2001 6:31 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Mil Spec Equivalent for IPC-A-610

        Hans
        Depending on the exact year, the 454 (Requirement 5?) reference
could be to
        any number of standards including WS-6536 or 45743, but you are very
correct
        they were eliminated without any identified replacement.  J-STD-001
has a
        recent DoD adoption notice that I can send if you like, or you can
get it
        from IPC directly.

        Mel

        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 1:08 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hello Fellow Techies,

        Thanks for the comments!

        The original drawings are from the late 80's and we're conformally
coating
        the assembly instead of using an insulating foam so I get to
change/improve
        things.
        MIL-STD-2000 came out after the drawings (which reference
MIL-STD-454).  And
        then there's the disconnect when both specs got canceled without an
        identified replacement.  I'd rather identify a non-government
specification
        supporting DOD's decision to get out of the spec. business.  (They
had
        better solder the thing to J-STD-001 or I've got bigger problems
than
        getting a good coating.)

        Happy Holidays.

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468



        -----Original Message-----
        From: Mel Parrish [mailto:[log in to unmask]]
        Sent: Wednesday, December 19, 2001 5:10 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hans
        The only standard from the Mil specs that expressly addressed
acceptability
        like 610 was the DOD-STD-2000, Volume 3.  The other standards like
        MIL-STD-2000 and 2000, Rev A included acceptability as would be
equivalent
        to J-STD-001.

        Mel Parrish
        Soldering Technology International
        Madison, AL
        256 705 5530
        256 705 5538 Fax
        [log in to unmask]


        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 11:42 AM
        To: [log in to unmask]
        Subject: [TN] Mil Spec Equivalent for IPC-A-610


        Hi All,

        Can anyone remember the equivalent Mil spec for IPC-A-610?
        Is it MIL-STD-454?

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468


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Date:         Thu, 20 Dec 2001 15:31:35 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Environmental issues
X-To:         "Leadfree Forum." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

There have recently been some threads here on environmental issues, with
the usual messages from some that they were not in context with the
purpose of the list.

If I receive sufficient support (say, 20 or more messages), offline, to
my private e-mail address ( [log in to unmask] ), I'll open a Yahoo
newsgroup devoted entirely to environmental issues within industry. This
will be cost-free, open to all, without reasonable restriction of
subject, which will allow those who are interested to continue these
discussions to their heart's content and without upsetting the
sensitivities of those who consider such threads as inappropriate here.

Please note that this is not in competition with the IPC but as a
complement.

Best regards,

Brian

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Date:         Thu, 20 Dec 2001 09:03:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Vivari, John" <[log in to unmask]>
Subject:      Re: mesh size
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Dan,

Assuming your aspect ratio is right, a good -325 mesh solder paste is
capable and consistent to 0.4mm apertures so a smaller mesh should not be
necessary.  The benefit vs cost comparison is poor.  Below 0.4mm a -400 or
-500 mesh (depending upon aperture size) gives a marked improvement in
depoist consistency due to the ball size to aperture size ratio.  If your
paste has trouble with 0.5mm apertures in general, then a -400 is probably
in order for the 0201 process.

John Vivari
Technical Service Engineer
EFD Inc.
www.efd-inc.com
<mailto:[log in to unmask]>
Ph: 401-333-3800 x2204
Fx: 401-333-4954


Date:    Wed, 19 Dec 2001 14:49:39 -0800
From:    "Dan R. Johnson" <[log in to unmask]>
Subject: mesh size

I am currently using a -325 mesh solder paste, we just started using 0201
components. Will a finer mesh solder give me more uniform solder application
with the smaller apertures?
Dan

------_=_NextPart_001_01C1895F.15041862
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>Re:  mesh size</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Dan,</FONT>
</P>

<P><FONT SIZE=3D2>Assuming your aspect ratio is right, a good -325 mesh =
solder paste is capable and consistent to 0.4mm apertures so a smaller =
mesh should not be necessary.&nbsp; The benefit vs cost comparison is =
poor.&nbsp; Below 0.4mm a -400 or -500 mesh (depending upon aperture =
size) gives a marked improvement in depoist consistency due to the ball =
size to aperture size ratio.&nbsp; If your paste has trouble with 0.5mm =
apertures in general, then a -400 is probably in order for the 0201 =
process.</FONT></P>

<P><FONT SIZE=3D2>John Vivari</FONT>
<BR><FONT SIZE=3D2>Technical Service Engineer</FONT>
<BR><FONT SIZE=3D2>EFD Inc.</FONT>
<BR><FONT SIZE=3D2>www.efd-inc.com</FONT>
<BR><FONT SIZE=3D2>&lt;<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>&gt;&n=
bsp; </FONT>
<BR><FONT SIZE=3D2>Ph: 401-333-3800 x2204</FONT>
<BR><FONT SIZE=3D2>Fx: 401-333-4954</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Date:&nbsp;&nbsp;&nbsp; Wed, 19 Dec 2001 14:49:39 =
-0800</FONT>
<BR><FONT SIZE=3D2>From:&nbsp;&nbsp;&nbsp; &quot;Dan R. Johnson&quot; =
&lt;[log in to unmask]&gt;</FONT>
<BR><FONT SIZE=3D2>Subject: mesh size</FONT>
</P>

<P><FONT SIZE=3D2>I am currently using a -325 mesh solder paste, we =
just started using 0201 components. Will a finer mesh solder give me =
more uniform solder application with the smaller apertures?</FONT></P>

<P><FONT SIZE=3D2>Dan</FONT>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01C1895F.15041862--

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Date:         Thu, 20 Dec 2001 09:55:24 EST
Reply-To:     "TechNet E-Mail Forum." <Tec[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: tin compatible etchants
MIME-Version: 1.0
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When you suggest that the ammonium sulfate etchant is the "best" for Tin, you
have to watch your definition of "best", as most people would much prefer to
put on more Tin, and be able to etch faster.

Because most people are in a situation where they can return spent etchant,
and they want the speed, the sulfate based etchant is virtually unheard of in
the world.

I am not familiar with anyone using this etchant anymore, but I also am not
aware of what most of the east coast of the US is doing.

Rudy Sedlak

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Date:         Thu, 20 Dec 2001 10:08:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kris Keating <[log in to unmask]>
Subject:      Re: porosity of gold plating on nickel
MIME-Version: 1.0
Content-Type: text/plain

Hello,
I am trying to do a nitric acid porosity test on gold plating, but the lab
here does not have sodium sulfide crystals to make a polysulfide reagent for
the test.  Is there a suitable substitute reagent that can be used for this?

Kris

> -----Original Message-----
> From: Mark Mazzoli [SMTP:[log in to unmask]]
> Sent: Thursday, December 13, 2001 3:50 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] porosity of gold plating on nickel
>
> Hi Kris,
> Try IPC TM-650 2.3.24.2 Nitric Vapor Test.  That's the easiest one I'm
> aware of.
> Here's a link:http://www.ipc.org/html/2.3.24.2.pdf
>
> Mark Mazzoli
>
>
>
>
>
>
> At 02:30 PM 12/13/01 -0500, you wrote:
> >Does anyone know of a fairly simple method of determining porosity of
> gold
> >plating over nickel on a PCB?
> >
> >
> >Kristopher J. Keating
> >Technical Service Engineer
> >Circuit-Wise, Inc.
> >400 Sackett Point Rd.
> >North Haven, CT 06473
> >Tel. (203) 281-6511
> >Fax (203) 287-8409
> >
> >-------------------------------------------------------------------------
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> >
> >E-mail Archives
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> additional
> >information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> >ext.5315
> >-------------------------------------------------------------------------
> --------
> >
>
> --------------------------------------------------------------------------
> -------
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Date:         Thu, 20 Dec 2001 07:18:37 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dan R. Johnson" <[log in to unmask]>
Subject:      Re: mesh size
MIME-version: 1.0
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              boundary="Boundary_(ID_WEY3+PSCv9J/d7Y+U+EtTw)"

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Thanks John, this confirms what I thought. I don't know if you could say the aspect ratio is "right" but I am using a .13X.26mm paste pad. This is an Rf application and the design engineer is adamant that all component pads be as small as possible.
You mentioned the ball size to aperture size ratio, is there a "rule of thumb" for this?
Dan

--Boundary_(ID_WEY3+PSCv9J/d7Y+U+EtTw)
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT size=2>Thanks John, this confirms what I thought. I don't know if you
could say the aspect ratio is "right" but I am using a .13X.26mm paste pad. This
is an Rf application and the design engineer is adamant that all component pads
be as small as possible. </FONT></DIV>
<DIV><FONT size=2>You mentioned the ball size to aperture size ratio, is there a
"rule of thumb" for this?</FONT></DIV>
<DIV><FONT size=2>Dan</FONT></DIV></BODY></HTML>

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Date:         Thu, 20 Dec 2001 09:51:19 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Abrahamson <[log in to unmask]>
Subject:      Re: mesh size

Dan,

The rule of thumb that I had heard from a solder paste application engineer
was that you should be able to fit 8 solder balls across your smallest
aperture width.

I am not sure your 0201 solder paste aperture will work very well (unless
you made a typo).  .13mm x .26mm is really, really small.  If your foil size
is .076mm
(.003") or greater, your aspect ratio is below .6

You really need to be around .3mm x .35mm or .34mm square if your foil size
is .13mm.  This puts your AAR over .66

Steve A

> -----Original Message-----
> From: Dan R. Johnson [SMTP:[log in to unmask]]
> Sent: Thursday,December 20,2001 8:19 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] mesh size
>
> Thanks John, this confirms what I thought. I don't know if you could say
> the aspect ratio is "right" but I am using a .13X.26mm paste pad. This is
> an Rf application and the design engineer is adamant that all component
> pads be as small as possible.
> You mentioned the ball size to aperture size ratio, is there a "rule of
> thumb" for this?
> Dan

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Date:         Thu, 20 Dec 2001 11:51:37 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Environmental issues
MIME-Version: 1.0
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Brian,
       There is already a forum called compliancenet, just like technet but
compliance related.  Very little activity there but if you're interested it's
there.

Steve Wentz
Florida CirTech

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Date:         Thu, 20 Dec 2001 10:04:48 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Abrahamson <[log in to unmask]>
Subject:      Re: Wave solder 0603

Patrick,

If your adhesive process is capable of placing adhesive for 0603 components,
and you are using a selective solder process where solder paste is already
applied to the bottom side, then I would recommend solder paste.  This way
you do not need to alter your component pad size for the 0603 components.
You also do not need to worry about knocking off components during the
handling process at TH insertion.  Another thing is that if you have tall
actives on the bottom side, and are thus using a very thick selective solder
process, I noticed that the small amount of adhesive used for 0603s is not
always strong enough to handle the solder wave as it crashes into the
selective solder pallet opening.  These SMT adhesives were typically
designed to withstand 8lbs of shear that is seen over a typical single or
dual wave process.  Depending on your selective solder pallet thickness, the
part could see 2 or 3 times that force.

Steve A

> -----Original Message-----
> From: Patrick Lam [SMTP:[log in to unmask]]
> Sent: Wednesday,December 19,2001 2:46 PM
> To:   [log in to unmask]
> Subject:      [TN] Wave solder 0603
>
> Hi TechNetters,
>
> I need some advice on putting 0603 parts on the bottom. Should the
> footprint be
> different than the one for reflow? What is the preferred footprint? Is it
> a good
> pratice to use both glue dots and solder paste for wave sodering?
>
> Thanks,
> Patrick
> This e-mail may contain SEL confidential information.  The opinions
> expressed
> are not necessarily those of SEL.  Any unauthorized disclosure,
> distribution or
> other use is prohibited.  If you received this e-mail in error, please
> notify
> the sender, permanently delete it, and destroy any printout.  Thank you.
>
> --------------------------------------------------------------------------
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Date:         Thu, 20 Dec 2001 10:12:32 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Abrahamson <[log in to unmask]>
Subject:      Re: white powder on leads

Andre,

The powder could simple just be oxides (tin oxides mostly).  The flux will
remove them from the bond area, and the loose oxides will float on the
solder and often end up at the top areas of the solder joint.  The area
untouched by the flux will also have some oxidation.
I was going to make a joke about powdered donut residue, but I realize that
the technet is pretty serious.  Happy Holidays everyone...he he..

Steve A

> -----Original Message-----
> From: Andre Leclair [SMTP:[log in to unmask]]
> Sent: Wednesday,December 19,2001 6:57 AM
> To:   [log in to unmask]
> Subject:      [TN] white powder on leads
>
> Hi All
>
> Here is another residue issue
>
> We have an assembly which has a white residue remaining after wash.
> The board is completely SMT (WS609) using a DI-Wash process,  the board is
> spotless except for one location.  The location is a QFP (from CRONTEL),
> the white powder is on the leads of the IC only.  There is not a spot on
> the PCB.
>
> The Powder dry brushes extremly easily. On a few of the leads ( usually
> about half way up the lead, nver near the joint)after brushing there is
> evidence of flux residue( yellow sort of like Crystal Flux residue) in
> spots.
> We have put a few boards through the Omega with readings lower then
> 2.3microgram/sq.inch.
>
> Could this be something the part manufacture has left/put on the leads? I
> have noticed that the plating is thin on the leads (exposed copper on the
> faces) the leads also look like sheared stock ( exposed copper on the
> sides)
>
> Thanks
> Andre
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date:         Thu, 20 Dec 2001 09:06:02 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Lush, Dorothy (FPTI)" <[log in to unmask]>
Subject:      Re: Voiding on BGA with uVias
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Peter,

Voiding is worse with a poorly formed or damaged via/micro-via. I have seen
some crushed vias where the side wall buckle produce some stupendous
voiding. Voiding happens worse with vias that are narrower at the top
surface of the board because solder has a more difficlt time filling the
hole at solder printing. Remember most no-clean solder is 50% flux by volume
and the volatiles need to do their thing and leave. Some think that trapped
volatiles and flux when they cannot leave become viscous clumps in the via
hole and then when the eutechtic BGA ball collapses the clump moves up into
the ball. This gets worse with a site that goes through a double reflow
process. One suggestion is to fill and plate over these vias so this cannot
happen. Another suggestion is to offset the via from the center to about 2
mils from the pad edge so the clumping happens outside the component ball.

Regards,

Dorothy Lush

-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Tuesday, December 18, 2001 11:20 PM
To: [log in to unmask]
Subject: [TN] Voiding on BGA with uVias


Hello,

We have encountered major BGA voiding issue. The void is sometimes up to
70% of the joint. Under X-ray inspection we found a blind 0.006" uVia,
0.01" deep under each void. Other BGA solder joint on board w/o uVias do
not have any void problems. Board is gold over Nickel finish and 2mm
thick.

Things we tried:
Reflow profile - WS/ no-clean paste, longer soak
Washing/ baking the bare PCB
Reworked by cleaning the uVias/pads and filled with solder but still
seeing void

Has anyone seen this before? Micro-sectioning clearly showed the void
originated from the uVia. We are trying to convince the board house that
it's not our process.


Rgds,
Peter



_________________________________________________________
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Get your free @yahoo.com address at http://mail.yahoo.com

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charset=3Diso-8859-1">
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<TITLE>RE: [TN] Voiding on BGA with uVias</TITLE>
</HEAD>
<BODY>
<BR>

<P><FONT SIZE=3D2>Peter,</FONT>
</P>

<P><FONT SIZE=3D2>Voiding is worse with a poorly formed or damaged =
via/micro-via. I have seen some crushed vias where the side wall buckle =
produce some stupendous voiding. Voiding happens worse with vias that =
are narrower at the top surface of the board because solder has a more =
difficlt time filling the hole at solder printing. Remember most =
no-clean solder is 50% flux by volume and the volatiles need to do =
their thing and leave. Some think that trapped volatiles and flux when =
they cannot leave become viscous clumps in the via hole and then when =
the eutechtic BGA ball collapses the clump moves up into the ball. This =
gets worse with a site that goes through a double reflow process. One =
suggestion is to fill and plate over these vias so this cannot happen. =
Another suggestion is to offset the via from the center to about 2 mils =
from the pad edge so the clumping happens outside the component =
ball.</FONT></P>

<P><FONT SIZE=3D2>Regards,</FONT>
</P>

<P><FONT SIZE=3D2>Dorothy Lush</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Peter Lee [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Tuesday, December 18, 2001 11:20 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Voiding on BGA with uVias</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Hello,</FONT>
</P>

<P><FONT SIZE=3D2>We have encountered major BGA voiding issue. The void =
is sometimes up to</FONT>
<BR><FONT SIZE=3D2>70% of the joint. Under X-ray inspection we found a =
blind 0.006&quot; uVia,</FONT>
<BR><FONT SIZE=3D2>0.01&quot; deep under each void. Other BGA solder =
joint on board w/o uVias do</FONT>
<BR><FONT SIZE=3D2>not have any void problems. Board is gold over =
Nickel finish and 2mm</FONT>
<BR><FONT SIZE=3D2>thick.</FONT>
</P>

<P><FONT SIZE=3D2>Things we tried:</FONT>
<BR><FONT SIZE=3D2>Reflow profile - WS/ no-clean paste, longer =
soak</FONT>
<BR><FONT SIZE=3D2>Washing/ baking the bare PCB</FONT>
<BR><FONT SIZE=3D2>Reworked by cleaning the uVias/pads and filled with =
solder but still</FONT>
<BR><FONT SIZE=3D2>seeing void</FONT>
</P>

<P><FONT SIZE=3D2>Has anyone seen this before? Micro-sectioning clearly =
showed the void</FONT>
<BR><FONT SIZE=3D2>originated from the uVia. We are trying to convince =
the board house that</FONT>
<BR><FONT SIZE=3D2>it's not our process.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Rgds,</FONT>
<BR><FONT SIZE=3D2>Peter</FONT>
</P>
<BR>
<BR>

<P><FONT =
SIZE=3D2>_________________________________________________________</FONT=
>
<BR><FONT SIZE=3D2>Do You Yahoo!?</FONT>
<BR><FONT SIZE=3D2>Get your free @yahoo.com address at <A =
HREF=3D"http://mail.yahoo.com" =
TARGET=3D"_blank">http://mail.yahoo.com</A></FONT>
</P>

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Date:         Thu, 20 Dec 2001 12:32:22 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Joseph Fjelstad <[log in to unmask]>
Subject:      Re: Environmental issues
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Hello Steve,

"Compliance" as a term seems to be more in tune with navigating the
bureaucracy that oversees policy and less about visiting upon the real
issues. Which is what I believe Brian is proposing.

Kind regards,
Joe

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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hello Steve,
<BR>
<BR>"Compliance" as a term seems to be more in tune with navigating the bureaucracy that oversees policy and less about visiting upon the real issues. Which is what I believe Brian is proposing.
<BR>
<BR>Kind regards,
<BR>Joe &nbsp;</FONT></HTML>

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Date:         Thu, 20 Dec 2001 13:29:16 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Vivari, John" <[log in to unmask]>
Subject:      Re: mesh size
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Dan,

First, I need to correct myself.  -325 mesh solder paste should be capable
to 0.2mm apertures.  You don't need -400 till you hit 0.15mm and -500 at
0.1mm.

There is a rule of thumb.  The smallest dimension on an aperture should be
no less than 1.5 times the thickness of the stencil foil.  So, for a .15mm x
.26mm aperture, the maximum foil thickness should less than or equal to 0.15
/ 1.5 = 0.1mm = about 4 mils.  You are probably better off going with 3mil
foil just to be on the safe side and I sincerely hope you are using metal
blades of some sort.

As a point of reference to work that has been done with 0201s, the May 2001
Circuits Assembly publication has a well written report on 0201 processing.
The pad sizes used in their study are quite a bit larger than your designer
proposes and that leads me to wonder what testing he has performed to ensure
his design is sound.  At roughly 50% by volume metal in solder paste, you
have very little alloy to go around in your proposed deposit.

John Vivari
Technical Service Engineer
EFD Inc.
Ph: 401-333-3800 x2204
Fx: 401-333-4954






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<TITLE>Re:  mesh size</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Dan,</FONT>
</P>

<P><FONT SIZE=3D2>First, I need to correct myself.&nbsp; -325 mesh =
solder paste should be capable to 0.2mm apertures.&nbsp; You don't need =
-400 till you hit 0.15mm and -500 at 0.1mm. </FONT></P>

<P><FONT SIZE=3D2>There is a rule of thumb.&nbsp; The smallest =
dimension on an aperture should be no less than 1.5 times the thickness =
of the stencil foil.&nbsp; So, for a .15mm x .26mm aperture, the =
maximum foil thickness should less than or equal to 0.15 / 1.5 =3D =
0.1mm =3D about 4 mils.&nbsp; You are probably better off going with =
3mil foil just to be on the safe side and I sincerely hope you are =
using metal blades of some sort.</FONT></P>

<P><FONT SIZE=3D2>As a point of reference to work that has been done =
with 0201s, the May 2001 Circuits Assembly publication has a well =
written report on 0201 processing.&nbsp; The pad sizes used in their =
study are quite a bit larger than your designer proposes and that leads =
me to wonder what testing he has performed to ensure his design is =
sound.&nbsp; At roughly 50% by volume metal in solder paste, you have =
very little alloy to go around in your proposed deposit.</FONT></P>

<P><FONT SIZE=3D2>John Vivari</FONT>
<BR><FONT SIZE=3D2>Technical Service Engineer</FONT>
<BR><FONT SIZE=3D2>EFD Inc.</FONT>
<BR><FONT SIZE=3D2>Ph: 401-333-3800 x2204</FONT>
<BR><FONT SIZE=3D2>Fx: 401-333-4954</FONT>
</P>
<BR>
<BR>
<BR>
<BR>

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Date:         Thu, 20 Dec 2001 16:45:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guy Ramsey <[log in to unmask]>
Subject:      Favorite SPC tools
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Is anyone out there using a plant wide SPC software tool?

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Date:         Thu, 20 Dec 2001 17:27:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Dan Cavaliere>" <[log in to unmask]>
Subject:      Re: Favorite SPC tools
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We are using a program called InfinityQS throughout our plant.  We are
using it for both variable and attribute data.
Go to http://www.infinityqs.com

Dan Cavaliere
Baxter Healthcare





Guy Ramsey <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
12/20/01 04:45 PM
Please respond to "TechNet E-Mail Forum."


        To:     [log in to unmask]
        cc:
        Subject:        [TN] Favorite SPC tools

Is anyone out there using a plant wide SPC software tool?

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<br><font size=3D2 face=3D"sans-serif">We are using a program called Infini=
tyQS throughout our plant. &nbsp;We are using it for both variable and attr=
ibute data.</font>
<br><font size=3D2 face=3D"sans-serif">Go to </font><a href=3D"&#254;u"><fo=
nt size=3D2 color=3Dblue face=3D"sans-serif">http://www.infinityqs.com</fon=
t></a>
<br>
<br><font size=3D2 face=3D"sans-serif">Dan Cavaliere</font>
<br><font size=3D2 face=3D"sans-serif">Baxter Healthcare</font>
<br>
<br>
<br>
<br>
<table width=3D100%>
<tr valign=3Dtop>
<td>
<td><font size=3D1 face=3D"sans-serif"><b>Guy Ramsey &lt;[log in to unmask]
&gt;</b></font>
<br><font size=3D1 face=3D"sans-serif">Sent by: TechNet &lt;[log in to unmask]
&gt;</font>
<p><font size=3D1 face=3D"sans-serif">12/20/01 04:45 PM</font>
<br><font size=3D1 face=3D"sans-serif">Please respond to &quot;TechNet E-Ma=
il Forum.&quot;</font>
<br>
<td><font size=3D1 face=3D"Arial">&nbsp; &nbsp; &nbsp; &nbsp; </font>
<br><font size=3D1 face=3D"sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; To: &nbs=
p; &nbsp; &nbsp; &nbsp;[log in to unmask]</font>
<br><font size=3D1 face=3D"sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; cc: &nbs=
p; &nbsp; &nbsp; &nbsp;</font>
<br><font size=3D1 face=3D"sans-serif">&nbsp; &nbsp; &nbsp; &nbsp; Subject:=
 &nbsp; &nbsp; &nbsp; &nbsp;[TN] Favorite SPC tools</font></table>
<br>
<br><font size=3D2 face=3D"Courier New">Is anyone out there using a plant w=
ide SPC software tool?<br>
<br>
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Date:         Thu, 20 Dec 2001 17:30:40 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mel Parrish <[log in to unmask]>
Subject:      Re: Mil Spec Equivalent for IPC-A-610
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Hi Jim!
Didn't find it on the site, but IPC is fixin (Alabamese) to put it on. In
fact it may be there by time this is posted.  It is also attached.

Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Thursday, December 20, 2001 3:51 AM
To: [log in to unmask]
Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


Is the adoption notice available on the IPC web site?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879



        -----Original Message-----
        From:   Mel Parrish [SMTP:[log in to unmask]]
        Sent:   Wednesday, December 19, 2001 6:31 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Mil Spec Equivalent for IPC-A-610

        Hans
        Depending on the exact year, the 454 (Requirement 5?) reference
could be to
        any number of standards including WS-6536 or 45743, but you are very
correct
        they were eliminated without any identified replacement.  J-STD-001
has a
        recent DoD adoption notice that I can send if you like, or you can
get it
        from IPC directly.

        Mel

        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 1:08 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hello Fellow Techies,

        Thanks for the comments!

        The original drawings are from the late 80's and we're conformally
coating
        the assembly instead of using an insulating foam so I get to
change/improve
        things.
        MIL-STD-2000 came out after the drawings (which reference
MIL-STD-454).  And
        then there's the disconnect when both specs got canceled without an
        identified replacement.  I'd rather identify a non-government
specification
        supporting DOD's decision to get out of the spec. business.  (They
had
        better solder the thing to J-STD-001 or I've got bigger problems
than
        getting a good coating.)

        Happy Holidays.

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468



        -----Original Message-----
        From: Mel Parrish [mailto:[log in to unmask]]
        Sent: Wednesday, December 19, 2001 5:10 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hans
        The only standard from the Mil specs that expressly addressed
acceptability
        like 610 was the DOD-STD-2000, Volume 3.  The other standards like
        MIL-STD-2000 and 2000, Rev A included acceptability as would be
equivalent
        to J-STD-001.

        Mel Parrish
        Soldering Technology International
        Madison, AL
        256 705 5530
        256 705 5538 Fax
        [log in to unmask]


        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 11:42 AM
        To: [log in to unmask]
        Subject: [TN] Mil Spec Equivalent for IPC-A-610


        Hi All,

        Can anyone remember the equivalent Mil spec for IPC-A-610?
        Is it MIL-STD-454?

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468


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=========================================================================
Date:         Thu, 20 Dec 2001 17:43:13 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jack Crawford <[log in to unmask]>
Subject:      Re: DoD Adoption of IPC/EIA J-STD-001C and IPC-HDBK-001C
Mime-Version: 1.0
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No, not right now but....  Post holiday I'll set it up as a download link =
from the bookstore but APEX is on my shoulders right now.  In the =
meantime, I've set up a rule so you can download it.

send an email to: [log in to unmask]

subject line copy in this character string just like it is here: request =
J-001-DOD

body can be anything but best to put your name/phone so we can assist if =
there are any problems.

jack

>>> [log in to unmask] 12/20/01 05:51AM >>>
Is the adoption notice available on the IPC web site?

Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879



        -----Original Message-----
        From:   Mel Parrish [SMTP:[log in to unmask]]
        Sent:   Wednesday, December 19, 2001 6:31 PM
        To:     [log in to unmask]
        Subject:        Re: [TN] Mil Spec Equivalent for IPC-A-610

        Hans
        Depending on the exact year, the 454 (Requirement 5?) reference
could be to
        any number of standards including WS-6536 or 45743, but you are =
very
correct
        they were eliminated without any identified replacement.  =
J-STD-001
has a
        recent DoD adoption notice that I can send if you like, or you can
get it
        from IPC directly.

        Mel

        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 1:08 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hello Fellow Techies,

        Thanks for the comments!

        The original drawings are from the late 80's and we're conformally
coating
        the assembly instead of using an insulating foam so I get to
change/improve
        things.
        MIL-STD-2000 came out after the drawings (which reference
MIL-STD-454).  And
        then there's the disconnect when both specs got canceled without =
an
        identified replacement.  I'd rather identify a non-government
specification
        supporting DOD's decision to get out of the spec. business.  (They
had
        better solder the thing to J-STD-001 or I've got bigger problems
than
        getting a good coating.)

        Happy Holidays.

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We =
Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468



        -----Original Message-----
        From: Mel Parrish [mailto:[log in to unmask]]
        Sent: Wednesday, December 19, 2001 5:10 PM
        To: [log in to unmask]
        Subject: Re: [TN] Mil Spec Equivalent for IPC-A-610


        Hans
        The only standard from the Mil specs that expressly addressed
acceptability
        like 610 was the DOD-STD-2000, Volume 3.  The other standards like
        MIL-STD-2000 and 2000, Rev A included acceptability as would be
equivalent
        to J-STD-001.

        Mel Parrish
        Soldering Technology International
        Madison, AL
        256 705 5530
        256 705 5538 Fax
        [log in to unmask]


        -----Original Message-----
        From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M
Civ
        WRALC/LUGE
        Sent: Wednesday, December 19, 2001 11:42 AM
        To: [log in to unmask]
        Subject: [TN] Mil Spec Equivalent for IPC-A-610


        Hi All,

        Can anyone remember the equivalent Mil spec for IPC-A-610?
        Is it MIL-STD-454?

        Hans

        Integrity First  -  Service Before Self  -  Excellence in All We =
Do
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        Hans M. Hinners
        Electronics Engineer
        Warner Robins - Air Logistics Center (WR-ALC/LUGE)
        226 Cochran Street
        Robins AFB GA 31098-1622

        mailto:[log in to unmask]

        Com: (478) 926 - 5224
        Fax:   (478) 926 - 4911
        DSN Prefix: 468


---------------------------------------------------------------------------=
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the BODY (NOT the subject field): SIGNOFF Technet
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Search previous postings at: www.ipc.org > On-Line Resources & Databases > =
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--=_8BD6988A.60016763
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1></FONT>No, not right now but....&nbsp; Post holiday =
I'll set=20
it up as a download link from the bookstore but APEX is on my shoulders =
right=20
now.&nbsp; In the meantime, I've set up a rule so you can download =
it.</DIV>
<DIV>&nbsp;</DIV>
<DIV>send an email to: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></DIV>
<DIV>&nbsp;</DIV>
<DIV>subject line copy in this character string just like it is here: =
request=20
J-001-DOD</DIV>
<DIV>&nbsp;</DIV>
<DIV>body can be anything but best to put your name/phone so we can assist =
if=20
there are any problems.</DIV>
<DIV>&nbsp;</DIV>
<DIV>jack<BR><BR>&gt;&gt;&gt; [log in to unmask] 12/20/01 05:51AM=20
&gt;&gt;&gt;<BR>Is the adoption notice available on the IPC web site?<BR><B=
R>Jim=20
Marsico<BR>Senior Engineer<BR>Production Engineering<BR>EDO Electronics =
Systems=20
Group<BR>[log in to unmask] &lt;<A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>&gt=
;<BR>631-595-5879<BR><BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
=20
-----Original Message-----<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20=

From:&nbsp;&nbsp; Mel Parrish=20
[SMTP:[log in to unmask]]<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;=20
Sent:&nbsp;&nbsp; Wednesday, December 19, 2001 6:31=20
PM<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp;&nbsp;&nbsp;&nbsp=
;=20
[log in to unmask]<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Mil Spec =
Equivalent=20
for IPC-A-610<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Hans<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Depending on the exact =
year,=20
the 454 (Requirement 5?) reference<BR>could be=20
to<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; any number of standards=20=

including WS-6536 or 45743, but you are=20
very<BR>correct<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; they were=20
eliminated without any identified replacement.&nbsp; J-STD-001<BR>has=20
a<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; recent DoD adoption notice =
that=20
I can send if you like, or you can<BR>get=20
it<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from IPC=20
directly.<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Mel<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -----Original=20
Message-----<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; From: TechNet =
[<A=20
href=3D"mailto:[log in to unmask]]On">mailto:[log in to unmask]]On</A> Behalf Of =
Hinners=20
Hans M<BR>Civ<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
WRALC/LUGE<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent: Wednesday,=
=20
December 19, 2001 1:08 PM<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
To:=20
[log in to unmask]<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject: Re: =
[TN]=20
Mil Spec Equivalent for=20
IPC-A-610<BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hello =
Fellow=20
Techies,<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Thanks for =
the=20
comments!<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The original=20=

drawings are from the late 80's and we're=20
conformally<BR>coating<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
the=20
assembly instead of using an insulating foam so I get=20
to<BR>change/improve<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
things.<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MIL-STD-2000 came =
out=20
after the drawings (which reference<BR>MIL-STD-454).&nbsp;=20
And<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; then there's the =
disconnect=20
when both specs got canceled without=20
an<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; identified replacement.&nb=
sp;=20
I'd rather identify a=20
non-government<BR>specification<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;=20
supporting DOD's decision to get out of the spec. business.&nbsp;=20
(They<BR>had<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; better solder =
the=20
thing to J-STD-001 or I've got bigger=20
problems<BR>than<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; getting a =
good=20
coating.)<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Happy=20
Holidays.<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Hans<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Integrity First&nbsp=
;=20
-&nbsp; Service Before Self&nbsp; -&nbsp; Excellence in All We=20
Do<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;=20
Hans M. Hinners<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Electronics=
=20
Engineer<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Warner Robins - =
Air=20
Logistics Center (WR-ALC/LUGE)<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 226=20
Cochran Street<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Robins AFB =
GA=20
31098-1622<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
l</A><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Com: (478) 926 - 5224<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Fax:&nbsp;&nbsp; (478) 926 - 4911<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;=20
DSN Prefix: 468<BR><BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
=20
-----Original Message-----<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
From:=20
Mel Parrish [<A=20
href=3D"mailto:[log in to unmask]]">mailto:[log in to unmask]
OM]</A><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Sent: Wednesday, December 19, 2001 5:10=20
PM<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To:=20
[log in to unmask]<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject: Re: =
[TN]=20
Mil Spec Equivalent for=20
IPC-A-610<BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Hans<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The only standard from =
the=20
Mil specs that expressly=20
addressed<BR>acceptability<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
like=20
610 was the DOD-STD-2000, Volume 3.&nbsp; The other standards=20
like<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MIL-STD-2000 and 2000, =
Rev A=20
included acceptability as would=20
be<BR>equivalent<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; to=20
J-STD-001.<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mel=20
Parrish<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Soldering Technology=
=20
International<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Madison,=20
AL<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705=20
5530<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256 705 5538=20
Fax<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
[log in to unmask]<BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;=20
-----Original Message-----<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
From:=20
TechNet [<A href=3D"mailto:[log in to unmask]]On">mailto:[log in to unmask]]On</A=
>=20
Behalf Of Hinners Hans M<BR>Civ<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;=20
WRALC/LUGE<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sent: Wednesday,=
=20
December 19, 2001 11:42 AM<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
To:=20
[log in to unmask]<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Subject: =
[TN] Mil=20
Spec Equivalent for=20
IPC-A-610<BR><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hi=20
All,<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Can anyone remember =
the=20
equivalent Mil spec for IPC-A-610?<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;=20
Is it MIL-STD-454?<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Hans<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Integrity First&nbsp=
;=20
-&nbsp; Service Before Self&nbsp; -&nbsp; Excellence in All We=20
Do<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;=20
Hans M. Hinners<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Electronics=
=20
Engineer<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Warner Robins - =
Air=20
Logistics Center (WR-ALC/LUGE)<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 226=20
Cochran Street<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Robins AFB =
GA=20
31098-1622<BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
l</A><BR><BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Com: (478) 926 - 5224<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Fax:&nbsp;&nbsp; (478) 926 - 4911<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;=20
DSN Prefix:=20
468<BR><BR><BR>------------------------------------------------------------=
----------------<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
-----<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Technet Mail List =
provided=20
as a free service by IPC using=20
LISTSERV<BR>1.8d<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To =
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To=20
temporarily halt delivery of Technet send the following=20
message:<BR>SET<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Technet=20
NOMAIL<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Search previous =
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at: www.ipc.org &gt; On-Line Resources &amp;<BR>Databases=20
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Archives<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Please visit IPC =
web site=20
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href=3D"http://www.ipc.org/html/forum.htm)">http://www.ipc.org/html/forum.h=
tm)</A>=20
for<BR>additional<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; information=
, or=20
contact Keach Sasamori at [log in to unmask]
or<BR>847-509-9700<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
ext.5315<BR><BR>-----------------------------------------------------------=
-----------------<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
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tm)</A>=20
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Date:         Thu, 20 Dec 2001 15:55:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Mcmaster, Michael" <[log in to unmask]>
Subject:      Re: Warp age in FR-4
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Bill

Can you give the specifics of the construction?  The board may be all FR4
but not all FR4 is created equal.  Are the design and the materials of
construction symmetric about the board centerline?  Any deviation from that
could contribute to warpage.  It's not just the relative position of the
plane layers and signal layers.  Depending on the cores and prepregs used to
build the board, the resin % can vary from the low 40s for 7628 glass to the
high 70s for 106.  I've seen boards that are all the same type of material
but have a preponderance of lower resin cores and prepregs on one side and
higher resin materials on the other with warpage.  Not 2.4% like you're
seeing, but more than was originally anticipated.  The industry usually only
publishes a single value for X/Y CTE for materials like FR4 but there's
actually a significant difference between FR4 that is 40% resin and 70%.

If the stackup is balanced, then you are probably looking at fab-related
issues.  Cool down as mentioned.  Or possible cross grain.  I think another
post alluded to this.  The process of making prepreg imparts a stress in the
fabric as it is pulled through the treater tower.  This is usually called
machine or grain direction.  The induced stress means that the material has
different CTE in the machine and transverse directions.  Even a balanced
board can have warpage if the grain direction is mixed in an unsymmetric
way.

There are two schools of thought on this.  One says that you just avoid
mixing grain direction.  The other says that you intentionally mix it,
though you have to maintain symmetry.  The latter is a lot more difficult to
do correctly and much more prone to mistakes.  There are also a lot of
constructions that don't lend themselves to maintaining the symmetry.

If it is cross grain, I'd also consider it the responsibility of the
fabricator.

> ----------
> From:         Safavi-Bayat Shahed[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.
> Sent:         Wednesday, December 19, 2001 5:44 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Warp age in FR-4
>
> Bill
> Are you sure that the material is FR4 on top and bottom layer?
> The reason I ask is I once used Rogers on component side and FR4 on
> circuit
> side and the board had
> warp age and the reason was mixing the two material.
> Other than that I think your fab shop kind of missed it this time.
>
> -----Original Message-----
> From: Kasprzak, Bill (sys) USX [mailto:[log in to unmask]]
> Sent: Wednesday, December 19, 2001 8:26 AM
> To: [log in to unmask]
> Subject: [TN] Warpage in FR-4
>
>
> Holiday Greetings to one and all,
>
> I have an 8 layer FR-4 board that was supposedly built IAW IPC-6011, Class
> 3
> and IPC-6012, Class 3. The board itself appears to be like any other
> board,
> .062" thick, no unusual ground plane layers etc. After wave soldering this
> assembly severely warped. Looking at the bare boards, they are also
> warped,
> but can be shaped into a straight position by bending a little. (I
> shouldn't
> have to do this.)
>
> Not being up to date on board fabrication techniques, was there anything
> in
> the fab process that could lead to a warped board? We're talking a 3/16"
> warp over an 8" length.. Or was there something at my assembly end that is
> introducing the warp. The boards were run in a titanium picture frame
> pallet.
>
> Your thoughts and ideas are greatly appreciated.
>
> Bill Kasprzak
> Moog Inc., Electronic Assembly Engineering
>
> --------------------------------------------------------------------------
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Date:         Thu, 20 Dec 2001 16:04:48 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Kiet Dang <[log in to unmask]>
Subject:      signoff
MIME-Version: 1.0
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Date:         Thu, 20 Dec 2001 17:06:40 -0800
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Sender:       TechNet <[log in to unmask]>
From:         "Lush, Dorothy (FPTI)" <[log in to unmask]>
Subject:      SET Technet NOMAIL
MIME-Version: 1.0
Content-Type: multipart/alternative;
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This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

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Please set nomail for Dec 21, 01-Jan7, 02

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
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Date:         Thu, 20 Dec 2001 19:09:45 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Richard Hamilton <[log in to unmask]>
Subject:      Re: Rejected posting to [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Boy, you just can't get anything past ole Jefry, can you? Or, can you???????

I'm sorry but I can not let this pass considering the initial drive to do
this anyway!!

Please be sure to read the original message as quoted below

Richard

At 08:09 PM 12/20/01 -0600, you wrote:
>Your  message is  being returned  to you  unprocessed because  it
>looks  like a
>LISTSERV command, rather than material intended for distribution to the
>members
>of the TechNet list. Please note that  LISTSERV commands must ALWAYS be
>sent to
>the LISTSERV address; if it was indeed  a command you were attempting to
>issue,
>please send it again to [log in to unmask] for execution. Otherwise,
>please
>accept our apologies  and try to rewrite the message  with a slightly
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>quotation marks, insert a line of dashes at the beginning of your message,
>etc.




>Date: Thu, 20 Dec 2001 18:18:32 -0800
>To: [log in to unmask]
>From: Richard Hamilton <[log in to unmask]>
>Subject: Please set Greetings
>Mime-Version: 1.0
>Content-Type: text/plain; charset="us-ascii"; format=flowed
>
>Set Greetings to all @ Happy for Christmas
>
>and
>
>Set Greetings to all @ Prosperous for New Year
>
>Set Outta Here to Richard Hamilton for awhile.
>
>EOT

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Date:         Fri, 21 Dec 2001 07:02:12 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Atkinson, Neil" <[log in to unmask]>
Subject:      Re: Favorite SPC tools
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I would be careful with this one!

SPC works well and gives advantages when people get in touch with the data
and the process.  Software can sometimes become a means to "do SPC" and not
to control the process because it can make people feel detached from the
data and by doing too much of the work can result in a lack of understanding
of variation, and if all a company gets out of an SPC programme is that
everyone understands variation, it has been worth the effort!

Neil


 -----Original Message-----
From:   Guy Ramsey [mailto:[log in to unmask]]
Sent:   20 December 2001 21:45
Subject:        Favorite SPC tools

Is anyone out there using a plant wide SPC software tool?

_____________________________________________________________________
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Date:         Fri, 21 Dec 2001 02:12:35 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rod Smith <[log in to unmask]>
Subject:      Rod Smith/Endicott/IBM is out of the office.
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

I will be out of the office starting December 21, 2001 and will not return
until January 2, 2002.

I will respond to your message when I return.

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Date:         Fri, 21 Dec 2001 14:19:53 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: Voiding on BGA with uVias
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Peter,

We recently had some problems with voiding in the solderjoints of ceramic =
BGA's on pads with via's. Per design the via's are overplated with copper =
and leadtin, but the actual bare boards had some problems with dimples and =
sometimes bad overplating.
So for one batch we made notes of the pads that were not according to the =
design specificaytion, and afterwards we tried to correlate this with the =
voids. Correlation was 100%. No void if the pad was flat and had good =
plating, and voids (up to 50% in diameter !!) whenever the pad didn't look =
right.

Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net

>>> Peter Lee <[log in to unmask]> 12/19 8:20 am >>>
Hello,

We have encountered major BGA voiding issue. The void is sometimes up to
70% of the joint. Under X-ray inspection we found a blind 0.006" uVia,
0.01" deep under each void. Other BGA solder joint on board w/o uVias do
not have any void problems. Board is gold over Nickel finish and 2mm
thick.

Things we tried:
Reflow profile - WS/ no-clean paste, longer soak
Washing/ baking the bare PCB
Reworked by cleaning the uVias/pads and filled with solder but still
seeing void

Has anyone seen this before? Micro-sectioning clearly showed the void
originated from the uVia. We are trying to convince the board house that
it's not our process.


Rgds,
Peter



_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com=20

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Date:         Fri, 21 Dec 2001 09:12:01 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Re: Favorite SPC tools

Neil's words remind me of what I read that Deming said one time when asked
if he would summarize his message to management:  Understand variability.

Quesenberry in "SPC Methods for Quality Improvement" says the real purpose
of SPC is "to establish when a process can reasonably be considered stable
or in control".

An unschooled but savvy mechanical engineer told me one time when we were
discussing SPC that "the best thing you can do for those machines is to
leave them alone".

Sorry I don't know of any plant-wide tools to use.  As I've suggested to
TechNet in the past, look into Quesenberry's Q-statistics for SPC if you
are starting from the beginning.

Lou Hart

-----Original Message-----
From:   Atkinson, Neil [SMTP:[log in to unmask]]
Sent:   Friday, December 21, 2001 2:02 AM
To:     [log in to unmask]
Subject:        Re: [TN] Favorite SPC tools

I would be careful with this one!

SPC works well and gives advantages when people get in touch with the data
and the process.  Software can sometimes become a means to "do SPC" and not
to control the process because it can make people feel detached from the
data and by doing too much of the work can result in a lack of
understanding
of variation, and if all a company gets out of an SPC programme is that
everyone understands variation, it has been worth the effort!

Neil


 -----Original Message-----
From:   Guy Ramsey [mailto:[log in to unmask]]
Sent:   20 December 2001 21:45
Subject:        Favorite SPC tools

Is anyone out there using a plant wide SPC software tool?

_____________________________________________________________________
This message has been checked for all known viruses by Star Internet
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Star Internet for details on the Virus Scanning Service.

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Date:         Fri, 21 Dec 2001 08:32:38 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Favorite SPC tools
X-To:         Louis Hart <[log in to unmask]>

Lou,

This always is a good discussion. The best point in the discussion is about
control. Juran said when a process is in a state of control, product quality
is consistent though it may be consistently good or bad. From this there is
a place to start process improvement.

Earl Moon

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Date:         Fri, 21 Dec 2001 09:43:55 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Ferry <[log in to unmask]>
Subject:      Off Topic - Holiday Best Wishes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Posted this little poem a few years back. Thought I'd dust it off, add a
bit, and send it along. It's a toast to Jack Crawford, IPC Director,
Assembly Standards and Technology. Jack is a Santa-like character if there
ever was one. If you don't know Jack he's a big backer of this free forum
hosted by our friends at IPC.

I'll be at APEX next month in San Diego. If you can make I hope we cross
paths.

Best wishes and hope you all have a great 2002.

Your friend,

Jeff Ferry
Circuit Technology Center
[log in to unmask]

====================================================

'Twas the night before Christmas and out in the shop,
the lines were shut down, I had just stowed the mop.
The tweezers and cutters were stored with great care,
in hopes that St. Crawford soon would be there.

The boards were all shielded in boxes and bags,
numbers were marked on their little white tags.
My ESD coat and wrist strap put away,
I was ready to leave on this cold winter day.

When back in the shop I heard such a clatter,
I sprang to my feet to see what was the matter.
Out onto the floor I flew with a flair,
tore open the ovens and shut off the air.

The benches, and boxes, and carts on the floor,
got me to thinking how to give our next tour.
Peering over a bench and a stack of old specs,
I saw a big fellow with 8 super Techs.

Arms full of old documents, lap top on his back,
I knew in a moment it must be St. Jack.
As sharp as can be these TechNetters came,
and he whistled, and shouted, and called them by name;

"Now, INGEMAR! now, RAMSEY! now, KUHLOW and HILLMAN!
On, MOON MAN! on, SELDAK! on, GREGORY and CHRISTIAN!
To the top of the rack! to the top of the wall!
Now dash away! dash away! dash away all!"

He was dressed in a lab coat, from neck to his waste.
It was covered with super glue and old solder paste.
Had a pocket protector full of sharp things with points,
he was mumbling and mumbling about solder joints.

His eyes -- how they twinkled! his dimples how merry!
His cheeks were like roses, his nose like a cherry!
His smile was sure wide, it was broad as a bow,
and the hair on his head, turning white just like snow.

The stump of a pencil was perched on his ear,
a tool of some kind to help him to hear.
He had a great face and a little round belly,
that shook, when he laughed like a bowl full of jelly.

He was chubby and plump, a right jolly old elf,
and I laughed when I saw him, in spite of myself.
A wink of his eye and a twist of his head,
soon gave me to know I had nothing to dread.

He spoke not a word, but went straight to his work,
he tested the benches; then turned with a jerk,
and laying his finger aside of his nose,
and giving a nod, through the air duct he rose.

He sprang to his sleigh, a quick pick and place,
and away they all flew like a Derby horse race.
But I heard him exclaim, as he drove out of sight,
"HAPPY CHRISTMAS TO ALL, AND TO ALL A GOODNIGHT!"

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Date:         Fri, 21 Dec 2001 09:34:11 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Panel Layout Standardization
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello Technetters and Designers,

First of all MERRY CHRISTMAS!

I am working on Panel Layout Standardization project.
We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
However, to better pursue the upper manager to see the
potential benefit from doing this, I have to make a
presentation in which all the ideas, objects, goals,
have to be presented clearly.

I have seen many, however, there are always more
upside and downside of the Panel Layout Standadization
that I have not seen.  I NEED YOUR HELP HERE.

1. Universally, I know the boardhouse use 18x24
rawstock size.  However, besides it, what else do they
use (Taiwan, Korean, Chinese, Ireland, and USA).
2. However the X-Out affects the cost of making PCB?
(We want panel size are around of 12' - L x 7' - W in
which the maximum of PCB can possibly fit).
3. Screen Printing quality of those big panel vs.
smaller panel.
4. More!

Please advise me.
Thanks!
Again Merry Christmas!!!

Stacy


__________________________________________________
Do You Yahoo!?
Check out Yahoo! Shopping and Yahoo! Auctions for all of
your unique holiday gifts! Buy at http://shopping.yahoo.com
or bid at http://auctions.yahoo.com

---------------------------------------------------------------------------------
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Date:         Fri, 21 Dec 2001 10:04:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brooks,Bill" <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

How about the panel size working with pick and place machines, wave solder,
auto-insertion, Auto test fixtures, solder paste application, storage racks,
anti-static board carriers and racks, inspection equipment, etc. .... all
these things have limitations on the max size they can handle...

Also, larger panels may need local fiducials for compensation due to
variations in tolerance accumulation across larger areas... Will the panels
be rigid enough or require support through the manufacturing process?

How do you plan do DE-Panelize the boards? How many "X-out" or reject boards
will you allow in a panel?

Doe it make sense to have "SUB" panels? Super-panels that can break down to
sub-panels for certain processes?

enough?

Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm


-----Original Message-----
From: My Nguyen [mailto:[log in to unmask]]
Sent: Friday, December 21, 2001 9:34 AM
To: [log in to unmask]
Subject: [TN] Panel Layout Standardization


Hello Technetters and Designers,

First of all MERRY CHRISTMAS!

I am working on Panel Layout Standardization project.
We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
However, to better pursue the upper manager to see the
potential benefit from doing this, I have to make a
presentation in which all the ideas, objects, goals,
have to be presented clearly.

I have seen many, however, there are always more
upside and downside of the Panel Layout Standadization
that I have not seen.  I NEED YOUR HELP HERE.

1. Universally, I know the boardhouse use 18x24
rawstock size.  However, besides it, what else do they
use (Taiwan, Korean, Chinese, Ireland, and USA).
2. However the X-Out affects the cost of making PCB?
(We want panel size are around of 12' - L x 7' - W in
which the maximum of PCB can possibly fit).
3. Screen Printing quality of those big panel vs.
smaller panel.
4. More!

Please advise me.
Thanks!
Again Merry Christmas!!!

Stacy


__________________________________________________
Do You Yahoo!?
Check out Yahoo! Shopping and Yahoo! Auctions for all of
your unique holiday gifts! Buy at http://shopping.yahoo.com
or bid at http://auctions.yahoo.com

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=========================================================================
Date:         Fri, 21 Dec 2001 13:48:42 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: Environmental issues
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Brian,
Go for it.
Bev

-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: December 20, 2001 8:32 AM
To: [log in to unmask]
Subject: [TN] Environmental issues


There have recently been some threads here on environmental issues, with
the usual messages from some that they were not in context with the
purpose of the list.

If I receive sufficient support (say, 20 or more messages), offline, to
my private e-mail address ( [log in to unmask] ), I'll open a Yahoo
newsgroup devoted entirely to environmental issues within industry. This
will be cost-free, open to all, without reasonable restriction of
subject, which will allow those who are interested to continue these
discussions to their heart's content and without upsetting the
sensitivities of those who consider such threads as inappropriate here.

Please note that this is not in competition with the IPC but as a
complement.

Best regards,

Brian

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Date:         Fri, 21 Dec 2001 14:07:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Stacy,

First of all MERRY CHRISTMAS!

I am working on Panel Layout Standardization project.
We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
However, to better pursue the upper manager to see the
potential benefit from doing this, I have to make a
presentation in which all the ideas, objects, goals,
have to be presented clearly.

I have seen many, however, there are always more
upside and downside of the Panel Layout Standadization
that I have not seen.  I NEED YOUR HELP HERE.

1. Universally, I know the boardhouse use 18x24
rawstock size.  However, besides it, what else do they
use (Taiwan, Korean, Chinese, Ireland, and USA).

I wouldn't say there is a universal size for FR-4 - it depends on the board
size you are making.
My laminate guys start with a sheet 38" x 50" and cut that down depending on
what we order.
My last gig had 10 panel sizes on the books but only 5 were being used with
any frequency.
Don't misunderstand me, 18 x 24 is very popular - cost effective, easier
handling (less scrap from handling damage), & good for panelization.

2. However the X-Out affects the cost of making PCB?
(We want panel size are around of 12' - L x 7' - W in
which the maximum of PCB can possibly fit).

One impact to the fab house expense is whether the customer accept X-outs on
a PCB array.  Some customers required us to scrap an entire panel if one
board was bad.  <We're talking "Put your hand in the box" kinda pain.>

3. Screen Printing quality of those big panel vs.
smaller panel.

Now you are talking about registration issues.  I can't speak to the silk
screen side of it - Steve ya still out there!  I hear folks can run into
trouble with panel sag - 20 x 28 panel 62 mils thick.  For inner layer
registration the shop has to have it's artwork compensation factors dialed
in.

4. More!

Work with your board shop on the panelization including coupon locations -
there may be some best practices they use.

And for the holidays all I want are a few of gigs of RDRAM . . .

Hans
Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468




Please advise me.
Thanks!
Again Merry Christmas!!!

Stacy

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=========================================================================
Date:         Fri, 21 Dec 2001 11:22:45 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
In-Reply-To:  <72F8793F1F00D411BE2D00805FA7C0EBCD7BC0@DATRON1>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Bill,

Thanks a lot for your input.  The panel size for
RIMM,DIMM, DDR,SODIMM, will be layout in such way that
those factors are put in serious consideration.

We use Dek (Screen Printing, CP6/7, QP2/3, Heller,
Amistar (labeler) Sayaka, Excelon, and Nortek for our
production line.  Within 11.5 x 7 inches, and less
than 11 units in X direction, 3 in Y direction, we
believe that the machines will handle those panels
just fine.

For Fiducials: Thanks again! For fine pitch component
placement (on QP) we use local, however, for 0603 and
above (Chip/cap), we use global fiducial (I just added
it into my  note).

Will the panels be rigid enough or require support
through the manufacturing process?

It seems to be ok with DIMM/DDR/RIMM (1 row) and
SODIMM (2 row).  Here IS THE QUESTION for YOU: For
Critical areas, we give the boardhouse a tolerance of
4 mils for those applications (from Edge to Edge).
What we do is to complete the entire the
de-panelization in house, thus, the panel will contain
NO V-Groove scoring or rat-bites.  However, if the
panel comes in in 4 mils off, then we have to round it
perfectly. For memory product, where is the critical
area? (SODIMM,DIMM,SIMM,DDR,RIMM) Are they the only
portion below the knots or the entire area where the
knots locate at?

Also, do you know the common vendors rawstock material
size for both domestic and oversea?

Thanks,
Stacy

__________________________________________________
Do You Yahoo!?
Check out Yahoo! Shopping and Yahoo! Auctions for all of
your unique holiday gifts! Buy at http://shopping.yahoo.com
or bid at http://auctions.yahoo.com

---------------------------------------------------------------------------------
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Date:         Fri, 21 Dec 2001 08:34:05 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: white powder on leads
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"

Hi Andre! I would suggest you get a Scanning Electron Microscopy element
scan conducted on the white residue. The white residue you describe could
be tin or lead oxides, lead crystals due to a component plating problem,
calcium crystals due to poor washing, etc. The SEM analysis will help
eliminate the inorganic (e.g. metallic) possibilities leaving the possible
flux related  (organic) source causes. Good luck and Happy Holidays.

Dave Hillman
Rockwell Collins
[log in to unmask]





Andre Leclair <[log in to unmask]>@ipc.org> on 12/19/2001 07:57:26 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

Sent by:  TechNet <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  [TN] white powder on leads


Hi All

Here is another residue issue

We have an assembly which has a white residue remaining after wash.
The board is completely SMT (WS609) using a DI-Wash process,  the board is
spotless except for one location.  The location is a QFP (from CRONTEL),
the white powder is on the leads of the IC only.  There is not a spot on
the PCB.

The Powder dry brushes extremly easily. On a few of the leads ( usually
about half way up the lead, nver near the joint)after brushing there is
evidence of flux residue( yellow sort of like Crystal Flux residue) in
spots.
We have put a few boards through the Omega with readings lower then
2.3microgram/sq.inch.

Could this be something the part manufacture has left/put on the leads? I
have noticed that the plating is thin on the leads (exposed copper on the
faces) the leads also look like sheared stock ( exposed copper on the
sides)

Thanks
Andre

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=========================================================================
Date:         Fri, 21 Dec 2001 14:16:52 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Merry Christmas to all
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

From the Great State of Texas, city of Stafford (Houston) I wish you all a Very
Merry Christmas and a safe New Year.

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Date:         Fri, 21 Dec 2001 15:29:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hiteshew, Michael" <[log in to unmask]>
Subject:      Soldermask: LPI vs Dry Film
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT

Techies,
        I have a circuit board with 0.024" diameter (finished size) vias.
I'd like to tent them in the final design. My question: Am I better off
specifying dry-film soldermask as opposed to LPI? Is there a cost tradeoff
with dry film? Is it hard to work with or hard to get? It seems to have
fallen out of favor lately, so that's why I'm asking. Thanks in advance.

~Mike

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Date:         Fri, 21 Dec 2001 13:03:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brooks,Bill" <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Please tell me I MIS-READ your comment...12' X 7' (12 FEET by 7 FEET)? I
can't imagine that... You must have meant 12" X 7" (12 inches by 7 inches)
no?
- Bill Brooks


-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Friday, December 21, 2001 11:07 AM
To: [log in to unmask]
Subject: Re: [TN] Panel Layout Standardization


Hi Stacy,

First of all MERRY CHRISTMAS!

I am working on Panel Layout Standardization project.
We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
However, to better pursue the upper manager to see the
potential benefit from doing this, I have to make a
presentation in which all the ideas, objects, goals,
have to be presented clearly.

I have seen many, however, there are always more
upside and downside of the Panel Layout Standadization
that I have not seen.  I NEED YOUR HELP HERE.

1. Universally, I know the boardhouse use 18x24
rawstock size.  However, besides it, what else do they
use (Taiwan, Korean, Chinese, Ireland, and USA).

I wouldn't say there is a universal size for FR-4 - it depends on the board
size you are making.
My laminate guys start with a sheet 38" x 50" and cut that down depending on
what we order.
My last gig had 10 panel sizes on the books but only 5 were being used with
any frequency.
Don't misunderstand me, 18 x 24 is very popular - cost effective, easier
handling (less scrap from handling damage), & good for panelization.

2. However the X-Out affects the cost of making PCB?
(We want panel size are around of 12' - L x 7' - W in
which the maximum of PCB can possibly fit).

One impact to the fab house expense is whether the customer accept X-outs on
a PCB array.  Some customers required us to scrap an entire panel if one
board was bad.  <We're talking "Put your hand in the box" kinda pain.>

3. Screen Printing quality of those big panel vs.
smaller panel.

Now you are talking about registration issues.  I can't speak to the silk
screen side of it - Steve ya still out there!  I hear folks can run into
trouble with panel sag - 20 x 28 panel 62 mils thick.  For inner layer
registration the shop has to have it's artwork compensation factors dialed
in.

4. More!

Work with your board shop on the panelization including coupon locations -
there may be some best practices they use.

And for the holidays all I want are a few of gigs of RDRAM . . .

Hans
Integrity First  -  Service Before Self  -  Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622

mailto:[log in to unmask]

Com: (478) 926 - 5224
Fax:   (478) 926 - 4911
DSN Prefix: 468




Please advise me.
Thanks!
Again Merry Christmas!!!

Stacy

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Date:         Fri, 21 Dec 2001 16:42:58 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject:      Re: Soldermask: LPI vs Dry Film

Mike, just a few minutes ago as I was looking over my new copy of IPC-7095,
"Design and Assembly Process Implementation for BGAs", I noticed on page 30
there is a statement "Most photoimageable wet film masks will not even tent
0.35 mm via holes because it is difficult to cure polymer in via holes".
 We have been having trouble at ICT from untented, unplugged vias.  The
board designer is helping us out now.  We have one board with 0.028" vias
that is worst.  By the way, I did a quick calculation that suggested if the
vias were 0.020", the pull-down force at ICT would be increased by a factor
of 6 over the 0.028" version.

Here's a question for TechNetters in general, in the same vein, that may
help Mike and me.  Page 31 of 7095 refers to Tenting and Capping.  What is
capping?  7095 says "Via capping is the preferred method since tenting
reliability is dependent on the finished hole size".  Never heard of it
before, and although I'm not an old timer by TechNet standards, I've been
around a few days.  Thanks for assitance.   Lou Hart

-----Original Message-----
From:   Hiteshew, Michael [SMTP:[log in to unmask]]
Sent:   Friday, December 21, 2001 3:29 PM
To:     [log in to unmask]
Subject:        [TN] Soldermask: LPI vs Dry Film

Techies,
        I have a circuit board with 0.024" diameter (finished size) vias.
I'd like to tent them in the final design. My question: Am I better off
specifying dry-film soldermask as opposed to LPI? Is there a cost tradeoff
with dry film? Is it hard to work with or hard to get? It seems to have
fallen out of favor lately, so that's why I'm asking. Thanks in advance.

~Mike

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Date:         Fri, 21 Dec 2001 13:56:20 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
In-Reply-To:  <72F8793F1F00D411BE2D00805FA7C0EBCD7BC5@DATRON1>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

LOL! Bill, you are right

12" x 7" (I forgot to press press down the shift key).

By the way, Paul excellently explain the PCB vs Panel
(rawstock) size so far.

I am looking at Jedec spec. for the critical areas.
If you could, please shoot us an advise.

Thanks,

Stacy.


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Date:         Fri, 21 Dec 2001 16:58:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Soldermask: LPI vs Dry Film
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_126.94d06a1.29550a75_boundary"

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Hi Lou!

Capping I believe, is going back as a secondary step, and using the via image
only, then "capping" the vias with something like a SR1000 mask. Works fine
for sealing off the vias, but sometimes causes problems with stenciling
solderpaste if done on the topside of the PCB. If you do "capping" do it on
the bottomside...

-Steve Gregory-


> Mike, just a few minutes ago as I was looking over my new copy of IPC-7095,
> "Design and Assembly Process Implementation for BGAs", I noticed on page 30
> there is a statement "Most photoimageable wet film masks will not even tent
> 0.35 mm via holes because it is difficult to cure polymer in via holes".
> We have been having trouble at ICT from untented, unplugged vias.  The
> board designer is helping us out now.  We have one board with 0.028" vias
> that is worst.  By the way, I did a quick calculation that suggested if the
> vias were 0.020", the pull-down force at ICT would be increased by a factor
> of 6 over the 0.028" version.
>
> Here's a question for TechNetters in general, in the same vein, that may
> help Mike and me.  Page 31 of 7095 refers to Tenting and Capping.  What is
> capping?  7095 says "Via capping is the preferred method since tenting
> reliability is dependent on the finished hole size".  Never heard of it
> before, and although I'm not an old timer by TechNet standards, I've been
> around a few days.  Thanks for assitance.   Lou Hart
>


--part1_126.94d06a1.29550a75_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Lou!<BR>
<BR>
Capping I believe, is going back as a secondary step, and using the via image only, then "capping" the vias with something like a SR1000 mask. Works fine for sealing off the vias, but sometimes causes problems with stenciling solderpaste if done on the topside of the PCB. If you do "capping" do it on the bottomside...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Mike, just a few minutes ago as I was looking over my new copy of IPC-7095,<BR>
"Design and Assembly Process Implementation for BGAs", I noticed on page 30<BR>
there is a statement "Most photoimageable wet film masks will not even tent<BR>
0.35 mm via holes because it is difficult to cure polymer in via holes".<BR>
We have been having trouble at ICT from untented, unplugged vias.&nbsp; The<BR>
board designer is helping us out now.&nbsp; We have one board with 0.028" vias<BR>
that is worst.&nbsp; By the way, I did a quick calculation that suggested if the<BR>
vias were 0.020", the pull-down force at ICT would be increased by a factor<BR>
of 6 over the 0.028" version.<BR>
<BR>
Here's a question for TechNetters in general, in the same vein, that may<BR>
help Mike and me.&nbsp; Page 31 of 7095 refers to Tenting and Capping.&nbsp; What is<BR>
capping?&nbsp; 7095 says "Via capping is the preferred method since tenting<BR>
reliability is dependent on the finished hole size".&nbsp; Never heard of it<BR>
before, and although I'm not an old timer by TechNet standards, I've been<BR>
around a few days.&nbsp; Thanks for assitance.&nbsp;&nbsp; Lou Hart<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_126.94d06a1.29550a75_boundary--

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Date:         Fri, 21 Dec 2001 17:20:10 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
MIME-Version: 1.0
Content-Type: multipart/alternative;
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--part1_142.6c1c829.29550f9a_boundary
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Hi Stacy!

Having read the replies that you've recieved so far, they are giving you good
information. The only thing I can add is some past experience from my
employment at a memory company...Smart Modular Technologies, they are no
longer, was bought out by Solectron...but I digress...

As far as X-outs, they aren't free. The FAB house won't charge you for them,
and your bare costs may be lower, but there are costs that you will see on
your production floor from X-outs.

Normally what I see from the fab houses is a big "X" drawn on the individual
boards. That X is something that we can't program our machines to see since
it's not consistently in the same place. We normally had to sort the panels
one-by-one and put a label that the machine can see on each of the x-outs, at
a consistent location, so the machine don't try and populate bad boards.

The other alternative is to sort the fabs according to which boards are bad,
and then have separate programs that populate only the good boards...either
way, you still have to handle each board.

The other thing to think about is the wasted solder paste that you print on
these bad fabs. It may seem insignificant, but when I worked at Smart
Modular, we would sometime do almost a million modules a month during our
busy times. I did a calulation of the solder paste that was wasted on bad
boards over a years time, and it was close to $50,000 a year!

It's not only that, you need to figure in the time that's wasted in
depaneling. You say you have a router inline that depanelizes everything,
does it do only the good boards, or does it do the whole panel? Is it wasting
time routing out bad boards?

X-out aren't a big deal in low volumes, but if you do high volumes, the costs
that you may save in the bare board costs may be insignificant compared to
what you spend on the production floor...


-Steve Gregory-


> Hello Technetters and Designers,
>
> First of all MERRY CHRISTMAS!
>
> I am working on Panel Layout Standardization project.
> We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
> However, to better pursue the upper manager to see the
> potential benefit from doing this, I have to make a
> presentation in which all the ideas, objects, goals,
> have to be presented clearly.
>
> I have seen many, however, there are always more
> upside and downside of the Panel Layout Standadization
> that I have not seen.  I NEED YOUR HELP HERE.
>
> 1. Universally, I know the boardhouse use 18x24
> rawstock size.  However, besides it, what else do they
> use (Taiwan, Korean, Chinese, Ireland, and USA).
> 2. However the X-Out affects the cost of making PCB?
> (We want panel size are around of 12' - L x 7' - W in
> which the maximum of PCB can possibly fit).
> 3. Screen Printing quality of those big panel vs.
> smaller panel.
> 4. More!
>
> Please advise me.
> Thanks!
> Again Merry Christmas!!!
>
> Stacy
>


--part1_142.6c1c829.29550f9a_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Stacy!<BR>
<BR>
Having read the replies that you've recieved so far, they are giving you good information. The only thing I can add is some past experience from my employment at a memory company...Smart Modular Technologies, they are no longer, was bought out by Solectron...but I digress...<BR>
<BR>
As far as X-outs, they aren't free. The FAB house won't charge you for them, and your bare costs may be lower, but there are costs that you will see on your production floor from X-outs.<BR>
<BR>
Normally what I see from the fab houses is a big "X" drawn on the individual boards. That X is something that we can't program our machines to see since it's not consistently in the same place. We normally had to sort the panels one-by-one and put a label that the machine can see on each of the x-outs, at a consistent location, so the machine don't try and populate bad boards.<BR>
<BR>
The other alternative is to sort the fabs according to which boards are bad, and then have separate programs that populate only the good boards...either way, you still have to handle each board.<BR>
<BR>
The other thing to think about is the wasted solder paste that you print on these bad fabs. It may seem insignificant, but when I worked at Smart Modular, we would sometime do almost a million modules a month during our busy times. I did a calulation of the solder paste that was wasted on bad boards over a years time, and it was close to $50,000 a year!<BR>
<BR>
It's not only that, you need to figure in the time that's wasted in depaneling. You say you have a router inline that depanelizes everything, does it do only the good boards, or does it do the whole panel? Is it wasting time routing out bad boards?<BR>
<BR>
X-out aren't a big deal in low volumes, but if you do high volumes, the costs that you may save in the bare board costs may be insignificant compared to what you spend on the production floor...<BR>
<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello Technetters and Designers,<BR>
<BR>
First of all MERRY CHRISTMAS!<BR>
<BR>
I am working on Panel Layout Standardization project.<BR>
We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)<BR>
However, to better pursue the upper manager to see the<BR>
potential benefit from doing this, I have to make a<BR>
presentation in which all the ideas, objects, goals,<BR>
have to be presented clearly.<BR>
<BR>
I have seen many, however, there are always more<BR>
upside and downside of the Panel Layout Standadization<BR>
that I have not seen.&nbsp; I NEED YOUR HELP HERE.<BR>
<BR>
1. Universally, I know the boardhouse use 18x24<BR>
rawstock size.&nbsp; However, besides it, what else do they<BR>
use (Taiwan, Korean, Chinese, Ireland, and USA).<BR>
2. However the X-Out affects the cost of making PCB?<BR>
(We want panel size are around of 12' - L x 7' - W in<BR>
which the maximum of PCB can possibly fit).<BR>
3. Screen Printing quality of those big panel vs.<BR>
smaller panel.<BR>
4. More!<BR>
<BR>
Please advise me.<BR>
Thanks!<BR>
Again Merry Christmas!!!<BR>
<BR>
Stacy<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_142.6c1c829.29550f9a_boundary--

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Date:         Fri, 21 Dec 2001 17:38:56 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      OT-Christmas Wishes...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi everybody!

First off, I truely wish everybody a warm and merry Christmas, and a most
prosperous and fullfilling New Year.

I pray that this next year won't be as eventfull as the past one has. I also
pray for and thank those that are serving our country now...they deserve all
of our prayers and thanks...

Mike Fenner sent me a email that I want to share. This is a most wonderful
image, I'm using it as my background on my computer....thank you Mike!

-Steve Gregory-

>>I offer this, if there is a God in heaven this is what He sees.

http://antwrp.gsfc.nasa.gov/apod/image/0011/earthlights_dmsp_big.jpg

A perspective for all the troubles and squabbles and a peaceful scene to end
the Year and wish you all the Seasons Greetings and a Happy New Year

Mike<<

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Date:         Fri, 21 Dec 2001 14:47:36 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Re: Panel Layout Standardization - PCB height increment
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello Technetters,

Thank you so much! You guys are awesome!

Yes Steve, thanks for your input, you don't mind if I
quote it in my report "50,000/year just for waste
solder paste on X-out modules for 1 mil module/month"
(our volume is about not less).

The problem of X-Out, from my concern, is how to
provide good support in Solder Paste Printing process
as we do second side product.  Width different
component height (D-Pac Stack, TSOP, SOJ, high/low
profile capacitors, different PCB thickness), it is
not easy to find flexible/cost effitive tool for the
support toolings.  Even with one product but the X-Out
position shift from block to block.

THE SECOND QUESTION IS PCB HEIGHT.  WE WANT THE LAYOUT
ENGINEER TO FOLLOW THE 0.125 INCREMENT. (I.e for DIMM,
the dimension will be 5.25x1.00/1.125/1.250/1.375...)
By doing we can standardize the panel size, the tools,
fixture, etc. However, I do not know is there any JDEC
spec or any other spec on PCB height or its increment.

Please advise,
Stacy

__________________________________________________
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Send your FREE holiday greetings online!
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Date:         Fri, 21 Dec 2001 21:37:10 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Seth Goodman <[log in to unmask]>
Subject:      Re: Panel Layout Standardization
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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This is a multi-part message in MIME format.

------=_NextPart_000_0000_01C18A67.A57271D0
Content-Type: text/plain;
        charset="us-ascii"
Content-Transfer-Encoding: 7bit

Hi Steve,

I didn't know that Smart Modular Technologies was no more.  I just spec'd in
some of their DIMM's about 6 months ago.  With regard to the X-outs being
randomly placed and not machine readable, I did some work a while back for a
contract manufacturer who had just put in place a system to "fix" this
problem.  Their solution, which seemed pretty clever to me, was to place a
diamond-shaped fiducial on each board in the panel, and then, you guessed
it, have the PCB fabricator black out just the little diamond.  So rather
than a big randomly placed "X", which is great for us near-sighted humans,
you got a small paint or ink blob on the fiducial.  I don't know where on
the process line they read the diamond-shaped fiducial to tell all the
subsequent machines about the bad board locations.  But it did seem like a
really good idea (like most ideas that I don't have to implement).  Your
point about solder paste is well taken.  That one seems pretty hard to avoid
without spending more than you could save.

Regards,

Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966

  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
  Sent: Friday, December 21, 2001 4:20 PM
  To: [log in to unmask]
  Subject: Re: [TN] Panel Layout Standardization


  Hi Stacy!

  Having read the replies that you've recieved so far, they are giving you
good information. The only thing I can add is some past experience from my
employment at a memory company...Smart Modular Technologies, they are no
longer, was bought out by Solectron...but I digress...

  As far as X-outs, they aren't free. The FAB house won't charge you for
them, and your bare costs may be lower, but there are costs that you will
see on your production floor from X-outs.

  Normally what I see from the fab houses is a big "X" drawn on the
individual boards. That X is something that we can't program our machines to
see since it's not consistently in the same place. We normally had to sort
the panels one-by-one and put a label that the machine can see on each of
the x-outs, at a consistent location, so the machine don't try and populate
bad boards.

  The other alternative is to sort the fabs according to which boards are
bad, and then have separate programs that populate only the good
boards...either way, you still have to handle each board.

  The other thing to think about is the wasted solder paste that you print
on these bad fabs. It may seem insignificant, but when I worked at Smart
Modular, we would sometime do almost a million modules a month during our
busy times. I did a calulation of the solder paste that was wasted on bad
boards over a years time, and it was close to $50,000 a year!

  It's not only that, you need to figure in the time that's wasted in
depaneling. You say you have a router inline that depanelizes everything,
does it do only the good boards, or does it do the whole panel? Is it
wasting time routing out bad boards?

  X-out aren't a big deal in low volumes, but if you do high volumes, the
costs that you may save in the bare board costs may be insignificant
compared to what you spend on the production floor...


  -Steve Gregory-


------=_NextPart_000_0000_01C18A67.A57271D0
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        charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

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<BODY>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D930482203-22122001>Hi=20
Steve,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D930482203-22122001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D930482203-22122001>I =
didn't know that=20
Smart Modular Technologies was no more.&nbsp; I just spec'd in some of =
their=20
DIMM's about 6 months ago.&nbsp; With regard to the X-outs being =
randomly placed=20
and not machine readable, I did some work a while back for a contract=20
manufacturer who had just put in place a system to "fix" this =
problem.&nbsp;=20
Their solution, which seemed pretty clever to me, was to place a =
diamond-shaped=20
fiducial on each board in the panel, and then, you guessed it, have the =
PCB=20
fabricator black out just the little diamond.&nbsp; So rather than a big =

randomly placed "X", which is great for us near-sighted humans, you got =
a small=20
paint or ink blob on the fiducial.&nbsp; I don't know where on the =
process line=20
they read the diamond-shaped fiducial to tell all the subsequent =
machines about=20
the bad board locations.&nbsp; But it did seem like a really good idea =
(like=20
most ideas that I don't have to implement).&nbsp; Your point about =
solder paste=20
is well taken.&nbsp; That one seems pretty hard to avoid without =
spending more=20
than you could save.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2><FONT face=3DArial>Regards,<BR><BR>Seth =
Goodman<BR>Goodman=20
Associates, LLC<BR>tel 608.833.9933<BR>fax =
608.833.9966<BR></FONT></DIV></FONT>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid">
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. =
Gregory<BR><B>Sent:</B>=20
  Friday, December 21, 2001 4:20 PM<BR><B>To:</B>=20
  [log in to unmask]<BR><B>Subject:</B> Re: [TN] Panel Layout=20
  Standardization<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi=20
  Stacy!<BR><BR>Having read the replies that you've recieved so far, =
they are=20
  giving you good information. The only thing I can add is some past =
experience=20
  from my employment at a memory company...Smart Modular Technologies, =
they are=20
  no longer, was bought out by Solectron...but I digress...<BR><BR>As =
far as=20
  X-outs, they aren't free. The FAB house won't charge you for them, and =
your=20
  bare costs may be lower, but there are costs that you will see on your =

  production floor from X-outs.<BR><BR>Normally what I see from the fab =
houses=20
  is a big "X" drawn on the individual boards. That X is something that =
we can't=20
  program our machines to see since it's not consistently in the same =
place. We=20
  normally had to sort the panels one-by-one and put a label that the =
machine=20
  can see on each of the x-outs, at a consistent location, so the =
machine don't=20
  try and populate bad boards.<BR><BR>The other alternative is to sort =
the fabs=20
  according to which boards are bad, and then have separate programs =
that=20
  populate only the good boards...either way, you still have to handle =
each=20
  board.<BR><BR>The other thing to think about is the wasted solder =
paste that=20
  you print on these bad fabs. It may seem insignificant, but when I =
worked at=20
  Smart Modular, we would sometime do almost a million modules a month =
during=20
  our busy times. I did a calulation of the solder paste that was wasted =
on bad=20
  boards over a years time, and it was close to $50,000 a =
year!<BR><BR>It's not=20
  only that, you need to figure in the time that's wasted in depaneling. =
You say=20
  you have a router inline that depanelizes everything, does it do only =
the good=20
  boards, or does it do the whole panel? Is it wasting time routing out =
bad=20
  boards?<BR><BR>X-out aren't a big deal in low volumes, but if you do =
high=20
  volumes, the costs that you may save in the bare board costs may be=20
  insignificant compared to what you spend on the production=20
  floor...<BR><BR><BR>-Steve =
Gregory-<BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>

------=_NextPart_000_0000_01C18A67.A57271D0--

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Date:         Sat, 22 Dec 2001 16:00:50 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Mass lead trimming systems...
MIME-Version: 1.0
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              boundary="part1_4f.15e3d76f.29564e82_boundary"

--part1_4f.15e3d76f.29564e82_boundary
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Swipe one of Doug's Mountain Dews? Sounds like you and Doug both need to
visit this site:

http://members.aol.com/seanborg/mtdew/mtdew1.htm

hehehe...

-Steve Gregory-


> Enough said, I am off to swipe one of Doug's Mountain Dew's. Happy Holidays
> to everyone.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>


--part1_4f.15e3d76f.29564e82_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Swipe one of Doug's Mountain Dews? Sounds like you and Doug both need to visit this site:<BR>
<BR>
http://members.aol.com/seanborg/mtdew/mtdew1.htm<BR>
<BR>
hehehe...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Enough said, I am off to swipe one of Doug's Mountain Dew's. Happy Holidays<BR>
to everyone.<BR>
<BR>
Dave Hillman<BR>
Rockwell Collins<BR>
[log in to unmask]<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_4f.15e3d76f.29564e82_boundary--

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Date:         Sun, 23 Dec 2001 03:19:56 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Flett <[log in to unmask]>
Subject:      Re: Warpage in FR-4

Bill,

plenty of people have answered your question on warpage and I agree with
the responces. The cooling rate is critical when the board passes through
the glass transition phase. This cooling rate could be 30 degrees / minute
if you could ensure that every point on each board were cooling at that
exact rate, but that would be near impossible. The truth is, cooling slowly
at the 7 degrees/min, as previously mentioned, will give you a better
chance of minimising temperature variation across the board. I suggest you
thermocouple a dummy panel, in several positions, and assess the
temparature variation. Back to Tg, if part of the board is above Tg and
part below, you will get the bi-metal strip effect (warpage) which will be
set in the board.

Hope this helps

Best regards to all and merry christmas

Michael

On Wed, 19 Dec 2001 08:26:21 -0500, Kasprzak, Bill (sys) USX
<[log in to unmask]> wrote:

>Holiday Greetings to one and all,
>
>I have an 8 layer FR-4 board that was supposedly built IAW IPC-6011, Class
3
>and IPC-6012, Class 3. The board itself appears to be like any other board,
>.062" thick, no unusual ground plane layers etc. After wave soldering this
>assembly severely warped. Looking at the bare boards, they are also warped,
>but can be shaped into a straight position by bending a little. (I
shouldn't
>have to do this.)
>
>Not being up to date on board fabrication techniques, was there anything in
>the fab process that could lead to a warped board? We're talking a 3/16"
>warp over an 8" length.. Or was there something at my assembly end that is
>introducing the warp. The boards were run in a titanium picture frame
>pallet.
>
>Your thoughts and ideas are greatly appreciated.
>
>Bill Kasprzak
>Moog Inc., Electronic Assembly Engineering
>
>---------------------------------------------------------------------------
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Date:         Sun, 23 Dec 2001 11:48:30 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve DiBartolomeo <[log in to unmask]>
Subject:      Checking Laminate Order is Patented!
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Technetters...

I have been reading the suggestions about how one
verifies that laminate layers are stacked correctly.

Did you know that a company, Samsung, has actually
"patented" the idea of using offset metal pads near
the edges of the substrate to determine that the
layup is correct.

No way! Yes way! - patent number 6,091,026 (I saw the
patent reviewed in Chip Scale Design Magazine...November
December 2001, page 57)

So all of you using the technique - send your money
to Samsung! And I though that patents had to be non-obvious
to those skilled in the industry ...

========================================================

Steve DiBartolomeo              [log in to unmask]
PC Tools                     Microelectronics Tools

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Date:         Sun, 23 Dec 2001 16:05:44 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Checking Laminate Order is Patented!
MIME-Version: 1.0
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              boundary="part1_14b.63554f9.2957a128_boundary"

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HA! I imagine that this patent is as enforcable as the one that "patented"
using epoxy for bottomside SMT components...

Were these companies to try and enforce such patents, the losses that they
would see from such enforcement, should be of much concern to the upper
management.

If they even attempted such enforment, I for one, would do everything in my
power to not engage in any sort of business with that company...it would be
possible to do that...they have a great stake in other markets...there's many
other companies that produce memory as one example...I don't think they would
be so short sighted...

-Steve Gregory-

> Technetters...
>
> I have been reading the suggestions about how one
> verifies that laminate layers are stacked correctly.
>
> Did you know that a company, Samsung, has actually
> "patented" the idea of using offset metal pads near
> the edges of the substrate to determine that the
> layup is correct.
>
> No way! Yes way! - patent number 6,091,026 (I saw the
> patent reviewed in Chip Scale Design Magazine...November
> December 2001, page 57)
>
> So all of you using the technique - send your money
> to Samsung! And I though that patents had to be non-obvious
> to those skilled in the industry ...
>
> ========================================================
>
> Steve DiBartolomeo              [log in to unmask]
> PC Tools                     Microelectronics Tools
>


--part1_14b.63554f9.2957a128_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>HA! I imagine that this patent is as enforcable as the one that "patented" using epoxy for bottomside SMT components...<BR>
<BR>
Were these companies to try and enforce such patents, the losses that they would see from such enforcement, should be of much concern to the upper management.<BR>
<BR>
If they even attempted such enforment, I for one, would do everything in my power to not engage in any sort of business with that company...it would be possible to do that...they have a great stake in other markets...there's many other companies that produce memory as one example...I don't think they would be so short sighted...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Technetters...<BR>
<BR>
I have been reading the suggestions about how one<BR>
verifies that laminate layers are stacked correctly.<BR>
<BR>
Did you know that a company, Samsung, has actually<BR>
"patented" the idea of using offset metal pads near<BR>
the edges of the substrate to determine that the<BR>
layup is correct.<BR>
<BR>
No way! Yes way! - patent number 6,091,026 (I saw the<BR>
patent reviewed in Chip Scale Design Magazine...November<BR>
December 2001, page 57)<BR>
<BR>
So all of you using the technique - send your money<BR>
to Samsung! And I though that patents had to be non-obvious<BR>
to those skilled in the industry ...<BR>
<BR>
========================================================<BR>
<BR>
Steve DiBartolomeo&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [log in to unmask]<BR>
PC Tools&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Microelectronics Tools<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date:         Sun, 23 Dec 2001 15:32:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Warpage in FR-4
X-To:         Michael Flett <[log in to unmask]>

Again, the lamination process often is more overlooked than most others. A
basic part of any process management tool must be to audit the process. As
you say, running the lamination process calibration simply is to, on a
regular basis, place the thermocouple "book" into the press openings, using
say 5 places, to determine the profile. It's not much different than
profiling a wave or reflow soldering process. Much else to do but often
overlooked.

MoonMan

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Date:         Sun, 23 Dec 2001 15:33:52 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: Checking Laminate Order is Patented!
X-To:         [log in to unmask]

It's more ridiculous than a patent for capacitance core.

MoonMan

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Date:         Sun, 23 Dec 2001 16:47:06 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Patented
MIME-Version: 1.0
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A whole lot about patent law, and its enforcement, is pretty dumb.  And it is
not helped by some REALLY serious screwups by the patent office in the US, (I
am aware of some of them) and probably in other places.

However, for those of us who want to be "technically correct", and I know we
all do, especially Steve..., you have the right to use a patented idea if you
"invented" it before the patent was filed.  So, if you were using the layer
count idea before the Samsung patent was filed, you are legally in the
clear....now, you can all sleep better, I am sure...

Rudy Sedlak
RD Chemical Company

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Date:         Mon, 24 Dec 2001 08:09:52 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Peter George Duncan>" <[log in to unmask]>
Subject:      Re: Soldermask: LPI vs Dry Film
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

The only answer I can help with is my brief experience with Dry Film. It's
becoming rarer as LPI has become the apparent industry standard, but also
it isn't as suitable as LPI is you have a board with a lot of closely
packed traces - it tends not to adhere too well. LPI tents OK too, so my
vote for less hassle is LPI.

Merry Christmas to all fellow T-Nagers.

Peter Duncan




                    "Hiteshew,
                    Michael"                 To:     [log in to unmask]
                    <michael.hiteshew        cc:     (bcc: DUNCAN Peter/Asst Prin Engr/ST
                    @LMCO.COM>               Aero/ST Group)
                    Sent by: TechNet         Subject:     [TN] Soldermask: LPI vs Dry Film
                    <[log in to unmask]>


                    12/22/01 04:29 AM
                    Please respond to
                    "TechNet E-Mail
                    Forum."






Techies,
        I have a circuit board with 0.024" diameter (finished size) vias.
I'd like to tent them in the final design. My question: Am I better off
specifying dry-film soldermask as opposed to LPI? Is there a cost tradeoff
with dry film? Is it hard to work with or hard to get? It seems to have
fallen out of favor lately, so that's why I'm asking. Thanks in advance.

~Mike

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Date:         Mon, 24 Dec 2001 08:20:24 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      DINOSAUR

Just thought some of you might like a little unseasonable yuck. Our good
friend from the farthest reaches of your planet provided some Eastern
insight. I replied with none.

Hello Moonman,

The interesting thing is I'm the AME/PCBA process engineer in several
PDTs(Product Development Team) right now. That's my job responsibilities. We
produce telecomm equipment in China. We have our own DFM checklists in the
company. Different from your big list, we use different checklists for the
different review points in a design process. We discuss a lot over the
checklists and keep updating them. It's interesting to see somebody at the
other end of the world doing similar things. But the company just started
the DFM/CE in the recent two years, so we are just pupils(over 30 years in
the business! what do they call such a man? Grand old man? or dinosaurs? : ).

Wish you a Merry Christmas on earth.

Jiang Ping

Jiang,

You're right about revising the check lists as needed. Just don't do it for
its sake alone. Keeping current with technology is essential, but trying to
get ahead is what it's all about. I mean, you know that what with such
"traditional" values you folks all have. No dinosaurs there, right?

You used the magical acronyms DFM/CE. Outstanding! Where did you come up
with the CE part of the equation. Oh yes, tradition and culture. You folks
must be incapable of doing it without concurrence. On the one hand I applaud
you all. On the other, you must become less traditional/dinosauristic and
get more entrepreneurial - though you shouldn't take it too far. The West
and East have been trying, though not too well, to get together forever. Why
doesn't it work. Maybe money will solve the problems but, maybe, with fewer
kidney harvests in the field in your country and fewer .coms in ours.

Grand old man? Not exactly! Dino! No, and still revered as someone
progressive having sought and taught CPI seemingly forever and people still
don't listen well enough. Ain't got no labels on me but for self
proclaimed - as MoonMan looking down upon it all and seeing it repeated time
after time though still not getting it right without DFM/CE.

Wish you a Merry Christmas - wherever you are.

MoonMan

Jiang,

Hope you don't mind my posting this. Even so, If you're really doing it
right where you are, some shame on us over here.

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Date:         Tue, 25 Dec 2001 00:23:01 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marife R. Gonzales" <[log in to unmask]>
Subject:      Marife R Gonzales/CUB/SC/PHILIPS is out of the office.
MIME-Version: 1.0
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I will be out of the office starting  12-24-2001 and will not return until 01-03-2002.

I will respond to your message when I return.

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Date:         Mon, 24 Dec 2001 17:54:11 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      OT - Christmas and New Years wishes...
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Just a few thoughts to think about in the new year. A doctor/priest who has
been with many, many people who passed-on said that there were always two
questions that came to light before the end...

"Was I loved?"

"Did I love enough?"

Don't need to elaborate about this...just something to think about.

Warmest wishes to each and everyone of you...

-Steve Gregory-

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Date:         Mon, 24 Dec 2001 21:34:03 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Re: OT - Christmas and New Years wishes...
X-To:         "Stephen R. Gregory" <[log in to unmask]>

Steve and all, certainly words to be seriously considered in troubled times.

I wasn't going to say anything, but I've gotten so many good wishes off
line, as I know you all have, I thought my thoughts may be interesting.
Though not purely technical, if at all, I have been involved in so many
conversations with folks I've never met from all over the world starting
that way and ending up as follows while answering a simple seasonal greeting:

Thank you Linda. It isn't an easy time, to say the least, but I've been
conversing with some folks in other lands (via the internet mostly), as well
as here, about who hopes for what in the future. In the recent past, the
talk has been of technology. Most recently (time dependent on the season I
suspect), more of it focuses on our type beings (some flatter ourselves as
human) and interrelationships, and how they may positively change based on
what we must do to survive let alone prosper - or simply make a living.
Talking this way certainly puts things a bit more in perspective but
emphasizes how differently we, on this shrinking sphere called earth, view
each other and how we continue to change - often for the better or?
Certainly, our time has become more perplexing without a clear vision of
where we all are headed. We now may begin viewing divergence in a whole new
light.

Much of the discussions revolve around ethics and moral values in the work
place. Moreover, these talks involve our leadership therein, or lack of it,
and how it influences our daily lives while trying to make a living. Even
God, or another entity to some, is viewed differently from one end of the
spectrum and planet to another - from kind and caring to a terrifying deity
promising death to infidels. Even the most terrible of crimes are just to
some and denounced by others - all based on a human perspective often
without regard to consequences on earth but a fruitful promise hereafter.

Much verbiage involves those past and how some have made billions of dollars
on and off the working person's back even in companies where a few led and
others followed eagerly down a path to certain riches. Enron is a most
recent example of those at the top promising great gains for all involved
while only they benefited, but those following now decry their losses as
though totally innocent. Mankind loves a .com type world and everyone wants
a big piece of it but not when it fails. Point the finger and become as
litigious as possible without regard to consequences. Worse, point the gun
and shoot "innocents" with no earthly regard at all.

In other times recent, though forgotten by most, the "junk bond" types
("kings") now are teaching ethics in Stanford MBA programs, and so forth,
come to mind and are clear examples of greed taken to the limits and the
profits made thereof kept them relatively safe from any serious punishment.
Write a check and go free worked for them. Truly amazing how we forgive some
with so much, and punish so many without. Third strike for stealing a loaf
of bread - now there's a concept failed though Milken and Ivan walk as free
and still very rich men to be followed in some classroom full of hopeful
billionaires. Almost makes recent "warlike" events pail by comparison.
That's a lot of what talk is about between myself and others in other places
with different, though not more well founded, viewpoints concerning what is
just.

One thing, out of all this, is sure. We have a nearly clean slate on which
we may all begin to do better, or not. The choice is ours. Though the
economy will get worse before better, we as humans can only get better.

It's not easy to find perspective for our situation and, what should be a
joyous time of year, is not exactly that as older promises held. However, as
some find justice in our inhumanities to one another, more of us may find a
better time ahead. That is my wish and that is what I, in my very limited
way, am working and hoping for so tomorrow is a better time and place.
Certainly, I am now going to reach out, beyond my technological confines,
and try to help make positive changes elsewhere. Because tomorrow is now,
you and I have work to do and I know you will do yours as well as I can only
hope do mine.

Enjoy,

Earl Moon and the Boyds


If a new year has any significance at all, the "clean slate" thing appeals
most to me. As my technical life slows to a crawl, I want to do something
else maybe just a bunch better.

MoonMan

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Date:         Wed, 26 Dec 2001 09:48:11 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         Dave Roesler <[log in to unmask]>
Subject:      Panel Utilization Software
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Is anyone aware of panel utilization software besides KwickFit?

Thanks,
Dave Roesler
TRI-C Design, Inc.

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Date:         Wed, 26 Dec 2001 19:34:43 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: Panel Utilization Software
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Hi Dave,

Yes, there is Propanel, at http://www.proms.com/ and you can download it =
at http://www.proms.com/downloadpropanel.asp
Don't know if it's any good, but I suppose you could give it a try,

Daan Terstegge
http://www.smtinfo.net
  ----- Original Message -----=20
  From: Dave Roesler=20
  To: [log in to unmask]
  Sent: Wednesday, December 26, 2001 4:48 PM
  Subject: [TN] Panel Utilization Software


  Is anyone aware of panel utilization software besides KwickFit?

  Thanks,
  Dave Roesler
  TRI-C Design, Inc.

  =
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi Dave,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Yes, there is Propanel, at <A=20
href=3D"http://www.proms.com/">http://www.proms.com/</A>&nbsp;and you =
can download=20
it at <A=20
href=3D"http://www.proms.com/downloadpropanel.asp">http://www.proms.com/d=
ownloadpropanel.asp</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Don't know if it's any good, but I =
suppose you=20
could give it a try,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Daan Terstegge</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">Dave Roesler</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, December 26, =
2001 4:48=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Panel Utilization =

  Software</DIV>
  <DIV><BR></DIV>Is anyone aware of panel utilization software besides=20
  KwickFit?<BR><BR>Thanks,<BR>Dave Roesler<BR>TRI-C Design,=20
  =
Inc.<BR><BR>-------------------------------------------------------------=
--------------------<BR>Technet=20
  Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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  for additional<BR>information, or contact Keach Sasamori at <A=20
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Date:         Wed, 26 Dec 2001 11:12:10 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         My Nguyen <[log in to unmask]>
Subject:      Re: Panel Utilization Software
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Good morning Technetters,

I have downloaded the Kwickfit.  It seems to be a
great software with affodable price.  However, if I
have a 2x7 panel size, and I want a 0.4 inches for the
middle rail, the software would not have that
features.  Instead, it takes 0.1 spacing for all the
space between PCBs (in sub-panel) in both XY
direction.

You may suggest that I can increase the left/right
rail size to fix the problem.  However, if I increase
the left/right rail size, then the 1 up would be
wrong.

I dont' know if the full version fix that problem or
not.  Or if any other software may have that features?

Thanks,

Stacy

__________________________________________________
Do You Yahoo!?
Send your FREE holiday greetings online!
http://greetings.yahoo.com

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Date:         Wed, 26 Dec 2001 22:49:44 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
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From:         "D.Terstegge" <[log in to unmask]>
Subject:      Re: Panel Utilization Software
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Hi Stacy,

Why don't you ask the KwickFit people ?  But now you asked us, the =
answer is yes it's fixed when you register the software.

Daan
http://www.smtinfo.net

  ----- Original Message -----=20
  From: My Nguyen=20
  To: [log in to unmask]
  Sent: Wednesday, December 26, 2001 8:12 PM
  Subject: Re: [TN] Panel Utilization Software


  Good morning Technetters,

  I have downloaded the Kwickfit.  It seems to be a
  great software with affodable price.  However, if I
  have a 2x7 panel size, and I want a 0.4 inches for the
  middle rail, the software would not have that
  features.  Instead, it takes 0.1 spacing for all the
  space between PCBs (in sub-panel) in both XY
  direction.

  You may suggest that I can increase the left/right
  rail size to fix the problem.  However, if I increase
  the left/right rail size, then the 1 up would be
  wrong.

  I dont' know if the full version fix that problem or
  not.  Or if any other software may have that features?

  Thanks,

  Stacy

  __________________________________________________
  Do You Yahoo!?
  Send your FREE holiday greetings online!
  http://greetings.yahoo.com

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<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi Stacy,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Why don't you ask the KwickFit people=20
?&nbsp;&nbsp;But now you asked us, the answer is yes it's fixed when you =

register the software.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Daan</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A [log in to unmask] =
href=3D"mailto:[log in to unmask]">My=20
  Nguyen</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, December 26, =
2001 8:12=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Panel =
Utilization=20
  Software</DIV>
  <DIV><FONT face=3DArial size=3D2></FONT><FONT face=3DArial=20
  size=3D2></FONT><BR></DIV>Good morning Technetters,<BR><BR>I have =
downloaded the=20
  Kwickfit.&nbsp; It seems to be a<BR>great software with affodable =
price.&nbsp;=20
  However, if I<BR>have a 2x7 panel size, and I want a 0.4 inches for=20
  the<BR>middle rail, the software would not have =
that<BR>features.&nbsp;=20
  Instead, it takes 0.1 spacing for all the<BR>space between PCBs (in =
sub-panel)=20
  in both XY<BR>direction.<BR><BR>You may suggest that I can increase =
the=20
  left/right<BR>rail size to fix the problem.&nbsp; However, if I=20
  increase<BR>the left/right rail size, then the 1 up would=20
  be<BR>wrong.<BR><BR>I dont' know if the full version fix that problem=20
  or<BR>not.&nbsp; Or if any other software may have that=20
  =
features?<BR><BR>Thanks,<BR><BR>Stacy<BR><BR>____________________________=
______________________<BR>Do=20
  You Yahoo!?<BR>Send your FREE holiday greetings online!<BR><A=20
  =
href=3D"http://greetings.yahoo.com">http://greetings.yahoo.com</A><BR><BR=
>------------------------------------------------------------------------=
---------<BR>Technet=20
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Date:         Wed, 26 Dec 2001 14:09:37 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Patrick Lam <[log in to unmask]>
Subject:      MELF Land Pattern
Mime-Version: 1.0
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Hi Technetters,

We are going to use MELF (MMB0207) in our design for the first time. I need some
advice on creating the land pattern.

Thanks,
Patrick
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Date:         Wed, 26 Dec 2001 18:24:42 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: MELF Land Pattern
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Hi Patrick!

Use the same land patterns that apply for chip components that are the same
width and length. Don't use those patterns that have the little "U-shaped"
cut-out in the center of the patterns...they will cause the the MELF to skew
during reflow unless placed PRECISELY!

I don't know where those patterns were created, or why they were, but they
don't accomplish what they tried to do...

They still exist out there by the component manufacturers...just two square
pads that match the component width and length are fine...they don't need any
special pads.

-Steve Gregory-


> Hi Technetters,
>
> We are going to use MELF (MMB0207) in our design for the first time. I need
> some
> advice on creating the land pattern.
>
> Thanks,
> Patrick


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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Patrick!<BR>
<BR>
Use the same land patterns that apply for chip components that are the same width and length. Don't use those patterns that have the little "U-shaped" cut-out in the center of the patterns...they will cause the the MELF to skew during reflow unless placed PRECISELY!<BR>
<BR>
I don't know where those patterns were created, or why they were, but they don't accomplish what they tried to do...<BR>
<BR>
They still exist out there by the component manufacturers...just two square pads that match the component width and length are fine...they don't need any special pads.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Technetters,<BR>
<BR>
We are going to use MELF (MMB0207) in our design for the first time. I need some<BR>
advice on creating the land pattern.<BR>
<BR>
Thanks,<BR>
Patrick</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date:         Wed, 26 Dec 2001 22:20:13 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Adam Seychell <[log in to unmask]>
Subject:      direct metallization

How long should it take for the holes to fully plate with copper in
direct metallization system, such as in the Blackhole process from Macdermid
? Obviously, the holes should plate a small fraction of the total plating
time so as to avoid non uniform hole thickness.

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Date:         Thu, 27 Dec 2001 01:34:35 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: direct metallization
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Maybe the hardest part of answering you is to ask "what you mean FULLY plate".

In other words, how fully is fully plated?

And under what ASF....what aspect ratio....

Rudy Sedlak

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Date:         Thu, 27 Dec 2001 12:14:19 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Yehuda Weisz <[log in to unmask]>
Subject:      Re: Direct Metallization
MIME-version: 1.0
Content-type: multipart/alternative;
              boundary="Boundary_(ID_Cj0mjRgVRoST5qMyp1q2KQ)"

This is a multi-part message in MIME format.

--Boundary_(ID_Cj0mjRgVRoST5qMyp1q2KQ)
Content-type: text/plain; charset=windows-1255
Content-transfer-encoding: 7BIT

Hi Adam,
If I understand, you mean to ask: "How long should it take to create the first ppms of a full conductive copper layer inside the PTH?" (something like that - how long untill the whole hole wall gets the "good" conductivity of copper).
I cannot relate specifically to Blackhole since I work with SHADOW, but I think the answer is really not that straight forward, as Rudy implied.
In general I can tell you that the creation of this "first conductive layer" does take relativly considerable time compared to electroless copper. This time depends on many factors, starting with the conductivity of the direct metallization layer, the diameter of the via, the Aspect ratio (I did mention the latter two separately in purpose), the actual current density, the agitaion and more.
If you want to get some approximation of this time dependency of plating, I would advise you to create an artwork of a mesh that has diffrent square sizes. You can image and etch this mesh on a regular double sided board, direct plate it and then copper plate. Examine the board every few minutes and see how the gaps in the mesh "close". The rate of closing should give you some idea regarding the time.
Of couse, you must keep in mind that this time dependency that exists on the outerlayer of a board is different from what you get inside a via, especially a small and deep via. For vias you may create a board with differnt hole sizes (many coupons - each containing 4-5 hole sizes) partially routed out, direct plate and electroplate it. Every few minutes lift the board out of the plating bath and break off one coupon (your partial routing should be such that would allow easy breaking off of these coupons, but not too easy that would break off during agitation). Microsection the different coupons and get a better knowledge of the time dependency of copper. It is more difficult and time consuming but a little more accurate (the actual current density will depend on the specific board layout and it will be always different from your test board, by definition).

I'll take this opportunity to wish You and all Technetters a very happy and an even happier and less eventfull New-Year.

Yehuda Weisz

--Boundary_(ID_Cj0mjRgVRoST5qMyp1q2KQ)
Content-type: text/html; charset=windows-1255
Content-transfer-encoding: 7BIT

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=windows-1255" http-equiv=Content-Type>
<META content="MSHTML 5.00.2314.1000" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face="Times New Roman">Hi Adam,</FONT></DIV>
<DIV><FONT face="Times New Roman">If I understand, you mean to ask: "How long
should it take to create the first ppms of a full conductive copper layer inside
the PTH?" (something like that - how long untill the whole hole wall gets the
"good" conductivity of copper).</FONT></DIV>
<DIV><FONT face="Times New Roman">I cannot relate specifically to Blackhole
since I work with SHADOW, but I think the answer is really not that straight
forward, as Rudy implied.</FONT></DIV>
<DIV><FONT face="Times New Roman">In general I can tell you that the creation of
this "first conductive layer" <U>does</U> take relativly considerable time
compared to electroless copper. This time depends on many factors, starting with
the conductivity of the direct metallization layer, the diameter of the via, the
Aspect ratio (I did mention the latter two separately in purpose), the actual
current density, the agitaion and more.</FONT></DIV>
<DIV><FONT face="Times New Roman">If you want to get some approximation of this
time dependency of plating, I would advise you to create an artwork of a mesh
that has diffrent square sizes. You can image and etch this mesh on a regular
double sided board, direct plate it and then copper plate. Examine the board
every few minutes and see how the gaps in the mesh "close". The rate of closing
should give you some idea regarding the time.</FONT></DIV>
<DIV><FONT face="Times New Roman">Of couse, you must keep in mind that this time
dependency that exists on the outerlayer of a board is different from what you
get inside a via, especially a small and deep via. For vias you may create a
board with differnt hole sizes (many coupons - each containing 4-5 hole
sizes)&nbsp;partially routed out, direct plate and electroplate it. Every few
minutes lift the board out of the plating bath and break off one coupon (your
partial routing should be such that would allow easy breaking off of these
coupons, but not too easy that would break off during agitation). Microsection
the different coupons and get a better knowledge of the time dependency of
copper. It is more difficult and time consuming but a little more accurate (the
actual current density will depend on the specific board layout and it will be
always different from your test board, by definition).</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face="Times New Roman">I'll take this opportunity to wish You and all
Technetters a very happy and an even happier and less eventfull
New-Year.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face="Times New Roman">Yehuda Weisz</FONT></DIV></BODY></HTML>

--Boundary_(ID_Cj0mjRgVRoST5qMyp1q2KQ)--

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Date:         Thu, 27 Dec 2001 16:17:41 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Vinit Verma <[log in to unmask]>
Subject:      Ultrasonic Cleaning
MIME-Version: 1.0
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Hi Technetters,

I am presently evaluating post reflow PCB cleaning machines, both aqueous
and ultrasonic. I have a concern regarding ultrasonic cleaning. Read
somewhere that the ultrasonic frequencies can have an effect on the wire
bonds inside the packaging. Does anyone have any idea of this?

Thanks in anticipation.

Regards
Vinit Verma

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Date:         Thu, 27 Dec 2001 12:57:25 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Ultrasonic Cleaning
MIME-Version: 1.0
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Vinit

The risks of ultrasonics are manifold, but not necessarily too terrible.
There are several component types that can suffer: MIL style
semiconductors, but not plastic-cased ones, quartz crystals, multilayer
capacitors etc. If you have semiconductor packages which do not have the
bonding wires held in a solid mass of plastic, then you may be at risk,
but this can be minimised (but not eliminated) by choosing the frequency
range and intensity. It is essentially a compromise. There is MUCH
general misunderstanding about ultrasonics.

I personally favour an adequate spray regime over any immersion type
(the bath and shower argument!). If you wish to know more, contact me
offline.

Brian

Vinit Verma wrote:
>
> Hi Technetters,
>
> I am presently evaluating post reflow PCB cleaning machines, both aqueous
> and ultrasonic. I have a concern regarding ultrasonic cleaning. Read
> somewhere that the ultrasonic frequencies can have an effect on the wire
> bonds inside the packaging. Does anyone have any idea of this?
>
> Thanks in anticipation.
>
> Regards
> Vinit Verma
>
> ---------------------------------------------------------------------------------
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------

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Date:         Thu, 27 Dec 2001 11:07:45 -0000
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Fenner <[log in to unmask]>
Subject:      Re: Ultrasonic Cleaning
In-Reply-To:  <C176BFD6AC4AD5119CE80002A5519B029AF16F@BGLNT005>
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Hi, Vinit.

This is a topic which comes up on a regular basis, and has been thoroughly
scrutinised in this forum. The consensus is that whilst there may once have
been a real concern, with modern equipment the chances of a problem
occurring are slight at most. I suggest you visit the TechNet archives at
www.IPC.org to find your answer and info to support this statement. You will
find reams.

Happy New Year


Mike Fenner
Applications Engineer, European Operations
Indium Corporation
 T: + 44 1908 580 400
M: + 44 7810 526 317
 F: + 44 1908 580 411
 E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Vinit Verma
Sent: Thursday, December 27, 2001 10:48 AM
To: [log in to unmask]
Subject: [TN] Ultrasonic Cleaning


Hi Technetters,

I am presently evaluating post reflow PCB cleaning machines, both aqueous
and ultrasonic. I have a concern regarding ultrasonic cleaning. Read
somewhere that the ultrasonic frequencies can have an effect on the wire
bonds inside the packaging. Does anyone have any idea of this?

Thanks in anticipation.

Regards
Vinit Verma

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Date:         Thu, 27 Dec 2001 11:42:55 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         pratap singh <[log in to unmask]>
Organization: RAMP Inc.
Subject:      Seasons Greetings
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To all technetters:

Seasons Greetings and Happy New Year

http://www.rampinc.com/sgretngs.htm



_________________________
pratap singh
tel/fax: 512-255-6820
email: [log in to unmask]
WEB: www.rampinc.com


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To all technetters:
<p>Seasons Greetings and Happy New Year
<p><u><A HREF="http://www.rampinc.com/sgretngs.htm">http://www.rampinc.com/sgretngs.htm</A></u>
<br>&nbsp;
<br>&nbsp;
<p>_________________________
<br>pratap singh
<br>tel/fax: 512-255-6820
<br>email: [log in to unmask]
<br>WEB: www.rampinc.com
<br>&nbsp;</html>

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Date:         Fri, 28 Dec 2001 09:03:28 +1100
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         David Muscat <[log in to unmask]>
Subject:      Re: Ultrasonic Cleaning
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Hi Vinit,

Perhaps check out smartsonics web site they have conclusive studies and
material on this type of cleaning that is very effective.
try www.smartsonic.com

Regards

David Muscat
Arqtek Design

Vinit Verma wrote:

>Hi Technetters,
>
>I am presently evaluating post reflow PCB cleaning machines, both aqueous
>and ultrasonic. I have a concern regarding ultrasonic cleaning. Read
>somewhere that the ultrasonic frequencies can have an effect on the wire
>bonds inside the packaging. Does anyone have any idea of this?
>
>Thanks in anticipation.
>
>Regards
>Vinit Verma
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
>---------------------------------------------------------------------------------
>
>

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Date:         Thu, 27 Dec 2001 20:17:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Adam Seychell <[log in to unmask]>
Subject:      Re: direct metallization

Holes which have been metallized with conductive carbon cause
electrodeposited copper to "grow" across the hole wall surface until the
entire hole has been plated. The reason for the growth effect is simple.
Carbon is relatively high in resistance compared to copper. Thus a voltage
drop will develop a small distance across the carbon surface from the copper
cathode which it is contacting. Current density decays rapidly as distance
increases from the contacting point. The effect is copper starts to grow
longitudinally from the hole ends until meeting half. Once copper has
completely covered the entire hole wall the plating thickness begins to clim
vertically.

The copper cladding foil on the surface will begin to plating immediately
where as the hole wall always lags behind. I am interested in knowing is how
long of a time (or how many mils of electroplated copper) does it take
before the hole wall reaches the point of completely covered with copper
(hole initiation). I understand the answer depends on many variables, such
as plating C.D. and bath additives.

What are the typically hole wall initiation times in a commercial process,
such as BLACKHOLE ?


Adam Seychell

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Date:         Thu, 27 Dec 2001 22:53:09 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dennis Fritz <[log in to unmask]>
Subject:      Re: direct metallization
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In a message dated 12/27/01 9:25:39 PM Eastern Standard Time,
[log in to unmask] writes:

<< What are the typically hole wall initiation times in a commercial process,
 such as BLACKHOLE ? >>

Adam -

You have the right concepts for the "knit rate" of acid copper plating over
direct metallization.  Basically, there are two major factors.

1) The amount and activity of the carbon deposit on the hole wall

2) The condition of the acid copper brightner system to "bury" the carbon
deposit and slow down the propagation of the acid copper coverage of the
carbon deposit.

The carbon deposition factors depend on many things - the conditioning of the
hole wall to make "water hating" epoxy want to wet with aqueous carbon black
emulsion, the carbon particle size (smaller adheres better), and the
percentage of the deposited carbon kept on the hole wall through steps of
drying, microetching the carbon off the copper surface, dry film developing,
and finally pre-electroplate cleaning and microetching.

All acid copper baths have film formers to act as leveling agents to overcome
rough deposition and achieve throw into the holes of the board.  These film
forming agents slow down the propagation of copper plating, so some acid
coppers are more favorable to direct metallizaton than others.  In addition,
impurities like wetting agents in developer antifoams or the wetter in
pre-electroplate cleaners can also retard propagaiton of copper plating over
carbon.  So even if a copper bath has a very compatible brightner, the
condition of the working bath may retard knitting of copper in carbon direct
metallization holes.  I have never seen a good knit rate from a green acid
copper bath ( and I can just guess the poor performance of the same copper
plated barrels in solder shock testing).

Adam, if you wish, I can send you (off line) a reprint of a MacDermid paper
on copper plating propagation as measured by either the copper grid in hull
cell described by Yehuda Weisz, or a MacDermid propagation test vehicle sort
of like this:
   __    __    __   __
__!  !__!  !__!  !__!  !__

where the horizontal lines are offset dogbones of copper circuitry on the
opposite sides of a double side board, and the vertical lines are the plated
through holes in susscession propagated and plated copper over carbon direct
metallizaton.

Let's just say that usually, we see many holes plated in 30 minutes, so that
the knit time of a single good BlackHole deposit is a minute or so.

Let me know (off line) if you want a copy of the controls paper.

Dennis Fritz
MacDermid, Inc
Waterbury CT..

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Date:         Fri, 28 Dec 2001 15:55:49 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lum Wee Mei <[log in to unmask]>
Subject:      IPC standards adopted by DoD
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I would appreaciate any kind soul who can provide me with a quick resource as to
where I can get the list of IPC standards that DoD adopted. It would be good if
the date is also included. I have not received any reply from IPC in my earlier
request. I guess they are too busy with the coming conferences.

Regards - Wee Mei

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Date:         Fri, 28 Dec 2001 14:20:40 +0530
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Vinit Verma <[log in to unmask]>
Subject:      Re: IPC standards adopted by DoD
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Wee Mei,

The information you require can be obtained from IPC's website
http://www.ipc.org/html/fsstandards.htm and go to IPC Status of
Standardization

OR

From the home page go to Standards Activities, and from there go to IPC
status of Standardization.

Hope this helps you.

Regards
Vinit Verma

-----Original Message-----
From: Lum Wee Mei [mailto:[log in to unmask]]
Sent: Friday, December 28, 2001 1:26 PM
To: [log in to unmask]
Subject: [TN] IPC standards adopted by DoD


I would appreaciate any kind soul who can provide me with a quick resource
as to
where I can get the list of IPC standards that DoD adopted. It would be good
if
the date is also included. I have not received any reply from IPC in my
earlier
request. I guess they are too busy with the coming conferences.

Regards - Wee Mei

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Date:         Fri, 28 Dec 2001 08:53:48 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Patrick Lam <[log in to unmask]>
Subject:      Re: MELF Land Pattern
Mime-Version: 1.0
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Thanks Steve.

Patrick




"Stephen R. Gregory" <[log in to unmask]> on 12/26/2001 03:24:42 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Patrick Lam/SEL)
Subject:  Re: [TN] MELF Land Pattern



Hi Patrick!

Use the same land patterns that apply for chip components that are the same
width and length. Don't use those patterns that have the little "U-shaped"
cut-out in the center of the patterns...they will cause the the MELF to skew
during reflow unless placed PRECISELY!

I don't know where those patterns were created, or why they were, but they
don't accomplish what they tried to do...

They still exist out there by the component manufacturers...just two square
pads that match the component width and length are fine...they don't need any
special pads.

-Steve Gregory-


> Hi Technetters,
>
> We are going to use MELF (MMB0207) in our design for the first time. I need
> some
> advice on creating the land pattern.
>
> Thanks,
> Patrick



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This e-mail may contain SEL confidential information.  The opinions expressed
are not necessarily those of SEL.  Any unauthorized disclosure, distribution or
other use is prohibited.  If you received this e-mail in error, please notify
the sender, permanently delete it, and destroy any printout.  Thank you.

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Date:         Fri, 28 Dec 2001 16:04:42 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Lefebvre, Scott" <[log in to unmask]>
Subject:      Baking Tape&Reel Components
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Could anyone be so kind to let me know what temperature I can use to bake
components that are in tape and reel.  I don't want to damage  the carrier
and or cover tape.

Scott

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Date:         Fri, 28 Dec 2001 18:06:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Baking Tape&Reel Components
MIME-Version: 1.0
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Hi Scott!

This can be kinda' tricky...3M makes carrier tape that can withstand high
temperatures but also says that the coverr tape should be of a PSA (Pressure
Sensitive Adhesive) type. I have heard of baking tape and reel components
that have a heat-seal type of cover tape, and having the components sealed in
by the tape so securely that they weren't able to be used in the feeder...the
cover tape would just keep breaking...

Harris Semiconductor has a *.PDF at:

http://rel.semi.harris.com/docs/rel/tb363_2.pdf

That says to bake moisture sensitive tape and reeled components at 40 C. +5
-0 C. at lower than 5% reletive humidity for at least 192 hours...that's
8-days!

I've never baked tape and reel components, so I can't tell you anything first
hand. You may want to consider outsourcing this. There are tape and reel
companies that will take them out of their current tape, bake them, and then
re-tape them and seal them inside of a moisture proof vacuum sealed bag with
dessicant inside.

-Steve Gregory-

> Could anyone be so kind to let me know what temperature I can use to bake
> components that are in tape and reel.  I don't want to damage  the carrier
> and or cover tape.
>
> Scott
>


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<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Hi Scott!<BR>
<BR>
This can be kinda' tricky...3M makes carrier tape that can withstand high temperatures but also says that the coverr tape should be of a PSA (Pressure Sensitive Adhesive) type. I have heard of baking tape and reel components that have a heat-seal type of cover tape, and having the components sealed in by the tape so securely that they weren't able to be used in the feeder...the cover tape would just keep breaking...<BR>
<BR>
Harris Semiconductor has a *.PDF at:<BR>
<BR>
http://rel.semi.harris.com/docs/rel/tb363_2.pdf<BR>
<BR>
That says to bake moisture sensitive tape and reeled components at 40 C. +5 -0 C. at lower than 5% reletive humidity for at least 192 hours...that's 8-days! <BR>
<BR>
I've never baked tape and reel components, so I can't tell you anything first hand. You may want to consider outsourcing this. There are tape and reel companies that will take them out of their current tape, bake them, and then re-tape them and seal them inside of a moisture proof vacuum sealed bag with dessicant inside.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Could anyone be so kind to let me know what temperature I can use to bake<BR>
components that are in tape and reel.&nbsp; I don't want to damage&nbsp; the carrier<BR>
and or cover tape.<BR>
<BR>
Scott<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_e4.20396d48.295e54df_boundary--

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Date:         Fri, 28 Dec 2001 21:54:35 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Baking Tape&Reel Components
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="part1_4f.162ed5a8.295e8a6b_boundary"

--part1_4f.162ed5a8.295e8a6b_boundary
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Scott,

What are these guys? TSOP's? Just wondering...

-Steve Gregory-



> Could anyone be so kind to let me know what temperature I can use to bake
> components that are in tape and reel.  I don't want to damage  the carrier
> and or cover tape.
>
> Scott
>


--part1_4f.162ed5a8.295e8a6b_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

<HTML><FONT FACE=arial,helvetica><FONT  SIZE=2>Scott,<BR>
<BR>
What are these guys? TSOP's? Just wondering...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Could anyone be so kind to let me know what temperature I can use to bake<BR>
components that are in tape and reel.&nbsp; I don't want to damage&nbsp; the carrier<BR>
and or cover tape.<BR>
<BR>
Scott<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_4f.162ed5a8.295e8a6b_boundary--

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Date:         Sat, 29 Dec 2001 21:02:10 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Adam The Tin Compatible Etchant Guy
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Adam:

I have lost your e-mail address, and need to talk to you about your etchant.
Can you contact me please.

Thanks

Rudy Sedlak [log in to unmask]

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Date:         Mon, 31 Dec 2001 07:31:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      DFM/CE BEYOND CHECK LISTS

With a new year almost here, I find myself re-energized though not with some
silly ass rabbit in my "titanium." Won't go farther.

Need to ask some of you serious about DFM and doing it better a question
concerning successes, failures, and ISO 9000 2000. 2000's 7.3 requirement
replaced '94's 4.4. That's ok and the language is somewhat the same but for
a great, to me, improvement concerning 7.3.1's final statement as something
like the organization shall manage the interfaces between different groups,
etc....

All this says CONCURRENCE to me. What about you all. Another question is how
many of you fine folks are doing this and how? Moreover, I need input
concerning how you turned the 7.3 requirement into reality. Can't promise
I'll make you famous, but I'll certainly introduce you to the world when my
DFM/CE book is finished.

Also, based on Jiang's response about large check-lists, I'm sure you all
understand the large one is made up of many small ones to be used by
everyone in the DFM/CE team, as required.

Going to detail the check-lists and my new book, containing them, within a
few weeks. Going to produce the things on a CD for better ease of
distribution with thoughts of supplying it as a basic edition initially,
with upgrades, ala software types (what a disgusting thought that). Any
comments or suggestions appreciated. Just want to help bring us all together
to do better work from concept to customer acceptance and all that stuff.

Look forward to the new year and your input,

MoonMan

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Date:         Mon, 31 Dec 2001 23:10:36 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      DFM/CE AND ISO 9000/2000

I've received some interesting off line comments concerning my last question
concerning DFM/CE. I need to be more specific, I think, as always.

There are about 20 SHALL statements in section 7.3 (Design and development)
alone. There were about 137 shall statements in all of the previous ISO
version. The following is section 7.3 and my question is how well is
everyone dealing with converting these shall requirements into "we are"
statements and ARE YOU REALLY DOING THEM and, if so, what are your results -
GOOD OR BAD? In other words, hows your DFM/CE program working?

7.3 Design And Development

7.3.1 Design And Development Planning

The organization shall plan and control the design and development of product.

During the design and development planning, the organization shall determine

a) the design and development stages,

b) the review, verification and validation that are appropriate to each
design and development stage, and

c) the responsibilities and authorities for design and development

The organization shall manage the interfaces between different groups
involved in design and development ot ensure effective communication and
clear assignment of responsibility.
Planning output shall be updated, as appropriate, as the design and
development progresses.

7.3.2 Design and Development Inputs
Inputs relating to product requirements shall be determined and records
maintained (see 4.2.4). These inputs shall include

a) functional and performance requirements,

b) applicable statutory and regulatory requirements,

c) where applicable, information derived from previous similary designs, and

d) other requirements essential for design and development.

These inputs shall be reviewed for adequacy. Requirements shall be complete,
unambiguous and not in conflict with each other.

7.3.3 Design and Development Outputs
The outputs of design and development shall be provided in a form that
enables verification development input and shall be approved prior to release.

Design and development outputs shall

a) meet the input requirements for design and development,

b) provide appropriate information for purchasing, production and service
provision,

c) contain or reference product acceptance criteria, and

d) specify the characteristics of the product that are essential for its
safe and proper use.

7.3.4 Design and development review
At suitable stages, systematic reviews of design and development shall be
performed in accordance with planned arrangements (see 7.3.1)

a) to evaluate the ability of the results of design and development to meet
requirements, and

b) to identify any problems and propose necessary actions.

Participants in such reviews shall include representatives of functions
concerned with the design and development stage (s) being reviewed. Records
of the results of the reviews and any necessary actions shall be maintained
(see 4.2.4).

7.3.5 Design and development verification
Verification shall be performed in accordance with planned arrangements (see
7.3.1) to ensure that the design and development outputs have met the design
and development input requirements. Records of the results of the
verification and any necessary actions shall be maintained (see 4.2.4).

7.3.6 Design and development validation
Design and development validation shall be performed in accordance with
planned arrangements (see 7.3.1) to ensure that the resulting product is
capable of meeting the requirements for the specified application or
intended use, where known. Whenever practicable, validation and any
necessary actions shall be maintained (4.2.4).

7.3.7 Control of design and development changes
Design and development changes shall be identified and records maintained.
The changes shall be reviewed, verified and validated, as appropriate, and
approved before implementation. The review of design and development changes
shall include evaluation of the effect of the changes on constituent parts
and product already delivered.

Records of the results of the review of changes and any necessary actions
shall be maintained (see 4.2.4).

What I'm getting at here is if you are registered to the 2000 version of ISO
9000, you must be doing everything ISO requires. If so, you are applying and
practicing good DFM/CE principles, right?

Just want some input about how everyone is approaching this important, to us
all, subject and how well it is working so far.

Thanks a lot,

Earl Moon

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