Sedat: I happened to be monitoring TechNet and saw your request.
Please just access the IPC website (www.ipc.org) and look in the Publications search. You should find that which you need with the "IPC-HDBK-001 Handbook Guide to J-STD-001". It will provide all the changes that occurred between the B- to C-revisions.
Tom Newton
Tom Newton
Director of PWB Standards & Technology
IPC
Association Connecting Electronics Industries
2215 Sanders Road
Northbrook, IL 60062-6135
Voice: (847) 790-5349
Fax: (847) 504-2349
E-mail: [log in to unmask]
>>> [log in to unmask] 11/09/01 04:04AM >>>
Hello All,
What are the requirement changes from revision J-STD-001B to C ?
Thanks
Sedat BAYAR
Aselsan Inc.
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========================================================================Date: Fri, 9 Nov 2001 09:35:41 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Parylene coating PBGAs
Hi folks,
We're designing a board assembly, which has 2 PBGAs on it. The plan is to
coat the boards with Parylene since they're going into an industrial
environment.
Is there any information in the industry about recommendations or problems
in parylening board assemblies containing PBGAs?
Thanks in advance,
Terri
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========================================================================Date: Fri, 9 Nov 2001 10:27:44 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: Re: Inner Layer Issues...
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
A couple of questions:
How is adhesion after thermal stress? Is this a real problem or just an odd
occurance that has someone nervous/curious?
What is the etchrate of the bath?
A couple of comments:
Usually, we can see a condition called 'spearheadding' when an over-etch
condition is present on our products. The conductor length appears to be
sticking out into the hole as normal, but the width of the conductor is
about 1/2W and gradually increases as you move closer to the hole wall where
it is close to original thickness.
Another question may be has anything caused the material to swell into the
hole instead of shrink the conductor. A sweller chemistry from desmear, if
permanganate chemistry is used, can be over done to cause some materials to
swell into the hole wall.
Back to the etchrate question. We have several types of copper etchants in
production. One, non-persulfate based, is used on our electroless copper
line and has an etchrate of 30 microinches per minute. The process has been
set up to remove 50-100 microinches of copper. The chemistry, time and
temperature have been determined to maintain the total remove depth.
We also have another bath, persulfate based, used in several final finish
processes. If given that the persulfate and sulfuric acid chemistry are at
pre-established levels, the temperature and the copper concentration will
dictate the etchrate of this bath. Little or no copper in the bath will
reduce the etchrate tremendously. Too much copper and the rate will be to
aggressive. Its etchrate is 40 microinches per minute at a temperature of 95
degrees F and a copper concentration of 11g/L. The time is adjusted to reach
the desired etch depth. A bath with no copper in it will have an etchrate of
approx. 15 microinches per minute. Often a new bath is 'doped' with leftover
previous chemistry from the same tank, or copper sulfate pentahydrate is
added to provide the needed copper.
I hope this helps. Offline I can be reached at 602-276-1600 to talk of this
til I'm blue in the face (pun intended).
Russ Burdick, process engineer, printed circuit mfg.
>From: "Stephen R. Gregory" <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] Inner Layer Issues...
>Date: Thu, 8 Nov 2001 21:12:38 EST
>
>Hi Everybody!
>
>I got a email from Rene Lopez who has a problem that want's looked at by
>the
>group. I've posted two pictures up on my web page at:
>
>http://stevezeva.homestead.com/
>
>Rene is having a bit of trouble getting posts from the TechNet, and I don't
>know if it's been solved yet, that's why I've included Rene's email address
>here, do a "reply all" so Rene receives your replies.
>
>(Thanks Rene for being patient with me...)
>
>-Steve Gregory-
>
>I've pasted Rene's email to me below:
>
>Hi Steve,
>
>Here are the two pics of concern. These boards were processed thru a sodium
>persulfate solution for 45 seconds at 72 F. We know that if we reduce the
>time in
>solution we may have problems on the surface of the board/adhesion issue.
>
>More time in solution may cause more negative etchback.The material next to
>the
>innerconnects is acrylic. Tank is agitated with enductors as opposed to air
>spargers.
>
>It also has good side to side mechanical agitation. Have tried running the
>tank with the enductors off and with them on with same results.
>
>As noted on the pictures, there is some sort of rounding off of the
>innnerconnects. Does anyone know what causes this and give some input on
>how
>it can be reduced or eliminated?
>
>Any input from your peers would be of great help.
>
>Thank you very much,
>
>-Rene A. Lopez-
>
>
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
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========================================================================Date: Fri, 9 Nov 2001 11:27:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Hot Oil
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
You learn something new (or new to you) every day.
I was just told of a board finishing process called Hot Oil Solder
Levelling. It was portrayed as a very flat, nice finish. I was also told
that it is old technology, which may be why I am not familiar with it. It
is only within the last year that I have really gotten involved with
specifying board finishes. I've been searching on the internet to learn
more and am a bit confused.
My questions:
Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
what is the difference?
What are advantages/disadvantages to this over HASL, or any of the newer
so-called 'flat' finishes needed for fine pitch?
Thanks.
Genny Gibbard (mailto:[log in to unmask])
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========================================================================Date: Fri, 9 Nov 2001 12:59:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Carroll, George" <[log in to unmask]>
Subject: Re: Hot Oil
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Sounds like the old HydroSqueegee. it leaves a flat finish on an already
solder coated board but it's flat because most of the solder has been blown
off. To my recollection of 20-25 years ago, the residual solder thickness
is about .05 to .1 mil. barely more than the intermetallic. Does not have
a great shelf life.
George Carroll
Process Engineer
Siemens Energy and Automation
Johnson City, TN
[log in to unmask]
-----Original Message-----
From: Genny Gibbard [mailto:[log in to unmask]]
Sent: Friday, November 09, 2001 12:27 PM
To: [log in to unmask]
Subject: [TN] Hot Oil
You learn something new (or new to you) every day.
I was just told of a board finishing process called Hot Oil Solder
Levelling. It was portrayed as a very flat, nice finish. I was also told
that it is old technology, which may be why I am not familiar with it. It
is only within the last year that I have really gotten involved with
specifying board finishes. I've been searching on the internet to learn
more and am a bit confused.
My questions:
Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
what is the difference?
What are advantages/disadvantages to this over HASL, or any of the newer
so-called 'flat' finishes needed for fine pitch?
Thanks.
Genny Gibbard (mailto:[log in to unmask])
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========================================================================Date: Fri, 9 Nov 2001 11:53:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
X-To: Gen Gibbard <[log in to unmask]>
I do love this question and hate it. I love it because it is so refreshing
seeing the "young" folks ask important questions in consideration of a
possible new technology. I hate it because it is very ancient "technology"
and dates me.
Hot oil leveling, really fusing, is the best damn process ever invented to
both to "level" a tin-lead plated surface (really quite flat to begin with),
also another old and best process invented to ensure solderable surfaces,
and to burn a few board shops down. The most solderalbe surface is one, in
my opinion, is one that has been electroplated with tin-lead - provided it
is hot oil leveled afterword. No oxides possible here except under extreme
conditions.
Actually the minimim .0003" mils of tin-lead plating, per the old
MIL-P-55110 requirements, is not leveled. It is "fused" making it a very
homogeneous surface suitable for all through hole applications. It is in no
way suitable for SMT applications as the fusing, again not leveling, causes
a "dome" to be formed on pads that can reach a majestic height of 1 mil or
so. Hot air leveling, or HAL/HASL, reaches no such lofty heights but is an
often ruiness, to SMT placement and soldering, hill and valley terrain with
other objectional, to me and many, characteristics.
I could go on forever about the gold old days firing up the "peanut" oil, as
the fusing medium was so fondly called, and smelling something like nothing
else on earth. Personally prefer polyimide cooking in an old PHI press. Two
of the reasons, besides Bud, I've so few brain cells left as evidenced by
this diatribe. But it is fun, or was?
And on it goes,
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 11:08:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: Re: Hot Oil
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Earl,
You're right in that it was good fusing for thru hole as opposed to IR.
Reliability between the two, IR vs Hot Oil, I don't believe has been studied
to prove one better than the other. Hot Oil was/is a dirty job, i.e. whoever
pissed off the boss that day was typically the guy running hot oil:-)
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 09, 2001 10:53 AM
To: [log in to unmask]
Subject: Re: [TN] Hot Oil
I do love this question and hate it. I love it because it is so refreshing
seeing the "young" folks ask important questions in consideration of a
possible new technology. I hate it because it is very ancient "technology"
and dates me.
Hot oil leveling, really fusing, is the best damn process ever invented to
both to "level" a tin-lead plated surface (really quite flat to begin with),
also another old and best process invented to ensure solderable surfaces,
and to burn a few board shops down. The most solderalbe surface is one, in
my opinion, is one that has been electroplated with tin-lead - provided it
is hot oil leveled afterword. No oxides possible here except under extreme
conditions.
Actually the minimim .0003" mils of tin-lead plating, per the old
MIL-P-55110 requirements, is not leveled. It is "fused" making it a very
homogeneous surface suitable for all through hole applications. It is in no
way suitable for SMT applications as the fusing, again not leveling, causes
a "dome" to be formed on pads that can reach a majestic height of 1 mil or
so. Hot air leveling, or HAL/HASL, reaches no such lofty heights but is an
often ruiness, to SMT placement and soldering, hill and valley terrain with
other objectional, to me and many, characteristics.
I could go on forever about the gold old days firing up the "peanut" oil, as
the fusing medium was so fondly called, and smelling something like nothing
else on earth. Personally prefer polyimide cooking in an old PHI press. Two
of the reasons, besides Bud, I've so few brain cells left as evidenced by
this diatribe. But it is fun, or was?
And on it goes,
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 12:08:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
X-To: George Carroll <[log in to unmask]>
Carroll,
You're right. Damn, I forgot all about this super process of the past.
Another trip down a lane long ago destroyed. Kinda like route 66.
Used the Hydro a couple of times and kicked out of house. Bad, bad process.
But along came hole plugging as the advent of solder mask over bare copper
and look at us now in control of all processes available. Wonder why so many
questions? Whoha hoss!
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 12:15:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
X-To: Rick Howieson <[log in to unmask]>
Now Rick, I know you never would be, or have been, pissed off at the boss.
You sure never saw, or see, me getting pissed off at such a clean process or
the boss. Hell, at one time I was the boss then traded in the shop for such
a wonderful future ex wife. What was here name anyway. Many things left
better not remembered.
Used the IR as well. The obvious reason it had problems was it was the
focused variety. No sir, no convection there. It was best for delaminating
boards. Talk about popcorning especially while trying to level boards with
those huge external ground planes of the day. Eehaw - again those were the days.
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 10:26:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Inner Layer Issues...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------5CC6DA322305239C30C68949"
--------------5CC6DA322305239C30C68949
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi,
Are these Flex Inner layers? I think so because I don't see any glass
weave or ends. If so, is it acrylic adhesive? If so the adhesive
swells in a sensitize line, the conditioner is often the culprit.
Let us know the construction please.
Chuck Brummer
Acuson
"Stephen R. Gregory" wrote:
> Hi Everybody!
>
> I got a email from Rene Lopez who has a problem that want's looked at
> by the group. I've posted two pictures up on my web page at:
>
> http://stevezeva.homestead.com/
>
> Rene is having a bit of trouble getting posts from the TechNet, and I
> don't know if it's been solved yet, that's why I've included Rene's
> email address here, do a "reply all" so Rene receives your replies.
>
> (Thanks Rene for being patient with me...)
>
> -Steve Gregory-
>
> I've pasted Rene's email to me below:
>
> Hi Steve,
>
> Here are the two pics of concern. These boards were processed thru a
> sodium
> persulfate solution for 45 seconds at 72 F. We know that if we reduce
> the time in
> solution we may have problems on the surface of the board/adhesion
> issue.
>
> More time in solution may cause more negative etchback.The material
> next to the
> innerconnects is acrylic. Tank is agitated with enductors as opposed
> to air spargers.
>
> It also has good side to side mechanical agitation. Have tried running
> the tank with the enductors off and with them on with same results.
>
> As noted on the pictures, there is some sort of rounding off of the
> innnerconnects. Does anyone know what causes this and give some input
> on how it can be reduced or eliminated?
>
> Any input from your peers would be of great help.
>
> Thank you very much,
>
> -Rene A. Lopez-
>
>
--------------5CC6DA322305239C30C68949
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<p>Are these Flex Inner layers? I think so because I don't see any
glass weave or ends. If so, is it acrylic adhesive? If so the
adhesive swells in a sensitize line, the conditioner is often the culprit.
<p>Let us know the construction please.
<p>Chuck Brummer
<br>Acuson
<p>"Stephen R. Gregory" wrote:
<blockquote TYPE=CITE><font size=-1>Hi Everybody!</font>
<p><font size=-1>I got a email from Rene Lopez who has a problem that want's
looked at by the group. I've posted two pictures up on my web page at:</font>
<p><font size=-1><A HREF="http://stevezeva.homestead.com/">http://stevezeva.homestead.com/</A></font>
<p><font size=-1>Rene is having a bit of trouble getting posts from the
TechNet, and I don't know if it's been solved yet, that's why I've included
Rene's email address here, do a "reply all" so Rene receives your replies.</font>
<p><font size=-1>(Thanks Rene for being patient with me...)</font>
<p><font size=-1>-Steve Gregory-</font>
<p><font size=-1>I've pasted Rene's email to me below:</font>
<p><font face="arial"><font color="#000000"><font size=-1>Hi Steve,</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>Here are the
two pics of concern. These boards were processed thru a sodium</font></font></font>
<br><font face="arial"><font color="#000000"><font size=-1>persulfate solution
for 45 seconds at 72 F. We know that if we reduce the time in</font></font></font>
<br><font face="arial"><font color="#000000"><font size=-1>solution we
may have problems on the surface of the board/adhesion issue.</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>More time in
solution may cause more negative etchback.The material next to the</font></font></font>
<br><font face="arial"><font color="#000000"><font size=-1>innerconnects
is acrylic. Tank is agitated with enductors as opposed to air spargers.</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>It also has good
side to side mechanical agitation. Have tried running the tank with the
enductors off and with them on with same results.</font></font></font>
<p><font face="Arial"><font color="#000000"><font size=-1>As noted on the
pictures, there is some sort of rounding off of the innnerconnects.
Does anyone know what causes this and give some input on how it can be
reduced or eliminated?</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>Any input from
your peers would be of great help.</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>Thank you very
much,</font></font></font>
<p><font face="arial"><font color="#000000"><font size=-1>-Rene A. Lopez-</font></font></font>
<br>
<br> </blockquote>
</html>
--------------5CC6DA322305239C30C68949--
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========================================================================Date: Fri, 9 Nov 2001 13:20:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Subject: Re: Hot Oil
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Genny,
A lifetime ago I was involved with a solder leveling system called
the Lightning. It involved immersion fluxing/preheating the panel, then
immersing it in a pot of molten solder, then using an immersion hot oil with
liquid knife technology to squeegee the excess solder off the pads and out
of the holes. Theoretically a system easier to control than air since you
were working with a heavy liquid than a compressible gas. THEORETICALLY!
It was extremely dirty and dangerous, and you wouldn't want to go
there.
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 434-978-5181
FAX: 434-978-5898
e-mail: [log in to unmask]
-----Original Message-----
From: Genny Gibbard [mailto:[log in to unmask]]
Sent: Friday, November 09, 2001 12:27 PM
To: [log in to unmask]
Subject: [TN] Hot Oil
You learn something new (or new to you) every day.
I was just told of a board finishing process called Hot Oil Solder
Levelling. It was portrayed as a very flat, nice finish. I was also told
that it is old technology, which may be why I am not familiar with it. It
is only within the last year that I have really gotten involved with
specifying board finishes. I've been searching on the internet to learn
more and am a bit confused.
My questions:
Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
what is the difference?
What are advantages/disadvantages to this over HASL, or any of the newer
so-called 'flat' finishes needed for fine pitch?
Thanks.
Genny Gibbard (mailto:[log in to unmask])
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========================================================================Date: Fri, 9 Nov 2001 13:29:23 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: Hot Oil
In-Reply-To: <A71205756C62D411B06900B0D03DC136B1BE09@CONNECTOR>
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Boy this is something I have not heard of in a long long time, HOT OIL
REFOLW. We used to call it hydrosqueegee. Use the hot oil to remove the
excess solder from the solder dip operation, the predecessor to HAL. The
main problem that I can remember is the thinnest of the final coating. The
coating was so thin is was almost pure intermetallic. The solderability of
the product was hours if not minutes afer the process. If you made the
boards, raw boards that is, and assembled them across the hall, perhaps they
would solder. If you had to send them across the street forget it, they were
no longer solderable.
If was an interesting and messy operation, I would think that OSHA would
have a picnic today with that old process today.
This process was used by Sanders Associates and Honeywell back in the 60's.
The next evolution of board was the electroplated tin/lead fused process and
as Paul Harvey would say, now you know the rest of the story.
Leo Lambert
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Genny Gibbard
Sent: Friday, November 09, 2001 12:27 PM
To: [log in to unmask]
Subject: [TN] Hot Oil
You learn something new (or new to you) every day.
I was just told of a board finishing process called Hot Oil Solder
Levelling. It was portrayed as a very flat, nice finish. I was also told
that it is old technology, which may be why I am not familiar with it. It
is only within the last year that I have really gotten involved with
specifying board finishes. I've been searching on the internet to learn
more and am a bit confused.
My questions:
Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
what is the difference?
What are advantages/disadvantages to this over HASL, or any of the newer
so-called 'flat' finishes needed for fine pitch?
Thanks.
Genny Gibbard (mailto:[log in to unmask])
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========================================================================Date: Fri, 9 Nov 2001 12:27:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
X-To: George Carroll <[log in to unmask]>
George,
Sorry to have uesd you last name first. Got hung up on it as I now remember
my x's name. Also, rember she got the board shop and that is why I'm no
longer the boss but doing this.
This could all have been avoided if Genny hadn't asked the question. Bad Genny.
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 14:42:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Pads -vs- Paste -vs- Components
In-Reply-To: <A1630D6F27C0D21198AF00805F61359547D699@DDLSBS>
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Yes, because the spec (class 3) is 25% of H or 0.5 mm which ever is less.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Cathy Killen
> Sent: Friday, November 09, 2001 4:06 AM
> To: [log in to unmask]
> Subject: [TN] Pads -vs- Paste -vs- Components
>
>
> Hi,
> As technology has forced component manufacturers ever decreasing
> real estate
> on SMT, components such as capacitors have become taller, is it still
> possible to achieve IPC standards minimum fillet height of 1/4 of the
> component termination?
> And...
> What is the optimum pad size, screen aperture size and paste volume
> relationship for a range of chip components in various sizes?
>
> Thanks in advance.
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
> The information contained in the E-mail is confidential. It is
> intended only
> for the stated addressee(s) and access to it by any other person is
> unauthorised.
> The views expressed in this E-mail are those of the author, and do not
> represent the views of Smtek Europe, its associates or
> subsidiaries, unless
> otherwise expressly indicated.
> Please note: It is your responsibility to scan this E-mail for viruses.
>
> ------------------------------------------------------------------
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========================================================================Date: Fri, 9 Nov 2001 14:23:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: BGA Via's to tent or cover or not?
Mime-Version: 1.0
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I have seen different ways to address masking small vias (<13mils) under BGA.
cover them with mask prior to HASL top an bottom ( can't we need to ict probe
bottom)
cover top with mask prior to HASL (could cause trapped chemistry in via and
will not allow solder thru, we like the effect on thermal reliability for
environmental extremes)
leave the mask opening only slightly larger than via (tent)
do a post hasl mask to cover over via ( causes 2x the thickness of mask at
overlap, could be a problem with uBGA ball only 14mils dia to start with may
not touch pads)
We use #3 but have problems with rework leaving solder plugged vias that look
like shorts in xray.
If there are some other ideas or thoughts on how to design the via masking under
the BGAs I would like input. Thanks!
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========================================================================Date: Fri, 9 Nov 2001 15:39:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: High Tg FR-4
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good afternoon all,
Excellent discussion.
Has anyone substituted a higher Tg material on a board and seen a better
MTBF than the low Tg version? From my brief stint in the real world,
customer priority was high (170C) Tg material and controlled impedance.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 09, 2001 4:58 AM
To: [log in to unmask]
Subject: Re: [TN] High Tg FR-4
Daan,
I always respect your input. I have studied and written a bit on this
subject over many years. The fact remains, we have serious problems
processing plated through holes as is evidenced by recent postings on this
fourm. Another fact remains, though I'm all for the highest Tg materials
available in my MLB constructions, higher Tg materials don't make good
designs, as such, better.
Earl
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========================================================================Date: Fri, 9 Nov 2001 14:46:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Re: BGA Via's to tent or cover or not?
Warren, some board shops are able to fill the vias with a conductive paste
and then plate over the top.
This avoids the problem of a partially plugged via while giving you a
surface to probe.
The BGA side could use soldermask to cover the plugged via.
Good luck,
Terri
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Friday, November 09, 2001 3:23 PM
> To: [log in to unmask]
> Subject: [TN] BGA Via's to tent or cover or not?
>
> I have seen different ways to address masking small vias (<13mils) under
> BGA.
> cover them with mask prior to HASL top an bottom ( can't we need to ict
> probe
> bottom)
> cover top with mask prior to HASL (could cause trapped chemistry in via
> and
> will not allow solder thru, we like the effect on thermal reliability
> for
> environmental extremes)
> leave the mask opening only slightly larger than via (tent)
> do a post hasl mask to cover over via ( causes 2x the thickness of mask
> at
> overlap, could be a problem with uBGA ball only 14mils dia to start
> with may
> not touch pads)
>
>
> We use #3 but have problems with rework leaving solder plugged vias that
> look
> like shorts in xray.
>
> If there are some other ideas or thoughts on how to design the via masking
> under
> the BGAs I would like input. Thanks!
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
> -------
>
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========================================================================Date: Fri, 9 Nov 2001 16:04:49 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Larry Tawyea <[log in to unmask]>
Subject: Re: High Tg FR-4
MIME-Version: 1.0
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In a message dated 11/8/01 12:40:03 PM Central Standard Time,
[log in to unmask] writes:
Graham,
It's not for the operating temperatures but for the assembly temperatures.
Larry Tawyea
> Hello Technet
> A question for bare board gurus. Is there a difference in reliability
> between high Tg and regular Tg FR-4 ( IPC-4101/24 vs IPC-4101/21) in a
> vehicle type application?
> The end use application is less than Tg of /21 material, so not in the
> glass transition range for either material.
>
> Typically - is the CTE different between these two? (I expect that depends
> on the manufacturer to some degree). If there isn't a high temperature
> operating requirement, why select the high temp FR-4?
>
> Thanks!
>
>
>
> regards,
>
> Graham Collins
>
--part1_c.1debfa69.291d9ef1_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 11/8/01 12:40:03 PM Central Standard Time, [log in to unmask] writes:
<BR>
<BR>Graham,
<BR>
<BR>It's not for the operating temperatures but for the assembly temperatures.
<BR>
<BR>Larry Tawyea
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello Technet
<BR>A question for bare board gurus. Is there a difference in reliability between high Tg and regular Tg FR-4 ( IPC-4101/24 vs IPC-4101/21) in a vehicle type application?
<BR>The end use application is less than Tg of /21 material, so not in the glass transition range for either material.
<BR>
<BR>Typically - is the CTE different between these two? (I expect that depends on the manufacturer to some degree). If there isn't a high temperature operating requirement, why select the high temp FR-4?
<BR>
<BR>Thanks!
<BR>
<BR>
<BR>
<BR>regards,
<BR>
<BR>Graham Collins
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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========================================================================Date: Fri, 9 Nov 2001 15:55:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gus Morvillo <[log in to unmask]>
Subject: Optical Component and SMT and PTH Assembly and repair
MIME-Version: 1.0
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I am new to assembly issues regarding optical interface components (such
as those from Infineon). What should I be careful about, with respect to
Temperatures, assembly and repair techniques, etc.
G.
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========================================================================Date: Fri, 9 Nov 2001 16:11:44 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Gold removal on ceramic chip carrier...
MIME-Version: 1.0
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Hi all!
Is there anybody out there that can remove plated soft gold on ceramic chip
carriers?
I was thinking about a HASL process or something...
A little more background:
We have a customer that uses a 2" X 2" ceramic chip carrier as a plug-in
module on a larger board. These chip carriers are made by Kyocera. Inside the
chip carriers is a bare die that has been wire bonded, and then is covered
and sealed with a lid when we get them. These carriers have been plated with
soft gold in order to do the wire bonding.
There's SMT on both sides that we are going to assemble, some 20-mil pitch
QFP's, 20-mil pitch SMT connectors, some 1206's and 0603's.
Our customer says that we need to remove the gold before SMT assembly as
there's anywhere from 100-150 microinches of gold plated on all the pads from
the plating operation done down inside the cavity for the wire bonding.
So, is there anybody out there that will do this for us? As I said, it's a 2"
X 2" ceramic carrier, double-sided SMT footprints, and it's made from a LTCC
material.
There's over 4,000 of these little jewels that need to have this done to
them...
Any takers?
-Steve Gregory-
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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Is there anybody out there that can remove plated soft gold on ceramic chip carriers?
<BR>I was thinking about a HASL process or something...
<BR>
<BR>A little more background:
<BR>
<BR>We have a customer that uses a 2" X 2" ceramic chip carrier as a plug-in module on a larger board. These chip carriers are made by Kyocera. Inside the chip carriers is a bare die that has been wire bonded, and then is covered and sealed with a lid when we get them. These carriers have been plated with soft gold in order to do the wire bonding.
<BR>
<BR>There's SMT on both sides that we are going to assemble, some 20-mil pitch QFP's, 20-mil pitch SMT connectors, some 1206's and 0603's.
<BR>
<BR>Our customer says that we need to remove the gold before SMT assembly as there's anywhere from 100-150 microinches of gold plated on all the pads from the plating operation done down inside the cavity for the wire bonding.
<BR>
<BR>So, is there anybody out there that will do this for us? As I said, it's a 2" X 2" ceramic carrier, double-sided SMT footprints, and it's made from a LTCC material.
<BR>
<BR>There's over 4,000 of these little jewels that need to have this done to them...
<BR>
<BR>Any takers?
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_171.3ac33ff.291da090_boundary--
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========================================================================Date: Fri, 9 Nov 2001 15:19:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: High Tg FR-4
X-To: Larry Tawyea <[log in to unmask]>
It is both for assembly and performance when considering some past
applications and studies. The EMPF used to be part, or all, of the Navy labs
in Indy.
I and others were involved with building some of the first digital engine
controls for Pratt & Whitney evolutionary engine technologh. Some planes and
pilots were lost when first launched with the product.
I can't remember everything, as I'm sure many of you can, but the FA
findings came down to, basically, one thing. Polyimide MLB's had a problem
because they were being cured/burned/cooked in the press too long trying to
reach their maximum Tg of 270 C.
It also was found that the initial foil and innerlaminar bond strength were
reduced siginificantly over short periods at that Tg. Foil bond strength, as
an example, was reduced from about 7 pounds to less than 1. Shocking enough
unto itself but consider all the other 80's type historical facts concerning
polyimide wiring insulation and its problems associated with fly by wire
technology early on the the F-16 prgram where, again, several planes and
pilots were lost.
For me, though not a normal personal trait, moderation is the key to success
in taking any design to successful verification and validation. Lowering the
final cured Tg of polyimide, to about 250 C, enhances both its foil and
innerlaminar bond strengths. The reason, to put it simply, is reduced
oxidation of all materials in the MLB structure.
In my most recent endeavors, as well as many others, a BT/epoxy blend,
providing a "good" all around Tg is the material of choice. This is
evidenced by my work, with many others, concerning very high layer count,
very complex MLB's in excess of 50 layers with all manner of blind, buried,
and micro vias.
Still, as having before said, there is nothing like polyimide in an open
press like some of the old PSI version. Again, to specify high Tg materials
for high Tg's sake, without taking into critical consiserations and plating
thickness and ductility, is ludicrous.
Earl Moon
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========================================================================Date: Fri, 9 Nov 2001 16:52:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Gold removal on ceramic chip carrier...
MIME-Version: 1.0
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Hi Steve,
Try this: http://www.corfin.com <http://www.corfin.com>
I used them a number of years ago for various component types including
tinning of CLCCs.
Steve Sauer
-----Original Message-----
Is there anybody out there that can remove plated soft gold on ceramic chip
carriers?
I was thinking about a HASL process or something...
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========================================================================Date: Fri, 9 Nov 2001 16:08:08 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Optical Component and SMT and PTH Assembly and repair
X-To: Gus Morvillo <[log in to unmask]>
Such a huge arena but remember it's only "plumbing" just as many
RF/microwave applications. I could write a book but, as with guys like
Coombs, why bother. It/they already are written. I know there are legendary
experts that can offer books and starting points for this discussion Are you
ready?
What are all the optical terms? There's fiber optical fibers, grinding,
polishing, alignment using all manner of goodies including Silicon optical
benches, fusing. No matter, it's all plumbing until you get to the
optical/electronic interfaces and components.
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 16:08:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Optical Component and SMT and PTH Assembly and repair
X-To: Gus Morvillo <[log in to unmask]>
Such a huge arena but remember it's only "plumbing" just as many
RF/microwave applications. I could write a book but, as with guys like
Coombs, why bother. It/they already are written. I know there are legendary
experts that can offer books and starting points for this discussion Are you
ready?
What are all the optical terms? There's fiber optical fibers, grinding,
polishing, alignment using all manner of goodies including Silicon optical
benches, and fusing, etc. No matter, it's all plumbing until you get to the
optical/electronic interfaces and components.
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 18:41:52 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Hot Oil
MIME-Version: 1.0
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Genny:
They say you learn more of a subject when you try to teach it than any other
way, and if so, I may be one of the smarter guys on the subject of Hot Oil
Reflow, AKA, Fusing.
Reflow or Fusing is NOT Hydrosqueegee...which came later.
The process started out in the early days of PCB production, and involved
dipping the PCB just before application of the solder mask into a bath of oil
heated to 400+ F. The Tin/Lead deposit which had been plated on the boards
as an etch resist, like pure Tin is used today, would then melt, or "reflow"
or "fuse", in about 30-60 seconds. The board was then pulled out, rinsed
off, and Soldermask applied.
This fusing process turned the plated Tin/Lead, (which is really discrete
chrystals of Tin and Lead, and not really a true alloy) into a true alloy,
and thus it became very resistant to tarnish and oxidation, and had a VERY
long shelf life, fully equal to HAL today.
Believe it or not, the oil originally used was peanut oil, but this required
solvents to rinse off, and thus was later changed to a detergent type oil
that rinsed (slowly) in water, with A WHOLE LOT OF FOAMING....
Later a process-specific oil was developed that rinsed easily, with no
foaming.
I cannot discuss the flatness of the deposit, because nobody knew about
"flatpacks" in those days, and thus did not care.
The whole process of leaving the plated Tin/Lead deposit on the board under
the soldermask was dumped because the solder would flow during assembly, and
short out when the PCB designers began to crowd the terrain with tight
spacing of circuitry.
This process was also done (later on) in high volume shops by an IR
(Infrared) conveyorized machine.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Fri, 9 Nov 2001 17:53:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
Thank goodness there is a smarter one on such an important subject.
Whewh!
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 19:55:17 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Gold removal on ceramic chip carrier...
MIME-Version: 1.0
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boundary="part1_106.8604a9c.291dd4f5_boundary"
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Hi Steve!
I've used Corfin as well too, but this isn't a CLCC, it's more of a ceramic
substrated sub-assembly...it's got a whole bunch of different SMT parts on it
along with some SMT high density male headers that facilitate it being
plugged into matching SMT sockets on a larger (24" X 24", if you consider
that large) printed circuit assembly...
This whole deal is quite the challenge, to say the least...it's made for some
good dreams...er, nightmares...for me lately. Gonna keep pushing on though,
not gonna let a printed circuit assembly get the best of me...(I say that
now...hehehe)
-Steve Gregory-
> Hi Steve,
> Try this: http://www.corfin.com <http://www.corfin.com>
> I used them a number of years ago for various component types including
> tinning of CLCCs.
>
> Steve Sauer
>
--part1_106.8604a9c.291dd4f5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<FONT SIZE=2>Hi Steve!<BR>
<BR>
I've used Corfin as well too, but this isn't a CLCC, it's more of a ceramic substrated sub-assembly...it's got a whole bunch of different SMT parts on it along with some SMT high density male headers that facilitate it being plugged into matching SMT sockets on a larger (24" X 24", if you consider that large) printed circuit assembly...<BR>
<BR>
This whole deal is quite the challenge, to say the least...it's made for some good dreams...er, nightmares...for me lately. Gonna keep pushing on though, not gonna let a printed circuit assembly get the best of me...(I say that now...hehehe)<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi Steve,<BR>
Try this: http://www.corfin.com <http://www.corfin.com><BR>
I used them a number of years ago for various component types including<BR>
tinning of CLCCs.<BR>
<BR>
Steve Sauer<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_106.8604a9c.291dd4f5_boundary--
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========================================================================Date: Fri, 9 Nov 2001 19:36:31 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Hot Oil
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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What the heck, as long as we're going down memory lane - did you ever run
blue laminate through the reflow machine when it was set for "natural" FR-4?
Still remember the aroma.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Friday, November 09, 2001 12:16 PM
To: [log in to unmask]
Subject: Re: [TN] Hot Oil
Now Rick, I know you never would be, or have been, pissed off at the boss.
You sure never saw, or see, me getting pissed off at such a clean process or
the boss. Hell, at one time I was the boss then traded in the shop for such
a wonderful future ex wife. What was here name anyway. Many things left
better not remembered.
Used the IR as well. The obvious reason it had problems was it was the
focused variety. No sir, no convection there. It was best for delaminating
boards. Talk about popcorning especially while trying to level boards with
those huge external ground planes of the day. Eehaw - again those were the
days.
MoonMan
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========================================================================Date: Fri, 9 Nov 2001 19:48:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Gold removal on ceramic chip carrier...
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0015_01C16957.8DBC8CA0"
This is a multi-part message in MIME format.
------=_NextPart_000_0015_01C16957.8DBC8CA0
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charset="us-ascii"
Content-Transfer-Encoding: 7bit
Steve:
Excuse me for being dense. If you're going to ;lug the carrier into a
socket, why do you need to remove the gold.........or did I miss something.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Friday, November 09, 2001 6:55 PM
To: [log in to unmask]
Subject: Re: [TN] Gold removal on ceramic chip carrier...
Hi Steve!
I've used Corfin as well too, but this isn't a CLCC, it's more of a ceramic
substrated sub-assembly...it's got a whole bunch of different SMT parts on
it along with some SMT high density male headers that facilitate it being
plugged into matching SMT sockets on a larger (24" X 24", if you consider
that large) printed circuit assembly...
This whole deal is quite the challenge, to say the least...it's made for
some good dreams...er, nightmares...for me lately. Gonna keep pushing on
though, not gonna let a printed circuit assembly get the best of me...(I say
that now...hehehe)
-Steve Gregory-
Hi Steve,
Try this: http://www.corfin.com <http://www.corfin.com>
I used them a number of years ago for various component types including
tinning of CLCCs.
Steve Sauer
------=_NextPart_000_0015_01C16957.8DBC8CA0
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=us-ascii">
<META content="MSHTML 5.50.4207.2601" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=480124701-10112001><FONT face=Arial color=#0000ff
size=2>Steve:</FONT></SPAN></DIV>
<DIV><SPAN class=480124701-10112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=480124701-10112001><FONT face=Arial color=#0000ff size=2>Excuse
me for being dense. If you're going to ;lug the carrier into a socket, why
do you need to remove the gold.........or did I miss
something.</FONT></SPAN></DIV>
<DIV><SPAN class=480124701-10112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=480124701-10112001><FONT face=Arial color=#0000ff size=2>Don
Vischulis</FONT></SPAN></DIV>
<DIV><SPAN class=480124701-10112001></SPAN> </DIV>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. Gregory<BR><B>Sent:</B>
Friday, November 09, 2001 6:55 PM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Gold removal on ceramic chip
carrier...<BR><BR></FONT></DIV><FONT size=2>Hi Steve!<BR><BR>I've used Corfin as
well too, but this isn't a CLCC, it's more of a ceramic substrated
sub-assembly...it's got a whole bunch of different SMT parts on it along with
some SMT high density male headers that facilitate it being plugged into
matching SMT sockets on a larger (24" X 24", if you consider that large)
printed circuit assembly...<BR><BR>This whole deal is quite the challenge, to
say the least...it's made for some good dreams...er, nightmares...for me lately.
Gonna keep pushing on though, not gonna let a printed circuit assembly get the
best of me...(I say that now...hehehe)<BR><BR>-Steve Gregory-<BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">Hi Steve,<BR>Try this: http://www.corfin.com
<http://www.corfin.com><BR>I used them a number of years ago for various
component types including<BR>tinning of CLCCs.<BR><BR>Steve
Sauer<BR></BLOCKQUOTE><BR><BR></FONT></BODY></HTML>
------=_NextPart_000_0015_01C16957.8DBC8CA0--
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========================================================================Date: Fri, 9 Nov 2001 21:14:42 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Gold removal on ceramic chip carrier...
MIME-Version: 1.0
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Hi Don!
You're not being dense, I don't think I've explained things well
enough...this is one of those times that a picture is worth a thousand words.
I've got some drawings at work that I can scan and post on my web page...but
I'll need to get back at work to do that.
This little 2-inch-by-2-inch substrate, is an assembly in, and of, itself.
It's a double sided SMT assembly with at what I would guess close to
100-components on it. SDRAM, caps, some resistors, and SMT interconnect
devices that allow it to be plugged into a main board.
In the center of it, is a die that has been wire bonded and sealed with a
metal lid, that's the way we'll get them. We'll receive them this way, with
all this soft gold plated over everything, and then need to assemble all the
SMT components that I spoke of above, to this ceramic substrate that just has
the sealed, wire bonded die installed inside...that's what kyocera gives
us...this is a mini, double sided, pure SMT, ceramic substrated assembly for
all tends and purposes.
I just need to figure out how to get rid of all the gold on the SMT pads that
resulted from plating the whole deal so that the wire bond operation could be
performed for the die in the cavity of the substrate. It seems that the gold
that needed to plated for that process couldn't be restricted to just the
cavity where the die is, but was plated all over the whole substrate, with it
being even thicker outside the cavity outside where the die is, where the
wire bonding is being done...
I know that something like this hasn't been seen by many others, and I
understand all the questions. I just want to learn if the is a way to HASL or
wash the gold away from a 2" X 2" ceramic substrate...I'll show some
drawings of what this little beast is and then it will be easier to
understand....
-Steve Gregory-
> Steve:
>
> Excuse me for being dense. If you're going to ;lug the carrier into a
> socket, why do you need to remove the gold.........or did I miss something.
>
> Don Vischulis
>
--part1_6a.16315b30.291de792_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<FONT SIZE=2>Hi Don!<BR>
<BR>
You're not being dense, I don't think I've explained things well enough...this is one of those times that a picture is worth a thousand words. I've got some drawings at work that I can scan and post on my web page...but I'll need to get back at work to do that.<BR>
<BR>
This little 2-inch-by-2-inch substrate, is an assembly in, and of, itself. It's a double sided SMT assembly with at what I would guess close to 100-components on it. SDRAM, caps, some resistors, and SMT interconnect devices that allow it to be plugged into a main board. <BR>
<BR>
In the center of it, is a die that has been wire bonded and sealed with a metal lid, that's the way we'll get them. We'll receive them this way, with all this soft gold plated over everything, and then need to assemble all the SMT components that I spoke of above, to this ceramic substrate that just has the sealed, wire bonded die installed inside...that's what kyocera gives us...this is a mini, double sided, pure SMT, ceramic substrated assembly for all tends and purposes.<BR>
<BR>
I just need to figure out how to get rid of all the gold on the SMT pads that resulted from plating the whole deal so that the wire bond operation could be performed for the die in the cavity of the substrate. It seems that the gold that needed to plated for that process couldn't be restricted to just the cavity where the die is, but was plated all over the whole substrate, with it being even thicker outside the cavity outside where the die is, where the wire bonding is being done...<BR>
<BR>
I know that something like this hasn't been seen by many others, and I understand all the questions. I just want to learn if the is a way to HASL or wash the gold away from a 2" X 2" ceramic substrate...I'll show some drawings of what this little beast is and then it will be easier to understand....<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve:</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Excuse me for being dense. If you're going to ;lug the carrier into a socket, why do you need to remove the gold.........or did I miss something.</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Don Vischulis</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT></HTML>
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========================================================================Date: Sat, 10 Nov 2001 17:23:29 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Hot Oil
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Hi, all!
Please let me set the record straight.
1) Hot oil reflow is NOT the same as hot-oil levelling
2) Hot oil reflow consists of reflowing an electrolytic tin/lead
plating, typically about 30 um thickness. It melts the plated metals
into solder and leaves a good, thick solder coat, just like IR reflow,
except smoother and shinier. The process was usually a three bath affair
with simple immersion in oil at, say, 140°C preheat for 10 secs, 230°C
fusion for about 3 seconds (more for thick boards) and 190°C quench for
a couple of seconds, so that the solder "froze" very rapidly on
extraction.
3) Hot oil levelling (such as the Hydrosqueegee) consists of wave
soldering or dip soldering the bare board and then removing the excess
solder by jets of hot oil. This is the process that, badly adjusted,
just left the intermetallics but, correctly adjusted, gave a result
quite similar to HASL, except that the coating was slightly more uniform
because the interface between the surface tension of two liquids is
better than between the molten solder and air, which tends to form a
bumpier meniscus.
4) In both cases, 3 types of oil were used. The initial one was Shell
Peblum A, which was a mineral oil designed originally for levelling the
tin on sheet steel used for making tin cans. For reasons of a) a
relatively short lifetime b) a fairly high cost, some intrepid
adventurers replaced it with peanut oil. Then some of the flux
manufacturers brought out special water-soluble "oils", such as Lonco
Fusecote 240. These were, in fact, blends of polyglycols and glycol
ethers. They had a lifetime in the machine of about 3 - 4 times that of
the mineral Peblum oil at about the same price and much reduced
operating costs (water clean, instead of solvent cleaning was also
cheaper).
5) All three oils were smelly, unless good ventilation and quite messy,
which was their downfall, in both processes. There was also worry about
loss of SIR with the water-soluble oils, although this was more worry
than fact. They also fell into some disrepute by a number of fires,
especially with peanut oil which has a flash point under the melting
point of solder. I don't believe there was a fire with the water-soluble
oils which had a TAG CC flash point of about 260°C, dropping to about
250°C after about three weeks of 1 shift use.
6) Hot-oil reflow was more popular than levelling as it was a very
simple process which was exceedingly easy to control and the fusion
temperature, unlike IR, was asymptotic. It was also popular for 3D flex
circuits which were simply impossible to reflow with IR.
For the anecdote, something like the Hydrosqueegee, but more powerful,
is coming back into the thinking within Europe in preparation for WEEE.
By putting in an end-of-life assembled board, all the solder can be
"washed" off and recovered for recycling. Roughly 95% of the lead and
85% of the tin can be recovered (more tin remains on the intermetallic
residues).
Hope this trip down 30 years of memory lane will explain.
Brian
Genny Gibbard wrote:
>
> You learn something new (or new to you) every day.
> I was just told of a board finishing process called Hot Oil Solder
> Levelling. It was portrayed as a very flat, nice finish. I was also told
> that it is old technology, which may be why I am not familiar with it. It
> is only within the last year that I have really gotten involved with
> specifying board finishes. I've been searching on the internet to learn
> more and am a bit confused.
> My questions:
> Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
> what is the difference?
> What are advantages/disadvantages to this over HASL, or any of the newer
> so-called 'flat' finishes needed for fine pitch?
>
> Thanks.
>
> Genny Gibbard (mailto:[log in to unmask])
>
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========================================================================Date: Sat, 10 Nov 2001 10:11:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Hot Oil
X-To: "Brian E." <[log in to unmask]>
Brian,
Truly a smarter man than anyone else claims. However, I said some of that
stuff. Just can't put it into words even resembling yours. How do you do all
this stuff from - what island is that? Now, we really know the rest of the
story.
Is Hydro really experienceing a come back? If so, Genny had it right about a
new/ancient technology. I am in, how shall I say it, awe and hope to become
even more humble while learing about this stuff. The question is: Why didn't
you just put an end to all this in the begining?
High regards,
MoonMan
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========================================================================Date: Sat, 10 Nov 2001 12:15:59 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Reflow Process Profiling Methods
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Hi Nancy,
IPC-7530, Guidelines for Temperature Profiling for Mass Soldering Processes
(Reflow & Wave), was written just to answer your questions.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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========================================================================Date: Sat, 10 Nov 2001 12:15:58 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: High Tg FR-4
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Hi Collin & MoonMan,
The high Tg actually is much more important during the assembly processes,
particularly manual soldering, than in field operation. Remember, the solder
process excursions are all above Tg, but how much above the Tg can make the
difference between barrel cracks and no barrel cracks.
Also, the glass transition region of the epoxies used for FR-4 starts about
25C below Tg; thus, merely stating that "the end use application is less than
Tg" is inadequate.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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========================================================================Date: Sat, 10 Nov 2001 12:49:02 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: High Tg FR-4
X-To: Werner Engelmaier <[log in to unmask]>
Well said Werner,
However, I am more concerned about surviing operational performance than
simple assembly processes if I am a user of that product.
I?ve never disagreed with the fact we must survive assembly. The old 55110,
and the new one?s, specified that test coupon B, derived from specified
quality conformance test circuitry must be subjected to an extensive
preconditioning period prior to being subjected to a solder ?float? of 550
F. for 10 seconds to ensure the most extreme soldering conditions, during
assembly, would ensure acceptable product. Also, thermal shock conditions
were to be imposed as ?55 C to 125 C in an elevator ride between low and
high temperature chambers simulating PERFORMANCE conditions. Therefore, if
the tests yielded acceptable results, no delamination, in the laminate
evaluation zone, or hole cracking, in the thermal evaluation zone, in
accordance with all that specification?s requirements, it would pass all
assembly processes. In other words, both assembly and performance conditions
would be satisfied and product would be acceptable.
All this meant if I?m a pilot sitting in my F-16 at 40,000 feet and
counting on going from ground level to that altitude, I certainly would feel
a bit more comfortable if my flight control system assembly was capable of
surviving the thermal transition both as stress and shock. To say the
assembly process is more important and it correlates directly to Tg, is
inadequate. Simply, it is but the first step and if failures exist at the
assembly level, they certainly will during performance ? at altitude as but
one example. AS LONG AS IT WORKS WELL having survived some nearly bad
fabrication/plating processes, I don't care the Tg. After all, we've
successfully used unmodified epoxy resin systems for years even though they
keep getting better.
MoonMan
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========================================================================Date: Sun, 11 Nov 2001 12:09:55 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Inner Layer Issues...
MIME-Version: 1.0
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Stephen,
Just looking on the shape of interconnect,it looks,that the innerlayer is
not equally microetched comparing laminate side and prepreg side. It seems
to me,that on prepreg side the etching rate is higher.
What desmear process is applied? Permanganate is doing strange things with
acrylic adhesive in conjuction with different surface preparation before
lamination.
I would advice your friend to take a look on "regular" multilayer and than
ask himself what are the differences in process path ( laminating
conditions/drilling/desmear). The negative etchback is just result of
previous processes and to my opinion persulfate microetch has nothing with
the problem itself.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: å ðåáîáø 09 2001 4:13
> To: [log in to unmask]
> Subject: [TN] Inner Layer Issues...
>
> Hi Everybody!
>
> I got a email from Rene Lopez who has a problem that want's looked at by
> the group. I've posted two pictures up on my web page at:
>
> http://stevezeva.homestead.com/
>
> Rene is having a bit of trouble getting posts from the TechNet, and I
> don't know if it's been solved yet, that's why I've included Rene's email
> address here, do a "reply all" so Rene receives your replies.
>
> (Thanks Rene for being patient with me...)
>
> -Steve Gregory-
>
> I've pasted Rene's email to me below:
>
> Hi Steve,
>
> Here are the two pics of concern. These boards were processed thru a
> sodium
> persulfate solution for 45 seconds at 72 F. We know that if we reduce the
> time in
> solution we may have problems on the surface of the board/adhesion issue.
>
> More time in solution may cause more negative etchback.The material next
> to the
> innerconnects is acrylic. Tank is agitated with enductors as opposed to
> air spargers.
>
> It also has good side to side mechanical agitation. Have tried running the
> tank with the enductors off and with them on with same results.
>
> As noted on the pictures, there is some sort of rounding off of the
> innnerconnects. Does anyone know what causes this and give some input on
> how it can be reduced or eliminated?
>
> Any input from your peers would be of great help.
>
> Thank you very much,
>
> -Rene A. Lopez-
>
>
>
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========================================================================Date: Sun, 11 Nov 2001 15:13:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Seeking info on replacement for IP Alcohol which is no longer
allowed for cleaning of electronics in California
X-cc: Jack Crawford <[log in to unmask]>
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11/11/2001
Folks, the law makers in California are at it again. Per South Coast Air Quality Management (SC AQMD) Rule 1171, the VOC solvent limits are lowered, again, starting in January 2002. The amount of VOC in lb/gal for electronic cleaning is 0.83 for electronic apparatus as well as for repair cleaning. I believe IP alcohol is around 6.55 lb/gal. Thus, IP alcohol is no longer allowed for electronic cleaning in California as of 1/1/2002.
I am checking with California to see if this also means that use of IP in Ionic cleanliness testers is also dis-allowed. Seems to me that we can consider these testers to be sccientific instruments which are exempt from the Rule 1171 solvent requirements. This is what I am proposing to the SC AQMD.
Does anyone out there have any experience with use of Dow Corning OS-2 or OS-20 as a solvent to remove RMA flux in military applications? The company claims the solvents are replacements for IP alcohol. These solvents are Octamethyltrisiloxane based.
------=_NextPart_000_00C7_01C16AC3.775F8440
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4611.1300" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>11/11/2001</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Folks, the law makers in California are at it
again. Per South Coast Air Quality Management (SC AQMD) Rule 1171,
the VOC solvent limits are lowered, again, starting in January 2002.
The amount of VOC in lb/gal for electronic cleaning is 0.83 for electronic
apparatus as well as for repair cleaning. I believe IP alcohol is around
6.55 lb/gal. Thus, IP alcohol is no longer allowed for electronic cleaning
in California as of 1/1/2002.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I am checking with California to see if this also
means that use of IP in Ionic cleanliness testers is also dis-allowed.
Seems to me that we can consider these testers to be sccientific instruments
which are exempt from the Rule 1171 solvent requirements. This is what I
am proposing to the SC AQMD.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Does anyone out there have any experience with use
of Dow Corning OS-2 or OS-20 as a solvent to remove RMA flux in military
applications? The company claims the solvents are replacements for IP
alcohol. These solvents are Octamethyltrisiloxane
based.</FONT></DIV></BODY></HTML>
------=_NextPart_000_00C7_01C16AC3.775F8440--
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========================================================================Date: Mon, 12 Nov 2001 09:17:03 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no l
onger allowed for cleaning of electronics in California
MIME-Version: 1.0
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Hi there,
I trialled the OS-20 which was recommended to me by Dow Corning as a Solvent
for cleaning conformal coating brushes, dispense nozzles etc. I had very
limited success with this, as I found IPA to be more effective. However, I
never tried it as a flux remover.
-----Original Message-----
From: Bogert [mailto:[log in to unmask]]
Sent: Monday, 12 November 2001 09:14
To: [log in to unmask]
Subject: [TN] Seeking info on replacement for IP Alcohol which is no longer
allowed for cleaning of electronics in California
11/11/2001
Folks, the law makers in California are at it again. Per South Coast Air
Quality Management (SC AQMD) Rule 1171, the VOC solvent limits are lowered,
again, starting in January 2002. The amount of VOC in lb/gal for electronic
cleaning is 0.83 for electronic apparatus as well as for repair cleaning. I
believe IP alcohol is around 6.55 lb/gal. Thus, IP alcohol is no longer
allowed for electronic cleaning in California as of 1/1/2002.
I am checking with California to see if this also means that use of IP in
Ionic cleanliness testers is also dis-allowed. Seems to me that we can
consider these testers to be sccientific instruments which are exempt from
the Rule 1171 solvent requirements. This is what I am proposing to the SC
AQMD.
Does anyone out there have any experience with use of Dow Corning OS-2 or
OS-20 as a solvent to remove RMA flux in military applications? The company
claims the solvents are replacements for IP alcohol. These solvents are
Octamethyltrisiloxane based.
------_=_NextPart_001_01C16AED.D3F49720
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.2614.3500" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classthere,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class<DIV><FONT color=#0000ff face=Arial size=2><SPAN classtrialled the OS-20 which was recommended to me by Dow Corning as a Solvent for
cleaning conformal coating brushes, dispense nozzles etc. I had very
limited success with this, as I found IPA to be more effective. However, I
never tried it as a flux remover. </SPAN></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Bogert
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, 12 November 2001
09:14<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Seeking info on
replacement for IP Alcohol which is no longer allowed for cleaning of
electronics in California<BR><BR></DIV></FONT>
<DIV><FONT face=Arial size=2>11/11/2001</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Folks, the law makers in California are at it
again. Per South Coast Air Quality Management (SC AQMD) Rule 1171,
the VOC solvent limits are lowered, again, starting in January
2002. The amount of VOC in lb/gal for electronic cleaning is 0.83 for
electronic apparatus as well as for repair cleaning. I believe IP
alcohol is around 6.55 lb/gal. Thus, IP alcohol is no longer allowed for
electronic cleaning in California as of 1/1/2002.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I am checking with California to see if this also
means that use of IP in Ionic cleanliness testers is also dis-allowed.
Seems to me that we can consider these testers to be sccientific instruments
which are exempt from the Rule 1171 solvent requirements. This is what I
am proposing to the SC AQMD.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Does anyone out there have any experience with
use of Dow Corning OS-2 or OS-20 as a solvent to remove RMA flux in military
applications? The company claims the solvents are replacements for IP
alcohol. These solvents are Octamethyltrisiloxane
based.</FONT></DIV></BLOCKQUOTE></BODY></HTML>
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---------------------------------------------------------------------------------
========================================================================Date: Sun, 11 Nov 2001 15:52:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no l
onger allowed for cleaning of electronics in California
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Thanks.
----- Original Message -----
From: Michael Bell
To: [log in to unmask]
Sent: Sunday, November 11, 2001 3:17 PM
Subject: Re: [TN] Seeking info on replacement for IP Alcohol which is no l onger allowed for cleaning of electronics in California
Hi there,
I trialled the OS-20 which was recommended to me by Dow Corning as a Solvent for cleaning conformal coating brushes, dispense nozzles etc. I had very limited success with this, as I found IPA to be more effective. However, I never tried it as a flux remover.
-----Original Message-----
From: Bogert [mailto:[log in to unmask]]
Sent: Monday, 12 November 2001 09:14
To: [log in to unmask]
Subject: [TN] Seeking info on replacement for IP Alcohol which is no longer allowed for cleaning of electronics in California
11/11/2001
Folks, the law makers in California are at it again. Per South Coast Air Quality Management (SC AQMD) Rule 1171, the VOC solvent limits are lowered, again, starting in January 2002. The amount of VOC in lb/gal for electronic cleaning is 0.83 for electronic apparatus as well as for repair cleaning. I believe IP alcohol is around 6.55 lb/gal. Thus, IP alcohol is no longer allowed for electronic cleaning in California as of 1/1/2002.
I am checking with California to see if this also means that use of IP in Ionic cleanliness testers is also dis-allowed. Seems to me that we can consider these testers to be sccientific instruments which are exempt from the Rule 1171 solvent requirements. This is what I am proposing to the SC AQMD.
Does anyone out there have any experience with use of Dow Corning OS-2 or OS-20 as a solvent to remove RMA flux in military applications? The company claims the solvents are replacements for IP alcohol. These solvents are Octamethyltrisiloxane based.
------=_NextPart_000_001D_01C16AC8.CF2386E0
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<DIV><FONT face=Arial size=2>Thanks.</FONT></DIV>
<BLOCKQUOTE dir=ltr
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">Michael
Bell</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Sunday, November 11, 2001 3:17
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] Seeking info on
replacement for IP Alcohol which is no l onger allowed for cleaning of
electronics in California</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN class=000261420-11112001>Hi
there,</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=000261420-11112001></SPAN></FONT> </DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN class=000261420-11112001>I
trialled the OS-20 which was recommended to me by Dow Corning as a Solvent for
cleaning conformal coating brushes, dispense nozzles etc. I had very
limited success with this, as I found IPA to be more effective. However,
I never tried it as a flux remover. </SPAN></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Bogert
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, 12 November 2001
09:14<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Seeking info on
replacement for IP Alcohol which is no longer allowed for cleaning of
electronics in California<BR><BR></DIV></FONT>
<DIV><FONT face=Arial size=2>11/11/2001</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Folks, the law makers in California are at it
again. Per South Coast Air Quality Management (SC AQMD) Rule
1171, the VOC solvent limits are lowered, again, starting in January
2002. The amount of VOC in lb/gal for electronic cleaning is 0.83 for
electronic apparatus as well as for repair cleaning. I believe IP
alcohol is around 6.55 lb/gal. Thus, IP alcohol is no longer allowed
for electronic cleaning in California as of 1/1/2002.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I am checking with California to see if this
also means that use of IP in Ionic cleanliness testers is also
dis-allowed. Seems to me that we can consider these testers to be
sccientific instruments which are exempt from the Rule 1171 solvent
requirements. This is what I am proposing to the SC AQMD.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Does anyone out there have any experience with
use of Dow Corning OS-2 or OS-20 as a solvent to remove RMA flux in military
applications? The company claims the solvents are replacements for IP
alcohol. These solvents are Octamethyltrisiloxane
based.</FONT></DIV></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_001D_01C16AC8.CF2386E0--
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========================================================================Date: Mon, 12 Nov 2001 10:37:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Parylene coating PBGAs
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
No problems that I know of apart from the hassle of rework. As you know,
parylene has to be "sand-blasted" off to remove it, and if it gets
underneath BGA's, it could make their removal pretty difficult. Do you
plan to epoxy underfill the BGA's at all? It might be worth considering if
you don't have such a plan. A capillary action flow-type underfill applied
after the BGA has been mounted will support the BGA solder joints, but it
has two other advantages in you case - 1) it is reworkable at soldering
temperature and 2) it will act as a barrier to parylene getting underneath
the BGA's and holding them to the board in a death grip.
Peter Duncan
"Houston,
Terri" To: [log in to unmask]
<Terri_Housto cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
[log in to unmask]> Aero/ST Group)
Sent by: Subject: [TN] Parylene coating PBGAs
TechNet
<[log in to unmask]
ORG>
11/10/01
12:35 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi folks,
We're designing a board assembly, which has 2 PBGAs on it. The plan is to
coat the boards with Parylene since they're going into an industrial
environment.
Is there any information in the industry about recommendations or problems
in parylening board assemblies containing PBGAs?
Thanks in advance,
Terri
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========================================================================Date: Mon, 12 Nov 2001 10:49:22 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Hot Oil
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Genny,
If you're hunting for info on the Net, the Hot Oil levelling process used
also to be known as "Hydro-Squeegee". It did indeed produce a fairly flat
finish ( often better than some HASL finishes I've seen), but as the name
suggests, it's messier than an air knife.
If dim and distant memory serves at all well, Hot Oil Reflow did just that
- it reflowed the solder on the board with no attempt to level it in any
way, whereas the Hot Oil Solder Levelling or Hyrosqueegee method did level
solder. My previous Company used to use it recover boards from which the
components had been salvaged, or on which the HASL finish was too thick to
start with. This process originated in the days of "conventional"
technology (plated through-hole), and I haven't so far heard of it being
used for SMT boards. Not to say it couldn't be used for SMT, but HASL is
possible more accurate and less contaminating.
Peter Duncan
Genny Gibbard
<Genny.Gibbard@W To: [log in to unmask]
AVECOM.CA> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Hot Oil
>
11/10/01 01:27
AM
Please respond
to "TechNet
E-Mail Forum."
You learn something new (or new to you) every day.
I was just told of a board finishing process called Hot Oil Solder
Levelling. It was portrayed as a very flat, nice finish. I was also told
that it is old technology, which may be why I am not familiar with it. It
is only within the last year that I have really gotten involved with
specifying board finishes. I've been searching on the internet to learn
more and am a bit confused.
My questions:
Is Hot Oil Reflow and Hot Oil Surface Levelling the same thing? If not,
what is the difference?
What are advantages/disadvantages to this over HASL, or any of the newer
so-called 'flat' finishes needed for fine pitch?
Thanks.
Genny Gibbard (mailto:[log in to unmask])
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========================================================================Date: Mon, 12 Nov 2001 11:10:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA Via's to tent or cover or not?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Plugging vias with conductive paste is limited to holes over a certain size
and aspect ratio. Anything below 10 to 12 mils is not really fillable and,
that aside, an aspect ratio of more than 1:6 (dia:depth) is also tricky.
Equally, if you're dealing with blind vias that need to be filled, the max
diameter I could get filled on a 7 mils deep hole is 24 mils.
My two cents-worth. But what's 2 cents worth? Yesterday I was approached by
a very poor-looking old fellow on a tricycle cart, begging for change to
get something to eat. I gave him the small amount of change I had in my
pocket - just over one Singapore dollar, which included a 5 cent "copper"
coin. The fellow actually called me back to return the copper - it wasn't
any use to him. Who said beggers aren't choosers?
Peter Duncan
"Houston,
Terri" To: [log in to unmask]
<Terri_Housto cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
[log in to unmask]> Aero/ST Group)
Sent by: Subject: Re: [TN] BGA Via's to tent or cover
TechNet or not?
<[log in to unmask]
ORG>
11/10/01
04:46 AM
Please
respond to
"TechNet
E-Mail
Forum."
Warren, some board shops are able to fill the vias with a conductive paste
and then plate over the top.
This avoids the problem of a partially plugged via while giving you a
surface to probe.
The BGA side could use soldermask to cover the plugged via.
Good luck,
Terri
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Friday, November 09, 2001 3:23 PM
> To: [log in to unmask]
> Subject: [TN] BGA Via's to tent or cover or not?
>
> I have seen different ways to address masking small vias (<13mils) under
> BGA.
> cover them with mask prior to HASL top an bottom ( can't we need to
ict
> probe
> bottom)
> cover top with mask prior to HASL (could cause trapped chemistry in
via
> and
> will not allow solder thru, we like the effect on thermal reliability
> for
> environmental extremes)
> leave the mask opening only slightly larger than via (tent)
> do a post hasl mask to cover over via ( causes 2x the thickness of
mask
> at
> overlap, could be a problem with uBGA ball only 14mils dia to start
> with may
> not touch pads)
>
>
> We use #3 but have problems with rework leaving solder plugged vias that
> look
> like shorts in xray.
>
> If there are some other ideas or thoughts on how to design the via
masking
> under
> the BGAs I would like input. Thanks!
>
>
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>
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========================================================================Date: Sun, 11 Nov 2001 23:38:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no longer
allowe...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
First....Suspect that an octyl Siloxane would be classified by SCAQMD (for
non-Californians, this is Southern California Air Quality Management
District) as a VOC..
They do not understand that there is virtually any such thing as a
NON-Volatile organic.
However, they do understand about consumption and use, and if you can
demonstrate that your IPA in your ionic tester does not consume significant
levels of IPA, they will probably let you off the hook.
If you need help, I can assist you in "proving" this to the SCAQMD, I have
done this for some of our products.
I suspect that a lot of what you life about IPA for cleaning is that the
residues evaporate, leaving nothing significant behind, and if this is a key
property, you may be in trouble, as you will definitely need a volatile
organic to give you this property.
Good luck.
Rudy Sedlak
RD Chemical Company (650-962-8004)
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========================================================================Date: Mon, 12 Nov 2001 08:50:53 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi!
The law is an ass! Logically, they should stop the sale and consumption
of all alcoholic liquor, as well. You could always try cleaning in
whisky!
Your best bet is to go water-soluble. Certainly, the OS-20 will be
classed as a VOC. What this law, and other VOC ones, in Europe as well
as in the USA, forget is that the effect of a VOC on the environment
depends on many factors, not the least of which are emissions. An open
bath of hot solvent is more emissive than a closed bath of a cold
solution of the same solvent. Then, not all solvents are equal in their
effect as an ozone smog precursor. The latter cannot be produced without
NOxs, as well, so that emissions in the middle of LA are more likely to
be serious than in the middle of the Mojave Desert (OK for the guys at
China Lake!) and most hydrocarbon solvents have a very short atmospheric
residence time, so that they are not going to roll down the hill into LA
from there!
As for the ionic contamination tester, the specs state quite clearly IPA
and nothing else, but the quantity used is so small that you must be
able to claim an essential use exemption. Anyway, testing is not
cleaning and you specifically state "for electronic cleaning".
Be comforted, no matter what you go for will be a better cleaner than
IPA! It may remove the thick of the rosin residues, but it is decidedly
not a good flux remover. If I were you, water-soluble is the answer.
Brian
> Bogert wrote:
>
> 11/11/2001
>
> Folks, the law makers in California are at it again. Per South Coast
> Air Quality Management (SC AQMD) Rule 1171, the VOC solvent limits are
> lowered, again, starting in January 2002. The amount of VOC in lb/gal
> for electronic cleaning is 0.83 for electronic apparatus as well as
> for repair cleaning. I believe IP alcohol is around 6.55 lb/gal.
> Thus, IP alcohol is no longer allowed for electronic cleaning in
> California as of 1/1/2002.
>
> I am checking with California to see if this also means that use of IP
> in Ionic cleanliness testers is also dis-allowed. Seems to me that we
> can consider these testers to be sccientific instruments which are
> exempt from the Rule 1171 solvent requirements. This is what I am
> proposing to the SC AQMD.
>
> Does anyone out there have any experience with use of Dow Corning OS-2
> or OS-20 as a solvent to remove RMA flux in military applications?
> The company claims the solvents are replacements for IP alcohol.
> These solvents are Octamethyltrisiloxane based.
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========================================================================Date: Mon, 12 Nov 2001 09:16:25 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: BGA Via's to tent or cover or not?
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Warren,
What about covering the BGA-via's on both sides, with addition of dedicated testpads on the bottom ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> <[log in to unmask]> 11/09 9:23 pm >>>
I have seen different ways to address masking small vias (<13mils) under BGA.
cover them with mask prior to HASL top an bottom ( can't we need to ict probe
bottom)
cover top with mask prior to HASL (could cause trapped chemistry in via and
will not allow solder thru, we like the effect on thermal reliability for
environmental extremes)
leave the mask opening only slightly larger than via (tent)
do a post hasl mask to cover over via ( causes 2x the thickness of mask at
overlap, could be a problem with uBGA ball only 14mils dia to start with may
not touch pads)
We use #3 but have problems with rework leaving solder plugged vias that look
like shorts in xray.
If there are some other ideas or thoughts on how to design the via masking under
the BGAs I would like input. Thanks!
---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 04:04:44 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: New Product Introduction checklist
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hello,
I like to get your inputs on evaluating a customer design prior to
building a prototype (electronic assembly). This may include any DFM/DFT
analysis and also in-house capability analysis.
Specifically, what key features of the assembly do you consider in
analyzing the product for any manufacturing issue that may arise during
the build?
For example, just to name a few:
- Mixed technology -> affect process selection and flow
- type of devices on board (0402, BGA, washable comp., heat sensitive
comp)
- jigs & fixtures requirements
- board finish, size etc.
Also how would each of the features affect your decision and method to
build?
I am looking for a more comprehensive checklist or steps that one can go
through or follow in analyzing the product design prior to quoting and
prototyping. I would greatly appreciate any inputs on this rather large
topic. Later on I can provide a summary of all the feedbacks I receive
as well.
Rgds,
Peter Lee
Creation Technologies Inc.
_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com
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========================================================================Date: Mon, 12 Nov 2001 05:52:43 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: New Product Introduction checklist
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Peter,
Hope you REALLY like EXTENSIVE stuff. I think I sent this to you before
anyway.
Earl Moon
----- Original Message -----
From: "Peter Lee" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 4:04 AM
Subject: [TN] New Product Introduction checklist
> Hello,
>
> I like to get your inputs on evaluating a customer design prior to
> building a prototype (electronic assembly). This may include any DFM/DFT
> analysis and also in-house capability analysis.
>
> Specifically, what key features of the assembly do you consider in
> analyzing the product for any manufacturing issue that may arise during
> the build?
>
> For example, just to name a few:
> - Mixed technology -> affect process selection and flow
> - type of devices on board (0402, BGA, washable comp., heat sensitive
> comp)
> - jigs & fixtures requirements
> - board finish, size etc.
>
> Also how would each of the features affect your decision and method to
> build?
>
> I am looking for a more comprehensive checklist or steps that one can go
> through or follow in analyzing the product design prior to quoting and
> prototyping. I would greatly appreciate any inputs on this rather large
> topic. Later on I can provide a summary of all the feedbacks I receive
> as well.
>
>
> Rgds,
> Peter Lee
> Creation Technologies Inc.
>
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
> --------------------------------------------------------------------------
-------
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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========================================================================Date: Mon, 12 Nov 2001 07:09:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: New Product Introduction checklist
X-To: Peter Lee <[log in to unmask]>
Peter,
I just replied to your request via normal email without realizing the
response would be posted on the forum. Honestly didn't mean it and, though
we did this some time ago, don't want to go through the process of sending
out another thousand or so of these things. I sent your check list to your
private email address after getting of this site.
If anyone, who hasn't received my latest check list, wants one BE SURE TO
CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
Kindess regards,
Earl
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========================================================================Date: Mon, 12 Nov 2001 07:16:58 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tenison Stone <[log in to unmask]>
Subject: PCB Assembly demographics
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Good Monday morning to everyone,
I am looking for demographic information about PCB assembly.
I need information about dollars for PCB assembly - OEM and CEM.
I would also like breakdown information like small, medium, and large
businesses.
Does anyone know where I can find this information - prefer internet since
I am in a small town.
Thank you in advance for all your terrific help.
Tenison Stone
Telex Communications
Blue Earth, MN
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========================================================================Date: Mon, 12 Nov 2001 07:18:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: High Tg FR-4
Folks,
I may be fooling myself, but this subject is important. As I have reached
the maximum level of the Peter Principle, I really have nothing more to say
on the subject.
However, the following is a response to several off line responses to the
subject:
I agree with all your are saying. All I've been saying, throughout the long
IPC postings on this subject, is that selecting a high Tg material, for its
sake alone, is not the way to go. If needed, certainly use it, if one is
aware of its benefits or detractions. However, all other process
requirements must be met as well.
Certainly, as we have agreed before, Cu plating thickness, though getting
thinner, and ductility (not being assured, in my opinion, adequately with
respect to the former) must be ensured as well - especially in these ever
increasing higher aspect ratio holes. I know Ervin was trying to make this
point as several others said to me offline as well. Today's plating
chemistry and processes still have a way to go, so material alone is not
going to do it.
Also, I have said, Tg only assures more time before hole wall and associated
anomalies, or the reverse, develop. It may take 30% more time for polyimide
to come apart than an high Tg epoxy, but come apart it will over time. We've
all seen TMA and DSC evidence graphically (I will post one on Steve's site
if requested) showing this consistently as the temperature is applied over
time, as expansion takes place, before destruction at or about the rated Tg.
We all know this is because the PPM/C Z-axis expansion rate is about the
same for all materials using reinforced resin systems as epoxies, BT's, and
polyimides. Therefore, hole walls, and associated anomalies, coming apart
must be prevented at the design and process levels. Simply choosing a high
Tg material won't get the job done.
As for the solder floats, and very serious pre-conditioning requirements,
550 for 10 thermal stress, notwithstanding serious thermal shock testing, is
pretty severe even today. This is true though some manual soldering
processes see higher temps, times usually are much shorter. Most certainly
recognize that, even though a soldering iron's tip temperature may be as
high as 800 degrees, it isn't brought to bear on the solder termination
areas for anything approaching 10 seconds. Hardly anything survives these
temps for long durations. As you, and many others, have said before, you
must get on an off in a time consistent with effecting a quality solder
joint - unless you are seeking destruction.
Based on my personal email, and others, we would all appreciate your input,
like this, to be on the TechNet forum. I may be wrong, but it seems very
important stuff to a lot of people seeking this type input.
Also, I'm surprised not to see more of you folks, who have spent so much
time and effort developing all these incredible standards and specifications
(especially the 6010 series), attending this subject. They, unlike some
plated holes, just keep getting better. I, and others, must be missing
something, or it isn't that important after all.
Earl Moon
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========================================================================Date: Mon, 12 Nov 2001 13:49:56 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain
Hi All,
I notice that a few new references have been made to the above subject and
thought I would share some of my early work with you.
In my first post as a graduate, I researched the causes of dewetting on
circuit boards. I came across a solution, the make-up of which I have since
lost, which dissolved the tin lead alloy but left the two intermetallic
layers.
I produced a number of one inch square coupons which I soldered using 63/37
alloy, RMA flux and a Tri Moore Rotary Dip Tester.
These were divided into three categories:
1 Control
2 Remove tin lead and re test in the Rotary Dip.
3 Remove tin lead, Several hours steam ageing and re test.
Microsections showed that I had taken off the alloy successfully and left
the IMC.s.
All of the re tested coupons soldered successfully, including the steam aged
ones.
This was some years ago so I cannot remember the etchant nor the hours and
conditions in the steam ageing equipment. I do remember that the IMC
soldered very well so I am always dubious when somebody blames the
intermetallic for poor soldering.
I seem to be alone in my faith that the IMC solders but this was the result
of my very own work and I stand by it.
Regards
Eric Dawson, Defender of the IMC.
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========================================================================Date: Mon, 12 Nov 2001 09:35:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ian Hanna <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
hey, you could always fill a ionic tester with 95% IPA and 'test' each
board...
course they'd all fail first pass...but they'd be a heck of a lot cleaner...
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========================================================================Date: Mon, 12 Nov 2001 10:58:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: PCB Assembly demographics
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Tenison,
Won't have all your looking for, but you may check out American Electronics
Association. Check out their Research and Industry Listings for more
details. See http://www.aeanet.org
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Tenison Stone [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 8:17 AM
To: [log in to unmask]
Subject: [TN] PCB Assembly demographics
Good Monday morning to everyone,
I am looking for demographic information about PCB assembly.
I need information about dollars for PCB assembly - OEM and CEM.
I would also like breakdown information like small, medium, and large
businesses.
Does anyone know where I can find this information - prefer internet since
I am in a small town.
Thank you in advance for all your terrific help.
Tenison Stone
Telex Communications
Blue Earth, MN
----------------------------------------------------------------------------
-----
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----------------------------------------------------------------------------
-----
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========================================================================Date: Mon, 12 Nov 2001 10:07:37 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lynn Norman <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
OS-10, -20, and -30 are exempt from VOC regulations and are included as
acceptable replacements in SNAP.
We too are looking to get away from IPA, but as yet have not evaluated the
efficacy of VMS cleaners.
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
========================================================================Date: Mon, 12 Nov 2001 18:30:13 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Eric
Interesting, but I'm nor all that keen. Some bronzes, which are
essentially high in Cu/Sn intermetallics, are devils to solder.
Brian
Eric Dawson wrote:
>
> Hi All,
>
> I notice that a few new references have been made to the above subject and
> thought I would share some of my early work with you.
>
> In my first post as a graduate, I researched the causes of dewetting on
> circuit boards. I came across a solution, the make-up of which I have since
> lost, which dissolved the tin lead alloy but left the two intermetallic
> layers.
>
> I produced a number of one inch square coupons which I soldered using 63/37
> alloy, RMA flux and a Tri Moore Rotary Dip Tester.
>
> These were divided into three categories:
>
> 1 Control
> 2 Remove tin lead and re test in the Rotary Dip.
> 3 Remove tin lead, Several hours steam ageing and re test.
>
> Microsections showed that I had taken off the alloy successfully and left
> the IMC.s.
>
> All of the re tested coupons soldered successfully, including the steam aged
> ones.
>
> This was some years ago so I cannot remember the etchant nor the hours and
> conditions in the steam ageing equipment. I do remember that the IMC
> soldered very well so I am always dubious when somebody blames the
> intermetallic for poor soldering.
>
> I seem to be alone in my faith that the IMC solders but this was the result
> of my very own work and I stand by it.
>
> Regards
> Eric Dawson, Defender of the IMC.
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 18:39:38 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is
nolongerallowed for cleaning of electronics in California
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Lynn
The real problem is their flammability. However, in Europe, they ARE,
most definitely, classed as VOCs and they are unlikely to be politically
exempted.
Brian
Lynn Norman wrote:
>
> OS-10, -20, and -30 are exempt from VOC regulations and are included as
> acceptable replacements in SNAP.
>
> We too are looking to get away from IPA, but as yet have not evaluated the
> efficacy of VMS cleaners.
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 10:03:53 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Spacing between board to board that has mouse/rat bite design...
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
All,
My fab house is recommending 0.062" spacing between the boards on a
subpanel. I am using mouse-bite or rat-bite. As there are 5 boards per
subpanel, I would like to get opinion on the recommended spacing between
the boards and NOT between the board and throw away tabs. Here that
hangover needed to removed from both boards and if it's only 0.062" wide
then I believe it will be a bit little difficult to remove from the
second board once removed from the first board.
________________________
Board #1
________________________
this spacing
________________________
Board #2
________________________
and more....
Any suggestion will be highly appreciated.
Re,
Ken Patel
---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 10:43:40 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Tape splicing tool recommendations
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Can anyone give me some recommendations for sources of tape splicing
tools to add leader tape to reeled components? I'm sure there are
several around and I'd like to get opinions from current users.
Thanks in advance.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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========================================================================Date: Mon, 12 Nov 2001 13:56:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Re: Spacing between board to board that has mouse/rat bite
design...
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Can you put the mouse-bite breakaway on the edges of the boards next to the
throw-away tabs only instead of board to board? Would be easier than say,
having breakaway tabs on all four sides. 0.062" is common diameter for
single-pass routing operations (as well as 0.093" diameter). Also depends
on how the mouse-bite breakaway is designed (hole spacing. hole diameter,
holes in line with board edge, holes offset from centerline of board edge,
etc.
Rgds,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
Ken Patel
<[log in to unmask] To: [log in to unmask]
OM> cc:
Sent by: Subject: [TN] Spacing between board to board that has mouse/rat bite
TechNet design...
<[log in to unmask]
ORG>
11/12/01
01:03 PM
Please
respond to
"TechNet
E-Mail
Forum."
All,
My fab house is recommending 0.062" spacing between the boards on a
subpanel. I am using mouse-bite or rat-bite. As there are 5 boards per
subpanel, I would like to get opinion on the recommended spacing between
the boards and NOT between the board and throw away tabs. Here that
hangover needed to removed from both boards and if it's only 0.062" wide
then I believe it will be a bit little difficult to remove from the
second board once removed from the first board.
________________________
Board #1
________________________
this spacing
________________________
Board #2
________________________
and more....
Any suggestion will be highly appreciated.
Re,
Ken Patel
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 20:03:54 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: New Product Introduction checklist
MIME-Version: 1.0
Content-Type: text/plain; charset="Windows-1252"
Content-Transfer-Encoding: 7bit
Hi Technet,
With permission of Earl I just uploaded his very extensive DFM document to
my website, where you can download it directly.
If you like Earl's work, let him know, not me.
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 2:09 PM
Subject: Re: [TN] New Product Introduction checklist
> Peter,
>
> I just replied to your request via normal email without realizing the
> response would be posted on the forum. Honestly didn't mean it and, though
> we did this some time ago, don't want to go through the process of sending
> out another thousand or so of these things. I sent your check list to your
> private email address after getting of this site.
>
> If anyone, who hasn't received my latest check list, wants one BE SURE TO
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
>
> Kindess regards,
>
> Earl
>
> --------------------------------------------------------------------------
-------
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E-mail Archives
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> --------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 11:24:29 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Tape splicing tool recommendations
X-To: Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have a very low-tech solution to your frustration. (only for the Mylar
tape)
Save some tape from other reels, for creating your new leaders.
Looking at the tape, there is a "shiny" side and a "dull" side. Cut the
desired length of leader and mate the dull side of the new piece to the dull
side of the tape on the reel. Using any thermal bag sealer, you can
"connect" the two tapes. (You may need to play with the setting a bit but I
have found a setting in the lower mid-range works well with our sealers.)
Then trim the excess.
The resulting joint will withstand a higher load than the original material.
This has proven to reduce the set-up times for our EMS jobs.
Hope this helps,
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Rick Thompson [SMTP:[log in to unmask]]
Sent: Monday, November 12, 2001 10:44 AM
To: [log in to unmask]
Subject: [TN] Tape splicing tool recommendations
Can anyone give me some recommendations for sources of tape splicing
tools to add leader tape to reeled components? I'm sure there are several
around and I'd like to get opinions from current users.
Thanks in advance.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
<mailto:[log in to unmask]>
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========================================================================Date: Mon, 12 Nov 2001 14:33:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Golembiewski, Ray" <[log in to unmask]>
Subject: Formula?
MIME-Version: 1.0
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What is the formula that proves when I put my thumb on the end
of a garden house, the pressure increases and volume decreases. Is the
same formula used with air? Please help,
Ray Golembiewski C.I.D.
Manufacturing Test Engineer
Projects Unlimited, Inc.
(937) 918-2200
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========================================================================Date: Mon, 12 Nov 2001 15:04:17 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: To My E-Mail Address <[log in to unmask]>
Subject: Re: Formula?
Mime-Version: 1.0
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Bernoulei's equation. (I think I spelled the scientist's name wrong). It is ment for fluids. In clasical terms, air is fluid.
Rush
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========================================================================Date: Mon, 12 Nov 2001 12:16:53 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Formula?
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Ehhhh, I=E/R ??
When R goes up, I goes down and/or E goes up.
Have fun,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Golembiewski, Ray
Sent: Monday, November 12, 2001 11:34
To: [log in to unmask]
Subject: [TN] Formula?
What is the formula that proves when I put my thumb on the end
of a garden house, the pressure increases and volume decreases. Is the
same formula used with air? Please help,
Ray Golembiewski C.I.D.
Manufacturing Test Engineer
Projects Unlimited, Inc.
(937) 918-2200
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========================================================================Date: Mon, 12 Nov 2001 15:16:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: Formula?
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Bernoulei = Bernoulli
ment = meant
clasical = classical
there, think we got'em all ;)
Bill...
At 03:04 PM 11/12/2001 -0500, you wrote:
>Bernoulei's equation. (I think I spelled the scientist's name wrong). It
>is ment for fluids. In clasical terms, air is fluid.
>
>Rush
>
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========================================================================Date: Mon, 12 Nov 2001 13:33:50 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ryan Grant <[log in to unmask]>
Subject: Re: Formula?
Hi Ray,
The formula you are looking for is A1v1¢v2 where A is the cross-sectional
area and v is the speed.
BTW, your physical principles are slightly incorrect. Liquids don't expand
or compress. (with exception of extreme pressures and CTE expansion)
Bernoulli's equation is P+(1/2)pv^2+pgy=C, while fundamental to fluid
dynamics, I'm not sure it will help in this case.
Kind Regards
Ryan Grant
Advanced Technology Engineer
MCMS
(208) 898-1145
[log in to unmask]
> -----Original Message-----
> From: Golembiewski, Ray [SMTP:[log in to unmask]]
> Sent: Monday, November 12, 2001 12:34 PM
> To: [log in to unmask]
> Subject: [TN] Formula?
>
> What is the formula that proves when I put my thumb on the end
> of a garden house, the pressure increases and volume decreases. Is the
> same formula used with air? Please help,
>
> Ray Golembiewski C.I.D.
> Manufacturing Test Engineer
> Projects Unlimited, Inc.
> (937) 918-2200
>
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 15:45:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Telgen <[log in to unmask]>
Subject: Re: Formula?
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Ray, try http://www.lmnoeng.com/Flow/bernoulli.htm
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
Sent: Monday, November 12, 2001 14:34
To: [log in to unmask]
Subject: [TN] Formula?
What is the formula that proves when I put my thumb on the end
of a garden house, the pressure increases and volume decreases. Is the
same formula used with air? Please help,
Ray Golembiewski C.I.D.
Manufacturing Test Engineer
Projects Unlimited, Inc.
(937) 918-2200
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========================================================================Date: Mon, 12 Nov 2001 19:21:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crain, Bob" <[log in to unmask]>
Subject: Qualifying SMT Adhesives for Space
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
We will soon need to apply adhesives to hold parts to the bottom side of the
board during second reflow. Our products fly in space and have heavy duty
requirements for thermal cycling and vibration. Do any of you who do
aerospace SMT have favorite products for this purpose? We need an adhesive
that meets NASA outgassing requirements and has a friendly coefficient of
expansion?
I need someplace to start our search. Thanks.
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========================================================================Date: Mon, 12 Nov 2001 18:11:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Thanks. The OEM elected not to use OS-20 because of cost. IP alcohol costs
about $3/gal while OSB-20 is about $79/gal. Folks should send CA bill for
the increase in manufacturing cost.
----- Original Message -----
From: "Brian Ellis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 1:50 AM
Subject: Re: [TN] Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
> Hi!
>
> The law is an ass! Logically, they should stop the sale and consumption
> of all alcoholic liquor, as well. You could always try cleaning in
> whisky!
>
> Your best bet is to go water-soluble. Certainly, the OS-20 will be
> classed as a VOC. What this law, and other VOC ones, in Europe as well
> as in the USA, forget is that the effect of a VOC on the environment
> depends on many factors, not the least of which are emissions. An open
> bath of hot solvent is more emissive than a closed bath of a cold
> solution of the same solvent. Then, not all solvents are equal in their
> effect as an ozone smog precursor. The latter cannot be produced without
> NOxs, as well, so that emissions in the middle of LA are more likely to
> be serious than in the middle of the Mojave Desert (OK for the guys at
> China Lake!) and most hydrocarbon solvents have a very short atmospheric
> residence time, so that they are not going to roll down the hill into LA
> from there!
>
> As for the ionic contamination tester, the specs state quite clearly IPA
> and nothing else, but the quantity used is so small that you must be
> able to claim an essential use exemption. Anyway, testing is not
> cleaning and you specifically state "for electronic cleaning".
>
> Be comforted, no matter what you go for will be a better cleaner than
> IPA! It may remove the thick of the rosin residues, but it is decidedly
> not a good flux remover. If I were you, water-soluble is the answer.
>
> Brian
>
> > Bogert wrote:
> >
> > 11/11/2001
> >
> > Folks, the law makers in California are at it again. Per South Coast
> > Air Quality Management (SC AQMD) Rule 1171, the VOC solvent limits are
> > lowered, again, starting in January 2002. The amount of VOC in lb/gal
> > for electronic cleaning is 0.83 for electronic apparatus as well as
> > for repair cleaning. I believe IP alcohol is around 6.55 lb/gal.
> > Thus, IP alcohol is no longer allowed for electronic cleaning in
> > California as of 1/1/2002.
> >
> > I am checking with California to see if this also means that use of IP
> > in Ionic cleanliness testers is also dis-allowed. Seems to me that we
> > can consider these testers to be sccientific instruments which are
> > exempt from the Rule 1171 solvent requirements. This is what I am
> > proposing to the SC AQMD.
> >
> > Does anyone out there have any experience with use of Dow Corning OS-2
> > or OS-20 as a solvent to remove RMA flux in military applications?
> > The company claims the solvents are replacements for IP alcohol.
> > These solvents are Octamethyltrisiloxane based.
>
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 18:07:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longer allowe...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Thanks for info. The OEM decided not to use the OS-20 solvent because of
cost considerations. IP alcohol is about 3/gal vs OS-20 which is about
$79/gal.
----- Original Message -----
From: "<Rudy Sedlak>" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Sunday, November 11, 2001 11:38 PM
Subject: Re: [TN] Seeking info on replacement for IP Alcohol which is no
longer allowe...
> First....Suspect that an octyl Siloxane would be classified by SCAQMD (for
> non-Californians, this is Southern California Air Quality Management
> District) as a VOC..
>
> They do not understand that there is virtually any such thing as a
> NON-Volatile organic.
>
> However, they do understand about consumption and use, and if you can
> demonstrate that your IPA in your ionic tester does not consume
significant
> levels of IPA, they will probably let you off the hook.
>
> If you need help, I can assist you in "proving" this to the SCAQMD, I have
> done this for some of our products.
>
> I suspect that a lot of what you life about IPA for cleaning is that the
> residues evaporate, leaving nothing significant behind, and if this is a
key
> property, you may be in trouble, as you will definitely need a volatile
> organic to give you this property.
>
> Good luck.
>
> Rudy Sedlak
> RD Chemical Company (650-962-8004)
>
> --------------------------------------------------------------------------
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>
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========================================================================Date: Mon, 12 Nov 2001 18:20:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I believe southern CA will allow use of IPA in ionic cleanliness testers.
----- Original Message -----
From: "Ian Hanna" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 9:35 AM
Subject: Re: [TN] Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
> hey, you could always fill a ionic tester with 95% IPA and 'test' each
> board...
> course they'd all fail first pass...but they'd be a heck of a lot
cleaner...
>
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>
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========================================================================Date: Mon, 12 Nov 2001 18:22:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Our OEM decided not to use OS-20 because of cost. OS-20 cost about $79/gal.
IP alcohol is about $3/gal.
----- Original Message -----
From: "Lynn Norman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 11:07 AM
Subject: Re: [TN] Seeking info on replacement for IP Alcohol which is no
longerallowed for cleaning of electronics in California
> OS-10, -20, and -30 are exempt from VOC regulations and are included as
> acceptable replacements in SNAP.
>
> We too are looking to get away from IPA, but as yet have not evaluated the
> efficacy of VMS cleaners.
>
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 19:47:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Qualifying SMT Adhesives for Space
MIME-Version: 1.0
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Hi Bob!
Here's a couple of places to start:
http://www.imaps.org/adv_micro/2001jan_feb/3.html
http://www.aitechnology.com/enter.html
-Steve Gregory-
> We will soon need to apply adhesives to hold parts to the bottom side of the
> board during second reflow. Our products fly in space and have heavy duty
> requirements for thermal cycling and vibration. Do any of you who do
> aerospace SMT have favorite products for this purpose? We need an adhesive
> that meets NASA outgassing requirements and has a friendly coefficient of
> expansion?
>
> I need someplace to start our search. Thanks.
--part1_fb.1cbd042c.2921c78f_boundary
Content-Type: text/html; charset="US-ASCII"
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<FONT SIZE=2>Hi Bob!<BR>
<BR>
Here's a couple of places to start:<BR>
<BR>
http://www.imaps.org/adv_micro/2001jan_feb/3.html<BR>
<BR>
http://www.aitechnology.com/enter.html<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">We will soon need to apply adhesives to hold parts to the bottom side of the<BR>
board during second reflow. Our products fly in space and have heavy duty<BR>
requirements for thermal cycling and vibration. Do any of you who do<BR>
aerospace SMT have favorite products for this purpose? We need an adhesive<BR>
that meets NASA outgassing requirements and has a friendly coefficient of<BR>
expansion?<BR>
<BR>
I need someplace to start our search. Thanks.</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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========================================================================Date: Mon, 12 Nov 2001 17:09:27 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Qualifying SMT Adhesives for Space
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
try talking to tracon at tra-con.com.
phil
-----Original Message-----
From: Crain, Bob [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 4:21 PM
To: [log in to unmask]
Subject: [TN] Qualifying SMT Adhesives for Space
We will soon need to apply adhesives to hold parts to the bottom side of the
board during second reflow. Our products fly in space and have heavy duty
requirements for thermal cycling and vibration. Do any of you who do
aerospace SMT have favorite products for this purpose? We need an adhesive
that meets NASA outgassing requirements and has a friendly coefficient of
expansion?
I need someplace to start our search. Thanks.
---------------------------------------------------------------------------------
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========================================================================Date: Mon, 12 Nov 2001 20:23:44 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Tape splicing tool recommendations
MIME-Version: 1.0
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Suppliers are:
* Siemens Industrial Automation in Alpharetta, GA 770-740-3922 [p/n 2102987
($1.4k) tool & 100 splices] [p/n 2102988 ($550) box of splices]
* H.R. Scheidegger Holzweidweg 34, CH-4852, Rothrist, Switzerland
062-794-23-69 [HRS Tape Splicer 4]
* TopLine 714.898.3830 [HRS Tape Splicer 4 $899 plus $129 for each of two
cutting tools that have sprocket pins to make the butt cuts.] [Splices are
$295 per thousand]
* Steier Tesa 011 49 41214 730 / 800 4262181 [(SMD Double Splice Tape. A box
of 500 splices was DM 16.75 (less than $10 )]
We allow no splicing, because it is too difficult to control. For us, it is
too easy to splice a new reel to the wrong leader, as compared to monitoring
part use and preparing a replacement feeder, programming multiple feeder
locations, etc.
Dave Fish
----- Original Message -----
From: "Rick Thompson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 10:43 AM
Subject: [TN] Tape splicing tool recommendations
> Can anyone give me some recommendations for sources of tape splicing
> tools to add leader tape to reeled components? I'm sure there are
> several around and I'd like to get opinions from current users.
>
> Thanks in advance.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
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========================================================================Date: Tue, 13 Nov 2001 09:59:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Aspect Ratio
MIME-Version: 1.0
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I have been leaving through IPC-2221 on aspect ratio but did not have
any value on this information. Can some kind soul provide the answers to
my questions :
1. what is the current achievable/acceptable aspect ratio for plated
through hole?
2. Is there a different on the aspect ratio for PTH via? If yes, please
provide.
3. What is the aspect ratio for micro via of HDI Type 1 and Type II
board?
4. How about the aspect ratio for blind via on normal PTH board?
A big THANK YOU to all who will be responding!
Regards - Wee Mei
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========================================================================Date: Mon, 12 Nov 2001 22:54:51 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Aspect Ratio
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Aspect ratio is the relation between the hole diameter and the thickness of
the via/board.
A 10 mil hole in a 62 mil board is an aspect ratio of 6:1
Buried vias maybe 1:1 like 4 mil hole that is 4 mil deep, or even less like a
six mil hole that is only 4 mil deep.
Hope this helps
George Milad
Shipley company
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Aspect ratio is the relation between the hole diameter and the thickness of the via/board.
<BR>A 10 mil hole in a 62 mil board is an aspect ratio of 6:1
<BR>Buried vias maybe 1:1 like 4 mil hole that is 4 mil deep, or even less like a six mil hole that is only 4 mil deep.
<BR>Hope this helps
<BR>George Milad
<BR>Shipley company</FONT></HTML>
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========================================================================Date: Mon, 12 Nov 2001 19:53:46 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: Aspect Ratio
In-Reply-To: <[log in to unmask]>
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At 09:59 AM 11/13/2001 +0800, you wrote:
>I have been leaving through IPC-2221 on aspect ratio but did not have
>any value on this information. Can some kind soul provide the answers to
>my questions :
>
>1. what is the current achievable/acceptable aspect ratio for plated
>through hole?
Most domestic shops can easily do a 6:1 aspect ratio.
>2. Is there a different on the aspect ratio for PTH via? If yes, please
>provide.
No. Any plated through hole regardless of function. It's a matter of the
ratio of hole diameter vs laminate thickness. For example; a 12mil PTH in a
60mil laminate is a 5:1 aspect ration. (60/12) a 10 mil PTH in a 60mil
laminate is a 6:1 aspect ratio and so on.
>3. What is the aspect ratio for micro via of HDI Type 1 and Type II
>board?
Depends on the hole diameter and the thickness of the laminate you're drilling.
>4. How about the aspect ratio for blind via on normal PTH board?
See #3
>A big THANK YOU to all who will be responding!
>Regards - Wee Mei
>
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--=====================_11510735==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
<font size=3>At 09:59 AM 11/13/2001 +0800, you wrote:<br>
<blockquote type=cite class=cite cite>I have been leaving through
IPC-2221 on aspect ratio but did not have<br>
any value on this information. Can some kind soul provide the answers
to<br>
my questions :<br><br>
1. what is the current achievable/acceptable aspect ratio for
plated<br>
through hole?</font></blockquote><br>
<font color="#0000FF">Most domestic shops can easily do a 6:1 aspect
ratio.<br><br>
</font><blockquote type=cite class=cite cite><font size=3>2. Is there a
different on the aspect ratio for PTH via? If yes, please<br>
provide.</font></blockquote><br>
<font color="#0000FF">No. Any plated through hole regardless of function.
It's a matter of the ratio of hole diameter vs laminate thickness. For
example; a 12mil PTH in a 60mil laminate is a 5:1 aspect ration. (60/12)
a 10 mil PTH in a 60mil laminate is a 6:1 aspect ratio and so
on.<br><br>
</font><blockquote type=cite class=cite cite><font size=3>3. What is the
aspect ratio for micro via of HDI Type 1 and Type II<br>
board?</font></blockquote><br>
<font color="#0000FF">Depends on the hole diameter and the thickness of
the laminate you're drilling.<br><br>
</font><blockquote type=cite class=cite cite><font size=3>4. How about
the aspect ratio for blind via on normal PTH
board?</font></blockquote><br>
<font color="#0000FF">See #3<br><br>
<br>
</font><blockquote type=cite class=cite cite><font size=3>A big THANK YOU
to all who will be responding!<br>
Regards - Wee Mei<br><br>
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========================================================================Date: Mon, 12 Nov 2001 21:58:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Aspect Ratio
X-To: Lum Wee Mei <[log in to unmask]>
You've asked the big question of my day. Board shops differ both on rhetoric
and fact. It's been little different since I've been in the business dating
back somewhat. Always, there is a demand for more and less - as I need to
package more on real estate that must be smaller.
Surprisingly, most board shops are pretty honest about this question - in
terms of discussion/rhetoric. Maybe honest should be stated as innocent.
Fact, on the other hand, is a bit more hard to verify and/or validate.
Still, we move ever forward.
There's a lot going on here. As usual, we seem to be going down a road at
ever increasing speeds needing not a rush but a solution (chemical or
otherwise). It's a bit driving a modern vehicle down a not so modern roadway.
Everyone on every committee associated with all the great IPC guidelines,
standards, and specifications constantly work hard to find solutions
(chemical or otherwise) to this question. I can't help feeling they are a
bit overwhelmed by the issue. Most of us innocents are so.
This is what one seemingly important discussion is all about. Please provide
your findings along with evidence concerning plating chemistry, processes,
plating thickness throughout the hole, plating ductility, material Tg, and
anything else you find as verification the design meets original intent and
validation clearly showing the customer contract requirements are met.
We all await,
MoonMan
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========================================================================Date: Mon, 12 Nov 2001 23:18:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: POLYIMIDE TMA RESULTS
For those interested, Steve placed an image derived from one of my TMA
results concering polyimide. If you have any trouble determining results,
please contact me. Also be advised, polyimide can achieve the highest Tg, if
improperly cured in the press or out, but that only means it comes apart
(delaminates and beyond) over a longer time than, say, a BT/epoxy blend.
Simply, the graph shows the delta T from start to destruction/delamination.
As important, it shows the %elongation over time also indicated. 12%
elongation was determined as a function of PPM/C discussed over the course
of some other postings.
Certainly, this is significant as plating thickness and ductility is an
issue of vital concern. Consider very high plated hole aspect ratios and the
elongation findings during the TMA. Again, for a high aspect ratio hole, how
much can it stand before coming apart?
MoonMan
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========================================================================Date: Tue, 13 Nov 2001 08:17:01 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Diamond, Pat" <[log in to unmask]>
Subject: Solder temperature question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
/Dear all,
I'm looking for some advice on the threshold limits for solder temperatures,
if for example, HMP solder is solidus/liquidus at say 296-301 deg C, what is
the highest temperature excursion it can see in service before the
properties of the soldered connection are affected?
I heard somewhere that as a rule of thumb you should allow around 40 deg C
below the melting point of the solder being used.
Any help/advice that you can give would be appreciated.
regards,
Pat Diamond
Weston Aerospace
Farnborough
UK
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========================================================================Date: Tue, 13 Nov 2001 09:26:37 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Formula?
MIME-Version: 1.0
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I think you're all barking up the wrong tree.
Bernoulli's equations shows the conservation of kinetic energy in fluids
and is generally used to calculate things like areodynamic lift on an
aerofoil or the forces exerted on a pipe wall as the the contents flows
round a corner.
I think you're searching for P1v1/T1 = P2v2/T2. However v is not volume
but specific volume ie m^3/Kg.
Spend a minute on a reality check. If you put your thumb on the end of a
hose pipe does the pipe get smaller? If not, how can the volume of the
pipe decrease?
Hope this helps,
[log in to unmask] wrote:
>
> Ray, try http://www.lmnoeng.com/Flow/bernoulli.htm
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
> Sent: Monday, November 12, 2001 14:34
> To: [log in to unmask]
> Subject: [TN] Formula?
>
> What is the formula that proves when I put my thumb on the end
> of a garden house, the pressure increases and volume decreases. Is the
> same formula used with air? Please help,
>
> Ray Golembiewski C.I.D.
> Manufacturing Test Engineer
> Projects Unlimited, Inc.
> (937) 918-2200
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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========================================================================Date: Tue, 13 Nov 2001 06:57:44 -0500
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Subject: Unsubscribe
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Dept. N62V, Bldg. 966-2, Office 2J1309, Mail Drop 967A
Phone (802) 769-4775, t/l 446-4775, Fax (802) 769-4139
Pager (802) 878-5386 Pin #4685 - external, 74685 - internal
--=_alternative 0041CC8785256B03_Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif"><br>
<br>
Stephen Ayotte, IMD Manufacturing Quality Senior Engineer<br>
Dept. N62V, Bldg. 966-2, Office 2J1309, Mail Drop 967A<br>
<br>
Phone (802) 769-4775, t/l 446-4775, Fax (802) 769-4139<br>
Pager (802) 878-5386 Pin #4685 - external, 74685 - internal<br>
</font>
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========================================================================Date: Tue, 13 Nov 2001 06:11:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rummy Makmur <[log in to unmask]>
Subject: Re: Formula?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
To prove that, you need combination of mass balance and mechanical energy
balance (i.e. bernoulli equation).
mass balance: mass rate in = mass rate out. Assuming incompressible fluid
(same density in and out), since mass rate = volume rate * density, density
get canceled out and the result is volume rate in = volume rate out. It is
also known that volume rate = velocity * Area. From this you can prove that,
if area is decreased (such as, putting your thumb on the hose), velocity
will increase.
Then you will need bernouli equation. Simplified Bernoulli Equation:
(P1/density) + (Velocity1^2/2)+ (gh1) = (P2/density) + (velocity2 ^ 2/ 2) +
(gh2)
Assuming h (height) is the same, they get canceled out. Then, you will have
an equation with only P (Pressure) and V (velocity) as variables which you
can use to prove that if V2 increases, P2 decreases, provided P1 and V1 are
constant.
So, volume rate at location 2 is not dependent on Pressure at location 2,
provided same pressure and volume rate coming in. It "feels" like pressure
increasing, but rather it's velocity that is increasing or kinetic energy
increases.
Check out these sites
http://physics.bu.edu/py105/notes/Bernoulli.html
http://rabi.phys.virginia.edu/HTW/water_distribution.html
For the second question, you might not be able to use same exact equations
for air, since air might be considered as compressible. It may involve more
complicated equations.
Rummy Makmur
Process Engineer
Ibiden Circuits of America
-----Original Message-----
From: Eric Christison [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 3:27 AM
To: [log in to unmask]
Subject: Re: [TN] Formula?
I think you're all barking up the wrong tree.
Bernoulli's equations shows the conservation of kinetic energy in fluids
and is generally used to calculate things like areodynamic lift on an
aerofoil or the forces exerted on a pipe wall as the the contents flows
round a corner.
I think you're searching for P1v1/T1 = P2v2/T2. However v is not volume
but specific volume ie m^3/Kg.
Spend a minute on a reality check. If you put your thumb on the end of a
hose pipe does the pipe get smaller? If not, how can the volume of the
pipe decrease?
Hope this helps,
[log in to unmask] wrote:
>
> Ray, try http://www.lmnoeng.com/Flow/bernoulli.htm
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
> Sent: Monday, November 12, 2001 14:34
> To: [log in to unmask]
> Subject: [TN] Formula?
>
> What is the formula that proves when I put my thumb on the end
> of a garden house, the pressure increases and volume decreases. Is the
> same formula used with air? Please help,
>
> Ray Golembiewski C.I.D.
> Manufacturing Test Engineer
> Projects Unlimited, Inc.
> (937) 918-2200
>
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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========================================================================Date: Tue, 13 Nov 2001 14:48:34 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Formula?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Gentelmen,
All those,who are graduated in chemical engineering are kindly asked to open
their old tekstbooks on "Heat,Momentum and Mass Transfer" ( 3rd,4th and 5th
semester in faculties of chemical engineering).Basic books used to be
McCabe-Smith and W.W.W. ( Whelty + 2 other with W ) .At least those were my
books more than 30 years ago.
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Rummy Makmur [SMTP:[log in to unmask]]
> Sent: â ðåáîáø 13 2001 14:12
> To: [log in to unmask]
> Subject: Re: [TN] Formula?
>
> To prove that, you need combination of mass balance and mechanical energy
> balance (i.e. bernoulli equation).
>
> mass balance: mass rate in = mass rate out. Assuming incompressible fluid
> (same density in and out), since mass rate = volume rate * density,
> density
> get canceled out and the result is volume rate in = volume rate out. It is
> also known that volume rate = velocity * Area. From this you can prove
> that,
> if area is decreased (such as, putting your thumb on the hose), velocity
> will increase.
>
> Then you will need bernouli equation. Simplified Bernoulli Equation:
> (P1/density) + (Velocity1^2/2)+ (gh1) = (P2/density) + (velocity2 ^ 2/ 2)
> +
> (gh2)
>
> Assuming h (height) is the same, they get canceled out. Then, you will
> have
> an equation with only P (Pressure) and V (velocity) as variables which you
> can use to prove that if V2 increases, P2 decreases, provided P1 and V1
> are
> constant.
>
> So, volume rate at location 2 is not dependent on Pressure at location 2,
> provided same pressure and volume rate coming in. It "feels" like pressure
> increasing, but rather it's velocity that is increasing or kinetic energy
> increases.
>
> Check out these sites
> http://physics.bu.edu/py105/notes/Bernoulli.html
> http://rabi.phys.virginia.edu/HTW/water_distribution.html
>
> For the second question, you might not be able to use same exact equations
> for air, since air might be considered as compressible. It may involve
> more
> complicated equations.
>
> Rummy Makmur
> Process Engineer
> Ibiden Circuits of America
>
> -----Original Message-----
> From: Eric Christison [mailto:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 3:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] Formula?
>
>
> I think you're all barking up the wrong tree.
>
> Bernoulli's equations shows the conservation of kinetic energy in fluids
> and is generally used to calculate things like areodynamic lift on an
> aerofoil or the forces exerted on a pipe wall as the the contents flows
> round a corner.
>
> I think you're searching for P1v1/T1 = P2v2/T2. However v is not volume
> but specific volume ie m^3/Kg.
>
> Spend a minute on a reality check. If you put your thumb on the end of a
> hose pipe does the pipe get smaller? If not, how can the volume of the
> pipe decrease?
>
> Hope this helps,
>
>
>
> [log in to unmask] wrote:
> >
> > Ray, try http://www.lmnoeng.com/Flow/bernoulli.htm
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
> > Sent: Monday, November 12, 2001 14:34
> > To: [log in to unmask]
> > Subject: [TN] Formula?
> >
> > What is the formula that proves when I put my thumb on the end
> > of a garden house, the pressure increases and volume decreases. Is the
> > same formula used with air? Please help,
> >
> > Ray Golembiewski C.I.D.
> > Manufacturing Test Engineer
> > Projects Unlimited, Inc.
> > (937) 918-2200
> >
> --
> Eric Christison
> Mechanical Engineer
> STMicroelectronics
> 33 Pinkhill
> Edinburgh
> EH12 7BF
>
> Tel: (0)131 336 6165
> Fax: (0)131 336 6001
>
> --------------------------------------------------------------------------
> --
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
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> --------------------------------------------------------------------------
> --
> -----
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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========================================================================Date: Tue, 13 Nov 2001 07:57:43 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Qualifying SMT Adhesives for Space
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_145.47e4cbe.292272c7_boundary"
--part1_145.47e4cbe.292272c7_boundary
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Content-Transfer-Encoding: 7bit
There are choices for adhesives that will support the outgassing
requirements. Merco in NJ does a nice job. Personally I found the Uralane
to be the best fit for my application. The "pink" 7762 has ceramic spheres
of .004 to ensure passives are not flat on land. The "beige" 7760 is for
leaded and mechanical parts (no particles). They are both one part frozen
and very safe to use. Most importantly is they have heritage in Space
applications.
Coretec Brad
781 858 0783
--part1_145.47e4cbe.292272c7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>There are choices for adhesives that will support the outgassing requirements. Merco in NJ does a nice job. Personally I found the Uralane to be the best fit for my application. The "pink" 7762 has ceramic spheres of .004 to ensure passives are not flat on land. The "beige" 7760 is for leaded and mechanical parts (no particles). They are both one part frozen and very safe to use. Most importantly is they have heritage in Space applications.
<BR>
<BR>Coretec Brad
<BR>781 858 0783</FONT></HTML>
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========================================================================Date: Tue, 13 Nov 2001 08:36:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: Aspect Ratio
MIME-Version: 1.0
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Denis,
You will find achievable aspect ratios for rigid boards in Table 9-4,
IPC-2222, page 20.
This forum has already defined aspect ratio for you. However, I would like to
present a hint at finding things within the IPC-2221/2222. The IPC-2221
provides information that is generic to a number of board types from rigid to
descrete wire. For tables specific to a technology, you will have to refer to
the sectional standard for that technology. In your case you needed to look
in the IPC-2222 for Rigid Organic Boards. The committees attempted to
maintain topic paragraph numbers between both specifications. As an example,
section 9 in both specifications would have something on aspect ratio.
Regards,
Gary
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========================================================================Date: Tue, 13 Nov 2001 08:38:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: New Product Introduction checklist
MIME-Version: 1.0
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Thanks Daan.
Earl, any thought of updating this for ISO 9000-2000?
Phil Nutting
-----Original Message-----
From: D.Terstegge [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 2:04 PM
To: [log in to unmask]
Subject: Re: [TN] New Product Introduction checklist
Hi Technet,
With permission of Earl I just uploaded his very extensive DFM document
to
my website, where you can download it directly.
If you like Earl's work, let him know, not me.
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 2:09 PM
Subject: Re: [TN] New Product Introduction checklist
> Peter,
>
> I just replied to your request via normal email without realizing the
> response would be posted on the forum. Honestly didn't mean it and,
though
> we did this some time ago, don't want to go through the process of
sending
> out another thousand or so of these things. I sent your check list to
your
> private email address after getting of this site.
>
> If anyone, who hasn't received my latest check list, wants one BE SURE
TO
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
>
> Kindess regards,
>
> Earl
>
>
------------------------------------------------------------------------
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========================================================================Date: Tue, 13 Nov 2001 08:50:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Tape splicing tool recommendations
In-Reply-To: <001c01c16ba9$f26317b0$3d00a8c0@rick>
MIME-Version: 1.0
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we are currently using a rather handy splicing tool (tape splicer HRS 5)
from a company called PRACTICAL COMPONENTS,INC. Their web is
"www.practicalcomponents.com" with a phone of 714-899-8309 and fax of
714-899-8599.
Replacement tabs are p/n "hrs5.01) and come 100 to a bundle.
This is a handheld device with precut adhesive tabs for joining the
tapes together. You will need to save some leader and pocket material from
the ends of other reels, but the tabs seem pretty durable and it does not
take too long to splice them together. We use this quite a bit for
consigned reels of material being sent in when a customer cannot give up a
full reel, or for when we need to split a reel in order to run two jobs on
different lines when they share common parts.
Hope it helps. --Dean Lillibridge
NEWvENTURE TECHNOLOGIES CORPORATION
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Thompson
Sent: Monday, November 12, 2001 1:44 PM
To: [log in to unmask]
Subject: [TN] Tape splicing tool recommendations
Can anyone give me some recommendations for sources of tape splicing
tools to add leader tape to reeled components? I'm sure there are
several around and I'd like to get opinions from current users.
Thanks in advance.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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========================================================================Date: Tue, 13 Nov 2001 08:42:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Dan Cavaliere>" <[log in to unmask]>
Subject: Re: New Product Introduction checklist
MIME-Version: 1.0
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What's POD?
Phil Nutting <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
11/13/01 08:38 AM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: Re: [TN] New Product Introduction checklist
Thanks Daan.
Earl, any thought of updating this for ISO 9000-2000?
Phil Nutting
-----Original Message-----
From: D.Terstegge [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 2:04 PM
To: [log in to unmask]
Subject: Re: [TN] New Product Introduction checklist
Hi Technet,
With permission of Earl I just uploaded his very extensive DFM document
to
my website, where you can download it directly.
If you like Earl's work, let him know, not me.
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 2:09 PM
Subject: Re: [TN] New Product Introduction checklist
> Peter,
>
> I just replied to your request via normal email without realizing the
> response would be posted on the forum. Honestly didn't mean it and,
though
> we did this some time ago, don't want to go through the process of
sending
> out another thousand or so of these things. I sent your check list to
your
> private email address after getting of this site.
>
> If anyone, who hasn't received my latest check list, wants one BE SURE
TO
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
>
> Kindess regards,
>
> Earl
>
>
------------------------------------------------------------------------
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--=_alternative 004B06AC85256B03_Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">What's POD?</font>
<br>
<br>
<br>
<br>
<table width0%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>Phil Nutting <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">11/13/01 08:38 AM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: Re: [TN] New Product Introduction checklist</font></table>
<br>
<br><font size=2 face="Courier New">Thanks Daan.<br>
<br>
Earl, any thought of updating this for ISO 9000-2000?<br>
<br>
Phil Nutting<br>
<br>
-----Original Message-----<br>
From: D.Terstegge [mailto:[log in to unmask]]<br>
Sent: Monday, November 12, 2001 2:04 PM<br>
To: [log in to unmask]<br>
Subject: Re: [TN] New Product Introduction checklist<br>
<br>
<br>
Hi Technet,<br>
<br>
With permission of Earl I just uploaded his very extensive DFM document<br>
to<br>
my website, where you can download it directly.<br>
If you like Earl's work, let him know, not me.<br>
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc<br>
<br>
Best regards,<br>
<br>
Daan Terstegge<br>
http://www.smtinfo.net<br>
<br>
----- Original Message -----<br>
From: "Earl Moon" <[log in to unmask]><br>
To: <[log in to unmask]><br>
Sent: Monday, November 12, 2001 2:09 PM<br>
Subject: Re: [TN] New Product Introduction checklist<br>
<br>
<br>
> Peter,<br>
><br>
> I just replied to your request via normal email without realizing the<br>
> response would be posted on the forum. Honestly didn't mean it and,<br>
though<br>
> we did this some time ago, don't want to go through the process of<br>
sending<br>
> out another thousand or so of these things. I sent your check list to<br>
your<br>
> private email address after getting of this site.<br>
><br>
> If anyone, who hasn't received my latest check list, wants one BE SURE<br>
TO<br>
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.<br>
><br>
> Kindess regards,<br>
><br>
> Earl<br>
><br>
><br>
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========================================================================Date: Tue, 13 Nov 2001 15:03:15 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] New Product Introduction checklist
MIME-Version: 1.0
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Think it´s Proof Of Design, isn´t it Earl ß
Wolfgang
-----Ursprüngliche Nachricht-----
Von: <Dan Cavaliere> [mailto:[log in to unmask]]
Gesendet am: Dienstag, 13. November 2001 14:42
An: [log in to unmask]
Betreff: Re: [TN] New Product Introduction checklist
What's POD?
Phil Nutting <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
11/13/01 08:38 AM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: Re: [TN] New Product Introduction checklist
Thanks Daan.
Earl, any thought of updating this for ISO 9000-2000?
Phil Nutting
-----Original Message-----
From: D.Terstegge [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 2:04 PM
To: [log in to unmask]
Subject: Re: [TN] New Product Introduction checklist
Hi Technet,
With permission of Earl I just uploaded his very extensive DFM document
to
my website, where you can download it directly.
If you like Earl's work, let him know, not me.
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 2:09 PM
Subject: Re: [TN] New Product Introduction checklist
> Peter,
>
> I just replied to your request via normal email without realizing the
> response would be posted on the forum. Honestly didn't mean it and,
though
> we did this some time ago, don't want to go through the process of
sending
> out another thousand or so of these things. I sent your check list to
your
> private email address after getting of this site.
>
> If anyone, who hasn't received my latest check list, wants one BE SURE
TO
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
>
> Kindess regards,
>
> Earl
>
>
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Databases >
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700
ext.5315
>
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========================================================================Date: Tue, 13 Nov 2001 08:13:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: New Product Introduction checklist
X-To: Phil Nutting <[log in to unmask]>
Phil,
Thanks for observing this particular check-list partially is based upon ISO
9000/94 not 2000. I will be brutally honest with myself and you, as a
consultant on these (DFM/CE) and some other matters (MLB's, SMT, etc.), I
have been only about 40% successful helping implement anything resembling a
"real" DFM/CE program in any company professing to need it. I take
responsibility for my actions but am concerned about industry's reluctance
especially in times when making quality product and money is a function
relative to doing it right the first time. Some folks just don't get it.
Some never will. Others really embrace it.
Currently, I am working on the "new and improved" ISO requirements while
connecting DFM/CE to them. I would note that not long ago, it was professed,
by many ISO consultants (not me) the 94 requirements represented CPI. As
"bare bones" requirements, they certainly presented opportunities for this
and many realized it but in no way was the gap bridged using ISO alone. QS
9000 was born out of it, as ISO was born out of MIL-Q-9858A, and really took
things a step farther as evidenced by much higher quality American automobiles.
The new revision/version certainly does include and promote CPI. However, as
I usually work with people in reactionary modes (needing help to correct so
much wrong), I haven't gotten to the project, with anyone using or being
registered to the new ISO standard, though in depth though opportunities abound.
I am looking for more folks to embrace the opportunities both the new ISO
and DFM/CE requirements provide. I, as most, am certainly looking forward to
more CPI.
Earl
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========================================================================Date: Tue, 13 Nov 2001 08:24:49 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] New Product Introduction checklist
X-To: Wolfgang Busko <[log in to unmask]>
Thanks Wolfgang. Hope you are doing well.
Yes, POD means Proof Of Design. It is an ancient term having been used
extensively during midEVIL times during the last century. Most people in the
military and aerospace communities used the term as meaning design
verification, as in ISO, meeting design intent, and validation as meeting
customer contract requirements.
I, when consulting, use the term to describe what I do. Hell, It's who I am.
Not much interest in POD, as a term, but increasing in other words as we
seek higher quality, more reliable product. Though the term POD has not made
a significant come back, the term SOW has. It is a big part of POD. Everyone
knows what a SOW is.
MoonPODMan
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========================================================================Date: Tue, 13 Nov 2001 08:28:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Aspect Ratio
X-To: Gary Ferrari <[log in to unmask]>
Gary,
Thanks for the input and clarification. Can you point to how reliability
studies were done to assure how reliable these holes, in various aspects and
materials, are? Is round robin testing still being done? I'm way to old to
remember how testing was/is being done. Also, any more progress with DFM/CE
relative to using GD&T?
Regards,
Earl
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========================================================================Date: Tue, 13 Nov 2001 08:50:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: New Product Introduction checklist
Mime-Version: 1.0
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Thanks Daan for posting this document. As always Moonman you are the cats meow.
Kathy
>>> [log in to unmask] 11/12/01 01:03PM >>>
Hi Technet,
With permission of Earl I just uploaded his very extensive DFM document to
my website, where you can download it directly.
If you like Earl's work, let him know, not me.
The URL is http://www.smtinfo.net/docs/PODDFMCECL1.doc
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 12, 2001 2:09 PM
Subject: Re: [TN] New Product Introduction checklist
> Peter,
>
> I just replied to your request via normal email without realizing the
> response would be posted on the forum. Honestly didn't mean it and, though
> we did this some time ago, don't want to go through the process of sending
> out another thousand or so of these things. I sent your check list to your
> private email address after getting of this site.
>
> If anyone, who hasn't received my latest check list, wants one BE SURE TO
> CONTACT ME OFF LINE SO AS NOT TO CLOG THIS FORUM SITE AGAIN.
>
> Kindess regards,
>
> Earl
>
> --------------------------------------------------------------------------
-------
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========================================================================Date: Tue, 13 Nov 2001 15:58:15 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] AW: [TN] New Product Introduction checklist
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SOW, ... would think it means "Sign Of Weakness".
No, don´t know. Guess you want somebody to ask that question.
Doing fine, thanks, and hope you as well
Wolfgang
-----Ursprüngliche Nachricht-----
Von: Earl Moon [mailto:[log in to unmask]]
Gesendet am: Dienstag, 13. November 2001 15:25
An: [log in to unmask]
Betreff: Re: [TN] AW: [TN] New Product Introduction checklist
Thanks Wolfgang. Hope you are doing well.
Yes, POD means Proof Of Design. It is an ancient term having been used
extensively during midEVIL times during the last century. Most people in the
military and aerospace communities used the term as meaning design
verification, as in ISO, meeting design intent, and validation as meeting
customer contract requirements.
I, when consulting, use the term to describe what I do. Hell, It's who I am.
Not much interest in POD, as a term, but increasing in other words as we
seek higher quality, more reliable product. Though the term POD has not made
a significant come back, the term SOW has. It is a big part of POD. Everyone
knows what a SOW is.
MoonPODMan
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========================================================================Date: Tue, 13 Nov 2001 09:16:10 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: New Product Introduction checklist
X-To: Kathy Kuhlow <[log in to unmask]>
Glad you got it Kathy. The new version will be better and relate more
directly with specific parameters as dimensions, tolerances, placement
parameters, hole sizes, connectors, slots, edge distances, material
selections, impedance, edge rate and broad side differential pairs, plating,
plating thicknesses, solder coatings, etc.
However, I must ask, If I'm the cat's meow what does that make you? The
cat's what? This is an innocent question but will you be my future ex wife,
when available?
MoonMan
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========================================================================Date: Tue, 13 Nov 2001 09:19:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] AW: [TN] New Product Introduction checklist
X-To: Wolfgang Busko <[log in to unmask]>
Yes Wolfgang, in my case, sign of weakness applies. How else could I do this
stuff?
Think of it as SOB meaning what? No, it means statement of boredom.
Therefore, SOW has to mean statement of w--k.
MoonMan
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========================================================================Date: Tue, 13 Nov 2001 11:24:49 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Eric! Sorry but I humbly disagree. There is an abundance of published
industry data which shows that oxidized Sn/Cu intermetallic is one of the
more unsolderable surfaces encountered on an assembly. Problems with poor
plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
intermetallic at the hole rim to become oxidized) and thin HASL coatings
are just two examples of everyday industry solderability issues associated
with Sn/Cu IMCs. What type of flux did you use in your testing? Very
aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
fair majority of the industry is moving away from these types of flux
formulations. With all that being said, without the Sn/Cu IMC we would have
no solder joints so it is a critical part of a solder joint.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Intermetallic Layers
Hi All,
I notice that a few new references have been made to the above subject and
thought I would share some of my early work with you.
In my first post as a graduate, I researched the causes of dewetting on
circuit boards. I came across a solution, the make-up of which I have since
lost, which dissolved the tin lead alloy but left the two intermetallic
layers.
I produced a number of one inch square coupons which I soldered using 63/37
alloy, RMA flux and a Tri Moore Rotary Dip Tester.
These were divided into three categories:
1 Control
2 Remove tin lead and re test in the Rotary Dip.
3 Remove tin lead, Several hours steam ageing and re test.
Microsections showed that I had taken off the alloy successfully and left
the IMC.s.
All of the re tested coupons soldered successfully, including the steam
aged
ones.
This was some years ago so I cannot remember the etchant nor the hours and
conditions in the steam ageing equipment. I do remember that the IMC
soldered very well so I am always dubious when somebody blames the
intermetallic for poor soldering.
I seem to be alone in my faith that the IMC solders but this was the result
of my very own work and I stand by it.
Regards
Eric Dawson, Defender of the IMC.
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========================================================================Date: Tue, 13 Nov 2001 06:55:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: this is a test
MIME-Version: 1.0
Content-Type: text/plain
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========================================================================Date: Tue, 13 Nov 2001 17:25:54 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: PPM Monitoring and Benchmarking
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_01C0_01C16C68.3F97DC00"
This is a multi-part message in MIME format.
------=_NextPart_000_01C0_01C16C68.3F97DC00
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Based on the SMART Group On-Line survey on defect monitoring, to date the use of PPM Parts Per Million Monitoring is the most popular method which is well covered in the IPC document see www.smartgroup.org
I have asked the question before but would engineers like to have an average PPM level each month for screen print, component placement, reflow and wave soldering to compare with their own production results. It would have to be based on a known technology but could be valuable as a point of reference for benchmarking. Its a little project we are considering over the UK and would like to know its value to other engineers. I know there are many issues but as long as everyone know what the data is, where it comes in terms of board type NOT COMPANY and how its calculated I think it has a value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
------=_NextPart_000_01C0_01C16C68.3F97DC00
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>
<DIV><FONT face=Arial size=2>
<DIV><FONT face=Arial size=2>Based on the SMART Group On-Line survey on defect
monitoring, to date the use of PPM Parts Per Million Monitoring is the
most popular method which is well covered in the IPC document see <FONT
face=Arial size=2><A
href="http://www.smartgroup.org">www.smartgroup.org</A></FONT></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I have asked the question before but would
engineers like to have an average PPM level each month for screen print,
component placement, reflow and wave soldering to compare with their own
production results. It would have to be based on a known technology but could be
valuable as a point of reference for benchmarking. Its a little project we are
considering over the UK and would like to know its value to other engineers. I
know there are many issues but as long as everyone know what the data is, where
it comes in terms of board type NOT COMPANY and how its calculated I think it
has a value.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Please let me know your thoughts on the
subject.</FONT> </DIV>
<DIV> </DIV></FONT></DIV></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Bob Willis<BR>Electronic Presentation Services<BR>2
Fourth Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Single solution to your seminar, conference or
roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></FONT></DIV></BODY></HTML>
------=_NextPart_000_01C0_01C16C68.3F97DC00--
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========================================================================Date: Tue, 13 Nov 2001 13:07:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
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Dave,
Right on! That is our experience also. That's one reason Lucent has an
internal specification for surface finishes. This specification lists
exceptions to industrial specs like IPC. We are not comfortable with a
"minimum coverage" spec for SnPb HASL because we've had many experiences
where 50 microinches or less of solder has caused severe soldering
problems. The failure have almost always been linked to oxidized
copper-tin intermetallic. Boards with thin solder (i.e., exposed and
oxidized copper-tin intermetallic) have successfully been re-used by
re-hasling with agressive water-soluble-fusing fluids which removes the
oxide and allows fress SnPb to "stick" to the IMC.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Celiant Corporation
40 Technology Drive
Warren, New Jersey 07059
-----Original Message-----
From: David Hillman [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 12:25 PM
To: [log in to unmask]
Subject: Re: [TN] Intermetallic Layers
Hi Eric! Sorry but I humbly disagree. There is an abundance of published
industry data which shows that oxidized Sn/Cu intermetallic is one of
the
more unsolderable surfaces encountered on an assembly. Problems with
poor
plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
intermetallic at the hole rim to become oxidized) and thin HASL coatings
are just two examples of everyday industry solderability issues
associated
with Sn/Cu IMCs. What type of flux did you use in your testing? Very
aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
fair majority of the industry is moving away from these types of flux
formulations. With all that being said, without the Sn/Cu IMC we would
have
no solder joints so it is a critical part of a solder joint.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Intermetallic Layers
Hi All,
I notice that a few new references have been made to the above subject
and
thought I would share some of my early work with you.
In my first post as a graduate, I researched the causes of dewetting on
circuit boards. I came across a solution, the make-up of which I have
since
lost, which dissolved the tin lead alloy but left the two intermetallic
layers.
I produced a number of one inch square coupons which I soldered using
63/37
alloy, RMA flux and a Tri Moore Rotary Dip Tester.
These were divided into three categories:
1 Control
2 Remove tin lead and re test in the Rotary Dip.
3 Remove tin lead, Several hours steam ageing and re test.
Microsections showed that I had taken off the alloy successfully and
left
the IMC.s.
All of the re tested coupons soldered successfully, including the steam
aged
ones.
This was some years ago so I cannot remember the etchant nor the hours
and
conditions in the steam ageing equipment. I do remember that the IMC
soldered very well so I am always dubious when somebody blames the
intermetallic for poor soldering.
I seem to be alone in my faith that the IMC solders but this was the
result
of my very own work and I stand by it.
Regards
Eric Dawson, Defender of the IMC.
------------------------------------------------------------------------
---------
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>
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---------
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---------
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========================================================================Date: Tue, 13 Nov 2001 13:30:32 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Hinton <[log in to unmask]>
Subject: Re: Solder temperature question
MIME-Version: 1.0
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Pat
The melting temperature can be a very misleading indicator as to the
temperature at which the system should operate. The solder you mention HMP
is high temperature solder, but has limited resistance to changes due to
thermal aging above 180oC,
In this case the lead forms large crystals with weak grain boundaries and are
unsatisfactory for suface mount as the solder connections crack and fail when
in operation. The downhole (oil well drilling industry) industry used HMP
solder for years with through-hole mounting and crimped leads. However, when
surface mount was introduced in this industry, it was found that some of the
lead free solders had a lower melting temperature but much more durabilty
when operated at elevated temperatures. Other examples of where the HMP
(high lead) solders should not be used are under the hood in the automotive
industry and aircraft engine accessories.
The 40oC rule could get you into a lot of failures.
Phil Hinton
Phil Hinton
--part1_162.3d071d1.2922c0c8_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Pat
<BR>
<BR>The melting temperature can be a very misleading indicator as to the temperature at which the system should operate. The solder you mention HMP is high temperature solder, but has limited resistance to changes due to thermal aging above 180oC,
<BR>In this case the lead forms large crystals with weak grain boundaries and are unsatisfactory for suface mount as the solder connections crack and fail when in operation. The downhole (oil well drilling industry) industry used HMP solder for years with through-hole mounting and crimped leads. However, when surface mount was introduced in this industry, it was found that some of the lead free solders had a lower melting temperature but much more durabilty when operated at elevated temperatures. Other examples of where the HMP (high lead) solders should not be used are under the hood in the automotive industry and aircraft engine accessories.
<BR>The 40oC rule could get you into a lot of failures.
<BR>
<BR>Phil Hinton
<BR>
<BR>
<BR>
<BR>
<BR>Phil Hinton </FONT></HTML>
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========================================================================Date: Tue, 13 Nov 2001 18:30:31 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Adrian Irwin <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
This sounds like an excellent idea. I am particularly interested in PPM
bench marking for wavesoldering 0805 SMT. Would it be possible not only to
give the average but also a statistical representation of the PPM
distribution (Range, STDDev, min and Max).
Adrian Irwin
New Products Manager
Lambda UK
Bob Willis
<eps@BOBWILLI To: [log in to unmask]
S.CO.UK> cc:
Sent by: Subject: [TN] PPM Monitoring and Benchmarking
TechNet
<[log in to unmask]
ORG>
11/13/01
05:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which is
well covered in the IPC document see www.smartgroup.org
I have asked the question before but would engineers like to have an
average PPM level each month for screen print, component placement, reflow
and wave soldering to compare with their own production results. It would
have to be based on a known technology but could be valuable as a point of
reference for benchmarking. Its a little project we are considering over
the UK and would like to know its value to other engineers. I know there
are many issues but as long as everyone know what the data is, where it
comes in terms of board type NOT COMPANY and how its calculated I think it
has a value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
_____________________________________________________________________
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========================================================================Date: Tue, 13 Nov 2001 13:37:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Dan Cavaliere>" <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
MIME-Version: 1.0
Content-Type: multipart/alternative; boundary="=_alternative 0066159E85256B03_="
This is a multipart message in MIME format.
--=_alternative 0066159E85256B03_Content-Type: text/plain; charset="us-ascii"
I beleive that DPMO monitoring is the preferred method for defect
monitoring. IPC has two documents addressing this; IPC-7912 and IPC-926.
Dan Cavaliere
Baxter Healthcare Corp.
[log in to unmask]
Bob Willis <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
11/13/01 12:25 PM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: [TN] PPM Monitoring and Benchmarking
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which
is well covered in the IPC document see www.smartgroup.org
I have asked the question before but would engineers like to have an
average PPM level each month for screen print, component placement, reflow
and wave soldering to compare with their own production results. It would
have to be based on a known technology but could be valuable as a point of
reference for benchmarking. Its a little project we are considering over
the UK and would like to know its value to other engineers. I know there
are many issues but as long as everyone know what the data is, where it
comes in terms of board type NOT COMPANY and how its calculated I think it
has a value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
--=_alternative 0066159E85256B03_Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">I beleive that DPMO monitoring is the preferred method for defect monitoring. IPC has two documents addressing this; IPC-7912 and IPC-926.</font>
<br>
<br><font size=2 face="sans-serif">Dan Cavaliere</font>
<br><font size=2 face="sans-serif">Baxter Healthcare Corp.</font>
<br><font size=2 face="sans-serif">[log in to unmask]</font>
<br>
<br>
<br>
<br>
<table width0%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>Bob Willis <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">11/13/01 12:25 PM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: [TN] PPM Monitoring and Benchmarking</font></table>
<br>
<br><font size=2 face="Arial">Based on the SMART Group On-Line survey on defect monitoring, to date the use of PPM Parts Per Million Monitoring is the most popular method which is well covered in the IPC document see </font><a href=http://www.smartgroup.org/><font size=2 color=blue face="Arial"><u>www.smartgroup.org</u></font></a>
<br><font size=2 face="Arial"> </font>
<br><font size=2 face="Arial">I have asked the question before but would engineers like to have an average PPM level each month for screen print, component placement, reflow and wave soldering to compare with their own production results. It would have to be based on a known technology but could be valuable as a point of reference for benchmarking. Its a little project we are considering over the UK and would like to know its value to other engineers. I know there are many issues but as long as everyone know what the data is, where it comes in terms of board type NOT COMPANY and how its calculated I think it has a value.</font>
<br><font size=2 face="Arial"> </font>
<br><font size=2 face="Arial">Please let me know your thoughts on the subject. </font>
<br><font size=2 face="Arial"> </font>
<br><font size=3 face="Times New Roman"> </font>
<br><font size=2 face="Arial">Bob Willis<br>
Electronic Presentation Services<br>
2 Fourth Avenue<br>
Chelmsford Essex CM1 4HA<br>
England</font><font size=2 color=blue face="Arial"><u><br>
</u></font><a href=http://www.bobwillis.co.uk/><font size=2 color=blue face="Arial"><u>www.bobwillis.co.uk</u></font></a><font size=2 face="Arial"><br>
Tel: (44) 01245 351502 Fax: (44) 01245 496123</font>
<br><font size=3 face="Times New Roman"> </font>
<br><font size=2 face="Arial">Single solution to your seminar, conference or roadshow </font><a href="http://www.seminar-registrations.com/"><font size=2 color=blue face="Arial"><u>www.seminar-registrations.com</u></font></a>
<br>
<br>
--=_alternative 0066159E85256B03_=--
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========================================================================Date: Tue, 13 Nov 2001 11:18:37 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
so maybe eric found a way to keep the intermetallic from oxidizing.
phil
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 10:07 AM
To: [log in to unmask]
Subject: Re: [TN] Intermetallic Layers
Dave,
Right on! That is our experience also. That's one reason Lucent has an
internal specification for surface finishes. This specification lists
exceptions to industrial specs like IPC. We are not comfortable with a
"minimum coverage" spec for SnPb HASL because we've had many experiences
where 50 microinches or less of solder has caused severe soldering
problems. The failure have almost always been linked to oxidized
copper-tin intermetallic. Boards with thin solder (i.e., exposed and
oxidized copper-tin intermetallic) have successfully been re-used by
re-hasling with agressive water-soluble-fusing fluids which removes the
oxide and allows fress SnPb to "stick" to the IMC.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Celiant Corporation
40 Technology Drive
Warren, New Jersey 07059
-----Original Message-----
From: David Hillman [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 12:25 PM
To: [log in to unmask]
Subject: Re: [TN] Intermetallic Layers
Hi Eric! Sorry but I humbly disagree. There is an abundance of published
industry data which shows that oxidized Sn/Cu intermetallic is one of
the
more unsolderable surfaces encountered on an assembly. Problems with
poor
plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
intermetallic at the hole rim to become oxidized) and thin HASL coatings
are just two examples of everyday industry solderability issues
associated
with Sn/Cu IMCs. What type of flux did you use in your testing? Very
aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
fair majority of the industry is moving away from these types of flux
formulations. With all that being said, without the Sn/Cu IMC we would
have
no solder joints so it is a critical part of a solder joint.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Intermetallic Layers
Hi All,
I notice that a few new references have been made to the above subject
and
thought I would share some of my early work with you.
In my first post as a graduate, I researched the causes of dewetting on
circuit boards. I came across a solution, the make-up of which I have
since
lost, which dissolved the tin lead alloy but left the two intermetallic
layers.
I produced a number of one inch square coupons which I soldered using
63/37
alloy, RMA flux and a Tri Moore Rotary Dip Tester.
These were divided into three categories:
1 Control
2 Remove tin lead and re test in the Rotary Dip.
3 Remove tin lead, Several hours steam ageing and re test.
Microsections showed that I had taken off the alloy successfully and
left
the IMC.s.
All of the re tested coupons soldered successfully, including the steam
aged
ones.
This was some years ago so I cannot remember the etchant nor the hours
and
conditions in the steam ageing equipment. I do remember that the IMC
soldered very well so I am always dubious when somebody blames the
intermetallic for poor soldering.
I seem to be alone in my faith that the IMC solders but this was the
result
of my very own work and I stand by it.
Regards
Eric Dawson, Defender of the IMC.
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========================================================================Date: Tue, 13 Nov 2001 14:19:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Franck, George" <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
During my PWB education I learned that there are at least three "alloys" of
copper and tin that are formed as the Copper diffuses into the solder. The
first alloy formed (and I don't remember the ratios) has the highest tin to
copper ratio, and has surface activation energies within the range of most
fluxes. Therefore, this first tin copper alloy, or IMC, is solderable. All
the others alloys, with higher amounts of copper in them, are not.
Activation energies reflect how strongly attached the Oxygen atom are on the
surface of the metal. The more copper on the surface alloy, the tighter the
oxygen is attached, the stronger the flux needed to break the oxygen from
the surface.
While the copper is diffusing into the Solder, the Tin is also diffusing
into the copper surface, lowering the % tin in the solder alloy, which
raises the melt temperature of the remaining solder. It is all quite an
interesting solid state diffusion system. By the way, for all intents and
purposes, the lead is just too big (physical size of the atom) to
participate in this diffusion system much, except to get in the way.
It is possible that Eric only exposed the "solderable" tin-copper
intermetallic in his tests, i.e. the one with the least amount of copper in
it.
What was the magic chemical I played with in my old PWB shop to make boards
solderable, Thiourea hydrochloride? Wasn't that the active chemical in
Tarnex also?
George Franck, CID+
who recalls his "PWB as Black Magic" roots.
--------------------
Disclaimers:
1) If Dave Hillman says I am wrong, then I probably am.
2) My company will neither confirm nor deny the existence of any of my
opinions.
3) Tin-copper alloys are commonly referred to as Bronze.
-----Original Message-----
From: David Hillman [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 12:25 PM
To: [log in to unmask]
Subject: Re: [TN] Intermetallic Layers
Hi Eric! Sorry but I humbly disagree. There is an abundance of published
industry data which shows that oxidized Sn/Cu intermetallic is one of the
more unsolderable surfaces encountered on an assembly. Problems with poor
plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
intermetallic at the hole rim to become oxidized) and thin HASL coatings
are just two examples of everyday industry solderability issues associated
with Sn/Cu IMCs. What type of flux did you use in your testing? Very
aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
fair majority of the industry is moving away from these types of flux
formulations. With all that being said, without the Sn/Cu IMC we would have
no solder joints so it is a critical part of a solder joint.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Intermetallic Layers
Hi All,
I notice that a few new references have been made to the above subject and
thought I would share some of my early work with you.
In my first post as a graduate, I researched the causes of dewetting on
circuit boards. I came across a solution, the make-up of which I have since
lost, which dissolved the tin lead alloy but left the two intermetallic
layers.
I produced a number of one inch square coupons which I soldered using 63/37
alloy, RMA flux and a Tri Moore Rotary Dip Tester.
These were divided into three categories:
1 Control
2 Remove tin lead and re test in the Rotary Dip.
3 Remove tin lead, Several hours steam ageing and re test.
Microsections showed that I had taken off the alloy successfully and left
the IMC.s.
All of the re tested coupons soldered successfully, including the steam
aged
ones.
This was some years ago so I cannot remember the etchant nor the hours and
conditions in the steam ageing equipment. I do remember that the IMC
soldered very well so I am always dubious when somebody blames the
intermetallic for poor soldering.
I seem to be alone in my faith that the IMC solders but this was the result
of my very own work and I stand by it.
Regards
Eric Dawson, Defender of the IMC.
----------------------------------------------------------------------------
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========================================================================Date: Tue, 13 Nov 2001 12:40:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Formula?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Frankly, I'm a "Bird, Stewart and Lightfooot" man my myself.
> ----------
> From: Edward Szpruch[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Tuesday, November 13, 2001 4:48 AM
> To: [log in to unmask]
> Subject: Re: [TN] Formula?
>
> Gentelmen,
> All those,who are graduated in chemical engineering are kindly asked to
> open
> their old tekstbooks on "Heat,Momentum and Mass Transfer" ( 3rd,4th and
> 5th
> semester in faculties of chemical engineering).Basic books used to be
> McCabe-Smith and W.W.W. ( Whelty + 2 other with W ) .At least those were
> my
> books more than 30 years ago.
>
>
> Edward Szpruch
> Eltek Ltd
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>
> > -----Original Message-----
> > From: Rummy Makmur [SMTP:[log in to unmask]]
> > Sent: â ðåáîáø 13 2001 14:12
> > To: [log in to unmask]
> > Subject: Re: [TN] Formula?
> >
> > To prove that, you need combination of mass balance and mechanical
> energy
> > balance (i.e. bernoulli equation).
> >
> > mass balance: mass rate in = mass rate out. Assuming incompressible
> fluid
> > (same density in and out), since mass rate = volume rate * density,
> > density
> > get canceled out and the result is volume rate in = volume rate out. It
> is
> > also known that volume rate = velocity * Area. From this you can prove
> > that,
> > if area is decreased (such as, putting your thumb on the hose), velocity
> > will increase.
> >
> > Then you will need bernouli equation. Simplified Bernoulli Equation:
> > (P1/density) + (Velocity1^2/2)+ (gh1) = (P2/density) + (velocity2 ^ 2/
> 2)
> > +
> > (gh2)
> >
> > Assuming h (height) is the same, they get canceled out. Then, you will
> > have
> > an equation with only P (Pressure) and V (velocity) as variables which
> you
> > can use to prove that if V2 increases, P2 decreases, provided P1 and V1
> > are
> > constant.
> >
> > So, volume rate at location 2 is not dependent on Pressure at location
> 2,
> > provided same pressure and volume rate coming in. It "feels" like
> pressure
> > increasing, but rather it's velocity that is increasing or kinetic
> energy
> > increases.
> >
> > Check out these sites
> > http://physics.bu.edu/py105/notes/Bernoulli.html
> > http://rabi.phys.virginia.edu/HTW/water_distribution.html
> >
> > For the second question, you might not be able to use same exact
> equations
> > for air, since air might be considered as compressible. It may involve
> > more
> > complicated equations.
> >
> > Rummy Makmur
> > Process Engineer
> > Ibiden Circuits of America
> >
> > -----Original Message-----
> > From: Eric Christison [mailto:[log in to unmask]]
> > Sent: Tuesday, November 13, 2001 3:27 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Formula?
> >
> >
> > I think you're all barking up the wrong tree.
> >
> > Bernoulli's equations shows the conservation of kinetic energy in fluids
> > and is generally used to calculate things like areodynamic lift on an
> > aerofoil or the forces exerted on a pipe wall as the the contents flows
> > round a corner.
> >
> > I think you're searching for P1v1/T1 = P2v2/T2. However v is not volume
> > but specific volume ie m^3/Kg.
> >
> > Spend a minute on a reality check. If you put your thumb on the end of a
> > hose pipe does the pipe get smaller? If not, how can the volume of the
> > pipe decrease?
> >
> > Hope this helps,
> >
> >
> >
> > [log in to unmask] wrote:
> > >
> > > Ray, try http://www.lmnoeng.com/Flow/bernoulli.htm
> > >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
> > > Sent: Monday, November 12, 2001 14:34
> > > To: [log in to unmask]
> > > Subject: [TN] Formula?
> > >
> > > What is the formula that proves when I put my thumb on the end
> > > of a garden house, the pressure increases and volume decreases. Is the
> > > same formula used with air? Please help,
> > >
> > > Ray Golembiewski C.I.D.
> > > Manufacturing Test Engineer
> > > Projects Unlimited, Inc.
> > > (937) 918-2200
> > >
> > --
> > Eric Christison
> > Mechanical Engineer
> > STMicroelectronics
> > 33 Pinkhill
> > Edinburgh
> > EH12 7BF
> >
> > Tel: (0)131 336 6165
> > Fax: (0)131 336 6001
> >
> >
> --------------------------------------------------------------------------
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========================================================================Date: Tue, 13 Nov 2001 23:35:02 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Yehuda Weisz <[log in to unmask]>
Subject: Re: Aspect Ratio
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Hi,
To the best of my knowledge, the typical aspect ratio for laser drilled vias (for HDI) and it is always close to or less then1:1.
Typical micro-Via diameters for HDI are 0.004".
Best regards,
Yehuda Weisz
----- Original Message -----
From: Denis Lefebvre
To: [log in to unmask]
Sent: Tuesday, November 13, 2001 5:53 AM
Subject: Re: [TN] Aspect Ratio
At 09:59 AM 11/13/2001 +0800, you wrote:
I have been leaving through IPC-2221 on aspect ratio but did not have
any value on this information. Can some kind soul provide the answers to
my questions :
1. what is the current achievable/acceptable aspect ratio for plated
through hole?
Most domestic shops can easily do a 6:1 aspect ratio.
2. Is there a different on the aspect ratio for PTH via? If yes, please
provide.
No. Any plated through hole regardless of function. It's a matter of the ratio of hole diameter vs laminate thickness. For example; a 12mil PTH in a 60mil laminate is a 5:1 aspect ration. (60/12) a 10 mil PTH in a 60mil laminate is a 6:1 aspect ratio and so on.
3. What is the aspect ratio for micro via of HDI Type 1 and Type II
board?
Depends on the hole diameter and the thickness of the laminate you're drilling.
4. How about the aspect ratio for blind via on normal PTH board?
See #3
A big THANK YOU to all who will be responding!
Regards - Wee Mei
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<DIV><FONT face=Arial>Hi,</FONT></DIV>
<DIV><FONT face=Arial>To the best of my knowledge, the typical aspect ratio for
laser drilled vias (for HDI) and it is always close to or less
then1:1.</FONT></DIV>
<DIV><FONT face=Arial>Typical micro-Via diameters for HDI are
0.004".</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial>Best regards,</FONT></DIV>
<DIV><FONT face=Arial>Yehuda Weisz</FONT></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial"><FONT size=3>----- Original Message </FONT>-----
</DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
titleÞ[log in to unmask]>Denis Lefebvre</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 13, 2001 5:53
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] Aspect Ratio</DIV>
<DIV><BR></DIV><FONT size=3>At 09:59 AM 11/13/2001 +0800, you wrote:<BR>
<BLOCKQUOTE class=cite cite type="cite">I have been leaving through IPC-2221
on aspect ratio but did not have<BR>any value on this information. Can some
kind soul provide the answers to<BR>my questions :<BR><BR>1. what is the
current achievable/acceptable aspect ratio for plated<BR>through
hole?</FONT></BLOCKQUOTE><BR><FONT color=#0000ff>Most domestic shops can
easily do a 6:1 aspect ratio.<BR><BR></FONT>
<BLOCKQUOTE class=cite cite type="cite"><FONT size=3>2. Is there a different
on the aspect ratio for PTH via? If yes,
please<BR>provide.</FONT></BLOCKQUOTE><BR><FONT color=#0000ff>No. Any plated
through hole regardless of function. It's a matter of the ratio of hole
diameter vs laminate thickness. For example; a 12mil PTH in a 60mil laminate
is a 5:1 aspect ration. (60/12) a 10 mil PTH in a 60mil laminate is a 6:1
aspect ratio and so on.<BR><BR></FONT>
<BLOCKQUOTE class=cite cite type="cite"><FONT size=3>3. What is the aspect
ratio for micro via of HDI Type 1 and Type
II<BR>board?</FONT></BLOCKQUOTE><BR><FONT color=#0000ff>Depends on the hole
diameter and the thickness of the laminate you're drilling.<BR><BR></FONT>
<BLOCKQUOTE class=cite cite type="cite"><FONT size=3>4. How about the aspect
ratio for blind via on normal PTH board?</FONT></BLOCKQUOTE><BR><FONT
color=#0000ff>See #3<BR><BR><BR></FONT>
<BLOCKQUOTE class=cite cite type="cite"><FONT size=3>A big THANK YOU to all
who will be responding!<BR>Regards - Wee
Mei<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Tue, 13 Nov 2001 17:13:11 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Dave Hoover Where Are You?
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Would like to get hold of Dave Hoover, late of McCurdy Circuits, does anybody
know how I can do that?
Rudy Sedlak
RD Chemical Company
650-962-8004
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========================================================================Date: Tue, 13 Nov 2001 16:23:10 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barbara Burcham <[log in to unmask]>
Subject: Re: Dave Hoover Where Are You?
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I think that Dave is with Data Circuits since McCurdy went out of business.
Try:
Data Circuit Systems
Ph 1-800-800-3278
Fx 408-494-0171
email [log in to unmask]
Barbara Burcham
-----Original Message-----
From: <Rudy Sedlak> [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 4:13 PM
To: [log in to unmask]
Subject: [TN] Dave Hoover Where Are You?
Would like to get hold of Dave Hoover, late of McCurdy Circuits, does
anybody
know how I can do that?
Rudy Sedlak
RD Chemical Company
650-962-8004
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========================================================================Date: Tue, 13 Nov 2001 20:05:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Solder temperature question
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Hi Pat,
The properties of solder are all VERY temperature dependent--so "a rule of
thumb you should allow around 40 deg C below the melting point of the solder
being used" does not make any sense. Because the properties change
continuously with temperature, there can be no "threshold limits for solder
temperatures."
Whether or not you have a problem depends entiry on the design details--get
yourself a copy of IPC-D-279.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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========================================================================Date: Tue, 13 Nov 2001 19:37:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Ziarek <[log in to unmask]>
Subject: Out Of The Office
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I will be out of the office starting 11/11/2001 and will not return until
11/20/2001.
Paul Ziarek
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========================================================================Date: Tue, 13 Nov 2001 21:01:50 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Dave Hoover Where Are You?
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Rudy,
I work with Dave, you can e-mail me directly. [log in to unmask]
Kind Regards,
Steve
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Rudy,
<BR> I work with Dave, you can e-mail me directly. [log in to unmask]
<BR>
<BR>
<BR>
<BR>Kind Regards,
<BR> Steve</FONT></HTML>
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========================================================================Date: Wed, 14 Nov 2001 09:01:59 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Grant Emandien <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bob,
With you on this one, but do I presume that the defects measured would be
the criteria defined in IPC-610 and IPC-J-STD-001 for terminations and
placement and what about component defects? Screen print criteria? Class 1,2
or 3 to be stated with the DPMO figures? Sample vs 100%? Should we be
singing off the same hymn sheet?
Grant
-----Original Message-----
From: Bob Willis [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 7:26 PM
To: [log in to unmask]
Subject: [TN] PPM Monitoring and Benchmarking
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which is
well covered in the IPC document see www.smartgroup.org
<http://www.smartgroup.org>
I have asked the question before but would engineers like to have an average
PPM level each month for screen print, component placement, reflow and wave
soldering to compare with their own production results. It would have to be
based on a known technology but could be valuable as a point of reference
for benchmarking. Its a little project we are considering over the UK and
would like to know its value to other engineers. I know there are many
issues but as long as everyone know what the data is, where it comes in
terms of board type NOT COMPANY and how its calculated I think it has a
value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
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========================================================================Date: Tue, 13 Nov 2001 23:46:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Manual Press for PEM PCB fastener
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
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========================================================================Date: Wed, 14 Nov 2001 08:18:06 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Intermetallic Layers
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Hi Dave,
Whilst I realise that there is an abundance of published data I am not
convinced that any of it that I have seen has been the result of a properly
controlled experiment. It is usually subjective comment. If there is such a
published work I would be glad to see it and change my views accordingly.
However, as I said, I cannot dismiss my observations. The flux used was pure
rosin, no activators.
There is, obviously, some mechanism which causes poor soldering and
dewetting but currently, I am not convinced that it is the tin copper
intermetallic or its oxide. If it is, what is the difference between the
structures and properties of an oxidised IMC and the individual oxides of
tin and copper? Even mild flux will aid the soldering in the presence of the
latter two; that is its job.
The other mechanism that I investigated was the possibility that impurities
in the copper or the solder were rejected ahead of the advancing
intermetallic layer thus building a concentration which eventually caused
problems. I had access to Auger and SEM/EDAX but found nothing significant.
The fact remains that I soldered oxidised IMC very easily under ideal
conditions, so if it fails in other conditions then there is some
explanation that we are all missing.
Please don't get me wrong, I will not defend the IMC to the death, but I
need good, solid evidence which is better than mine.
My duty these days is the prosaic one of maintaining quality on a modern
surface mount line, one day I will take up where I left off and nail this
one.
Regards
Eric Dawson
> -----Original Message-----
> From: David Hillman [SMTP:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 5:25 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
> Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> industry data which shows that oxidized Sn/Cu intermetallic is one of the
> more unsolderable surfaces encountered on an assembly. Problems with poor
> plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> intermetallic at the hole rim to become oxidized) and thin HASL coatings
> are just two examples of everyday industry solderability issues associated
> with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> fair majority of the industry is moving away from these types of flux
> formulations. With all that being said, without the Sn/Cu IMC we would
> have
> no solder joints so it is a critical part of a solder joint.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] Intermetallic Layers
>
>
> Hi All,
>
> I notice that a few new references have been made to the above subject and
> thought I would share some of my early work with you.
>
> In my first post as a graduate, I researched the causes of dewetting on
> circuit boards. I came across a solution, the make-up of which I have
> since
> lost, which dissolved the tin lead alloy but left the two intermetallic
> layers.
>
> I produced a number of one inch square coupons which I soldered using
> 63/37
> alloy, RMA flux and a Tri Moore Rotary Dip Tester.
>
> These were divided into three categories:
>
> 1 Control
> 2 Remove tin lead and re test in the Rotary Dip.
> 3 Remove tin lead, Several hours steam ageing and re test.
>
> Microsections showed that I had taken off the alloy successfully and left
> the IMC.s.
>
> All of the re tested coupons soldered successfully, including the steam
> aged
> ones.
>
> This was some years ago so I cannot remember the etchant nor the hours and
> conditions in the steam ageing equipment. I do remember that the IMC
> soldered very well so I am always dubious when somebody blames the
> intermetallic for poor soldering.
>
> I seem to be alone in my faith that the IMC solders but this was the
> result
> of my very own work and I stand by it.
>
> Regards
> Eric Dawson, Defender of the IMC.
>
> --------------------------------------------------------------------------
> -------
>
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========================================================================Date: Wed, 14 Nov 2001 08:59:20 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi George,
One pertinent point here is that the intermetallic layers are compounds not
alloys. Thus their oxidising and other chemical reactions will probably be
different from those of their constituent metals.
The surface activation energies may be the key, can you give me references
please George? I would like to follow them up. (See my other reply!)
One point though, I would expect the copper rich compound to lie adjacent to
the copper interface and the copper deficient one next to the solder
interface. My microsections after solder etching showed that the normally
visible two layers were still present, so I must have been soldering the
copper deficient layer, which, as you say, is the easiest one to solder.
Also, since the melting points of these compounds are higher than soldering
temperatures we would always be soldering to the copper deficient layer. Or
are we? So, open question, can the copper deficient, aka easily solderable,
compound turn into a copper rich layer. Has anybody reading this discussion
got access to a well equipped laboratory?
Regards
Eric Dawson
> -----Original Message-----
> From: Franck, George [SMTP:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 7:20 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
> During my PWB education I learned that there are at least three "alloys"
> of
> copper and tin that are formed as the Copper diffuses into the solder.
> The
> first alloy formed (and I don't remember the ratios) has the highest tin
> to
> copper ratio, and has surface activation energies within the range of most
> fluxes. Therefore, this first tin copper alloy, or IMC, is solderable.
> All
> the others alloys, with higher amounts of copper in them, are not.
>
> Activation energies reflect how strongly attached the Oxygen atom are on
> the
> surface of the metal. The more copper on the surface alloy, the tighter
> the
> oxygen is attached, the stronger the flux needed to break the oxygen from
> the surface.
>
> While the copper is diffusing into the Solder, the Tin is also diffusing
> into the copper surface, lowering the % tin in the solder alloy, which
> raises the melt temperature of the remaining solder. It is all quite an
> interesting solid state diffusion system. By the way, for all intents and
> purposes, the lead is just too big (physical size of the atom) to
> participate in this diffusion system much, except to get in the way.
>
> It is possible that Eric only exposed the "solderable" tin-copper
> intermetallic in his tests, i.e. the one with the least amount of copper
> in
> it.
>
> What was the magic chemical I played with in my old PWB shop to make
> boards
> solderable, Thiourea hydrochloride? Wasn't that the active chemical in
> Tarnex also?
>
> George Franck, CID+
> who recalls his "PWB as Black Magic" roots.
>
> --------------------
> Disclaimers:
> 1) If Dave Hillman says I am wrong, then I probably am.
> 2) My company will neither confirm nor deny the existence of any of my
> opinions.
> 3) Tin-copper alloys are commonly referred to as Bronze.
>
> -----Original Message-----
> From: David Hillman [mailto:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 12:25 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
>
> Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> industry data which shows that oxidized Sn/Cu intermetallic is one of the
> more unsolderable surfaces encountered on an assembly. Problems with poor
> plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> intermetallic at the hole rim to become oxidized) and thin HASL coatings
> are just two examples of everyday industry solderability issues associated
> with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> fair majority of the industry is moving away from these types of flux
> formulations. With all that being said, without the Sn/Cu IMC we would
> have
> no solder joints so it is a critical part of a solder joint.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] Intermetallic Layers
>
>
> Hi All,
>
> I notice that a few new references have been made to the above subject and
> thought I would share some of my early work with you.
>
> In my first post as a graduate, I researched the causes of dewetting on
> circuit boards. I came across a solution, the make-up of which I have
> since
> lost, which dissolved the tin lead alloy but left the two intermetallic
> layers.
>
> I produced a number of one inch square coupons which I soldered using
> 63/37
> alloy, RMA flux and a Tri Moore Rotary Dip Tester.
>
> These were divided into three categories:
>
> 1 Control
> 2 Remove tin lead and re test in the Rotary Dip.
> 3 Remove tin lead, Several hours steam ageing and re test.
>
> Microsections showed that I had taken off the alloy successfully and left
> the IMC.s.
>
> All of the re tested coupons soldered successfully, including the steam
> aged
> ones.
>
> This was some years ago so I cannot remember the etchant nor the hours and
> conditions in the steam ageing equipment. I do remember that the IMC
> soldered very well so I am always dubious when somebody blames the
> intermetallic for poor soldering.
>
> I seem to be alone in my faith that the IMC solders but this was the
> result
> of my very own work and I stand by it.
>
> Regards
> Eric Dawson, Defender of the IMC.
>
> --------------------------------------------------------------------------
> --
> -----
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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> --
> -----
>
> --------------------------------------------------------------------------
> --
> -----
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> -----
>
> --------------------------------------------------------------------------
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========================================================================Date: Wed, 14 Nov 2001 10:47:40 +0100
Reply-To: Roland Jaquet <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roland Jaquet <[log in to unmask]>
Subject: Which standards do apply for civil aircrafts ?
MIME-Version: 1.0
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boundary="----=_NextPart_000_02A6_01C16CF9.C80DD210"
C'est un message de format MIME en plusieurs parties.
------=_NextPart_000_02A6_01C16CF9.C80DD210
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Dear Technetters,
I would like to know which standards have to be followed up for the Design, Manufacturing and Assembly of PWB that will be used into civil Aircrafts and aircraft engines ?
So far, I followed the lead with MIL-PFR-55110 F -> MIL-PRF-31032-X -> AS9100A -> IPC-6010 ..11 ...12 ...13
I could have a look to the MIL and have ordered the AS9100A.. had a look at IPC-6011 and IPC-6012, but couldn't have a look to IPC-6010.
I really need a statement of which standards do apply for Aircraft Engines or Aircraft flying equipment for approbation by the FAA
In advance, I would like to thank those of you who care to reply.
Very Best Regards
Roland
Http://www.PCBspecialist.com
Roland Jaquet - PCBspecialist - 14 ch. de Vers - CH-1228 Plan-Les-Ouates - Geneva - Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - Fax +41-22-880-0409 - Company Viability - Technical Viability - Technology Choice - Yield Improvement - Company Strategy - Equipment Choice - Company Acquisition
------=_NextPart_000_02A6_01C16CF9.C80DD210
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4807.2300" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>
<DIV><FONT face=Arial size=2>Dear Technetters,</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I would like to know which standards have to be
followed up for the Design, Manufacturing and Assembly of PWB that will be used
into civil Aircrafts and aircraft engines ?</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>So far, I followed the lead with MIL-PFR-55110 F
-> MIL-PRF-31032-X -> AS9100A -> IPC-6010 ..11 ...12 ...13</FONT></DIV>
<DIV><FONT face=Arial size=2>I could have a look to the MIL and have ordered the
AS9100A.. had a look at IPC-6011 and IPC-6012, but couldn't have a look to
IPC-6010.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I really need a statement of which standards do
apply for Aircraft Engines or Aircraft flying equipment for approbation by the
FAA</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>In advance, I would like to thank those of you who
care to reply.</FONT></DIV>
<DIV> </DIV></FONT></DIV>
<DIV><FONT face=Arial size=2>Very Best Regards</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Roland</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.PCBspecialist.com">Http://www.PCBspecialist.com</A><BR>Roland
Jaquet - PCBspecialist - 14 ch. de Vers - CH-1228 Plan-Les-Ouates - Geneva -
Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - Fax
+41-22-880-0409 - Company Viability - Technical Viability - Technology Choice -
Yield Improvement - Company Strategy - Equipment Choice - Company
Acquisition<BR></FONT></DIV></BODY></HTML>
------=_NextPart_000_02A6_01C16CF9.C80DD210--
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========================================================================Date: Wed, 14 Nov 2001 06:33:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: HELP <=> PCB vs. High Vacuum <=> HELP
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Hello Technetters,
There is very little concrete information concerning manufacturing of the
PCBs that are going to be mounted in high vacuum. I'm aware that the PCBs
got to be extremely clean. First of all there is the question of the
materials that are involved during the manufacturing process. Laminate that
printed board is build of, type of solder mask, type of finish, type of the
mounted parts and their properties, soldering paste, flux, residues,
cleaning chemicals, humidity et cetera.
There is need for a circular pad in the middle of the PCB that’s got to be
as plane as possible and has Ф25mm.
The designer has specified printed board with exposed copper alt. HASL
finish on the pads and the soldering mask should be founded only on one
side of the PCB. I believe that he want is to prevent or limit the
outgassing (Note that the whole PCB is going to be mounted in high vacuum).
I can't see why is better to have soldering mask only on one side. The
contamination degree is not that much different if there is the soldering
mask on the both sides. Aren't the laminates itself very porous and when
the soldering mask is on the PCB that you get less porosity? Thereby,
should a minimum degree of contamination after the cleaning process, be
obtained.
This is how I'm thinking.
Printed board should have ENIG finish on the pads to obtain as plain pads
as possible and prevent the oxidation and also soldering mask on both sides
of the PCB to limit porosity of the PCB. Then, before mounting the PCB in
to the vacuum, wash (Zestron) and dry/bake the PCB in, we say, 8-10 hours.
This is followed by, we say, 8-10 hours in the vacuum chamber outgassing as
much as possible and at the same time preventing the oxidation on exposed
solder.
My general opinion about cleaning is that easiest way to clean something is
if that "something" doesn't exist. On the printed board in this case,
oxidation, contamination in the laminate, residues et cetera.
If there is anything that is wrong in my way of solving this problem or if
you have any expirience with PCBs in High Vaccum, please write a comment on
this.
I would appreciate getting any kind of answer. :)
Thnx,
Sasha
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========================================================================Date: Wed, 14 Nov 2001 07:48:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Aspect Ratio
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Hi Earl,
Round robin testing was done--the details and results can be found in
IPC-TR-579 "Round Robin Reliability Evaluation of Small Diameter Plated
Through Holes in Printed Wiring Boards."
Werner Engelmaier
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========================================================================Date: Wed, 14 Nov 2001 06:55:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Aspect Ratio
X-To: Werner Engelmaier <[log in to unmask]>
Thanks Werner,
I just didn't know if this still was being done and didn't know where to
find the results.
Earl
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========================================================================Date: Wed, 14 Nov 2001 08:09:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
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Peter,
I bought a system that we use for swage standoffs that would just as
easily insert PEMs with the right die sets. Check out
http://www.cambridgeautomatic.com/. We use their AE2000 press. Very
nice unit that only needs air pressure to run. Cambridge Automatic has
a complete machine shop with excellent tool makers. They are located in
Natick Mass.
Regards,
Phil Nutting
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
_________________________________________________________
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========================================================================Date: Wed, 14 Nov 2001 08:18:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Peter,
Based on volume, a small bench mount pneumatic works fine. Also, the
assemblers prefer it over the arbor.
Things to watch out for:
1. Watch out for component clearance around the anvil and the pin setter.
2. Insure the insert is far enough back from the edge of the PCB to avoid a
stress concentration area.
3. Spec the hole tolerance accurately per the PEM callout.
Good Luck!
Kerry
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com
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========================================================================Date: Wed, 14 Nov 2001 07:35:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Owen <[log in to unmask]>
Subject: 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
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========================================================================Date: Wed, 14 Nov 2001 08:52:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Goldman, Patricia J." <[log in to unmask]>
Subject: Re: Aspect Ratio
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Note that this is a pretty old report. It was published in 1988, but the data for it was generated several years earlier. I do recall making parts and submitting for this round robin, I believe in the 1984 time frame.
Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]
-----Original Message-----
From: Werner Engelmaier [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 7:48 AM
To: [log in to unmask]
Subject: Re: [TN] Aspect Ratio
Hi Earl,
Round robin testing was done--the details and results can be found in
IPC-TR-579 "Round Robin Reliability Evaluation of Small Diameter Plated
Through Holes in Printed Wiring Boards."
Werner Engelmaier
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========================================================================Date: Wed, 14 Nov 2001 07:47:21 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Actuator Tabs falling off
Hi all
I'm hoping some of you have had this problem before and can pass on some
reasonable solutions.
We have several assemblies from the same customer which use a small 30 pin
SMT connector from Molex ( for flex cables) that have an actuator tab ( to
lock cable in place). This tab has a tendancy to fall off,the wash is the
worst area. But it will also fall off in other areas of the process as well.
We have run it through the wash in various directions with no success.
Taping the tab down is even worse since the wash will lift the tape causing
the tab to flip open then blow the tab off.
Any ideas??
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========================================================================Date: Wed, 14 Nov 2001 08:56:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: 0603 Components.
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hi Steve, we stencil print our adhesive onto our boards... works really
well on all our components including our 0603's. Our boards are approx 5"
x 13" in size, with over 600 components on the bottom side which we mount
with an adhesive...
At 07:35 AM 11/14/2001 -0600, you wrote:
>We are having some problems with 0603 components on adhesive, we are
>running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
>the consistency of the adhesive dot right.
>
>Many thanks
>Steve.
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========================================================================Date: Wed, 14 Nov 2001 07:55:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Independant Board Analysis
I am looking for someone who can do independant analysis of PCBs (RAW CARDS
AND COMPLETED UNITS).
Currently as an EMS we send any card issues back to the suppling board shop
to be analized ( for problems we can't easily find in-house such as inner
layer).
We would like to use an independant to do the destruct and non-destructive
testing.
Someone in Canada and preferably in Ontario would be best.
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========================================================================Date: Wed, 14 Nov 2001 07:57:43 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
X-To: Sasha Miladinovic <[log in to unmask]>
I like your statement "My general opinion about cleaning is that easiest way
to clean something is if that "something" doesn't exist. On the printed
board in this case,oxidation, contamination in the laminate, residues et
cetera."
We all know some type contamination will exist no matter the manufacturing
or cleaning process used. How it affects a "steril" high vacuum environment
is another matter. You have acceptance criteria during operation?
Using Steve Z's logic, I would start with the least "porous" material
possible then laminate it in a vacuum press, for dimensional, outgassing,
and other purposes. The choice of ENIG seems right. Solder mask or not, if
it is LPI it is epoxy approximating the laminate material and finished board
so, I think, go for whatever is needed.
Clean as required to meet specified requirements. Follow this with a good
high vacuum "soak" simulating the operational environment. Then, go for it.
MoonMan
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========================================================================Date: Wed, 14 Nov 2001 15:06:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Actuator Tabs falling off
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Andre: I guess those actuators don´t fall off when locked. One could try
using dummy flex pieces and having the beasts locked during assembly.
Depends on the amount of work pieces in progress how much you need.
You asked for ideas, this is mine, don´t know how much worth
Wolfgang
-----Ursprüngliche Nachricht-----
Von: Andre Leclair [mailto:[log in to unmask]]
Gesendet am: Mittwoch, 14. November 2001 14:47
An: [log in to unmask]
Betreff: [TN] Actuator Tabs falling off
Hi all
I'm hoping some of you have had this problem before and can pass on some
reasonable solutions.
We have several assemblies from the same customer which use a small 30 pin
SMT connector from Molex ( for flex cables) that have an actuator tab ( to
lock cable in place). This tab has a tendancy to fall off,the wash is the
worst area. But it will also fall off in other areas of the process as well.
We have run it through the wash in various directions with no success.
Taping the tab down is even worse since the wash will lift the tape causing
the tab to flip open then blow the tab off.
Any ideas??
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========================================================================Date: Wed, 14 Nov 2001 08:04:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: 0603 Components.
X-To: Stephen Owen <[log in to unmask]>
Consistency, meaning consistently good or bad, means what to you? I never
could glue anything together including my fingers with super type stuff, so
I was consistently bad.
Much has changed since I workd with gluing 0603's, I hope. Just 3 years ago,
we had trouble with glue CONSISTENTLY geting into solder joints causing
great concern. Is industry over that little problem/issue yet? Last year,
some folks were still having problems CONSISTENTLY using glue with these
devices without getting it in solder joints.
I've kept up a bit with more "modern" equipment and processes. I'm sure
everyone is doing 0402's just fine by now. Right?
MoonMan
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========================================================================Date: Wed, 14 Nov 2001 08:08:41 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Actuator Tabs falling off
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_3D67F9E6.4B2A470E"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_3D67F9E6.4B2A470E
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
I know of several companies who use a small basket with a fine enough mesh to keep parts like these together. Just make sure that the basket mesh isn't too closely woven or you may have an ionic issue.
Kathy
--=_3D67F9E6.4B2A470E
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I know of several companies who use a small basket with a fine enough mesh
to keep parts like these together. Just make sure that the basket mesh
isn't too closely woven or you may have an ionic issue. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_3D67F9E6.4B2A470E--
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========================================================================Date: Wed, 14 Nov 2001 08:08:24 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Aspect Ratio
X-To: Patty Goldman <[log in to unmask]>
Patricia,
I appreciate you input as well. I'm looking for a trail from the work all
you folks, like Werner, you, and probably hundreds of others did on this.
I'm hoping it leads to, how to put this without offending, how the "new"
standards and specifications say these things are reliable primarily based
on plating process management effectiveness and materials.
Thanks again,
Earl
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========================================================================Date: Wed, 14 Nov 2001 09:16:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
_________________________________________________________
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========================================================================Date: Wed, 14 Nov 2001 14:17:07 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bob,
This is something I have raised a few times on the Technet and something
which you have always replied to. I think benchmark PPM figures would be
invaluable in the industry as long as company names are not disclosed.
Yes, we all have 'special cases' which result in higher ppms but our aim
should be to eliminate the special cases by design changes or process
changes to overcome the problem.
If everyone could agree to start giving out data in an agreed format (based
on the draft IPC standard which I have forgotton the number for!) then maybe
we can start getting some useful data so we know how well we are doing.
Regards,
Neil Atkinson
-----Original Message-----
From: Bob Willis [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 7:26 PM
To: [log in to unmask]
Subject: [TN] PPM Monitoring and Benchmarking
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which is
well covered in the IPC document see www.smartgroup.org
<http://www.smartgroup.org>
I have asked the question before but would engineers like to have an average
PPM level each month for screen print, component placement, reflow and wave
soldering to compare with their own production results. It would have to be
based on a known technology but could be valuable as a point of reference
for benchmarking. Its a little project we are considering over the UK and
would like to know its value to other engineers. I know there are many
issues but as long as everyone know what the data is, where it comes in
terms of board type NOT COMPANY and how its calculated I think it has a
value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
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========================================================================Date: Wed, 14 Nov 2001 08:42:17 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Gleason <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
We have made many pem specific insertion machines using Schmidt. They have a
good number of extras you can pick and choose from and it's easy to make the
base and anvil for the pem nuts. So far our customers have loved them and
some have been in service for 2 years now. Schmidt can be outiftted with
rotating tables, 2 button safteys, light curtains, and indexers to name a
few options. We have been really happy with them.
Jim
----- Original Message -----
From: "Peter Lee" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 13, 2001 11:46 PM
Subject: [TN] Manual Press for PEM PCB fastener
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
>
> Rgds,
> Peter
>
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
> --------------------------------------------------------------------------
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> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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========================================================================Date: Wed, 14 Nov 2001 09:42:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Resistor Networks of 0.5 mm Pitch
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Hello to All,
we are planning to start using resistor networks of 0.5 mm pitch
in a normal reflow soldering process. The boards are FR-4 with HASL coating.
Is there any special concern about this component?
So far the smallest resistor network that we are using is a 0.8 mm pitch.
Within my company it is being recommended a stepped stencil for this
component. Is this necessary?
Thanks,
Alejandro Becerra
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<P><FONT SIZE=2 FACE="Arial">Hello to All,</FONT>
<BR><FONT SIZE=2 FACE="Arial">we are planning to start using resistor networks of 0.5 mm pitch</FONT>
<BR><FONT SIZE=2 FACE="Arial">in a normal reflow soldering process. The boards are FR-4 with HASL coating.</FONT>
<BR><FONT SIZE=2 FACE="Arial">Is there any special concern about this component?</FONT>
<BR><FONT SIZE=2 FACE="Arial">So far the smallest resistor network that we are using is a 0.8 mm pitch.</FONT>
<BR><FONT SIZE=2 FACE="Arial">Within my company it is being recommended a stepped stencil for this component. Is this necessary?</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Thanks,</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Alejandro Becerra</FONT>
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========================================================================Date: Wed, 14 Nov 2001 09:52:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Void in capacitor
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We have a failure due to a leakage in one ceramic chip capacitor.
External inspection did not show any obvious damage. Cross section showed a
void in the capacitor.
The void has a elliptical shape and it is longitudinal to the length of the
capacitor.
The photos have been posted in Steve's page http://stevezeva.homestead.com/
Is it possible to be a Thermal Shock Failure or it could be a pre-existent
void in the capacitor?
The part failed after 11 hours in life test.
Thanks,
Alejandro Becerra
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<P><FONT SIZE=2 FACE="Arial">We have a failure due to a leakage in one ceramic chip capacitor.</FONT>
<BR><FONT SIZE=2 FACE="Arial">External inspection did not show any obvious damage. Cross section showed a void in the capacitor.</FONT>
<BR><FONT SIZE=2 FACE="Arial">The void has a elliptical shape and it is longitudinal to the length of the capacitor.</FONT>
<BR><FONT SIZE=2 FACE="Arial">The photos have been posted in Steve's page <A HREF="http://stevezeva.homestead.com/" TARGET="_blank">http://stevezeva.homestead.com/</A></FONT>
<BR><FONT SIZE=2 FACE="Arial">Is it possible to be a Thermal Shock Failure or it could be a pre-existent void in the capacitor?</FONT>
<BR><FONT SIZE=2 FACE="Arial">The part failed after 11 hours in life test.</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Thanks,</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Alejandro Becerra</FONT>
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========================================================================Date: Wed, 14 Nov 2001 10:18:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul <[log in to unmask]>
Subject: Re: 0603 Components.
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I agree with Bill......printing is the way to go with these little buggers.
Paul Peltier
Sure Design
----- Original Message -----
From: Bill Raymond <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, November 14, 2001 8:56 AM
Subject: Re: [TN] 0603 Components.
> Hi Steve, we stencil print our adhesive onto our boards... works really
> well on all our components including our 0603's. Our boards are approx 5"
> x 13" in size, with over 600 components on the bottom side which we mount
> with an adhesive...
>
>
>
> At 07:35 AM 11/14/2001 -0600, you wrote:
> >We are having some problems with 0603 components on adhesive, we are
> >running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to
get
> >the consistency of the adhesive dot right.
> >
> >Many thanks
> >Steve.
>
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========================================================================Date: Wed, 14 Nov 2001 09:43:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: 0603 Components.
X-To: Paul Peltier <[log in to unmask]>
I know you folks using stencils are right. I just hoped, within the last
year (last time I did glue in a hybrid thick film house), the needle guys
had something better. Hate cleaning stencils.
Doesn't Asymtek or that Cookson company - what's it's name now (can't keep
up with all the changes here) have something that works on the little guys?
MoonMan
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========================================================================Date: Wed, 14 Nov 2001 07:55:29 -0800
Reply-To: Karl Sauter <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Karl Sauter <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
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Hope you are only concerned with double-sided boards here.
The lateral fracturing out along the glass fibers away from
NPTH PEM site can be surprisingly extensive. For multilayer
boards; better product design has PEM located in associated
metal fastener, with only the screw going through PCB Fab
(minimize potential for lateral stress).
Is product Class 1, 2, or 3 ?
- Karl Sauter
> MIME-Version: 1.0
> Date: Wed, 14 Nov 2001 08:18:19 -0500
> From: "McMullen, Kerry" <[log in to unmask]>
> Subject: Re: [TN] Manual Press for PEM PCB fastener
> To: [log in to unmask]
>
> Hi Peter,
> Based on volume, a small bench mount pneumatic works fine. Also, the
> assemblers prefer it over the arbor.
> Things to watch out for:
> 1. Watch out for component clearance around the anvil and the pin setter.
> 2. Insure the insert is far enough back from the edge of the PCB to avoid a
> stress concentration area.
> 3. Spec the hole tolerance accurately per the PEM callout.
>
> Good Luck!
> Kerry
>
>
> -----Original Message-----
> From: Peter Lee [mailto:[log in to unmask]]
> Sent: Wednesday, November 14, 2001 2:46 AM
> To: [log in to unmask]
> Subject: [TN] Manual Press for PEM PCB fastener
>
>
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
>
> Rgds,
> Peter
>
>
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========================================================================Date: Wed, 14 Nov 2001 11:04:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
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I have had boards in vaccum and gasketed so as the eterior of the board was
not in vaccum. The CTE in the negitive degree C (or K) commands respect. We
used gold finish, hard and or ENIG. Ensure the design is balanced
constructionand if your in the cold make sure you wear gloves. really.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I have had boards in vaccum and gasketed so as the eterior of the board was not in vaccum. The CTE in the negitive degree C (or K) commands respect. We used gold finish, hard and or ENIG. Ensure the design is balanced constructionand if your in the cold make sure you wear gloves. really.
<BR>
<BR>Brad</FONT></HTML>
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========================================================================Date: Wed, 14 Nov 2001 10:00:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: AOI AND STENCILS
Speaking of stencils, a couple years ago, I talked a company into assuring
Gerber data was made available to those stencil suppliers capable of
performing AOI inspection. Photo Stencil, in CO, I believe started using the
inspection method.
I raise this question because so many of the aperture and dimensional issues
should have been resolved before receiving the stencils where I was working.
Really got tired of using some supplier's product and having to tape up or
re-order new stencils whether a result of design or process issues - most
offen the former.
In fab shops, as everyone knows, AOI is a very important and logical tool to
inspect the results of the etch process, and all leading to it. As the same
basic technology uses Gerber or, more importantly, ODB++ data, it only seems
resonable everyone is now, or has been, jumping on the bandwagon.
Very curious,
MoonMan
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========================================================================Date: Wed, 14 Nov 2001 11:14:56 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Kovar
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have a question for the forum - how would one go about etching Kovar?
regards
Rich Fudalewski
FCT
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">have a question for the forum - how would one go about etching Kovar?
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>
<BR>FCT</FONT></HTML>
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========================================================================Date: Wed, 14 Nov 2001 10:32:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Kovar
X-To: [log in to unmask]
Ferric Chloride. Same as for CIC and CMC.
MoonMan
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========================================================================Date: Wed, 14 Nov 2001 08:35:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lush, Dorothy (FPTI)" <[log in to unmask]>
Subject: Re: 0603 Components.
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Why are you glueing? Can't you use a selective solderwave? Isn't exposing
0603's to molten solder going to affect their life span? How about using a
single dot?
Dorothy Lush
-----Original Message-----
From: Stephen Owen [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 5:36 AM
To: [log in to unmask]
Subject: [TN] 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
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<P><FONT SIZE=2>Why are you glueing? Can't you use a selective solderwave? Isn't exposing 0603's to molten solder going to affect their life span? How about using a single dot?</FONT></P>
<P><FONT SIZE=2>Dorothy Lush</FONT>
</P>
<P><FONT SIZE=2>-----Original Message-----</FONT>
<BR><FONT SIZE=2>From: Stephen Owen [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=2>Sent: Wednesday, November 14, 2001 5:36 AM</FONT>
<BR><FONT SIZE=2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=2>Subject: [TN] 0603 Components.</FONT>
</P>
<BR>
<P><FONT SIZE=2>We are having some problems with 0603 components on adhesive, we are</FONT>
<BR><FONT SIZE=2>running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get</FONT>
<BR><FONT SIZE=2>the consistency of the adhesive dot right.</FONT>
</P>
<P><FONT SIZE=2>Many thanks</FONT>
<BR><FONT SIZE=2>Steve.</FONT>
</P>
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========================================================================Date: Wed, 14 Nov 2001 11:01:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Gleason <[log in to unmask]>
Subject: Re: 0603 Components.
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RE: [TN] 0603 Components.Most of the 603 packages I've worked with went through the wave of if you had proper thermal profiles. But some people do prefer to reflow them and then cover them with a masking solder palllet. If your interested in the pallet give me a buzz offline.
Jim
GSC
972-494-1911
----- Original Message -----
From: Lush, Dorothy (FPTI)
To: [log in to unmask]
Sent: Wednesday, November 14, 2001 8:35 AM
Subject: Re: [TN] 0603 Components.
Why are you glueing? Can't you use a selective solderwave? Isn't exposing 0603's to molten solder going to affect their life span? How about using a single dot?
Dorothy Lush
-----Original Message-----
From: Stephen Owen [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 5:36 AM
To: [log in to unmask]
Subject: [TN] 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
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<DIV><FONT face=Arial size=2>Most of the 603 packages I've worked with went
through the wave of if you had proper thermal profiles. But some people do
prefer to reflow them and then cover them with a masking solder palllet. If your
interested in the pallet give me a buzz offline.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Jim</FONT></DIV>
<DIV><FONT face=Arial size=2>GSC</FONT></DIV>
<DIV><FONT face=Arial size=2>972-494-1911</FONT></DIV>
<BLOCKQUOTE dir=ltr
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask]
href="mailto:[log in to unmask]">Lush, Dorothy (FPTI)</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Wednesday, November 14, 2001 8:35
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] 0603 Components.</DIV>
<DIV><BR></DIV>
<P><FONT size=2>Why are you glueing? Can't you use a selective solderwave?
Isn't exposing 0603's to molten solder going to affect their life span? How
about using a single dot?</FONT></P>
<P><FONT size=2>Dorothy Lush</FONT> </P>
<P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From:
Stephen Owen [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Wednesday, November 14, 2001 5:36 AM</FONT> <BR><FONT
size=2>To: <A href="mailto:[log in to unmask]">[log in to unmask]</A></FONT>
<BR><FONT size=2>Subject: [TN] 0603 Components.</FONT> </P><BR>
<P><FONT size=2>We are having some problems with 0603 components on adhesive,
we are</FONT> <BR><FONT size=2>running Fugi CP6's. Using 0.3mm dual nozzles,
don't seem to be able to get</FONT> <BR><FONT size=2>the consistency of the
adhesive dot right.</FONT> </P>
<P><FONT size=2>Many thanks</FONT> <BR><FONT size=2>Steve.</FONT> </P>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Technet Mail List provided as a free service by IPC using
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========================================================================Date: Wed, 14 Nov 2001 12:06:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: 0603 Components.
In-Reply-To: <[log in to unmask]
itch.com>
Mime-Version: 1.0
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Dorothy, in our case, we have a big PGA thru-hole socket along with many
other thru-hole connectors that are not available in SMT format... along
with that, a VERY large percentage of the passive devices on the bottom
side of the board HAVE to be placed extremely close to the pins of the
thru-hole sockets and connectors I've mentioned...So, selective soldering
would be VERY challenging to attempt if not impossible - then there is the
problem of the products limited life span when a new replacement design
appears every 6 to 9 months! Besides, our wavesolder temperature of 232
degrees C and a contact time of less than 5 seconds is well within the
component manufacturers specifications. Yes, we use a single dot, stencil
printed.
At 08:35 AM 11/14/2001 -0800, you wrote:
>Why are you glueing? Can't you use a selective solderwave? Isn't exposing
>0603's to molten solder going to affect their life span? How about using a
>single dot?
>
>Dorothy Lush
>
>-----Original Message-----
>From: Stephen Owen
>[<mailto:[log in to unmask]>mailto:[log in to unmask]]
>Sent: Wednesday, November 14, 2001 5:36 AM
>To: [log in to unmask]
>Subject: [TN] 0603 Components.
>
>We are having some problems with 0603 components on adhesive, we are
>running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
>the consistency of the adhesive dot right.
>
>Many thanks
>Steve.
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========================================================================Date: Wed, 14 Nov 2001 12:13:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Creswick, Steven" <[log in to unmask]>
Subject: Re: Kovar
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Most any company that chemically mills (etches) copper, brass, stainless,
etc. for a living can etch Kovar
Steve Creswick - Gentex
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 11:15 AM
To: [log in to unmask]
Subject: [TN] Kovar
have a question for the forum - how would one go about etching Kovar?
regards
Rich Fudalewski
FCT
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<DIV><FONT color=#0000ff face=Arial size=2><SPAN class™7441217-14112001>Most
any company that chemically mills (etches) copper, brass, stainless, etc. for a
living can etch Kovar</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class™7441217-14112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class™7441217-14112001>Steve
Creswick - Gentex</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, November 14, 2001 11:15
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN]
Kovar<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT
face="Times New Roman" lang=0 size=3 FAMILY="SERIF">have a question for the
forum - how would one go about etching Kovar? <BR><BR>regards <BR><BR>Rich
Fudalewski <BR><BR>FCT</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 14 Nov 2001 12:20:07 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Kovar
MIME-Version: 1.0
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Steve
thanks for your input - but was looking for a little more substance in the
answer.
regards
Rich Fudalewski
FCT
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">Steve
<BR>
<BR>thanks for your input - but was looking for a little more substance in the answer.
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>
<BR>FCT</FONT></HTML>
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========================================================================Date: Wed, 14 Nov 2001 10:49:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Abrahamson <[log in to unmask]>
Subject: Re: 0603 Components.
Steve,
I am not sure what to make of your posting. Let me make some assumptions.
I assume when you say you are using Fugi CP6's, you might be talking about
the Fuji GL5 adhesive dispensors (the CP6 is a chipshooter). The inherent
problem with the Fuji dispensors is that they are "air over" machines. Most
of the modern dispensors went over to positive displacement machines 5 years
ago....Not Fuji.
If you are running selective solder, yet have passives that are still
exposed to the wave, then you cannot print adhesive. So let's focus on the
dispense process.
Your .3mm dual nozzle is the right choice- it is big enough to clean and
manage, and can put small enough dots down to work for the 0603 process.
Your dot size needs to be 1.5X to 2.5X- where X is your nozzle diameter. If
you are closer to 1.5X, your consistency will not be so great. I would
focus on a dot diameter of .6mm to ensure a stable dot (surface tension of
dot to board must be 2X of the dot to nozzle surface tension).
Air over machines are tough because volume is dependent on viscosity. A
valve opens for X amount of time and then shuts in an air over machine. If
you were putting down peanut butter on one valve and jelly in another, then
with the same dispense time, you would get twice as much jelly (thats how I
like my sandwich!!!).
The viscosity of adhesive will change will temperature, and to some extent
can be affected by the volume of adhesive in the syringe.
A positive displacement machine would put down the same volume of each. It
simply fills the chamber (usually a archimedes screw), and turns the auger X
degrees to displace/ or dispense an exact and repeatable amount...
For an air over machine, the more adhesive you put down, the lower the
variation between dots. The variation should only be about +/-10% of the
dot diameter, thus for a .6mm dot you should see .6mm +/-.06mm. If you are
seeing more than this you need to increase your dot size such that it is at
least 2X the inside diameter of the nozzle.
If that is too much adhesive, then move to a smaller nozzle.
If you are in a hot environment, the GL5 machine has a air conditioner
option (it is a stand alone unit). If you have some money to burn, check
out a positive displacement machine. I like the Camelot 2800 machine
because it is cheap (although very slow). Perhaps you could pick up a cheap
used Camelot Gemini machine if you need high speeds. I do not want to
discount Asymtek, Universal, GPD, Creative Automation, or any other
dispensor company whom surely create equally superb products, my experience
has just been with Fuji and Camelot.
Steve A
> -----Original Message-----
> From: Stephen Owen [SMTP:[log in to unmask]]
> Sent: Wednesday,November 14,2001 6:36 AM
> To: [log in to unmask]
> Subject: [TN] 0603 Components.
>
> We are having some problems with 0603 components on adhesive, we are
> running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
> the consistency of the adhesive dot right.
>
> Many thanks
> Steve.
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> --------------------------------------------------------------------------
> -------
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========================================================================Date: Wed, 14 Nov 2001 11:04:20 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Abrahamson <[log in to unmask]>
Subject: Re: Resistor Networks of 0.5 mm Pitch
Alejandro,
I noticed that you did not state the stencil thickness you are currently
using. I do not think you need to step the stencil, but should go with a
.125mm thick stencil. The stencil should have smooth walls (Laser cut and
electropolished). Just make sure you don't violate your area aspect ratio.
A .125mm stencil should apply adequate paste for most SMT components with
the exception of CCGA components- although you might need to tweak aperture
sizes on some components to ensure adequate solder volumes.
Step stencils, metal blades, and high density don't always work because of
the paste shadowing clearances that are necessary.
Steve A
> -----Original Message-----
> From: Becerra Alejandro [SMTP:[log in to unmask]]
> Sent: Wednesday,November 14,2001 7:42 AM
> To: [log in to unmask]
> Subject: [TN] Resistor Networks of 0.5 mm Pitch
>
> Hello to All,
> we are planning to start using resistor networks of 0.5 mm pitch
> in a normal reflow soldering process. The boards are FR-4 with HASL
> coating.
> Is there any special concern about this component?
> So far the smallest resistor network that we are using is a 0.8 mm pitch.
> Within my company it is being recommended a stepped stencil for this
> component. Is this necessary?
>
> Thanks,
>
> Alejandro Becerra
>
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========================================================================Date: Wed, 14 Nov 2001 17:55:46 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: 0603 Components.
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I feel sure you will get some comments from the machine guys but I did trials for a well known phone supplier for repeatability on adhesive dispense and the conclusion was we needed a different make of machine for dispensing.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Stephen Owen
To: [log in to unmask]
Sent: Wednesday, November 14, 2001 1:35 PM
Subject: [TN] 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
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<DIV><FONT face=Arial size=2>I feel sure you will get some comments from the
machine guys but I did trials for a well known phone supplier for repeatability
on adhesive dispense and the conclusion was we needed a different make of
machine for dispensing.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
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<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Stephen
Owen</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Wednesday, November 14, 2001 1:35
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] 0603 Components.</DIV>
<DIV><BR></DIV>We are having some problems with 0603 components on adhesive,
we are<BR>running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able
to get<BR>the consistency of the adhesive dot right.<BR><BR>Many
thanks<BR>Steve.<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Wed, 14 Nov 2001 13:27:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Re: 0603 Components (Torque Value)
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Talking about 0603 components attached with glue,
Is there any value for the torque strength of these components?
I have measured torque to these components (Glue is printed with stencil)
and I have observed torque values between 1 and 1.5 N-cm.
Alejandro Becerra
-----Original Message-----
From: Stephen Owen [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Wednesday, November 14, 2001 5:36 AM
To: [log in to unmask]
Subject: [TN] 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
----------------------------------------------------------------------------
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<TITLE>RE: [TN] 0603 Components.</TITLE>
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<BODY>
<P><SPAN class‡5391518-14112001><FONT face=Arial color=#0000ff size=2>Talking
about 0603 components attached with glue,</FONT></SPAN></P>
<P><SPAN class‡5391518-14112001><FONT face=Arial color=#0000ff size=2>Is there
any value for the torque strength of these components?</FONT></SPAN></P>
<P><SPAN class‡5391518-14112001><FONT face=Arial color=#0000ff size=2>I have
measured torque to these components (Glue is printed with stencil) and
I have observed torque values between 1 and 1.5 N-cm.</FONT></SPAN></P>
<P><SPAN class‡5391518-14112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </P>
<P><SPAN class‡5391518-14112001><FONT face=Arial color=#0000ff
size=2>Alejandro Becerra</FONT></SPAN></P>
<P><FONT size=2><SPAN class‡5391518-14112001> </SPAN>-----Original
Message-----</FONT> <BR><FONT size=2>From: Stephen Owen [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Wednesday, November 14, 2001 5:36 AM</FONT> <BR><FONT
size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject: [TN] 0603
Components.</FONT> </P><BR>
<P><FONT size=2>We are having some problems with 0603 components on adhesive, we
are</FONT> <BR><FONT size=2>running Fugi CP6's. Using 0.3mm dual nozzles, don't
seem to be able to get</FONT> <BR><FONT size=2>the consistency of the adhesive
dot right.</FONT> </P>
<P><FONT size=2>Many thanks</FONT> <BR><FONT size=2>Steve.</FONT> </P>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
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========================================================================Date: Wed, 14 Nov 2001 13:31:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Spacing between board to board that has mouse/rat bite d
esign...
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Hi Ken,
A plea from a former Lamination Engineer. Use any spacing you like but
leave some copper in the gap to avoid a low pressure area and wrinkles if
they use foil lam. The venting/theft pattern should be offset from one
layer to the next. This avoids creating high spots. The CAM guys & gals
used to kill me with huge gaps. Besides, all that etched off copper costs
them money - chemistry or energy.
Do they have their plating line under control? The plating thickness cross
the panel might vary significantly around the panel's edges
I'm befuddled. Aren't they routing the boards - why would one board be
harder to remove than another?
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Monday, November 12, 2001 1:04 PM
To: [log in to unmask]
Subject: [TN] Spacing between board to board that has mouse/rat bite
design...
All,
My fab house is recommending 0.062" spacing between the boards on a
subpanel. I am using mouse-bite or rat-bite. As there are 5 boards per
subpanel, I would like to get opinion on the recommended spacing between
the boards and NOT between the board and throw away tabs. Here that
hangover needed to removed from both boards and if it's only 0.062" wide
then I believe it will be a bit little difficult to remove from the
second board once removed from the first board.
________________________
Board #1
________________________
this spacing
________________________
Board #2
________________________
and more....
Any suggestion will be highly appreciated.
Re,
Ken Patel
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========================================================================Date: Wed, 14 Nov 2001 18:35:41 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
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Thank you very much for all the great responses its been a hobby horse of mine for years so I will circulate my proposed plan shortly for comment.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Atkinson, Neil
To: [log in to unmask]
Sent: Wednesday, November 14, 2001 2:17 PM
Subject: Re: [TN] PPM Monitoring and Benchmarking
Bob,
This is something I have raised a few times on the Technet and something
which you have always replied to. I think benchmark PPM figures would be
invaluable in the industry as long as company names are not disclosed.
Yes, we all have 'special cases' which result in higher ppms but our aim
should be to eliminate the special cases by design changes or process
changes to overcome the problem.
If everyone could agree to start giving out data in an agreed format (based
on the draft IPC standard which I have forgotton the number for!) then maybe
we can start getting some useful data so we know how well we are doing.
Regards,
Neil Atkinson
-----Original Message-----
From: Bob Willis [mailto:[log in to unmask]]
Sent: Tuesday, November 13, 2001 7:26 PM
To: [log in to unmask]
Subject: [TN] PPM Monitoring and Benchmarking
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which is
well covered in the IPC document see www.smartgroup.org
<http://www.smartgroup.org>
I have asked the question before but would engineers like to have an average
PPM level each month for screen print, component placement, reflow and wave
soldering to compare with their own production results. It would have to be
based on a known technology but could be valuable as a point of reference
for benchmarking. Its a little project we are considering over the UK and
would like to know its value to other engineers. I know there are many
issues but as long as everyone know what the data is, where it comes in
terms of board type NOT COMPANY and how its calculated I think it has a
value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
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<DIV><FONT face=Arial size=2>Thank you very much for all the great responses its
been a hobby horse of mine for years so I will circulate my proposed plan
shortly for comment.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>Atkinson, Neil</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Wednesday, November 14, 2001 2:17
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] PPM Monitoring and
Benchmarking</DIV>
<DIV><BR></DIV>Bob,<BR><BR>This is something I have raised a few times on the
Technet and something<BR>which you have always replied to. I think
benchmark PPM figures would be<BR>invaluable in the industry as long as
company names are not disclosed.<BR><BR>Yes, we all have 'special cases' which
result in higher ppms but our aim<BR>should be to eliminate the special cases
by design changes or process<BR>changes to overcome the problem.<BR><BR>If
everyone could agree to start giving out data in an agreed format (based<BR>on
the draft IPC standard which I have forgotton the number for!) then
maybe<BR>we can start getting some useful data so we know how well we are
doing.<BR><BR>Regards,<BR><BR>Neil Atkinson<BR><BR>-----Original
Message-----<BR>From: Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Sent:
Tuesday, November 13, 2001 7:26 PM<BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Subject: [TN] PPM
Monitoring and Benchmarking<BR><BR><BR><BR><BR>Based on the SMART Group
On-Line survey on defect monitoring, to date the<BR>use of PPM Parts Per
Million Monitoring is the most popular method which is<BR>well covered in the
IPC document see <A
href="http://www.smartgroup.org">www.smartgroup.org</A><BR><<A
href="http://www.smartgroup.org">http://www.smartgroup.org</A>><BR><BR>I
have asked the question before but would engineers like to have an
average<BR>PPM level each month for screen print, component placement, reflow
and wave<BR>soldering to compare with their own production results. It would
have to be<BR>based on a known technology but could be valuable as a point of
reference<BR>for benchmarking. Its a little project we are considering over
the UK and<BR>would like to know its value to other engineers. I know there
are many<BR>issues but as long as everyone know what the data is, where it
comes in<BR>terms of board type NOT COMPANY and how its calculated I think it
has a<BR>value.<BR><BR>Please let me know your thoughts on the
subject.<BR><BR><BR>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR><BR><BR>**********************************************************************<BR>Notice:<BR><BR>The
information contained in this e-mail (including any attachments)
may<BR>contain commercially sensitive or confidential information which may
be<BR>legally privileged and is for the sole use of the intended recipient(s).
If<BR>you are not, or believe you may not be, the intended recipient, you
are<BR>hereby notified that any use, dissemination, copying, review,
disclosure or<BR>action taken in reliance of this e-mail is prohibited and may
be unlawful.<BR>If you have received this message in error, please notify the
sender<BR>immediately by reply e-mail and delete all copies of the
message.<BR><BR>Any views expressed in this message are those of the
individual sender<BR>unless expressly stated by the sender to be given on
behalf of Tellumat<BR>(Pty) Ltd. Tellumat (Pty) Ltd disclaims liability for
any unauthorised<BR>opinion or representation made by the sender on behalf of
Tellumat (Pty)<BR>Ltd.<BR><BR>No warranty is given by Tellumat (Pty) Ltd that
the integrity or security of<BR>this e-mail (including any attachments) has
been maintained through<BR>transmission, nor that the communication is free of
virus, interception
or<BR>interference.<BR><BR>**********************************************************************<BR><BR>_____________________________________________________________________<BR>This
message has been checked for all known viruses by Star Internet<BR>delivered
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========================================================================Date: Wed, 14 Nov 2001 18:45:33 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Void in capacitor
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Void in capacitorI think you can safely say the void was there before but its unusual today.
It can be damage during sectioning but you would expect to see some other damage as well.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Becerra Alejandro
To: [log in to unmask]
Sent: Wednesday, November 14, 2001 2:52 PM
Subject: [TN] Void in capacitor
We have a failure due to a leakage in one ceramic chip capacitor.
External inspection did not show any obvious damage. Cross section showed a void in the capacitor.
The void has a elliptical shape and it is longitudinal to the length of the capacitor.
The photos have been posted in Steve's page http://stevezeva.homestead.com/
Is it possible to be a Thermal Shock Failure or it could be a pre-existent void in the capacitor?
The part failed after 11 hours in life test.
Thanks,
Alejandro Becerra
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<DIV><FONT face=Arial size=2>I think you can safely say the void was there
before but its unusual today.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>It can be damage during sectioning but you would
expect to see some other damage as well.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Becerra Alejandro</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Wednesday, November 14, 2001 2:52
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] Void in capacitor</DIV>
<DIV><BR></DIV>
<P><FONT face=Arial size=2>We have a failure due to a leakage in one ceramic
chip capacitor.</FONT> <BR><FONT face=Arial size=2>External inspection did not
show any obvious damage. Cross section showed a void in the capacitor.</FONT>
<BR><FONT face=Arial size=2>The void has a elliptical shape and it is
longitudinal to the length of the capacitor.</FONT> <BR><FONT face=Arial
size=2>The photos have been posted in Steve's page <A
href="http://stevezeva.homestead.com/"
target=_blank>http://stevezeva.homestead.com/</A></FONT> <BR><FONT face=Arial
size=2>Is it possible to be a Thermal Shock Failure or it could be a
pre-existent void in the capacitor?</FONT> <BR><FONT face=Arial size=2>The
part failed after 11 hours in life test.</FONT> </P>
<P><FONT face=Arial size=2>Thanks,</FONT> </P>
<P><FONT face=Arial size=2>Alejandro Becerra</FONT>
</P></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 14 Nov 2001 12:40:20 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ou Sokkhon-R5AALJ <[log in to unmask]>
Subject: Separation of DIN connector
MIME-Version: 1.0
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Can someone lead me to separation requirements (per DIN standard 41612) of DIN mating after drop test.
Motorola currently use DIN connectors on an assembly. A drop test showed the DIN connectors had minor separation. What is the requirement in inch or meter?
Sokkhon Ou
Product Engineering Group
MultiMedia Systems Division
Phone: 512-996-5211
E-Mail: [log in to unmask]
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========================================================================Date: Wed, 14 Nov 2001 14:05:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Stern <[log in to unmask]>
Subject: Re: Intermetallic Layers
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Eric:
I am also interested in a response to Eric's second to last question regarding the rate of tin
rich IMC converting to copper rich IMC.
To Dave and George: in addition to Eric's question, do you have info you can share regarding
the effect (mechanism) of lead in inhibiting the rate and/or thickness of tin/copper IMC
growth? George, your point on lead atomic radii inhibiting its migration caught my attention.
Are there other factors aside from size encumbrance that inhibit migration (ie. - mechanism
whereby nickel prevents/inhibits gold/copper migration)?
Thanks for the great discussion,
Ted Stern
Eric Dawson wrote:
> Hi George,
> One pertinent point here is that the intermetallic layers are compounds not
> alloys. Thus their oxidising and other chemical reactions will probably be
> different from those of their constituent metals.
> The surface activation energies may be the key, can you give me references
> please George? I would like to follow them up. (See my other reply!)
> One point though, I would expect the copper rich compound to lie adjacent to
> the copper interface and the copper deficient one next to the solder
> interface. My microsections after solder etching showed that the normally
> visible two layers were still present, so I must have been soldering the
> copper deficient layer, which, as you say, is the easiest one to solder.
> Also, since the melting points of these compounds are higher than soldering
> temperatures we would always be soldering to the copper deficient layer. Or
> are we? So, open question, can the copper deficient, aka easily solderable,
> compound turn into a copper rich layer. Has anybody reading this discussion
> got access to a well equipped laboratory?
> Regards
> Eric Dawson
> > -----Original Message-----
> > From: Franck, George [SMTP:[log in to unmask]]
> > Sent: Tuesday, November 13, 2001 7:20 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Intermetallic Layers
> >
> > During my PWB education I learned that there are at least three "alloys"
> > of
> > copper and tin that are formed as the Copper diffuses into the solder.
> > The
> > first alloy formed (and I don't remember the ratios) has the highest tin
> > to
> > copper ratio, and has surface activation energies within the range of most
> > fluxes. Therefore, this first tin copper alloy, or IMC, is solderable.
> > All
> > the others alloys, with higher amounts of copper in them, are not.
> >
> > Activation energies reflect how strongly attached the Oxygen atom are on
> > the
> > surface of the metal. The more copper on the surface alloy, the tighter
> > the
> > oxygen is attached, the stronger the flux needed to break the oxygen from
> > the surface.
> >
> > While the copper is diffusing into the Solder, the Tin is also diffusing
> > into the copper surface, lowering the % tin in the solder alloy, which
> > raises the melt temperature of the remaining solder. It is all quite an
> > interesting solid state diffusion system. By the way, for all intents and
> > purposes, the lead is just too big (physical size of the atom) to
> > participate in this diffusion system much, except to get in the way.
> >
> > It is possible that Eric only exposed the "solderable" tin-copper
> > intermetallic in his tests, i.e. the one with the least amount of copper
> > in
> > it.
> >
> > What was the magic chemical I played with in my old PWB shop to make
> > boards
> > solderable, Thiourea hydrochloride? Wasn't that the active chemical in
> > Tarnex also?
> >
> > George Franck, CID+
> > who recalls his "PWB as Black Magic" roots.
> >
> > --------------------
> > Disclaimers:
> > 1) If Dave Hillman says I am wrong, then I probably am.
> > 2) My company will neither confirm nor deny the existence of any of my
> > opinions.
> > 3) Tin-copper alloys are commonly referred to as Bronze.
> >
> > -----Original Message-----
> > From: David Hillman [mailto:[log in to unmask]]
> > Sent: Tuesday, November 13, 2001 12:25 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Intermetallic Layers
> >
> >
> > Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> > industry data which shows that oxidized Sn/Cu intermetallic is one of the
> > more unsolderable surfaces encountered on an assembly. Problems with poor
> > plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> > intermetallic at the hole rim to become oxidized) and thin HASL coatings
> > are just two examples of everyday industry solderability issues associated
> > with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> > aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> > fair majority of the industry is moving away from these types of flux
> > formulations. With all that being said, without the Sn/Cu IMC we would
> > have
> > no solder joints so it is a critical part of a solder joint.
> >
> > Dave Hillman
> > Rockwell Collins
> > [log in to unmask]
> >
> >
> >
> >
> > Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
> >
> > Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
> >
> > Sent by: TechNet <[log in to unmask]>
> >
> >
> > To: [log in to unmask]
> > cc:
> >
> > Subject: [TN] Intermetallic Layers
> >
> >
> > Hi All,
> >
> > I notice that a few new references have been made to the above subject and
> > thought I would share some of my early work with you.
> >
> > In my first post as a graduate, I researched the causes of dewetting on
> > circuit boards. I came across a solution, the make-up of which I have
> > since
> > lost, which dissolved the tin lead alloy but left the two intermetallic
> > layers.
> >
> > I produced a number of one inch square coupons which I soldered using
> > 63/37
> > alloy, RMA flux and a Tri Moore Rotary Dip Tester.
> >
> > These were divided into three categories:
> >
> > 1 Control
> > 2 Remove tin lead and re test in the Rotary Dip.
> > 3 Remove tin lead, Several hours steam ageing and re test.
> >
> > Microsections showed that I had taken off the alloy successfully and left
> > the IMC.s.
> >
> > All of the re tested coupons soldered successfully, including the steam
> > aged
> > ones.
> >
> > This was some years ago so I cannot remember the etchant nor the hours and
> > conditions in the steam ageing equipment. I do remember that the IMC
> > soldered very well so I am always dubious when somebody blames the
> > intermetallic for poor soldering.
> >
> > I seem to be alone in my faith that the IMC solders but this was the
> > result
> > of my very own work and I stand by it.
> >
> > Regards
> > Eric Dawson, Defender of the IMC.
> >
> > --------------------------------------------------------------------------
> > --
> > -----
> >
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text in
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> > To temporarily halt delivery of Technet send the following message: SET
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> > Search previous postings at: www.ipc.org > On-Line Resources & Databases >
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> > --------------------------------------------------------------------------
> > --
> > -----
> >
> > --------------------------------------------------------------------------
> > --
> > -----
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> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> > --------------------------------------------------------------------------
> > --
> > -----
> >
> > --------------------------------------------------------------------------
> > -------
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> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> > --------------------------------------------------------------------------
> > -------
>
> ---------------------------------------------------------------------------------
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========================================================================Date: Wed, 14 Nov 2001 15:32:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-Type: text/plain
Ted,
I'm way out of my area of expertise, but I would think the relative size of
all the atoms (Pb, Sn, Cu) would be one factor, but also the type of atomic
arrangement such as body center cubic, face center cubic, etc. would also
greatly effect migration. I would suggest that the greater the packing
density the more it would inhibit migration. I throw this out as a
supposition only. I would appreciate the input of anyone who could address
this more knowledgably.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Ted Stern [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 3:05 PM
To: [log in to unmask]
Subject: Re: [TN] Intermetallic Layers
Eric:
I am also interested in a response to Eric's second to last question
regarding the rate of tin
rich IMC converting to copper rich IMC.
To Dave and George: in addition to Eric's question, do you have info you
can share regarding
the effect (mechanism) of lead in inhibiting the rate and/or thickness of
tin/copper IMC
growth? George, your point on lead atomic radii inhibiting its migration
caught my attention.
Are there other factors aside from size encumbrance that inhibit migration
(ie. - mechanism
whereby nickel prevents/inhibits gold/copper migration)?
Thanks for the great discussion,
Ted Stern
Eric Dawson wrote:
> Hi George,
> One pertinent point here is that the intermetallic layers are compounds
not
> alloys. Thus their oxidising and other chemical reactions will probably be
> different from those of their constituent metals.
> The surface activation energies may be the key, can you give me references
> please George? I would like to follow them up. (See my other reply!)
> One point though, I would expect the copper rich compound to lie adjacent
to
> the copper interface and the copper deficient one next to the solder
> interface. My microsections after solder etching showed that the normally
> visible two layers were still present, so I must have been soldering the
> copper deficient layer, which, as you say, is the easiest one to solder.
> Also, since the melting points of these compounds are higher than
soldering
> temperatures we would always be soldering to the copper deficient layer.
Or
> are we? So, open question, can the copper deficient, aka easily
solderable,
> compound turn into a copper rich layer. Has anybody reading this
discussion
> got access to a well equipped laboratory?
> Regards
> Eric Dawson
> > -----Original Message-----
> > From: Franck, George [SMTP:[log in to unmask]]
> > Sent: Tuesday, November 13, 2001 7:20 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Intermetallic Layers
> >
> > During my PWB education I learned that there are at least three "alloys"
> > of
> > copper and tin that are formed as the Copper diffuses into the solder.
> > The
> > first alloy formed (and I don't remember the ratios) has the highest tin
> > to
> > copper ratio, and has surface activation energies within the range of
most
> > fluxes. Therefore, this first tin copper alloy, or IMC, is solderable.
> > All
> > the others alloys, with higher amounts of copper in them, are not.
> >
> > Activation energies reflect how strongly attached the Oxygen atom are on
> > the
> > surface of the metal. The more copper on the surface alloy, the tighter
> > the
> > oxygen is attached, the stronger the flux needed to break the oxygen
from
> > the surface.
> >
> > While the copper is diffusing into the Solder, the Tin is also diffusing
> > into the copper surface, lowering the % tin in the solder alloy, which
> > raises the melt temperature of the remaining solder. It is all quite an
> > interesting solid state diffusion system. By the way, for all intents
and
> > purposes, the lead is just too big (physical size of the atom) to
> > participate in this diffusion system much, except to get in the way.
> >
> > It is possible that Eric only exposed the "solderable" tin-copper
> > intermetallic in his tests, i.e. the one with the least amount of copper
> > in
> > it.
> >
> > What was the magic chemical I played with in my old PWB shop to make
> > boards
> > solderable, Thiourea hydrochloride? Wasn't that the active chemical in
> > Tarnex also?
> >
> > George Franck, CID+
> > who recalls his "PWB as Black Magic" roots.
> >
> > --------------------
> > Disclaimers:
> > 1) If Dave Hillman says I am wrong, then I probably am.
> > 2) My company will neither confirm nor deny the existence of any of my
> > opinions.
> > 3) Tin-copper alloys are commonly referred to as Bronze.
> >
> > -----Original Message-----
> > From: David Hillman [mailto:[log in to unmask]]
> > Sent: Tuesday, November 13, 2001 12:25 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] Intermetallic Layers
> >
> >
> > Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> > industry data which shows that oxidized Sn/Cu intermetallic is one of
the
> > more unsolderable surfaces encountered on an assembly. Problems with
poor
> > plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> > intermetallic at the hole rim to become oxidized) and thin HASL coatings
> > are just two examples of everyday industry solderability issues
associated
> > with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> > aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> > fair majority of the industry is moving away from these types of flux
> > formulations. With all that being said, without the Sn/Cu IMC we would
> > have
> > no solder joints so it is a critical part of a solder joint.
> >
> > Dave Hillman
> > Rockwell Collins
> > [log in to unmask]
> >
> >
> >
> >
> > Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
> >
> > Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
> >
> > Sent by: TechNet <[log in to unmask]>
> >
> >
> > To: [log in to unmask]
> > cc:
> >
> > Subject: [TN] Intermetallic Layers
> >
> >
> > Hi All,
> >
> > I notice that a few new references have been made to the above subject
and
> > thought I would share some of my early work with you.
> >
> > In my first post as a graduate, I researched the causes of dewetting on
> > circuit boards. I came across a solution, the make-up of which I have
> > since
> > lost, which dissolved the tin lead alloy but left the two intermetallic
> > layers.
> >
> > I produced a number of one inch square coupons which I soldered using
> > 63/37
> > alloy, RMA flux and a Tri Moore Rotary Dip Tester.
> >
> > These were divided into three categories:
> >
> > 1 Control
> > 2 Remove tin lead and re test in the Rotary Dip.
> > 3 Remove tin lead, Several hours steam ageing and re test.
> >
> > Microsections showed that I had taken off the alloy successfully and
left
> > the IMC.s.
> >
> > All of the re tested coupons soldered successfully, including the steam
> > aged
> > ones.
> >
> > This was some years ago so I cannot remember the etchant nor the hours
and
> > conditions in the steam ageing equipment. I do remember that the IMC
> > soldered very well so I am always dubious when somebody blames the
> > intermetallic for poor soldering.
> >
> > I seem to be alone in my faith that the IMC solders but this was the
> > result
> > of my very own work and I stand by it.
> >
> > Regards
> > Eric Dawson, Defender of the IMC.
> >
> >
--------------------------------------------------------------------------
> > --
> > -----
> >
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send the following message: SET
> > Technet NOMAIL
> > Search previous postings at: www.ipc.org > On-Line Resources & Databases
>
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
--------------------------------------------------------------------------
> > --
> > -----
> >
> >
--------------------------------------------------------------------------
> > --
> > -----
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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in
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>
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
--------------------------------------------------------------------------
> > --
> > -----
> >
> >
--------------------------------------------------------------------------
> > -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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in
> > the BODY (NOT the subject field): SIGNOFF Technet
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>
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
--------------------------------------------------------------------------
> > -------
>
>
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-----
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========================================================================Date: Wed, 14 Nov 2001 17:39:14 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Kovar
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 11/14/01 9:21:10 AM Pacific Standard Time,
[log in to unmask] writes:
thanks for your input - but was looking for a little more substance in the
answer.
>>
What specifically would you like to know about etching Kovar?
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========================================================================Date: Wed, 14 Nov 2001 20:29:54 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Aspect Ratio
MIME-Version: 1.0
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Hi Earl,
You may also want to look at IPC-D-279, Design Guidelines for Reliable
Surface Mount Technology Printed Board Assemblies, Appendix B, for more info
that is pretty up-to-date.
Werner
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========================================================================Date: Wed, 14 Nov 2001 20:29:53 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Aspect Ratio
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Hi Patty,
True, its been some time since the round-robin. However, the findings are
generally applicable to todays PCBs--one only has to put in the appropriate
geometry and property differences.
Best regards,
Werner Engelmaier
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========================================================================Date: Wed, 14 Nov 2001 22:29:30 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Kovar
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_9c.16498787.2924909a_boundary"
--part1_9c.16498787.2924909a_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
concentration of the ferric chloride - temperature? how different is it than
etching copper clad?
Richard
--part1_9c.16498787.2924909a_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=3 FAMILY="SERIF" FACE="Times New Roman" LANG="0">concentration of the ferric chloride - temperature? how different is it than etching copper clad?
<BR>
<BR>Richard</FONT></HTML>
--part1_9c.16498787.2924909a_boundary--
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========================================================================Date: Wed, 14 Nov 2001 21:38:55 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: "Cowen, Mike" <[log in to unmask]>
Subject: Reflow Solder balls
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I am looking for any information on the reduction of solder balls caused by
the reflow/printing process.
Any help or ideas would be greatly appreciated.
Michael Cowen
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========================================================================Date: Thu, 15 Nov 2001 13:17:39 +0800
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From: "Zhu, Xiang" <[log in to unmask]>
Subject: ENIG-Black Pad
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Hello All,
I encounter a touch problem with ENIG (Electroless Nickel / Immersion Gold)
PCB in assembly process. This problem maybe so-called "Black Pad".
This problem happen on a ten layers RCC build-up PCB's uBGA pads. The BGA
pad on PCB is 0.4mm in diameter with 0.8mm pitch. On some BGA pads, there
are 6 mil laser via connecting layer 1 and layer 2 (via in pad).
In ICT station, detect this problem as open. When I remove the BGA wit hot
air, find some pads didn't wetted with solder at all and have a dark/black
appearance. I think the surface of black pad is passivated nickel.
I don't know what kind of source caused this defect and how to prevent it.
PCB vendor or our assembly process cause this problem?
Is there anybody who ever encounter this kind of problem? Please kindly
offer me a hand.
Thank you in advance for your kindly help!
Best regards,
Zhu Xiang
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========================================================================Date: Thu, 15 Nov 2001 00:28:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: Earl Moon <[log in to unmask]>
Subject: Re: ENIG-Black Pad
X-To: Zhu Xiang <[log in to unmask]>
Get back to your board supplier as soon as possible and discuss. I haven't
seen, or even heard of this problem in over six months now. I am in touch
with many ENIG users - as designers, assemblers, and test folks using mostly
the big board fab houses though some protos are made in smaller shops.
I hope the problems is lessening because board shops are doing a better job
with better plating/coating chemistries and processes. Much has been written
on this problem on this forum, so look in the archives.
Black pad is exactly as you describe and opens are easily found during test
but that's very unfortunate as then it's way too late. As received, you
cannot tell the problem exists.
Visually, upon device removal, non-wetted pads appear black where
non-wetting is observed often with solder "bumps or ridges" where wetting
did occur.
There is no possibility of rendering the black surfaces solderable. You
can't scrape it off and no matter how many times you try, you cannot solder
to it though I did once have success taking the boards back to the supplier
and have them HASL coated after stripping off the surface coating.
Wish you the very best in your unfortunate situation,
MoonMan
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========================================================================Date: Thu, 15 Nov 2001 00:34:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Kovar
X-To: [log in to unmask]
Having a little trouble understanding your question. Kovar is copper clad.
Are you using this stuff in CTE/core boards or what? Used to use in with
Invar, a variation on the them, for LCCC boards.
Talk to TI, as one example. They use it, as some other semi manufacturers,
to etch lead frames. That's where I found out about it over 15 years ago
when using CIC/CCI.
MoonMan
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========================================================================Date: Thu, 15 Nov 2001 13:55:10 +0800
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Fritz Benjamin G. Cabingan
RF PCC Equipment Engineering
Philips Semiconductors Phils., Inc.
Tel. Nos.: (6349) 5430001 to 25 ext. 288
(632) 8445139 ext. 288
Fax Nos.: (632) 8445248/(6349) 5430027
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========================================================================Date: Thu, 15 Nov 2001 07:12:19 -0000
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From: Bob Willis <[log in to unmask]>
Subject: Re: Reflow Solder balls
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You should be a little more specific for people to assist but here you are with some general guidence:
Elimination of solder beading first you need to consider what causes solder beads on your board
First what is a Solder Bead?
The term solder bead is used to differentiate it from solder balls. A solder bead is a solder ball but its location is normally constant unlike solder balls. Solder beads are located on the side of chip components between the terminations and away from the lands as illustrated in the photographs.
Solder beads are seen more commonly with no clean processes due to the fact that there is no cleaning process to wash them away. The solder beads are normally 0.010" in size but this can vary depending on the amount of solder paste available to form them. On some occasions there can be more than one ball at any one location.
Solder beads can also be found at the side of SOT89, SOT23 and on leadless ceramic chip carriers. Many of your production and quality engineering colleagues look to a specification for guidance on the acceptable size of a ball as they are very difficult and time consuming to remove. The real solution is find the cause and that will help you to eliminate the problem.
The solder bead is formed when solder paste is present under a component and can not form a joint at the solderable land or component termination. Solder paste can become trapped under the body of a component and then when the paste particles reflow it starts to coaless together to form a larger ball. Normally speaking the solder paste at the end terminations has already reflowed and wet the joint so the paste under the device can not form due to the limited space available under the part. This causes the liquid solder to flow from under the part at this point the solder is free to form a bead and hence the defect. You can see the solder beading phenomena demonstrated on my video tape titled "Reflow Soldering and Temperature Profiling".
After explaining what it is and how it forms let us together consider the causes and corrective action. Stencil Printing can cause the problem if the incorrect process parameters are used. The stencil aperture should be slightly reduced from the pad size 10% reduction is quite a common rule in our industry.
The stencil should make contact with the surface of the pad before and during printing this prevents paste being forced under the stencil causing it to be transferred to the surface of the next board. This correct initial set-up prevents the need for high squeegee pressures it also reduced the rate of under stencil wiping. Excess pressure will cause you problems paste is forced under the stencil and possibly where parts are to be placed.
Placement can cause the paste to be forced under the component body. Setting excessive placement force will displace solder paste between the component and resist coating. During reflow the beads will form. Removing components before reflow in areas where beads have formed in the past you can generally detect if this is the cause of the problem. The same thing can occur if you have a variation in the paste height. With the same placement force if the paste is higher you get the same end result.
Reflow Soldering inspection is where the solder beading fault is generally first detected. In-process inspection after reflow will allow you to detect the rate of solder beading. In the case of reflow it is the rate of paste slump which causes the solder paste to be present under the parts. When evaluating solder paste a key factor is paste slump which can occur during the early stages of pre heat or just before the paste moves into the reflow stage.
Simple reflow tests using a board which has been printed and components placed can help you understand the process. Placing the board on a hot plate using similar profile parameters as the oven will allow the whole sequence to be viewed. An alternative is to take a populated board and pass it through the reflow oven without the final reflow spike. This can be achieved by lowering the final zone temperature which will give the sample board the complete pre heat cycle without reflow. The sample board can then be examined by removing selected chips and examining the amount of paste under the parts.
Solder slump tests on paste is a standard paste test you should conduct using a ceramic tile and printing small dots of paste. A measure of the diameter of the paste is made before and after heat exposure. As the paste does not reflow you can measure the worst possible slump for a given paste and oven profile. This test is normally refereed to as hot slumping.
As I have previously stated the oven profile and the point when the flux activates can also increase or decrees the amount of solder beads. That is why so often changing a paste can reduce the problem. This demonstrates that the original profile used was incorrect and poorly specified by the engineering staff. Remember that a poorly set-up oven profile can make the best paste on the market look poor.
Solder paste particles rely on their initial surface cleanliness and the activity of the paste to allow them to reflow and coaless in to a single ball. If the activity is low then it is quite possible for any paste to leave multiple balls at the side of chip parts. Inevitably as the components get smaller the distance between terminations on the chips becomes smaller. This may increase the presence of solder beads.
The solder mask thickness between the chip and board will exaggerate the problem as a limited space is available to allow the paste to flow back to the original print area. From a design point of view solder mask under chip components is only required if a track is placed under a part. If there is no mask the paste will flow back to the termination points more readily. Solder mask apertures are a necessity around pads when a track or via hole is present under a component.
Bob Willis Guide to Solder Spots - A New Plague in Manufacture ?
So what are solder spots ? They appear to be the next big problem in modern reflow assembly, in fact in any process that involves solder paste. The spots are visible on the surface of pads which have not been pasted prior to reflow. The spots are seen more commonly on copper, gold or any surface which is not fusible during reflow. The spots are a tin lead alloy which become visible due mainly to the different colour of the pad surface and the wetting action which takes place at reflow. If the spots were on a tin/lead or silver surface there would not be much of a problem. Out of sight out of mind. Some companies do apply rigid standards or apply the IPC guidelines very vigorously, failing the products at final test or during goods receipt if products are contracted out.
If the surface of the pads are to be used for interconnection then any contamination may not be acceptable. Contact strips, LCD interconnection or key pads are examples where solder contamination of course, mechanical connection failure or intermittence. This would, have cause be related to the position and the size of the spots. It is, however much easier to just reject the products than make a judgment call but that is a costly option. Depending on the cost of the product, make repair viable the spots can be removed without any obvious signs.
If the spot is high off the surface of the pad concern may be shown on the effect on contact resistance on the switch pads. Any key contact or button contacting the surface may be lifted off the pad by the solder spot which will decrease the surface contact and increase the contact resistance. In most cases the contact resistance tolerance on such actions is wide and less likely to cause a problem.
Surface analysis of the solder spots has confirmed that the spots are tin/lead and are most probably caused by solder paste particles. More detailed evaluation would be able to determine the alloy content and separate the hand cored wire, wave soldering alloy or even plating from component terminations. The particles present on the surface of the pads during reflow will wet the surface and it only takes the smallest of particles to have a visual impact on copper and gold features. The surface spots can be seen as a random defect or consistently in the same position on the circuit pattern. They are very commonly seen at the edge of tacks and pads which is normally a fairly good indication of the root cause of the problem.
Elimination of the spot plague needs close consideration of each of the assembly stages in the modern factory. This is necessary as each could contribute to the problem of surface contaminates.
So lets call in the spot inspector !
Screen Print
During solder paste printing thousands of small balls are printed on to the surface of the board in an attempt to produce consistent solder joints. During normal printing there are a number of things which make contact with the top and bottom surface of the board. The most obvious is the metal stencil which contacts the surface of the pads and depending on the pressure applied during printing, the surface of the board.
Solder paste will squeeze out between the stencil and the pad if a poor gasket is produced allowing paste to contaminate the base of the stencil. Recent video recordings produced by the author showing paste squeeze out due to uneven board surfaces show how much this can be a problem in manufacture. In this situation the paste particles on the base of the stencil can contaminate the adjacent areas of the next and future boards. When an under stencil wipe is used the particles can be spread around on the base of the stencil without being properly removed resulting in random spots after reflow. Care needs to be taken on the maintenance of the wiper cloth and the solvents used.
During printing supports are used to maintain the board flat and provide the ideal surface for printing. The board support may be a solid machined plate, groups of magnetic pins or specially moulded supports. In the case of the machined or moulded support or nests vacuum is normally used to help nest the board. Excessive suction has been shown to pull paste particles through the board to the base or along the surface of the board between the stencil. In each case this has resulted in surface contamination which can be random or in a line from a pasted pad feature to a via or hole where the vacuum pressure is seen. It is also most likely to be on the edge of pads.
There are very few examples of plating outgassing today but one example of a surface mount component was analysed recently. The component terminations outgassed during soldering caused voids in the joints and local spots. This was originally blamed on the paste and reflow profile until the components were tested.
PCB Wash Off
One of the most common reasons for random defects is washed off boards. The board may look clean but a few solder balls is all it takes to cause solder spotting. If the board is poorly printed or there is down time on a production line boards may be washed off. When this is done paste particles can still be found in via holes, tooling holes and in resist apertures between the resist wall and the pad. This is why solder spotting is often seen at the very edge of the pads after reflow.
There have been many occasions where poor washing was the cause but every one said the boards had never been cleaned.
"We never ever do that" said one contractor at an workshop only to be shown the particles in the solder resist undercut.
Placement
After components are placed into the surface of the paste the board should be reflowed and that is the operation complete. Misplaced components can be only just off the surface of the pad or completely misplaced. This can result in manual pick up of a part and repositioning it in its correct location. If the part has been in contact with the paste then the terminations will have paste on them. If the part was on another pad which is not pasted some paste will be left behind when the part is lifted. This would be totally random and very few companies have records of the occasional replacement exercise.
If a component is released prematurely by the placement head or the component bounces on the surface of the board the part will not be present. The paste spots would be on the surface of gold or on other non-tin/lead pads causing solder spots after reflow. Some other engineers have also noted that solder paste can be blown off pads by the air pressure of the pick up tools when the component has been released. This has been noted on boards with very small paste deposits, 0201, CSP etc.
Printed Boards
There are times where the type of assembly or issues with the printed board can cause solder spotting during reflow. There are occasions when manufacturing engineers have printed solder paste into via holes to fill the via during reflow. This may have been done to provide a test pad, prevent vacuum loss during in circuit test or in an attempt to improve the reliability of the via. Paste printed into a via will reflow but what if the copper plating thickness is poorly controlled the via will gas causing the particles of paste to be displaced.
The same can be seen during pin in hole/intrusive reflow assembly. A large volume of paste in a confined space will prove difficult for the soak zone of a reflow process to allow the evaporation of the solvent. Again small particles can gas out causing random spotting.
Reflow
Some engineers have blamed the reflow oven for causing the paste to spit resulting in random spotting. Solder paste should not spit during reflow if the profile and the paste are compatible. To test your product simply take a hot plate and a pasted board and reflow the board on the plate matching the profile recommended by the solder paste supplier. This has been done in the past by placing shims between the board and the plate to adjust the ramp rate. The same test can be conducted in an oven during the normal reflow cycle but it does not provide the opportunity to record or observe the cycle, seeing is believing.
Take an hour glass plate normally used in a laboratory and place it over the board. The smaller the glass and the closer it is to the paste the better. This technique was originally used by the author to show when the different solvents in a paste evaporated during reflow. Normally condensation is seen on the surface of the glass. If any spitting were to occur with a paste this would be visible on the hour glass. An alternative is to use a white card when placed over a hot plate. The white paper or card trick is also used to assess some cored solder wires for spitting during hand soldering and is simple and cheap evaluation tool.
A number of engineers have considered the possibility of paste particles being circulated in the convection reflow oven, either due to high convection rates or re-circulating of gas at reflow or cooling phases. Poor maintenance of the equipment could, it has been suggested allow paste particles to fall onto the surface of passing boards prior to reflow. This is less likely due to the weight of the paste particles but can easily be determined. Production manager may not like it as throughput is king, but a problem needs to be sorted. Take a few sheets of thin copper laminate and, without any production running through the machine, pass the sheets repeatedly through the process. Inspect the panels after each pass for spotting.
There are still some companies who process double sided reflow products on mesh belts with the board in contact with the mesh during its second pass. A poorly maintained machine can easily have paste residues on the mesh which could contaminate the base of the board.
A final area to investigate are the entry and zone curtains on some ovens. The rubber curtains can, if incorrectly positioned or cut, will not only contaminate the board but displace components.
Rework
If solder paste is used during rework there is an opportunity for paste contamination. Normally paste used during rework is manually dispensed although some companies use mini stencils to apply the paste. This is a more obvious area for paste contamination and would normally be spotted quite quickly during investigation.
Finally just handling the boards in production should be avoided as any operator or technician knows paste gets everywhere. Generally when operators are using bare hands to handle boards they tend to be more careful with paste contamination. Some companies have the policy of wearing gloves which reduces the need for care as the paste will not go on your hands. Disposable gloves are used but they tend to cause sweating and not that well liked. The alternative reusable gloves tend to get dirty and again cause handling contamination.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Cowen, Mike
To: [log in to unmask]
Sent: Thursday, November 15, 2001 3:38 AM
Subject: [TN] Reflow Solder balls
I am looking for any information on the reduction of solder balls caused by
the reflow/printing process.
Any help or ideas would be greatly appreciated.
Michael Cowen
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Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>You should be a little more specific for people to
assist but here you are with some general guidence:</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Elimination of solder beading first you need to
consider what causes solder beads on your board</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><BR>First what is a Solder Bead? </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The term solder bead is used to differentiate it
from solder balls. A solder bead is a solder ball but its location is normally
constant unlike solder balls. Solder beads are located on the side of chip
components between the terminations and away from the lands as illustrated in
the photographs. </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Solder beads are seen more commonly with no clean
processes due to the fact that there is no cleaning process to wash them away.
The solder beads are normally 0.010" in size but this can vary depending on the
amount of solder paste available to form them. On some occasions there can be
more than one ball at any one location.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Solder beads can also be found at the side of
SOT89, SOT23 and on leadless ceramic chip carriers. Many of your production and
quality engineering colleagues look to a specification for guidance on the
acceptable size of a ball as they are very difficult and time consuming to
remove. The real solution is find the cause and that will help you to eliminate
the problem.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The solder bead is formed when solder paste is
present under a component and can not form a joint at the solderable land or
component termination. Solder paste can become trapped under the body of a
component and then when the paste particles reflow it starts to coaless together
to form a larger ball. Normally speaking the solder paste at the end
terminations has already reflowed and wet the joint so the paste under the
device can not form due to the limited space available under the part. This
causes the liquid solder to flow from under the part at this point the solder is
free to form a bead and hence the defect. You can see the solder beading
phenomena demonstrated on my video tape titled "Reflow Soldering and Temperature
Profiling".</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>After explaining what it is and how it forms let us
together consider the causes and corrective action. Stencil Printing can cause
the problem if the incorrect process parameters are used. The stencil aperture
should be slightly reduced from the pad size 10% reduction is quite a
common rule in our industry. </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The stencil should make contact with the surface of
the pad before and during printing this prevents paste being forced under the
stencil causing it to be transferred to the surface of the next board. This
correct initial set-up prevents the need for high squeegee pressures it also
reduced the rate of under stencil wiping. Excess pressure will cause you
problems paste is forced under the stencil and possibly where parts are to be
placed. </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Placement can cause the paste to be forced under
the component body. Setting excessive placement force will displace solder paste
between the component and resist coating. During reflow the beads will form.
Removing components before reflow in areas where beads have formed in the past
you can generally detect if this is the cause of the problem. The same thing can
occur if you have a variation in the paste height. With the same placement force
if the paste is higher you get the same end result.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Reflow Soldering inspection is where the solder
beading fault is generally first detected. In-process inspection after reflow
will allow you to detect the rate of solder beading. In the case of reflow it is
the rate of paste slump which causes the solder paste to be present under the
parts. When evaluating solder paste a key factor is paste slump which can occur
during the early stages of pre heat or just before the paste moves into the
reflow stage.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Simple reflow tests using a board which has been
printed and components placed can help you understand the process. Placing the
board on a hot plate using similar profile parameters as the oven will allow the
whole sequence to be viewed. An alternative is to take a populated board and
pass it through the reflow oven without the final reflow spike. This can be
achieved by lowering the final zone temperature which will give the sample board
the complete pre heat cycle without reflow. The sample board can then be
examined by removing selected chips and examining the amount of paste under the
parts.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Solder slump tests on paste is a standard paste
test you should conduct using a ceramic tile and printing small dots of paste. A
measure of the diameter of the paste is made before and after heat exposure. As
the paste does not reflow you can measure the worst possible slump for a given
paste and oven profile. This test is normally refereed to as hot
slumping.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>As I have previously stated the oven profile and
the point when the flux activates can also increase or decrees the amount of
solder beads. That is why so often changing a paste can reduce the problem. This
demonstrates that the original profile used was incorrect and poorly specified
by the engineering staff. Remember that a poorly set-up oven profile can make
the best paste on the market look poor.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Solder paste particles rely on their initial
surface cleanliness and the activity of the paste to allow them to reflow and
coaless in to a single ball. If the activity is low then it is quite
possible for any paste to leave multiple balls at the side of chip parts.
Inevitably as the components get smaller the distance between terminations on
the chips becomes smaller. This may increase the presence of solder
beads.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The solder mask thickness between the chip and
board will exaggerate the problem as a limited space is available to allow the
paste to flow back to the original print area. From a design point of view
solder mask under chip components is only required if a track is placed under a
part. If there is no mask the paste will flow back to the termination points
more readily. Solder mask apertures are a necessity around pads when a track or
via hole is present under a component.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Bob Willis Guide to Solder Spots - A New Plague in
Manufacture ?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>So what are solder spots ? They appear to be the
next big problem in modern reflow assembly, in fact in any process that involves
solder paste. The spots are visible on the surface of pads which have not been
pasted prior to reflow. The spots are seen more commonly on copper, gold or any
surface which is not fusible during reflow. The spots are a tin lead alloy which
become visible due mainly to the different colour of the pad surface and the
wetting action which takes place at reflow. If the spots were on a tin/lead or
silver surface there would not be much of a problem. Out of sight out of mind.
Some companies do apply rigid standards or apply the IPC guidelines very
vigorously, failing the products at final test or during goods receipt if
products are contracted out.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>If the surface of the pads are to be used for
interconnection then any contamination may not be acceptable. Contact strips,
LCD interconnection or key pads are examples where solder contamination of
course, mechanical connection failure or intermittence. This would, have cause
be related to the position and the size of the spots. It is, however much easier
to just reject the products than make a judgment call but that is a costly
option. Depending on the cost of the product, make repair viable the spots can
be removed without any obvious signs.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>If the spot is high off the surface of the pad
concern may be shown on the effect on contact resistance on the switch pads. Any
key contact or button contacting the surface may be lifted off the pad by the
solder spot which will decrease the surface contact and increase the contact
resistance. In most cases the contact resistance tolerance on such actions is
wide and less likely to cause a problem.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Surface analysis of the solder spots has confirmed
that the spots are tin/lead and are most probably caused by solder paste
particles. More detailed evaluation would be able to determine the alloy content
and separate the hand cored wire, wave soldering alloy or even plating from
component terminations. The particles present on the surface of the pads during
reflow will wet the surface and it only takes the smallest of particles to have
a visual impact on copper and gold features. The surface spots can be seen as a
random defect or consistently in the same position on the circuit pattern. They
are very commonly seen at the edge of tacks and pads which is normally a fairly
good indication of the root cause of the problem.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Elimination of the spot plague needs close
consideration of each of the assembly stages in the modern factory. This is
necessary as each could contribute to the problem of surface contaminates.
<BR>So lets call in the spot inspector !</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Screen Print</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>During solder paste printing thousands of small
balls are printed on to the surface of the board in an attempt to produce
consistent solder joints. During normal printing there are a number of things
which make contact with the top and bottom surface of the board. The most
obvious is the metal stencil which contacts the surface of the pads and
depending on the pressure applied during printing, the surface of the board.
</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Solder paste will squeeze out between the stencil
and the pad if a poor gasket is produced allowing paste to contaminate the base
of the stencil. Recent video recordings produced by the author showing paste
squeeze out due to uneven board surfaces show how much this can be a problem in
manufacture. In this situation the paste particles on the base of the stencil
can contaminate the adjacent areas of the next and future boards. When an under
stencil wipe is used the particles can be spread around on the base of the
stencil without being properly removed resulting in random spots after reflow.
Care needs to be taken on the maintenance of the wiper cloth and the
solvents used.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>During printing supports are used to maintain the
board flat and provide the ideal surface for printing. The board support may be
a solid machined plate, groups of magnetic pins or specially moulded supports.
In the case of the machined or moulded support or nests vacuum is normally used
to help nest the board. Excessive suction has been shown to pull paste particles
through the board to the base or along the surface of the board between the
stencil. In each case this has resulted in surface contamination which can be
random or in a line from a pasted pad feature to a via or hole where the vacuum
pressure is seen. It is also most likely to be on the edge of pads.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>There are very few examples of plating outgassing
today but one example of a surface mount component was analysed recently. The
component terminations outgassed during soldering caused voids in the joints and
local spots. This was originally blamed on the paste and reflow profile until
the components were tested.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>PCB Wash Off</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>One of the most common reasons for random defects
is washed off boards. The board may look clean but a few solder balls is all it
takes to cause solder spotting. If the board is poorly printed or there is down
time on a production line boards may be washed off. When this is done paste
particles can still be found in via holes, tooling holes and in resist apertures
between the resist wall and the pad. This is why solder spotting is often seen
at the very edge of the pads after reflow.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>There have been many occasions where poor washing
was the cause but every one said the boards had never been
cleaned.<BR> <BR>"We never ever do that" said one contractor at an workshop
only to be shown the particles in the solder resist undercut.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Placement</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>After components are placed into the surface of the
paste the board should be reflowed and that is the operation complete. Misplaced
components can be only just off the surface of the pad or completely misplaced.
This can result in manual pick up of a part and repositioning it in its correct
location. If the part has been in contact with the paste then the terminations
will have paste on them. If the part was on another pad which is not pasted some
paste will be left behind when the part is lifted. This would be totally random
and very few companies have records of the occasional replacement
exercise.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>If a component is released prematurely by the
placement head or the component bounces on the surface of the board the part
will not be present. The paste spots would be on the surface of gold or on other
non-tin/lead pads causing solder spots after reflow. Some other engineers have
also noted that solder paste can be blown off pads by the air pressure of the
pick up tools when the component has been released. This has been noted on
boards with very small paste deposits, 0201, CSP etc.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Printed Boards</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>There are times where the type of assembly or
issues with the printed board can cause solder spotting during reflow. There are
occasions when manufacturing engineers have printed solder paste into via holes
to fill the via during reflow. This may have been done to provide a test pad,
prevent vacuum loss during in circuit test or in an attempt to improve the
reliability of the via. Paste printed into a via will reflow but what if the
copper plating thickness is poorly controlled the via will gas causing the
particles of paste to be displaced.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same can be seen during pin in hole/intrusive
reflow assembly. A large volume of paste in a confined space will prove
difficult for the soak zone of a reflow process to allow the evaporation of the
solvent. Again small particles can gas out causing random spotting.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Reflow</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Some engineers have blamed the reflow oven for
causing the paste to spit resulting in random spotting. Solder paste should not
spit during reflow if the profile and the paste are compatible. To test your
product simply take a hot plate and a pasted board and reflow the board on the
plate matching the profile recommended by the solder paste supplier. This has
been done in the past by placing shims between the board and the plate to adjust
the ramp rate. The same test can be conducted in an oven during the normal
reflow cycle but it does not provide the opportunity to record or observe the
cycle, seeing is believing.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Take an hour glass plate normally used in a
laboratory and place it over the board. The smaller the glass and the closer it
is to the paste the better. This technique was originally used by the author to
show when the different solvents in a paste evaporated during reflow. Normally
condensation is seen on the surface of the glass. If any spitting were to occur
with a paste this would be visible on the hour glass. An alternative is to use a
white card when placed over a hot plate. The white paper or card trick is also
used to assess some cored solder wires for spitting during hand soldering and is
simple and cheap evaluation tool.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>A number of engineers have considered the
possibility of paste particles being circulated in the convection reflow oven,
either due to high convection rates or re-circulating of gas at reflow or
cooling phases. Poor maintenance of the equipment could, it has been suggested
allow paste particles to fall onto the surface of passing boards prior to
reflow. This is less likely due to the weight of the paste particles but can
easily be determined. Production manager may not like it as throughput is king,
but a problem needs to be sorted. Take a few sheets of thin copper laminate and,
without any production running through the machine, pass the sheets repeatedly
through the process. Inspect the panels after each pass for
spotting.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>There are still some companies who process double
sided reflow products on mesh belts with the board in contact with the mesh
during its second pass. A poorly maintained machine can easily have paste
residues on the mesh which could contaminate the base of the board.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>A final area to investigate are the entry and zone
curtains on some ovens. The rubber curtains can, if incorrectly positioned or
cut, will not only contaminate the board but displace
components.<BR> <BR>Rework</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>If solder paste is used during rework there is an
opportunity for paste contamination. Normally paste used during rework is
manually dispensed although some companies use mini stencils to apply the paste.
This is a more obvious area for paste contamination and would normally be
spotted quite quickly during investigation.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Finally just handling the boards in production
should be avoided as any operator or technician knows paste gets everywhere.
Generally when operators are using bare hands to handle boards they tend to be
more careful with paste contamination. Some companies have the policy of wearing
gloves which reduces the need for care as the paste will not go on your
hands. Disposable gloves are used but they tend to cause sweating and not
that well liked. The alternative reusable gloves tend to get dirty and again
cause handling contamination.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Cowen,
Mike</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Thursday, November 15, 2001 3:38
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] Reflow Solder balls</DIV>
<DIV><BR></DIV>I am looking for any information on the reduction of solder
balls caused by<BR>the reflow/printing process.<BR>Any help or ideas would be
greatly appreciated.<BR><BR><BR>Michael
Cowen<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Thu, 15 Nov 2001 07:06:08 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: ENIG-Black Pad
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As Earl says this is most likely to be PCB related from your description. I still see this when doing failure investigations and can be a real show stopper.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Earl Moon
To: [log in to unmask]
Sent: Thursday, November 15, 2001 6:28 AM
Subject: Re: [TN] ENIG-Black Pad
Get back to your board supplier as soon as possible and discuss. I haven't
seen, or even heard of this problem in over six months now. I am in touch
with many ENIG users - as designers, assemblers, and test folks using mostly
the big board fab houses though some protos are made in smaller shops.
I hope the problems is lessening because board shops are doing a better job
with better plating/coating chemistries and processes. Much has been written
on this problem on this forum, so look in the archives.
Black pad is exactly as you describe and opens are easily found during test
but that's very unfortunate as then it's way too late. As received, you
cannot tell the problem exists.
Visually, upon device removal, non-wetted pads appear black where
non-wetting is observed often with solder "bumps or ridges" where wetting
did occur.
There is no possibility of rendering the black surfaces solderable. You
can't scrape it off and no matter how many times you try, you cannot solder
to it though I did once have success taking the boards back to the supplier
and have them HASL coated after stripping off the surface coating.
Wish you the very best in your unfortunate situation,
MoonMan
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<DIV><FONT face=Arial size=2>As Earl says this is most likely to be PCB related
from your description. I still see this when doing failure investigations and
can be a real show stopper.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Earl Moon</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Thursday, November 15, 2001 6:28
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] ENIG-Black Pad</DIV>
<DIV><BR></DIV>Get back to your board supplier as soon as possible and
discuss. I haven't<BR>seen, or even heard of this problem in over six months
now. I am in touch<BR>with many ENIG users - as designers, assemblers, and
test folks using mostly<BR>the big board fab houses though some protos are
made in smaller shops.<BR><BR>I hope the problems is lessening because board
shops are doing a better job<BR>with better plating/coating chemistries and
processes. Much has been written<BR>on this problem on this forum, so look in
the archives.<BR><BR>Black pad is exactly as you describe and opens are easily
found during test<BR>but that's very unfortunate as then it's way too late. As
received, you<BR>cannot tell the problem exists.<BR><BR>Visually, upon device
removal, non-wetted pads appear black where<BR>non-wetting is observed often
with solder "bumps or ridges" where wetting<BR>did occur.<BR>There is no
possibility of rendering the black surfaces solderable. You<BR>can't scrape it
off and no matter how many times you try, you cannot solder<BR>to it though I
did once have success taking the boards back to the supplier<BR>and have them
HASL coated after stripping off the surface coating.<BR><BR>Wish you the very
best in your unfortunate
situation,<BR><BR>MoonMan<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Thu, 15 Nov 2001 16:26:40 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Solder temperature question
MIME-Version: 1.0
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Hi, Pat,
HMP solder has a melting point about 100 degrees lower than your example
for electronics. Depends what you are soldering, but most components have
an upper temp limit for the dies around 230 deg C and a few go to 250 deg
C. Beyond that you risk internal damage.
In-service temperature excursions depend on the operating environment and
are limited by, and to, the rating of your components. Commercial parts are
rated between -20 deg C (at best) and +70 deg C. Industrial parts are rated
between -40 deg C and +85 deg C, while military parts are rated between -40
deg C and +125 deg C. Outside of these temperatures, the components may
work, but their specified performance is not guaranteed. They should not
see temperatures approaching soldering temperature in operation - they
definitely wouldn't survive for long at that.
Temperature settings for soldering should be 20 to 30 deg C above
liquidous, but watch out for the max case temperature of the components -
you may be getting pretty close to that with these settings. You will have
to tread a fine line between peak temperature and its duration to get the
boards to solder without damaging the component dies.
Good luck
Peter Duncan
"Diamond, Pat"
<PDiamond@WESTO To: [log in to unmask]
NAERO.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Solder temperature question
<[log in to unmask]
G>
11/13/01 04:17
PM
Please respond
to "TechNet
E-Mail Forum."
/Dear all,
I'm looking for some advice on the threshold limits for solder
temperatures,
if for example, HMP solder is solidus/liquidus at say 296-301 deg C, what
is
the highest temperature excursion it can see in service before the
properties of the soldered connection are affected?
I heard somewhere that as a rule of thumb you should allow around 40 deg C
below the melting point of the solder being used.
Any help/advice that you can give would be appreciated.
regards,
Pat Diamond
Weston Aerospace
Farnborough
UK
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========================================================================Date: Thu, 15 Nov 2001 16:43:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: ENIG-Black Pad
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
The main thing to check with your fab house is the phosphor concentration
in their Nickel Plating Bath. Maybe take a sample and have it independantly
analysed if you're in any doubt. If it's higher than about 10%, this is
probably the cause of your Black Pad (it should be between 6 and 8% for
good results). Also, make sure they don't allow the boards to dry out
between the Nickel plating process and the Gold Plating process, or the
Nickel will oxidise and also cause problems.
Peter Duncan
Earl Moon
<[log in to unmask] To: [log in to unmask]
M.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] ENIG-Black Pad
<[log in to unmask]
ORG>
11/15/01
02:28 PM
Please
respond to
"TechNet
E-Mail
Forum."
Get back to your board supplier as soon as possible and discuss. I haven't
seen, or even heard of this problem in over six months now. I am in touch
with many ENIG users - as designers, assemblers, and test folks using
mostly
the big board fab houses though some protos are made in smaller shops.
I hope the problems is lessening because board shops are doing a better job
with better plating/coating chemistries and processes. Much has been
written
on this problem on this forum, so look in the archives.
Black pad is exactly as you describe and opens are easily found during test
but that's very unfortunate as then it's way too late. As received, you
cannot tell the problem exists.
Visually, upon device removal, non-wetted pads appear black where
non-wetting is observed often with solder "bumps or ridges" where wetting
did occur.
There is no possibility of rendering the black surfaces solderable. You
can't scrape it off and no matter how many times you try, you cannot solder
to it though I did once have success taking the boards back to the supplier
and have them HASL coated after stripping off the surface coating.
Wish you the very best in your unfortunate situation,
MoonMan
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========================================================================Date: Thu, 15 Nov 2001 09:58:45 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: 0603 Components.
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Just looking into the IPC-SM-782 for landpatterns: The value of "G", which is the distance between the two pads, is 0.6 mm for 0603's but alos for 0805 components. So if you're using IPC-dimensioned footprints, the 0603 should be just as easy to glue as 0805's (or the other way around).
On real boards I see quite a lot of variation in the pad-to-pad distance, and the optimization of this value is one of the keys to succesfull glue dispensing for 0603 parts. From what I see, most designers don't care whether a board will be waved of double-reflowed, and they're using the same pads for both technologies. So if I advise a designer to have the pads close together to prevent from tombstoning during reflow, I'll have a problem later on if I have to wave-solder these same components because there's not enough space for a consistent glue dot.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Jim Gleason <[log in to unmask]> 11/14 8:01 pm >>>
RE: [TN] 0603 Components.Most of the 603 packages I've worked with went through the wave of if you had proper thermal profiles. But some people do prefer to reflow them and then cover them with a masking solder palllet. If your interested in the pallet give me a buzz offline.
Jim
GSC
972-494-1911
----- Original Message -----
From: Lush, Dorothy (FPTI)
To: [log in to unmask]
Sent: Wednesday, November 14, 2001 8:35 AM
Subject: Re: [TN] 0603 Components.
Why are you glueing? Can't you use a selective solderwave? Isn't exposing 0603's to molten solder going to affect their life span? How about using a single dot?
Dorothy Lush
-----Original Message-----
From: Stephen Owen [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 5:36 AM
To: [log in to unmask]
Subject: [TN] 0603 Components.
We are having some problems with 0603 components on adhesive, we are
running Fugi CP6's. Using 0.3mm dual nozzles, don't seem to be able to get
the consistency of the adhesive dot right.
Many thanks
Steve.
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========================================================================Date: Thu, 15 Nov 2001 09:09:52 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: [LF] US lead free logo TV Ad
X-To: [log in to unmask]
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Following the requests to see the Panasonic Lead Free Ad for the Mini Disk player you can view it at
www.seminar-registrations.com/videos/pana6c.rm
The ad was provided to the SMART Group Lead-Free Mission Team after our tour in February this year. The English translation at the bottom of the clip was done by those nice people at the British Embassy in Japan.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: [log in to unmask]
To: [log in to unmask]
Sent: Monday, November 12, 2001 10:07 PM
Subject: FW: [LF] US lead free logo
Hi, Bob:
Can you forward a copy of the Panasonic TV Ad?
Thanks
Dongkai
Regards,
Dongkai Shangguan, Ph.D.
Manager - Advanced Process Technology
FLEXTRONICS
2090 Fortune Drive, San Jose, CA 95131
Phone: (408) 428 1336 Fax: (408) 576 7988
E-mail: [log in to unmask]
-----Original Message-----
From: Bob Willis [mailto:[log in to unmask]]
Sent: Tuesday, October 30, 2001 8:38 AM
To: [log in to unmask]
Subject: Re: [LF] US lead free logo
If I get a chance before I go off to Productronica, Germany I will put all the logos to download on my web site. Alternativley I can put them into a folder which the IPC can put uk on thire site. We also recored a copy of the Lead Free TV Ad from Panasonic which I showed at Apex this year. Its neat and the first TV ad, unless anyone knows differently. The British Embasy translated the clip for us and we digitised it with the text under the film.
If any one is going to the show in Germany I am running a lead free production line including pin in hole intrusive reflow. If any one wants to see the video clips on the solder joints reflowing, x-rays or sections from the boards we are processing you may find its interesting. www.bobwillis.co.uk/workshops/Productronica.html
I intend to provide all the new video clips, x-rays, joint images for people to download after the event if any one wants to use them in thire own presentations that fine with me.
Many thanks for the interest.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Richard Hamilton
To: [log in to unmask]
Sent: Tuesday, October 30, 2001 4:18 PM
Subject: Re: [LF] US lead free logo
Bob,
Sounds like a good use of posting to a page on the web somewhere. Can you do that? I know I would be interested in looking at the various versions you have collected.
Richard
At 04:02 PM 10/30/01 +0000, you wrote:
Interesting debate, when we toured Japan with the SMART Group Lead Free Mission we asked the same question to most companies and also asked the relevant movement bodies and industries groups.
They said there was not one industry logo or a move to have one from the government, this surprised me but as most companies shave there own version of a leaf logo there are lots of different logos. If any one is interested I have most of them as images, my favourite is the Sony environmental logo its a teddy with baby teddy and green leaf.
There should be some simple coding of assemblies to show allot and I look forward to hearing about any activity to standardise this.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Romm, Doug
To: [log in to unmask]
Sent: Tuesday, October 30, 2001 3:38 PM
Subject: Re: [LF] US lead free logo
Tenison,
I have seen discussions about an 'industry-wide' lead-free logo through NEMI as well as through other industry organizations that standardize packing materials/strategies. I don't believe a 'standard' logo has been adopted yet.
The goal is to be able to identify 'lead-free' components at the packing material level. This would help to differentiate between lead-free and Pb-bearing components during the transition time from Pb-bearing to Pb-free.
As for TI, some product groups have begun indicating 'Pb-free' in specific advertising, where possible. We have not adopted a 'Pb-free' logo for packing materials although it is in discussion. We would prefer to follow the industry standard when available.
Best regards,
Doug Romm
Texas Instruments
http://www.ti.com/sc/leadfree
-----Original Message-----
From: Tenison Stone [mailto:[log in to unmask]]
Sent: Tuesday, October 30, 2001 8:07 AM
To: [log in to unmask]
Subject: [LF] US lead free logo
Hi everyone,
Has the IPC or a committee decided what and how a leadfree logo will be
implemented in the US?
What are businesses using in the US?
Tenison Stone
Telex Communications
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Following the requests to see the Panasonic Lead
Free Ad for the Mini Disk player you can view it at</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.seminar-registrations.com/videos/pana6c.rm">www.seminar-registrations.com/videos/pana6c.rm</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The ad was provided to the SMART Group Lead-Free
Mission Team after our tour in February this year. The English translation at
the bottom of the clip was done by those nice people at the British Embassy in
Japan.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 12, 2001 10:07
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> FW: [LF] US lead free logo</DIV>
<DIV><BR></DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001>Hi, Bob:</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001>Can you forward a copy of the Panasonic TV
Ad?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001>Thanks</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Book Antiqua" size=2><SPAN
class=126550622-12112001>Dongkai</SPAN></FONT></DIV>
<DIV> </DIV>
<P><FONT face="Times New Roman" size=1>Regards,</FONT> <BR><B><I><FONT
color=#0000ff face="Times New Roman" size=2>Dongkai
Shangguan</FONT></I></B><I></I><FONT face="Times New Roman" size=1>,</FONT>
<FONT face="Times New Roman" size=1>Ph.D.</FONT> <BR><FONT
face="Times New Roman" size=1>Manager - Advanced Process Technology</FONT>
<BR><B><FONT color=#000080 face=Arial size=1>FLE</FONT><FONT color=#c0c0c0
face=Arial size=1>X</FONT><FONT color=#000080 face=Arial
size=1>TRONICS</FONT></B> <BR><FONT face="Times New Roman" size=1>2090 Fortune
Drive, San Jose, CA 95131</FONT> <BR><FONT face="Times New Roman"
size=1>Phone: (408) 428 1336 Fax: (408) 576
7988</FONT> <BR><FONT face="Times New Roman" size=1>E-mail: <A
href="mailto:[log in to unmask]">[log in to unmask]</A></FONT>
</P>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR><B>Sent:</B>
Tuesday, October 30, 2001 8:38 AM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [LF] US lead free
logo<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>If I get a chance before I go off to
Productronica, Germany I will put all the logos to download on my web site.
Alternativley I can put them into a folder which the IPC can put uk on thire
site.</FONT><FONT face=Arial size=2> We also recored a copy of the Lead Free
TV Ad from Panasonic which I showed at Apex this year. Its neat and the first
TV ad, unless anyone knows differently. The British Embasy translated the clip
for us and we digitised it with the text under the film.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>If any one is going to the show in Germany I am
running a lead free production line including pin in hole intrusive reflow. If
any one wants to see the video clips on the solder joints reflowing, x-rays or
sections from the boards we are processing you may find its interesting. <A
href="http://www.bobwillis.co.uk/workshops/Productronica.html">www.bobwillis.co.uk/workshops/Productronica.html</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>I intend to provide all the new video clips,
x-rays, joint images for people to download after the event if any one wants
to use them in thire own presentations that fine with me.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Many thanks for the interest.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth
Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>Richard Hamilton</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, October 30, 2001 4:18
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [LF] US lead free
logo</DIV>
<DIV><BR></DIV>Bob,<BR><BR>Sounds like a good use of posting to a page on
the web somewhere. Can you do that? I know I would be interested in looking
at the various versions you have collected. <BR><BR>Richard<BR><BR>At 04:02
PM 10/30/01 +0000, you wrote:<BR><FONT face=arial size=2>
<BLOCKQUOTE cite type="cite">Interesting debate, when we toured Japan with
the SMART Group Lead Free Mission we asked the same question to most
companies and also asked the relevant movement bodies and industries
groups.</FONT><BR> <BR><FONT face=arial size=2>They said there was
not one industry logo or a move to have one from the government, this
surprised me but as most companies shave there own version of a leaf logo
there are lots of different logos. If any one is interested I have most of
them as images, my favourite is the Sony environmental logo its a teddy
with baby teddy and green leaf.</FONT><BR> <BR><FONT face=arial
size=2>There should be some simple coding of assemblies to show allot and
I look forward to hearing about any activity to standardise
this.</FONT><BR> <BR>Bob Willis<BR>Electronic Presentation
Services<BR>2 Fourth Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123<BR> <BR>Single solution to your
seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A><BR>
<BLOCKQUOTE cite type="cite">----- Original Message -----
<BR><B>From:</B> <A href="mailto:[log in to unmask]">Romm, Doug</A>
<BR><B>To:</B> <A href="mailto:[log in to unmask]">[log in to unmask]</A>
<BR><B>Sent:</B> Tuesday, October 30, 2001 3:38 PM<BR><B>Subject:</B>
Re: [LF] US lead free logo<BR><BR><FONT size=2>Tenison,</FONT>
<BR><BR><FONT size=2>I have seen discussions about an 'industry-wide'
lead-free logo through NEMI as well as through other industry
organizations that standardize packing materials/strategies. I
don't believe a 'standard' logo has been adopted yet.<BR></FONT><BR>The
goal is to be able to identify 'lead-free' components at the packing
material level. This would help to differentiate between lead-free
and Pb-bearing components during the transition time from Pb-bearing to
Pb-free.<BR><BR>As for TI, some product groups have begun indicating
'Pb-free' in specific advertising, where possible. We have not
adopted a 'Pb-free' logo for packing materials although it is in
discussion. We would prefer to follow the industry standard when
available.<BR><BR>Best regards, <BR><BR>Doug Romm <BR><FONT size=2>Texas
Instruments</FONT> <BR><FONT size=2><A
href="http://www.ti.com/sc/leadfree">http://www.ti.com/sc/leadfree</A></FONT>
<BR><BR><BR><BR><BR><BR><FONT size=2>-----Original Message-----</FONT>
<BR><FONT size=2>From: Tenison Stone [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Tuesday, October 30, 2001 8:07 AM</FONT>
<BR><FONT size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject:
[LF] US lead free logo</FONT> <BR><BR><FONT size=2>Hi everyone,</FONT>
<BR><BR><FONT size=2>Has the IPC or a committee decided what and how a
leadfree logo will be</FONT> <BR><FONT size=2>implemented in the
US?</FONT> <BR><BR><FONT size=2>What are businesses using in the
US?</FONT> <BR><BR><FONT size=2>Tenison Stone</FONT> <BR><FONT
size=2>Telex Communications</FONT> <BR><BR><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Leadfee Mail List provided as a free service by IPC
using LISTSERV 1.8d</FONT> <BR><FONT size=2>To unsubscribe, send a
message to [log in to unmask] with following text in</FONT> <BR><FONT
size=2>the BODY (NOT the subject field): SIGNOFF Leadfree</FONT>
<BR><FONT size=2>To temporarily stop delivery of Leadree for vacation
breaks send: SET Leadfree NOMAIL</FONT> <BR><FONT size=2>Search previous
postings at: <A href="http://www.ipc.org/"
eudora="autourl">www.ipc.org</A> > On-Line Resources & Databases
> E-mail Archives</FONT> <BR><FONT size=2>Please visit IPC web site
(<A
href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</A>)
for additional</FONT> <BR><FONT size=2>information, or contact Keach
Sasamori at [log in to unmask] or 847-509-9700 ext.5315</FONT> <BR><FONT
size=2>---------------------------------------------------------------------------------</FONT>
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---------------------------------------------------------------------------------
========================================================================Date: Thu, 15 Nov 2001 11:15:47 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Grant Emandien <[log in to unmask]>
Subject: Handling of moisture sensitive devices
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi All,
I am seeking advice on handling methods of moisture sensitive devices from
reception/storage to use. Components have varying baking requirements after
the packaging has been opened - is baking performed as per. manufacturer's
instructions?
One of our customers is insistent on us, as an assembler to bake
(customer-supplied) components just prior to assembly - this approach
however does impose some impracticalities on production. Our initial counter
proposal is to receive only components in original OEM wrapping indicating
the moisture instructions and class/level and to then return bake and reseal
(vacuum/nitrogen) excess opened material to stores - the package would also
include a humidity indicator. Our proposal is more amenable to production,
but is it sufficient to ensure device integrity? Any insights on the
approach of assemblers?
TIA
Grant
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========================================================================Date: Thu, 15 Nov 2001 19:01:10 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Handling of moisture sensitive devices
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
We're doing a prototype run of boards for which awareness of Moisture
Control and Moisture Sensitive components came quite late on. Components'
packaging was opened and left opened in an uncontrolled environment, so I
also insist that all MSD's are baked out at 125 deg C for 48 hours prior to
assembly and stored in a dry cabinet (5% RH and 25 deg C).
Ideally though, they should be baked out and immediatey re-sealed in their
original packaging as you describe. J-STD's 20 and 33 should give you the
info you need on this. The moisture classification really only indicates
the sensitivity to moisture absorbtion - how quickly the component reaches
it moisture limit before bake-out is required. Bake-out time and
temperature is standard, I believe, as stated above. I always prefer to
have the minimum number of thermal excursions of any kind for anything to
do with board assemblies to maximise longevity and reliability, and
continually pre-baking components that are not properly sealed in their
original packaging is anathema to me.
Peter Duncan
Grant Emandien
<gemandien@TEL To: [log in to unmask]
LUMAT.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Handling of moisture sensitive
<[log in to unmask] devices
RG>
11/15/01 05:15
PM
Please respond
to "TechNet
E-Mail Forum."
Hi All,
I am seeking advice on handling methods of moisture sensitive devices from
reception/storage to use. Components have varying baking requirements after
the packaging has been opened - is baking performed as per. manufacturer's
instructions?
One of our customers is insistent on us, as an assembler to bake
(customer-supplied) components just prior to assembly - this approach
however does impose some impracticalities on production. Our initial
counter
proposal is to receive only components in original OEM wrapping indicating
the moisture instructions and class/level and to then return bake and
reseal
(vacuum/nitrogen) excess opened material to stores - the package would also
include a humidity indicator. Our proposal is more amenable to production,
but is it sufficient to ensure device integrity? Any insights on the
approach of assemblers?
TIA
Grant
**********************************************************************
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========================================================================Date: Thu, 15 Nov 2001 14:33:42 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Resistor Networks of 0.5 mm Pitch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi Alejandro,
it may turn out that HASL is not the best choice for this application. With
this pitch and lower we love to have a more planar surface.
We had enough trouble with 0.8mm pitch and concave termination in the
beginning and a lot of pad-tuning had to be done. It turned out that the
manufacturer´s recommendations weren´t that bad at all (exept for the
excessive length of the pad, must have been for wavesoldering I guess).
Don´t think that a stepped stencil is necessary, it would make life more
complicated than necessary. Better control the amount of paste with the
aperture size.
Would be nice to have a test board with different layouts for that purpose,
wouldn´t it?
Good luck
Wolfgang
-----Ursprüngliche Nachricht-----
Von: Becerra Alejandro [mailto:[log in to unmask]]
Gesendet am: Mittwoch, 14. November 2001 15:42
An: [log in to unmask]
Betreff: [TN] Resistor Networks of 0.5 mm Pitch
Hello to All,
we are planning to start using resistor networks of 0.5 mm pitch
in a normal reflow soldering process. The boards are FR-4 with HASL coating.
Is there any special concern about this component?
So far the smallest resistor network that we are using is a 0.8 mm pitch.
Within my company it is being recommended a stepped stencil for this
component. Is this necessary?
Thanks,
Alejandro Becerra
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========================================================================Date: Thu, 15 Nov 2001 14:50:57 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Handling of moisture sensitive devices
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi Grant,
that´s the trouble with customer supplied components. If you don´t know the
history of that package and the devices in respect to moisture and open time
baking should be the way to go.
Your approach to get those parts in the normal workflow for MSD-parts using
drybacks and recording the history sounds reasonable and you should convince
your customer of the merits of these procedures. In future you may not have
to bake his components.
Good luck
Wolfgang
-----Ursprüngliche Nachricht-----
Von: Grant Emandien [mailto:[log in to unmask]]
Gesendet am: Donnerstag, 15. November 2001 10:16
An: [log in to unmask]
Betreff: [TN] Handling of moisture sensitive devices
Hi All,
I am seeking advice on handling methods of moisture sensitive devices from
reception/storage to use. Components have varying baking requirements after
the packaging has been opened - is baking performed as per. manufacturer's
instructions?
One of our customers is insistent on us, as an assembler to bake
(customer-supplied) components just prior to assembly - this approach
however does impose some impracticalities on production. Our initial counter
proposal is to receive only components in original OEM wrapping indicating
the moisture instructions and class/level and to then return bake and reseal
(vacuum/nitrogen) excess opened material to stores - the package would also
include a humidity indicator. Our proposal is more amenable to production,
but is it sufficient to ensure device integrity? Any insights on the
approach of assemblers?
TIA
Grant
**********************************************************************
Notice:
The information contained in this e-mail (including any attachments) may
contain commercially sensitive or confidential information which may be
legally privileged and is for the sole use of the intended recipient(s). If
you are not, or believe you may not be, the intended recipient, you are
hereby notified that any use, dissemination, copying, review, disclosure or
action taken in reliance of this e-mail is prohibited and may be unlawful.
If you have received this message in error, please notify the sender
immediately by reply e-mail and delete all copies of the message.
Any views expressed in this message are those of the individual sender
unless expressly stated by the sender to be given on behalf of Tellumat
(Pty) Ltd. Tellumat (Pty) Ltd disclaims liability for any unauthorised
opinion or representation made by the sender on behalf of Tellumat (Pty)
Ltd.
No warranty is given by Tellumat (Pty) Ltd that the integrity or security of
this e-mail (including any attachments) has been maintained through
transmission, nor that the communication is free of virus, interception or
interference.
**********************************************************************
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========================================================================Date: Thu, 15 Nov 2001 09:09:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Vivari, John" <[log in to unmask]>
Subject: Re: Reflow Solder balls
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C16DDF.3171BFD3"
This message is in MIME format. Since your mail reader does not understand
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------_=_NextPart_001_01C16DDF.3171BFD3
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Mike,
Quite a few remedies for various kinds of "solder balls" exist. Which is
appropriate depends upon what kind of "solder balls" you have. If you can
give me a description of what kind of paste you use (flux type and alloy),
where the balls are, and how big they are, I can narrow down what options
you have to correct your problem.
John Vivari
Technical Service Engineer
EFD Inc.
www.efd-inc.com
<mailto:[log in to unmask]>
Ph: 401-333-3800 x2204
Fx: 401-333-4954
Date: Wed, 14 Nov 2001 21:38:55 -0600
From: "Cowen, Mike" <[log in to unmask]>
Subject: Reflow Solder balls
I am looking for any information on the reduction of solder balls caused by
the reflow/printing process.
Any help or ideas would be greatly appreciated.
Michael Cowen
------_=_NextPart_001_01C16DDF.3171BFD3
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META NAME="Generator" CONTENT="MS Exchange Server version 5.5.2653.12">
<TITLE>Re: Reflow Solder balls</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=2 FACE="Courier New">Mike,</FONT>
</P>
<P><FONT SIZE=2 FACE="Courier New">Quite a few remedies for various kinds of "solder balls" exist. Which is appropriate depends upon what kind of "solder balls" you have. If you can give me a description of what kind of paste you use (flux type and alloy), where the balls are, and how big they are, I can narrow down what options you have to correct your problem.</FONT></P>
<P><FONT SIZE=2 FACE="Times New Roman">John Vivari</FONT>
<BR><FONT SIZE=2 FACE="Times New Roman">Technical Service Engineer</FONT>
<BR><FONT SIZE=2 FACE="Times New Roman">EFD Inc.</FONT>
<BR><U><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">www.efd-inc.com</FONT></U>
<BR><U><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman"><<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT></U><FONT SIZE=2 FACE="Times New Roman"> </FONT>
<BR><FONT SIZE=2 FACE="Times New Roman">Ph: 401-333-3800 x2204</FONT>
<BR><FONT SIZE=2 FACE="Times New Roman">Fx: 401-333-4954</FONT>
</P>
<BR>
<BR>
<BR>
<P><FONT SIZE=2 FACE="Courier New">Date: Wed, 14 Nov 2001 21:38:55 -0600</FONT>
<BR><FONT SIZE=2 FACE="Courier New">From: "Cowen, Mike" <[log in to unmask]></FONT>
<BR><FONT SIZE=2 FACE="Courier New">Subject: Reflow Solder balls</FONT>
</P>
<P><FONT SIZE=2 FACE="Courier New">I am looking for any information on the reduction of solder balls caused by</FONT>
<BR><FONT SIZE=2 FACE="Courier New">the reflow/printing process.</FONT>
<BR><FONT SIZE=2 FACE="Courier New">Any help or ideas would be greatly appreciated.</FONT>
</P>
<BR>
<P><FONT SIZE=2 FACE="Courier New">Michael Cowen</FONT>
</P>
</BODY>
</HTML>
------_=_NextPart_001_01C16DDF.3171BFD3--
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========================================================================Date: Thu, 15 Nov 2001 10:01:22 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Reflow Solder balls
MIME-Version: 1.0
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Hi Mike!
Here's a good link to go to:
http://www.amtechinc.com/solderballs.html
-Steve Gregory-
> I am looking for any information on the reduction of solder balls caused by
> the reflow/printing process.
> Any help or ideas would be greatly appreciated.
>
>
> Michael Cowen
>
--part1_163.3ec3858.292532c2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Mike!
<BR>
<BR>Here's a good link to go to:
<BR>
<BR>http://www.amtechinc.com/solderballs.html
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I am looking for any information on the reduction of solder balls caused by
<BR>the reflow/printing process.
<BR>Any help or ideas would be greatly appreciated.
<BR>
<BR>
<BR>Michael Cowen
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_163.3ec3858.292532c2_boundary--
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========================================================================Date: Thu, 15 Nov 2001 07:21:29 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wildes, Earl" <[log in to unmask]>
Subject: Re: Handling of moisture sensitive devices
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
The National Semiconductor web site has a nice application note about
handling of moisture sensitive devices. I believe Motorola has one also.
Would you happen to have any information about proper physical handling
surface mount parts? I need a guideline to give the stockroom for when
small quantities are issued to the line.
Earl Wildes
Sr. Component Engineer
Korry Electronics Co.
901 Dexter Ave N.
Seattle, WA 98109
206-694-1398
[log in to unmask]
-----Original Message-----
From: Grant Emandien [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 1:16 AM
To: [log in to unmask]
Subject: [TN] Handling of moisture sensitive devices
Hi All,
I am seeking advice on handling methods of moisture sensitive devices from
reception/storage to use. Components have varying baking requirements after
the packaging has been opened - is baking performed as per. manufacturer's
instructions?
One of our customers is insistent on us, as an assembler to bake
(customer-supplied) components just prior to assembly - this approach
however does impose some impracticalities on production. Our initial counter
proposal is to receive only components in original OEM wrapping indicating
the moisture instructions and class/level and to then return bake and reseal
(vacuum/nitrogen) excess opened material to stores - the package would also
include a humidity indicator. Our proposal is more amenable to production,
but is it sufficient to ensure device integrity? Any insights on the
approach of assemblers?
TIA
Grant
**********************************************************************
Notice:
The information contained in this e-mail (including any attachments) may
contain commercially sensitive or confidential information which may be
legally privileged and is for the sole use of the intended recipient(s). If
you are not, or believe you may not be, the intended recipient, you are
hereby notified that any use, dissemination, copying, review, disclosure or
action taken in reliance of this e-mail is prohibited and may be unlawful.
If you have received this message in error, please notify the sender
immediately by reply e-mail and delete all copies of the message.
Any views expressed in this message are those of the individual sender
unless expressly stated by the sender to be given on behalf of Tellumat
(Pty) Ltd. Tellumat (Pty) Ltd disclaims liability for any unauthorised
opinion or representation made by the sender on behalf of Tellumat (Pty)
Ltd.
No warranty is given by Tellumat (Pty) Ltd that the integrity or security of
this e-mail (including any attachments) has been maintained through
transmission, nor that the communication is free of virus, interception or
interference.
**********************************************************************
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========================================================================Date: Thu, 15 Nov 2001 10:42:57 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
MIME-Version: 1.0
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Hey Steve, for some reason IPC can't receive my e-mails. Could you post
this for me?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Marsico, James
Sent: Thursday, November 15, 2001 7:54 AM
To: 'Technet'
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board materials
(organic?) and design that can handle clock speeds up to 1GHz? Or another
question, what aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
--part1_156.40e4f23.29253c81_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey Steve, for some reason IPC can't receive my e-mails. Could you post
<BR>this for me?
<BR>
<BR>Thanks,
<BR>Jim Marsico
<BR>Senior Engineer
<BR>Production Engineering
<BR>EDO Electronics Systems Group
<BR>[log in to unmask] <mailto:[log in to unmask]>
<BR>631-595-5879
<BR>
<BR>
<BR>
<BR> -----Original Message-----
<BR> From: Marsico, James
<BR> Sent: Thursday, November 15, 2001 7:54 AM
<BR> To: 'Technet'
<BR> Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
<BR>
<BR> OK, here's another hi-tech topic...
<BR>
<BR> What's the latest and greatest in multilayer board materials
<BR>(organic?) and design that can handle clock speeds up to 1GHz? Or another
<BR>question, what aspects of the PWB affects signal speed?
<BR>
<BR> Thanks,
<BR> Jim Marsico
<BR> Senior Engineer
<BR> Production Engineering
<BR> EDO Electronics Systems Group
<BR> [log in to unmask] <mailto:[log in to unmask]>
<BR> 631-595-5879
<BR></FONT></HTML>
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========================================================================Date: Thu, 15 Nov 2001 09:37:07 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl Ray <[log in to unmask]>
Subject: Moisture Sensitive Devices
MIME-Version: 1.0
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I am running into situation where my customer has our purchasing
group to buy preprogrammed devices. Some of these devices are moisture
sensitive and suppliers are not very concerned about handling these
parts. Are there any standards for component manufactures/ distributors
to follow for handling of moisture sensitive devices?
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========================================================================Date: Thu, 15 Nov 2001 10:57:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Kovar Etching
MIME-Version: 1.0
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Etch conditions for Kovar are pretty much the same as Copper with Ferric
Chloride.
A lot of the small houses etch Iron based alloys first with Ferric Chloride,
then finish up etching Copper.
Usually you use 40+ Baume' Ferric Chloride, and the key issue is watching the
HCl, you keep it low to give you good "etch ratios", and higher to increase
speed.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Thu, 15 Nov 2001 11:02:13 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Leo Lambert <[log in to unmask]>
Subject: Re: Moisture Sensitive Devices
In-Reply-To: <[log in to unmask]>
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Hello there, yes there are documents related to moisture sensitive parts and
how they should be handled. IPC-JEDEC J-STD-033 Standard for Handling,
Packing, Shipping and Use of Moisture/Reflow Sensitive surface Mount
Devices. IPC also has the IPC-M-109 Guidelines Manual for Moisture Sensitive
Component Standards and guidelines Manual.
It is important to know how to handle these parts whether they come from the
supplier, distributors or have been in house for some period of time.
Labeling, packaging and baking procedures need to be followed to prevent
potential reliability problems down the road when the product is in use.
Hope this helps.
Leo Lambert
EPTAC Corp
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Carl Ray
Sent: Thursday, November 15, 2001 10:37 AM
To: [log in to unmask]
Subject: [TN] Moisture Sensitive Devices
I am running into situation where my customer has our purchasing
group to buy preprogrammed devices. Some of these devices are moisture
sensitive and suppliers are not very concerned about handling these
parts. Are there any standards for component manufactures/ distributors
to follow for handling of moisture sensitive devices?
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========================================================================Date: Thu, 15 Nov 2001 10:56:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Actuator Tabs falling off
We already run most of the assemblies that use this connector in meshed
baskets since the bds are too small ( approx 3"x3") ( tend to get knocked
around the wash when not in baskets) and are 1ups.
We have tried a slightly smaller mesh but did run into Ionic problems.
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========================================================================Date: Thu, 15 Nov 2001 17:33:09 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: ENIG-Black Pad
MIME-Version: 1.0
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I'm afraid that I have to disagree with Peter Duncan on his 'check the
phosphur content of the bath ' explanation. Phosphorus is codeposited with
the nickel at a concentration dependent on the rate of nickel deposition.
The percent phosphorus in the bath has no effect. The good processes
(compared to the ones prone to problems) control the nickel deposition rate
very carefully. The black pad is created by the immersion gold process,
which is a substitution reaction, and so has a corrosive attack on the
nickel. If the nickel deposit has too many crevices due to poor deposition,
or the gold reaction is too slow, then you end up with a phosphur rich
layer at the gold nickel interface (also known as black band), and this is
impossible to solder. Microsectioning the pad should show a 'toothache'
effect if you really do have black pad, and then you should talk to your
raw card supplier.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Zhu, Xiang [SMTP:[log in to unmask]]
Sent: 15 November 2001 05:18
To: [log in to unmask]
Subject: [TN] ENIG-Black Pad
Hello All,
I encounter a touch problem with ENIG (Electroless Nickel / Immersion Gold)
PCB in assembly process. This problem maybe so-called "Black Pad".
This problem happen on a ten layers RCC build-up PCB's uBGA pads. The BGA
pad on PCB is 0.4mm in diameter with 0.8mm pitch. On some BGA pads, there
are 6 mil laser via connecting layer 1 and layer 2 (via in pad).
In ICT station, detect this problem as open. When I remove the BGA wit hot
air, find some pads didn't wetted with solder at all and have a dark/black
appearance. I think the surface of black pad is passivated nickel.
I don't know what kind of source caused this defect and how to prevent it.
PCB vendor or our assembly process cause this problem?
Is there anybody who ever encounter this kind of problem? Please kindly
offer me a hand.
Thank you in advance for your kindly help!
Best regards,
Zhu Xiang
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========================================================================Date: Thu, 15 Nov 2001 09:51:18 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: PPM Monitoring and Benchmarking
In-Reply-To: <01e701c16c6a$f2cae180$0300a8c0@dell>
MIME-Version: 1.0
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Hi Bob,
From my own work in Manufacturing Engineering, the ppm (error opportunities)
data, as compared to first pass yield, is the most useful for controlling a
manufacturing operation. It removes from the equation the difference between
the great first pass yield results obtained with simple boards and not so
great results with complex boards and really showes how well the assembly
operation is running.
When ppm is used to describe the number of bad boards versus good boards
(often called first pass yield) you get a number that the enduser (or your
marketing manager) is somewhat interested in, because it has a strong
relationship to the quality of the end-product. As a user of an electronic
product I dont care how many components with how many legs are placed on how
many circuit board inside my video recorder, I want to know how well it
works as a unit.
As Manufacturing Engineer (and in my present case as a stencil maker) I like
to know how many print errors are observed when assembling boards, thus the
interest in the PPM (or PPMO) number.
From my experience, it is very hard to get such a number, as too few
companies collect such data. I know that some companies talk about and have
goals of 60 to as low as 30 ppm before they consider the results acceptable.
This is right in line with what seems to be the acceptable number to be
classified as World Class: <50ppmo. The best result I have feedback on for a
steel, lasercut stencil for regular and fine pitch components without
electro polishing: zero errors for a run of 1500 boards with about 5000
apertures. That shows that great results are at least possible, given good
design of apertures for the process and materials used.
Regards,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bob Willis
Sent: Tuesday, November 13, 2001 09:26
To: [log in to unmask]
Subject: [TN] PPM Monitoring and Benchmarking
Based on the SMART Group On-Line survey on defect monitoring, to date the
use of PPM Parts Per Million Monitoring is the most popular method which is
well covered in the IPC document see www.smartgroup.org
I have asked the question before but would engineers like to have an
average PPM level each month for screen print, component placement, reflow
and wave soldering to compare with their own production results. It would
have to be based on a known technology but could be valuable as a point of
reference for benchmarking. Its a little project we are considering over the
UK and would like to know its value to other engineers. I know there are
many issues but as long as everyone know what the data is, where it comes in
terms of board type NOT COMPANY and how its calculated I think it has a
value.
Please let me know your thoughts on the subject.
Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford Essex CM1 4HA
England
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
------=_NextPart_000_0063_01C16DBB.13C20980
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff size=2>Hi
Bob,</FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff size=2>From my
own work in Manufacturing Engineering, the ppm (error opportunities) data,
as compared to first pass yield, is the most useful for controlling a
manufacturing operation. It removes from the equation the difference between the
great first pass yield results obtained with simple boards and not so great
results with complex boards and really showes how well the assembly operation is
running.</FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff size=2>When
ppm is used to describe the number of bad boards versus good boards (often
called first pass yield) you get a number that the enduser (or your marketing
manager) is somewhat interested in, because it has a strong relationship to the
quality of the end-product. As a user of an electronic product I dont care
how many components with how many legs are placed on how many circuit board
inside my video recorder, I want to know how well it works as a
unit.</FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff size=2>As
Manufacturing Engineer (and in my present case as a stencil maker) I like
to know how many print errors are observed when assembling boards, thus the
interest in the PPM (or PPMO) number. </FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff size=2>From my
experience, it is very hard to get such a number, as too few companies collect
such data. I know that some companies talk about and have goals of 60 to as low
as 30 ppm before they consider the results acceptable. This is right in line
with what seems to be the acceptable number to be classified as World Class:
<50ppmo. The best result I have feedback on for a steel, lasercut stencil for
regular and fine pitch components without electro polishing: zero errors
for a run of 1500 boards with about 5000 apertures. That shows that great
results are at least possible, given good design of apertures for the process
and materials used.</FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff
size=2>Regards, </FONT></SPAN></DIV>
<DIV><SPAN class=75362118-13112001><FONT face=Arial color=#0000ff
size=2>Ahne.</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of</B> Bob Willis<BR><B>Sent:</B>
Tuesday, November 13, 2001 09:26<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> [TN] PPM Monitoring and
Benchmarking<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>
<DIV><FONT face=Arial size=2>
<DIV><FONT face=Arial size=2>Based on the SMART Group On-Line survey on defect
monitoring, to date the use of PPM Parts Per Million Monitoring is
the most popular method which is well covered in the IPC document see <FONT
face=Arial size=2><A
href="http://www.smartgroup.org">www.smartgroup.org</A></FONT></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I have asked the question before but would
engineers like to have an average PPM level each month for screen print,
component placement, reflow and wave soldering to compare with their own
production results. It would have to be based on a known technology but could
be valuable as a point of reference for benchmarking. Its a little project we
are considering over the UK and would like to know its value to other
engineers. I know there are many issues but as long as everyone know what the
data is, where it comes in terms of board type NOT COMPANY and how its
calculated I think it has a value.</FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Please let me know your thoughts on the
subject.</FONT> </DIV>
<DIV><FONT color=#0000ff></FONT> </DIV></FONT></DIV></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Bob Willis<BR>Electronic Presentation
Services<BR>2 Fourth Avenue<BR>Chelmsford Essex CM1 4HA<BR>England<BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) 01245
351502 Fax: (44) 01245 496123</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Single solution to your seminar, conference or
roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Thu, 15 Nov 2001 15:00:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Danny W. Harkins" <[log in to unmask]>
Subject: Glue stencils
MIME-Version: 1.0
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Hello all,
Need info on using a stencil to glue parts to bottom side of pcb for
wave soldering . Right now the only type parts to be glued are sot23,
0603-1206 components. What thickness stencil? What type of glue? Use bar
or dot apertures? I've been taught about part orientations and spacings
but what is really used in real life experiences? The wave we have has a
type of chip agitator built into the main wave if needed. I'm trying to
get enough information so as to know where to start in conducting some
designed experiments.
Thanks for your help in this matter.
Danny Harkins
CSI
[log in to unmask]
--=_alternative 006DBE7D85256B05_Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Hello all,</font>
<br>
<br><font size=2 face="sans-serif">Need info on using a stencil to glue parts to bottom side of pcb for wave soldering . Right now the only type parts to be glued are sot23, 0603-1206 components. What thickness stencil? What type of glue? Use bar or dot apertures? I've been taught about part orientations and spacings but what is really used in real life experiences? The wave we have has a type of chip agitator built into the main wave if needed. I'm trying to get enough information so as to know where to start in conducting some designed experiments.</font>
<br><font size=2 face="sans-serif">Thanks for your help in this matter.</font>
<br>
<br><font size=2 face="sans-serif">Danny Harkins</font>
<br><font size=2 face="sans-serif">CSI</font>
<br><font size=2 face="sans-serif">[log in to unmask]</font>
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========================================================================Date: Thu, 15 Nov 2001 15:42:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Hargreaves <[log in to unmask]>
Subject: IPC6014
MIME-Version: 1.0
Content-Type: text/plain
Hi All,
A customers drawing references IPC 6014, but I can't find it in my manuals.
Does it exist? What's it cover?
Many Thanks,
Mark Hargreaves
EMDS
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========================================================================Date: Thu, 15 Nov 2001 14:53:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Hunter, Brian C" <[log in to unmask]>
Subject: Pad Lifting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have data for peel strengths of copper pads on FR-4 PWBs of approximately
6 PSI. I believe this pertains to a tensile loading of the pad.
However, the pad lifting that we are getting appears to be from shear
loading. Therefore, what I'm looking for is the shear strength of copper
pads on FR-4.
Any help you can provide will be appreciated.
Thanks,
Brian
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========================================================================Date: Thu, 15 Nov 2001 17:13:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Re: IPC6014
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
See IPC-6011 of the IPC-6010 series for generic standards for printed
circuit/printed wiring boards.
IPC-6014 is Qualification and Performance Specifications for PCMCIA Boards
(bare boards). Would be good to have a copy of the 6011 to use in
conjunction with 6014.
Also see the IPC website, http://www.ipc.org to purchase specs.
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
Mark
Hargreaves To: [log in to unmask]
<[log in to unmask] cc:
OM> Subject: [TN] IPC6014
Sent by:
TechNet
<[log in to unmask]
ORG>
11/15/01
03:42 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hi All,
A customers drawing references IPC 6014, but I can't find it in my manuals.
Does it exist? What's it cover?
Many Thanks,
Mark Hargreaves
EMDS
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========================================================================Date: Thu, 15 Nov 2001 14:27:06 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Pad Lifting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
i believe that value is pounds per inch width not psi.
phil
-----Original Message-----
From: Hunter, Brian C [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 1:53 PM
To: [log in to unmask]
Subject: [TN] Pad Lifting
I have data for peel strengths of copper pads on FR-4 PWBs of approximately
6 PSI. I believe this pertains to a tensile loading of the pad.
However, the pad lifting that we are getting appears to be from shear
loading. Therefore, what I'm looking for is the shear strength of copper
pads on FR-4.
Any help you can provide will be appreciated.
Thanks,
Brian
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========================================================================Date: Thu, 15 Nov 2001 16:24:32 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mike Manwell <[log in to unmask]>
Subject: WaveSolder Process Monitoring Tools
Does anyone know of profiling devices or tools that you run through a
wavesolder machine that will capture preheat temperature & wave height?
Thanks,
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========================================================================Date: Thu, 15 Nov 2001 18:00:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: WaveSolder Process Monitoring Tools
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I believe the ECD WaveRider and the TIC Wave Solder Optimizer do this.
http://www.ecd.com/downloads/emfg/DataShts/WaveRider.pdf
http://www.techinfocorp.com/wso.htm
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
> Sent: Thursday, November 15, 2001 5:25 PM
> To: [log in to unmask]
> Subject: [TN] WaveSolder Process Monitoring Tools
>
>
> Does anyone know of profiling devices or tools that you run through a
> wavesolder machine that will capture preheat temperature & wave height?
> Thanks,
>
> ------------------------------------------------------------------
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========================================================================Date: Thu, 15 Nov 2001 18:20:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Crain <[log in to unmask]>
Subject: Re: WaveSolder Process Monitoring Tools
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
We just finished testing a tool that does all that you mentioned. It was
called the 'Wave Solder Opitmizer.'
The company gave a lot of customer support and plenty of material to read
through. We thought it was a useful tool for monitoring the wave solder
process.
> g
GE Energy Services
______________________
Peter Crain
Manufacturing Engineering
Substation Automation Solutions
GE Harris Energy Control Systems Canada, Inc.
2728 Hopewell Place N.E., Calgary, Alberta T1Y 7J7 CANADA
Tel: 403.214.4560, Dialcomm: 8.498.4560, Fax: 403.214.4776
Website: www.gepower.com/geharrisenergy/
NOTICE: The information contained in this e-mail is privileged,
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-----Original Message-----
From: Mike Manwell [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 3:25 PM
To: [log in to unmask]
Subject: [TN] WaveSolder Process Monitoring Tools
Does anyone know of profiling devices or tools that you run through a
wavesolder machine that will capture preheat temperature & wave height?
Thanks,
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========================================================================Date: Fri, 16 Nov 2001 07:56:58 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Moisture Sensitive Devices
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
J-STD-020 and J-STD-033 are teh main specs for packaging, handling and
controlling MSD's.
Peter Duncan
Carl Ray
<carl.ray@SAN To: [log in to unmask]
MINA.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Moisture Sensitive Devices
<[log in to unmask]
ORG>
11/15/01
11:37 PM
Please
respond to
"TechNet
E-Mail
Forum."
I am running into situation where my customer has our purchasing
group to buy preprogrammed devices. Some of these devices are moisture
sensitive and suppliers are not very concerned about handling these
parts. Are there any standards for component manufactures/ distributors
to follow for handling of moisture sensitive devices?
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========================================================================Date: Thu, 15 Nov 2001 18:15:13 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mike Manwell <[log in to unmask]>
Subject: Conformal Coating to IPC Class 3
When I read IPC Standards regarding conformal coating requirements for the
different classes, all I can find is coating thickness on a board.
I'm trying to work to class 3 standards for conformal coating and am
meeting those thickness requirements, however, I have to wonder how it
works on a BGA for example, where the coating thickness is sufficient but
doesn't completely cover and encapsulate the component. In other words,
there is a gap between the top of the BGA and the PCB.
Any thoughts on this would be appreciated.
Thanks,
Mike Manwell
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========================================================================Date: Thu, 15 Nov 2001 19:23:38 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Component Charactristics
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi All,
I need to get some information on various components to do a proper analysis
for actual solder reflow profiling needs.
I am interested in components with the largest variation in thermal masses,
e.g., 0603 CC, 1803 CC, 44 I/O PQFP, 100 I/O PBGA, 400 I/O PBGA, 400 I/O
SBGA, 100 I/O CBGA, 400 I/O CBGA, etc.
What I am looking for are the dimensions, volume, weight, and for the
component packages how much of the volume/weight is ceramic, metal(s),
silicon, plastic, exposed heat transfer areas, thermal mass, etc.
Given the large differences in thermal mass, and the higher reflow
temperatures necessary for lead-free solders, the temperature differences at
the reflow peaks are likely to become very important.
Of course, if any of you have done studies in this direction, I would like to
get a copy of these if at all possible.
Thanks,
Werner Engelmaier
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========================================================================Date: Fri, 16 Nov 2001 10:11:16 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
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========================================================================Date: Fri, 16 Nov 2001 10:26:15 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dear All,
I have another problem for you PCB Fab guru's. The sister board to the
warped one of my previous posting has the problem of being over-etched in
some areas. Some pads are half the width they should be. It is 12 layer,
ENIG finished, with 3 different blind via depths from the bottom of the
board and two from the top, as well as the through-hole group. They are
laminated conventionally - i.e. each blind group is laminated. drilled and
plated before lamination for the next hole group, and so on, so there is
considerable variance in surface copper weight by the time the board is
fully laminated.
Our fab house tried remaking the boards by laminating the entire board at
once, then laser drilling to depth and plating. The result was a total
failure, and once again we're faced with a re-make using the previous
processes.
Does anyone know how we can reduce the variance in surface copper weight
such that, in final etch, there isn't such a poor compromise between
getting the widths and spacings of the heavier copper areas right, without
over-etching the lighter copper areas? I tentatively suggested selective
masking of some kind for the areas already plated, but I have no idea if
that's feasible or not. How do other fab houses deal with this situation?
Thanks as ever for your invaluable help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
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========================================================================Date: Fri, 16 Nov 2001 10:32:05 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Zhu, Xiang" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Please check you design first. If this design have an uneven copper pattern
/ stack-up/ soldermask thickness, the warpage is very hard to avoid. My
suggestion is use a fixture to force the board come back to flat in
assembly. But, please take care about the potential tension strength after
fixture removal, for tension will cause BGA solder joint crack.
Good Luck!
Ben
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 10:11
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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========================================================================Date: Fri, 16 Nov 2001 10:45:51 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Zhu, Xiang" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Typically, expensive machine can make it.
Like horizontal pulse plating / horizontal scrub, etc. In a word, the
traditional sequential lamination process can have a favorable result only
by good/expensive machine. Try to ask biggest fab house build the board for
you!
Ben
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 10:26
To: [log in to unmask]
Subject: [TN] Over-etch
Dear All,
I have another problem for you PCB Fab guru's. The sister board to the
warped one of my previous posting has the problem of being over-etched in
some areas. Some pads are half the width they should be. It is 12 layer,
ENIG finished, with 3 different blind via depths from the bottom of the
board and two from the top, as well as the through-hole group. They are
laminated conventionally - i.e. each blind group is laminated. drilled and
plated before lamination for the next hole group, and so on, so there is
considerable variance in surface copper weight by the time the board is
fully laminated.
Our fab house tried remaking the boards by laminating the entire board at
once, then laser drilling to depth and plating. The result was a total
failure, and once again we're faced with a re-make using the previous
processes.
Does anyone know how we can reduce the variance in surface copper weight
such that, in final etch, there isn't such a poor compromise between
getting the widths and spacings of the heavier copper areas right, without
over-etching the lighter copper areas? I tentatively suggested selective
masking of some kind for the areas already plated, but I have no idea if
that's feasible or not. How do other fab houses deal with this situation?
Thanks as ever for your invaluable help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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========================================================================Date: Thu, 15 Nov 2001 21:11:36 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Board Warp
X-To: "<Peter George Duncan>" <[log in to unmask]>
This is exactly the type thing making DMF/CE disregarded and impossible.
What everyone is (seems to be) doing is violating all design principles and
whatever rules/standards are known to the PCB/MLB world just to get product
to market without thought of how many times you all must do it over again
and again and again. This includes MLB structures and plating processes.
When are you all going to attempt seeing from the concept to the finished
product?
Many continually ask questions about how can "I" fix something that could
have been prevented in the first place - at the design level using DFM/CE.
How can you ask questions about making boards flatter after lamination? It
cannot be done if the design, material selections, and fab processes are out
of control. How can one even ask about etch? It's something that's been
going on far too long and it's time you all stopped and started doing it
right the first time.
Unbelievable,
MoonMan
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========================================================================Date: Thu, 15 Nov 2001 22:53:48 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: Handling of moisture sensitive devices
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Dear Grant,
I believe you are on the right path by wanting to avoid systematically
baking incoming components. You should bring up the concern that excessive
bake will impact component solderability and intermetallic growth.
If you are interested to get additional information on this subject you can
check the knowledge base on our web site at www.cogiscan.com, click on
Moisture Sensitive Devices. It contains many technical papers that you might
find useful.
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
Date: Thu, 15 Nov 2001 11:15:47 +0200
From: Grant Emandien <[log in to unmask]>
Subject:
Hi All,
I am seeking advice on handling methods of moisture sensitive devices from
reception/storage to use. Components have varying baking requirements after
the packaging has been opened - is baking performed as per. manufacturer's
instructions?
One of our customers is insistent on us, as an assembler to bake
(customer-supplied) components just prior to assembly - this approach
however does impose some impracticalities on production. Our initial counter
proposal is to receive only components in original OEM wrapping indicating
the moisture instructions and class/level and to then return bake and reseal
(vacuum/nitrogen) excess opened material to stores - the package would also
include a humidity indicator. Our proposal is more amenable to production,
but is it sufficient to ensure device integrity? Any insights on the
approach of assemblers?
TIA
Grant
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========================================================================Date: Thu, 15 Nov 2001 21:51:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Handling of moisture sensitive devices
X-To: Francois Monette <[log in to unmask]>
Thank you. Outstanding! Keep it simple in accordance with what works. It's
all spelled out.
MoonMan
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========================================================================Date: Thu, 15 Nov 2001 23:08:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Kick my butt if you wish
Had to reply to someone, and many others, I respect very much:
> Wow! Seems like I hit the high pressure setting on Moonman's boiler.
Ah Peter, I never reach such a High PREssure SETTing ON MY BOILER. My relief
valve is set on low - depending on paycheck size and how well I do (often
overpaid and ineffective). Hell, you never see me getting so outraged that I
LOOSE CONTROL.
You asked a great question understanding it was asked under extreme duress
at the back end of a completed process in a place and society,
notwithstanding technical culture, I have seldom visited. How could I, or
anyone else, get pissed about that - so don't be embarrased? Love you babe!
I make way too much money correcting that which is unfixable. Simply, it's
what I do after having found, or finding me, so many needing this stuff.
You, and so many others including Zhu, ask so many questions having been
answered so many times before. I love you babe for asking these questions
over again knowing all the while you have the answers but have to work for
those not knowing You have provided so many answers as well though more
complex questions need answers and are not proven even in IPC standards,
guidelines, and specifications. I'm writing a book on that very matter. So
what!
You have the same responsibilities as me. You have to ask the questions, as
me, having been provided by you, WE, PH, GC, SZ, MM, and all the others
having given so much free time to all these issues - on and off line.
The bottom line is there are no embarrassing questions just as as there are
no communication lines too long. IPC, and others, have made it too simple.
Added to that, many free givers, as Werner, Steve, Phil, and all, have
already given all the answers. How hard can it be? Amazingly, it gets much
harder as designs get more complex.
DFM/CE is alien to almost everyone but those few really practicing it. I
only know a few.
It is what technocratic dreams are made of but not fully realized. Those
practicing it, are fulfilled with a sense of knowing how easy it can be.
Those not, ask questions like how to overcome 100% inspection with a
sampling plan when their suppliers are out of control or their designs suck.
Certainly they ask because there is no design/process compatibility. There's
not DFM/CE.
Again, for me, I make a living attempting to assure this "dream" is
realized. It's good money, but little satisfaction. It's better giving it
away here than getting paid for it in BF Montana with my social club, or
wherever/whatever.
Again and again I love you babe as desparate as you may be. Been there, done
that, still feeling as you. However, the designs can't be that good without
DFM/CE.
MoonMan who cares about you
It was
> a horribly embarrassing question I asked, I know, but I'm just the poor
> sucker who has to work with the end result. The warp fault appears to be
> with one fab house, and its sister board's etch problem came from another
> fab house. They're both in CA while I'm in Singapore, so lines of
> communication are long, and we don't seem to have fab houses in this
region
> certified to produce class 3 boards over about 8 layers (please stand up
if
> you are out there and can do 12 layer class 3's with blind vias, and are
> IPC-6012 certified).
>
> The boards are FR4/26, and the design is well balanced in terms of copper
> distribution. They are the first boards we've done with blind vias, and
the
> fab house we've mostly used to date has been pretty reliable. When they
> said that they could produce the boards, we had no reason to doubt them.
>
> I've been with this company for only a few months, and DFM/CE is an alien
> concept at the moment. I have busted several blood vessels trying to get
> the DFM/CE idea and practice across, but have you ever been one man trying
> single handedly to move a battleship? The inertia takes a bit of breaking,
> and the culture is well different from The West, too. However, they do
know
> how to design and lay out boards, even if they could use something better
> (but more expensive) than FR4.
>
> If I weren't desperate, d'ya think I'ld even ask such a question?
>
> Kind regards
>
> Peter Duncan
>
>
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========================================================================Date: Fri, 16 Nov 2001 01:13:57 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Over-etch
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Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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========================================================================Date: Fri, 16 Nov 2001 15:37:04 +0800
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From: Shine Wang-0337CE <[log in to unmask]>
Subject: solderability
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who can tell me about how to do a solderability test?
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========================================================================Date: Fri, 16 Nov 2001 16:04:10 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
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Hi, Rudy,
The boards are ENIG finished, the ENIG plating being carried out
post-solder-mask, which must be after final copper etch, so No, there is no
other metal in the area, unless my understanding of the plating/etching
sequence is all wrong. My understanding (faulty or otherwise) of what the
fab house has done, is that they laminate, drill and plate the layers with
the first suite of blind vias, then laminate, drill and plate for the
second suite of blind vias, then again for the 3rd suite until everything
is stacked up, pressed, drilled and plated for the through-holes. I haven't
quite been able to make sense of it all yet, but I think what I'm being
told is that the plating becomes "stepped" somehow. I have 3 sets of blind
vias from each outer surface (for ease of argument), making 4 plating
sessions on each side by the time the through-hole group is done. The first
areas to be drilled and plated are therefore plated 4 times, while the last
areas to be drilled are only plated once, with the groups in between
getting their proportional share of multiple plating.
Thus at final etch, there is, I am told, a compromise to be reached - how
to achieve the correct widths and spacings on the heavily plated areas
without over-etching the lightly-plated areas. In my simple way, I would
have expected the entire board surface to have an even plating thickness,
however thick, but seemingly not. The compromise hasn't worked for the
number of blind via groups featured in this board, and I need to try to
find out how to address a solution without solely relying on what our fab
house tells me.
In my entire life, I never had to worry about the processes involved in
fabricating PCB's - only that components could be soldered to them, that
they passed test and proved to be reliable in the field. I only ever worked
with good boards - the ones that passed in-coming inspection - in an
assembly environment, so my experience of board design and PCB fab is
limited to the past 8 or 9 months, in a company that has no previous
convictions for designing this type of board, so it's a case of the blind
leading the blind to a certain extent.
Any further help in this area would be greatly appreciated.
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch
ORG>
11/16/01
02:13 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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========================================================================Date: Fri, 16 Nov 2001 00:25:07 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: BGA voids
In-Reply-To: <[log in to unmask]>
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Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I've observed (with Xray) contribute to as high
as 60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at
the joint. I also inspected the PCB lands and didn't see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
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<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><!-- Converted from text/rtf format -->Hello,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'>I am encountering voids after <span class=SpellE>reflow</span>
on several micro <span class=SpellE>BGAs</span> on one PCA product. The voids
that I’ve observed (with <span class=SpellE>Xray</span>) contribute to as
high as 60-70% of the joint area. My <span class=SpellE>reflow</span> profile
was designed by running a sample board with dummy components and <span
class=SpellE>thermalcouples</span> attached right at the joint. I also inspected
the PCB lands and didn’t see any via on pad.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'>Does anyone know the possible reasons for voids formation in
BGA (micro) <span class=SpellE>reflow</span>? <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'>In general, in step by step how would one trouble shoot such
a defect? <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><span class=SpellE><font size=3 color=navy face=SimSun><span
style='font-size:12.0pt;color:navy'>Rgds</span></font></span><font color=navy><span
style='color:navy'>,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'>Peter <span style='mso-spacerun:yes'> </span><o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
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<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 color=navy face=SimSun><span style='font-size:
12.0pt;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=3 face=SimSun><span style='font-size:12.0pt'><span
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========================================================================Date: Fri, 16 Nov 2001 16:34:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: BGA voids
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We have meet the same problem in one product , but the rootcause is the
via on the pad .Attachment is our report ,it may help to you
Regards
Tony Zhang <<clio-bga hole.xls>>
> -----Original Message-----
> From: Peter Lee [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 8:25 AM
> To: [log in to unmask]
> Subject: [TN] BGA voids
>
> Hello,
>
> I am encountering voids after reflow on several micro BGAs on one PCA
> product. The voids that I've observed (with Xray) contribute to as
> high as 60-70% of the joint area. My reflow profile was designed by
> running a sample board with dummy components and thermalcouples
> attached right at the joint. I also inspected the PCB lands and didn't
> see any via on pad.
>
> Does anyone know the possible reasons for voids formation in BGA
> (micro) reflow?
>
> In general, in step by step how would one trouble shoot such a defect?
>
>
> Rgds,
> Peter
>
>
>
>
>
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<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">We have meet the same problem in one product , but the rootcause is the via on the pad .Attachment is our report ,it may help to you</FONT></SPAN></P>
<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Regards </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Tony Zhang<FONT FACE="SimSun" SIZE=2 COLOR="#000000"> <<clio-bga hole.xls>> </FONT></FONT></SPAN>
</P>
<UL>
<P><SPAN LANG="en-us"><FONT SIZE=1 FACE="Arial">-----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">From: </FONT></B> <FONT SIZE=1 FACE="Arial">Peter Lee [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Sent: </FONT></B> <FONT SIZE=1 FACE="Arial">Friday, November 16, 2001 8:25 AM</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">To: </FONT></B> <FONT SIZE=1 FACE="Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Subject: </FONT></B> <FONT SIZE=1 FACE="Arial"> [TN] BGA voids</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">Hello,</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">I am encountering voids after reflow on several micro BGAs on one PCA product. The voids that I’ve observed (with Xray) contribute to as high as 60-70% of the joint area. My reflow profile was designed by running a sample board with dummy components and thermalcouples attached right at the joint. I also inspected the PCB lands and didn’t see any via on pad.</FONT></SPAN></P>
<P><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">Does anyone know the possible reasons for voids formation in BGA (micro) reflow?</FONT> </SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">In general, in step by step how would one trouble shoot such a defect?</FONT> </SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">Rgds</FONT><FONT COLOR="#000080" FACE="SimSun">,</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="SimSun">Peter</FONT> <FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#000080" FACE="Courier New"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT FACE="Courier New"> </FONT></SPAN>
</P>
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========================================================================Date: Fri, 16 Nov 2001 16:52:53 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA voids
MIME-Version: 1.0
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Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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========================================================================Date: Fri, 16 Nov 2001 06:18:27 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Over-etch
X-To: "<Peter George Duncan>" <[log in to unmask]>
Peter and other folks,
This board sounds just like Ervin's. He first posted at #59 on the subject.
Lot of this stuff going round these days. He posted something very important
to us all to consider just as has Peter. Interesting!
A question for all, based on the above, concerning a neat, according to me,
article written on the subject of virtual plating. It appeared in last
month's issue of Circuit Tree. It was in one of those special sections of
the mag.
Has anyone read the virtual plating article? If so, what do you think?
It speaks to issues concerning the ability to "plate" a board with data
contained in Gerber or ODB++, using a software package rendering images on
screen. The images, essentially, represent areas on a boards surface where
high or low plating thicknesses would be processed in the real tanks. It
allows, again in my terms, a shop to make "masks" that are placed over the
board's surface before being processed. The "masks" prevent over or under
plating to ensure specified consistency in all holes and across surfaces.
I would appreciate knowing if anyone has read this exciting prospect.
Moreover, I sure would like to know if anyone has taken the step converting
the virtual process into reality.
Earl Moon
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========================================================================Date: Fri, 16 Nov 2001 08:04:41 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "S. Miller" <[log in to unmask]>
Subject: Board Warpage/CEM-1 Material
MIME-Version: 1.0
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I am currently being supplied S/S technology on CEM-1 material from a variety
of suppliers and regardless of origin, they all exhibit a slight warpage.
My questions are twofold; is warpage indigenous of CEM-1 material and what
could I do to minimize it.
Any feedback would be truly appreciated.
Regards,
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I am currently being supplied S/S technology on CEM-1 material from a variety of suppliers and regardless of origin, they all exhibit a slight warpage.
<BR>
<BR>My questions are twofold; is warpage indigenous of CEM-1 material and what could I do to minimize it.
<BR>
<BR>Any feedback would be truly appreciated.
<BR>
<BR>Regards,</FONT></HTML>
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========================================================================Date: Fri, 16 Nov 2001 08:15:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
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Not having seen any other responses to this posting I will take a *SWAG* at
it.
1) The clock speed is not the most damning part of the "high speed design"
problem. Look at the rise time of the primary signals on the board and
convert that in to frequency. Your speed issue is probably much worse than
you think.
2) The material properties that you need to be concerned about are the
dielectric constant (variable for FR4) and the loss tangent. The loss
tangent of the material becomes especially important when working with low
level signals and narrow noise to signal ratios.
3) There are several levels of solution you can explore to get out of FR4
and in to a more stable material. The first are the PPO materials like
GeTek. They are an epoxy-glass material with the resin being highly
modified, to improve electrical and temperature performance. Next there are
the co-laminates like Speedboard N and C, prepreg only, which are used to
create a better final laminated board. Next in line would be the more exotic
ceramic-filled thermoplastics like Roger's RO4003/4350 materials.
Good Luck
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 10:43 AM
To: [log in to unmask]
Subject: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Hey Steve, for some reason IPC can't receive my e-mails. Could you post
this for me?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Marsico, James
Sent: Thursday, November 15, 2001 7:54 AM
To: 'Technet'
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board materials
(organic?) and design that can handle clock speeds up to 1GHz? Or another
question, what aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN classƒ3455712-16112001><FONT color=#0000ff>Not having seen any
other responses to this posting I will take a *SWAG* at it.</FONT></SPAN></DIV>
<DIV><SPAN classƒ3455712-16112001><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN classƒ3455712-16112001><FONT color=#0000ff>1) The clock speed
is not the most damning part of the "high speed design" problem. Look at the
rise time of the primary signals on the board and convert that in to frequency.
Your speed issue is probably much worse than you think.</FONT></SPAN></DIV>
<DIV><SPAN classƒ3455712-16112001><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN classƒ3455712-16112001><FONT color=#0000ff>2) The material
properties that you need to be concerned about are the dielectric constant
(variable for FR4) and the loss tangent. The loss tangent of the material
becomes especially important when working with low level signals and narrow
noise to signal ratios.</FONT></SPAN></DIV>
<DIV><SPAN classƒ3455712-16112001><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN classƒ3455712-16112001><FONT color=#0000ff>3) There are several
levels of solution you can explore to get out of FR4 and in to a more stable
material. The first are the PPO materials like GeTek. They are
an epoxy-glass material with the resin being highly modified, to improve
electrical and temperature performance. Next there are the co-laminates
like Speedboard N and C, prepreg only, which are used to create a
better final laminated board. Next in line would be the more exotic
ceramic-filled thermoplastics like Roger's RO4003/4350
materials.</FONT></SPAN></DIV>
<DIV><SPAN classƒ3455712-16112001><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN classƒ3455712-16112001><FONT
face=Arial>Good Luck</FONT></SPAN></DIV>
<DIV><SPAN classƒ3455712-16112001></SPAN> </DIV>
<DIV><SPAN classƒ3455712-16112001></SPAN>
<P><I><FONT face="Comic Sans MS" color=#008080 size=5>Jeffrey A. McGlaughlin
CID</FONT></I></P>
<P><SPAN classƒ3455712-16112001><FONT face=Arial size=2>Sr.
Designe</FONT></SPAN><SPAN classƒ3455712-16112001><FONT face=Arial
size=2>r</FONT></SPAN> <BR><FONT face=Arial size=2>Battelle Memorial
Institute</FONT> <BR><FONT face=Arial size=2>Columbus Ohio</FONT> <BR><FONT
face=Arial size=2>[log in to unmask]</FONT> </P> </DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, November 15, 2001 10:43
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] PWB MATERIALS,
DESIGNS AND TECHNOLOGY<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT
size=2>Hey Steve, for some reason IPC can't receive my e-mails. Could
you post <BR>this for me? <BR><BR>Thanks, <BR>Jim Marsico <BR>Senior Engineer
<BR>Production Engineering <BR>EDO Electronics Systems Group
<BR>[log in to unmask] <mailto:[log in to unmask]>
<BR>631-595-5879
<BR><BR><BR><BR> -----Original
Message----- <BR> From:
Marsico, James
<BR> Sent: Thursday, November
15, 2001 7:54 AM <BR> To:
'Technet'
<BR> Subject: PWB
MATERIALS, DESIGNS AND TECHNOLOGY
<BR><BR> OK, here's another hi-tech
topic... <BR><BR> What's the latest
and greatest in multilayer board materials <BR>(organic?) and design that can
handle clock speeds up to 1GHz? Or another <BR>question, what aspects of
the PWB affects signal speed?
<BR><BR> Thanks,
<BR> Jim Marsico
<BR> Senior Engineer
<BR> Production Engineering
<BR> EDO Electronics Systems Group
<BR> [log in to unmask]
<mailto:[log in to unmask]>
<BR> 631-595-5879
<BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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========================================================================Date: Fri, 16 Nov 2001 07:52:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: [log in to unmask]
Subject: Re: Conformal Coating to IPC Class 3
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When I read IPC Standards regarding conformal coating requirements for the
different classes, all I can find is coating thickness on a board.
**Mike, I feel your pain. You can find the materials requirements, the
minimum that conformal coating materials must do, in IPC-CC-830. The B
revision should be released in the next few months. That is primarily a
materials procurement or qualification document. The two standards dealing
with coating after it is put on are IPC-A-610 and J-STD-001. Both
documents boil down to the same thing: put coating down where the drawing
says, keep coating off where it ain't supposed to be, and make sure the
coating film has a certain thickness and a certain quality, i.e. no
pinholes, cracks wrinkles, etc. It is left to the user to determine what a
coating needs to do for their hardware. You might find some more insight
if you look at the latest draft of the Conformal Coating Handbook, which
should be nearing publication.
I'm trying to work to class 3 standards for conformal coating and am
meeting those thickness requirements, however, I have to wonder how it
works on a BGA for example, where the coating thickness is sufficient but
doesn't completely cover and encapsulate the component. In other words,
there is a gap between the top of the BGA and the PCB.
**Thicknesses are measured on a flat unencumbered surface, not on just any
surface on the board. You may have the minimum 2 mils of acrylic coating
on the board, but it won't be that thick on sharp component edges, or tops
of components, and certainly not on the underside of the components. The
only coating that will get the bottom side of components is
paralene/parylene/paralyne (I never can remember which one is right).
Any thoughts on this would be appreciated.
**If'n ya want, give me response off-line if there was something more
specific you need.
Doug Pauls
Rockwell Collins
"Conformal Coating - The Great Career Limiting Move"
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========================================================================Date: Fri, 16 Nov 2001 08:53:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
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Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have nothing
to do!
Removing warp is actually rather simple, and is an IPC documented procedure.
I've attached a link to our online procedure with more details. We find that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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========================================================================Date: Fri, 16 Nov 2001 08:03:30 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeffery,
I certainly apreciate your posting as a reminder to me as well. I would add,
from a DFM point of view concerning materials and their processing:
Getek has good electrical properties, as you say, but processing and some
results associated with it can be dissapointing. This material must be
processed more along the lines of polyimide. It requires a more damanding
press cycle than those for FR4 types using simple straight up processing
from 0 to 90 minutes or so. Therefore, not all shops like or do well with it.
The Rogers and Arlon (liscensed from Rogers but with slight variations
concerning properties) material is really neat stuff. It has processing
drawbacks as well as being limited in prepreg glass styles and thicknesses
when reinforced. If improperly processed, as with any material type, it has
several failing characteristics. As is widely known, this type material
often is married/laminated to Getek to meet design and performance
requirements. Really low DC and loss tangents.
My money is on BT epoxy blends when and where possible. It has high
performance characteristics and is easily processed. I have designed it in
and used in in very complex, large, high layer count MLB's with great
success. It is/was used in some Cray designs built by IBM, as one example.
Just wanted to add to your good comments,
MoonMan
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========================================================================Date: Fri, 16 Nov 2001 08:23:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: solderability
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I would suggest the IPC-TM-650. There are several test methods listed there.
Kathy
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<DIV>I would suggest the IPC-TM-650. There are several test methods listed
there. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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========================================================================Date: Fri, 16 Nov 2001 08:33:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Board Warp
X-To: Jeff Ferry <[log in to unmask]>
Jeff,
Meant in the kindess possible way, us DFM/CE fanatics would love to put you
folks out of business knowing full well YOU could do anything else very
well, as well. Well damn!
Earl
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========================================================================Date: Fri, 16 Nov 2001 10:17:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: OA & LCCs
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We are looking to mount a GPS receiver that is constructed similar to an LCC
type package. That is, it is an FR-4 board with gold terminations on the
side. These terminations also wrap under the board about .035". The
underside of the board has traces covered with soldermask. Has anybody ever
used a package such as this with water soluble flux cleaned with DI water
(we have an in-line system)? When soldered, there is virtually no standoff
of the receiver. Is there a danger of flux being trapped underneath and
causing potential problems? Or is this a non-issue. I am thinking that
resistors and capacitors have terminations that wrap underneath and they do
not seem to be a problem. Thanks.
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
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========================================================================Date: Fri, 16 Nov 2001 09:15:12 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ashok Dhawan <[log in to unmask]>
Subject: Re: WaveSolder Process Monitoring Tools
In-Reply-To: <[log in to unmask]>
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I am using Wave Optimizer supplied by ECD. There could be other suppliers as
well.
Ashok Dhawan P.Eng.
Engineering
C-MAC Network Systems Inc.
1455 Mountain Roar
Winnipeg Manitoba R2X 2Y9
WWW.CMAC.COM
TEL (204) 631 7208
FAX (204) 631 7294
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
> Sent: Thursday, November 15, 2001 4:25 PM
> To: [log in to unmask]
> Subject: [TN] WaveSolder Process Monitoring Tools
>
>
> Does anyone know of profiling devices or tools that you run through a
> wavesolder machine that will capture preheat temperature & wave height?
> Thanks,
>
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========================================================================Date: Fri, 16 Nov 2001 10:23:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Over-etch II
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This MAY be so simple, we will wonder why/how they did not see the problem...
To understand this analysis/suggestion, you have to understand the difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a similar
design? (In other words, is the problem one of process/board design, or one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Fri, 16 Nov 2001 10:28:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
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Peter,
I'm probably out of my league here, but the board house may be able to
compensate somewhat with "etch compensation", adding copper width where the
most etching will take place. If you know you're going to lose 2 or 3 mils
[.05-.08mm] per side in the final etch, add on copper before the
lam/drill/plate processes to get what you want. Check with your supplier
to see if this would work. I know this doesn't help you with this board
now, but may fix future problems. Time for Tums...(or Rolaids, Ativan,
Guinness, etc.).
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
"<Peter
George To: [log in to unmask]
Duncan>" cc:
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/16/01
03:04 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi, Rudy,
The boards are ENIG finished, the ENIG plating being carried out
post-solder-mask, which must be after final copper etch, so No, there is no
other metal in the area, unless my understanding of the plating/etching
sequence is all wrong. My understanding (faulty or otherwise) of what the
fab house has done, is that they laminate, drill and plate the layers with
the first suite of blind vias, then laminate, drill and plate for the
second suite of blind vias, then again for the 3rd suite until everything
is stacked up, pressed, drilled and plated for the through-holes. I haven't
quite been able to make sense of it all yet, but I think what I'm being
told is that the plating becomes "stepped" somehow. I have 3 sets of blind
vias from each outer surface (for ease of argument), making 4 plating
sessions on each side by the time the through-hole group is done. The first
areas to be drilled and plated are therefore plated 4 times, while the last
areas to be drilled are only plated once, with the groups in between
getting their proportional share of multiple plating.
Thus at final etch, there is, I am told, a compromise to be reached - how
to achieve the correct widths and spacings on the heavily plated areas
without over-etching the lightly-plated areas. In my simple way, I would
have expected the entire board surface to have an even plating thickness,
however thick, but seemingly not. The compromise hasn't worked for the
number of blind via groups featured in this board, and I need to try to
find out how to address a solution without solely relying on what our fab
house tells me.
In my entire life, I never had to worry about the processes involved in
fabricating PCB's - only that components could be soldered to them, that
they passed test and proved to be reliable in the field. I only ever worked
with good boards - the ones that passed in-coming inspection - in an
assembly environment, so my experience of board design and PCB fab is
limited to the past 8 or 9 months, in a company that has no previous
convictions for designing this type of board, so it's a case of the blind
leading the blind to a certain extent.
Any further help in this area would be greatly appreciated.
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch
ORG>
11/16/01
02:13 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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========================================================================Date: Fri, 16 Nov 2001 07:53:22 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wildes, Earl" <[log in to unmask]>
Subject: handling single parts
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi there. I sent this out once before, but it might have bounced.
Is there any guideline or procedure detailing how to handle single surface
mount parts, especially fine pitch. I've found several on moisture and ESD,
but none on re-packaging. Our production numbers are rather low, so it is
not always best to issue the whole tray of parts to the board shop. We need
a document to teach the stockroom personnel how to pick up and package
individual parts without bending the leads.
Thanks for your help.
Earl Wildes
Sr. Component Engineer
Korry Electronics Co.
901 Dexter Ave N.
Seattle, WA 98109
206-694-1398
[log in to unmask]
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========================================================================Date: Fri, 16 Nov 2001 10:02:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Donaldson <[log in to unmask]>
Subject: Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two small wires
to a PWB assembly while we are reflow soldering the other SMT parts to the
board. So far we have not found a wire type that a manufacturer will ensure
will survive the reflow temperatures. Solid wire with insulation is needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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========================================================================Date: Fri, 16 Nov 2001 16:39:12 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: solderability
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0034_01C16EBD.38F466A0"
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------=_NextPart_000_0034_01C16EBD.38F466A0
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solderabilityShine Wang
I can. Let me have your mailing and emailing details and I will forward the
info to you directly.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk
For instant access to Product Data Sheets register on the Tech-Shot area of
http://www.concoat.co.uk
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Shine Wang-0337CE
Sent: Friday, November 16, 2001 07:37
To: [log in to unmask]
Subject: [TN] solderability
who can tell me about how to do a solderability test?
------=_NextPart_000_0034_01C16EBD.38F466A0
Content-Type: text/html;
charset="gb2312"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>solderability</TITLE>
<META content="text/html; charset=windows-1252" http-equiv=Content-Type>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=070093716-16112001><STRONG>Shine Wang</STRONG></SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=070093716-16112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=070093716-16112001><STRONG>I can. Let me have your mailing and emailing
details and I will forward the info to you
directly.</STRONG></SPAN></FONT></DIV>
<DIV> </DIV>
<P><FONT face=Arial size=2><STRONG>Regards, Graham
Naisbitt<BR><BR>[log in to unmask]<BR></STRONG><A
href="http://www.concoat.co.uk/"><STRONG>www.concoat.co.uk</STRONG></A></FONT></P>
<DIV><FONT face=Arial size=2>For instant access to Product Data Sheets register
on the Tech-Shot area of http://<A
href="http://www.concoat.co.uk/">www.concoat.co.uk</A> </FONT></DIV>
<DIV><BR><FONT face=Arial size=2><STRONG>Concoat
Limited <BR>Alasan
House, Albany Park<BR>CAMBERLEY GU16 7PH UK<BR>Phone: +44 (0)1276 691100<BR>Fax:
+44 (0)1276 691227<BR>Mobile: +44 (0)79 6858 2121 </STRONG></FONT></DIV>
<DIV> </DIV>
<DIV><B><FONT size=2>
<P> </P></B></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>Shine Wang-0337CE<BR><B>Sent:</B>
Friday, November 16, 2001 07:37<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> [TN] solderability<BR><BR></DIV></FONT><!-- Converted from text/rtf format -->
<P><FONT face=Arial size=2>who can tell me about how to do a solderability
test?</FONT> </P></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0034_01C16EBD.38F466A0--
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========================================================================Date: Fri, 16 Nov 2001 16:45:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Conformal Coating to IPC Class 3
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Mike
Following on from Doug's response, I have customers in 2 camps:
#1 : "We require the coating to be under low stand-off devices but with no
filleting. So we apply a thinned dip coat first, and then top-off with a
proper spray coat"
#2 : "We want no coating under the components so we only dip with high
viscosity material"
I guess the issue they have concern about is TCE mis-match, however the
coating SHOULD be forgiving in this sense. Silicones, as I learnt from Brian
Ellis, are not suitable for such requirements/applications.
If you want to ensure that all the solder joints are protected under a BGA,
my suggestion is to dip coat. This may well cause you major problems with
component masking, but is the only easy way to get the coating penetration
under such devices.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
Sent: Friday, November 16, 2001 12:15
To: [log in to unmask]
Subject: [TN] Conformal Coating to IPC Class 3
When I read IPC Standards regarding conformal coating requirements for the
different classes, all I can find is coating thickness on a board.
I'm trying to work to class 3 standards for conformal coating and am
meeting those thickness requirements, however, I have to wonder how it
works on a BGA for example, where the coating thickness is sufficient but
doesn't completely cover and encapsulate the component. In other words,
there is a gap between the top of the BGA and the PCB.
Any thoughts on this would be appreciated.
Thanks,
Mike Manwell
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========================================================================Date: Fri, 16 Nov 2001 11:52:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
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What about using Teflon insulated wires?
-----Original Message-----
From: Bob Donaldson [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 11:03 AM
To: [log in to unmask]
Subject: [TN] Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two small
wires
to a PWB assembly while we are reflow soldering the other SMT parts to
the
board. So far we have not found a wire type that a manufacturer will
ensure
will survive the reflow temperatures. Solid wire with insulation is
needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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========================================================================Date: Fri, 16 Nov 2001 11:21:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: solderability
MIME-Version: 1.0
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Hi! I recommend you look at the IPC JSTD 002A specification for component
solderability and the IPC JSTD 003 specification for printed wiring board
solderability.
Dave Hillman
002A/003 Committee Chairman
[log in to unmask]
Shine Wang-0337CE <[log in to unmask]>@ipc.org> on 11/16/2001 01:37:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] solderability
who can tell me about how to do a solderability test?
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========================================================================Date: Fri, 16 Nov 2001 09:24:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Land size for wave soldering
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Hi ALll,
Should the land size be different for wave soldering? Suggestions are
appreciated.
Is there a standard glue dot size?
Thanks,
Patrick
This e-mail may contain SEL confidential information. The opinions expressed
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========================================================================Date: Fri, 16 Nov 2001 12:30:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
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Hi Bob,
I've reflowed a lot of air and core wound inductors that are made with
magnet wire that has polyimide (type ML) insulation. This is straight from
the spec sheet "ML is a film coated magnet wire made with polyimide resin.
It is a Class 220°C thermal life insulation with exceptional resistance to
chemical solvents and burnout. It will operate at temperatures up to 240°C.
The outstanding cut-thru of over 400°C and its ability to withstand
excessiver overloads extends the use of magnet wire in extreme conditions.
ML is unaffected by prolonged exposure to varnish solvents and is compatible
with virtually all systems."
There are multiple mfr's but MWS Wire Industries (www.mwswire.com) is one
that I use the most.
Steve Sauer
Mfg Engineer
Xetron Corporation
-----Original Message-----
We have a application where it would be very nice to solder two small wires
to a PWB assembly while we are reflow soldering the other SMT parts to the
board. So far we have not found a wire type that a manufacturer will ensure
will survive the reflow temperatures. Solid wire with insulation is needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
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========================================================================Date: Fri, 16 Nov 2001 09:48:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
X-To: Bob Donaldson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bob,
I have had good results with Teflon and I-PVC insulated wires in a
reflow application. We even wave soldered a few applications. (sub-merged)
Through testing I found we could a use pin-in-paste method and the
insulation held up well. If you are doing a Pb-free reflow, there may be
issues, as the temps are higher than SnPb.
Do some testing, with TC's attached to the wires. You may be
surprised to see the results.
Good Luck,
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Bob Donaldson [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 8:03 AM
To: [log in to unmask]
Subject: [TN] Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two
small wires
to a PWB assembly while we are reflow soldering the other SMT parts
to the
board. So far we have not found a wire type that a manufacturer will
ensure
will survive the reflow temperatures. Solid wire with insulation is
needed
in the 22-24 awg. size. Does anybody have experience soldering wires
to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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========================================================================Date: Fri, 16 Nov 2001 17:58:30 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
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We have experienced voiding with via in pad, I know it ws stated that the pads don't have vias in them but if they did they can somtimes gass through the plating, its not the air traped by the paste. I have investigated this with my old outgassing oil test which showes up the problem and will contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Peter George [log in to unmask]
To: [log in to unmask]
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
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<DIV><FONT face=Arial size=2>We have experienced voiding with via in pad, I know
it ws stated that the pads don't have vias in them but if they did they can
somtimes gass through the plating, its not the air traped by the paste. I have
investigated this with my old outgassing oil test which showes up the problem
and will contribute to voiding.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:Peter George [log in to unmask]"
title="Peter George [log in to unmask]">Peter George
[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Friday, November 16, 2001 8:52
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] BGA voids</DIV>
<DIV><BR></DIV>Hi, Peter,<BR><BR>I was at a seminar earlier this year where
BGA's and their solder joints<BR>were discussed at some length. The received
wisdom is that voids in solder<BR>joints are not of themselves a 'defect'
unless they break out through the<BR>side of the ball. In fact, they make the
joint more "flexible" - better<BR>able to withstand creep fatigue - so are
beneficial, up to a point.<BR><BR>What causes them is often outgassing of
volatiles in the solder paste flux<BR>during the reflow process, though the
size and shape of voids increases and<BR>changes when there are via-in-pad
features as well. About the only way to<BR>detect them is by X-ray, and to
judge from previous TechNet postings, there<BR>are some pretty fancy machines
around now that can give you a very much<BR>clearer view of the balls than is
normally the case ... if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one PCA<BR>product.
The voids that I $B!G (Bve observed (with Xray) contribute to as high
as<BR>60-70% of the joint area. My reflow profile was designed by running
a<BR>sample board with dummy components and thermalcouples attached right at
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see any via on
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for voids
formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step
by step how would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately; you
should<BR>not copy or use it for any purpose, nor disclose its contents to any
other<BR>person. Thank
you.]<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Fri, 16 Nov 2001 12:17:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! Intermetallic layers are alloys (at least per the ASMI definition
of an "alloy") but that is another discussion topic. Eric - take a look
section 6.5.5 in the book : The Mechanics of Solder Alloy Wetting &
Spreading, ISBN 0-442-01752-9. Several very controlled experiments have
been conducted by Dr. Tench showing what happens with the Cu3Sn and Cu6Sn5
IMCs. The data shows that the Cu3Sn oxidizes in only 10 minutes and is
very unsolderable. Also check out the information in Soldering In
Electronics, Klein Wassink, ISBN0-901150-14-2, section 4.2.5.3 which
discusses oxidation and Cu/Sn IMCs. The key looks to be which intermetallic
is present - a good deal of the published data I have been reading defines
the "bad" IMC as the Cu3Sn. The consensus trends to the Cu6Sn5 IMC as the
IMC the fluxes can deal with. The SERA testing I have participated in also
trends the same direction. Did you identify the which of the Cu/Sn IMCs
were on your samples? If the IMC was Cu6Sn5 then that would fit the
literature trend. George's ideal of the diffusion kinetics is another
possible detail which may play a part - I am pretty well versed in Sn
oxidation because of my master thesis but the kinetics of copper/tin I need
to do some reading. One interesting point from George's idea - Sn
preferentially oxidizes at the expense of Pb on a tin/lead surface so I
would guess that the copper/tin diffusion kinetics are playing a role too.
Take a look at those references and let me know what you think - oxidation
and IMCs - wonderful discussion topics.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/14/2001 02:59:20 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Intermetallic Layers
Hi George,
One pertinent point here is that the intermetallic layers are compounds not
alloys. Thus their oxidising and other chemical reactions will probably be
different from those of their constituent metals.
The surface activation energies may be the key, can you give me references
please George? I would like to follow them up. (See my other reply!)
One point though, I would expect the copper rich compound to lie adjacent
to
the copper interface and the copper deficient one next to the solder
interface. My microsections after solder etching showed that the normally
visible two layers were still present, so I must have been soldering the
copper deficient layer, which, as you say, is the easiest one to solder.
Also, since the melting points of these compounds are higher than soldering
temperatures we would always be soldering to the copper deficient layer. Or
are we? So, open question, can the copper deficient, aka easily solderable,
compound turn into a copper rich layer. Has anybody reading this discussion
got access to a well equipped laboratory?
Regards
Eric Dawson
> -----Original Message-----
> From: Franck, George [SMTP:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 7:20 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
> During my PWB education I learned that there are at least three "alloys"
> of
> copper and tin that are formed as the Copper diffuses into the solder.
> The
> first alloy formed (and I don't remember the ratios) has the highest tin
> to
> copper ratio, and has surface activation energies within the range of
most
> fluxes. Therefore, this first tin copper alloy, or IMC, is solderable.
> All
> the others alloys, with higher amounts of copper in them, are not.
>
> Activation energies reflect how strongly attached the Oxygen atom are on
> the
> surface of the metal. The more copper on the surface alloy, the tighter
> the
> oxygen is attached, the stronger the flux needed to break the oxygen from
> the surface.
>
> While the copper is diffusing into the Solder, the Tin is also diffusing
> into the copper surface, lowering the % tin in the solder alloy, which
> raises the melt temperature of the remaining solder. It is all quite an
> interesting solid state diffusion system. By the way, for all intents
and
> purposes, the lead is just too big (physical size of the atom) to
> participate in this diffusion system much, except to get in the way.
>
> It is possible that Eric only exposed the "solderable" tin-copper
> intermetallic in his tests, i.e. the one with the least amount of copper
> in
> it.
>
> What was the magic chemical I played with in my old PWB shop to make
> boards
> solderable, Thiourea hydrochloride? Wasn't that the active chemical in
> Tarnex also?
>
> George Franck, CID+
> who recalls his "PWB as Black Magic" roots.
>
> --------------------
> Disclaimers:
> 1) If Dave Hillman says I am wrong, then I probably am.
> 2) My company will neither confirm nor deny the existence of any of my
> opinions.
> 3) Tin-copper alloys are commonly referred to as Bronze.
>
> -----Original Message-----
> From: David Hillman [mailto:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 12:25 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
>
> Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> industry data which shows that oxidized Sn/Cu intermetallic is one of the
> more unsolderable surfaces encountered on an assembly. Problems with poor
> plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> intermetallic at the hole rim to become oxidized) and thin HASL coatings
> are just two examples of everyday industry solderability issues
associated
> with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> fair majority of the industry is moving away from these types of flux
> formulations. With all that being said, without the Sn/Cu IMC we would
> have
> no solder joints so it is a critical part of a solder joint.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] Intermetallic Layers
>
>
> Hi All,
>
> I notice that a few new references have been made to the above subject
and
> thought I would share some of my early work with you.
>
> In my first post as a graduate, I researched the causes of dewetting on
> circuit boards. I came across a solution, the make-up of which I have
> since
> lost, which dissolved the tin lead alloy but left the two intermetallic
> layers.
>
> I produced a number of one inch square coupons which I soldered using
> 63/37
> alloy, RMA flux and a Tri Moore Rotary Dip Tester.
>
> These were divided into three categories:
>
> 1 Control
> 2 Remove tin lead and re test in the Rotary Dip.
> 3 Remove tin lead, Several hours steam ageing and re test.
>
> Microsections showed that I had taken off the alloy successfully and left
> the IMC.s.
>
> All of the re tested coupons soldered successfully, including the steam
> aged
> ones.
>
> This was some years ago so I cannot remember the etchant nor the hours
and
> conditions in the steam ageing equipment. I do remember that the IMC
> soldered very well so I am always dubious when somebody blames the
> intermetallic for poor soldering.
>
> I seem to be alone in my faith that the IMC solders but this was the
> result
> of my very own work and I stand by it.
>
> Regards
> Eric Dawson, Defender of the IMC.
>
>
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========================================================================Date: Fri, 16 Nov 2001 13:24:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
Earl -
I agree that many shops do not do well with the more exotic laminates, but
we can not let that determine our choices. BT epoxy is better than FR4 in
some ways but it is still not up to performance standards needed to play in
the 1GHz *clock* range which necessitates a sub .5 nanosecond rise time for
signals. The loss tangent is the limiting factor for BT, with a range of
0.015-0.022 it is still to high for these designs. PPO's lower this
somewhat, 0.01-0.015, and are "flatter" in the Er curve with regard to
frequency. Cynate Ester maybe an answer to the problems, but when it comes
to cost vs. functionality the hands down winner is the ceramic-filled, glass
reinforced thermoset plastics (Rogers 4003/4350 and the like). Hopefully
the commercial fabricators will catch up with the prototype houses in
delivering quality product in the more "bleeding" edge materials.
None of this is meant to say that FR4 can not be used in
high-speed/high-frequency design just that it is easier to get the
performance from other products. I have seen/heard of/worked on designs in
the 2+ GHz range on multilayer FR4 laminates. These can/do work but design
becomes super-critical, and it is not a simple place and autoroute routine.
Not all designer or engineers understand the parameters and attention to
detail required to make it work.
Jeffrey
[log in to unmask]
4-7582
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 9:04 AM
To: [log in to unmask]
Subject: Re: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Jeffery,
I certainly apreciate your posting as a reminder to me as well. I would add,
from a DFM point of view concerning materials and their processing:
Getek has good electrical properties, as you say, but processing and some
results associated with it can be dissapointing. This material must be
processed more along the lines of polyimide. It requires a more damanding
press cycle than those for FR4 types using simple straight up processing
from 0 to 90 minutes or so. Therefore, not all shops like or do well with
it.
The Rogers and Arlon (liscensed from Rogers but with slight variations
concerning properties) material is really neat stuff. It has processing
drawbacks as well as being limited in prepreg glass styles and thicknesses
when reinforced. If improperly processed, as with any material type, it has
several failing characteristics. As is widely known, this type material
often is married/laminated to Getek to meet design and performance
requirements. Really low DC and loss tangents.
My money is on BT epoxy blends when and where possible. It has high
performance characteristics and is easily processed. I have designed it in
and used in in very complex, large, high layer count MLB's with great
success. It is/was used in some Cray designs built by IBM, as one example.
Just wanted to add to your good comments,
MoonMan
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========================================================================Date: Fri, 16 Nov 2001 13:13:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeff,
I agree with most all you say. Just can't buy the thought of not considering
who and who cannot work with what materials. To ignore this is violating one
of many important rules of DFM/CE. The very high speed requirements, as in
Jim Marsico's pending designs, certainly demand high performance, exotic
materials. Not having a highly qualified supplier puts these requirements in
great jeopardy. Of course, this should not be the case for Jim - should it Jim?
I certainly agree with your technical assessment of material performance
properties. Some other physical properties simply add to the extent of the
compromise.
I started working with Arlon's CLTE material, I belive in 1997, before
Rogers had its own treaters and presses to make this type prepreg and core
material (though they own the patents for it), respectively, and had mixed
results. It must be said, that in the begining, there were but two or three
shops capable of successfully processing CLTE. It must also be said that
material was hard to come by and deliveries were slow.
Now, Rogers is making its prepreg and core as well, so deliveries and
material consistency is much better though the glass styles still (typically
106, or there abouts, glass styles) can cause issues especially when thicker
layer structures are needed. However, most high speed dielectric thicknesses
are in the 4 to 6 mil range so this is not such a big problem. Also, there
are fab shops more capable of managing their processes properly and ensuring
some initial "defects" I found do not occur. Initial defects, and currently
potential types, consisted of very low foil and innerlaminar bond strengths
as well as some a little wierd looking like "mush" on the surface layers.
In agreeing with most all you say, part of that means compromise always is a
factor in any design. The compromises here are, as always, design rules,
materials selections based on design need, fabrication process capabilities,
and assembly process capabilities.
What ultimately must come out of all this is quality, and reliability - over
a long performance period, meeting clearly specified contract requirements.
Other factors must enter the equation as well and, of course, are
availability, delivery, and cost.
DFM/CE, when properly practiced, ensures all this is taken into
consideration. Many other issues must be considered at the design level as
well. Plated holes, blind vias, buried vias, micro vias and the impact they
have on the critical, high speed equation and, again, reliabilty together
with specified performance. All this, and so much more, is part of the
designer's realm while working concurrently with everyone else on the DFM/CE
team as board fab and assembly process and manufacturing engineers
notwithstanding component engineers plus many others.
There's so much more for another discussion, but you say it well,
Earl
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========================================================================Date: Fri, 16 Nov 2001 11:38:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Wong <[log in to unmask]>
Subject: Cab Maestro 2M blades
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_010A_01C16E93.3381D880"
This is a multi-part message in MIME format.
------=_NextPart_000_010A_01C16E93.3381D880
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Has anyone bothered to sharpen their CAB Maestro blades or did you just order replacements? If so, who did you get the replacements from? We bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
------=_NextPart_000_010A_01C16E93.3381D880
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Has anyone bothered to sharpen their CAB Maestro
blades or did you just order replacements? If so, who did you get the
replacements from? We bought our 2M used and don't know of any local reps
in WA/OR.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Thanks</FONT></DIV>
<DIV><FONT face=Arial size=2>Peter</FONT></DIV></BODY></HTML>
------=_NextPart_000_010A_01C16E93.3381D880--
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========================================================================Date: Fri, 16 Nov 2001 13:02:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Conformal Coating to IPC Class 3
MIME-Version: 1.0
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Doug,
"Conformal Coating - The Great Career Limiting Move"
May I use this for the title of my book! ;-)
David A. Douthit
Manager
LoCan LLC
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========================================================================Date: Fri, 16 Nov 2001 13:54:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeff,
This is the part of you message I agree with most:
None of this is meant to say that FR4 can not be used in
high-speed/high-frequency design just that it is easier to get the
performance from other products. I have seen/heard of/worked on designs in
the 2+ GHz range on multilayer FR4 laminates. These can/do work but design
becomes super-critical, and it is not a simple place and autoroute routine.
Not all designer or engineers understand the parameters and attention to
detail required to make it work.
I especially mean the last sentence. Got some great stories to tell here.
Earl
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========================================================================Date: Thu, 15 Nov 2001 07:30:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: conformal coating
MIME-Version: 1.0
Content-Type: text/plain
A few months ago someone (Mike) from Technet said that they would send me
info on a water soluble acrylic conformal coating that meets NASA outgassing
requirements. Would you please contact me off line?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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========================================================================Date: Thu, 15 Nov 2001 07:53:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board materials (organic?) and
design that can handle clock speeds up to 1GHz? Or another question, what
aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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========================================================================Date: Fri, 16 Nov 2001 08:33:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "McGlaughlin, Jeffrey A" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jeff, thanks for the response... I'm sending this to you directly because
I'm having trouble sending anything to IPC. (Maybe this will get through,
who knows!)
What about PWB design/fab techniques. Does thinner lines, microvias, buried
vias, embedded discretes, etc. affect signal speed? What about a 'power
mesh architecture' technology?
We're presently in production with a polyimide multilayer PWB which has an
MCM at 560 MHz. We think we're pushing the limit. Our next generation
designs might be up to I gig... I'm looking for board materials, designs,
etc. to accommodate.
Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: McGlaughlin, Jeffrey A [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 8:15 AM
To: [log in to unmask]
Subject: Re: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Not having seen any other responses to this posting I will take a
*SWAG* at it.
1) The clock speed is not the most damning part of the "high speed
design" problem. Look at the rise time of the primary signals on the board
and convert that in to frequency. Your speed issue is probably much worse
than you think.
2) The material properties that you need to be concerned about are
the dielectric constant (variable for FR4) and the loss tangent. The loss
tangent of the material becomes especially important when working with low
level signals and narrow noise to signal ratios.
3) There are several levels of solution you can explore to get out
of FR4 and in to a more stable material. The first are the PPO materials
like GeTek. They are an epoxy-glass material with the resin being highly
modified, to improve electrical and temperature performance. Next there are
the co-laminates like Speedboard N and C, prepreg only, which are used to
create a better final laminated board. Next in line would be the more exotic
ceramic-filled thermoplastics like Roger's RO4003/4350 materials.
Good Luck
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 10:43 AM
To: [log in to unmask]
Subject: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Hey Steve, for some reason IPC can't receive my e-mails.
Could you post
this for me?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Marsico, James
Sent: Thursday, November 15, 2001 7:54 AM
To: 'Technet'
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board
materials
(organic?) and design that can handle clock speeds up to
1GHz? Or another
question, what aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask]
<mailto:[log in to unmask]>
631-595-5879
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========================================================================Date: Fri, 16 Nov 2001 15:46:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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Help me out with this technetters,
The problem: BGA opens on a HASL board.
The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
0.28mm.
Management's solution is to increase the pad size to 0.4mm. I say to look
elsewhere in the process for the problem.
I'd like to hear the opinions of my esteemed colleagues. What do you say folks?
Thanks in advance,
Tom
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========================================================================Date: Fri, 16 Nov 2001 16:33:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Peter,
Symmetrical stack-up is crucial and I've seen a few designs where it just
couldn't be helped (impedance). Rapid or uncontrolled cool down during
lamination can also contribute to bow/twist in a balanced construction.
I've successfully used post lamination dewarp procedures similar to Jeff's
suggestion but that was for Class 2 stuff. The trick is making the dewarp
last through subsequent high temp. assembly steps (soldering).
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
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========================================================================Date: Fri, 16 Nov 2001 15:07:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Harinder Jassal <[log in to unmask]>
Subject: Re: Cab Maestro 2M blades
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Peter,
Contact Cab Technologies headquarters directly http://www.cabtechn.com/
<http://www.cabtechn.com/>
Harinder
-----Original Message-----
From: Peter Wong [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 11:38 AM
To: [log in to unmask]
Subject: [TN] Cab Maestro 2M blades
Has anyone bothered to sharpen their CAB Maestro blades or did you just
order replacements? If so, who did you get the replacements from? We
bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
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<DIV><SPAN classI5280423-16112001><FONT face=Arial color=#0000ff
size=2>Peter,</FONT></SPAN></DIV>
<DIV><SPAN classI5280423-16112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN classI5280423-16112001><FONT face=Arial color=#0000ff
size=2>Contact Cab Technologies headquarters directly <A
href="http://www.cabtechn.com/">http://www.cabtechn.com/</A></FONT></SPAN></DIV>
<DIV><SPAN classI5280423-16112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN classI5280423-16112001><FONT face=Arial color=#0000ff
size=2>Harinder</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Peter Wong
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, November 16, 2001 11:38
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Cab Maestro 2M
blades<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Has anyone bothered to sharpen their CAB Maestro
blades or did you just order replacements? If so, who did you get the
replacements from? We bought our 2M used and don't know of any local
reps in WA/OR.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Thanks</FONT></DIV>
<DIV><FONT face=Arial
size=2>Peter</FONT></DIV>---------------------------------------------------------------------------------
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========================================================================Date: Fri, 16 Nov 2001 17:05:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Cab Maestro 2M blades
X-To: Peter Wong <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
We did both. Sharpened the old and purchased new form CAB (costly).
Sharpening will work until you hit the end of the adjustment slots.
I don't currently know of any after-market parts.
Hope that helps.
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Peter Wong [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 11:38 AM
To: [log in to unmask]
Subject: [TN] Cab Maestro 2M blades
Has anyone bothered to sharpen their CAB Maestro blades or did you
just order replacements? If so, who did you get the replacements from? We
bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
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========================================================================Date: Sat, 17 Nov 2001 10:15:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: solderability
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Graham Naisbitt,
I am Tony ,shine 's college I am sorry to tell that Shine is
sick now and you can forward the information to the address
[log in to unmask] and pls cc to [log in to unmask]
Thanks for your help
Tony Zhang
Process Engineer
Hangzhou Motorola
> -----Original Message-----
> From: Graham Naisbitt [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 4:39 PM
> To: [log in to unmask]
> Subject: Re: [TN] solderability
>
> Shine Wang
>
> I can. Let me have your mailing and emailing details and I will
> forward the info to you directly.
>
>
> Regards, Graham Naisbitt
>
> [log in to unmask]
> www.concoat.co.uk <http://www.concoat.co.uk/>
>
> For instant access to Product Data Sheets register on the Tech-Shot
> area of http://www.concoat.co.uk <http://www.concoat.co.uk/>
>
> Concoat Limited
> Alasan House, Albany Park
> CAMBERLEY GU16 7PH UK
> Phone: +44 (0)1276 691100
> Fax: +44 (0)1276 691227
> Mobile: +44 (0)79 6858 2121
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Shine
> Wang-0337CE
> Sent: Friday, November 16, 2001 07:37
> To: [log in to unmask]
> Subject: [TN] solderability
>
>
>
> who can tell me about how to do a solderability test?
>
------_=_NextPart_001_01C16F0D.C35E9670
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<HEAD>
<TITLE>RE: Re: [TN] solderability</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<P><SPAN LANG="en-us"><B><FONT SIZE=2 FACE="Arial">Graham Naisbitt,</FONT></B></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=2 FACE="Arial"> </FONT></B> <FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">I am Tony ,shine 's college I am sorry to tell that Shine is sick now and you can forward the information to the address [log in to unmask] and pls cc to [log in to unmask]</FONT></SPAN></P>
<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Thanks for your help</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="Tahoma">Tony Zhang</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="Tahoma">Process Engineer </FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="Tahoma">Hangzhou Motorola</FONT> </SPAN>
</P>
<BR>
<BR>
<UL>
<P><SPAN LANG="en-us"><FONT SIZE=1 FACE="Arial">-----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">From: </FONT></B> <FONT SIZE=1 FACE="Arial">Graham Naisbitt [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Sent: </FONT></B> <FONT SIZE=1 FACE="Arial">Friday, November 16, 2001 4:39 PM</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">To: </FONT></B> <FONT SIZE=1 FACE="Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Subject: </FONT></B> <FONT SIZE=1 FACE="Arial"> Re: [TN] solderability</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><B><FONT COLOR="#0000FF" SIZE=2 FACE="Arial">Shine Wang</FONT></B></SPAN>
<BR><SPAN LANG="en-us"><FONT FACE="Arial"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT COLOR="#0000FF" SIZE=2 FACE="Arial">I can. Let me have your mailing and emailing details and I will forward the info to you directly.</FONT></B></SPAN>
<BR><SPAN LANG="en-us"><FONT FACE="Arial"> </FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><B><FONT SIZE=2 FACE="Arial">Regards, Graham Naisbitt<BR>
<BR>
[log in to unmask]<BR>
</FONT></B><FONT SIZE=2 FACE="Arial">www.concoat.co.uk <<U></U></FONT><U><FONT COLOR="#0000FF" SIZE=2 FACE="Arial"><A HREF="http://www.concoat.co.uk/">http://www.concoat.co.uk/</A></FONT></U><FONT SIZE=2 FACE="Arial">></FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="Arial">For instant access to Product Data Sheets register on the Tech-Shot area of</FONT><U> <FONT COLOR="#0000FF" SIZE=2 FACE="Arial"><A HREF="http://www.concoat.co.uk">http://www.concoat.co.uk</A> <<A HREF="http://www.concoat.co.uk/">http://www.concoat.co.uk/</A>></FONT></U><FONT SIZE=2 FACE="Arial"></FONT> </SPAN></P>
<P><SPAN LANG="en-us"><B><FONT SIZE=2 FACE="Arial">Concoat Limited <BR>
Alasan House, Albany Park<BR>
CAMBERLEY GU16 7PH UK<BR>
Phone: +44 (0)1276 691100<BR>
Fax: +44 (0)1276 691227<BR>
Mobile: +44 (0)79 6858 2121</FONT></B> </SPAN>
<BR><SPAN LANG="en-us"><FONT FACE="Arial"> </FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=2 FACE="Arial"> </FONT></B></SPAN>
</P>
<UL>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="Tahoma">-----Original Message-----<BR>
</FONT><B><FONT SIZE=2 FACE="Tahoma">From:</FONT></B><FONT SIZE=2 FACE="Tahoma"> TechNet [</FONT><U><FONT COLOR="#0000FF" SIZE=2 FACE="Tahoma"><A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT></U><U><B><FONT COLOR="#0000FF" SIZE=2 FACE="Tahoma">On</FONT></B></U><B><FONT SIZE=2 FACE="Tahoma"> Behalf Of</FONT></B> <FONT SIZE=2 FACE="Tahoma">Shine Wang-0337CE<BR>
</FONT><B><FONT SIZE=2 FACE="Tahoma">Sent:</FONT></B><FONT SIZE=2 FACE="Tahoma"> Friday, November 16, 2001 07:37<BR>
</FONT><B><FONT SIZE=2 FACE="Tahoma">To:</FONT></B><FONT SIZE=2 FACE="Tahoma"> [log in to unmask]<BR>
</FONT><B><FONT SIZE=2 FACE="Tahoma">Subject:</FONT></B><FONT SIZE=2 FACE="Tahoma"> [TN] solderability<BR>
<BR>
</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="Arial">who can tell me about how to do a solderability test?</FONT><FONT FACE="Arial"> </FONT></SPAN>
</P>
</UL></UL>
</BODY>
</HTML>
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========================================================================Date: Fri, 16 Nov 2001 21:41:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
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========================================================================Date: Sat, 17 Nov 2001 08:43:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
awarding business on the basis of price tag. Instead, minimize total cost.
Move toward a single supplier for any one item, on a long-term
relationship of loyalty and trust." Lou Hart
-----Original Message-----
From: Stephen R. Gregory [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 9:41 PM
To: [log in to unmask]
Subject: [TN] E-Business auctions for EMS providers...
Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty
closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any
of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
------------------------------------------------------------------------
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---------
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========================================================================Date: Sat, 17 Nov 2001 09:07:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles McMahon <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
I support Lou's contribution to the e-business auction discussion.
As a proponent of W. Edwards Deming's 14 points of management, I am
gratified to see there are others in the US (I think Lou is US based) who
believe in his teachings. I carry the 14 points with me on calls to
clients to provide a continuous reminder of the added
value we all hope to provide those whom we supply.
The reality is it takes more effort on behalf of the manufacturing world
that they are willing to expend to become more profitable. If we all
followed the principals.
the benefits would be proven by empirical data and increased profitability.
There appears to be little interest however.
Even though the results would be, in my view , demonstrably superior and
profitable as compared to the current paradigm, the only issue that
matters to the customer is can we built it for less v. (my view), can we
help you design it so that we can THEN build it for less.
As an advocate for co-operative engineering, I can only aspire to the
hope that more will move in this direction in order to meet the global
competive challenge.
Steve....ignore the auction.. Leave it for those unwilling to do the
work needed to build a successful product. They won't survive anyway.
Charlie McMahon
Lou Hart wrote:
>Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
>awarding business on the basis of price tag. Instead, minimize total cost.
> Move toward a single supplier for any one item, on a long-term
>relationship of loyalty and trust." Lou Hart
>
>-----Original Message-----
>From: Stephen R. Gregory [SMTP:[log in to unmask]]
>Sent: Friday, November 16, 2001 9:41 PM
>To: [log in to unmask]
>Subject: [TN] E-Business auctions for EMS providers...
>
>Hey all,
>
>Today, just learned about E-Business auctions for contracts for work in the
>EMS industry. It's been going on for a little while I guess, but I just
>learned about it today...new stuff for me...
>
>Watched how different companies were bidding for work from a OEM...I have
>mixed feelings about this. It was for work that we looked at pretty
>closely,
>priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
>be competitive, but make a fair profit...
>
>I just learned about this, and watched for a bit how things went (this was
>all real-time), companies were bidding lower and lower, fighting each
>other...making bids for the business that would cut into the profit margins
>that was originally quoted...
>
>I guess this is the future of significant orders for us EMS guys, have any
>of
>you been involved with this?
>
>What are your thoughts? Just curious?
>
>-Steve Gregory-
>
>------------------------------------------------------------------------
>---------
>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
>To unsubscribe, send a message to [log in to unmask] with following text in
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>
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>
>
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========================================================================Date: Sat, 17 Nov 2001 11:02:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
X-To: "Stephen R. Gregory" <[log in to unmask]>
Couple of years ago appeared an online auction for independent consultants.
Might still be ghere, who cares. Just saw an on line auction for contract
employes. This observation and yours shows a sign of the times.
Right now, anything is fair game for auctioneers. Like EMS work, contract
hourly rates, and consulting rates are down the tubes but for the good guys.
No big deal this phenomonon. The economy, however, is.
MoonMan
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========================================================================Date: Sat, 17 Nov 2001 17:07:55 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
I couldn't agree more with Lou's view, but would question why all the large
OEMs who compete for the Demming award (including among others, Motorola),
send all their production offshore, where the low labour cost is the
driving force, and quality is enforced. The European PCB industry has been
decimated by the global telecomms full stop, but when the business comes
back it will be made in China. Why? Not for quality, but purely for low
PRICE. The E-auction is a buyers dream - keep screwing the price until it
goes no lower, THEN impose horrendous contract conditions just to guarantee
that the poor supplier goes bust. We are all guilty of wanting everything
free, perfect and now, but until we change our attitude and put a VALUE,
not a price on what we buy, the current third world countries (China) will
become first order countries, and the US and Europe will become 3rd rate
economies.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Lou Hart [SMTP:[log in to unmask]]
Sent: 17 November 2001 13:43
To: [log in to unmask]
Subject: Re: [TN] E-Business auctions for EMS providers...
Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
awarding business on the basis of price tag. Instead, minimize total cost.
Move toward a single supplier for any one item, on a long-term
relationship of loyalty and trust." Lou Hart
-----Original Message-----
From: Stephen R. Gregory [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 9:41 PM
To: [log in to unmask]
Subject: [TN] E-Business auctions for EMS providers...
Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty
closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any
of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
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========================================================================Date: Sat, 17 Nov 2001 23:02:00 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: conformal coating
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Jim
It twas I!
But, I did not say that it meets NASA outgassing, but that we think it
might. You should have received samples by now, maybe locked-up in customs
since Sep 11th? I will send more.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Thursday, November 15, 2001 12:30
To: [log in to unmask]
Subject: [TN] conformal coating
A few months ago someone (Mike) from Technet said that they would send me
info on a water soluble acrylic conformal coating that meets NASA outgassing
requirements. Would you please contact me off line?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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========================================================================Date: Sun, 18 Nov 2001 09:08:05 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Peter,
Let me refrase your question from plating point of view since you rised 1
milion dollar question:
How to plate the holes without plating the surface.
As far as I know,the best equipment,the best technologies,the best chemistry
etc have limitited capacity in terms of throwing capability ( ratio of metal
plated inside the hole to metal plated on the surface).The best figure is
slighty above 1.0 , usually is less than 1.0 .
No magic in this area:if the design requires to plate 3 times at least 20
microns or so in the holes, the surface will get additional around 60 -70
microns of copper before plating and etching of the final pattern.
PCB designer should know this basic fact of life while imposing fancy
construction.
Of course PCB manufacturer has some possibilities to manipulate artwork
compensations according to copper thickness to be etched, but etching
factors are also fact of life.
There are some tricky ways,but most of them are not working well on HDI
boards with fine lines.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: å ðåáîáø 16 2001 10:04
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Rudy,
>
> The boards are ENIG finished, the ENIG plating being carried out
> post-solder-mask, which must be after final copper etch, so No, there is
> no
> other metal in the area, unless my understanding of the plating/etching
> sequence is all wrong. My understanding (faulty or otherwise) of what the
> fab house has done, is that they laminate, drill and plate the layers with
> the first suite of blind vias, then laminate, drill and plate for the
> second suite of blind vias, then again for the 3rd suite until everything
> is stacked up, pressed, drilled and plated for the through-holes. I
> haven't
> quite been able to make sense of it all yet, but I think what I'm being
> told is that the plating becomes "stepped" somehow. I have 3 sets of blind
> vias from each outer surface (for ease of argument), making 4 plating
> sessions on each side by the time the through-hole group is done. The
> first
> areas to be drilled and plated are therefore plated 4 times, while the
> last
> areas to be drilled are only plated once, with the groups in between
> getting their proportional share of multiple plating.
>
> Thus at final etch, there is, I am told, a compromise to be reached - how
> to achieve the correct widths and spacings on the heavily plated areas
> without over-etching the lightly-plated areas. In my simple way, I would
> have expected the entire board surface to have an even plating thickness,
> however thick, but seemingly not. The compromise hasn't worked for the
> number of blind via groups featured in this board, and I need to try to
> find out how to address a solution without solely relying on what our fab
> house tells me.
>
> In my entire life, I never had to worry about the processes involved in
> fabricating PCB's - only that components could be soldered to them, that
> they passed test and proved to be reliable in the field. I only ever
> worked
> with good boards - the ones that passed in-coming inspection - in an
> assembly environment, so my experience of board design and PCB fab is
> limited to the past 8 or 9 months, in a company that has no previous
> convictions for designing this type of board, so it's a case of the blind
> leading the blind to a certain extent.
>
> Any further help in this area would be greatly appreciated.
>
> Best regards
>
> Peter Duncan
>
>
>
>
> "<Rudy
> Sedlak>" To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN] Over-etch
> ORG>
>
>
> 11/16/01
> 02:13 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> Peter:
>
> I am not sure if I fully understand the process you are using....so I am
> going to ask a dumb question, that may shed some light on the issue...
>
> Is there, anywhere in electrical contact with Copper being etched any
> other
> metal excepting Tin?
>
> This sort of thing, selective over-etch, is classically seen when there is
> some other metal, (Nickel, Gold, or???) than Tin in electrical contact
> with
> the over-etched Copper, and also in contact with the etchant.
>
> And if I am completely out in space with this question, please forgive the
> intrusion.
>
> Rudy Sedlak
>
> --------------------------------------------------------------------------
> -------
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========================================================================Date: Mon, 19 Nov 2001 10:49:56 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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========================================================================Date: Mon, 19 Nov 2001 11:06:55 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Mon, 19 Nov 2001 11:30:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Thanks for your advice, Roger. I have looked into this already, but the
spacing available on the over-etched area isn't enough to widen the pads by
the 4 mils or so needed without winding up with a solid copper strip.
Will continue the quest!
Best regards
Peter Duncan
"Roger M. Stoops"
<rstoops@SPECTRAPRECISI To: [log in to unmask]
ONDAY.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Over-etch
11/16/01 11:28 PM
Please respond to
"TechNet E-Mail Forum."
Peter,
I'm probably out of my league here, but the board house may be able to
compensate somewhat with "etch compensation", adding copper width where the
most etching will take place. If you know you're going to lose 2 or 3 mils
[.05-.08mm] per side in the final etch, add on copper before the
lam/drill/plate processes to get what you want. Check with your supplier
to see if this would work. I know this doesn't help you with this board
now, but may fix future problems. Time for Tums...(or Rolaids, Ativan,
Guinness, etc.).
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
"<Peter
George To: [log in to unmask]
Duncan>" cc:
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/16/01
03:04 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi, Rudy,
The boards are ENIG finished, the ENIG plating being carried out
post-solder-mask, which must be after final copper etch, so No, there is no
other metal in the area, unless my understanding of the plating/etching
sequence is all wrong. My understanding (faulty or otherwise) of what the
fab house has done, is that they laminate, drill and plate the layers with
the first suite of blind vias, then laminate, drill and plate for the
second suite of blind vias, then again for the 3rd suite until everything
is stacked up, pressed, drilled and plated for the through-holes. I haven't
quite been able to make sense of it all yet, but I think what I'm being
told is that the plating becomes "stepped" somehow. I have 3 sets of blind
vias from each outer surface (for ease of argument), making 4 plating
sessions on each side by the time the through-hole group is done. The first
areas to be drilled and plated are therefore plated 4 times, while the last
areas to be drilled are only plated once, with the groups in between
getting their proportional share of multiple plating.
Thus at final etch, there is, I am told, a compromise to be reached - how
to achieve the correct widths and spacings on the heavily plated areas
without over-etching the lightly-plated areas. In my simple way, I would
have expected the entire board surface to have an even plating thickness,
however thick, but seemingly not. The compromise hasn't worked for the
number of blind via groups featured in this board, and I need to try to
find out how to address a solution without solely relying on what our fab
house tells me.
In my entire life, I never had to worry about the processes involved in
fabricating PCB's - only that components could be soldered to them, that
they passed test and proved to be reliable in the field. I only ever worked
with good boards - the ones that passed in-coming inspection - in an
assembly environment, so my experience of board design and PCB fab is
limited to the past 8 or 9 months, in a company that has no previous
convictions for designing this type of board, so it's a case of the blind
leading the blind to a certain extent.
Any further help in this area would be greatly appreciated.
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch
ORG>
11/16/01
02:13 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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========================================================================Date: Mon, 19 Nov 2001 13:47:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA bone of contention
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I would say use another board finish - ENIG or similar - as you may have a
flatness problem with HASL. Or you can think about answers to the following
questions and see if they give you any other clues, or help us to give you
better answers:
What substrate are you using?
Are the opens occuring at first test after assembly, or in qualification
testing or are they field returns? Has any temperature cycling been carried
out?
How old are the PCB's you're using - have they become oxidised?
Have the BGA's been re-worked/replaced?
Do the opens occur with the same contacts or are they more random?
Do you have any thermally assymetrical design features near the problem
area(s) such as heavy traces running nearby, or some longer traces and some
shorter traces? These can contribute to theft of heat, which may result in
there being insufficient heat left to make a proper solder joint,
especially if they're connected to thermal, voltage or ground planes, which
will dissipate the heat even more. You may have to reduce your peak
soldering temperature and increase its duration to compensate.
How was the thermal profiling carried out? Are you certain that all the BGA
contacts are reaching proper soldering temperature?
BGA pads in general are smaller than the ball diameter. Why did
"management" pick on 0.4mm as a pad size that would improve the situation?
If you are not using via-in-pad, 0.4mm pad sizes are going to interfere
with the offset vias and probably lead to greater problems of
solderability.
What other possible causes have been considered? What causes have you
rejected?
Good Luck - you may find there is no quick answer to this problem, but I
hope for your sake it's easily solved.
Peter Duncan
Tom Colby
<tcolby@CREST To: [log in to unmask]
RON.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA bone of contention
<[log in to unmask]
ORG>
11/17/01
04:46 AM
Please
respond to
"TechNet
E-Mail
Forum."
Help me out with this technetters,
The problem: BGA opens on a HASL board.
The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
0.28mm.
Management's solution is to increase the pad size to 0.4mm. I say to look
elsewhere in the process for the problem.
I'd like to hear the opinions of my esteemed colleagues. What do you say
folks?
Thanks in advance,
Tom
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========================================================================Date: Mon, 19 Nov 2001 13:54:51 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Hans,
Uncontrolled or too rapid cool-down during lamination is what I thought had
probably caused the warp in the first place, and you're right - the trick
with de-warping is not getting the warp back again as soon as you go near
reflow or wave soldering. I suspect a lot of finger crossing and whispered
prayers are likely the main means of passing that hurdle successfully, as
there are no guarantees that a flattened board will stay flattened.
I'm going to follow Jeff's guideline - it's not so different from what I
used years ago on "conventional" technology boards - to try and straighten
out some of the boards we have as a back-up in case we can't get good
boards even after a second re-make. I'm three and a half months into a 2
week delivery on these little b----rs!
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Board Warp
<[log in to unmask]>
11/17/01 05:33 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter,
Symmetrical stack-up is crucial and I've seen a few designs where it just
couldn't be helped (impedance). Rapid or uncontrolled cool down during
lamination can also contribute to bow/twist in a balanced construction.
I've successfully used post lamination dewarp procedures similar to Jeff's
suggestion but that was for Class 2 stuff. The trick is making the dewarp
last through subsequent high temp. assembly steps (soldering).
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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========================================================================Date: Mon, 19 Nov 2001 14:24:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Hi, Edward,
The heavy copper weight resulting from all these plating processes was
recognised early on, but a) we assumed it would be reasonably even across
the board surface, and b) was not so heavy that the required widths and
spacings couldn't achieved after final etch. Certainly it wasn't flagged up
to us by the fab house as being a problem.
A very similar board was made by another fab house with no problem, apart
from the boards being warped. The etching was fine - it's just that they
took 7 weeks to make them on priority, which we couldn't afford again.
Hmmm! The things we have to find out the hard way.
Peter Duncan
Edward
Szpruch To: [log in to unmask]
<edward@ELTEK cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
.CO.IL> Aero/ST Group)
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/18/01
03:08 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter,
Let me refrase your question from plating point of view since you rised 1
milion dollar question:
How to plate the holes without plating the surface.
As far as I know,the best equipment,the best technologies,the best
chemistry
etc have limitited capacity in terms of throwing capability ( ratio of
metal
plated inside the hole to metal plated on the surface).The best figure is
slighty above 1.0 , usually is less than 1.0 .
No magic in this area:if the design requires to plate 3 times at least 20
microns or so in the holes, the surface will get additional around 60 -70
microns of copper before plating and etching of the final pattern.
PCB designer should know this basic fact of life while imposing fancy
construction.
Of course PCB manufacturer has some possibilities to manipulate artwork
compensations according to copper thickness to be etched, but etching
factors are also fact of life.
There are some tricky ways,but most of them are not working well on HDI
boards with fine lines.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: å ðåáîáø 16 2001 10:04
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Rudy,
>
> The boards are ENIG finished, the ENIG plating being carried out
> post-solder-mask, which must be after final copper etch, so No, there is
> no
> other metal in the area, unless my understanding of the plating/etching
> sequence is all wrong. My understanding (faulty or otherwise) of what the
> fab house has done, is that they laminate, drill and plate the layers
with
> the first suite of blind vias, then laminate, drill and plate for the
> second suite of blind vias, then again for the 3rd suite until everything
> is stacked up, pressed, drilled and plated for the through-holes. I
> haven't
> quite been able to make sense of it all yet, but I think what I'm being
> told is that the plating becomes "stepped" somehow. I have 3 sets of
blind
> vias from each outer surface (for ease of argument), making 4 plating
> sessions on each side by the time the through-hole group is done. The
> first
> areas to be drilled and plated are therefore plated 4 times, while the
> last
> areas to be drilled are only plated once, with the groups in between
> getting their proportional share of multiple plating.
>
> Thus at final etch, there is, I am told, a compromise to be reached - how
> to achieve the correct widths and spacings on the heavily plated areas
> without over-etching the lightly-plated areas. In my simple way, I would
> have expected the entire board surface to have an even plating thickness,
> however thick, but seemingly not. The compromise hasn't worked for the
> number of blind via groups featured in this board, and I need to try to
> find out how to address a solution without solely relying on what our fab
> house tells me.
>
> In my entire life, I never had to worry about the processes involved in
> fabricating PCB's - only that components could be soldered to them, that
> they passed test and proved to be reliable in the field. I only ever
> worked
> with good boards - the ones that passed in-coming inspection - in an
> assembly environment, so my experience of board design and PCB fab is
> limited to the past 8 or 9 months, in a company that has no previous
> convictions for designing this type of board, so it's a case of the blind
> leading the blind to a certain extent.
>
> Any further help in this area would be greatly appreciated.
>
> Best regards
>
> Peter Duncan
>
>
>
>
> "<Rudy
> Sedlak>" To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN] Over-etch
> ORG>
>
>
> 11/16/01
> 02:13 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> Peter:
>
> I am not sure if I fully understand the process you are using....so I am
> going to ask a dumb question, that may shed some light on the issue...
>
> Is there, anywhere in electrical contact with Copper being etched any
> other
> metal excepting Tin?
>
> This sort of thing, selective over-etch, is classically seen when there
is
> some other metal, (Nickel, Gold, or???) than Tin in electrical contact
> with
> the over-etched Copper, and also in contact with the etchant.
>
> And if I am completely out in space with this question, please forgive
the
> intrusion.
>
> Rudy Sedlak
>
>
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>
>
>
>
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> intended recipient, please delete it and notify us immediately; you
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> not copy or use it for any purpose, nor disclose its contents to any
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========================================================================Date: Mon, 19 Nov 2001 15:48:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: No power on after underfill
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C170CE.97A1C470"
This is a multi-part message in MIME format.
------_=_NextPart_001_01C170CE.97A1C470
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
3513 and the curing condition is 115C , 15 minutes , the BGA' s package
is below .
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3
; pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3
; pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good ones
.But after curing , some phone failed because "can not power on ", and
some failed for "check SIM card ", the defect sample is closed to 3%. I
think "check card "issue" may caused by the underfill material emission
which cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
------_=_NextPart_001_01C170CE.97A1C470
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<TITLE>No power on after underfill</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Arial">Pls help me to solve this issue</FONT>
</P>
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Arial">We use undefilll for two BGA in one product ,the epoxy is Loctite LPD 3513 and the curing condition is 115C , 15 minutes , the BGA' s package is below .</FONT></P>
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman"> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3 ; pitch, 0.8*0.8 ;bump array 10*10</FONT>
<BR><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman"> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ; pitch, 0.8*0.8 ; bump array 14*14</FONT>
</P>
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Arial">Before the underfilll we check the electric function .All are good ones .</FONT><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">But after curing , some phone failed because "can not power on ", and some failed for "check SIM card ", the defect sample is closed to 3%. I think "check card "issue" may caused by the underfill material emission which cover the SIM card lead .</FONT></P>
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">But I can not get any idea for further.</FONT>
</P>
<P><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Thanks </FONT>
<BR><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Tony</FONT>
</P>
</BODY>
</HTML>
------_=_NextPart_001_01C170CE.97A1C470--
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========================================================================Date: Mon, 19 Nov 2001 07:50:44 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: handling single parts
MIME-Version: 1.0
Content-Type: text/plain
Hi Earl,
I've experienced the same problem in the past. My solution was to write my
own short training program and deliver it to manufacturing, test and stores.
This gives them the idea that there is a need to handle the components in a
sympathetic way, but the best bit was the follow up.
With the permission of their Management, I gave them conducted tours of the
SMT line and showed them, first hand, what excellent quality we can achieve
when all goes well and, more importantly, what problems we have when things
go wrong; bent legs, mis-orientated components, shortages etc.
I'm a great believer in the idea that nobody comes to work to do a bad job,
they just lack information. If I can give them that information in a
positive way they nearly always respond.
Oh dear! This now sounds like a lecture, sorry, but communications is a
passion with me.
Regards
Eric Dawson
> -----Original Message-----
> From: Wildes, Earl [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 3:53 PM
> To: [log in to unmask]
> Subject: [TN] handling single parts
>
> Hi there. I sent this out once before, but it might have bounced.
> Is there any guideline or procedure detailing how to handle single surface
> mount parts, especially fine pitch. I've found several on moisture and
> ESD,
> but none on re-packaging. Our production numbers are rather low, so it is
> not always best to issue the whole tray of parts to the board shop. We
> need
> a document to teach the stockroom personnel how to pick up and package
> individual parts without bending the leads.
> Thanks for your help.
>
>
> Earl Wildes
> Sr. Component Engineer
> Korry Electronics Co.
> 901 Dexter Ave N.
> Seattle, WA 98109
> 206-694-1398
> [log in to unmask]
>
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 08:20:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: BGA bone of contention
MIME-Version: 1.0
Content-Type: text/plain
Hi Tom,
Are you wave soldering the other side of the board with the reflow soldered
bga.s on top? I have come across this practice and it definitely disturbs
the bga joints causing opens which cannot be detected by ordinary X ray
inspection.
Hope this helps.
Regards
Eric Dawson
> -----Original Message-----
> From: Tom Colby [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 8:47 PM
> To: [log in to unmask]
> Subject: [TN] BGA bone of contention
>
> Help me out with this technetters,
>
> The problem: BGA opens on a HASL board.
>
> The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
> 0.28mm.
>
> Management's solution is to increase the pad size to 0.4mm. I say to look
> elsewhere in the process for the problem.
>
> I'd like to hear the opinions of my esteemed colleagues. What do you say
> folks?
>
> Thanks in advance,
>
> Tom
>
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 09:16:53 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Stencil Reductions
MIME-Version: 1.0
Content-Type: text/plain
Hi,
Does any standard/procedure exist in relation to stencil reductions on a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
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========================================================================Date: Mon, 19 Nov 2001 10:33:15 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] handling single parts
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi Earl,
I don´t think it´s any good what you have in mind with your fine pitch
parts. If you have them in a tray better leave them there, supply only trays
to your line, handle them according their moisture level, reseal the bags
and send the remaining parts back to your stock.
For safe repacking you will need to have some kind of equipment, a
manipulator seems to be the minimum requirement for that task, all necessary
ESD measures and operators with enough sensitiveness to handle those
delicate parts, all things that normally aren´t found in stockrooms.
Don´t get yourself in trouble
Wolfgang
-----Ursprüngliche Nachricht-----
Von: Wildes, Earl [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 16:53
An: [log in to unmask]
Betreff: [TN] handling single parts
Hi there. I sent this out once before, but it might have bounced.
Is there any guideline or procedure detailing how to handle single surface
mount parts, especially fine pitch. I've found several on moisture and ESD,
but none on re-packaging. Our production numbers are rather low, so it is
not always best to issue the whole tray of parts to the board shop. We need
a document to teach the stockroom personnel how to pick up and package
individual parts without bending the leads.
Thanks for your help.
Earl Wildes
Sr. Component Engineer
Korry Electronics Co.
901 Dexter Ave N.
Seattle, WA 98109
206-694-1398
[log in to unmask]
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========================================================================Date: Mon, 19 Nov 2001 10:45:36 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] BGA voids
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-2022-jp"
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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========================================================================Date: Mon, 19 Nov 2001 18:27:10 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably doesn't
matter. The main thing I can think of that would cause your problem is the
thermal excursions needed to apply and cure the underfill. Am I correct to
say that the boards passed test at room temperature before the underfill is
applied?
You may have a manufacturing problem where the balls make contact enough to
pass test, but fail at elevated temperature. I would try testing the boards
at 100 or 115 degrees C prior to underfilling them and see if they still
pass. If they do, but fail again after underfilling, then the problem is
probably related to your underfilling process. It is quite easy to apply
too much if you're not using an automated process or have not correctly
calculated the amount of material to apply. It does flow more prior to
curing at curing temperature, and if it's getting into nearby interface
contacts as a result, you will need to look at damming the area around the
BGA with a peelable masking to contain the underfill until it's cured, or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have any
conductive residues left on the board, especially if you use no-clean
soldering processes, they may be picked up by the underfill and there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance of the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No power on after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD 3513
and the curing condition is 115C , 15 minutes , the BGA' s package is below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good ones .
But after curing , some phone failed because "can not power on ", and some
failed for "check SIM card ", the defect sample is closed to 3%. I think
"check card "issue" may caused by the underfill material emission which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
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========================================================================Date: Mon, 19 Nov 2001 12:45:48 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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The outgassin test for blowhole in printed boards was developed in the years gone bye after it appeared in and Italian PCB specification I was asked to review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In the last test I did with ten scrap boards dfrom different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Busko, Wolfgang
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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charset="iso-2022-jp"
Content-Transfer-Encoding: quoted-printable
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<META content="text/html; charset=iso-2022-jp" http-equiv=Content-Type>
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<STYLE></STYLE>
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<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed boards
was developed in the years gone bye after it appeared in and Italian PCB
specification I was asked to review. After some testing I did it ended up in the
IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for outgassing
tests with via in pad. In the last test I did with ten scrap boards dfrom
different suppliers 2 outgassed on the pads from the vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could and has
been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil trick I
recently cited ond not Earl the<BR>Moonman, sorry for not remembering and
citing correct.<BR>Although I often remember the good things my memory for
names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche Nachricht-----<BR>Von: Bob
Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN] BGA
voids<BR><BR><BR>We have experienced voiding with via in pad, I know it ws
stated that the<BR>pads don't have vias in them but if they did they can
somtimes gass through<BR>the plating, its not the air traped by the paste. I
have investigated this<BR>with my old outgassing oil test which showes up the
problem and will<BR>contribute to voiding.<BR><BR>Bob Willis<BR><BR>See us at
APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent: Friday,
November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA voids<BR><BR>Hi,
Peter,<BR><BR>I was at a seminar earlier this year where BGA's and their
solder joints<BR>were discussed at some length. The received wisdom is that
voids in solder<BR>joints are not of themselves a 'defect' unless they break
out through the<BR>side of the ball. In fact, they make the joint more
"flexible" - better<BR>able to withstand creep fatigue - so are beneficial, up
to a point.<BR><BR>What causes them is often outgassing of volatiles in the
solder paste flux<BR>during the reflow process, though the size and shape of
voids increases and<BR>changes when there are via-in-pad features as well.
About the only way to<BR>detect them is by X-ray, and to judge from previous
TechNet postings, there<BR>are some pretty fancy machines around now that can
give you a very much<BR>clearer view of the balls than is normally the case
... if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one PCA<BR>product.
The voids that I $B!G (Bve observed (with Xray) contribute to as<BR>high
as<BR>60-70% of the joint area. My reflow profile was designed by running
a<BR>sample board with dummy components and thermalcouples attached right at
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see any via on
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for voids
formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step
by step how would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
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========================================================================Date: Mon, 19 Nov 2001 12:52:06 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Stencil Reductions
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If you call Peter Swanson at Intertronics in the UK he can supply you the IPC Standard document.
Many thanks
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Cathy Killen
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:16 AM
Subject: [TN] Stencil Reductions
Hi,
Does any standard/procedure exist in relation to stencil reductions on a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
for the stated addressee(s) and access to it by any other person is
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The views expressed in this E-mail are those of the author, and do not
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otherwise expressly indicated.
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<DIV><FONT face=Arial size=2>If you call Peter Swanson at Intertronics in the UK
he can supply you the IPC Standard document.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Many thanks</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Cathy
Killen</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:16
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] Stencil Reductions</DIV>
<DIV><BR></DIV>Hi,<BR>Does any standard/procedure exist in relation to stencil
reductions on a<BR>paste screen? If so, where can I source them. If there are
no<BR>standards/procedures what reductions would you
recommend?<BR>Thanks.<BR><BR>Cathy Killen<BR>Training Instructor<BR>Smtek
Europe Ltd.<BR>The information contained in the E-mail is confidential. It is
intended only<BR>for the stated addressee(s) and access to it by any other
person is<BR>unauthorised.<BR>The views expressed in this E-mail are those of
the author, and do not<BR>represent the views of Smtek Europe, its associates
or subsidiaries, unless<BR>otherwise expressly indicated.<BR>Please note: It
is your responsibility to scan this E-mail for
viruses.<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Mon, 19 Nov 2001 08:15:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
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What site is doing this? Interesting concept but way too many risks.
Kathy
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<DIV>What site is doing this? Interesting concept but way too many
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<DIV> </DIV>
<DIV> </DIV>
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========================================================================Date: Mon, 19 Nov 2001 10:16:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
(#2001-713)
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I'm not that far up in the food chain to know all of the particulars, but
it wouldn't surprise me if that were the case.
What I'm looking for is comments on the increase of pad size and
corroboration in my belief that it's the wrong solution to this problem.
Tom
At 04:20 AM 11/19/01 -0600, you wrote:
>Date: Mon, 19 Nov 2001 08:20:31 -0000
>From: Eric Dawson <[log in to unmask]>
>Subject: Re: BGA bone of contention
>
>Hi Tom,
>Are you wave soldering the other side of the board with the reflow soldered
>bga.s on top? I have come across this practice and it definitely disturbs
>the bga joints causing opens which cannot be detected by ordinary X ray
>inspection.
>Hope this helps.
>Regards
>Eric Dawson
>
> > -----Original Message-----
> > From: Tom Colby [SMTP:[log in to unmask]]
> > Sent: Friday, November 16, 2001 8:47 PM
> > To: [log in to unmask]
> > Subject: [TN] BGA bone of contention
> >
> > Help me out with this technetters,
> >
> > The problem: BGA opens on a HASL board.
> >
> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
> > 0.28mm.
> >
> > Management's solution is to increase the pad size to 0.4mm. I say to look
> > elsewhere in the process for the problem.
> >
> > I'd like to hear the opinions of my esteemed colleagues. What do you say
> > folks?
> >
> > Thanks in advance,
> >
> > Tom
> >
> > --------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 07:27:17 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Stencil Reductions
X-cc: [log in to unmask]
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The document you probably are referring to is IPC7525. It describes stencil
design GUIDELINES. Because of all the variables in the printing process you
can not come up with design RULES.
If you design and assemble your own boards you can establish in-house rules
for stencil design, but for a contract manufacturer that is a different
story. He has to look at the board that is provided and choose the best
design rules that than fit his process.
As far as aperture reductions go, some assemblers (very few) reduce all
their apertures by 1mil, most reduce only some apertures to eliminate
bridging.
Look at your own assembly process, determine what works best and write a set
of "design rules" as your own addendum to IPC7525 to match that in order to
get to World Class production quality.
Good luck,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bob Willis
Sent: Monday, November 19, 2001 04:52
To: [log in to unmask]
Subject: Re: [TN] Stencil Reductions
If you call Peter Swanson at Intertronics in the UK he can supply you the
IPC Standard document.
Many thanks
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
----- Original Message -----
From: Cathy Killen
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:16 AM
Subject: [TN] Stencil Reductions
Hi,
Does any standard/procedure exist in relation to stencil reductions on a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended
only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries,
unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for viruses.
------------------------------------------------------------------------
---------
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in
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<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff size=2>The
document you probably are referring to is IPC7525. It describes stencil design
GUIDELINES. Because of all the variables in the printing process you can not
come up with design RULES. </FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff size=2>If you
design and assemble your own boards you can establish in-house rules for stencil
design, but for a contract manufacturer that is a different story. He has to
look at the board that is provided and choose the best design rules that than
fit his process.</FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff size=2>As far
as aperture reductions go, some assemblers (very few) reduce all their apertures
by 1mil, most reduce only some apertures to eliminate
bridging.</FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff size=2>Look
at your own assembly process, determine what works best and write a set of
"design rules" as your own addendum to IPC7525 to match that in order to get to
World Class production quality.</FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff size=2>Good
luck,</FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff
size=2>Ahne.</FONT></SPAN></DIV>
<DIV><SPAN class=490331415-19112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of</B> Bob Willis<BR><B>Sent:</B> Monday,
November 19, 2001 04:52<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re:
[TN] Stencil Reductions<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>If you call Peter Swanson at Intertronics in the
UK he can supply you the IPC Standard document.</FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Many thanks</FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">Cathy
Killen</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:16
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] Stencil Reductions</DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT><FONT face=Arial
color=#0000ff size=2></FONT><BR></DIV>Hi,<BR>Does any standard/procedure
exist in relation to stencil reductions on a<BR>paste screen? If so, where
can I source them. If there are no<BR>standards/procedures what reductions
would you recommend?<BR>Thanks.<BR><BR>Cathy Killen<BR>Training
Instructor<BR>Smtek Europe Ltd.<BR>The information contained in the E-mail
is confidential. It is intended only<BR>for the stated addressee(s) and
access to it by any other person is<BR>unauthorised.<BR>The views expressed
in this E-mail are those of the author, and do not<BR>represent the views of
Smtek Europe, its associates or subsidiaries, unless<BR>otherwise expressly
indicated.<BR>Please note: It is your responsibility to scan this E-mail for
viruses.<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Mon, 19 Nov 2001 07:42:59 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
(#2001-713)
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
As a layout designer, I am surprised that they used such small land areas.
Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
See attached PDF from Motorola.
Denis Lefebvre, C.I.D.
Senior PCB Designer
Finisar Corporation
(408)542-3832
http://www.finisar.com
At 10:16 AM 11/19/2001 -0500, you wrote:
>I'm not that far up in the food chain to know all of the particulars, but
>it wouldn't surprise me if that were the case.
>
>What I'm looking for is comments on the increase of pad size and
>corroboration in my belief that it's the wrong solution to this problem.
>
>Tom
>
>At 04:20 AM 11/19/01 -0600, you wrote:
>>Date: Mon, 19 Nov 2001 08:20:31 -0000
>>From: Eric Dawson <[log in to unmask]>
>>Subject: Re: BGA bone of contention
>>
>>Hi Tom,
>>Are you wave soldering the other side of the board with the reflow soldered
>>bga.s on top? I have come across this practice and it definitely disturbs
>>the bga joints causing opens which cannot be detected by ordinary X ray
>>inspection.
>>Hope this helps.
>>Regards
>>Eric Dawson
>>
>> > -----Original Message-----
>> > From: Tom Colby [SMTP:[log in to unmask]]
>> > Sent: Friday, November 16, 2001 8:47 PM
>> > To: [log in to unmask]
>> > Subject: [TN] BGA bone of contention
>> >
>> > Help me out with this technetters,
>> >
>> > The problem: BGA opens on a HASL board.
>> >
>> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
>> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
>> > 0.28mm.
>> >
>> > Management's solution is to increase the pad size to 0.4mm. I say to look
>> > elsewhere in the process for the problem.
>> >
>> > I'd like to hear the opinions of my esteemed colleagues. What do you say
>> > folks?
>> >
>> > Thanks in advance,
>> >
>> > Tom
>> >
>> > --------------------------------------------------------------------------
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 09:21:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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========================================================================Date: Mon, 19 Nov 2001 11:26:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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Who are suppliers of inspection quality oils [Canadian Balson??] the bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the years gone bye after it appeared in and Italian PCB specification I was asked to review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In the last test I did with ten scrap boards dfrom different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Busko, Wolfgang
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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<DIV><FONT face=Arial size=2>Who are suppliers of inspection quality oils
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Bob Willis</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 4:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed boards
was developed in the years gone bye after it appeared in and Italian PCB
specification I was asked to review. After some testing I did it ended up in
the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for
outgassing tests with via in pad. In the last test I did with ten scrap boards
dfrom different suppliers 2 outgassed on the pads from the vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could and
has been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil trick I
recently cited ond not Earl the<BR>Moonman, sorry for not remembering and
citing correct.<BR>Although I often remember the good things my memory for
names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche Nachricht-----<BR>Von:
Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN] BGA
voids<BR><BR><BR>We have experienced voiding with via in pad, I know it ws
stated that the<BR>pads don't have vias in them but if they did they can
somtimes gass through<BR>the plating, its not the air traped by the paste. I
have investigated this<BR>with my old outgassing oil test which showes up
the problem and will<BR>contribute to voiding.<BR><BR>Bob Willis<BR><BR>See
us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA voids<BR><BR>Hi,
Peter,<BR><BR>I was at a seminar earlier this year where BGA's and their
solder joints<BR>were discussed at some length. The received wisdom is that
voids in solder<BR>joints are not of themselves a 'defect' unless they break
out through the<BR>side of the ball. In fact, they make the joint more
"flexible" - better<BR>able to withstand creep fatigue - so are beneficial,
up to a point.<BR><BR>What causes them is often outgassing of volatiles in
the solder paste flux<BR>during the reflow process, though the size and
shape of voids increases and<BR>changes when there are via-in-pad features
as well. About the only way to<BR>detect them is by X-ray, and to judge from
previous TechNet postings, there<BR>are some pretty fancy machines around
now that can give you a very much<BR>clearer view of the balls than is
normally the case ... if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one PCA<BR>product.
The voids that I $B!G (Bve observed (with Xray) contribute to as<BR>high
as<BR>60-70% of the joint area. My reflow profile was designed by running
a<BR>sample board with dummy components and thermalcouples attached right at
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see any via
on pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for
voids formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general,
in step by step how would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately; you
should<BR>not copy or use it for any purpose, nor disclose its contents to
any other<BR>person. Thank
you.]<BR><BR>----------------------------------------------------------------------------<BR>-----<BR>Technet
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========================================================================Date: Mon, 19 Nov 2001 16:42:43 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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Its the standard oil you use with a microscope when you are using a 100x objective for immersion.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: David Fish
To: [log in to unmask]
Sent: Monday, November 19, 2001 7:26 PM
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the years gone bye after it appeared in and Italian PCB specification I was asked to review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In the last test I did with ten scrap boards dfrom different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Busko, Wolfgang
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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<DIV><FONT face=Arial size=2>Its the standard oil you use with a microscope when
you are using a 100x objective for immersion.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>David Fish</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 7:26
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>Who are suppliers of inspection quality oils
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Bob
Willis</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 4:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed
boards was developed in the years gone bye after it appeared in and Italian
PCB specification I was asked to review. After some testing I did it ended
up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for
outgassing tests with via in pad. In the last test I did with ten scrap
boards dfrom different suppliers 2 outgassed on the pads from the
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could and
has been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil trick
I recently cited ond not Earl the<BR>Moonman, sorry for not remembering
and citing correct.<BR>Although I often remember the good things my memory
for names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche Nachricht-----<BR>Von:
Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN] BGA
voids<BR><BR><BR>We have experienced voiding with via in pad, I know it ws
stated that the<BR>pads don't have vias in them but if they did they can
somtimes gass through<BR>the plating, its not the air traped by the paste.
I have investigated this<BR>with my old outgassing oil test which showes
up the problem and will<BR>contribute to voiding.<BR><BR>Bob
Willis<BR><BR>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this year where
BGA's and their solder joints<BR>were discussed at some length. The
received wisdom is that voids in solder<BR>joints are not of themselves a
'defect' unless they break out through the<BR>side of the ball. In fact,
they make the joint more "flexible" - better<BR>able to withstand creep
fatigue - so are beneficial, up to a point.<BR><BR>What causes them is
often outgassing of volatiles in the solder paste flux<BR>during the
reflow process, though the size and shape of voids increases
and<BR>changes when there are via-in-pad features as well. About the only
way to<BR>detect them is by X-ray, and to judge from previous TechNet
postings, there<BR>are some pretty fancy machines around now that can give
you a very much<BR>clearer view of the balls than is normally the case ...
if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray) contribute
to as<BR>high as<BR>60-70% of the joint area. My reflow profile was
designed by running a<BR>sample board with dummy components and
thermalcouples attached right at the<BR>joint. I also inspected the PCB
lands and didn $B!G (Bt see any via on pad.<BR><BR><BR><BR><BR><BR>Does
anyone know the possible reasons for voids formation in BGA
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by step how
would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately; you
should<BR>not copy or use it for any purpose, nor disclose its contents to
any other<BR>person. Thank
you.]<BR><BR>----------------------------------------------------------------------------<BR>-----<BR>Technet
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========================================================================Date: Mon, 19 Nov 2001 08:47:52 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brooks,Bill" <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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We used to make PCB's back in the mid 1970's and used a fusing oil produced
by Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut
oil... but I can't remember for sure... Those were my High School years...
:)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the bear
the heat of soldering well?
----- Original Message -----
From: Bob <mailto:[log in to unmask]> Willis
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the years
gone bye after it appeared in and Italian PCB specification I was asked to
review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In
the last test I did with ten scrap boards dfrom different suppliers 2
outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is
on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Busko, Wolfgang <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl
the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [ mailto:[log in to unmask] <mailto:[log in to unmask]> ]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask] <mailto:[log in to unmask]>
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
< http://www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm> >
www.bobwillis.co.uk <http://www.bobwillis.co.uk> < http://www.bobwillis.co.
uk <http://www.bobwillis.co.uk> >
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com> <
http://www.seminar-registrations.com <http://www.seminar-registrations.com>
>
----- Original Message -----
From: Peter George < mailto:Peter <mailto:Peter> George [log in to unmask]
ORG <mailto:[log in to unmask]> >
[log in to unmask] <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]> < mailto:[log in to unmask]
<mailto:[log in to unmask]> >
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
< mailto:[log in to unmask] <mailto:[log in to unmask]> >
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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<DIV><SPAN class6294316-19112001><FONT face=Arial color=#0000ff size=2>We
used to make PCB's back in the mid 1970's and used a fusing oil produced by
Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut oil...
but I can't remember for sure... Those were my High School years...
:)</FONT></SPAN></DIV>
<DIV><SPAN class6294316-19112001><FONT face=Arial color=#0000ff size=2>Good
luck... - Bill Brooks</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> David Fish
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, November 19, 2001 11:27
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Who are suppliers of inspection quality oils
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">Bob
Willis</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 4:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed
boards was developed in the years gone bye after it appeared in and Italian
PCB specification I was asked to review. After some testing I did it ended
up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for
outgassing tests with via in pad. In the last test I did with ten scrap
boards dfrom different suppliers 2 outgassed on the pads from the
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could and
has been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask]
href="mailto:[log in to unmask]">Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil trick
I recently cited ond not Earl the<BR>Moonman, sorry for not remembering
and citing correct.<BR>Although I often remember the good things my memory
for names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche Nachricht-----<BR>Von:
Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN] BGA
voids<BR><BR><BR>We have experienced voiding with via in pad, I know it ws
stated that the<BR>pads don't have vias in them but if they did they can
somtimes gass through<BR>the plating, its not the air traped by the paste.
I have investigated this<BR>with my old outgassing oil test which showes
up the problem and will<BR>contribute to voiding.<BR><BR>Bob
Willis<BR><BR>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this year where
BGA's and their solder joints<BR>were discussed at some length. The
received wisdom is that voids in solder<BR>joints are not of themselves a
'defect' unless they break out through the<BR>side of the ball. In fact,
they make the joint more "flexible" - better<BR>able to withstand creep
fatigue - so are beneficial, up to a point.<BR><BR>What causes them is
often outgassing of volatiles in the solder paste flux<BR>during the
reflow process, though the size and shape of voids increases
and<BR>changes when there are via-in-pad features as well. About the only
way to<BR>detect them is by X-ray, and to judge from previous TechNet
postings, there<BR>are some pretty fancy machines around now that can give
you a very much<BR>clearer view of the balls than is normally the case ...
if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray) contribute
to as<BR>high as<BR>60-70% of the joint area. My reflow profile was
designed by running a<BR>sample board with dummy components and
thermalcouples attached right at the<BR>joint. I also inspected the PCB
lands and didn $B!G (Bt see any via on pad.<BR><BR><BR><BR><BR><BR>Does
anyone know the possible reasons for voids formation in BGA
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by step how
would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately; you
should<BR>not copy or use it for any purpose, nor disclose its contents to
any other<BR>person. Thank
you.]<BR><BR>----------------------------------------------------------------------------<BR>-----<BR>Technet
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========================================================================Date: Mon, 19 Nov 2001 09:06:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Glynn Shaw <[log in to unmask]>
Subject: Re: Over-etch
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hello Peter.
I have been building complex boards seems like all my life. I understand
completely how the processes your fab shop used could result in difficulty
etching the patterns. I also understand how designers are capable of making
board production nearly impossible. If you are serious and would like real
help in determining if a better process exists for this particular board
then I am willing to devote a few hours of study to your problem-- but I
will need real information. I invite you to send me a fab drawing showing
the stack-ups and finished hole sizes, the various layer interconnections,
etc. In addition, if there aren't major confidentiality issues, I also
invite you to visit our web site and use the Data Transfer Menu to send us
the CAD Data for the part. We will load it onto our systems and check the
layout for plating-related issues.
It could well be that there is no better process than the fab house has
already chosen, but I also think they might have "overlooked" some viable
solutions to the problem. Only your fab drawing and data will tell for sure.
My web site is: www.protoengineering.com
My fax is USA: (408) 738-1290
At 10:26 AM 11/16/01 +0800, you wrote:
>Dear All,
>
>I have another problem for you PCB Fab guru's. The sister board to the
>warped one of my previous posting has the problem of being over-etched in
>some areas. Some pads are half the width they should be. It is 12 layer,
>ENIG finished, with 3 different blind via depths from the bottom of the
>board and two from the top, as well as the through-hole group. They are
>laminated conventionally - i.e. each blind group is laminated. drilled and
>plated before lamination for the next hole group, and so on, so there is
>considerable variance in surface copper weight by the time the board is
>fully laminated.
>
>Our fab house tried remaking the boards by laminating the entire board at
>once, then laser drilling to depth and plating. The result was a total
>failure, and once again we're faced with a re-make using the previous
>processes.
>
>Does anyone know how we can reduce the variance in surface copper weight
>such that, in final etch, there isn't such a poor compromise between
>getting the widths and spacings of the heavier copper areas right, without
>over-etching the lighter copper areas? I tentatively suggested selective
>masking of some kind for the areas already plated, but I have no idea if
>that's feasible or not. How do other fab houses deal with this situation?
>
>Thanks as ever for your invaluable help.
>
>Peter Duncan
>
>[This e-mail is confidential and may also be privileged. If you are not the
>intended recipient, please delete it and notify us immediately; you should
>not copy or use it for any purpose, nor disclose its contents to any other
>person. Thank you.]
>
>---------------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 11:42:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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Used to purchase fusing oil with a Chevron label. They had a water soluble
as well as solvent oil but seems to me that the WS was at a significantly
higher price. Hollis used to carry oil for their oil injection wave
machines which was basically the same thing. Think it was Hollis 225. Did
a very nice job of wave soldering and reducing dross on the pot but sure was
messy.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Brooks,Bill
Sent: Monday, November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some sort
of Peanut oil... but I can't remember for sure... Those were my High School
years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the
bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the
years gone bye after it appeared in and Italian PCB specification I was
asked to review. After some testing I did it ended up in the IEC
specification.
The same oil can be used effectivly for outgassing tests with via in
pad. In the last test I did with ten scrap boards dfrom different suppliers
2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to
vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
----- Original Message -----
From: Busko, Wolfgang
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond
not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems
a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated
that the
pads don't have vias in them but if they did they can somtimes gass
through
the plating, its not the air traped by the paste. I have
investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder
joints
were discussed at some length. The received wisdom is that voids in
solder
joints are not of themselves a 'defect' unless they break out
through the
side of the ball. In fact, they make the joint more "flexible" -
better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder
paste flux
during the reflow process, though the size and shape of voids
increases and
changes when there are via-in-pad features as well. About the only
way to
detect them is by X-ray, and to judge from previous TechNet
postings, there
are some pretty fancy machines around now that can give you a very
much
clearer view of the balls than is normally the case ... if you have
cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN
Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one
PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute
to as
high as
60-70% of the joint area. My reflow profile was designed by running
a
sample board with dummy components and thermalcouples attached right
at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via
on pad.
Does anyone know the possible reasons for voids formation in BGA
(micro)
reflow?
In general, in step by step how would one trouble shoot such a
defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are
not the
intended recipient, please delete it and notify us immediately; you
should
not copy or use it for any purpose, nor disclose its contents to any
other
person. Thank you.]
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<DIV><SPAN class=304383519-19112001><FONT face=Tahoma color=#000080 size=2>Used
to purchase fusing oil with a Chevron label. They had a water soluble as well as
solvent oil but seems to me that the WS was at a significantly
higher price. Hollis used to carry oil for their oil injection wave
machines which was basically the same thing. Think it was Hollis
225. Did a very nice job of wave soldering and reducing dross on the pot
but sure was messy. </FONT></SPAN></DIV>
<DIV><SPAN class=304383519-19112001>
<P><FONT size=2>Mel Parrish<BR>Soldering Technology International<BR>Madison,
AL<BR>256 705 5530<BR>256 705 5538
Fax<BR>[log in to unmask]<BR> </FONT> </P></SPAN></DIV>
<DIV><SPAN class=304383519-19112001><FONT size=2><BR> </FONT> </DIV></SPAN>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of </B>Brooks,Bill<BR><B>Sent:</B>
Monday, November 19, 2001 8:48 AM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids<BR><BR></FONT></DIV>
<DIV><SPAN class=196294316-19112001><FONT face=Arial color=#0000ff size=2>We
used to make PCB's back in the mid 1970's and used a fusing oil produced by
Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut
oil... but I can't remember for sure... Those were my High School years...
:)</FONT></SPAN></DIV>
<DIV><SPAN class=196294316-19112001><FONT face=Arial color=#0000ff size=2>Good
luck... - Bill Brooks</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> David Fish
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, November 19, 2001 11:27
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Who are suppliers of inspection quality oils
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">Bob
Willis</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 4:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed
boards was developed in the years gone bye after it appeared in and
Italian PCB specification I was asked to review. After some testing I did
it ended up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for
outgassing tests with via in pad. In the last test I did with ten scrap
boards dfrom different suppliers 2 outgassed on the pads from the
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could
and has been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask]
href="mailto:[log in to unmask]">Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001
9:45 AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil
trick I recently cited ond not Earl the<BR>Moonman, sorry for not
remembering and citing correct.<BR>Although I often remember the good
things my memory for names seems a bit<BR>weak.<BR><BR>Hope you don $B!-
(Jt forgive me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche
Nachricht-----<BR>Von: Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN]
BGA voids<BR><BR><BR>We have experienced voiding with via in pad, I know
it ws stated that the<BR>pads don't have vias in them but if they did
they can somtimes gass through<BR>the plating, its not the air traped by
the paste. I have investigated this<BR>with my old outgassing oil test
which showes up the problem and will<BR>contribute to
voiding.<BR><BR>Bob Willis<BR><BR>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this year
where BGA's and their solder joints<BR>were discussed at some length.
The received wisdom is that voids in solder<BR>joints are not of
themselves a 'defect' unless they break out through the<BR>side of the
ball. In fact, they make the joint more "flexible" - better<BR>able to
withstand creep fatigue - so are beneficial, up to a point.<BR><BR>What
causes them is often outgassing of volatiles in the solder paste
flux<BR>during the reflow process, though the size and shape of voids
increases and<BR>changes when there are via-in-pad features as well.
About the only way to<BR>detect them is by X-ray, and to judge from
previous TechNet postings, there<BR>are some pretty fancy machines
around now that can give you a very much<BR>clearer view of the balls
than is normally the case ... if you have cash
to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray)
contribute to as<BR>high as<BR>60-70% of the joint area. My reflow
profile was designed by running a<BR>sample board with dummy components
and thermalcouples attached right at the<BR>joint. I also inspected the
PCB lands and didn $B!G (Bt see any via on
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for
voids formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In
general, in step by step how would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately;
you should<BR>not copy or use it for any purpose, nor disclose its
contents to any other<BR>person. Thank
you.]<BR><BR>----------------------------------------------------------------------------<BR>-----<BR>Technet
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---------------------------------------------------------------------------------
========================================================================Date: Mon, 19 Nov 2001 12:42:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
The rule of thumb, as I understand it, is 80% of the smallest ball size or
preferably the same size as the substrate land. The object being to control
the collapse of the solderball.
If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a
pad size of 0.4-0.5mm?
At 10:40 AM 11/19/01 -0600, you wrote:
>Date: Mon, 19 Nov 2001 07:42:59 -0800
>From: Denis Lefebvre <[log in to unmask]>
>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
> (#2001-713)
>
>As a layout designer, I am surprised that they used such small land areas.
>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
>See attached PDF from Motorola.
>
>Denis Lefebvre, C.I.D.
>Senior PCB Designer
>Finisar Corporation
>(408)542-3832
>http://www.finisar.com
>
>At 10:16 AM 11/19/2001 -0500, you wrote:
> >I'm not that far up in the food chain to know all of the particulars, but
> >it wouldn't surprise me if that were the case.
> >
> >What I'm looking for is comments on the increase of pad size and
> >corroboration in my belief that it's the wrong solution to this problem.
> >
> >Tom
> >
> >At 04:20 AM 11/19/01 -0600, you wrote:
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> >>From: Eric Dawson <[log in to unmask]>
> >>Subject: Re: BGA bone of contention
> >>
> >>Hi Tom,
> >>Are you wave soldering the other side of the board with the reflow soldered
> >>bga.s on top? I have come across this practice and it definitely disturbs
> >>the bga joints causing opens which cannot be detected by ordinary X ray
> >>inspection.
> >>Hope this helps.
> >>Regards
> >>Eric Dawson
> >>
> >> > -----Original Message-----
> >> > From: Tom Colby [SMTP:[log in to unmask]]
> >> > Sent: Friday, November 16, 2001 8:47 PM
> >> > To: [log in to unmask]
> >> > Subject: [TN] BGA bone of contention
> >> >
> >> > Help me out with this technetters,
> >> >
> >> > The problem: BGA opens on a HASL board.
> >> >
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a
> pad of
> >> > 0.28mm.
> >> >
> >> > Management's solution is to increase the pad size to 0.4mm. I say to
> look
> >> > elsewhere in the process for the problem.
> >> >
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you say
> >> > folks?
> >> >
> >> > Thanks in advance,
> >> >
> >> > Tom
> >> >
> >> >
> --------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 10:41:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
What is the recommended pre-bake of multilayer boards prior to insertion and
wave. 221F for 1hour??? Or would this be a little extreme?
Thanks,
Rick
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========================================================================Date: Mon, 19 Nov 2001 12:56:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
issue (#2001-713)
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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In reference to the pad layout for the Motorola MCF5272, from many years
of experience in process engineering within a prominent PCB layout design
firm, a pad design of .28mm on this device would warrant extensive process
control to provide for an exceptable yield of soldering this device.
1. This would force manufacturing to perform solder paste stenciling thru
.28mm round apertures.(very difficult)
2. Secondly, If pcb is HASL processed, excess solder could hinder an
already difficult process of paste stenciling.
3. Mechanical reliability of these solder joints would be questionable in
my opinion because of the small surface area provided on the pcb.
4. Component mounting would have to be very accurate and repeatable since
the small surface area on the pcb would decrease the dynamic centering where
BGAs would center on solder reflow.
In conclusion, I think that Motorola recommends approximately .5mm pad
layout and .35mm via pad connections. Our designers would probably follow
what Motorola has recommended and we would require a reputable pcb house
that had good controls over its HASL process or require a different pcb
process that would provide flatter pad surfaces.
Paul Peltier,
Senior Process Manager
----- Original Message -----
From: Denis Lefebvre <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 19, 2001 10:42 AM
Subject: Re: [TN] TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
issue (#2001-713)
> As a layout designer, I am surprised that they used such small land areas.
> Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
> See attached PDF from Motorola.
>
> Denis Lefebvre, C.I.D.
> Senior PCB Designer
> Finisar Corporation
> (408)542-3832
> http://www.finisar.com
>
> At 10:16 AM 11/19/2001 -0500, you wrote:
> >I'm not that far up in the food chain to know all of the particulars, but
> >it wouldn't surprise me if that were the case.
> >
> >What I'm looking for is comments on the increase of pad size and
> >corroboration in my belief that it's the wrong solution to this problem.
> >
> >Tom
> >
> >At 04:20 AM 11/19/01 -0600, you wrote:
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> >>From: Eric Dawson <[log in to unmask]>
> >>Subject: Re: BGA bone of contention
> >>
> >>Hi Tom,
> >>Are you wave soldering the other side of the board with the reflow
soldered
> >>bga.s on top? I have come across this practice and it definitely
disturbs
> >>the bga joints causing opens which cannot be detected by ordinary X ray
> >>inspection.
> >>Hope this helps.
> >>Regards
> >>Eric Dawson
> >>
> >> > -----Original Message-----
> >> > From: Tom Colby [SMTP:[log in to unmask]]
> >> > Sent: Friday, November 16, 2001 8:47 PM
> >> > To: [log in to unmask]
> >> > Subject: [TN] BGA bone of contention
> >> >
> >> > Help me out with this technetters,
> >> >
> >> > The problem: BGA opens on a HASL board.
> >> >
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad
of
> >> > 0.28mm.
> >> >
> >> > Management's solution is to increase the pad size to 0.4mm. I say to
look
> >> > elsewhere in the process for the problem.
> >> >
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you
say
> >> > folks?
> >> >
> >> > Thanks in advance,
> >> >
> >> > Tom
> >> >
> >>
> --------------------------------------------------------------------------
> >
>
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========================================================================Date: Mon, 19 Nov 2001 13:09:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Mon, 19 Nov 2001 10:22:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
I guess that's a good question for Motorola.
We (designers) have used a "rule of thumb" that says the land size should
be no larger than 1/2 of the ball pitch. Diameter .4mm fits that rule. I
cannot testify as to whether or not it's a good rule... I'm just parroting
what I've been told. We also TEND to follow the manufacturer's
recommendations (when they are given).
-Denis
At 12:42 PM 11/19/2001 -0500, you wrote:
>The rule of thumb, as I understand it, is 80% of the smallest ball size or
>preferably the same size as the substrate land. The object being to control
>the collapse of the solderball.
>
>If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a
>pad size of 0.4-0.5mm?
>
>At 10:40 AM 11/19/01 -0600, you wrote:
>>Date: Mon, 19 Nov 2001 07:42:59 -0800
>>From: Denis Lefebvre <[log in to unmask]>
>>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
>> (#2001-713)
>>
>>As a layout designer, I am surprised that they used such small land areas.
>>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
>>See attached PDF from Motorola.
>>
>>Denis Lefebvre, C.I.D.
>>Senior PCB Designer
>>Finisar Corporation
>>(408)542-3832
>>http://www.finisar.com
>>
>>At 10:16 AM 11/19/2001 -0500, you wrote:
>> >I'm not that far up in the food chain to know all of the particulars, but
>> >it wouldn't surprise me if that were the case.
>> >
>> >What I'm looking for is comments on the increase of pad size and
>> >corroboration in my belief that it's the wrong solution to this problem.
>> >
>> >Tom
>> >
>> >At 04:20 AM 11/19/01 -0600, you wrote:
>> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
>> >>From: Eric Dawson <[log in to unmask]>
>> >>Subject: Re: BGA bone of contention
>> >>
>> >>Hi Tom,
>> >>Are you wave soldering the other side of the board with the reflow
>> soldered
>> >>bga.s on top? I have come across this practice and it definitely disturbs
>> >>the bga joints causing opens which cannot be detected by ordinary X ray
>> >>inspection.
>> >>Hope this helps.
>> >>Regards
>> >>Eric Dawson
>> >>
>> >> > -----Original Message-----
>> >> > From: Tom Colby [SMTP:[log in to unmask]]
>> >> > Sent: Friday, November 16, 2001 8:47 PM
>> >> > To: [log in to unmask]
>> >> > Subject: [TN] BGA bone of contention
>> >> >
>> >> > Help me out with this technetters,
>> >> >
>> >> > The problem: BGA opens on a HASL board.
>> >> >
>> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
>> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a
>>pad of
>> >> > 0.28mm.
>> >> >
>> >> > Management's solution is to increase the pad size to 0.4mm. I say to
>>look
>> >> > elsewhere in the process for the problem.
>> >> >
>> >> > I'd like to hear the opinions of my esteemed colleagues. What do
>> you say
>> >> > folks?
>> >> >
>> >> > Thanks in advance,
>> >> >
>> >> > Tom
>> >> >
>> >> >
>>--------------------------------------------------------------------------
>
>---------------------------------------------------------------------------------
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========================================================================Date: Mon, 19 Nov 2001 14:20:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: ion chromatography
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Good day TechNet
I'm looking for a recommendation for a lab to do ion chromatography testing for me. Small job, 3 lots of 4 pieces each. I'm looking to verify that our cleaning process can properly clean under a BGA module.
Reminder - anyone recommending themselves - no ads on TechNet, please contact me direct.
Thanks!
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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========================================================================Date: Mon, 19 Nov 2001 14:46:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Re: ion chromatography
MIME-Version: 1.0
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Graham,
You could try http://www.tracelaboratories.com/ or IBM labs in Bromont (not
sure if they do chromatography testing) at 1 888 IBM LABO ( 1 888 426-5226 )
Regards,
Mario Dion
Prod. Technologist
Mediatrix Telecom Inc
-----Original Message-----
From: Graham Collins [mailto:[log in to unmask]]
Sent: 19 novembre, 2001 14:20
To: [log in to unmask]
Subject: [TN] ion chromatography
Good day TechNet
I'm looking for a recommendation for a lab to do ion chromatography testing
for me. Small job, 3 lots of 4 pieces each. I'm looking to verify that our
cleaning process can properly clean under a BGA module.
Reminder - anyone recommending themselves - no ads on TechNet, please
contact me direct.
Thanks!
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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========================================================================Date: Mon, 19 Nov 2001 15:30:05 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: ion chromatography
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In the past I have regularly used CSL in kokomo IN for this work.
Jon Moore
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========================================================================Date: Mon, 19 Nov 2001 15:41:07 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jan Satterfield <[log in to unmask]>
Subject: Circuit Repair Facility
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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========================================================================Date: Mon, 19 Nov 2001 15:17:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David North <[log in to unmask]>
Subject: Re: Circuit Repair Facility
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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If you can't find someone in the Salt Lake City area, there's a company in
Seattle, Schippers & Crew, Inc. that recently introduced a service to do
this. 206-782-2325.
David North
Qualitel Corporation
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jan Satterfield
Sent: Monday, November 19, 2001 2:41 PM
To: [log in to unmask]
Subject: [TN] Circuit Repair Facility
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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========================================================================Date: Mon, 19 Nov 2001 18:34:36 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Circuit Repair Facility
MIME-Version: 1.0
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Hi Jan!
Why send them out when you can do it yourself? Go to:
http://www.hunterproducts.com/micro-metallizer.htm
I've got their system and it works like a charm...you'll get a nickel plating
pen, and a gold pen. There's really good instructions that come with the
system, even a knot-head like me can use it hehehe....you can do a finger in
about 10-minutes.
The thing I like about their system is that all the plating solutions are in
self-contained pens, so you don't have to worry about spilling it.
-Steve Gregory-
> My company was using Pacific Meta Corp for replating of gold fingers after
> solder was accidentally deposited. They are no longer doing repairs. Can
> someone guide me to a new company that can replate a single gold finger.
> We
> are located in Salt Lake City.
> Jan Satterfield
> Process Engineer
> L-3 Communications
>
--part1_b9.16fb3357.292af10c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jan!<BR>
<BR>
Why send them out when you can do it yourself? Go to:<BR>
<BR>
http://www.hunterproducts.com/micro-metallizer.htm<BR>
<BR>
I've got their system and it works like a charm...you'll get a nickel plating pen, and a gold pen. There's really good instructions that come with the system, even a knot-head like me can use it hehehe....you can do a finger in about 10-minutes.<BR>
<BR>
The thing I like about their system is that all the plating solutions are in self-contained pens, so you don't have to worry about spilling it.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">My company was using Pacific Meta Corp for replating of gold fingers after<BR>
solder was accidentally deposited. They are no longer doing repairs. Can<BR>
someone guide me to a new company that can replate a single gold finger. We<BR>
are located in Salt Lake City.<BR>
Jan Satterfield<BR>
Process Engineer<BR>
L-3 Communications<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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========================================================================Date: Mon, 19 Nov 2001 19:22:55 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: CCGA's, the good, the bad, and the ugly...
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Hi all!
May be getting the opportunity to assemble some boards with CCGA's on them.
Don't have any direct experience with these puppies. Downloaded IBM's
application *.PDF on assembling and reworking them (it's pretty good by the
way), and seems that basically, you would do the same thing assembling these
guys as you do when working with BGA's...am I over-simplifiying things too
much?
Any advice, or "gotcha's" I should look out for would be appreciated...
As always, thanks a bunch!!!
-Steve Gregory-
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========================================================================Date: Tue, 20 Nov 2001 08:37:30 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: No power on after underfill
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> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] No power on after underfill
>
> Hi, Joseph,
>
> I cannot find the 3513 material data sheet, but that probably doesn't
> matter. The main thing I can think of that would cause your problem is
> the
> thermal excursions needed to apply and cure the underfill. Am I
> correct to
> say that the boards passed test at room temperature before the
> underfill is
> applied?
>
> You may have a manufacturing problem where the balls make contact
> enough to
> pass test, but fail at elevated temperature. I would try testing the
> boards
> at 100 or 115 degrees C prior to underfilling them and see if they
> still
> pass. If they do, but fail again after underfilling, then the problem
> is
> probably related to your underfilling process. It is quite easy to
> apply
> too much if you're not using an automated process or have not
> correctly
> calculated the amount of material to apply. It does flow more prior to
> curing at curing temperature, and if it's getting into nearby
> interface
> contacts as a result, you will need to look at damming the area around
> the
> BGA with a peelable masking to contain the underfill until it's cured,
> or
> reducing the amount of material applied.
>
> One other thing might be contamination under the BGA. If you have any
> conductive residues left on the board, especially if you use no-clean
> soldering processes, they may be picked up by the underfill and
> there's a
> chance you're suffering from short circuits through the increased
> conductivity of the epoxy. It's very important to the performance of
> the
> underfill that the underneath of the BGA's are very clean.
>
> Hope this gives you some clues and you find a solution.
>
> Peter Duncan
>
>
>
>
> "Joseph H.
> Smith" To: [log in to unmask]
> <Tony_Zhang@H cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> ZMOT.COM> Aero/ST Group)
> Sent by: Subject: [TN] No power on
> after underfill
> TechNet
> <[log in to unmask]
> ORG>
>
>
> 11/19/01
> 03:48 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> Pls help me to solve this issue
>
>
> We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
> 3513
> and the curing condition is 115C , 15 minutes , the BGA' s package is
> below
> .
>
>
> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ;bump array 10*10
> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ; bump array 14*14
>
>
> Before the underfilll we check the electric function .All are good
> ones .
> But after curing , some phone failed because "can not power on ", and
> some
> failed for "check SIM card ", the defect sample is closed to 3%. I
> think
> "check card "issue" may caused by the underfill material emission
> which
> cover the SIM card lead .
>
>
> But I can not get any idea for further.
>
>
> Thanks
> Tony
>
>
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you are
> not the
> intended recipient, please delete it and notify us immediately; you
> should
> not copy or use it for any purpose, nor disclose its contents to any
> other
> person. Thank you.]
>
> ----------------------------------------------------------------------
> -----------
> Technet Mail List provided as a free service by IPC using LISTSERV
> 1.8d
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> in
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> SET Technet NOMAIL
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> Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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<P><SPAN LANG="en-us"><FONT SIZE=1 FACE="Arial">-----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">From: </FONT></B> <FONT SIZE=1 FACE="Arial"><Peter George Duncan> [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Sent: </FONT></B> <FONT SIZE=1 FACE="Arial">Monday, November 19, 2001 10:27 AM</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">To: </FONT></B> <FONT SIZE=1 FACE="Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Subject: </FONT></B> <FONT SIZE=1 FACE="Arial"> Re: [TN] No power on after underfill</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Hi, Joseph,</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">I cannot find the 3513 material data sheet, but that probably doesn't</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">matter. The main thing I can think of that would cause your problem is the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">thermal excursions needed to apply and cure the underfill. Am I correct to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">say that the boards passed test at room temperature before the underfill is</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">applied?</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">You may have a manufacturing problem where the balls make contact enough to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pass test, but fail at elevated temperature. I would try testing the boards</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">at 100 or 115 degrees C prior to underfilling them and see if they still</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pass. If they do, but fail again after underfilling, then the problem is</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">probably related to your underfilling process. It is quite easy to apply</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">too much if you're not using an automated process or have not correctly</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">calculated the amount of material to apply. It does flow more prior to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">curing at curing temperature, and if it's getting into nearby interface</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">contacts as a result, you will need to look at damming the area around the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">BGA with a peelable masking to contain the underfill until it's cured, or</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">reducing the amount of material applied.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">One other thing might be contamination under the BGA. If you have any</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">conductive residues left on the board, especially if you use no-clean</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">soldering processes, they may be picked up by the underfill and there's a</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">chance you're suffering from short circuits through the increased</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">conductivity of the epoxy. It's very important to the performance of the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">underfill that the underneath of the BGA's are very clean.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Hope this gives you some clues and you find a solution.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Peter Duncan</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> "Joseph H.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Smith" To: [log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> <Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> ZMOT.COM> Aero/ST Group)</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Sent by: Subject: [TN] No power on after underfill</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> TechNet</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> <[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> ORG></FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> 11/19/01</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> 03:48 PM</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Please</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> respond to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> "TechNet</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> E-Mail</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Forum."</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Pls help me to solve this issue</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">We use undefilll for two BGA in one product ,the epoxy is Loctite LPD 3513</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">and the curing condition is 115C , 15 minutes , the BGA' s package is below</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pitch, 0.8*0.8 ;bump array 10*10</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pitch, 0.8*0.8 ; bump array 14*14</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Before the underfilll we check the electric function .All are good ones .</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">But after curing , some phone failed because "can not power on ", and some</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">failed for "check SIM card ", the defect sample is closed to 3%. I think</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">"check card "issue" may caused by the underfill material emission which</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">cover the SIM card lead .</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">But I can not get any idea for further.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Thanks</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Tony</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">[This e-mail is confidential and may also be privileged. If you are not the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">intended recipient, please delete it and notify us immediately; you should</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">not copy or use it for any purpose, nor disclose its contents to any other</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">person. Thank you.]</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">---------------------------------------------------------------------------------</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Technet Mail List provided as a free service by IPC using LISTSERV 1.8d</FONT></SPAN>
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========================================================================Date: Tue, 20 Nov 2001 08:58:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: No power on after underfill
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1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and
the solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill 50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no
effective
4. what is conductive residues when we applying no-clean soldering
process ?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] No power on after underfill
>
> Hi, Joseph,
>
> I cannot find the 3513 material data sheet, but that probably doesn't
> matter. The main thing I can think of that would cause your problem is
> the
> thermal excursions needed to apply and cure the underfill. Am I
> correct to
> say that the boards passed test at room temperature before the
> underfill is
> applied?
>
> You may have a manufacturing problem where the balls make contact
> enough to
> pass test, but fail at elevated temperature. I would try testing the
> boards
> at 100 or 115 degrees C prior to underfilling them and see if they
> still
> pass. If they do, but fail again after underfilling, then the problem
> is
> probably related to your underfilling process. It is quite easy to
> apply
> too much if you're not using an automated process or have not
> correctly
> calculated the amount of material to apply. It does flow more prior to
> curing at curing temperature, and if it's getting into nearby
> interface
> contacts as a result, you will need to look at damming the area around
> the
> BGA with a peelable masking to contain the underfill until it's cured,
> or
> reducing the amount of material applied.
>
> One other thing might be contamination under the BGA. If you have any
> conductive residues left on the board, especially if you use no-clean
> soldering processes, they may be picked up by the underfill and
> there's a
> chance you're suffering from short circuits through the increased
> conductivity of the epoxy. It's very important to the performance of
> the
> underfill that the underneath of the BGA's are very clean.
>
> Hope this gives you some clues and you find a solution.
>
> Peter Duncan
>
>
>
>
> "Joseph H.
> Smith" To: [log in to unmask]
> <Tony_Zhang@H cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> ZMOT.COM> Aero/ST Group)
> Sent by: Subject: [TN] No power on
> after underfill
> TechNet
> <[log in to unmask]
> ORG>
>
>
> 11/19/01
> 03:48 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> Pls help me to solve this issue
>
>
> We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
> 3513
> and the curing condition is 115C , 15 minutes , the BGA' s package is
> below
> .
>
>
> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ;bump array 10*10
> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ; bump array 14*14
>
>
> Before the underfilll we check the electric function .All are good
> ones .
> But after curing , some phone failed because "can not power on ", and
> some
> failed for "check SIM card ", the defect sample is closed to 3%. I
> think
> "check card "issue" may caused by the underfill material emission
> which
> cover the SIM card lead .
>
>
> But I can not get any idea for further.
>
>
> Thanks
> Tony
>
>
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you are
> not the
> intended recipient, please delete it and notify us immediately; you
> should
> not copy or use it for any purpose, nor disclose its contents to any
> other
> person. Thank you.]
>
> ----------------------------------------------------------------------
> -----------
> Technet Mail List provided as a free service by IPC using LISTSERV
> 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text
> in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message:
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or
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<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and the solder paster type is Alpha RMA 9147</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">2. we have done the experiement for letting the epoxy only underfill 50% BGA size , the result is still bad</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">3. we reduce the curing temperature from 150 C to 120C , also no effective</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">4. what is</FONT> <FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">conductive residues when we applying no-clean soldering process ?</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">By the way, if you need MDS of 3513, I can send to you .</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Thanks for your great help.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">Tony</FONT> </SPAN>
<UL>
<P><SPAN LANG="en-us"><FONT SIZE=1 FACE="Arial">-----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">From: </FONT></B> <FONT SIZE=1 FACE="Arial"><Peter George Duncan> [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Sent: </FONT></B> <FONT SIZE=1 FACE="Arial">Monday, November 19, 2001 10:27 AM</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">To: </FONT></B> <FONT SIZE=1 FACE="Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Subject: </FONT></B> <FONT SIZE=1 FACE="Arial"> Re: [TN] No power on after underfill</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Hi, Joseph,</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">I cannot find the 3513 material data sheet, but that probably doesn't</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">matter. The main thing I can think of that would cause your problem is the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">thermal excursions needed to apply and cure the underfill. Am I correct to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">say that the boards passed test at room temperature before the underfill is</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">applied?</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">You may have a manufacturing problem where the balls make contact enough to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pass test, but fail at elevated temperature. I would try testing the boards</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">at 100 or 115 degrees C prior to underfilling them and see if they still</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pass. If they do, but fail again after underfilling, then the problem is</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">probably related to your underfilling process. It is quite easy to apply</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">too much if you're not using an automated process or have not correctly</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">calculated the amount of material to apply. It does flow more prior to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">curing at curing temperature, and if it's getting into nearby interface</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">contacts as a result, you will need to look at damming the area around the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">BGA with a peelable masking to contain the underfill until it's cured, or</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">reducing the amount of material applied.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">One other thing might be contamination under the BGA. If you have any</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">conductive residues left on the board, especially if you use no-clean</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">soldering processes, they may be picked up by the underfill and there's a</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">chance you're suffering from short circuits through the increased</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">conductivity of the epoxy. It's very important to the performance of the</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">underfill that the underneath of the BGA's are very clean.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Hope this gives you some clues and you find a solution.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Peter Duncan</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> "Joseph H.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Smith" To: [log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> <Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> ZMOT.COM> Aero/ST Group)</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Sent by: Subject: [TN] No power on after underfill</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> TechNet</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> <[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> ORG></FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> 11/19/01</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> 03:48 PM</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Please</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> respond to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> "TechNet</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> E-Mail</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> Forum."</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Pls help me to solve this issue</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">We use undefilll for two BGA in one product ,the epoxy is Loctite LPD 3513</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">and the curing condition is 115C , 15 minutes , the BGA' s package is below</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pitch, 0.8*0.8 ;bump array 10*10</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun"> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pitch, 0.8*0.8 ; bump array 14*14</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Before the underfilll we check the electric function .All are good ones .</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">But after curing , some phone failed because "can not power on ", and some</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">failed for "check SIM card ", the defect sample is closed to 3%. I think</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">"check card "issue" may caused by the underfill material emission which</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">cover the SIM card lead .</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">But I can not get any idea for further.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Thanks</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">Tony</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">[This e-mail is confidential and may also be privileged. If you are not the</FONT></SPAN>
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========================================================================Date: Tue, 20 Nov 2001 10:16:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: BGA bone of contention
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As I know, 80% of the smallest ball size or preferably the same size
should be as the stencil aperture size not as the pad size.
> -----Original Message-----
> From: Tom Colby [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 5:42 PM
> To: [log in to unmask]
> Subject: Re: [TN] BGA bone of contention
>
> The rule of thumb, as I understand it, is 80% of the smallest ball
> size or
> preferably the same size as the substrate land. The object being to
> control
> the collapse of the solderball.
>
> If the minimum ball size is 0.35mm, how can you (or Mortorola) justify
> a
> pad size of 0.4-0.5mm?
>
> At 10:40 AM 11/19/01 -0600, you wrote:
> >Date: Mon, 19 Nov 2001 07:42:59 -0800
> >From: Denis Lefebvre <[log in to unmask]>
> >Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
> issue
> > (#2001-713)
> >
> >As a layout designer, I am surprised that they used such small land
> areas.
> >Motorola recommends a land of .40 to .50mm. IMO .28mm is
> insufficient.
> >See attached PDF from Motorola.
> >
> >Denis Lefebvre, C.I.D.
> >Senior PCB Designer
> >Finisar Corporation
> >(408)542-3832
> >http://www.finisar.com
> >
> >At 10:16 AM 11/19/2001 -0500, you wrote:
> > >I'm not that far up in the food chain to know all of the
> particulars, but
> > >it wouldn't surprise me if that were the case.
> > >
> > >What I'm looking for is comments on the increase of pad size and
> > >corroboration in my belief that it's the wrong solution to this
> problem.
> > >
> > >Tom
> > >
> > >At 04:20 AM 11/19/01 -0600, you wrote:
> > >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> > >>From: Eric Dawson <[log in to unmask]>
> > >>Subject: Re: BGA bone of contention
> > >>
> > >>Hi Tom,
> > >>Are you wave soldering the other side of the board with the reflow
> soldered
> > >>bga.s on top? I have come across this practice and it definitely
> disturbs
> > >>the bga joints causing opens which cannot be detected by ordinary
> X ray
> > >>inspection.
> > >>Hope this helps.
> > >>Regards
> > >>Eric Dawson
> > >>
> > >> > -----Original Message-----
> > >> > From: Tom Colby [SMTP:[log in to unmask]]
> > >> > Sent: Friday, November 16, 2001 8:47 PM
> > >> > To: [log in to unmask]
> > >> > Subject: [TN] BGA bone of contention
> > >> >
> > >> > Help me out with this technetters,
> > >> >
> > >> > The problem: BGA opens on a HASL board.
> > >> >
> > >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball
> size of
> > >> > 0.35/0.65. Substrate land size unknown. Footprint designed with
> a
> > pad of
> > >> > 0.28mm.
> > >> >
> > >> > Management's solution is to increase the pad size to 0.4mm. I
> say to
> > look
> > >> > elsewhere in the process for the problem.
> > >> >
> > >> > I'd like to hear the opinions of my esteemed colleagues. What
> do you say
> > >> > folks?
> > >> >
> > >> > Thanks in advance,
> > >> >
> > >> > Tom
> > >> >
> > >> >
> >
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<P><SPAN LANG="en-us"><FONT COLOR="#0000FF" SIZE=2 FACE="Times New Roman">As I know, 80% of the smallest ball size or preferably the same size should be as the stencil aperture size not as the pad size.</FONT></SPAN></P>
<UL>
<P><SPAN LANG="en-us"><FONT SIZE=1 FACE="Arial">-----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">From: </FONT></B> <FONT SIZE=1 FACE="Arial">Tom Colby [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Sent: </FONT></B> <FONT SIZE=1 FACE="Arial">Monday, November 19, 2001 5:42 PM</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">To: </FONT></B> <FONT SIZE=1 FACE="Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><B><FONT SIZE=1 FACE="Arial">Subject: </FONT></B> <FONT SIZE=1 FACE="Arial"> Re: [TN] BGA bone of contention</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">The rule of thumb, as I understand it, is 80% of the smallest ball size or</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">preferably the same size as the substrate land. The object being to control</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">the collapse of the solderball.</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">pad size of 0.4-0.5mm?</FONT></SPAN>
</P>
<P><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">At 10:40 AM 11/19/01 -0600, you wrote:</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Date: Mon, 19 Nov 2001 07:42:59 -0800</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>From: Denis Lefebvre <[log in to unmask]></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> (#2001-713)</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>As a layout designer, I am surprised that they used such small land areas.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>See attached PDF from Motorola.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Denis Lefebvre, C.I.D.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Senior PCB Designer</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>Finisar Corporation</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>(408)542-3832</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">><U></U></FONT><U><FONT COLOR="#0000FF" SIZE=2 FACE="SimSun"><A HREF="http://www.finisar.com">http://www.finisar.com</A></FONT></U></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">>At 10:16 AM 11/19/2001 -0500, you wrote:</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >I'm not that far up in the food chain to know all of the particulars, but</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >it wouldn't surprise me if that were the case.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >What I'm looking for is comments on the increase of pad size and</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >corroboration in my belief that it's the wrong solution to this problem.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >Tom</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >At 04:20 AM 11/19/01 -0600, you wrote:</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Date: Mon, 19 Nov 2001 08:20:31 -0000</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>From: Eric Dawson <[log in to unmask]></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Subject: Re: BGA bone of contention</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Hi Tom,</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Are you wave soldering the other side of the board with the reflow soldered</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>bga.s on top? I have come across this practice and it definitely disturbs</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>the bga joints causing opens which cannot be detected by ordinary X ray</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>inspection.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Hope this helps.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Regards</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >>Eric Dawson</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > -----Original Message-----</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > From: Tom Colby [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Sent: Friday, November 16, 2001 8:47 PM</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > To: [log in to unmask]</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Subject: [TN] BGA bone of contention</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Help me out with this technetters,</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > The problem: BGA opens on a HASL board.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> pad of</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > 0.28mm.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Management's solution is to increase the pad size to 0.4mm. I say to</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> look</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > elsewhere in the process for the problem.</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > I'd like to hear the opinions of my esteemed colleagues. What do you say</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > folks?</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Thanks in advance,</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> > Tom</FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> >> ></FONT></SPAN>
<BR><SPAN LANG="en-us"><FONT SIZE=2 FACE="SimSun">> --------------------------------------------------------------------------</FONT></SPAN>
</P>
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========================================================================Date: Tue, 20 Nov 2001 11:47:26 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Mario,
Don't you carry out EMC/EMI test on your products to determine if they are
sensitive to incoming radiation? Try taking a few working examples along to
your local airport and ask to have them put through the X-ray machines a
few times, then see if they still work afterwards. Easier to do first than
doing a whole lot of theoretical research which may show nothing in the
end.
Good luck
Peter Duncan
Mario Dion
<mdion@MEDIAT To: [log in to unmask]
RIX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Is X-RAY can damaged Flash IC
<[log in to unmask] i.e. imbeded program ?
ORG>
11/19/01
11:21 PM
Please
respond to
"TechNet
E-Mail
Forum."
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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========================================================================Date: Tue, 20 Nov 2001 12:12:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Our std at BAE Systems was 90 deg C (194 F) for 1 hour, though since I have
achieved greater enlightenment, I would suggest that you have your boards
packed by your fab house in sealed bags with desiccant, you keep them in a
dry cabinet and that you don't open them until needed on the line. That way
you won't have to pre-bake them, and they won't have to go through an
avoidable thermal excursion.
Peter Duncan
Rick Howieson
<RHowieson@DELTAGRO To: [log in to unmask]
UPINC.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Pre-bake
11/20/01 01:41 AM
Please respond to
"TechNet E-Mail
Forum."
What is the recommended pre-bake of multilayer boards prior to insertion
and
wave. 221F for 1hour??? Or would this be a little extreme?
Thanks,
Rick
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========================================================================Date: Tue, 20 Nov 2001 13:02:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
A very big thanks to you all, especially Edward, Rummy, Hans, Jeff, Moonman
and many others for all the help and advice I've received on this topic. In
spite of Moonman's reaching near-critical mass to start with, this thread
became a rope, so there was obviously a lot of information and several
issues that were worth sharing.
I had a long and expensive discussion by phone with the fab house this
morning and they're proceeding with conventional sequential lamination of
the boards with selective plating of holes and pads. At each stage they
will grind the plated copper off the pads on each side of the laminated
stack to maintain thickness until they get to the final, through-hole
group, where the plating will be left to bring the outer surface copper
weight up to intended design thickness. They are now very confident about
being able to produce good boards, though why they couldn't have done all
this to start with and saved me a lot of grief and black marks, I can't
say.
I will follow up Hans's lead on plating holes only, not surface pads, as
this would obviously be an ideal solution for this type of board, as long
as the hole plating still connects well with the inner edge of the pads on
the outer layers. It sounds as though it will save a lot of process time
and reduce risk by removing the unnecessary filling and grinding
operations, which are what has extended the time of the third attempt to
make these boards.
I join those who have gone before me in being in the position of having
received tremendous support, and no small amount of valuable help. My
heartfelt gratitude and thanks to all the TNagers for their generosity.
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Over-etch II
<[log in to unmask]>
11/20/01 02:09 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass
Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The
down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Tue, 20 Nov 2001 13:40:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hmmm! I can't see anything in your points 1 to 3 that would directly cause
you any trouble, and the conductive residues I had in mind ranged from
ionic contaminants on the surfaces to any solder balls that might have
become lodged underneath.
You didn't answer if you've tried testing at elevated temperature prior to
underfilling, and one thing I didn't ask (because I 99.99...% know the
answer) is are your devices hermetically sealed? I'ld try doing a
cross-section of some of the BGA's that failed after underfilling and see
if any of the epoxy has got inside and damaged anything.
More things spring to mind - like did you bake out the assemblies prior to
underfilling? The Dexter Hysol (sorry, Loctite) underfill that I use
recommends pre-baking of assemblies prior to underfilling. If the BGA's
have been out of their bag longer than a couple of days before
underfilling, they have probably absorbed a lot of moisture. I can't say
for sure what effect heating moisture-laden components to 120 or even 150
deg for 20 minutes or so would have, but your 3% may have suffered some
delam at some point. Or it may be warping and breaking/losing contact and
underfill is getting between the contact surfaces and isolating them.
Cross-sectioning and analysis should show this up too.
About tapped out of ideas again for now. Good luck with your search for a
cause - I'ld be interested in hearing what you find.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] No power on after underfill
TechNet
<[log in to unmask]
ORG>
11/20/01
08:58 AM
Please
respond to
"TechNet
E-Mail
Forum."
1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and the
solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill 50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no effective
4. what is conductive residues when we applying no-clean soldering process
?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony
-----Original Message-----
From: <Peter George Duncan> [SMTP:[log in to unmask]]
Sent: Monday, November 19, 2001 10:27 AM
To: [log in to unmask]
Subject: Re: [TN] No power on after underfill
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably doesn't
matter. The main thing I can think of that would cause your problem is
the
thermal excursions needed to apply and cure the underfill. Am I
correct to
say that the boards passed test at room temperature before the
underfill is
applied?
You may have a manufacturing problem where the balls make contact
enough to
pass test, but fail at elevated temperature. I would try testing the
boards
at 100 or 115 degrees C prior to underfilling them and see if they
still
pass. If they do, but fail again after underfilling, then the problem
is
probably related to your underfilling process. It is quite easy to
apply
too much if you're not using an automated process or have not
correctly
calculated the amount of material to apply. It does flow more prior to
curing at curing temperature, and if it's getting into nearby
interface
contacts as a result, you will need to look at damming the area around
the
BGA with a peelable masking to contain the underfill until it's cured,
or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have any
conductive residues left on the board, especially if you use no-clean
soldering processes, they may be picked up by the underfill and
there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance of
the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No power on
after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
3513
and the curing condition is 115C , 15 minutes , the BGA' s package is
below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good
ones .
But after curing , some phone failed because "can not power on ", and
some
failed for "check SIM card ", the defect sample is closed to 3%. I
think
"check card "issue" may caused by the underfill material emission
which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
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========================================================================Date: Tue, 20 Nov 2001 13:53:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
A very big thanks to you all, especially Edward, Rummy, Hans, Jeff, Moonman
and many others for all the help and advice I've received on this topic. In
spite of Moonman's reaching near-critical mass to start with, this thread
became a rope, so there was obviously a lot of information and several
issues that were worth sharing.
I had a long and expensive discussion by phone with the fab house this
morning and they're proceeding with conventional sequential lamination of
the boards with selective plating of holes and pads. They are now very
confident about being able to produce good boards, though why they couldn't
have done all this to start with and saved me a lot of grief and black
marks, I can't say.
I will follow up Hans's lead on plating holes only, not surface pads, as
this would obviously be an ideal solution for this type of board, as long
as the hole plating still connects well with the inner edge of the pads on
the outer layers. It sounds as though it will save a lot of process time
and reduce risk by removing the unnecessary filling and grinding
operations.
I join those who have gone before me in being in the position of having
received tremendous support, and no small amount of valuable help. My
heartfelt gratitude and thanks to all the TNagers for their generosity.
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Over-etch II
<[log in to unmask]>
11/20/01 02:09 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass
Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The
down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Mon, 19 Nov 2001 22:29:55 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: BGA voids
In-Reply-To: <72F8793F1F00D411BE2D00805FA7C0EBCD7B38@DATRON1>
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How would one rework an assembly with micro BGA voiding due to several
micro vias on pad?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some
sort of Peanut oil... but I can't remember for sure... Those were my
High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the
bear the heat of soldering well?
----- Original Message -----
From: Bob Willis <mailto:[log in to unmask]>
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the
years gone bye after it appeared in and Italian PCB specification I was
asked to review. After some testing I did it ended up in the IEC
specification.
The same oil can be used effectivly for outgassing tests with via in
pad. In the last test I did with ten scrap boards dfrom different
suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias
is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
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<div class=Section1>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>How would one rework an assembly with
micro BGA voiding due to several micro <span class=SpellE>vias</span> on pad?<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><span class=SpellE><font size=2 color=navy face=Arial><span
style='font-size:10.0pt;font-family:Arial;color:navy'>Rgds</span></font></span><font
size=2 color=navy face=Arial><span style='font-size:10.0pt;font-family:Arial;
color:navy'>,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Peter<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'>-----Original Message-----<br>
<b><span style='font-weight:bold'>From:</span></b> TechNet
[mailto:[log in to unmask]] <b><span style='font-weight:bold'>On Behalf Of </span></b>Brooks,Bill<br>
<b><span style='font-weight:bold'>Sent:</span></b> </span></font><st1:date
Month="11" Day="19" Year="2001"><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'>November 19, 2001</span></font></st1:date><font
size=2 face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour="8" Minute="48"><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'>8:48 AM</span></font></st1:time><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'><br>
<b><span style='font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style='font-weight:bold'>Subject:</span></b> Re: [TN] AW: [TN] BGA
voids</span></font></p>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="MS PGothic"><span
style='font-size:12.0pt'><o:p> </o:p></span></font></p>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 color=blue face=Arial><span
style='font-size:10.0pt;font-family:Arial;color:blue'>We used to make PCB's
back in the mid 1970's and used a fusing oil produced by Shell Oil in our
Hydro-squeegee. I want to say it was some sort of Peanut oil... but I can't
remember for sure... Those were my High School years... :)</span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 color=blue face=Arial><span
style='font-size:10.0pt;font-family:Arial;color:blue'>Good luck... - Bill
Brooks</span></font><o:p></o:p></p>
</div>
<blockquote style='margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>
<p class=MsoNormal style='mso-margin-top-alt:0in;margin-right:0in;margin-bottom:
12.0pt;margin-left:.5in'><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'>-----Original Message-----<br>
<b><span style='font-weight:bold'>From:</span></b> David Fish
[mailto:[log in to unmask]]<br>
<b><span style='font-weight:bold'>Sent:</span></b> </span></font><st1:date
Month="11" Day="19" Year="2001"><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'>Monday, November 19, 2001</span></font></st1:date><font
size=2 face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour="11" Minute="27"><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'>11:27 AM</span></font></st1:time><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'><br>
<b><span style='font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style='font-weight:bold'>Subject:</span></b> Re: [TN] AW: [TN] BGA
voids</span></font><o:p></o:p></p>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>Who are suppliers of inspection
quality oils [Canadian Balson??] the bear the heat of soldering well?</span></font><o:p></o:p></p>
</div>
<blockquote style='border:none;border-left:solid black 1.5pt;padding:0in 0in 0in 3.0pt;
margin-left:3.0pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>----- Original Message ----- <o:p></o:p></span></font></p>
</div>
<div style='font-color:black'>
<p class=MsoNormal style='margin-left:.5in;background:#E4E4E4'><b><font size=2
face=Arial><span style='font-size:10.0pt;font-family:Arial;font-weight:bold'>From:</span></font></b><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'> <a
href="mailto:[log in to unmask]" title="[log in to unmask]">Bob Willis</a> <o:p></o:p></span></font></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><b><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial;font-weight:bold'>To:</span></font></b><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'> <a
href="mailto:[log in to unmask]" title="[log in to unmask]">[log in to unmask]</a> <o:p></o:p></span></font></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><b><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial;font-weight:bold'>Sent:</span></font></b><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'> </span></font><st1:date
Month="11" Day="19" Year="2001"><font size=2 face=Arial><span style='font-size:
10.0pt;font-family:Arial'>Monday, November 19, 2001</span></font></st1:date><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'> </span></font><st1:time
Hour="4" Minute="45"><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>4:45 AM</span></font></st1:time><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><b><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial;font-weight:bold'>Subject:</span></font></b><font
size=2 face=Arial><span style='font-size:10.0pt;font-family:Arial'> Re: [TN]
AW: [TN] BGA voids<o:p></o:p></span></font></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="MS PGothic"><span
style='font-size:12.0pt'><o:p> </o:p></span></font></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>The outgassin test for blowhole in
printed boards was developed in the years gone bye after it appeared in and
Italian PCB specification I was asked to review. After some testing I did it
ended up in the IEC specification.</span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="Times New Roman"><span
style='font-size:12.0pt;font-family:"Times New Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>The same oil can be used effectivly
for outgassing tests with via in pad. In the last test I did with ten scrap
boards dfrom different suppliers 2 outgassed on the pads from the vias.</span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="Times New Roman"><span
style='font-size:12.0pt;font-family:"Times New Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>The procedure for through hole which
could and has been applied to vias is on my web site which is in the download
section.</span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="Times New Roman"><span
style='font-size:12.0pt;font-family:"Times New Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Arial><span
style='font-size:10.0pt;font-family:Arial'>Hope this helps.</span></font><o:p></o:p></p>
</div>
<div>
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<p class=MsoNormal style='margin-left:.5in'><font size=3 face="MS PGothic"><span
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Electronic Presentation Services<br>
</span></font><st1:address><st1:Street>2 Fourth Ave</st1:Street>, <st1:City>Chelmsford</st1:City></st1:address>,
<st1:place><st1:City>Essex</st1:City>, <st1:PostalCode>CM1 4HA</st1:PostalCode>
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href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</a><o:p></o:p></p>
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========================================================================Date: Tue, 20 Nov 2001 07:09:51 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
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If you have voiding from the via due to outgassing you could bake the board prior to rework.
You first should ask the question are the voids significant.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Peter Lee
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 6:29 AM
Subject: Re: [TN] BGA voids
How would one rework an assembly with micro BGA voiding due to several micro vias on pad?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil produced by Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut oil... but I can't remember for sure... Those were my High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the years gone bye after it appeared in and Italian PCB specification I was asked to review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In the last test I did with ten scrap boards dfrom different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
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<DIV><FONT face=Arial size=2>If you have voiding from the via due to outgassing
you could bake the board prior to rework.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>You first should ask the question are the voids
significant.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Peter Lee</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, 2001 6:29
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] BGA voids</DIV>
<DIV><BR></DIV>
<DIV class=Section1>
<P class=MsoNormal><FONT color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt">How would one rework
an assembly with micro BGA voiding due to several micro <SPAN
class=SpellE>vias</SPAN> on pad?<o:p></o:p></SPAN></FONT></P>
<P class=MsoNormal><FONT color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt"><o:p> </o:p></SPAN></FONT></P>
<P class=MsoNormal><SPAN class=SpellE><FONT color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt">Rgds</SPAN></FONT></SPAN><FONT
color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt">,<o:p></o:p></SPAN></FONT></P>
<P class=MsoNormal><FONT color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt">Peter<o:p></o:p></SPAN></FONT></P>
<P class=MsoNormal><FONT color=navy face=Arial size=2><SPAN
style="COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt"><o:p> </o:p></SPAN></FONT></P>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">-----Original
Message-----<BR><B><SPAN style="FONT-WEIGHT: bold">From:</SPAN></B> TechNet
[<A href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>] <B><SPAN
style="FONT-WEIGHT: bold">On Behalf Of </SPAN></B>Brooks,Bill<BR><B><SPAN
style="FONT-WEIGHT: bold">Sent:</SPAN></B> </SPAN></FONT><st1:date Year="2001"
Day="19" Month="11"><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">November 19,
2001</SPAN></FONT></st1:date><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"> </SPAN></FONT><st1:time
Minute="48" Hour="8"><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">8:48
AM</SPAN></FONT></st1:time><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"><BR><B><SPAN
style="FONT-WEIGHT: bold">To:</SPAN></B> <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><B><SPAN
style="FONT-WEIGHT: bold">Subject:</SPAN></B> Re: [TN] AW: [TN] BGA
voids</SPAN></FONT></P>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN style="FONT-SIZE: 12pt"><o:p> </o:p></SPAN></FONT></P>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT color=blue face=Arial
size=2><SPAN style="COLOR: blue; FONT-FAMILY: Arial; FONT-SIZE: 10pt">We used
to make PCB's back in the mid 1970's and used a fusing oil produced by Shell
Oil in our Hydro-squeegee. I want to say it was some sort of Peanut oil... but
I can't remember for sure... Those were my High School years...
:)</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT color=blue face=Arial
size=2><SPAN style="COLOR: blue; FONT-FAMILY: Arial; FONT-SIZE: 10pt">Good
luck... - Bill Brooks</SPAN></FONT><o:p></o:p></P></DIV>
<BLOCKQUOTE style="MARGIN-BOTTOM: 5pt; MARGIN-RIGHT: 0in; MARGIN-TOP: 5pt">
<P class=MsoNormal
style="MARGIN-BOTTOM: 12pt; MARGIN-LEFT: 0.5in; MARGIN-RIGHT: 0in; mso-margin-top-alt: 0in"><FONT
face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">-----Original
Message-----<BR><B><SPAN style="FONT-WEIGHT: bold">From:</SPAN></B> David
Fish [mailto:[log in to unmask]]<BR><B><SPAN
style="FONT-WEIGHT: bold">Sent:</SPAN></B> </SPAN></FONT><st1:date
Year="2001" Day="19" Month="11"><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">Monday, November 19,
2001</SPAN></FONT></st1:date><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"> </SPAN></FONT><st1:time
Minute="27" Hour="11"><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">11:27
AM</SPAN></FONT></st1:time><FONT face=Tahoma size=2><SPAN
style="FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"><BR><B><SPAN
style="FONT-WEIGHT: bold">To:</SPAN></B> [log in to unmask]<BR><B><SPAN
style="FONT-WEIGHT: bold">Subject:</SPAN></B> Re: [TN] AW: [TN] BGA
voids</SPAN></FONT><o:p></o:p></P>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">Who are suppliers of inspection
quality oils [Canadian Balson??] the bear the heat of soldering
well?</SPAN></FONT><o:p></o:p></P></DIV>
<BLOCKQUOTE
style="BORDER-BOTTOM: medium none; BORDER-LEFT: black 1.5pt solid; BORDER-RIGHT: medium none; BORDER-TOP: medium none; MARGIN: 5pt 0in 5pt 3pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 3pt; PADDING-RIGHT: 0in; PADDING-TOP: 0in">
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">----- Original
Message ----- <o:p></o:p></SPAN></FONT></P></DIV>
<DIV style="font-color: black">
<P class=MsoNormal
style="BACKGROUND: #e4e4e4; MARGIN-LEFT: 0.5in"><B><FONT face=Arial
size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: bold">From:</SPAN></FONT></B><FONT
face=Arial size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt"> <A
href="mailto:[log in to unmask]" [log in to unmask]>Bob Willis</A>
<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><B><FONT face=Arial
size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: bold">To:</SPAN></FONT></B><FONT
face=Arial size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt"> <A
href="mailto:[log in to unmask]" [log in to unmask]>[log in to unmask]</A>
<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><B><FONT face=Arial
size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: bold">Sent:</SPAN></FONT></B><FONT
face=Arial size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">
</SPAN></FONT><st1:date Year="2001" Day="19" Month="11"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">Monday, November
19, 2001</SPAN></FONT></st1:date><FONT face=Arial size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt"> </SPAN></FONT><st1:time
Minute="45" Hour="4"><FONT face=Arial size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">4:45
AM</SPAN></FONT></st1:time><FONT face=Arial size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt"><o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><B><FONT face=Arial
size=2><SPAN
style="FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: bold">Subject:</SPAN></FONT></B><FONT
face=Arial size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt"> Re:
[TN] AW: [TN] BGA voids<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN
style="FONT-SIZE: 12pt"><o:p> </o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">The outgassin
test for blowhole in printed boards was developed in the years gone bye
after it appeared in and Italian PCB specification I was asked to review.
After some testing I did it ended up in the IEC
specification.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">The same oil can
be used effectivly for outgassing tests with via in pad. In the last test
I did with ten scrap boards dfrom different suppliers 2 outgassed on the
pads from the vias.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">The procedure for
through hole which could and has been applied to vias is on my web site
which is in the download section.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face=Arial
size=2><SPAN style="FONT-FAMILY: Arial; FONT-SIZE: 10pt">Hope this
helps.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN style="FONT-SIZE: 12pt">Bob Willis<BR>Electronic Presentation
Services<BR></SPAN></FONT><st1:address><st1:Street>2 Fourth
Ave</st1:Street>, <st1:City>Chelmsford</st1:City></st1:address>,
<st1:place><st1:City>Essex</st1:City>, <st1:PostalCode>CM1
4HA</st1:PostalCode>
<st1:country-region>England</st1:country-region></st1:place><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN style="FONT-SIZE: 12pt">See us at APEX
2002</SPAN></FONT><FONT face="Times New Roman"><SPAN
style="FONT-FAMILY: 'Times New Roman'; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT>
<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN style="FONT-SIZE: 12pt"><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="Times New Roman"
size=3><SPAN
style="FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN style="FONT-SIZE: 12pt">Single solution to your seminar,
conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A><o:p></o:p></SPAN></FONT></P></DIV>
<BLOCKQUOTE
style="BORDER-BOTTOM: medium none; BORDER-LEFT: black 1.5pt solid; BORDER-RIGHT: medium none; BORDER-TOP: medium none; MARGIN: 5pt 0in 5pt 3pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 3pt; PADDING-RIGHT: 0in; PADDING-TOP: 0in">
<P class=MsoNormal style="MARGIN-LEFT: 0.5in"><FONT face="MS PGothic"
size=3><SPAN
style="FONT-SIZE: 12pt">---<o:p></o:p></SPAN></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_001D_01C17192.590D6AE0--
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========================================================================Date: Tue, 20 Nov 2001 09:31:14 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit
Bravo, Peter, for the obvious answer. I have been thoroughly opposed to
prebaking ever since I first started using G-10 PTH boards in the 1960s.
Not only should it not be necessary, it is, as you say, an extra and
unnecessary thermal cycle AND it causes sufficient oxidation of the
finish on the pads (including the nickel under the porous gold with ENIG
or electrolytic) that you are giving the flux a lot of extra work to do.
Unfortunately, not all PCB fab shops realise that they, too, sometimes
ship boards with built-in blow-holing etc., so proper packing (rare) is
not going to help in these cases. However, this is one of those cases
where prevention is better than cure.
IMHO, purchasing contracts for bare boards should include a clause,
especially for value-added multilayers, to the effect that any boards
that are up to n months old that are removed from their original
packaging and blowholes occur during soldering within, say, 24 hours
shall be replaced free-of-charge. This will place the ball fairly in the
PCB fab's court and we'll get better boards which are correctly packed.
This will mean the demise of polyethylene as a packing material, because
it is as porous to humidity as a kitchen sieve. To boot, it will make a
small contribution to a better environment because if you add up all the
energy required to heat up x million boards per day throughout the world
some 80°C for an hour, it will represent so much less CO2 (and reduce
costs).
Voila, Brian can now get off his soap-box :-)
Brian
Rick Howieson wrote:
>
> What is the recommended pre-bake of multilayer boards prior to insertion and
> wave. 221F for 1hour??? Or would this be a little extreme?
> Thanks,
> Rick
>
> ---------------------------------------------------------------------------------
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========================================================================Date: Tue, 20 Nov 2001 17:03:48 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA voids
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Peter,
I can't help you with how to rework a micro BGA, never having dealt with
them, but I ask a question: Are you wanting to rework them just because
they have voids, or have the voids broken through the side of the balls?
Voids in themselves are not necessarily to be taken as being defects unless
they do break through.
Having had larger BGA's reworked, I can say that changing BGA's is an
expensive pain and better avoided if possible.
My tuppence worth only
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] BGA voids
<[log in to unmask]
ORG>
11/20/01
02:29 PM
Please
respond to
"TechNet
E-Mail
Forum."
How would one rework an assembly with micro BGA voiding due to several
micro vias on pad?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some
sort of Peanut oil... but I can't remember for sure... Those were my
High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??]
the bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed
in the years gone bye after it appeared in and Italian PCB
specification I was asked to review. After some testing I did it
ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with
via in pad. In the last test I did with ten scrap boards dfrom
different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied
to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
---
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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========================================================================Date: Tue, 20 Nov 2001 16:02:00 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anil Kher <[log in to unmask]>
Subject: O. MATERIALS. TO : VALUED ASSOCIATES.
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Dear Sir ,
Due to space problem we have now moved from G-4A,Kalkaji to the following address.:-
BHARTI TELETECH LTD.
C-87, BASEMENT
NEAR PETROL PUMP/
POLICE STATION
KALKAJI
NEW DELHI – 19.
TELPHONE NO. : 6233113
CONTACT PERSON: MR. VIJAY SINGH NEGI.
WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING TO LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
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========================================================================Date: Tue, 20 Nov 2001 06:45:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Steve
I got to observe some CCGA work several years back, and the one big gotcha is that they are much less robust than a BGA part - the columns bend pretty easy. Not that I'm saying you should juggle BGAs - but treat these puppies like you would a QFP. And as they are heavy - make sure you have a good vacuum pen...
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/19/01 08:22PM >>>
Hi all!
May be getting the opportunity to assemble some boards with CCGA's on them.
Don't have any direct experience with these puppies. Downloaded IBM's
application *.PDF on assembling and reworking them (it's pretty good by the
way), and seems that basically, you would do the same thing assembling these
guys as you do when working with BGA's...am I over-simplifiying things too
much?
Any advice, or "gotcha's" I should look out for would be appreciated...
As always, thanks a bunch!!!
-Steve Gregory-
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========================================================================Date: Tue, 20 Nov 2001 07:22:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Mario
I agree with Dave,, check out for yourself if the data is getting corrupted.
I worked for a company a few years ago were we had a similar problem with
EEPROMS we would send to customers for program upgrades. The customer
would get them and they wouldn't function. Verifying the programs would
show that the data was corrupted. The same thing would happen with UV-
erasable EPLDs.
As a test we ran many samples of programmed devices through our Circuit
Scan machine with no effect but when run through the Airport's Machines we
did have some random failures. The manufacture couldn't explain it.
We started packaging spares in a heavier silver ESD packaging and the
problem mysteriously went away.
We never had a problem with completely assembled units, possibly because
they were in metal cabinets.
I don't know if this helps at all but good luck
Hope you solve the problem.
---------------------------------------------------------------------------------
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========================================================================Date: Tue, 20 Nov 2001 07:24:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Sorry I meant Peter Duncan not Dave.. I work with a Dave.
Again Good luck
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========================================================================Date: Tue, 20 Nov 2001 08:32:54 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Fjelstad <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_f4.1299e863.292bb586_boundary"
--part1_f4.1299e863.292bb586_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hello Tony,
You may wish to look at using components which do not require underfill such
as the compliant package structures manufactured by licensees of Tessera's
technologies
(most of the major semiconductor supplier make such offerings). They are cost
competitive when you consider all of the extra steps you avoid (and in light
of the problems you are experiencing). Sometimes apparently cheaper solutions
are more expensive when viewed at the system level. It is a value/price
consideration. If you are not familiar with their technology you can visit
their web site to learn more.
www.tessera.com.
Kind regards,
Joe
--part1_f4.1299e863.292bb586_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Tony,
<BR>
<BR>You may wish to look at using components which do not require underfill such as the compliant package structures manufactured by licensees of Tessera's technologies
<BR>(most of the major semiconductor supplier make such offerings). They are cost competitive when you consider all of the extra steps you avoid (and in light of the problems you are experiencing). Sometimes apparently cheaper solutions are more expensive when viewed at the system level. It is a value/price consideration. If you are not familiar with their technology you can visit their web site to learn more.
<BR>
<BR>www.tessera.com.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>
--part1_f4.1299e863.292bb586_boundary--
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========================================================================Date: Tue, 20 Nov 2001 08:46:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbedded program ?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Greetings and Hallucinations,
Perhaps it isn't the X-rays but the strong EM field the X-ray machine is
generating that could be causing the trouble? I know we used to kill credit
cards in the ole physics lab with some of the coils we used. This is a
blind guess.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Andre Leclair [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 8:22 AM
To: [log in to unmask]
Subject: Re: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Mario
I agree with Dave,, check out for yourself if the data is getting corrupted.
I worked for a company a few years ago were we had a similar problem with
EEPROMS we would send to customers for program upgrades. The customer
would get them and they wouldn't function. Verifying the programs would
show that the data was corrupted. The same thing would happen with UV-
erasable EPLDs.
As a test we ran many samples of programmed devices through our Circuit
Scan machine with no effect but when run through the Airport's Machines we
did have some random failures. The manufacture couldn't explain it.
We started packaging spares in a heavier silver ESD packaging and the
problem mysteriously went away.
We never had a problem with completely assembled units, possibly because
they were in metal cabinets.
I don't know if this helps at all but good luck
Hope you solve the problem.
----------------------------------------------------------------------------
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========================================================================Date: Tue, 20 Nov 2001 08:49:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
MIME-Version: 1.0
Content-Type: text/plain
Hi Steve,
there is something you should consider about CCGAs, and that is $$$!!! You
must read this literally and make sure that everybody in the company, from
the Incoming inspectors, through the kitting persons and to the operators
know it. If you run a small prototype batch, contact the supplier (or worse,
the broker) and make sure the parts come in the original trays and they are
properly strapped. If you end up getting the parts in hand made boxes,
because the broker divided the stuff from one tray between several
customers, there are big chances that you get them with bent leads. And if
the leads are bent more than 10 degrees, they exceed the elastic zone and
there is no point in trying to straighten them up, the reliability is gone.
Of course, they are reworkable, the manufacturer can replace the columns,
but the cost is almost like buying new parts.
Besides that, make sure that the design of the land pattern complies with
the guidelines in the IBM document you have. We once had to assemble on pads
that were a lot smaller and don't ask me how I had them pass the QA.
Assembly concerns:
- if you cannot see the leads during machine inspection, a tough job, since
the body is white, go with the body check, you can't miss
- some packages are pretty high, more than the 10mm that Fuji moves around
with the regular 26mm long nozzles, so, if you have some IP3s, or if this
applies to your machines, you might have to buy the shorter nozzles.
That's pretty much it. No other particular concerns, other than making sure
the side with this part is the last one to assemble, hehehe. Or the good old
DFM.
Have fun,
Ioan
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 7:23 PM
> To: [log in to unmask]
> Subject: [TN] CCGA's, the good, the bad, and the ugly...
>
> Hi all!
>
> May be getting the opportunity to assemble some boards with CCGA's on
> them.
> Don't have any direct experience with these puppies. Downloaded IBM's
> application *.PDF on assembling and reworking them (it's pretty good by
> the
> way), and seems that basically, you would do the same thing assembling
> these
> guys as you do when working with BGA's...am I over-simplifiying things too
> much?
>
> Any advice, or "gotcha's" I should look out for would be appreciated...
>
> As always, thanks a bunch!!!
>
> -Steve Gregory-
>
> --------------------------------------------------------------------------
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========================================================================Date: Tue, 20 Nov 2001 08:59:21 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Fjelstad <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
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Hello Mario
It is good question to ask but look about and you will note that there are
tens of thousands of digital devices with flash memory run through x-ray
every day (cell phones, cameras, MP3, memory cards) at airports around the
globe every day. We would likely have had bell ringing by now if there were
any significant risk.
Kind regards,
Joe
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Mario
<BR>
<BR>It is good question to ask but look about and you will note that there are tens of thousands of digital devices with flash memory run through x-ray every day (cell phones, cameras, MP3, memory cards) at airports around the globe every day. We would likely have had bell ringing by now if there were any significant risk.
<BR>
<BR>Kind regards,
<BR>Joe </FONT></HTML>
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========================================================================Date: Tue, 20 Nov 2001 06:38:32 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
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An 80% paste aperture certainly makes more sense than an 80% land. I'm just
trying to answer answer Tom's original question- "...BGA opens on a HASL
board."..."What I'm looking for is comments on the increase of pad size and
corroboration in my belief that it's the wrong solution to this problem."
They are using 80% lands now - and they're having problems. Motorola
recommends a .4mm land. I don't need to justify anything... I believe I've
already done that. Tom - you asked for comments, you got mine.. and
Motorolas'. Do with it as you please.
-Denis
At 10:16 AM 11/20/2001 +0800, you wrote:
>As I know, 80% of the smallest ball size or preferably the same size
>should be as the stencil aperture size not as the pad size.
>-----Original Message----- From: Tom Colby
>[SMTP:[log in to unmask]] Sent: Monday, November 19, 2001 5:42
>PM To: [log in to unmask] Subject: Re: [TN] BGA bone of
>contention
>
>The rule of thumb, as I understand it, is 80% of the smallest ball size
>or preferably the same size as the substrate land. The object being to
>control the collapse of the solderball.
>
>If the minimum ball size is 0.35mm, how can you (or Mortorola) justify
>a pad size of 0.4-0.5mm?
>
>At 10:40 AM 11/19/01 -0600, you wrote: >Date: Mon, 19 Nov 2001
>07:42:59 -0800 >From: Denis Lefebvre
><[log in to unmask]> >Subject: Re: TechNet Digest - 18 Nov 2001
>to 19 Nov 2001 - Special issue > (#2001-713) > >As a layout
>designer, I am surprised that they used such small land areas. >Motorola
>recommends a land of .40 to .50mm. IMO .28mm is insufficient. >See
>attached PDF from Motorola. > >Denis Lefebvre, C.I.D. >Senior PCB
>Designer >Finisar
>Corporation >(408)542-3832
> ><http://www.finisar.com>http://www.finisar.com > >At 10:16 AM
>11/19/2001 -0500, you wrote: > >I'm not that far up in the food chain to
>know all of the particulars, but > >it wouldn't surprise me if that were
>the case. > > > >What I'm looking for is comments on the increase of pad
>size and > >corroboration in my belief that it's the wrong solution to
>this problem. > > > >Tom > > > >At 04:20 AM 11/19/01 -0600, you
>wrote: > >>Date: Mon, 19 Nov 2001 08:20:31 -0000 > >>From: Eric
>Dawson <[log in to unmask]> > >>Subject: Re: BGA bone of
>contention > >> > >>Hi Tom, > >>Are you wave soldering the other side
>of the board with the reflow soldered > >>bga.s on top? I have come
>across this practice and it definitely disturbs > >>the bga joints
>causing opens which cannot be detected by ordinary X
>ray > >>inspection. > >>Hope this helps. > >>Regards > >>Eric
>Dawson > >> > >> > -----Original Message----- > >> > From: Tom Colby
>[SMTP:[log in to unmask]] > >> > Sent: Friday, November 16, 2001 8:47
>PM > >> > To: [log in to unmask] > >> > Subject: [TN] BGA bone of
>contention > >> > > >> > Help me out with this
>technetters, > >> > > >> > The problem: BGA opens on a HASL
>board. > >> > > >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm
>pitch, ball size of > >> > 0.35/0.65. Substrate land size unknown.
>Footprint designed with a > pad of > >> > 0.28mm. > >> > > >> >
>Management's solution is to increase the pad size to 0.4mm. I say to >
>look > >> > elsewhere in the process for the problem. > >> > > >> > I'd
>like to hear the opinions of my esteemed colleagues. What do you
>say > >> > folks? > >> > > >> > Thanks in advance, > >> > > >> >
>Tom > >> > > >> > >
>--------------------------------------------------------------------------
>
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<html>
An 80% paste aperture certainly makes more sense than an 80% land. I'm
just trying to answer answer Tom's original question-
"...<font face="SimSun" size=2>BGA opens on a HASL
board.</font>"<font face="SimSun" size=2>...</font>"<font face="SimSun" size=2>What
I'm looking for is comments on the increase of pad size and</font>
<font face="SimSun" size=2>corroboration in my belief that it's the wrong
solution to this problem." </font>They are using 80% lands now - and
they're having problems. Motorola recommends a .4mm land. I don't need to
justify anything... I believe I've already done that. Tom - you asked for
comments, you got mine.. and Motorolas'. Do with it as you please.<br>
-Denis<br>
At 10:16 AM 11/20/2001 +0800, you wrote:<br><br>
<blockquote type=cite class=cite cite><font face="Times New Roman, Times" size=2 color="#0000FF">As
I know, 80% of the smallest ball size or preferably the same size should
be as the stencil aperture size not as the pad size.<br>
</font>
<ul><font face="Arial, Helvetica" size=1>
-----Original Message-----</font>
<font face="Arial, Helvetica" size=1><b>
From: </b></font> <font face="Arial, Helvetica" size=1>Tom Colby
[SMTP:[log in to unmask]]</font>
<font face="Arial, Helvetica" size=1><b>
Sent: </b></font> <font face="Arial, Helvetica" size=1>Monday,
November 19, 2001 5:42 PM</font>
<font face="Arial, Helvetica" size=1><b>
To: </b></font>
<font face="Arial, Helvetica" size=1>[log in to unmask]</font>
<font face="Arial, Helvetica" size=1><b>
Subject: </b></font> <font face="Arial, Helvetica" size=1> Re: [TN] BGA bone of contention</font> <br><br>
<font face="SimSun" size=2>
The rule of thumb, as I understand it, is 80% of the smallest ball size or</font> <font face="SimSun" size=2>
preferably the same size as the substrate land. The object being to control</font> <font face="SimSun" size=2>
the collapse of the solderball.</font> <br><br>
<font face="SimSun" size=2>
If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a</font> <font face="SimSun" size=2>
pad size of 0.4-0.5mm?</font> <br><br>
<font face="SimSun" size=2>
At 10:40 AM 11/19/01 -0600, you wrote:</font> <font face="SimSun" size=2>
>Date: Mon, 19 Nov 2001 07:42:59 -0800</font> <font face="SimSun" size=2>
>From: Denis Lefebvre <[log in to unmask]></font> <font face="SimSun" size=2>
>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue</font> <font face="SimSun" size=2>
> (#2001-713)</font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>As a layout designer, I am surprised that they used such small land areas.</font> <font face="SimSun" size=2>
>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.</font> <font face="SimSun" size=2>
>See attached PDF from Motorola.</font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>Denis Lefebvre, C.I.D.</font> <font face="SimSun" size=2>
>Senior PCB Designer</font> <font face="SimSun" size=2>
>Finisar Corporation</font> <font face="SimSun" size=2>
>(408)542-3832</font> <font face="SimSun" size=2>
></font><a href="http://www.finisar.com"><font face="SimSun" size=2 color="#0000FF"><u>http://www.finisar.com</a></u></font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>At 10:16 AM 11/19/2001 -0500, you wrote:</font> <font face="SimSun" size=2>
> >I'm not that far up in the food chain to know all of the particulars, but</font> <font face="SimSun" size=2>
> >it wouldn't surprise me if that were the case.</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >What I'm looking for is comments on the increase of pad size and</font> <font face="SimSun" size=2>
> >corroboration in my belief that it's the wrong solution to this problem.</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >Tom</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >At 04:20 AM 11/19/01 -0600, you wrote:</font> <font face="SimSun" size=2>
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000</font> <font face="SimSun" size=2>
> >>From: Eric Dawson <[log in to unmask]></font> <font face="SimSun" size=2>
> >>Subject: Re: BGA bone of contention</font> <font face="SimSun" size=2>
> >></font> <font face="SimSun" size=2>
> >>Hi Tom,</font> <font face="SimSun" size=2>
> >>Are you wave soldering the other side of the board with the reflow soldered</font> <font face="SimSun" size=2>
> >>bga.s on top? I have come across this practice and it definitely disturbs</font> <font face="SimSun" size=2>
> >>the bga joints causing opens which cannot be detected by ordinary X ray</font> <font face="SimSun" size=2>
> >>inspection.</font> <font face="SimSun" size=2>
> >>Hope this helps.</font> <font face="SimSun" size=2>
> >>Regards</font> <font face="SimSun" size=2>
> >>Eric Dawson</font> <font face="SimSun" size=2>
> >></font> <font face="SimSun" size=2>
> >> > -----Original Message-----</font> <font face="SimSun" size=2>
> >> > From: Tom Colby [SMTP:[log in to unmask]]</font> <font face="SimSun" size=2>
> >> > Sent: Friday, November 16, 2001 8:47 PM</font> <font face="SimSun" size=2>
> >> > To: [log in to unmask]</font> <font face="SimSun" size=2>
> >> > Subject: [TN] BGA bone of contention</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Help me out with this technetters,</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > The problem: BGA opens on a HASL board.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of</font> <font face="SimSun" size=2>
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a</font> <font face="SimSun" size=2>
> pad of</font> <font face="SimSun" size=2>
> >> > 0.28mm.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Management's solution is to increase the pad size to 0.4mm. I say to</font> <font face="SimSun" size=2>
> look</font> <font face="SimSun" size=2>
> >> > elsewhere in the process for the problem.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you say</font> <font face="SimSun" size=2>
> >> > folks?</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Thanks in advance,</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Tom</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> --------------------------------------------------------------------------</font> <br><br>
<font face="SimSun" size=2>
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Technet Mail List provided as a free service by IPC using LISTSERV 1.8d</font> <font face="SimSun" size=2>
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Please visit IPC web site (</font><a href="http://www.ipc.org/html/forum.htm"><font face="SimSun" size=2 color="#0000FF"><u>http://www.ipc.org/html/forum.htm</a></u></font><font face="SimSun" size=2>) for additional</font> <font face="SimSun" size=2>
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========================================================================Date: Tue, 20 Nov 2001 09:45:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Circuit Repair Facility
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jan,
We may be able to help with either the equipment or the service.
For services see: http://www.circuittechctr.com/services/gold.htm
For equipment see: http://www.circuittechctr.com/products/115-1702.htm
Please contact us offline for additional info.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: Jan Satterfield [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 5:41 PM
To: [log in to unmask]
Subject: [TN] Circuit Repair Facility
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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========================================================================Date: Tue, 20 Nov 2001 09:54:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
If the clamping/baking doesn't remove the warp on the first try, you could
give it one more try. What we do in these cases is to slightly bend a pair
of tool steel bars. We then clamp these bars to the warped edge bowing that
edge in the opposite direction. Go through the baking cycle again and cross
your fingers.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 9:50 PM
To: [log in to unmask]
Subject: Re: [TN] Board Warp
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board
Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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========================================================================Date: Tue, 20 Nov 2001 20:22:10 +0530
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Anil Kher wrote:
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> Due to space problem we have now moved from G-4A,Kalkaji to the following address.:-
>
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> TELPHONE NO. : 6233113
>
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>
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========================================================================Date: Tue, 20 Nov 2001 09:44:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: Bob Willis <[log in to unmask]>
Subject: Re: Pre-bake
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I to have never suggested that baking is right or necessary for standard boards. It should not be required on a well produced board with satisfactory plating thickness.
The old oil test is simply used were there is a debate on the quality and demostrating the route cause. Brian could of course reserect his faamouse Plop O Meter for testing for out gassing ?
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
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----- Original Message -----
From: Brian Ellis
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 7:31 AM
Subject: Re: [TN] Pre-bake
Bravo, Peter, for the obvious answer. I have been thoroughly opposed to
prebaking ever since I first started using G-10 PTH boards in the 1960s.
Not only should it not be necessary, it is, as you say, an extra and
unnecessary thermal cycle AND it causes sufficient oxidation of the
finish on the pads (including the nickel under the porous gold with ENIG
or electrolytic) that you are giving the flux a lot of extra work to do.
Unfortunately, not all PCB fab shops realise that they, too, sometimes
ship boards with built-in blow-holing etc., so proper packing (rare) is
not going to help in these cases. However, this is one of those cases
where prevention is better than cure.
IMHO, purchasing contracts for bare boards should include a clause,
especially for value-added multilayers, to the effect that any boards
that are up to n months old that are removed from their original
packaging and blowholes occur during soldering within, say, 24 hours
shall be replaced free-of-charge. This will place the ball fairly in the
PCB fab's court and we'll get better boards which are correctly packed.
This will mean the demise of polyethylene as a packing material, because
it is as porous to humidity as a kitchen sieve. To boot, it will make a
small contribution to a better environment because if you add up all the
energy required to heat up x million boards per day throughout the world
some 80°C for an hour, it will represent so much less CO2 (and reduce
costs).
Voila, Brian can now get off his soap-box :-)
Brian
Rick Howieson wrote:
>
> What is the recommended pre-bake of multilayer boards prior to insertion and
> wave. 221F for 1hour??? Or would this be a little extreme?
> Thanks,
> Rick
>
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<DIV><FONT face=Arial size=2>I to have never suggested that baking is right or
necessary for standard boards. It should not be required on a well produced
board with satisfactory plating thickness.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The old oil test is simply used were there is a
debate on the quality and demostrating the route cause. Brian could of course
reserect his faamouse Plop O Meter for testing for out gassing ?</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Brian
Ellis</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, 2001 7:31
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] Pre-bake</DIV>
<DIV><BR></DIV>Bravo, Peter, for the obvious answer. I have been thoroughly
opposed to<BR>prebaking ever since I first started using G-10 PTH boards in
the 1960s.<BR>Not only should it not be necessary, it is, as you say, an extra
and<BR>unnecessary thermal cycle AND it causes sufficient oxidation of
the<BR>finish on the pads (including the nickel under the porous gold with
ENIG<BR>or electrolytic) that you are giving the flux a lot of extra work to
do.<BR>Unfortunately, not all PCB fab shops realise that they, too,
sometimes<BR>ship boards with built-in blow-holing etc., so proper packing
(rare) is<BR>not going to help in these cases. However, this is one of those
cases<BR>where prevention is better than cure.<BR><BR>IMHO, purchasing
contracts for bare boards should include a clause,<BR>especially for
value-added multilayers, to the effect that any boards<BR>that are up to n
months old that are removed from their original<BR>packaging and blowholes
occur during soldering within, say, 24 hours<BR>shall be replaced
free-of-charge. This will place the ball fairly in the<BR>PCB fab's court and
we'll get better boards which are correctly packed.<BR>This will mean the
demise of polyethylene as a packing material, because<BR>it is as porous to
humidity as a kitchen sieve. To boot, it will make a<BR>small contribution to
a better environment because if you add up all the<BR>energy required to heat
up x million boards per day throughout the world<BR>some 80°C for an hour, it
will represent so much less CO2 (and reduce<BR>costs).<BR><BR>Voila, Brian can
now get off his soap-box :-)<BR><BR>Brian<BR><BR>Rick Howieson
wrote:<BR>><BR>> What is the recommended pre-bake of multilayer boards
prior to insertion and<BR>> wave. 221F for 1hour??? Or would this be a
little extreme?<BR>> Thanks,<BR>> Rick<BR>><BR>>
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========================================================================Date: Tue, 20 Nov 2001 09:53:09 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: No power on after underfill
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One of the reasons that people bake boards prior to underfilling is to overcome moisture and outgassing. Recent work in the UK has demonstrated that moisture comes out of the solder mask and can cause voiding in the underfill and cause part movement if a no flow material is used as the solder joints will not have been produced at this stage.
I am working with the NPL in UK on a solder mask project at the moment, if its of interest check out the NPL web site www.npl.co.uk/npl/ei/studio/
I have produces some video clips showing the outgassing from masks which I can put on line if people wish in RealPlayer format.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Peter George [log in to unmask]
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 5:40 AM
Subject: Re: [TN] No power on after underfill
Hmmm! I can't see anything in your points 1 to 3 that would directly cause
you any trouble, and the conductive residues I had in mind ranged from
ionic contaminants on the surfaces to any solder balls that might have
become lodged underneath.
You didn't answer if you've tried testing at elevated temperature prior to
underfilling, and one thing I didn't ask (because I 99.99...% know the
answer) is are your devices hermetically sealed? I'ld try doing a
cross-section of some of the BGA's that failed after underfilling and see
if any of the epoxy has got inside and damaged anything.
More things spring to mind - like did you bake out the assemblies prior to
underfilling? The Dexter Hysol (sorry, Loctite) underfill that I use
recommends pre-baking of assemblies prior to underfilling. If the BGA's
have been out of their bag longer than a couple of days before
underfilling, they have probably absorbed a lot of moisture. I can't say
for sure what effect heating moisture-laden components to 120 or even 150
deg for 20 minutes or so would have, but your 3% may have suffered some
delam at some point. Or it may be warping and breaking/losing contact and
underfill is getting between the contact surfaces and isolating them.
Cross-sectioning and analysis should show this up too.
About tapped out of ideas again for now. Good luck with your search for a
cause - I'ld be interested in hearing what you find.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] No power on after underfill
TechNet
<[log in to unmask]
ORG>
11/20/01
08:58 AM
Please
respond to
"TechNet
E-Mail
Forum."
1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and the
solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill 50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no effective
4. what is conductive residues when we applying no-clean soldering process
?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony
-----Original Message-----
From: <Peter George Duncan> [SMTP:[log in to unmask]]
Sent: Monday, November 19, 2001 10:27 AM
To: [log in to unmask]
Subject: Re: [TN] No power on after underfill
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably doesn't
matter. The main thing I can think of that would cause your problem is
the
thermal excursions needed to apply and cure the underfill. Am I
correct to
say that the boards passed test at room temperature before the
underfill is
applied?
You may have a manufacturing problem where the balls make contact
enough to
pass test, but fail at elevated temperature. I would try testing the
boards
at 100 or 115 degrees C prior to underfilling them and see if they
still
pass. If they do, but fail again after underfilling, then the problem
is
probably related to your underfilling process. It is quite easy to
apply
too much if you're not using an automated process or have not
correctly
calculated the amount of material to apply. It does flow more prior to
curing at curing temperature, and if it's getting into nearby
interface
contacts as a result, you will need to look at damming the area around
the
BGA with a peelable masking to contain the underfill until it's cured,
or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have any
conductive residues left on the board, especially if you use no-clean
soldering processes, they may be picked up by the underfill and
there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance of
the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No power on
after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
3513
and the curing condition is 115C , 15 minutes , the BGA' s package is
below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good
ones .
But after curing , some phone failed because "can not power on ", and
some
failed for "check SIM card ", the defect sample is closed to 3%. I
think
"check card "issue" may caused by the underfill material emission
which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
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<DIV><FONT face=Arial size=2>One of the reasons that people bake boards prior to
underfilling is to overcome moisture and outgassing. Recent work in the UK has
demonstrated that moisture comes out of the solder mask and can cause voiding in
the underfill and cause part movement if a no flow material is used as the
solder joints will not have been produced at this stage.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>I am working with the NPL in UK on a solder mask
project at the moment, if its of interest check out the NPL web site <A
href="http://www.npl.co.uk/npl/ei/">www.npl.co.uk/npl/ei/</A>studio/</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>I have produces some video clips showing the
outgassing from masks which I can put on line if people wish in RealPlayer
format.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:Peter George [log in to unmask]"
title="Peter George [log in to unmask]">Peter George
[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, 2001 5:40
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] No power on after
underfill</DIV>
<DIV><BR></DIV>Hmmm! I can't see anything in your points 1 to 3 that would
directly cause<BR>you any trouble, and the conductive residues I had in mind
ranged from<BR>ionic contaminants on the surfaces to any solder balls that
might have<BR>become lodged underneath.<BR><BR>You didn't answer if you've
tried testing at elevated temperature prior to<BR>underfilling, and one thing
I didn't ask (because I 99.99...% know the<BR>answer) is are your devices
hermetically sealed? I'ld try doing a<BR>cross-section of some of the BGA's
that failed after underfilling and see<BR>if any of the epoxy has got inside
and damaged anything.<BR><BR>More things spring to mind - like did you bake
out the assemblies prior to<BR>underfilling? The Dexter Hysol (sorry, Loctite)
underfill that I use<BR>recommends pre-baking of assemblies prior to
underfilling. If the BGA's<BR>have been out of their bag longer than a couple
of days before<BR>underfilling, they have probably absorbed a lot of moisture.
I can't say<BR>for sure what effect heating moisture-laden components to 120
or even 150<BR>deg for 20 minutes or so would have, but your 3% may have
suffered some<BR>delam at some point. Or it may be warping and breaking/losing
contact and<BR>underfill is getting between the contact surfaces and isolating
them.<BR>Cross-sectioning and analysis should show this up too.<BR><BR>About
tapped out of ideas again for now. Good luck with your search for a<BR>cause -
I'ld be interested in hearing what you find.<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
"Joseph
H.<BR>
Smith"
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>
<Tony_Zhang@H
cc: (bcc: DUNCAN Peter/Asst Prin
Engr/ST<BR>
ZMOT.COM>
Aero/ST
Group)<BR>
Sent
by:
Subject: Re: [TN] No power on after
underfill<BR>
TechNet<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/20/01<BR>
08:58
AM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>1.The PCB we use is Ni/Au but there is Tin
plated on the BGA side and the<BR>solder paster type is Alpha RMA 9147<BR>2.
we have done the experiement for letting the epoxy only underfill 50%<BR>BGA
size , the result is still bad<BR>3. we reduce the curing temperature
from 150 C to 120C , also no effective<BR><BR>4. what is conductive residues
when we applying no-clean soldering process<BR>?<BR><BR><BR>By the way, if you
need MDS of 3513, I can send to you .<BR><BR><BR>Thanks for your great
help.<BR><BR><BR>Tony<BR><BR><BR> -----Original
Message-----<BR> From: <Peter George
Duncan> [<A
href="mailto:SMTP:[log in to unmask]">SMTP:[log in to unmask]</A>]<BR>
Sent: Monday, November 19, 2001 10:27
AM<BR> To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>
Subject:
Re: [TN] No power on after underfill<BR><BR><BR> Hi,
Joseph,<BR><BR><BR> I cannot find the 3513 material
data sheet, but that probably doesn't<BR> matter. The
main thing I can think of that would cause your problem
is<BR> the<BR> thermal
excursions needed to apply and cure the underfill. Am
I<BR> correct to<BR> say that
the boards passed test at room temperature before
the<BR> underfill is<BR>
applied?<BR><BR><BR> You may have a manufacturing
problem where the balls make contact<BR> enough
to<BR> pass test, but fail at elevated temperature. I
would try testing the<BR>
boards<BR> at 100 or 115 degrees C prior to
underfilling them and see if they<BR>
still<BR> pass. If they do, but fail again after
underfilling, then the problem<BR>
is<BR> probably related to your underfilling process.
It is quite easy to<BR>
apply<BR> too much if you're not using an automated
process or have not<BR>
correctly<BR> calculated the amount of material to
apply. It does flow more prior to<BR><BR> curing at
curing temperature, and if it's getting into
nearby<BR> interface<BR>
contacts as a result, you will need to look at damming the area
around<BR> the<BR> BGA with a
peelable masking to contain the underfill until it's
cured,<BR> or<BR> reducing the
amount of material applied.<BR><BR><BR> One other
thing might be contamination under the BGA. If you have
any<BR> conductive residues left on the board,
especially if you use no-clean<BR> soldering
processes, they may be picked up by the underfill
and<BR> there's a<BR> chance
you're suffering from short circuits through the
increased<BR> conductivity of the epoxy. It's very
important to the performance of<BR>
the<BR> underfill that the underneath of the BGA's are
very clean.<BR><BR><BR> Hope this gives you some clues
and you find a solution.<BR><BR><BR> Peter
Duncan<BR><BR><BR><BR><BR><BR><BR><BR>
"Joseph
H.<BR>
Smith"
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>
<Tony_Zhang@H
cc: (bcc: DUNCAN<BR>
Peter/Asst Prin
Engr/ST<BR>
ZMOT.COM>
Aero/ST
Group)<BR>
Sent
by:
Subject: [TN] No power on<BR>
after
underfill<BR>
TechNet<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR><BR><BR><BR>
11/19/01<BR>
03:48
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR> Pls
help me to solve this issue<BR><BR><BR><BR><BR><BR> We
use undefilll for two BGA in one product ,the epoxy is Loctite
LPD<BR> 3513<BR> and the
curing condition is 115C , 15 minutes , the BGA' s package
is<BR> below<BR>
.<BR><BR><BR><BR><BR><BR>
U3 information : Body size, 9*9mm ; height 1.7 ; bump
diameter<BR> 0.3 ;<BR> pitch,
0.8*0.8 ;bump array
10*10<BR> U1 information
: Body size, 12*12 ; heigh t1.7 ; bump
diameter<BR> 0.3 ;<BR> pitch,
0.8*0.8 ; bump array 14*14<BR><BR><BR><BR><BR><BR>
Before the underfilll we check the electric function .All are
good<BR> ones .<BR> But after
curing , some phone failed because "can not power on ",
and<BR> some<BR> failed for
"check SIM card ", the defect sample is closed to 3%.
I<BR> think<BR> "check card
"issue" may caused by the underfill material
emission<BR> which<BR> cover
the SIM card lead .<BR><BR><BR><BR><BR><BR> But I can
not get any idea for further.<BR><BR><BR><BR><BR><BR>
Thanks<BR>
Tony<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR> [This
e-mail is confidential and may also be privileged. If you
are<BR> not the<BR> intended
recipient, please delete it and notify us immediately;
you<BR> should<BR> not copy or
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Thank you.]<BR><BR><BR>
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========================================================================Date: Tue, 20 Nov 2001 10:13:41 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
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RE: Re: [TN] BGA voidsThe test procedure is on the web site to download. The procedure will be adapted for the boards but its the boards you are testing.
The issue of paste and voids in joints due to the air trapped in the via during printing is a separate issue.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: [log in to unmask]
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 1:47 AM
Subject: RE: Re: [TN] BGA voids
I have gone to your website today and downloaded some data what I need. What I still want to know is,
1, how to do outgassing oil test
2, it is plated in via, so what is the rootcause of void? Do you agree it cause by the solder paste flux during the reflow process
Thanks
tony
-----Original Message-----
From: Bob Willis [SMTP:[log in to unmask]]
Sent: Monday, November 19, 2001 12:17 PM
To: Tony Zhang-0343CE
Subject: Re: Re: [TN] BGA voids
I may be able to send you information but you need to tell me what you want or wait till your server is working.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm <http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: [log in to unmask] <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, November 19, 2001 2:48 AM
Subject: RE: Re: [TN] BGA voids
Willis,
Our sever downed for daoys, so I can not go to your website to see the detail information, Could you pls send the information to me?
Thanks
Tony Zhang
Process Engineer
Hangzhou Motorola
-----Original Message-----
From: Bob Willis [SMTP:[log in to unmask] <mailto:SMTP:[log in to unmask]>]
Sent: Friday, November 16, 2001 5:59 PM
To: [log in to unmask]
Subject: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the pads don't have vias in them but if they did they can somtimes gass through the plating, its not the air traped by the paste. I have investigated this with my old outgassing oil test which showes up the problem and will contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm <<http://www.bobwillis.co.uk/workshops/apex/apex.htm>>
www.bobwillis.co.uk <<http://www.bobwillis.co.uk>>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com <<http://www.seminar-registrations.com>>
----- Original Message -----
From: Peter George [log in to unmask] <<mailto:Peter> George [log in to unmask]>
To: [log in to unmask] <<mailto:[log in to unmask]>>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask] <<mailto:[log in to unmask]>>
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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<HTML><HEAD><TITLE>RE: Re: [TN] BGA voids</TITLE>
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<DIV><FONT face=Arial size=2>The test procedure is on the web site to download.
The procedure will be adapted for the boards but its the boards you are
testing.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The issue of paste and voids in joints due to the
air trapped in the via during printing is a separate issue.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, 2001 1:47
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> RE: Re: [TN] BGA voids</DIV>
<DIV><BR></DIV><!-- Converted from text/rtf format -->
<P><SPAN lang=en-us><FONT color=#0000ff face="Times New Roman" size=2>I have
gone to your website today and downloaded some data what I need. What I
still want to know is,</FONT></SPAN> <BR><SPAN lang=en-us><FONT color=#0000ff
face="Times New Roman" size=2>1, how to do</FONT> <FONT color=#0000ff
face="Times New Roman" size=2>outgassing oil test</FONT> </SPAN><BR><SPAN
lang=en-us><FONT color=#0000ff face="Times New Roman" size=2>2, it is
plated in via, so what is the rootcause of void? Do you agree it cause
by</FONT> <FONT color=#0000ff face="Times New Roman" size=2>the solder paste
flux during the reflow process</FONT></SPAN></P>
<P><SPAN lang=en-us><FONT color=#0000ff face="Times New Roman"
size=2>Thanks</FONT></SPAN> <BR><SPAN lang=en-us><FONT color=#0000ff
face="Times New Roman" size=2>tony</FONT></SPAN>
<UL>
<P><SPAN lang=en-us><FONT face=Arial size=1>-----Original
Message-----</FONT></SPAN> <BR><SPAN lang=en-us><B><FONT face=Arial
size=1>From: </FONT></B> <FONT face=Arial size=1>Bob Willis
[SMTP:[log in to unmask]]</FONT></SPAN> <BR><SPAN lang=en-us><B><FONT
face=Arial size=1>Sent: </FONT></B> <FONT face=Arial
size=1>Monday, November 19, 2001 12:17 PM</FONT></SPAN> <BR><SPAN
lang=en-us><B><FONT face=Arial size=1>To: </FONT></B>
<FONT face=Arial size=1>Tony Zhang-0343CE</FONT></SPAN> <BR><SPAN
lang=en-us><B><FONT face=Arial
size=1>Subject: </FONT></B> <FONT
face=Arial size=1>Re: Re: [TN] BGA voids</FONT></SPAN> </P>
<P><SPAN lang=en-us><FONT face=Arial size=2>I may be able to send you
information but you need to tell me what you want or wait till your server
is working.</FONT></SPAN> <BR><SPAN lang=en-us><FONT
face=Arial> </FONT></SPAN> <BR><SPAN lang=en-us><FONT face=Arial>Bob
Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</FONT></SPAN> <BR><SPAN lang=en-us><FONT
face=Arial> </FONT></SPAN> <BR><SPAN lang=en-us><FONT face=Arial>See us
at APEX 2002 <U> </U></FONT><U><FONT color=#0000ff
face=Arial>www.bobwillis.co.uk/workshops/apex/apex.htm <<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>></FONT></U></SPAN>
<BR><SPAN lang=en-us><FONT face=Arial> </FONT></SPAN> <BR><SPAN
lang=en-us><U><FONT color=#0000ff face=Arial>www.bobwillis.co.uk <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>></FONT></U><BR><FONT
face=Arial>Tel: (44) 01245 351502 Fax: (44) 01245 496123</FONT></SPAN>
<BR><SPAN lang=en-us><FONT face=Arial> </FONT></SPAN> <BR><SPAN
lang=en-us><FONT face=Arial>Single solution to your seminar, conference or
roadshow</FONT><U> <FONT color=#0000ff
face=Arial>www.seminar-registrations.com <<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>></FONT></U></SPAN></P>
<UL>
<P><SPAN lang=en-us><FONT face=Arial>----- Original Message -----
</FONT></SPAN><BR><SPAN lang=en-us><B><FONT
face=Arial>From:</FONT></B><FONT face=Arial></FONT><U> <FONT color=#0000ff
face=Arial>[log in to unmask] <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT></U><FONT
face=Arial> </FONT></SPAN><BR><SPAN lang=en-us><B><FONT
face=Arial>To:</FONT></B><FONT face=Arial></FONT><U> <FONT color=#0000ff
face=Arial>[log in to unmask] <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT></U><FONT
face=Arial> </FONT></SPAN><BR><SPAN lang=en-us><B><FONT
face=Arial>Sent:</FONT></B><FONT face=Arial> Monday, November 19, 2001
2:48 AM</FONT></SPAN> <BR><SPAN lang=en-us><B><FONT
face=Arial>Subject:</FONT></B><FONT face=Arial> RE: Re: [TN] BGA
voids</FONT></SPAN> </P><BR>
<P><SPAN lang=en-us><FONT color=#0000ff face="Times New Roman"
size=2>Willis,</FONT><FONT face=Arial><BR></FONT><FONT color=#0000ff
face="Times New Roman" size=2> Our sever downed
for daoys, so I can not go to your website to see the detail information,
Could you pls send the information to me?</FONT></SPAN></P>
<P><SPAN lang=en-us><FONT color=#0000ff face="Times New Roman"
size=2>Thanks</FONT><FONT face=Arial><BR></FONT><FONT face=Tahoma
size=2>Tony Zhang</FONT><FONT face=Arial><BR></FONT><FONT face=Tahoma
size=2>Process Engineer</FONT><BR><FONT face=Tahoma size=2>Hangzhou
Motorola</FONT><FONT face=Arial> </FONT></SPAN></P><BR><BR><BR>
<P><SPAN lang=en-us> <FONT
face=Arial size=1>-----Original Message-----</FONT><FONT
face=Arial><BR></FONT><B><FONT face=Arial
size=1>From: </FONT></B><FONT face=Arial> </FONT><FONT
face=Arial size=1>Bob Willis [</FONT><U><FONT color=#0000ff face=Arial
size=1>SMTP:[log in to unmask] <<A
href="mailto:SMTP:[log in to unmask]">mailto:SMTP:[log in to unmask]</A>></FONT></U><FONT
face=Arial size=1>]</FONT><FONT face=Arial><BR></FONT><B><FONT face=Arial
size=1>Sent: </FONT></B><FONT face=Arial> </FONT><FONT
face=Arial size=1>Friday, November 16, 2001 5:59 PM</FONT><FONT
face=Arial><BR></FONT><B><FONT face=Arial
size=1>To: </FONT></B><FONT face=Arial>
</FONT><FONT face=Arial size=1>[log in to unmask]</FONT><FONT
face=Arial><BR></FONT><B><FONT face=Arial
size=1>Subject: </FONT></B><FONT
face=Arial> </FONT><FONT face=Arial size=1> Re:
[TN] BGA voids</FONT><FONT face=Arial> </FONT></SPAN></P>
<P><SPAN lang=en-us> <FONT
face=Arial size=2>We have experienced voiding with via in pad, I know it
ws stated that the pads don't have vias in them but if they did they can
somtimes gass through the plating, its not the air traped by the paste. I
have investigated this with my old outgassing oil test which showes up the
problem and will contribute to voiding.</FONT></SPAN></P>
<P><SPAN lang=en-us> <FONT
face=Arial> <BR></FONT><FONT face="MS Mincho">Bob Willis</FONT><FONT
face=Arial><BR> <BR></FONT><FONT face="MS Mincho">See us at APEX
2002</FONT><FONT face=Arial> </FONT><U></U><U><FONT face="MS Mincho">
</FONT><FONT color=#0000ff
face="MS Mincho">www.bobwillis.co.uk/workshops/apex/apex.htm <<<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>>></FONT></U><FONT
face=Arial><BR> <BR></FONT><U></U><U><FONT color=#0000ff
face="MS Mincho">www.bobwillis.co.uk <<<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>>></FONT></U><BR><FONT
face="MS Mincho">Tel: (44) 01245 351502 Fax: (44) 01245 496123</FONT><FONT
face=Arial><BR> <BR></FONT><FONT face="MS Mincho">Single solution to
your seminar, conference or roadshow</FONT><U></U><U><FONT
face=Arial></FONT> <FONT color=#0000ff
face="MS Mincho">www.seminar-registrations.com <<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>>></FONT></U></SPAN></P>
<UL>
<P><SPAN lang=en-us> <FONT
face="MS Mincho">----- Original Message -----</FONT><BR><B></B><B><FONT
face="MS Mincho">From:</FONT></B><FONT face="MS Mincho"> Peter George
[log in to unmask] <</FONT><U><FONT color=#0000ff
face="MS Mincho"><<A href="mailto:Peter">mailto:Peter</A>> George
[log in to unmask]</FONT></U><FONT
face="MS Mincho">></FONT><BR><B></B><B><FONT
face="MS Mincho">To:</FONT></B><B><U></U></B><U></U><U><FONT
face=Arial></FONT> <FONT color=#0000ff face="MS Mincho">[log in to unmask]
<<<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>>></FONT></U><FONT
face="MS Mincho"></FONT><BR><B></B><B><FONT
face="MS Mincho">Sent:</FONT></B><FONT face="MS Mincho"> Friday,
November 16, 2001 8:52 AM</FONT><FONT
face=Arial><BR></FONT><B></B><B><FONT
face="MS Mincho">Subject:</FONT></B><FONT face="MS Mincho"> Re: [TN] BGA
voids</FONT><FONT face=Arial> </FONT></SPAN></P>
<P><SPAN lang=en-us> <FONT
face="MS Mincho">Hi, Peter,<BR><BR>I was at a seminar earlier this year
where BGA's and their solder joints<BR>were discussed at some length.
The received wisdom is that voids in solder<BR>joints are not of
themselves a 'defect' unless they break out through the<BR>side of the
ball. In fact, they make the joint more "flexible" - better<BR>able to
withstand creep fatigue - so are beneficial, up to a point.<BR><BR>What
causes them is often </FONT><FONT color=#ff0000
face="MS Mincho">outgassing</FONT><FONT face="MS Mincho"> of volatiles
in the solder paste flux<BR>during the reflow process, though the size
and shape of voids increases and<BR>changes when there are via-in-pad
features as well. About the only way to<BR>detect them is by X-ray, and
to judge from previous TechNet postings, there<BR>are some pretty fancy
machines around now that can give you a very much<BR>clearer view of the
balls than is normally the case ... if you have cash
to<BR>splash!<BR><BR>Peter Duncan<BR><BR><BR><BR><BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> Peter
Lee<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho">
<ppwlee@YAHOO</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> To:</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><U><FONT face=Arial></FONT> <FONT color=#0000ff
face="MS Mincho">[log in to unmask] <<<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>>></FONT></U><BR><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> .COM></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> cc:</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> (bcc: DUNCAN Peter/Asst
Prin Engr/ST<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> Sent by:</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> Aero/ST
Group)<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> TechNet</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> Subject:</FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> [TN] BGA
voids<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho">
<[log in to unmask]<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho">
ORG><BR><BR><BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> 11/16/01<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> 04:25 PM<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> Please<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> respond
to<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> "TechNet<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho"> E-Mail<BR></FONT><FONT
face="Courier New"> </FONT><FONT
face=Arial> </FONT><FONT face="MS Mincho">
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray)
contribute to as high as<BR>60-70% of the joint area. My reflow profile
was designed by running a<BR>sample board with dummy components and
thermalcouples attached right at the<BR>joint. I also inspected the PCB
lands and didn $B!G (Bt see any via on pad.<BR><BR><BR><BR><BR><BR>Does
anyone know the possible reasons for voids formation in BGA
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by step
how would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately;
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you.]<BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Tue, 20 Nov 2001 11:00:56 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUED ASSOCIATES.
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_81.135596c4.292bd838_boundary"
--part1_81.135596c4.292bd838_boundary
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
I got this email sent directly to me and it had an attachment, the attachment
was a virus, it was the W32.Magistr.24876@mm worm. If any of you get this
email sent directly to you, don't run the attachment!!!
The attached file will be named: Kalkaji.com
Below is a paste from Symantec about the virus...
-Steve Gregory-
When a file that is infected by W32.Magistr.24876@mm is executed, it searches
in memory for a readable, writable, initialized section inside the memory
space of Explorer.exe. If one is found, a 110-byte routine is inserted into
that area, and the TranslateMessage function is hooked to point to that
routine. This code first appeared in W32.Dengue.
When the inserted code gains control, a thread is created and the original
TranslateMessage function is called. The thread waits for three minutes
before activating. Then the virus obtains the name of the computer, converts
it to a base64 string, and depending on the first character of the name,
creates a file in either the \Windows folder, the \Program Files folder, or
the root folder. This file contains certain information, such as the location
of the email address books and the date of initial infection. Then it
retrieves the current user's email name and address information from the
registry (Outlook, Exchange, Internet Mail and News), or the Prefs.js file
(Netscape). The virus keeps in its body a history of the 10 most recently
infected users, and these names are visible in infected files when the virus
is decrypted. After this, the virus searches for the Sent file in the
Netscape folder, and for .wab, .mbx, and .dbx files in the \Windows and
\Program Files folders.
If an active Internet connection exists, the virus searches for up to five
.doc and .txt files and chooses a random number of words from one of these
files. These words are used to construct the subject and message body of the
email message. Then the virus searches for up to 20 .exe and .scr files
smaller than 128 KB, infects one of these files, attaches the infected file
to the new message, and sends this message to up to 100 people from the
address books. In addition there is a 20-percent chance that it will attach
the file from which the subject and message body was taken, and an 80-percent
chance that it will add the number 1 to the second character of the sender
address. This last change prevents replies from being returned to you and
possibly alerting you to the infection.
> ??????
>
> Anil Kher wrote:
>
> > Dear Sir ,
> >
> > Due to space problem we have now moved from G-4A,Kalkaji to the following
> address.:-
> >
> > BHARTI TELETECH LTD.
> > C-87, BASEMENT
> > NEAR PETROL PUMP/
> > POLICE STATION
> > KALKAJI
> > NEW DELHI – 19.
> > TELPHONE NO. : 6233113
> >
> > CONTACT PERSON: MR. VIJAY SINGH NEGI.
> >
> > WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING TO
> LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
>
--part1_81.135596c4.292bd838_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I got this email sent directly to me and it had an attachment, the attachment was a virus, it was the W32.Magistr.24876@mm worm. If any of you get this email sent directly to you, don't run the attachment!!!
<BR>
<BR>The attached file will be named: Kalkaji.com
<BR>
<BR>Below is a paste from Symantec about the virus...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>When a file that is infected by W32.Magistr.24876@mm is executed, it searches in memory for a readable, writable, initialized section inside the memory space of Explorer.exe. If one is found, a 110-byte routine is inserted into that area, and the TranslateMessage function is hooked to point to that routine. This code first appeared in W32.Dengue.
<BR>
<BR>When the inserted code gains control, a thread is created and the original TranslateMessage function is called. The thread waits for three minutes before activating. Then the virus obtains the name of the computer, converts it to a base64 string, and depending on the first character of the name, creates a file in either the \Windows folder, the \Program Files folder, or the root folder. This file contains certain information, such as the location of the email address books and the date of initial infection. Then it retrieves the current user's email name and address information from the registry (Outlook, Exchange, Internet Mail and News), or the Prefs.js file (Netscape). The virus keeps in its body a history of the 10 most recently infected users, and these names are visible in infected files when the virus is decrypted. After this, the virus searches for the Sent file in the Netscape folder, and for .wab, .mbx, and .dbx files in the \Windows and \Program Files folders.
<BR>
<BR>If an active Internet connection exists, the virus searches for up to five .doc and .txt files and chooses a random number of words from one of these files. These words are used to construct the subject and message body of the email message. Then the virus searches for up to 20 .exe and .scr files smaller than 128 KB, infects one of these files, attaches the infected file to the new message, and sends this message to up to 100 people from the address books. In addition there is a 20-percent chance that it will attach the file from which the subject and message body was taken, and an 80-percent chance that it will add the number 1 to the second character of the sender address. This last change prevents replies from being returned to you and possibly alerting you to the infection.
<BR>
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">??????
<BR>
<BR>Anil Kher wrote:
<BR>
<BR>> Dear Sir ,
<BR>>
<BR>> Due to space problem we have now moved from G-4A,Kalkaji to the following address.:-
<BR>>
<BR>> BHARTI TELETECH LTD.
<BR>> C-87, BASEMENT
<BR>> NEAR PETROL PUMP/
<BR>> POLICE STATION
<BR>> KALKAJI
<BR>> NEW DELHI – 19.
<BR>> TELPHONE NO. : 6233113
<BR>>
<BR>> CONTACT PERSON: MR. VIJAY SINGH NEGI.
<BR>>
<BR>> WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING TO LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></FONT></HTML>
--part1_81.135596c4.292bd838_boundary--
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========================================================================Date: Tue, 20 Nov 2001 11:06:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
In CCGA, it's important to:
* Have pads on the board that are the same size as the pads on the ceramic
imterposer.
* Have pads on the board that are in the same location as the pads on the
ceramic interposer.
* Apply 4800 to 5500 thou^3 of near eutectic solder paste on each pad.
* Show discipline. Longer at lower temps is better than shorter at higher
temps. There is a tendency to rush the profile in order to get more
throughput. Resist the temptation!
Dave Fish
----- Original Message -----
From: "Stephen R. Gregory" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 19, 2001 4:22 PM
Subject: [TN] CCGA's, the good, the bad, and the ugly...
> Hi all!
>
> May be getting the opportunity to assemble some boards with CCGA's on
them.
> Don't have any direct experience with these puppies. Downloaded IBM's
> application *.PDF on assembling and reworking them (it's pretty good by
the
> way), and seems that basically, you would do the same thing assembling
these
> guys as you do when working with BGA's...am I over-simplifiying things too
> much?
>
> Any advice, or "gotcha's" I should look out for would be appreciated...
>
> As always, thanks a bunch!!!
>
> -Steve Gregory-
>
> --------------------------------------------------------------------------
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ext.5315
> --------------------------------------------------------------------------
-------
>
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========================================================================Date: Tue, 20 Nov 2001 18:43:33 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Gawd, Bob! You've got a fantastic memory! The prototype Plopometer
worked fine, but I never got round to writing a good analytical software
for it. As it never saw the light of a commercial day, I don't think
"faamouse" is exactly the best adjective to describe it.
Best regards,
Brian
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========================================================================Date: Tue, 20 Nov 2001 08:56:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Solder spikes and icicling
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Hello,
Can someone explain what are possible causes for wave
soldering spikes and icicling on the assemblies?
I am encountering this defect on boards with larger
BNC connectors and fuse jumpers. Could this be a
pre-heating issue? How would one resolve this?
Rgds,
Peter
__________________________________________________
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Yahoo! GeoCities - quick and easy web site hosting, just $8.95/month.
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========================================================================Date: Tue, 20 Nov 2001 16:44:25 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUEDASSOCIATES.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hmmm,
At first I thought this must be a joke but now I wonder if it was sent
by a competitor of this company...
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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========================================================================Date: Tue, 20 Nov 2001 09:11:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: How to remove silk screen from the plated area
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I have received boards from my fab suppliers and found with silk screen
on plated area where EMI shield is mounted. The fabs are ENIG
processed. Is there any solution or method to remove white silk screen?
re,
Ken Patel
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========================================================================Date: Tue, 20 Nov 2001 11:09:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Solder spikes and icicling
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Nitrogen at wave not on, lack of flux, large lead diameters with pointy apex's, flux type. Those are the culprits I have found that resolved past problems for me.
Kathy
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<DIV>Nitrogen at wave not on, lack of flux, large lead diameters with pointy
apex's, flux type. Those are the culprits I have found that resolved past
problems for me. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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========================================================================Date: Tue, 20 Nov 2001 12:03:33 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neda Thrash <[log in to unmask]>
Subject: Re: Circuit Repair Facility
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We can help you.
Call 601-486-1700.
<<< [log in to unmask] 11/19 4:56p >>>
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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========================================================================Date: Tue, 20 Nov 2001 12:17:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO :
VALUEDASSOCIATES.
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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And here I thought it was just another misuse of the forum to advertise
company capability or to make a business announcement.
Mel Parrish
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Christison
Sent: Tuesday, November 20, 2001 8:44 AM
To: [log in to unmask]
Subject: Re: [TN] (VIRUS ALERT!!!) [TN] O. MATERIALS. TO :
VALUEDASSOCIATES.
Hmmm,
At first I thought this must be a joke but now I wonder if it was sent
by a competitor of this company...
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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========================================================================Date: Tue, 20 Nov 2001 19:11:28 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Solder mask outgassing
X-To: "Creswick, Steven" <[log in to unmask]>
MIME-Version: 1.0
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boundary="----=_NextPart_000_01C0_01C171F7.27D02DE0"
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
The video clips are on my sever to access them now use the following links. You will need RealPlayer to view the clips.
www.seminar-registrations.com/bw508.rm
www.seminar-registrations.com/bw507.rm
I produced the video clips for a flip chip and underfill workshop I was organising with Speedline Technologies in the UK at the start of the year. I was trying to show the problems of outgassing from the mask during reflow of no-flow underfills. The same issue can occur with traditional underfill but these can cause misaligment of the devices before the solder joint is formed on the connection pads.
I am currently conducting a project as part of team at NPL on solder mask related problems related to cure of masks.
The text below outlines the project and I have also used it for a abstract for the Printed Circuit Board World Convention.
Hope this all of interest.
Characterising Solder Resist/Mask Performance and Degree of Cure
Chris Hunt, Alan Brewing and Bob Willis
National Physical Laboratory Teddington, Middlesex, England
Industry currently uses a number of simple ad-hoc evaluation test methods that correlate poorly with the mask performance during assembly. The industry has long understood that the test methods contained in national and international specifications to be inadequate. NPL is to evaluate a number of test methods and show the relevance to issues experienced during assembly operations. The project will also bench-mark the current test methods with new procedures.
Issues with voiding during underfill cure have been documented, where out-gassing from the solder mask has occurred. Voids in the underfill can dramatically impact on the reliability performance of the solder joints and the mechanical strength of devices to the resist surface. This is particularly important with modern electronics. Evolution of gas and changes in surface tension can significantly influence the occurrence, or the adhesion of solder balls, during soldering. Absorption by solder masks of solvents and other components from cleaning, which then can be desorbed, will significantly impinge on solder wetting.
The aim of the NPL project in conjunction to leading solder mask supplier and soldering material manufacturers will help to achieve the following project goals:
Produce a code of practice to define test methods and criteria to allow companies to simply define and test printed circuit boards prior to assembly or supply.
Investigate current and new methods of assessing the degree of cure of solder masks after fabrication and prior to assembly. Define test methods which could be economically introduced to assembly and fabrication operations.
Compare assembly defects like resist out-gassing, underfill voiding and solder balling and the variations on selected solder resist surfaces.
Propose these test methods and procedures to national and international standards committees to incorporate into future standards to reduce the variation of test results in the industry.
This technical paper will outline the work conducted and the results obtained.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow www.seminar-registrations.com
----- Original Message -----
From: Creswick, Steven
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 3:40 PM
Subject: Solder mask outgassing
Bob,
I for one am interested in seeing the RealTime video clip/s on solder mask
outgassing
Steven Creswick - Gentex Corp
------=_NextPart_000_01C0_01C171F7.27D02DE0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>The video clips are on my sever to access them now
use the following links. You will need RealPlayer to view the
clips.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.seminar-registrations.com/bw508.rm">www.seminar-registrations.com/bw508.rm</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.seminar-registrations.com/bw507.rm">www.seminar-registrations.com/bw507.rm</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>I produced the video clips for a flip chip and
underfill workshop I was organising with Speedline Technologies in the UK at the
start of the year. I was trying to show the problems of outgassing from the mask
during reflow of no-flow underfills. The same issue can occur with traditional
underfill but these can cause misaligment of the devices before the solder joint
is formed on the connection pads.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>I am currently conducting a project as part of team
at NPL on solder mask related problems related to cure of masks.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The text below outlines the project and I have also
used it for a abstract for the Printed Circuit Board World
Convention.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this all of interest.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><BR>Characterising Solder Resist/Mask Performance
and Degree of Cure</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Chris Hunt, Alan Brewing and Bob Willis
<BR>National Physical Laboratory Teddington, Middlesex, England</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Industry currently uses a number of simple ad-hoc
evaluation test methods that correlate poorly with the mask performance during
assembly. The industry has long understood that the test methods contained in
national and international specifications to be inadequate. NPL is to evaluate a
number of test methods and show the relevance to issues experienced during
assembly operations. The project will also bench-mark the current test methods
with new procedures.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Issues with voiding during underfill cure have been
documented, where out-gassing from the solder mask has occurred. Voids in the
underfill can dramatically impact on the reliability performance of the solder
joints and the mechanical strength of devices to the resist surface. This is
particularly important with modern electronics. Evolution of gas and changes in
surface tension can significantly influence the occurrence, or the adhesion of
solder balls, during soldering. Absorption by solder masks of solvents and other
components from cleaning, which then can be desorbed, will significantly impinge
on solder wetting.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The aim of the NPL project in conjunction to
leading solder mask supplier and soldering material manufacturers will help to
achieve the following project goals:</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Produce a code of practice to define test methods
and criteria to allow companies to simply define and test printed circuit boards
prior to assembly or supply.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Investigate current and new methods of assessing
the degree of cure of solder masks after fabrication and prior to
assembly. Define test methods which could be economically introduced to
assembly and fabrication operations.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Compare assembly defects like resist out-gassing,
underfill voiding and solder balling and the variations on selected solder
resist surfaces.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Propose these test methods and procedures to
national and international standards committees to incorporate into future
standards to reduce the variation of test results in the industry.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>This technical paper will outline the work
conducted and the results obtained.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><BR></FONT> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, Chelmsford,
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44)
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Creswick,
Steven</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A
href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, 2001 3:40
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Solder mask outgassing</DIV>
<DIV><BR></DIV>Bob,<BR><BR>I for one am interested in seeing the RealTime
video clip/s on solder mask<BR>outgassing<BR><BR>Steven Creswick - Gentex
Corp</BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_01C0_01C171F7.27D02DE0--
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========================================================================Date: Mon, 19 Nov 2001 07:48:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: test e-mail
MIME-Version: 1.0
Content-Type: text/plain
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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========================================================================Date: Tue, 20 Nov 2001 15:28:45 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: How to remove silk screen from the plated area
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Send them back to their maker.
Dave Fish
----- Original Message -----
From: "Ken Patel" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 20, 2001 9:11 AM
Subject: [TN] How to remove silk screen from the plated area
> I have received boards from my fab suppliers and found with silk screen
> on plated area where EMI shield is mounted. The fabs are ENIG
> processed. Is there any solution or method to remove white silk screen?
>
> re,
> Ken Patel
>
> --------------------------------------------------------------------------
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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========================================================================Date: Tue, 20 Nov 2001 14:42:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: test e-mail
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
So Jim, did we pass, huh, did we did we did we????? Are you grading on a
curve? Was it a life test and do you consider a sample size of one to be
an adequate test? What standards exist for an e-mail test......
Yup, definitely time to lay off the Dew for the day.......
Doug Pauls
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========================================================================Date: Tue, 20 Nov 2001 17:38:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels
of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse
in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way
ENIG always plates, and it's just the way it always looks down inside holes,
I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
--part1_120.76ac8fb.292c3576_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Just recieved a bare fab that I noticed some very rough walls of the barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse in the smaller diameter holes than do the larger holes. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com/
<BR>
<BR>and look at the two pics titled "rough walls"...
<BR>
<BR>Didn't see any real voids, or fibers protruding...just maybe this is the way ENIG always plates, and it's just the way it always looks down inside holes, I've never noticed it being this rough before...See any problems?
<BR>
<BR>Thanks!
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_120.76ac8fb.292c3576_boundary--
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========================================================================Date: Wed, 21 Nov 2001 07:52:22 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, All,
I want to thank all of you, especially Hans, Rummy, Edward, Moonman who
reached near-critical mass early on, Ian Hanna and others for taking time
and trouble on and off line to offer me so much valuable help and advice on
my board problems. In spite of the fundemental nature of the original
questions, this thread became a rope - a sure sign that there are still
issues and information our there to be shared and discussed on "old-hat"
topics, even if they only serve to educate the novices and act as reminders
to the more expert.
This is an excellent forum - long may it continue to be so. I've found a
way forward again as a result of all the help, and will follow up on Hans's
lead about the technique of plating holes only as a way of keeping copper
weights down in boards with multiple blind via groups. This sounds like an
ideal way to build this type of PCB if the process is reliable and provides
good connectivity to the outside layers.
Again my profound thanks and appreciation.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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========================================================================Date: Thu, 26 Oct 2000 10:15:32 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: chris johnston <[log in to unmask]>
Subject: Re: thermistors
MIME-Version: 1.0
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I have need of some design information on thermistors, having never
designed with such devices before, I would like to know the technically
correct way to do things, I mean common sense tells me quite a lot, but the
proper way does not go astray. If any one can point me in the right
direction for some design information, it would be greatly appreciated, or
even email, [log in to unmask], please remember, I live in Australia,
electricity was only invented here last week, and the horseless carriage the
week before.
Christopher Johnston.
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========================================================================Date: Tue, 20 Nov 2001 18:59:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 11/20/01 2:40:04 PM Pacific Standard Time,
[log in to unmask] writes:
Steve:
Do not know if this roughness is a problem, as that ain't my area of
expertise, (if I have one....) but, the "The roughness seems worse in the
smaller diameter holes than do the larger holes" statement yells that the
problem is caused by gas bubbles trapped in the holes....and thus could
probably be remedied (minimized) by "canting" or tipping the boards during
Nickel plating, to allow the bubbles to come out of the holes.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Tue, 20 Nov 2001 16:01:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
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boundary="----_=_NextPart_001_01C1721F.A3612590"
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this format, some or all of this message may not be legible.
------_=_NextPart_001_01C1721F.A3612590
Content-Type: text/plain;
charset="iso-8859-1"
hi,
they look somewhat what a hole looks like when it comes out of the electroless copper bath and strike bath. i'd say it looks okay. do you have the mounts that the fabricator, hopefully, sent to you when you got the boards? that should be the final word.
phil
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 2:39 PM
To: [log in to unmask]
Subject: [TN] Rough PTH barrel walls in ENIG plated PCB...
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way ENIG always plates, and it's just the way it always looks down inside holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
------_=_NextPart_001_01C1721F.A3612590
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class)4125823-20112001><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class)4125823-20112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class)4125823-20112001><FONT face=Arial color=#0000ff size=2>they
look somewhat what a hole looks like when it comes out of the electroless copper
bath and strike bath. i'd say it looks okay. do you have the mounts
that the fabricator, hopefully, sent to you when you got the boards? that
should be the final word.</FONT></SPAN></DIV>
<DIV><SPAN class)4125823-20112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class)4125823-20112001><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 20, 2001 2:39
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Rough PTH barrel
walls in ENIG plated PCB...<BR><BR></FONT></DIV><FONT
face=arial,helvetica><FONT size=2>Hi all! <BR><BR>Just recieved a bare fab
that I noticed some very rough walls of the barrels of the PTH's. This is a
ENIG plated PCB by the way. The roughness seems worse in the smaller diameter
holes than do the larger holes. Go to:
<BR><BR>http://www.stevezeva.homestead.com/ <BR><BR>and look at the two pics
titled "rough walls"... <BR><BR>Didn't see any real voids, or fibers
protruding...just maybe this is the way ENIG always plates, and it's
just the way it always looks down inside holes, I've never noticed it being
this rough before...See any problems? <BR><BR>Thanks! <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1721F.A3612590--
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========================================================================Date: Wed, 21 Nov 2001 08:06:07 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Thanks, Jeff. Sorry, I missed you from my list of special thankees, but
your help has been tremendous. I should know today if I have boards that
are flat enough to use.
Cheers
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board Warp
11/20/01 10:54 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
If the clamping/baking doesn't remove the warp on the first try, you could
give it one more try. What we do in these cases is to slightly bend a pair
of tool steel bars. We then clamp these bars to the warped edge bowing that
edge in the opposite direction. Go through the baking cycle again and cross
your fingers.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 9:50 PM
To: [log in to unmask]
Subject: Re: [TN] Board Warp
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN
Peter/Asst
Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board
Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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========================================================================Date: Wed, 21 Nov 2001 08:38:50 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
I've had a number of ENIG boards made, and they don't look THAT rough.
Looks like someone's run a blunt drill through the board very fast.
Problems? - apart from "Are the holes cleaned and conditioned properly for
plating in the first place?":
Ductility of the copper, or at least its ability to stretch as much as it
could in the Z, perhaps.
Reliability of interconnection between layers?
Local delam behind the plating if the drill did have a rough ride?
Dunno.
Do you have any test coupons exhibiting the same phenomenon to cross
section?
Peter Duncan
"Stephen R.
Gregory" To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: [TN] Rough PTH barrel walls in ENIG
TechNet plated PCB...
<[log in to unmask]
ORG>
11/21/01
06:38 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the
barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness
seems worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the
way ENIG always plates, and it's just the way it always looks down inside
holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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========================================================================Date: Tue, 20 Nov 2001 21:08:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Steve
ENIG don't usually appear like yours. As the others - have you got cross
sections?
Holes can be rough and still have intact plating - or there may be some many
folds and microvoids that you may have problems
Susan Mansilla
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========================================================================Date: Tue, 20 Nov 2001 21:18:26 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: RF "Black Magic", why do vias need to be beneath components?
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves lucky...
-Steve Gregory-
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========================================================================Date: Tue, 20 Nov 2001 21:45:58 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_5b.1f040796.292c6f66_boundary"
--part1_5b.1f040796.292c6f66_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Steve,
The holes on your site look like rough drilling.
ENIG mimicks the appeareance of whatever substarte it is plated on. These
holes were rough before ENIG plating.
If a crossection shows adequate copper plate then the roughness could be non
consequential. If u need to talk more about this e-mail me at [log in to unmask]
George Milad
Shipley
--part1_5b.1f040796.292c6f66_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Steve,
<BR>The holes on your site look like rough drilling.
<BR>ENIG mimicks the appeareance of whatever substarte it is plated on. These holes were rough before ENIG plating.
<BR>If a crossection shows adequate copper plate then the roughness could be non consequential. If u need to talk more about this e-mail me at [log in to unmask]
<BR>George Milad
<BR>Shipley</FONT></HTML>
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========================================================================Date: Wed, 21 Nov 2001 08:02:50 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Steve,
I completly agree with George.It has nothing with ENIG.Probably too rough
drilling or too agresive desmear.
ENIG finishing does follow surface geometry.This is contrary to HASL,that
fill some of valleys giving impression that the hole is smooth.
By the way,if the cross sections are OK, solder float tests wre OK ( copper
mechanical properties) and they do not create problems in soldering (
cleaning etc) ,and if there diameter is OK, I do not see reasons for reject.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: George Milad [SMTP:[log in to unmask]]
> Sent: ã ðåáîáø 21 2001 4:46
> To: [log in to unmask]
> Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
>
> Steve,
> The holes on your site look like rough drilling.
> ENIG mimicks the appeareance of whatever substarte it is plated on. These
> holes were rough before ENIG plating.
> If a crossection shows adequate copper plate then the roughness could be
> non consequential. If u need to talk more about this e-mail me at
> [log in to unmask]
> George Milad
> Shipley
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========================================================================Date: Tue, 20 Nov 2001 23:51:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
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========================================================================Date: Wed, 21 Nov 2001 08:12:51 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: Solder spikes and icicling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
Did some work recently on large BNC connectors, the trouble with them is
that the body of the connector acts as a great heat sink thus drawing heat
away from the solder land and connector lead I was trying to solder.
P.s when I contacted the component supplier's they informed me that the
component in question was not suitable for wave solder. We now solder them
with an RF soldering iron.
Hope this is of some use.
Steve.
-----Original Message-----
From: peter lee [mailto:[log in to unmask]]
Sent: 20 November 2001 16:56
To: [log in to unmask]
Subject: [TN] Solder spikes and icicling
Hello,
Can someone explain what are possible causes for wave
soldering spikes and icicling on the assemblies?
I am encountering this defect on boards with larger
BNC connectors and fuse jumpers. Could this be a
pre-heating issue? How would one resolve this?
Rgds,
Peter
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========================================================================Date: Wed, 21 Nov 2001 08:26:45 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Brown <[log in to unmask]>
Organization: Xyratex
Subject: Raw Card Track Repairs
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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========================================================================Date: Wed, 21 Nov 2001 08:54:35 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brown <[log in to unmask]>
Subject: Non-wetting
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Good Morning, this is my first posting to this forum I hope to get some
help. We are building a small PWB with 4 per panel. The problems we are
encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
are all located near to or the center of the PWB. There is paste on the pad
and the component placed properly but the paste will not wet onto the leads
or terminations.
What have we done?
1. Run the PWB at various profiles even the highest. Still have problem.
2. Changed from no clean to aqueous with an agressive flux. Still have
problem.
3. Changed screen apertures. Still have problem.
This PWB is multi layer and heavily populated.
Are there any hints as to what we do next?
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
---------------------------------------------------------------------------------
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========================================================================Date: Wed, 21 Nov 2001 17:35:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Solutions may be more elegant these days, but a mechanical guard screen
coupled to an interlock used to be the method of preventing squashed
operators. In position, the screen prevented the operator getting access to
the moving parts of the machine while it was operating, and with the screen
raised, the interlock prevented the machine from operating by activating a
cut-out. Not fool-proof, as ingenious operators on piece-work would bypass
the interlock to keep the machine functioning with the screen raised to
increase throughput rather than spending time raising and lowering a screen
for each piece of work. Bear in mind that "bolt-on" safety mechanisms are
never as good as mechanisms that are designed in with the machine to start
with.
Special fixtures will be required anyway, but if you use them without a
guard screen of some kind as well, the operator can still get access while
the machine is capable of being operated. The risk of injury is reduced but
still present. I'm not up on current safety methods in this situation, so
can't advise alternatives, but a light curtain that comes on when the start
button is pressed sounds like a neat way of achieving the desired result.
At least if it gets too dirty or fails, the machine will be inoperable,
which is erring on the side of safety.
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Manual Press for PEM PCB
<[log in to unmask] fastener
ORG>
11/21/01
03:51 PM
Please
respond to
"TechNet
E-Mail
Forum."
My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
_________________________________________________________
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Get your free @yahoo.com address at http://mail.yahoo.com
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========================================================================Date: Wed, 21 Nov 2001 17:52:58 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
The number of track repairs allowable is normally a matter between the
contractor and the customer and depends to some extent on the design and
its operating environment. I once had a customer who insisted on reviewing
the situation if the number of track repairs, cuts or jumpers went above 3,
and the board had to be re-routed if the number of track mods exceeded 5.
On the other hand, I have seen customer-owned card assemblies with a
veritable wiring harness of repair and mod wires, so there are no fixed
rules.
You have to assess the situation on its own merits, rather than relying on
specs to tell you the road out. All things being equal, though, if the
repairs are carried out well to a spec such as IPC-7721, and they don't
interfere with, or reduce the reliable mountability of components, you
should not have much of an issue. Having said that, and not knowing the
extent of the track repairs being proposed, I would not like to accept new
boards with long stretches of repaired track (greater that, say, half an
inch) or more than about 6 repairs, but that's just my personal view.
It's not always an easy call to make, but discuss it with the designers,
the customer if need be, and the assembly line. Repaired tracks are weaker
than original track, and this must be borne in mind for processing as well
as reliability in the field. If in doubt, let the fab house repair one or
two (best and worst case) and see how they fare through the production
cycle. Then you can better determine what level of repair you can accept.
Good luck!
Peter Duncan
Stephen Brown
<[log in to unmask] To: [log in to unmask]
RATEX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Raw Card Track Repairs
11/21/01 04:26 PM
Please respond to
"TechNet E-Mail
Forum."
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
---------------------------------------------------------------------------------
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========================================================================Date: Wed, 21 Nov 2001 18:31:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Non-wetting
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, John,
Welcome to TN. I have to answer your question with more questions, like:
1) Are the problem components used anywhere else on the board and are they
being properly wetted in those other positions?
2) What board finish are you using?
3) What is the termination finish of the components? Do they have any
silver content for any reason?
4) How old are the components and what conditions have they been stored
under?
5) Are the same locations failing to wet each time, or are some wetting in
some cases and others in others?
6) What solder are you using?
I suspect you have an oxidisation problem with the component leads, perhaps
leeching of silver if there is any silver content. If it's a silver
problem, try using a 2% silver solder to redress the balance. If it's
oxide, you will have to replace the components or re-tin them in a solder
pot with a very aggressive flux.
Maybe I can help more with more detail.
Peter Duncan
John Brown
<johnbrown118@HO To: [log in to unmask]
TMAIL.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Non-wetting
>
11/21/01 04:54
PM
Please respond
to "TechNet
E-Mail Forum."
Good Morning, this is my first posting to this forum I hope to get some
help. We are building a small PWB with 4 per panel. The problems we are
encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
are all located near to or the center of the PWB. There is paste on the pad
and the component placed properly but the paste will not wet onto the leads
or terminations.
What have we done?
1. Run the PWB at various profiles even the highest. Still have problem.
2. Changed from no clean to aqueous with an agressive flux. Still have
problem.
3. Changed screen apertures. Still have problem.
This PWB is multi layer and heavily populated.
Are there any hints as to what we do next?
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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========================================================================Date: Wed, 21 Nov 2001 10:14:57 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
The best method I've seen of protecting press equipment is to wire the
equipment so that the operator has to press two buttons simultaneously
to operate the equipment and that the buttons are far enough apart that
both hands are required. Of course this is in addition to rather than
instead of the usual guards etc. A really determined idiot will always
find a way to bypass safety guards but this way seemed elegant and
effective.
Regards,
"" wrote:
>
> Solutions may be more elegant these days, but a mechanical guard screen
> coupled to an interlock used to be the method of preventing squashed
> operators. In position, the screen prevented the operator getting access to
> the moving parts of the machine while it was operating, and with the screen
> raised, the interlock prevented the machine from operating by activating a
> cut-out. Not fool-proof, as ingenious operators on piece-work would bypass
> the interlock to keep the machine functioning with the screen raised to
> increase throughput rather than spending time raising and lowering a screen
> for each piece of work. Bear in mind that "bolt-on" safety mechanisms are
> never as good as mechanisms that are designed in with the machine to start
> with.
>
> Special fixtures will be required anyway, but if you use them without a
> guard screen of some kind as well, the operator can still get access while
> the machine is capable of being operated. The risk of injury is reduced but
> still present. I'm not up on current safety methods in this situation, so
> can't advise alternatives, but a light curtain that comes on when the start
> button is pressed sounds like a neat way of achieving the desired result.
> At least if it gets too dirty or fails, the machine will be inoperable,
> which is erring on the side of safety.
>
> Peter Duncan
>
> Peter Lee
> <ppwlee@YAHOO To: [log in to unmask]
> .COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
> Sent by: Aero/ST Group)
> TechNet Subject: Re: [TN] Manual Press for PEM PCB
> <[log in to unmask] fastener
> ORG>
>
> 11/21/01
> 03:51 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
> My application requires operator to support and locate the board
> assembly with one hand while activating the start button on the press to
> install the PEM fasteners.
>
> For safety reason I am considering limiting operator access while the
> machine is in operation.
>
> What is the normal practice? Installing a light curtain sensor around
> the area? Or multi-purpose fixtures that will secure the board to ensure
> a "hands free" operation?
>
> Any input is greatly appreciated.
>
> Rgd,
> Peter
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
> Sent: November 14, 2001 6:16 AM
> To: [log in to unmask]
> Subject: Re: [TN] Manual Press for PEM PCB fastener
>
> Peter,
>
> Might suggest you look over Janesville Tool at
> http://www.janesvilletool.com/.
> We use their presses for setting eyelets.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
> www.circuittechctr.com
> [log in to unmask]
> 978-374-5000
>
> Sign up for our Free E-mail Newsletter at:
> www.circuittechctr.com/general/free_email.htm
>
> -----Original Message-----
> From: Peter Lee [mailto:[log in to unmask]]
> Sent: Wednesday, November 14, 2001 2:46 AM
> To: [log in to unmask]
> Subject: [TN] Manual Press for PEM PCB fastener
>
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
> Rgds,
> Peter
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
> ------------------------------------------------------------------------
> ----
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text
> in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
> Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases
> >
> E-mail Archives
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========================================================================Date: Wed, 21 Nov 2001 07:24:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Non-wetting
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I am assuming that you actually profiled the board and know that the
temperature profile conforms to the recomendations of the paste
manufacturer.
You need to determine if the board or components are at fault. J-STD-002 and
J-STD-003 provide test methods for the components and the board,
respectively. Did the paste wet to the board and leave the component
non-wetted? I would check the parts.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of John Brown
> Sent: Wednesday, November 21, 2001 3:55 AM
> To: [log in to unmask]
> Subject: [TN] Non-wetting
>
>
> Good Morning, this is my first posting to this forum I hope to get some
> help. We are building a small PWB with 4 per panel. The problems we are
> encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
> are all located near to or the center of the PWB. There is paste
> on the pad
> and the component placed properly but the paste will not wet onto
> the leads
> or terminations.
> What have we done?
> 1. Run the PWB at various profiles even the highest. Still have problem.
> 2. Changed from no clean to aqueous with an agressive flux. Still have
> problem.
> 3. Changed screen apertures. Still have problem.
> This PWB is multi layer and heavily populated.
> Are there any hints as to what we do next?
>
> _________________________________________________________________
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========================================================================Date: Wed, 21 Nov 2001 07:24:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
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Steve
I hear your agony almost anybody who assembles RF boards have to face with
these difficulties
The main reason is RF parts need good ground and a good ground for RF
designers means
many vias to provide this.
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 9:18 PM
To: [log in to unmask]
Subject: [TN] RF "Black Magic", why do vias need to be beneath
components?
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been
bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive
that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves
lucky...
-Steve Gregory-
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========================================================================Date: Wed, 21 Nov 2001 14:38:26 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: sedat bayar <[log in to unmask]>
Subject: nitrogen purity
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Hello All,
What is the minimum nitrogen purity to use in the convection reflow system?
Thanks
Sedat BAYAR
Aselsan Inc.
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========================================================================Date: Wed, 21 Nov 2001 13:36:07 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Non-wetting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi John,
some questions:
- have you tried to handsolder and did you get good wetting ?
- did you profile for this particular area ?
- what kind of surface do you have?
- have you checked for contamination?
- are you sure what you see is non-wetting or could it be dewetting ?
- how about the wetting in other areas than in the center ?
- how old are the parts/boards ?
- were they stored properly ?
- tell us more about your profile, is your equipment capable of handling
those assemblies ?
- if you are sure you have done your best, have you thought of giving this
to a laboratory for further investigations?
- what is so special with the area, the parts ?
A lot of questions and there may be some more
Tell us more
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========================================================================Date: Wed, 21 Nov 2001 08:13:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brewer <[log in to unmask]>
Subject: grounds....
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Steve,
As a ham radio operator, all I could say is that at RF (and especially very high freq RF), if
you make
a ground a significant distance away (in relation to the wavelength of the RF signal) it
becomes NOT a ground. Getting ground CLOSE to the point being grounded
is essential. At DC, it doesnt matter...ground's ground as long as there's ANY path
(within reason) to get there.
That'd be my guess.
Happy VF (Virtual Friday!)
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========================================================================Date: Wed, 21 Nov 2001 08:21:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
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Peter,
The Cambridge Automatic press (AE2000) has a nice safety interlock for
keeping the fingers out of the press area. They use an air driven ring
which comes down around the work piece and has a normally open magnetic
air switch which prevents movement of the main ram until it is within
about 1/4" of the board surface. It works very well.
Phil Nutting
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 2:51 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
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========================================================================Date: Wed, 21 Nov 2001 08:26:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Goldman, Patricia J." <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
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Steve,
I agree with both George and Edward.
The best clue (even before looking at the pictures) was your statement that the smaller size hole was affected. Smaller holes are more difficult to drill smoothly, shall we say. When looking at the rows of holes, note that the roughness defect looks nearly identical in each hole. Regarding ENIG, it is a pretty thin coating - too thin to add significantly to topography. Any defect from it would more likely show up as poor coverage or as a salting-out (sanding?) type of defect. A gas bubble defect normally shows up as a perfect ring somewhere in the hole barrel and usually would prevent plating coverage in that area.
Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]
-----Original Message-----
From: Edward Szpruch [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 1:03 AM
To: [log in to unmask]
Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
Steve,
I completly agree with George.It has nothing with ENIG.Probably too rough
drilling or too agresive desmear.
ENIG finishing does follow surface geometry.This is contrary to HASL,that
fill some of valleys giving impression that the hole is smooth.
By the way,if the cross sections are OK, solder float tests wre OK ( copper
mechanical properties) and they do not create problems in soldering (
cleaning etc) ,and if there diameter is OK, I do not see reasons for reject.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: George Milad [SMTP:[log in to unmask]]
> Sent: ã ðåáîáø 21 2001 4:46
> To: [log in to unmask]
> Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
>
> Steve,
> The holes on your site look like rough drilling.
> ENIG mimicks the appeareance of whatever substarte it is plated on. These
> holes were rough before ENIG plating.
> If a crossection shows adequate copper plate then the roughness could be
> non consequential. If u need to talk more about this e-mail me at
> [log in to unmask]
> George Milad
> Shipley
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========================================================================Date: Wed, 21 Nov 2001 08:33:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
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Steve,
I don't have a hard and fast number, but for new bare boards we like no
etch (track) cuts or repairs. For production stuffed PTH boards we try
to keep the number of rework cuts and jumpers to a minimum partially for
reliability reasons but also for the labor cost reasons. Hand rework
can get expensive not to mention the "artwork" some reworks take on
depending on the complexity. For R&D boards, well... there R&D boards.
Need I say more?
Phil Nutting
-----Original Message-----
From: Stephen Brown [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 3:27 AM
To: [log in to unmask]
Subject: [TN] Raw Card Track Repairs
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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========================================================================Date: Wed, 21 Nov 2001 08:29:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C17290.83A17C20"
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I've been using ENIG on holes from .008 to .040 for three years. These look
fine. I call the roughness "barrelling". You still have plenty of Au in
the holes.
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 5:39 PM
To: [log in to unmask]
Subject: [TN] Rough PTH barrel walls in ENIG plated PCB...
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels
of the PTH's. This is a ENIG plated PCB by the way. The roughness seems
worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way
ENIG always plates, and it's just the way it always looks down inside
holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
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<BODY>
<DIV><FONT color=#0000ff face=Arial size=2>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classu0383013-21112001>I've
been using ENIG on holes from .008 to .040 for three years. These look
fine. I call the roughness "barrelling". You still have plenty of Au
in the holes.</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr></FONT><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 20, 2001 5:39
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Rough PTH barrel
walls in ENIG plated PCB...<BR><BR></DIV></BLOCKQUOTE></DIV>
<BLOCKQUOTE></FONT><FONT face=arial,helvetica><FONT size=2>Hi all!
<BR><BR>Just recieved a bare fab that I noticed some very rough walls of the
barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness
seems worse in the smaller diameter holes than do the larger holes. Go to:
<BR><BR>http://www.stevezeva.homestead.com/ <BR><BR>and look at the two pics
titled "rough walls"... <BR><BR>Didn't see any real voids, or fibers
protruding...just maybe this is the way ENIG always plates, and it's
just the way it always looks down inside holes, I've never noticed it being
this rough before...See any problems? <BR><BR>Thanks! <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C17290.83A17C20--
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========================================================================Date: Wed, 21 Nov 2001 07:41:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Thomas Highland <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Steve:
Try IPC-600.
Thomas C. Highland
Quality Assurance Manager
Innovatec Communications
-----Original Message-----
From: Stephen Brown [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 02:27
To: [log in to unmask]
Subject: [TN] Raw Card Track Repairs
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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========================================================================Date: Wed, 21 Nov 2001 09:36:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lik-Jen Wu <[log in to unmask]>
Organization: Alcatel BND
Subject: Re: thermistors
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
You can find information regarding NTC thermistor on
http://www.chipcenter.com/eexpert/akruger/archive.html
Also, you can usually find an article or two on how to use thermistor at thermistor
manufacturer websites.
chris johnston wrote:
> I have need of some design information on thermistors, having never
> designed with such devices before, I would like to know the technically
> correct way to do things, I mean common sense tells me quite a lot, but the
> proper way does not go astray. If any one can point me in the right
> direction for some design information, it would be greatly appreciated, or
> even email, [log in to unmask], please remember, I live in Australia,
> electricity was only invented here last week, and the horseless carriage the
> week before.
>
> Christopher Johnston.
>
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========================================================================Date: Wed, 21 Nov 2001 08:50:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Mario! I have a reference which may be helpful. A number of years ago
Nicolet Instruments (they are an xray equipment supplier) worked with
Sandia National Labs on the effects of ionizing radiation on electronic
components. They used a 100KV anode voltage and exposed a variety of
components to ionizing radiation for various dwell times. Their conclusion
was that it would require 43 days of direct exposure to damage a component
(for the testing conditions and specific components selected). Contact
Nicolet Test Instruments Division and obtain a copy of their Application
Notes titled "Ionizing Radiation and Its Effects Upon Electronic
Components" for the details. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Mario Dion <[log in to unmask]>@ipc.org> on 11/19/2001 09:21:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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========================================================================Date: Wed, 21 Nov 2001 06:57:14 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Kimmey <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
Bear with me while I try this.
First of all there is an issue in RF design that has priority over
just about everything, that is the "return path". As a signal is sent down a
RF pathway (components, transmission lines, etc.) there is an equivalent
signal traveling the return path. If the return path is of a different
length than the signal path then there is a degradation of the signal (this
is a bad thing). So as RF goes the closer I get ground (my return path of
choice) the better integrity I have for my RF signal.
Secondly, there is the issue of RF ground as a part of the RF magic
(I think it is mostly the return path issue) having an effect on the
electromagnetic fields surrounding the RF signal path. Any disruption in
this field can cause integrity issues and performance failures.
Thirdly, there is the need to develop and market product rapidly in
todays world that tends to make the extra XXX hours needed to refine a
circuit enough to pull vias back impossible to get.
Lastly there is the RF factor. This is the fact that even the top RF
guys will admit to "it's magic" sometimes.
Even though as designers we hate to make the boards harder for you to
assemble, we must make the circuit work. This means vias near lands, poor
thermal relief around components (poor hell, usually none), and extremely
tight component placements are all caused by the driving need to maintain
the signal's integrity (so you can hear that cell call, static and all).
Though as a designer I feel bad for what we do to guys like you, know you
are appreciated for making us look good when the customer has a product that
achieves spec.
Hope it helps,
FNK
Frank N Kimmey, C.I.D.+
Senior PCB Designer
Powerwave Technologies
PH. 916-941-3159
Fax 916-941-3195
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 6:18 PM
To: [log in to unmask]
Subject: [TN] RF "Black Magic", why do vias need to be beneath
components?
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been
bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive
that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves
lucky...
-Steve Gregory-
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========================================================================Date: Wed, 21 Nov 2001 10:22:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bonjour David,
Thks for the information. In fact I got the report from Nicolet (Great
Mister Messerschmidt !) 2 days ago. Even though the report is dated from few
years already, it contains as you mentionned interesting information about
the effects of X-RAY on electronic components. Unfortunately it seems it is
not available in electronic format so if someone needs a copy I suggest to
contact Teradyne who now own Genrad which own Nicolet Imaging Systems....
My contact is M.Ken Messerschmidt, mailto:[log in to unmask]
Thks to all for your feedback about the subject,
Regards
Mario Dion
Mediatrix Telecom Inc
[log in to unmask]
--------------------------------------------------------
-----Original Message-----
From: David Hillman [mailto:[log in to unmask]]
Sent: 21 novembre, 2001 09:50
To: [log in to unmask]
Subject: Re: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Hi Mario! I have a reference which may be helpful. A number of years ago
Nicolet Instruments (they are an xray equipment supplier) worked with
Sandia National Labs on the effects of ionizing radiation on electronic
components. They used a 100KV anode voltage and exposed a variety of
components to ionizing radiation for various dwell times. Their conclusion
was that it would require 43 days of direct exposure to damage a component
(for the testing conditions and specific components selected). Contact
Nicolet Test Instruments Division and obtain a copy of their Application
Notes titled "Ionizing Radiation and Its Effects Upon Electronic
Components" for the details. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Mario Dion <[log in to unmask]>@ipc.org> on 11/19/2001 09:21:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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========================================================================Date: Wed, 21 Nov 2001 09:39:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Gleason <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
FYI,
I recommend making a press block that holds the pins so that the operator
hands are out of the press area. Once this is done, a two button start is
the most economical. Call me if you'd like I can show you a digital picture
of ours.
Jim
972-494-1911
----- Original Message -----
From: "Peter Lee" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 20, 2001 11:51 PM
Subject: Re: [TN] Manual Press for PEM PCB fastener
> My application requires operator to support and locate the board
> assembly with one hand while activating the start button on the press to
> install the PEM fasteners.
>
> For safety reason I am considering limiting operator access while the
> machine is in operation.
>
> What is the normal practice? Installing a light curtain sensor around
> the area? Or multi-purpose fixtures that will secure the board to ensure
> a "hands free" operation?
>
> Any input is greatly appreciated.
>
> Rgd,
> Peter
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
> Sent: November 14, 2001 6:16 AM
> To: [log in to unmask]
> Subject: Re: [TN] Manual Press for PEM PCB fastener
>
> Peter,
>
> Might suggest you look over Janesville Tool at
> http://www.janesvilletool.com/.
> We use their presses for setting eyelets.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
> www.circuittechctr.com
> [log in to unmask]
> 978-374-5000
>
> Sign up for our Free E-mail Newsletter at:
> www.circuittechctr.com/general/free_email.htm
>
>
>
> -----Original Message-----
> From: Peter Lee [mailto:[log in to unmask]]
> Sent: Wednesday, November 14, 2001 2:46 AM
> To: [log in to unmask]
> Subject: [TN] Manual Press for PEM PCB fastener
>
>
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
>
> Rgds,
> Peter
>
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
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========================================================================Date: Wed, 21 Nov 2001 17:00:51 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Earl, Brad,
Thank you for the answers. Obviously, there is no a lots of experiences on
this area among TechNetters or the question itself wasn't interesting
enough. :)
However I just want to follow up this subject with the experiences that I
gained during the testing of the PCB in vacuum chamber. I hope that this is
going to help someone in the future.
I found that the best solution was to add two extra layers (top and bottom)
to the PCBs that are only containing pads and annular rings for the plated
holes. Pads are connected with the layers with hidden vias. That way, I
minimised the amount of the exposed copper/ENIG on the surface of the PCB.
There is no coating on the laminate at all, which minimises outgassing (I
wouldn't believe this if I haven't seen it myself).
I'm washing the flux residues away directly after the reflow, first with
Zestron and than with not-ionised water. After this, the PCBs are baked and
stored in the nitrogen atmosphere. Before mounting the PCBs in to the
vacuum the PCBs are stored in the vacuum chamber during the 8 hours period,
outgassing as much as possible. When this procedure is finnished and the
PCBs are mounted in to the vacuum, make little prayer and hope for the best
when you push "ON" button. :)
Sasha Miladinovic
**********************************************************************
Sasha Miladinovic - Production Engineering
Amersham Biosciences, PCB Production, Umeå
Tel: +46 (0) 90 150 232
Fax: +46 (0) 90 138 372
E-mail: [log in to unmask]
**********************************************************************
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========================================================================Date: Wed, 21 Nov 2001 09:41:25 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Bergman <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
IPC-6012A describes the characteristic "circuit repairs" as being acceptable in Class 1, 2,
and 3 only "As agreed by user and supplier." Generally these repairs, if done properly, are
reliable. See IPC 7721 for methods. It is your call, basically.
K. Bergman
Stephen Brown wrote:
> People.
>
> We get our PCB's assembled to IPC-610 class 2. We have recently been
> approached by our vendor regarding track repairs on our raw cards. Now I
> personally am not keen on allowing this, but is there a standard for raw
> cards similar to 610 which states an allowable quantity of track
> repairs, if any?
>
> Regards.
>
> Steve Brown.
> Commodity Specialist
> Xyratex.
>
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========================================================================Date: Wed, 21 Nov 2001 13:38:37 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_11f.79b58a3.292d4ead_boundary"
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Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Frank!
Thank-you very much for taking the time to explain things for me, makes
things more understandable now...not easier to deal with (GRIN), but more
understandable.
-Steve Gregory-
> Steve,
> Bear with me while I try this.
> First of all there is an issue in RF design that has priority over
> just about everything, that is the "return path". As a signal is sent down a
> RF pathway (components, transmission lines, etc.) there is an equivalent
> signal traveling the return path. If the return path is of a different
> length than the signal path then there is a degradation of the signal (this
> is a bad thing). So as RF goes the closer I get ground (my return path of
> choice) the better integrity I have for my RF signal.
> Secondly, there is the issue of RF ground as a part of the RF magic
> (I think it is mostly the return path issue) having an effect on the
> electromagnetic fields surrounding the RF signal path. Any disruption in
> this field can cause integrity issues and performance failures.
> Thirdly, there is the need to develop and market product rapidly in
> todays world that tends to make the extra XXX hours needed to refine a
> circuit enough to pull vias back impossible to get.
> Lastly there is the RF factor. This is the fact that even the top RF
> guys will admit to "it's magic" sometimes.
> Even though as designers we hate to make the boards harder for you to
> assemble, we must make the circuit work. This means vias near lands, poor
> thermal relief around components (poor hell, usually none), and extremely
> tight component placements are all caused by the driving need to maintain
> the signal's integrity (so you can hear that cell call, static and all).
> Though as a designer I feel bad for what we do to guys like you, know you
> are appreciated for making us look good when the customer has a product that
> achieves spec.
> Hope it helps,
> FNK
>
> Frank N Kimmey, C.I.D.+
> Senior PCB Designer
> Powerwave Technologies
> PH. 916-941-3159
> Fax 916-941-3195
>
--part1_11f.79b58a3.292d4ead_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Frank!
<BR>
<BR>Thank-you very much for taking the time to explain things for me, makes things more understandable now...not easier to deal with (GRIN), but more understandable.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve,
<BR>Bear with me while I try this.
<BR> First of all there is an issue in RF design that has priority over
<BR>just about everything, that is the "return path". As a signal is sent down a
<BR>RF pathway (components, transmission lines, etc.) there is an equivalent
<BR>signal traveling the return path. If the return path is of a different
<BR>length than the signal path then there is a degradation of the signal (this
<BR>is a bad thing). So as RF goes the closer I get ground (my return path of
<BR>choice) the better integrity I have for my RF signal.
<BR> Secondly, there is the issue of RF ground as a part of the RF magic
<BR>(I think it is mostly the return path issue) having an effect on the
<BR>electromagnetic fields surrounding the RF signal path. Any disruption in
<BR>this field can cause integrity issues and performance failures.
<BR> Thirdly, there is the need to develop and market product rapidly in
<BR>todays world that tends to make the extra XXX hours needed to refine a
<BR>circuit enough to pull vias back impossible to get.
<BR> Lastly there is the RF factor. This is the fact that even the top RF
<BR>guys will admit to "it's magic" sometimes.
<BR>Even though as designers we hate to make the boards harder for you to
<BR>assemble, we must make the circuit work. This means vias near lands, poor
<BR>thermal relief around components (poor hell, usually none), and extremely
<BR>tight component placements are all caused by the driving need to maintain
<BR>the signal's integrity (so you can hear that cell call, static and all).
<BR>Though as a designer I feel bad for what we do to guys like you, know you
<BR>are appreciated for making us look good when the customer has a product that
<BR>achieves spec.
<BR>Hope it helps,
<BR>FNK
<BR>
<BR>Frank N Kimmey, C.I.D.+
<BR>Senior PCB Designer
<BR>Powerwave Technologies
<BR>PH. 916-941-3159
<BR>Fax 916-941-3195
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_11f.79b58a3.292d4ead_boundary--
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========================================================================Date: Wed, 21 Nov 2001 15:24:30 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: nitrogen purity
X-To: Sedat Cbayar <[log in to unmask]>
After a brief 3.5 day trip from BF Montana to Eastern Michigan, I'm back.
Big whoop! How 'bout those Chicago commuters! Never again as long as I live
will I take the 80 anywhere near that city. Trains only, thank you.
You measure the amount of oxygen (%), not the nitrogen purity or amount -
can't be done. The oxygen content should be as specified for the type
soldering you are attempting. Usually, below 20% oxygen content is acceptable.
MoonMan
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========================================================================Date: Wed, 21 Nov 2001 15:32:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
X-To: "David H. Fish" <[log in to unmask]>
All that's been said about CCGA's, by all saying it, is true. Not much
bigger deal than BGA's but bigger and much heavier parts. Best solder joints
possible with those "flexible" columns and solder fillets at joint level.
Machine vision offers biggest challenge, as someone said. Rework must be
considered as well. That's the most fun but very doable.
Done hundreds of these using cast, not clasp, columns from IBM. With columns
about .070" long, inspection not too tough. Whoever noted it very important
to ensure columns straight said it right. When bent, I used an engineering
scale to "comb" the little muthas straight again. Pretty forgiving those
columns when a little bent but not so when abused.
MoonMan
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========================================================================Date: Wed, 21 Nov 2001 15:41:02 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Over-etch
X-To: [log in to unmask]
Not a paid endorsement for Glynn. However, I must say among many others, he
runs the best little board house in the country. He does a lot of things for
free, as well, that saves you lot's of money. He's a real board guy.
Earl Moon
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========================================================================Date: Wed, 21 Nov 2001 16:49:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter
I think we now know why you've had warpage problems on the other boards.
Building up unequally thick sequentially laminated parts then laminating
them together is likely the underlying asymmetry that's warping the boards.
Even if in the final stackup appears symmetric the fact that the "building
blocks" were unbalanced is enough to warp the final boards.
By the way, I think 7 weeks seems about right for building something like
this the first time. If at all possible, I'd try to simplify the structure
to reduce the sequential lamination sequences. Laser microvias and
controlled depth drills can be helpful in doing this.
I saw from your other posting that your fabricator is going to try to grind
down the accumulated plating thickness. I don't want to dash your hopes but
there is a fair amount of risk in doing so. One of the challenges in
building a multi-level board like this is understanding how the different
layers move through each level of the build. That's part of what takes 7
weeks. You have to build the board almost all the way through the process
to monitor and correct for the shifts that occur. On something this complex
even the second pass might not be correct. Except for the line width issues
your fabricator has presumably gone through this process and learned all of
this. But now they are going to grind off the plating. Unfortunately,
grinding also stretches the panel, which means the data they collected on
the previous builds likely won't be applicable. It's not unheard of to have
1 mm or more of growth on a panel. I'm guessing your IL pads and clearances
weren't designed to accommodate such misregistration. They'll likely have
to re-characterize the movement of the board and re-size the IL accordingly.
Good luck, but don't be surprised if the first re-build has some
registration issues.
> ----------
> From: <Peter George Duncan>[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Sunday, November 18, 2001 10:24 PM
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Edward,
>
> The heavy copper weight resulting from all these plating processes was
> recognised early on, but a) we assumed it would be reasonably even across
> the board surface, and b) was not so heavy that the required widths and
> spacings couldn't achieved after final etch. Certainly it wasn't flagged
> up
> to us by the fab house as being a problem.
>
> A very similar board was made by another fab house with no problem, apart
> from the boards being warped. The etching was fine - it's just that they
> took 7 weeks to make them on priority, which we couldn't afford again.
>
> Hmmm! The things we have to find out the hard way.
>
> Peter Duncan
>
>
>
>
>
> Edward
>
> Szpruch To: [log in to unmask]
>
> <edward@ELTEK cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> .CO.IL> Aero/ST Group)
>
> Sent by: Subject: Re: [TN] Over-etch
>
> TechNet
>
> <[log in to unmask]
>
> ORG>
>
>
>
>
>
> 11/18/01
>
> 03:08 PM
>
> Please
>
> respond to
>
> "TechNet
>
> E-Mail
>
> Forum."
>
>
>
>
>
>
>
>
>
> Peter,
> Let me refrase your question from plating point of view since you rised 1
> milion dollar question:
> How to plate the holes without plating the surface.
> As far as I know,the best equipment,the best technologies,the best
> chemistry
> etc have limitited capacity in terms of throwing capability ( ratio of
> metal
> plated inside the hole to metal plated on the surface).The best figure is
> slighty above 1.0 , usually is less than 1.0 .
> No magic in this area:if the design requires to plate 3 times at least 20
> microns or so in the holes, the surface will get additional around 60 -70
> microns of copper before plating and etching of the final pattern.
> PCB designer should know this basic fact of life while imposing fancy
> construction.
> Of course PCB manufacturer has some possibilities to manipulate artwork
> compensations according to copper thickness to be etched, but etching
> factors are also fact of life.
> There are some tricky ways,but most of them are not working well on HDI
> boards with fine lines.
> Edward
>
> Edward Szpruch
> Eltek Ltd
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>
> > -----Original Message-----
> > From: <Peter George Duncan> [SMTP:[log in to unmask]]
> > Sent: å ðåáîáø 16 2001 10:04
> > To: [log in to unmask]
> > Subject: Re: [TN] Over-etch
> >
> > Hi, Rudy,
> >
> > The boards are ENIG finished, the ENIG plating being carried out
> > post-solder-mask, which must be after final copper etch, so No, there is
> > no
> > other metal in the area, unless my understanding of the plating/etching
> > sequence is all wrong. My understanding (faulty or otherwise) of what
> the
> > fab house has done, is that they laminate, drill and plate the layers
> with
> > the first suite of blind vias, then laminate, drill and plate for the
> > second suite of blind vias, then again for the 3rd suite until
> everything
> > is stacked up, pressed, drilled and plated for the through-holes. I
> > haven't
> > quite been able to make sense of it all yet, but I think what I'm being
> > told is that the plating becomes "stepped" somehow. I have 3 sets of
> blind
> > vias from each outer surface (for ease of argument), making 4 plating
> > sessions on each side by the time the through-hole group is done. The
> > first
> > areas to be drilled and plated are therefore plated 4 times, while the
> > last
> > areas to be drilled are only plated once, with the groups in between
> > getting their proportional share of multiple plating.
> >
> > Thus at final etch, there is, I am told, a compromise to be reached -
> how
> > to achieve the correct widths and spacings on the heavily plated areas
> > without over-etching the lightly-plated areas. In my simple way, I would
> > have expected the entire board surface to have an even plating
> thickness,
> > however thick, but seemingly not. The compromise hasn't worked for the
> > number of blind via groups featured in this board, and I need to try to
> > find out how to address a solution without solely relying on what our
> fab
> > house tells me.
> >
> > In my entire life, I never had to worry about the processes involved in
> > fabricating PCB's - only that components could be soldered to them, that
> > they passed test and proved to be reliable in the field. I only ever
> > worked
> > with good boards - the ones that passed in-coming inspection - in an
> > assembly environment, so my experience of board design and PCB fab is
> > limited to the past 8 or 9 months, in a company that has no previous
> > convictions for designing this type of board, so it's a case of the
> blind
> > leading the blind to a certain extent.
> >
> > Any further help in this area would be greatly appreciated.
> >
> > Best regards
> >
> > Peter Duncan
> >
> >
> >
> >
> > "<Rudy
> > Sedlak>" To: [log in to unmask]
> > Sent by: cc: (bcc: DUNCAN Peter/Asst
> > Prin Engr/ST
> > TechNet Aero/ST Group)
> > <[log in to unmask] Subject: Re: [TN] Over-etch
> > ORG>
> >
> >
> > 11/16/01
> > 02:13 PM
> > Please
> > respond to
> > "TechNet
> > E-Mail
> > Forum."
> >
> >
> >
> >
> >
> >
> > Peter:
> >
> > I am not sure if I fully understand the process you are using....so I am
> > going to ask a dumb question, that may shed some light on the issue...
> >
> > Is there, anywhere in electrical contact with Copper being etched any
> > other
> > metal excepting Tin?
> >
> > This sort of thing, selective over-etch, is classically seen when there
> is
> > some other metal, (Nickel, Gold, or???) than Tin in electrical contact
> > with
> > the over-etched Copper, and also in contact with the etchant.
> >
> > And if I am completely out in space with this question, please forgive
> the
> > intrusion.
> >
> > Rudy Sedlak
> >
> >
> --------------------------------------------------------------------------
> > -------
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> >
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========================================================================Date: Thu, 22 Nov 2001 07:54:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I think this one depends on which side of the fence you are on.
I personally would prefer not to have any track repairs. If you do decide
to allow repairs then I would get a copy of IPC7721 and decide which of the
many methods in the standard you want your supplier to use. I would also
insist that any repaired boards are segregated from normal production with a
list of the locations of the repairs.
If you make the procedure complex enough your supplier may just decide it's
not worth the bother and scrap them / improve his yield!!
Neil
-----Original Message-----
From: Kathy Bergman [mailto:[log in to unmask]]
Sent: 21 November 2001 17:41
Subject: Re: Raw Card Track Repairs
IPC-6012A describes the characteristic "circuit repairs" as being acceptable
in Class 1, 2,
and 3 only "As agreed by user and supplier." Generally these repairs, if
done properly, are
reliable. See IPC 7721 for methods. It is your call, basically.
K. Bergman
Stephen Brown wrote:
> People.
>
> We get our PCB's assembled to IPC-610 class 2. We have recently been
> approached by our vendor regarding track repairs on our raw cards. Now I
> personally am not keen on allowing this, but is there a standard for raw
> cards similar to 610 which states an allowable quantity of track
> repairs, if any?
>
> Regards.
>
> Steve Brown.
> Commodity Specialist
> Xyratex.
>
>
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========================================================================Date: Thu, 22 Nov 2001 17:07:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Hi, Michael,
Thanks very much indeed for your input, even though it looks as though
you're confirming my worst fears. I made a phone call to the States
specifically on the grinding issue on Tuesday morning, as I was concerned,
not about stretch, as I didn't know to consider that, but about the risk of
over-doing it and removing pads or making them too thin.
I honestly believe that the design itself is balanced in terms of copper
distribution, as I calculated the copper volume for each layer and compared
each to its opposite number in the stack-up. But I see and understand that
the increasing weight on the outer layers with the number of sequential
plating processes could warp those layers already laminated. I was crossing
my fingers and hoping that the opposing bows of the two halves of the board
would cancel each other out and relieve the stresses in the final pressing
that joins them together. Is that being naive?
I'll warn our fab house about the stretch and registration issues, and note
their response. That is a real concern, though having said that, all the
boards on this project have a grinding operation to level silver epoxy in
the thermal vias with the surface of the board, and those boards have been
very successful, albeit all the holes are through-holes (no blinds apart
from these two boards).
The fab house's current attempt is their third - the second one took them
(via a subcontractor) into laser drilling for the first time, and it was a
disaster. Every board failed electrical test big time with missing
connectivity, and drilling too deep and contacting other layers. Put me off
laser drilling rather, though I understand from fab houses with more
experience of this that after some practice it is a very reliable process,
as are the subsequent plating operations.
The bottom line is that we didn't know enough about the pitfalls with this
type of design to take steps to counteract them. We learn the hard way, but
still have to get the darned things made somehow!
My profound thanks again for taking the trouble to write.
Best regards
Peter
ST Aerospace
"Mcmaster,
Michael" To: [log in to unmask]
<michaelm@MER cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
IX.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/22/01
08:49 AM
Please
respond to
"TechNet
E-Mail
Forum."
Peter
I think we now know why you've had warpage problems on the other boards.
Building up unequally thick sequentially laminated parts then laminating
them together is likely the underlying asymmetry that's warping the boards.
Even if in the final stackup appears symmetric the fact that the "building
blocks" were unbalanced is enough to warp the final boards.
By the way, I think 7 weeks seems about right for building something like
this the first time. If at all possible, I'd try to simplify the structure
to reduce the sequential lamination sequences. Laser microvias and
controlled depth drills can be helpful in doing this.
I saw from your other posting that your fabricator is going to try to grind
down the accumulated plating thickness. I don't want to dash your hopes
but
there is a fair amount of risk in doing so. One of the challenges in
building a multi-level board like this is understanding how the different
layers move through each level of the build. That's part of what takes 7
weeks. You have to build the board almost all the way through the process
to monitor and correct for the shifts that occur. On something this
complex
even the second pass might not be correct. Except for the line width
issues
your fabricator has presumably gone through this process and learned all of
this. But now they are going to grind off the plating. Unfortunately,
grinding also stretches the panel, which means the data they collected on
the previous builds likely won't be applicable. It's not unheard of to
have
1 mm or more of growth on a panel. I'm guessing your IL pads and
clearances
weren't designed to accommodate such misregistration. They'll likely have
to re-characterize the movement of the board and re-size the IL
accordingly.
Good luck, but don't be surprised if the first re-build has some
registration issues.
> ----------
> From: <Peter George Duncan>[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Sunday, November 18, 2001 10:24 PM
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Edward,
>
> The heavy copper weight resulting from all these plating processes was
> recognised early on, but a) we assumed it would be reasonably even across
> the board surface, and b) was not so heavy that the required widths and
> spacings couldn't achieved after final etch. Certainly it wasn't flagged
> up
> to us by the fab house as being a problem.
>
> A very similar board was made by another fab house with no problem, apart
> from the boards being warped. The etching was fine - it's just that they
> took 7 weeks to make them on priority, which we couldn't afford again.
>
> Hmmm! The things we have to find out the hard way.
>
> Peter Duncan
>
>
>
>
>
> Edward
>
> Szpruch To: [log in to unmask]
>
> <edward@ELTEK cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> .CO.IL> Aero/ST Group)
>
> Sent by: Subject: Re: [TN] Over-etch
>
> TechNet
>
> <[log in to unmask]
>
> ORG>
>
>
>
>
>
> 11/18/01
>
> 03:08 PM
>
> Please
>
> respond to
>
> "TechNet
>
> E-Mail
>
> Forum."
>
>
>
>
>
>
>
>
>
> Peter,
> Let me refrase your question from plating point of view since you rised 1
> milion dollar question:
> How to plate the holes without plating the surface.
> As far as I know,the best equipment,the best technologies,the best
> chemistry
> etc have limitited capacity in terms of throwing capability ( ratio of
> metal
> plated inside the hole to metal plated on the surface).The best figure is
> slighty above 1.0 , usually is less than 1.0 .
> No magic in this area:if the design requires to plate 3 times at least 20
> microns or so in the holes, the surface will get additional around 60 -70
> microns of copper before plating and etching of the final pattern.
> PCB designer should know this basic fact of life while imposing fancy
> construction.
> Of course PCB manufacturer has some possibilities to manipulate artwork
> compensations according to copper thickness to be etched, but etching
> factors are also fact of life.
> There are some tricky ways,but most of them are not working well on HDI
> boards with fine lines.
> Edward
>
> Edward Szpruch
> Eltek Ltd
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>
> > -----Original Message-----
> > From: <Peter George Duncan> [SMTP:[log in to unmask]]
> > Sent: å ðåáîáø 16 2001 10:04
> > To: [log in to unmask]
> > Subject: Re: [TN] Over-etch
> >
> > Hi, Rudy,
> >
> > The boards are ENIG finished, the ENIG plating being carried out
> > post-solder-mask, which must be after final copper etch, so No, there
is
> > no
> > other metal in the area, unless my understanding of the plating/etching
> > sequence is all wrong. My understanding (faulty or otherwise) of what
> the
> > fab house has done, is that they laminate, drill and plate the layers
> with
> > the first suite of blind vias, then laminate, drill and plate for the
> > second suite of blind vias, then again for the 3rd suite until
> everything
> > is stacked up, pressed, drilled and plated for the through-holes. I
> > haven't
> > quite been able to make sense of it all yet, but I think what I'm being
> > told is that the plating becomes "stepped" somehow. I have 3 sets of
> blind
> > vias from each outer surface (for ease of argument), making 4 plating
> > sessions on each side by the time the through-hole group is done. The
> > first
> > areas to be drilled and plated are therefore plated 4 times, while the
> > last
> > areas to be drilled are only plated once, with the groups in between
> > getting their proportional share of multiple plating.
> >
> > Thus at final etch, there is, I am told, a compromise to be reached -
> how
> > to achieve the correct widths and spacings on the heavily plated areas
> > without over-etching the lightly-plated areas. In my simple way, I
would
> > have expected the entire board surface to have an even plating
> thickness,
> > however thick, but seemingly not. The compromise hasn't worked for the
> > number of blind via groups featured in this board, and I need to try to
> > find out how to address a solution without solely relying on what our
> fab
> > house tells me.
> >
> > In my entire life, I never had to worry about the processes involved in
> > fabricating PCB's - only that components could be soldered to them,
that
> > they passed test and proved to be reliable in the field. I only ever
> > worked
> > with good boards - the ones that passed in-coming inspection - in an
> > assembly environment, so my experience of board design and PCB fab is
> > limited to the past 8 or 9 months, in a company that has no previous
> > convictions for designing this type of board, so it's a case of the
> blind
> > leading the blind to a certain extent.
> >
> > Any further help in this area would be greatly appreciated.
> >
> > Best regards
> >
> > Peter Duncan
> >
> >
> >
> >
> > "<Rudy
> > Sedlak>" To: [log in to unmask]
> > Sent by: cc: (bcc: DUNCAN
Peter/Asst
> > Prin Engr/ST
> > TechNet Aero/ST Group)
> > <[log in to unmask] Subject: Re: [TN]
Over-etch
> > ORG>
> >
> >
> > 11/16/01
> > 02:13 PM
> > Please
> > respond to
> > "TechNet
> > E-Mail
> > Forum."
> >
> >
> >
> >
> >
> >
> > Peter:
> >
> > I am not sure if I fully understand the process you are using....so I
am
> > going to ask a dumb question, that may shed some light on the issue...
> >
> > Is there, anywhere in electrical contact with Copper being etched any
> > other
> > metal excepting Tin?
> >
> > This sort of thing, selective over-etch, is classically seen when there
> is
> > some other metal, (Nickel, Gold, or???) than Tin in electrical contact
> > with
> > the over-etched Copper, and also in contact with the etchant.
> >
> > And if I am completely out in space with this question, please forgive
> the
> > intrusion.
> >
> > Rudy Sedlak
> >
> >
>
--------------------------------------------------------------------------
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========================================================================Date: Thu, 22 Nov 2001 08:49:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ian Hanna <[log in to unmask]>
Subject: Re: Over-etch
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
just a quick note on lasing...i found it, once dialed in, to be a very good
process. the biggest deal besides ablating the holes is plating
them...sounds like an old song now. it took me less than a week to work up
a very wide process window for 1080 fr-4 with an nd/yag UV laser.
everything looked great on the microsections but we found we had about .5%
fall out due to plating voids in the finished boards...a difficult number to
really work with, too slim for easy failure analysis yet one or two opens
per board didn't work...used really low amps and a couple of 'cheats' at
electroless (metalization) to get the job out...and ended up going to
complex waveform reverse pulse plating...which made things more or less a
cake-walk...bottom line is that if i was to bring laser drilling in house
again i'd sub-contract the drilling (that is hold off on the rather
substantial capitol investment in a laser via machine) until i had the rest
of my processes dialed in...registration on n-1 layers...coordinating the
registration between the mechanical hole grid and the micro-via
placement...and of course reliable process....one of the more 'holistic'
processes i've worked with...everything needs to work together, you can't
just ship out panels for drilling and process them the same old way...
might as well throw in my $.02 worth on your grinding idea....i'm a little
concerned about the integrity of the 'knees' of the plated barrels...it's
always nice to see an even coating of rich, thick, well leveled copper going
from the surface all the way into the barrel of the hole...interrupting
this, then re-plating over top -might- not give you as solid a 'knee' and
with board expansion from z-axis CTE mismatches so common in fr-4
construction, you might see a higher than normal drop out well after the
fabrication fact...i'd do some fairly aggressive solder floats, at least 5x
10 seconds in a pot of 550 degrees and look for any signs of failure...to
ensure that there are no long-term reliability issuesthat being said,
i've plated, filled and ground lots of blind vias without too many
reliability issues in avionics applications...so it's do-able...just so
you're aware of potential pit-falls really...
good luck...sounds like an exciting project
ian
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========================================================================Date: Thu, 22 Nov 2001 12:12:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: another one bites the dust
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Dear Technetters,
I'm sorry to report that my current employer has closed down. Mosaic Printed
Circuits (formerly Quality Printed Circuits) shut down November 16, 2001.
I am still on techet and will contribute as I can while searching for new
employment. Hopefully, this will be a temporary condition.
Chemically yours,
Russell Burdick
Process Engineer
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
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========================================================================Date: Thu, 22 Nov 2001 15:56:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Crain <[log in to unmask]>
Subject: best finish for through hole boards
Good day tech-net
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========================================================================Date: Thu, 22 Nov 2001 16:14:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Crain <[log in to unmask]>
Subject: best finish for through hole boards
I am not sure why an empty message just got posted. Anyway, here is my
question: We are looking to standardize our board finish for all of our
through-hole boards. We have many types of finishes (mat or flat,gloss,
semi-gloss, dark green, light green)and are looking to change to the mat
finish to cover, um hide, the little bit of flux residue that we find
exceptable. We use a no-clean flux.
Is there any difference in solderability when using different finishes. Do
the profiles change between board finishes? Does the type of finish affect
defect rate? What are other's using and finding best results?
Thanks
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========================================================================Date: Fri, 23 Nov 2001 12:15:34 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Ian,
I've attracted a remarkable amount of correspondence on this subject, and
have been very impressed with the help and information received. Laser
drilling is brand new to me, and with everyone's help, I feel I'm building
up a pretty comprehensive overview of this technology, which is very
interesting learning. It's a tricky process, it seems in inexperienced
hands, but for people who know it, they say it's every bit as reliable as
more conventional methods and much cheaper. Hopefully we won't have too
many projects that require it, unless we do find a fab house at the right
price who can successfully handle all the processes.
On the grinding thang, your concern was exactly mine when it was first
proposed by the fab house - by grinding off the plated copper, I'ld be left
with plated copper joined to the inside thickness of the original pad. I've
seen enough microsections in my time to know that there is a "weakness" at
the interface of these two metalisations. Although there is a final plating
session that will cover a lot of this, still it is a concern.
Thanks again to you and all the others who have responded on this issue. I
hope it's helped more people than just me.
Best regards
Peter Duncan
Ian Hanna
<ianh@LAZER-T To: [log in to unmask]
ECH.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Over-etch
<[log in to unmask]
ORG>
11/22/01
09:49 PM
Please
respond to
"TechNet
E-Mail
Forum."
just a quick note on lasing...i found it, once dialed in, to be a very good
process. the biggest deal besides ablating the holes is plating
them...sounds like an old song now. it took me less than a week to work up
a very wide process window for 1080 fr-4 with an nd/yag UV laser.
everything looked great on the microsections but we found we had about .5%
fall out due to plating voids in the finished boards...a difficult number
to
really work with, too slim for easy failure analysis yet one or two opens
per board didn't work...used really low amps and a couple of 'cheats' at
electroless (metalization) to get the job out...and ended up going to
complex waveform reverse pulse plating...which made things more or less a
cake-walk...bottom line is that if i was to bring laser drilling in house
again i'd sub-contract the drilling (that is hold off on the rather
substantial capitol investment in a laser via machine) until i had the rest
of my processes dialed in...registration on n-1 layers...coordinating the
registration between the mechanical hole grid and the micro-via
placement...and of course reliable process....one of the more 'holistic'
processes i've worked with...everything needs to work together, you can't
just ship out panels for drilling and process them the same old way...
might as well throw in my $.02 worth on your grinding idea....i'm a little
concerned about the integrity of the 'knees' of the plated barrels...it's
always nice to see an even coating of rich, thick, well leveled copper
going
from the surface all the way into the barrel of the hole...interrupting
this, then re-plating over top -might- not give you as solid a 'knee' and
with board expansion from z-axis CTE mismatches so common in fr-4
construction, you might see a higher than normal drop out well after the
fabrication fact...i'd do some fairly aggressive solder floats, at least 5x
10 seconds in a pot of 550 degrees and look for any signs of failure...to
ensure that there are no long-term reliability issuesthat being said,
i've plated, filled and ground lots of blind vias without too many
reliability issues in avionics applications...so it's do-able...just so
you're aware of potential pit-falls really...
good luck...sounds like an exciting project
ian
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---------------------------------------------------------------------------------
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========================================================================Date: Fri, 23 Nov 2001 09:07:54 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Storage of moisture sensitive components
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)"
This is a multi-part message in MIME format.
--Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)
Content-type: text/plain; charset=windows-1255
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How long and in what conditions may moisture sensitive components be stored in their original package?
Thank.you,
Gaby
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<DIV><FONT face=Arial size=2>How long and in what conditions may moisture
sensitive components be stored in their original
package?<BR>Thank.you,<BR>Gaby</FONT></DIV></BODY></HTML>
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========================================================================Date: Fri, 23 Nov 2001 10:05:11 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
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Gaby,
that should be written on the label of the original package ( if it´s
according to J-STD-033 ). In most cases dependend on the material used it
reads 12 month from packing date (bag seal date) which also should be on
that label.
You may get yourself a copy of J-STD-033 which can be downloaded ( for free
:-) ) from JEDEC or IPC, don´t remember which one it was.
In case of doubt get and follow the manufacturers recommendations.
Wolfgang
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Friday, November 23, 2001 8:08 AM
To: [log in to unmask]
Subject: [TN] Storage of moisture sensitive components
How long and in what conditions may moisture sensitive components be stored
in their original package?
Thank.you,
Gaby
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========================================================================Date: Fri, 23 Nov 2001 11:14:12 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
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Thanks!
Gaby
----- Original Message -----
From: "Busko, Wolfgang" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, November 23, 2001 11:05 AM
Subject: Re: [TN] Storage of moisture sensitive components
> Gaby,
>
> that should be written on the label of the original package ( if it´s
> according to J-STD-033 ). In most cases dependend on the material used it
> reads 12 month from packing date (bag seal date) which also should be on
> that label.
> You may get yourself a copy of J-STD-033 which can be downloaded ( for
free
> :-) ) from JEDEC or IPC, don´t remember which one it was.
> In case of doubt get and follow the manufacturers recommendations.
>
> Wolfgang
>
>
> -----Original Message-----
> From: Gaby Bogdan [mailto:[log in to unmask]]
> Sent: Friday, November 23, 2001 8:08 AM
> To: [log in to unmask]
> Subject: [TN] Storage of moisture sensitive components
>
>
> How long and in what conditions may moisture sensitive components be
stored
> in their original package?
> Thank.you,
> Gaby
>
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========================================================================Date: Fri, 23 Nov 2001 12:30:48 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: best finish for through hole boards
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I think that this is a chicken and egg question and needs to be considered
from a PCB fab viewpoint as well. It is expensive for a pcb fab house to
have more than one soldermask, because they have to pay for UL approval,
because they cannot 'leverage' their supply as well (lower volume), because
they either have to have seperate equipment or incur set up costs every
time they change ink, and because they have to change their exposure,
developing and cure cycle settings for different inks. The metal finish
required by the customer - HASL, ENIG, Immersion silver, immersion tin,
entek - also has an effect on the ink that can be used - many inks do not
withstand the chemical attack from these finishes, so I would suggest you
go back to your PCB supplier(s) and ask the question how will this affect
their supply to you (and ask the Operations or Technical Director, not the
sales guy who will say no problem - I speak from experience) and by how it
may affect their supply, I include lead time, UL certification, metal
finish options, SIR and SECC conformity. It may just be green paint to you,
but it has a major impact on the fab process.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Peter Crain [SMTP:[log in to unmask]]
Sent: 22 November 2001 22:14
To: [log in to unmask]
Subject: [TN] best finish for through hole boards
I am not sure why an empty message just got posted. Anyway, here is my
question: We are looking to standardize our board finish for all of our
through-hole boards. We have many types of finishes (mat or flat,gloss,
semi-gloss, dark green, light green)and are looking to change to the mat
finish to cover, um hide, the little bit of flux residue that we find
exceptable. We use a no-clean flux.
Is there any difference in solderability when using different finishes. Do
the profiles change between board finishes? Does the type of finish affect
defect rate? What are other's using and finding best results?
Thanks
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========================================================================Date: Sat, 24 Nov 2001 07:36:52 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
MIME-Version: 1.0
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Sasha,
Congrats on being the new senior fellow regarding PCB for vacuum (not to be
confused with designing in a vacuum). If you have a need for non outgassing
soldermask in future let me know, my fab house in Denver uses it on a regular
basis. Glad to hear it was a happy ending.
Coretec Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Sasha,
<BR>
<BR>Congrats on being the new senior fellow regarding PCB for vacuum (not to be confused with designing in a vacuum). If you have a need for non outgassing soldermask in future let me know, my fab house in Denver uses it on a regular basis. Glad to hear it was a happy ending.
<BR>
<BR>Coretec Brad</FONT></HTML>
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========================================================================Date: Sat, 24 Nov 2001 13:27:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: unsubscribe
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Dorothy Lush
Solectron
408 957 2736
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========================================================================Date: Sun, 25 Nov 2001 00:57:42 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
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Sasha,
I don't have experience with PCB's in a vacuum system, but I do have some
experience with lots of other materials in high vacuum as I used to work
designing electronics for mass spectrometers. I'm an EE, not a materials
person, but a few insights rubbed off on me while I worked with them. The
high vacuum part of our system was around 10exp(-9) torr, so I don't know if
this is the same range that you are concerned with.
However, in this range of vacuum, the main problem was any surface
irregularities that could contain bits of material that slowly but steadily
vaporize at this low pressure level. If you inserted a "dirty" piece into
the vacuum system, you could wait days for the pressure to approach the
final value. If the part was dirty enough, you could wait a week or more
and perhaps never get there. We called this phenomenon a virtual leak.
That is, when a part has enough material with low volatility in it, the
steady outgassing acts similarly to a small leak in the chamber. Heating
the vacuum chamber and the parts inside it speeds up this process quite a
bit. Since the parts in our system were made of stainless steel, ceramics
and glasses, we could heat the system to 350 degrees C. for several days to
get everything clean and the pressures stable. Since the instrument was a
mass spectrometer, we had the luxury of being able to monitor the
composition of the outgassed material and it was usually water! Even at 350
degrees C. and high vacuum, it could take days for most of the water to come
off. Obviously, you can't do this with a PCB but heating helps get the
outgassing over with sooner.
The bottom line is that any rough or porous materials are bad news in a high
vacuum system, as it makes it very difficult to get them truly clean. That
is why I'm not surprised that boards with solder mask performed worse than
boards with no mask. We look at solder mask and think of it as a smooth
"sealing" layer, but on a micro scale, I bet it looks like a piece of
Muenster cheese. The board itself will entrap material in its surface, then
you cover it up with another porous layer that entraps more material and the
composite will outgas for a long time. Also, any uncured mask would
probably outgas badly for a long period.
If I were to guess how to improve things, I might try using the thinnest
laminate possible so entrapped material had the best chance to get out.
Beyond that, I'm on pretty thin ice. I would guess you want a resin
material that has the fewest voids and the lowest gas diffusion rate, but I
could be way off on this. Also, I don't know the properties of the copper
foils and the electrodeposited copper used in PCB fabrication with respect
to outgassing. Any materials scientists out there care to pick this up?
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Sasha Miladinovic
> Sent: Wednesday, November 21, 2001 10:01 AM
> To: [log in to unmask]
> Subject: Re: [TN] HELP <=> PCB vs. High Vacuum <=> HELP
>
>
> Earl, Brad,
>
> Thank you for the answers. Obviously, there is no a lots of experiences on
> this area among TechNetters or the question itself wasn't interesting
> enough. :)
> However I just want to follow up this subject with the experiences that I
> gained during the testing of the PCB in vacuum chamber. I hope
> that this is
> going to help someone in the future.
> I found that the best solution was to add two extra layers (top
> and bottom)
> to the PCBs that are only containing pads and annular rings for the plated
> holes. Pads are connected with the layers with hidden vias. That way, I
> minimised the amount of the exposed copper/ENIG on the surface of the PCB.
> There is no coating on the laminate at all, which minimises outgassing (I
> wouldn't believe this if I haven't seen it myself).
> I'm washing the flux residues away directly after the reflow, first with
> Zestron and than with not-ionised water. After this, the PCBs are
> baked and
> stored in the nitrogen atmosphere. Before mounting the PCBs in to the
> vacuum the PCBs are stored in the vacuum chamber during the 8
> hours period,
> outgassing as much as possible. When this procedure is finnished and the
> PCBs are mounted in to the vacuum, make little prayer and hope
> for the best
> when you push "ON" button. :)
>
> Sasha Miladinovic
>
>
> **********************************************************************
> Sasha Miladinovic - Production Engineering
> Amersham Biosciences, PCB Production, Umeå
> Tel: +46 (0) 90 150 232
> Fax: +46 (0) 90 138 372
> E-mail: [log in to unmask]
> **********************************************************************
>
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========================================================================Date: Mon, 26 Nov 2001 16:00:47 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
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Thanks on the promotion. :)
Sasha
*************************************************************************
Sasha Miladinovic - Production Engineering
Amersham Biosciences, PCB Production, Umeå
Tel: +46 (0) 90 150 232
Fax: +46 (0) 90 138 372
E-mail: [log in to unmask]
*************************************************************************
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========================================================================Date: Mon, 26 Nov 2001 10:07:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: BGA long term storage?
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Good day Technet! Hope my friends to the south had a good Thanksgiving holiday!
A question today concerning shelf life and storage. We build equipment that is expected to be supported for a fairly long time - say a decade or more. We are also as an industry moving to using COTS (commercial) components to reduce cost. Fine and good, but the life cycle for commercial parts is often pretty short compared with a military spec'd component - which puts us into a life time buy situation earlier rather than later.
My question:
Is there a good method to use to store BGA type components for long term storage? E.G. I build board X using a particular BGA part. It goes "end of life" a couple of years later, but I'm expected to support repair and overhaul for another few years yet, so I buy as many as I predict I'll need. As the time goes on, the solder balls oxidize. How should I store the spare parts? In nitrogen? Cold environment? Will it even be a problem?
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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========================================================================Date: Mon, 26 Nov 2001 16:31:35 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: BGA long term storage?
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Hi Graham,
Long term storage is more a problem for QFP's and other leaded parts, where intermetallics can make the parts unsolderable.
The oxidation that you will have on the BGA's balls is what you're using flux for. I don't think you will have any soldering problem at all, as long as you bake before soldering.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Graham Collins <[log in to unmask]> 11/26 4:07 pm >>>
Good day Technet! Hope my friends to the south had a good Thanksgiving holiday!
A question today concerning shelf life and storage. We build equipment that is expected to be supported for a fairly long time - say a decade or more. We are also as an industry moving to using COTS (commercial) components to reduce cost. Fine and good, but the life cycle for commercial parts is often pretty short compared with a military spec'd component - which puts us into a life time buy situation earlier rather than later.
My question:
Is there a good method to use to store BGA type components for long term storage? E.G. I build board X using a particular BGA part. It goes "end of life" a couple of years later, but I'm expected to support repair and overhaul for another few years yet, so I buy as many as I predict I'll need. As the time goes on, the solder balls oxidize. How should I store the spare parts? In nitrogen? Cold environment? Will it even be a problem?
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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========================================================================Date: Mon, 26 Nov 2001 16:45:47 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Isolation between connector pins
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Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is possible to have some extra isolation between these pins. I was thinking that a drop of solderresist that we sometimes use for repairs would do the job, but I'm not sure that it'll work. Maybe someone can give me a better advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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========================================================================Date: Mon, 26 Nov 2001 11:40:13 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0
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Welcome to the COTS catch 22,
My experience is the best laid plans of "buy out and save" haven't worked.
What I've seen is the need to "Revision" spin for parts acceptibility or
repackage die either from the silicin to the package needed or have the sub
harvest from one package to the one needed. It just doesn't seem reasonable
to store piece parts for more than three years never mind ten plus.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Welcome to the COTS catch 22,
<BR>My experience is the best laid plans of "buy out and save" haven't worked. What I've seen is the need to "Revision" spin for parts acceptibility or repackage die either from the silicin to the package needed or have the sub harvest from one package to the one needed. It just doesn't seem reasonable to store piece parts for more than three years never mind ten plus.
<BR>
<BR>Brad</FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 11:45:50 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Isolation between connector pins
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I am seeing this 200 volt requirement everywhere. Hopefully you separate the
two signals in the schematic. Hopefully it isn't two adjacent pins
regardless of signal. Loctite, E/C or the equivalent source will have an
electrically isolating compound (such as used in backshells); but the
application is going to very costly in ongoing assemblies.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I am seeing this 200 volt requirement everywhere. Hopefully you separate the two signals in the schematic. Hopefully it isn't two adjacent pins regardless of signal. Loctite, E/C or the equivalent source will have an electrically isolating compound (such as used in backshells); but the application is going to very costly in ongoing assemblies.
<BR>
<BR>Brad</FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 12:18:02 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Buried Capacitance - unlicensed
MIME-Version: 1.0
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Sorry for the tardy reply, I am just affording some time now.
Coretec is a licensed PWB/PCB supplier of the buried capacitance material
"BC2000" (the Z has been dropped). Suppliers of substrate material are
required to report all shipments of clad 1-3 core. There is sufficient fines
that board suppliers will not risk doing quasi capacitance boards. Over .003
thick there is little capacitance gain (no pun intended), the patent
threshold. There is the propensity, which isn't bad. I know folks in the
business do not like nor agree with the patent and I am aware of and been to
the seminar where it is insinuated that the patent rights can be side
stepped. I personally feel the rights of the patentee must be respected and
in a business sense it just isn't worth the risk (monetarily).
Lastly, those who know how to build are successful, those who don't; aren't.
It is not like traces, opposing planes are different; hence the patent.
If there are any technical questions please contact me.
Best Regards,
Coretec's Boston Brad
781-858-0783
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Sorry for the tardy reply, I am just affording some time now.
<BR>
<BR>Coretec is a licensed PWB/PCB supplier of the buried capacitance material "BC2000" (the Z has been dropped). Suppliers of substrate material are required to report all shipments of clad 1-3 core. There is sufficient fines that board suppliers will not risk doing quasi capacitance boards. Over .003 thick there is little capacitance gain (no pun intended), the patent threshold. There is the propensity, which isn't bad. I know folks in the business do not like nor agree with the patent and I am aware of and been to the seminar where it is insinuated that the patent rights can be side stepped. I personally feel the rights of the patentee must be respected and in a business sense it just isn't worth the risk (monetarily).
<BR>Lastly, those who know how to build are successful, those who don't; aren't. It is not like traces, opposing planes are different; hence the patent.
<BR>If there are any technical questions please contact me.
<BR>
<BR>Best Regards,
<BR>Coretec's Boston Brad
<BR>781-858-0783</FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 12:29:09 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Copper Invar Copper and BGA's
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I have used both core and foil CIC boards and it is more challenging than non
metal boards. The rework was easier than the original profiling. That is
good. The need for touch up after reflow was common place. I never did
BGAs, but the need for heat in a BGA and the need for heat in CIC combined
with elongation of duration lends this CIC/BGA configuration as a predictable
need for touch up (can't touch up under a BGA easily). I might advise to
attach the BGAs after initial solder float. It is not very economical, but
then again neither is CIC.
I have had success with CIC and Thermount. Thermount has all but killed CIC
although there are moisture issues with Thermount. I say this relative to
the ongoing existence of CIC. The rumor mill had it that CIC was going the
way of Howefill... discontinued.
Coretec Brad
781 858 0783
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I have used both core and foil CIC boards and it is more challenging than non metal boards. The rework was easier than the original profiling. That is good. The need for touch up after reflow was common place. I never did BGAs, but the need for heat in a BGA and the need for heat in CIC combined with elongation of duration lends this CIC/BGA configuration as a predictable need for touch up (can't touch up under a BGA easily). I might advise to attach the BGAs after initial solder float. It is not very economical, but then again neither is CIC.
<BR>
<BR>I have had success with CIC and Thermount. Thermount has all but killed CIC although there are moisture issues with Thermount. I say this relative to the ongoing existence of CIC. The rumor mill had it that CIC was going the way of Howefill... discontinued.
<BR>
<BR>Coretec Brad
<BR>781 858 0783</FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 12:46:51 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Copper Invar Copper and BGA's
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Hi Brad!
Have you heard anything about StableCorâ„¢ PCB's? Go to:
-Steve Gregory-
> I have used both core and foil CIC boards and it is more challenging than
> non metal boards. The rework was easier than the original profiling. That
> is good. The need for touch up after reflow was common place. I never did
> BGAs, but the need for heat in a BGA and the need for heat in CIC combined
> with elongation of duration lends this CIC/BGA configuration as a
> predictable need for touch up (can't touch up under a BGA easily). I might
> advise to attach the BGAs after initial solder float. It is not very
> economical, but then again neither is CIC.
>
> I have had success with CIC and Thermount. Thermount has all but killed
> CIC although there are moisture issues with Thermount. I say this relative
> to the ongoing existence of CIC. The rumor mill had it that CIC was going
> the way of Howefill... discontinued.
>
> Coretec Brad
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Brad!
<BR>
<BR>Have you heard anything about StableCorâ„¢ PCB's? Go to:
<BR>
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I have used both core and foil CIC boards and it is more challenging than non metal boards. The rework was easier than the original profiling. That is good. The need for touch up after reflow was common place. I never did BGAs, but the need for heat in a BGA and the need for heat in CIC combined with elongation of duration lends this CIC/BGA configuration as a predictable need for touch up (can't touch up under a BGA easily). I might advise to attach the BGAs after initial solder float. It is not very economical, but then again neither is CIC.
<BR>
<BR>I have had success with CIC and Thermount. Thermount has all but killed CIC although there are moisture issues with Thermount. I say this relative to the ongoing existence of CIC. The rumor mill had it that CIC was going the way of Howefill... discontinued.
<BR>
<BR>Coretec Brad
<BR>781 858 0783 </BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 13:58:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Subject: Silicones in Printed Wiring Board Assembly
MIME-Version: 1.0
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Technetters,
The "silicone contamination" question has been raised in my plant
again. An end user has requested that we certify that we don't use ANY
silicones in our electronic assembly facility (they have paint lines).
In various locations we use silicone RTVs and the like to seal face
plates, in addition to using RTVs in the maintenance areas for gasketing.
Are these "silicones" a threat to our customer regarding carrying
contamination into their plant?
And, knowing that various silicone oils and mold releases are a
definite no-no, are there other classes of silicones that are
dangerous/safe?
Where does one find references to such?
Thanks,
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 434-978-5181
FAX: 434-978-5898
e-mail: [log in to unmask]
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========================================================================Date: Mon, 26 Nov 2001 14:14:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Parkinson - Quality System Manager <[log in to unmask]>
Subject: Re: Silicones in Printed Wiring Board Assembly
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Greg
You might also want to check the hand lotion your employees are using.
There are some out there that still have Silicone in them. Most do not,
but I'd check anyway.
Tom
"Anderson, Greg (IndSys, GEFanuc, NA)" wrote:
>
> Technetters,
> The "silicone contamination" question has been raised in my plant
> again. An end user has requested that we certify that we don't use ANY
> silicones in our electronic assembly facility (they have paint lines).
> In various locations we use silicone RTVs and the like to seal face
> plates, in addition to using RTVs in the maintenance areas for gasketing.
> Are these "silicones" a threat to our customer regarding carrying
> contamination into their plant?
> And, knowing that various silicone oils and mold releases are a
> definite no-no, are there other classes of silicones that are
> dangerous/safe?
> Where does one find references to such?
>
> Thanks,
>
> Greg Anderson
> Senior Advanced Manufacturing Engineer
> GE Fanuc Automation
> Charlottesville, VA 22911
> Phone: 434-978-5181
> FAX: 434-978-5898
> e-mail: [log in to unmask]
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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========================================================================Date: Mon, 26 Nov 2001 11:18:06 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Isolation between connector pins
In-Reply-To: <[log in to unmask]>
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Hi Daan,
That 220V sounds an awful lot like MAINS voltage. If that is the case you
probably need to worry a lot more about spacings dictated by safety
agencies, like UL in the USA or KEMA in The Netherlands, rather than
following the common V/mm guidelines.
On top of setting the rules for proper spacing between those pins they also
have rules regarding the spacing between those two pins and everything
else!!
The actual values depend on the purpose for which the board is being used.
Veel plezier,
Ahne,
A-Laser, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of d. terstegge
Sent: Monday, November 26, 2001 07:46
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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========================================================================Date: Mon, 26 Nov 2001 13:34:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Silicones in Printed Wiring Board Assembly
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
The "silicone contamination" question has been raised in my plant
again. An end user has requested that we certify that we don't use ANY
silicones in our electronic assembly facility (they have paint lines).
In various locations we use silicone RTVs and the like to seal face
plates, in addition to using RTVs in the maintenance areas for gasketing.
Are these "silicones" a threat to our customer regarding carrying
contamination into their plant?
*In a word, yes. I know that in our facility, silicones are a major
contributor to conformal coating adhesion problems, which rapidly become MY
problem. Paint would likely be similar. Coatings do not like to adhere to
silicone RTVs, or to any outgassing or exuded oils or cure byproducts, or
"re-distributed" silicones.
And, knowing that various silicone oils and mold releases are a
definite no-no, are there other classes of silicones that are
dangerous/safe?
*The two most common here are silicone RTV adhesives and silicone thermal
grease (silicone gel filled with zinc oxide particles). Our manufacturing
procedures make sure these are very closely watched items, and life in
manufacturing would be easier if we could get certain concepts through to
certain design engineers (e.g. with a baseball bat). RTVs are mildly
cleaned before coating to get the exuded alcohol cure byproducts and the
silicone thermal grease does not go on until the automated wash processes
are over. This prevents our saponifier chemicals from washing the stuff
out. We also maintain a very aggressive preventative maintenance schedule
to make sure that even if there is silicone contamination, it does not
build to problem proportions. We are currently looking at non-silicone
alternatives to both materials.
*As far as mold release agents go, PTFE agents are more common, but
represent the same threat of adhesion loss that silicone does. If you are
using circuit boards, be advised that the use of silicones sometimes occurs
in PWB manufacturing, so you may have silicone surface residues coming in
from the boards shop and not know it. While not a common occurrance, it is
something to think about.
Where does one find references to such?
*Well, you just asked the best source for technical advise (TechNet, not
me). I don't know if you will find published articles on the topic. The
best experience in manufacturing problems comes from bad experiences in
manufacturing. Because of the "L" word (liability), most manufacturers do
not publish articles admitting they EVER had a manufacturing problem. You
might look for technical bulletins on Dow Corning's web site.
Doug Pauls
Rockwell Collins
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========================================================================Date: Mon, 26 Nov 2001 12:51:02 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0
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boundary="------------98D42CC7E1B4C83717C878DB"
--------------98D42CC7E1B4C83717C878DB
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Brad,
I agree with your assessment but if management does not listen then
calculate the cost of 10 years worth of storage in dry nitrogen. If that
is not acceptable then plan be gone from the company before the contract
"clock" runs out.
David A. Douthit
Manager
LoCan LLC
Brad Saunders wrote:
> Welcome to the COTS catch 22,
> My experience is the best laid plans of "buy out and save" haven't
> worked. What I've seen is the need to "Revision" spin for parts
> acceptibility or repackage die either from the silicin to the package
> needed or have the sub harvest from one package to the one needed. It
> just doesn't seem reasonable to store piece parts for more than three
> years never mind ten plus.
>
> Brad
--------------98D42CC7E1B4C83717C878DB
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Brad,
<p>I agree with your assessment but if management does not listen then
calculate the cost of 10 years worth of storage in dry nitrogen. If that
is not acceptable then plan be gone from the company before the contract
"clock" runs out.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Brad Saunders wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Welcome
to the COTS catch 22,</font></font>
<br><font face="arial,helvetica"><font size=-1>My experience is the best
laid plans of "buy out and save" haven't worked. What I've seen is
the need to "Revision" spin for parts acceptibility or repackage die either
from the silicin to the package needed or have the sub harvest from one
package to the one needed. It just doesn't seem reasonable to store
piece parts for more than three years never mind ten plus.</font></font>
<p><font face="arial,helvetica"><font size=-1>Brad</font></font></blockquote>
</html>
--------------98D42CC7E1B4C83717C878DB--
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========================================================================Date: Mon, 26 Nov 2001 14:49:04 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Dear Gaby,
Take note that the shelf life and the seal date on the package are only
there for information purpose. This is not an expiration date since it only
represents the minimum calculated shelf life, when stored in a noncondensing
atmospheric environment of <40C/90%RH. The Humidity Indicator Card (HIC)
inside the bag should always be the proper method to find out if parts need
to be baked before processing.
Ref: J-STD-033, section 6.3.4 Shelf life and section 8.5.1 Excessive
humidity in the dry pack
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Friday, November 23, 2001 8:08 AM
To: [log in to unmask]
Subject: [TN] Storage of moisture sensitive components
How long and in what conditions may moisture sensitive components be stored
in their original package?
Thank.you,
Gaby
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========================================================================Date: Mon, 26 Nov 2001 12:11:06 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: Isolation between connector pins
In-Reply-To: <[log in to unmask]>
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For external layers, the minimum spacing for uncoated leads is 1.25mm, but
for coated leads it is .4mm. I'm sure someone here can suggest a good
permanent polymer coating. Also, if you can route a slot between the pins,
the numbers will change in your favor, but I'm not sure by how much.
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of d. terstegge
Sent: Monday, November 26, 2001 7:46 AM
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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========================================================================Date: Mon, 26 Nov 2001 14:11:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA long term storage?
MIME-Version: 1.0
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The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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========================================================================Date: Mon, 26 Nov 2001 15:49:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bissonnette, Jean-Francois" <[log in to unmask]>
Subject: Acceptability of flex boards
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Is there a document giving detailed information on acceptability of
flexible printed circuit (like IPC-A-600 but on flex only).
If not what is the document closest to it?
Thanks!
JF
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========================================================================Date: Mon, 26 Nov 2001 15:56:02 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Acceptability of flex boards
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_105.ce830ef.29340662_boundary"
--part1_105.ce830ef.29340662_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Jean-Francois!
Sure is! Go to:
http://www.ipc.org/html/IPC-6013Amendment1Published4-00.pdf
and download it, it's free!
-Steve Gregory-
> Is there a document giving detailed information on acceptability of
> flexible printed circuit (like IPC-A-600 but on flex only).
>
> If not what is the document closest to it?
>
> Thanks!
>
> JF
>
--part1_105.ce830ef.29340662_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jean-Francois!
<BR>
<BR>Sure is! Go to:
<BR>
<BR>http://www.ipc.org/html/IPC-6013Amendment1Published4-00.pdf
<BR>
<BR>and download it, it's free!
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Is there a document giving detailed information on acceptability of
<BR>flexible printed circuit (like IPC-A-600 but on flex only).
<BR>
<BR>If not what is the document closest to it?
<BR>
<BR>Thanks!
<BR>
<BR>JF
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 14:54:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Smith, Russell (US LA)" <[log in to unmask]>
Subject: Re: CuCl etch normality
MIME-Version: 1.0
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Any one out there have a good chart showing etch rate versus
acid normality in a Cupric Bath ?
Thanks
Russell Smith
[log in to unmask]
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========================================================================Date: Mon, 26 Nov 2001 16:57:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Looking for Information
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! I'm looking for contact information for Altos Engineering and
their TVP Baking process - anyone have a good email or phone number? Also -
anyone using the TVP Baking process and could share their experiences with
it?
Dave Hillman
Rockwell Collins
[log in to unmask]
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========================================================================Date: Mon, 26 Nov 2001 16:53:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Yu-Hung Shiau <[log in to unmask]>
Subject: IPC SM-782 on-line calculator
Hi,
Does anyone know how to use the on-line SM-782 calculator? There are few
fields I don't know what numbers should I plug in.
1-1. Man. Allowance- P Place Accuracy
1-2. Man. Allowance- J/T Toe Min.
2-1. Solder Joint Design Goal- J/T Toe Min
2-1. Solder Joint Design Goal- J/H Heel Min
2-1. Solder Joint Design Goal- J/S Side Min
I have lost my hard copy of my IPC SM-782 standard for a while.
By the way, which category I should go for the resistor array (resistor
network) while I use the SM-782 calculator?
Thank you all for any feedback.
YH Shiau
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========================================================================Date: Tue, 27 Nov 2001 10:29:31 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: DUTTON Phil <[log in to unmask]>
Subject: Re: Isolation between connector pins
MIME-Version: 1.0
Content-Type: text/plain
Hello Daan,
This sounds like a connection to mains supply. In which case there are
safety compliance issues that must be addressed. I've just been designing
some power supply boards with 240V AC input voltages (our mains voltage in
Australia)We have a compliance engineer in our company who makes sure that
we do the right thing with respect to safety compliance and EMC. The
Comparative Tracking Index of the board material and the environment it is
used in comes into play. This can become a complex issue. Our Australian
Standard AS3260 is closely based on IEC-950, which would be a good place to
start looking. (As an example, our spacing for 240V AC is at least 2.5mm.)
regards,
Phil.
-----Original Message-----
From: d. terstegge [mailto:[log in to unmask]]
Sent: Tuesday, 27 November 2001 02:16
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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========================================================================Date: Mon, 26 Nov 2001 18:30:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Looking for Information
MIME-Version: 1.0
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Hi Dave!
Wasn't able to find anything on Altos Engineering directly, but found what I
think is a rep firm that offers the Altos Engineering Thermal Vacuum Drying
ovens. You might want to contact them to get a contact directly at Altos. Go
to:
http://www.sicoast.com/companies.html
-Steve Gregory-
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number? Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
--part1_f6.12f24d84.29342aa5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Dave!<BR>
<BR>
Wasn't able to find anything on Altos Engineering directly, but found what I think is a rep firm that offers the Altos Engineering Thermal Vacuum Drying ovens. You might want to contact them to get a contact directly at Altos. Go to:<BR>
<BR>
http://www.sicoast.com/companies.html<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi folks! I'm looking for contact information for Altos Engineering and<BR>
their TVP Baking process - anyone have a good email or phone number? Also -<BR>
anyone using the TVP Baking process and could share their experiences with<BR>
it?<BR>
<BR>
Dave Hillman<BR>
Rockwell Collins<BR>
[log in to unmask]<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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========================================================================Date: Mon, 26 Nov 2001 15:48:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Mazzoli <[log in to unmask]>
Subject: Re: CuCl etch normality
In-Reply-To: <[log in to unmask]
rp.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hey Russ,
Here's a link that might be what you're looking for:
http://www.circuitresearch.com/cupric_chloride_options.htm
At 02:54 PM 11/26/01 -0800, you wrote:
> Any one out there have a good chart showing etch rate versus
>acid normality in a Cupric Bath ?
>
>
> Thanks
>
> Russell Smith
> [log in to unmask]
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
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========================================================================Date: Mon, 26 Nov 2001 20:31:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: CuCl etch normality
MIME-Version: 1.0
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If Mark Mazzoli's graph is not good enough....Don Ball of Atotech (formerly
Chemcut) in State College PA has a graph on data he generated with his own
hands...
Remember, that absolute etch rate is also a function of ORP, so one man's one
normal acid etch rate may not be the same as your results.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Tue, 27 Nov 2001 08:35:02 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: Looking for Information
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
http://digital.ni.com/alliance.nsf/b7d49ea02c8aa32c8625642f007e2ba6/cbaf76de
5445e3c88625652a006fbff7?OpenDocument
Here is the wb site
Gaby
----- Original Message -----
From: "David Hillman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 27, 2001 12:57 AM
Subject: [TN] Looking for Information
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number?
Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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E-mail Archives
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additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
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>
>
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========================================================================Date: Mon, 26 Nov 2001 23:44:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
In-Reply-To: <000801c1770d$a5e7da00$8655003e@gabriela>
MIME-Version: 1.0
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Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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========================================================================Date: Tue, 27 Nov 2001 06:49:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
Mime-Version: 1.0
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Peter
I agree - cooling the jigs can be a big problem for throughput. One solution I've seen was to have a rack at the unload end, the operators would put the jigs in it and a fan directed at the rack would convection cool them faster than just sitting.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/27/01 03:44AM >>>
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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========================================================================Date: Tue, 27 Nov 2001 07:02:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: BGA long term storage?
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Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use (unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm thick document describing some experiments and results with it. Very interesting machine. Do you know if anything ever come of the work to produce a commercial (non-lab) version of this? Hmm... wonder what happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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========================================================================Date: Tue, 27 Nov 2001 12:13:43 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Adrian Irwin <[log in to unmask]>
Subject: Re: Wave soldering jig thickness
MIME-Version: 1.0
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There are exit conveyors you can purchase that have fans installed. We have
recently purchased one from GWB. The size of the pallet will have an effect
on the profile so this must be checked, with regards to the dross I can not
comment as we always use pallets.
Adrian Irwin
New Products Manager
Lambda UK
Graham Collins
<Collins.Graham@LITT To: [log in to unmask]
ONLSL.COM> cc:
Sent by: TechNet Subject: Re: [TN] Wave soldeing jig thickness
<[log in to unmask]>
11/27/01 11:49 AM
Please respond to
"TechNet E-Mail
Forum."
Peter
I agree - cooling the jigs can be a big problem for throughput. One
solution I've seen was to have a rack at the unload end, the operators
would put the jigs in it and a fan directed at the rack would convection
cool them faster than just sitting.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/27/01 03:44AM >>>
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com
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========================================================================Date: Wed, 27 Nov 2002 13:37:29 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rajkumar <[log in to unmask]>
Subject: University web page
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Content-Type: multipart/alternative;
boundary="----=_NextPart_000_000F_01C2961A.217CAC50"
This is a multi-part message in MIME format.
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Dear Technet members
Can you pls check the following website
http://www.acme.salford.ac.uk/research/emerg/home.htm
Regards
Raj
Rajkumar Durairaj
Electronics Manufacturing Engineering Research Group
School of Aeronautical, Civil and Mechanical Engineering
University of Salford
http://www.acme.salford.ac.uk/emerg
Salford, UK, M5 4WT
Tel: +44-161-2954696
Fax: +44-161-2955575/5060
------=_NextPart_000_000F_01C2961A.217CAC50
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Dear Technet members</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Can you pls check the following
website</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.acme.salford.ac.uk/research/emerg/home.htm">http://www.acme.salford.ac.uk/research/emerg/home.htm</A></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Regards</FONT></DIV>
<DIV><FONT face=Arial size=2>Raj</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Rajkumar Durairaj<BR>Electronics Manufacturing
Engineering Research Group<BR>School of Aeronautical, Civil and Mechanical
Engineering<BR>University of Salford<BR><A
href="http://www.acme.salford.ac.uk/emerg">http://www.acme.salford.ac.uk/emerg</A><BR>Salford,
UK, M5 4WT<BR>Tel: +44-161-2954696<BR>Fax: +44-161-2955575/5060</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV></BODY></HTML>
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========================================================================Date: Tue, 27 Nov 2001 07:22:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Pick-and-Place Evaluation Checklist?
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I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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========================================================================Date: Tue, 27 Nov 2001 10:58:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Looking for Information
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Try:
Altos Engineering [500-9 TVP Demoisturizing System] 6009 North 61st Ave
Glendale AZ 85301 602-931-8434 fax 602-937-6396
Can't comment on their product.
Dave Fish
----- Original Message -----
From: "David Hillman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 26, 2001 2:57 PM
Subject: [TN] Looking for Information
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number?
Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>
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========================================================================Date: Tue, 27 Nov 2001 11:03:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
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Rick,
The important question is SMT or PTH?
We are using Contact Systems PTH equipment (5 systems) are very happy
with them.
One question that becomes important is, what means is used to go from
your PCB layout program to making a working machine placement program?
We ended up creating a custom Microsoft Access® module that made several
comparisons and ran several filters to output those components that were
machine inserted and a separate list of the non-machine insertable
parts.
Phil Nutting
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 10:22 AM
To: [log in to unmask]
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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in
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========================================================================Date: Tue, 27 Nov 2001 11:22:31 -0500
Reply-To: [log in to unmask]
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From: Gary Bremer <[log in to unmask]>
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Whith the removal of all the good cleaning solvents, what is
recommended for cleaning gold card edge fingers? IPA electronic
grade does not work any suggestions?
Gary Bremer
Manufacturing Engineer
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========================================================================Date: Tue, 27 Nov 2001 10:33:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
In-Reply-To: <001001c17757$4dc6aa50$3d00a8c0@rick>
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Try the IPC-9850 document.
The scope statement is attached below.
1.1 Scope
This standard establishes the procedures to characterize machine placement
capability of surface mount assembly
equipment in specification documents, as well as in documentation used to
verify a specific machine's placement
capability conformance to the specification, while maintaining a placement
accuracy to placement speed
relationship.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Thompson
Sent: Tuesday, November 27, 2001 7:22 AM
To: [log in to unmask]
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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========================================================================Date: Tue, 27 Nov 2001 12:50:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
MIME-Version: 1.0
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Circuits Assembly Magazine, www.circuitsassembly.com, has an annual
comparison guide on its website. I believe the document is in .pdf format
that can be downloaded or viewed on-line. It gives side by side comparisons
of all the machines from placement speed to feeder changeover time,
including some aspects that you may not think of.
Steve Sauer
Mfg. Engineer
Xetron Corporation
-----Original Message-----
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines.
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========================================================================Date: Tue, 27 Nov 2001 14:32:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
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There was a post on this last year. And a good response. I do not remember
all the fields.
P Place accuracy is an allowance for your pick and place equipment.
The solder joint design goals are derived from the component and the type of
solder fillet you want. Minimum Heel fillet height for example, Class 3 is
the thickness of the solder under the lead plus the thickness of the lead .
. . I wouldn't expect there to be too much solder under the lead. So, the
thickness of the lead would be an appropriate value to place there.
If this was not enough help try the archive . . . If that doesn't help. Post
back and I will try harder.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Yu-Hung Shiau
> Sent: Monday, November 26, 2001 5:53 PM
> To: [log in to unmask]
> Subject: [TN] IPC SM-782 on-line calculator
>
>
> Hi,
> Does anyone know how to use the on-line SM-782 calculator? There are few
> fields I don't know what numbers should I plug in.
>
> 1-1. Man. Allowance- P Place Accuracy
> 1-2. Man. Allowance- J/T Toe Min.
>
> 2-1. Solder Joint Design Goal- J/T Toe Min
> 2-1. Solder Joint Design Goal- J/H Heel Min
> 2-1. Solder Joint Design Goal- J/S Side Min
>
> I have lost my hard copy of my IPC SM-782 standard for a while.
>
> By the way, which category I should go for the resistor array (resistor
> network) while I use the SM-782 calculator?
>
> Thank you all for any feedback.
> YH Shiau
>
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========================================================================Date: Tue, 27 Nov 2001 15:02:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
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There are three items that are required to be filled in when using the
calculator.
The first is the allowances for fabrication (etch factor). The second is the
pick and place accuracy. If you are unsure what number to actually use, you
may select the default for that component group as shown in the online
assumptions block.
Next you will have to indicate what your desire solder joint fillet sizes
are. These are for the toe, heel and side. These values usually come from
your manufacturing assemblers. However, you may again utilize the default
values for that specific component family as shown in the assumptions table
or in similar components within the family in the calculator.
You will be required to make adjustments so that the resulting land pattern
fits comfortably on an even grid increment. Make sure you consider which
joint provides the greatest strength to the connection and make your
adjustments so as not to violate that particular minimum joint requirement.
The other two joints are not as significant and therefore may go on the
negative side in relation to the lead size.
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========================================================================Date: Tue, 27 Nov 2001 15:21:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lee Whiteman <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
X-cc: Jeff Stong <[log in to unmask]>
In-Reply-To: <001001c17757$4dc6aa50$3d00a8c0@rick>
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Rick,
You may want to check out the following website from SMT In Focus:
http://www.smtinfocus.com/processguide_placement.html.
One thing that you may also wish to consider is the health of the company
that you're buying your equipment from. In these times, it would be
unfortunate if you purchased a very sophisticated piece of hardware only to
find out that the company you purchased it from went out of business.
Good Luck
Lee Whiteman
Senior Manufacturing Engineer
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x208
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Thompson
> Sent: Tuesday, November 27, 2001 10:22 AM
> To: [log in to unmask]
> Subject: [TN] Pick-and-Place Evaluation Checklist?
>
>
> I'm in the process of looking for new equipment and was wondering if
> there are any online resources such as checklists or evaluation guides
> for features, etc. to use when comparing machines. I realize that a lot
> of it depends on individual needs but was hoping there may be some
> generic guidelines available as a good starting point. Can anyone point
> me in the right direction or perhaps be willing to share something
> you've used?
>
> Thanks in advance for any help you might be able to provide.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
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========================================================================Date: Tue, 27 Nov 2001 15:04:36 -0600
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========================================================================Date: Tue, 27 Nov 2001 22:53:05 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
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See http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html for a survey of pick&place machines.
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: Rick Thompson
To: [log in to unmask]
Sent: Tuesday, November 27, 2001 4:22 PM
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>See <A
href="http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html">http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html</A> for
a survey of pick&place machines.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Daan Terstegge</FONT></DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask]
href="mailto:[log in to unmask]">Rick Thompson</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 27, 2001 4:22
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] Pick-and-Place Evaluation
Checklist?</DIV>
<DIV><BR></DIV>I'm in the process of looking for new equipment and was
wondering if<BR>there are any online resources such as checklists or
evaluation guides<BR>for features, etc. to use when comparing machines. I
realize that a lot<BR>of it depends on individual needs but was hoping there
may be some<BR>generic guidelines available as a good starting point. Can
anyone point<BR>me in the right direction or perhaps be willing to share
something<BR>you've used?<BR><BR>Thanks in advance for any help you might be
able to provide.<BR><BR><BR>Rick Thompson<BR>Ventura Electronics
Assembly<BR>2655 Park Center Dr.<BR>Simi Valley, CA 93065<BR><BR>+1 (805)
584-9858 x-304 voice<BR>+1 (805) 584-1529 fax<BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><BR>---------------------------------------------------------------------------------<BR>Technet
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========================================================================Date: Tue, 27 Nov 2001 13:57:41 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Other than utilizing exit cooling fans, what other
cooling medium and method would be considered
practical?
Rgds,
Peter
--- Graham Collins <[log in to unmask]>
wrote:
> Peter
> I agree - cooling the jigs can be a big problem for
> throughput. One solution I've seen was to have a
> rack at the unload end, the operators would put the
> jigs in it and a fan directed at the rack would
> convection cool them faster than just sitting.
>
> regards
>
> Graham Collins
> Process Engineer,
> Northrop Grumman
> Atlantic Facility of Litton Systems Canada
> (902) 873-2000 ext 6215
>
> >>> [log in to unmask] 11/27/01 03:44AM >>>
> Hello,
>
> Has anyone experienced problems with running boards
> through wave
> soldering in a pallet with deep machined pockets?
>
> My jigs are quite thick (~0.5") in order to mask off
> the high filter
> components on the solder side. As a result the jigs
> get very hot after
> soldering and takes long time to cool down to be
> feed back to the cycle.
> It also affects my profiling, throughput, and seems
> to create more dross
> than usual.
>
> Any comment or advice?
>
> Rgds,
> Peter
>
>
>
_________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at
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>
>
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>
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========================================================================Date: Tue, 27 Nov 2001 17:12:15 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: SSOP to SOIC adaptors...
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Hey All!!
Getting ready for our first winter blast here in "Okra-homie"...supposed to
get sleet, freezing rain, and snow starting tonight and lasting through
tomorrow night. Funny thing is, it was in the 70's this past weekend????
On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build
3-boards that uses three RS-232 Transceivers per board (this is the first
build of these boards), and the problem is that these parts are 20-pin
SSOP's, but the footprint on the board is standard 20-pin SOIC's. I know
that's NEVER happened to any of you before, huh?
Tried Adapters.Com, and they don't have anything off-the-shelf...they'll make
us some, at $80 each, with a two-week turn...no good.
Aries has one that will work, the SSOP will have some toe overhang, but not
real bad. Trying to find stock somewhere...
Is there anyplace else that I might look in case we can't find stock on the
Aries part?
Thanks a bunch!!!
-Steve Gregory-
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey All!!
<BR>
<BR>Getting ready for our first winter blast here in "Okra-homie"...supposed to get sleet, freezing rain, and snow starting tonight and lasting through tomorrow night. Funny thing is, it was in the 70's this past weekend????
<BR>
<BR>On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build 3-boards that uses three RS-232 Transceivers per board (this is the first build of these boards), and the problem is that these parts are 20-pin SSOP's, but the footprint on the board is standard 20-pin SOIC's. I know that's NEVER happened to any of you before, huh?
<BR>
<BR>Tried Adapters.Com, and they don't have anything off-the-shelf...they'll make us some, at $80 each, with a two-week turn...no good.
<BR>
<BR>Aries has one that will work, the SSOP will have some toe overhang, but not real bad. Trying to find stock somewhere...
<BR>
<BR>Is there anyplace else that I might look in case we can't find stock on the Aries part?
<BR>
<BR>Thanks a bunch!!!
<BR>
<BR>-Steve Gregory-</FONT></HTML>
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========================================================================Date: Wed, 28 Nov 2001 11:14:44 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Solder Resist and QFP's
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Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this matter?
Cheers
Mike
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<DIV><FONT color=#0000ff face=Arial size=2><SPAN classV0331122-27112001>Hi
all,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classV0331122-27112001>What
are peoples thoughts on solder resist between fine pitch micro pads??? I
have recently heard two differing theories regarding this matter, one is that
solder resist between the pads on some very fine pitch QFP's will reduce the
risk of solder shorts. The other theory was that with solder resist between
these pads you could risk getting the resist onto the pads and reducing the
soldering surface??? What is the general consensus on this matter???
Which approach to others take on this matter?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001>Cheers</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001>Mike</SPAN></FONT></DIV></BODY></HTML>
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========================================================================Date: Tue, 27 Nov 2001 15:17:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: Need Help with 85-15 Altera QFPs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
> Fellow Technetters:
>
> I am sending this looking for any help, I guess I've done everything
> as far as the process and I haven't been able to resolve the issue. We've
> been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> finish on the leads. The solder doesn't flow properly and an acceptable
> solder joint is not formed, the leads can be sometimes lifted with no
> effort. The solder paste was checked after the screen printer operation
> and it looked alright, the oven profile was also verified and it's always
> within the solder paste manufacturer's recommendations. This problem seems
> to be affecting all the different products with this type of component.
> These part numbers are manufactured by Altera. Has anybody experienced
> similar problems with QFPs from this manufacturer?, Does anybody have
> recommendations as far as the reflow oven profile?. I read somewhere that
> this particular alloy has the liquidus temperature at 205 degrees, is this
> accurate?
>
Any help would be really appreciated
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> E-mail: [log in to unmask]
>
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========================================================================Date: Tue, 27 Nov 2001 15:52:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivan Barrios <[log in to unmask]>
Subject: Wave soldeing jig thickness
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One thing you can try, is that since you have to return the jigs anyway to
the beginning of the wave solder process, you might want to use a conveyor
with fans on top so that the fans will cool off the pallets as they go
through the conveyor.
Ivan
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
--=_alternative 007DEF6487256B11_Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="Courier New">One thing you can try, is that since you have to return the jigs anyway to the beginning of the wave solder process, you might want to use a conveyor with fans on top so that the fans will cool off the pallets as they go through the conveyor. </font>
<br><font size=2 face="Courier New">Ivan</font>
<br>
<br>
<br><font size=2 face="Courier New">Date: Mon, 26 Nov 2001 23:44:19 -0800<br>
From: Peter Lee <[log in to unmask]><br>
Subject: Wave soldeing jig thickness<br>
<br>
Hello,<br>
<br>
Has anyone experienced problems with running boards through wave<br>
soldering in a pallet with deep machined pockets?<br>
<br>
My jigs are quite thick (~0.5") in order to mask off the high filter<br>
components on the solder side. As a result the jigs get very hot after<br>
soldering and takes long time to cool down to be feed back to the cycle.<br>
It also affects my profiling, throughput, and seems to create more dross<br>
than usual.<br>
<br>
Any comment or advice?<br>
<br>
Rgds,<br>
Peter</font>
--=_alternative 007DEF6487256B11_=--
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========================================================================Date: Tue, 27 Nov 2001 17:09:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
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Carl,
You are indeed subscribed as [log in to unmask] for Technet.
No action is necessary.
Keach
>>> [log in to unmask] 11/27/01 15:17 PM >>>
My new e-mail address will be [log in to unmask] . Please ensure you
have changed my address in your files or there is a fellow at SCI who
will receive my e-mails.
This will take effect Friday November 30th.
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========================================================================Date: Wed, 28 Nov 2001 08:31:25 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Isolation between connector pins
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Hi, Daan,
Are all the connector pins being used? Frequently, several to many pins are
not used, in which case why not design so that pins adjacent to the 220V AC
connection are not connected to anything else. This will effectively
increase the spacing between the high voltage and other signals.
Peter Duncan
"d. terstegge"
<[log in to unmask] To: [log in to unmask]
GROUP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Isolation between connector pins
11/26/01 11:45 PM
Please respond to
"TechNet E-Mail Forum."
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5
mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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========================================================================Date: Tue, 27 Nov 2001 22:34:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: SSOP to SOIC adaptors...
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Try:
Aries 908.996.6841
Antona 310.473.8995
Oztech 510.782.2654fax2656
Emulation Technology 408.982.0660 800.232.7837 fax 0664 www.emulation.com
Interconnect Systems 708 Via Alondra Camarillo CA 93012 805.482.2870 fax 8470 www.isipkg.com
Dave Fish
----- Original Message -----
From: Stephen R. Gregory
To: [log in to unmask]
Sent: Tuesday, November 27, 2001 2:12 PM
Subject: [TN] SSOP to SOIC adaptors...
Hey All!!
Getting ready for our first winter blast here in "Okra-homie"...supposed to get sleet, freezing rain, and snow starting tonight and lasting through tomorrow night. Funny thing is, it was in the 70's this past weekend????
On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build 3-boards that uses three RS-232 Transceivers per board (this is the first build of these boards), and the problem is that these parts are 20-pin SSOP's, but the footprint on the board is standard 20-pin SOIC's. I know that's NEVER happened to any of you before, huh?
Tried Adapters.Com, and they don't have anything off-the-shelf...they'll make us some, at $80 each, with a two-week turn...no good.
Aries has one that will work, the SSOP will have some toe overhang, but not real bad. Trying to find stock somewhere...
Is there anyplace else that I might look in case we can't find stock on the Aries part?
Thanks a bunch!!!
-Steve Gregory-
------=_NextPart_000_0014_01C17793.A4FE1F60
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<META content="MSHTML 5.00.2919.6307" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Try:</FONT></DIV>
<DIV><FONT face=Arial size=2>Aries 908.996.6841<BR>Antona 310.473.8995<BR>Oztech
510.782.2654fax2656<BR>Emulation Technology 408.982.0660 800.232.7837 fax 0664
<A href="http://www.emulation.com">www.emulation.com</A><BR>Interconnect Systems
708 Via Alondra Camarillo CA 93012 805.482.2870 fax 8470 <A
href="http://www.isipkg.com">www.isipkg.com</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Dave Fish</FONT></DIV>
<BLOCKQUOTE
style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A href="mailto:[log in to unmask]" [log in to unmask]>Stephen R.
Gregory</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, November 27, 2001 2:12
PM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] SSOP to SOIC
adaptors...</DIV>
<DIV><BR></DIV><FONT face=arial,helvetica><FONT size=2>Hey All!!
<BR><BR>Getting ready for our first winter blast here in
"Okra-homie"...supposed to get sleet, freezing rain, and snow starting tonight
and lasting through tomorrow night. Funny thing is, it was in the 70's this
past weekend???? <BR><BR>On to my question; looking for a SSOP-to-SOIC
adaptor. Trying to build 3-boards that uses three RS-232 Transceivers per
board (this is the first build of these boards), and the problem is that these
parts are 20-pin SSOP's, but the footprint on the board is standard 20-pin
SOIC's. I know that's NEVER happened to any of you before, huh? <BR><BR>Tried
Adapters.Com, and they don't have anything off-the-shelf...they'll make us
some, at $80 each, with a two-week turn...no good. <BR><BR>Aries has one that
will work, the SSOP will have some toe overhang, but not real bad. Trying to
find stock somewhere... <BR><BR>Is there anyplace else that I might look in
case we can't find stock on the Aries part? <BR><BR>Thanks a bunch!!!
<BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 28 Nov 2001 12:25:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
MIME-Version: 1.0
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Yu-Hung Shiau
<yshiau@ATPUS To: [log in to unmask]
A.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] IPC SM-782 on-line calculator
<[log in to unmask]
ORG>
11/27/01
06:53 AM
Please
respond to
"TechNet
E-Mail
Forum."
Land Pattern calculation is still an artform, not a science and depends on
a number of parameters such as board material, component package (often
manufacturer-specific), assembly process to be used (Wave or CR, etc), P&P
machines being used to populate the boards and your own design rules.
I raised this issue on TechNet a few weeks ago, especially since I was
getting different answers for land pattern sizes depending on which method
I used ( component data sheets, SM-782 or calculators). IPC stated that
they are working to address these issues. However, to answer your specific
questions, see comments below, PLUS the 4 main factors to consider are the
board manufacturing tolerence, the component placement tolerence and the
tolerence of the component itself, as well as the component's actual
lead:board contact area and component dimensions.
If you have any experience of determining land patterns that work, use that
background to judge the "reasonableness" of the calculated results. For
example, the larger allowance between heel and toe has to go to the end
where max stress is going to be experienced. Usually this is the end where
the lead goes on to join the component body, if you follow.
Hi,
Does anyone know how to use the on-line SM-782 calculator? There are few
fields I don't know what numbers should I plug in.
1-1. Man. Allowance- P Place Accuracy **FIND OUT FROM YOUR ASSEMBLY PEOPLE
WHAT THE PLACEMENT ACCURACY IS OF THE PICK AND PLACE MACHINES THEY USE AND
PLUG THAT FIGURE IN.**
1-2. Man. Allowance- J/T Toe Min. ** FROM YOU FAB HOUSE, OBTAIN THE PAD
POSITIONAL TOLERENCE THEY ARE WORKING TO WHEN FABRICATING THE BOARDS AND
PLUG THAT FIGURE IN.**
2-1. Solder Joint Design Goal- J/T Toe Min **IN THE ABSENCE OF COMPONENT
DATA SHEET INFORMATION OR SPECIFIC DATA FOR THE PACKAGE FROM SM-782, MIN.
TOE ALLOWANCE CAN BE TAKEN FROM TABLE 3.4 (NEAR THE FRONT) OF SM-782. I
DON'T BELIEVE IT'S ACCURATE FOR ALL PURPOSES, BUT IT'S THE BEST AVAILABLE
IN THE ABSENCE OF ANY OTHER INFO.**
2-1. Solder Joint Design Goal- J/H Heel Min ** SAME AS FOR TOE-TAKE FROM
THE SPEC TABLE**
2-1. Solder Joint Design Goal- J/S Side Min ** SIDE ALLOWANCE DEPENDS ON
THE COMPONENT PITCH AND LAND SPACING REQUIREMENTS OF THE DESIGN. FIND A
COMPROMISE BETWEEN YOUR DESIGN RULES AND THE REQUIREMENTS OF THE COMPONENT.
OFTEN THE SIDE ALLOWANCE IS ZERO BECAUSE THERE ISN'T ROOM TO HAVE THE PAD
ANY WIDER THAN THE COMPONENT LEAD, BUT ARE ALSO NOT MUCH LARGER IN MANY
CASES THAN ABOUT 0.02MM. I THINK A SIDE ALLOWANCE IS ALSO GIVEN IN THE SPEC
TABLE **
**IN SUMMARY, YOU HAVE YOU USE YOUR OWN BEST KNOWLEDGE/JUDGEMENT TO OBTAIN
THE FINAL PATTERN. DON'T MAKE THEM TOO LONG AT EITHER END, OR TOO SHORT
EITHER, BUT DETERMINING WHAT IS TOO LONG AND WHAT IS TOO SHORT COMES DOWN
TO EXPERIENCE, TRIAL AND ERROR.**
I have lost my hard copy of my IPC SM-782 standard for a while. **I DON'T
HAVE A COPY OF THE SPEC TO HAND EITHER, OR I WOULD BE ABLE TO REPRODUCE THE
TABLE FOR YOU - IT'S NOT VERY LARGE.**
By the way, which category I should go for the resistor array (resistor
network) while I use the SM-782 calculator? **SORRY, CAN'T HELP YOU HERE**
Thank you all for any feedback.
YH Shiau
Best of luck
Peter Duncan
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========================================================================Date: Tue, 27 Nov 2001 23:49:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
In-Reply-To: <[log in to unmask]>
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How about industrial air/water chiller small enough to stack several
jigs in for a short period of time? Has anyone come across something
like that?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ivan Barrios
Sent: November 27, 2001 2:53 PM
To: [log in to unmask]
Subject: [TN] Wave soldeing jig thickness
One thing you can try, is that since you have to return the jigs anyway
to the beginning of the wave solder process, you might want to use a
conveyor with fans on top so that the fans will cool off the pallets as
they go through the conveyor.
Ivan
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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<div class=Section1>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'>How about industrial air/water chiller small enough
to stack several jigs in for a short period of time? Has anyone come across something
like that?<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=MsoNormal><span class=SpellE><font size=2 color=navy face=Arial><span
style='font-size:10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;
color:navy;mso-fareast-language:ZH-TW'>Rgds</span></font></span><font size=2
color=navy face=Arial><span style='font-size:10.0pt;font-family:Arial;
mso-fareast-font-family:PMingLiU;color:navy;mso-fareast-language:ZH-TW'>,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'>Peter<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=MsoNormal style='margin-left:.5in'><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'>-----Original Message-----<br>
<b><span style='font-weight:bold'>From:</span></b> TechNet
[mailto:[log in to unmask]] <b><span style='font-weight:bold'>On Behalf Of </span></b>Ivan
Barrios<br>
<b><span style='font-weight:bold'>Sent:</span></b> </span></font><st1:date
Month="11" Day="27" Year="2001"><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'>November 27, 2001</span></font></st1:date><font
size=2 face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour="14" Minute="53"><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma'>2:53 PM</span></font></st1:time><font size=2 face=Tahoma><span
style='font-size:10.0pt;font-family:Tahoma'><br>
<b><span style='font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style='font-weight:bold'>Subject:</span></b> [TN] Wave soldeing jig
thickness</span></font></p>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="Times New Roman"><span
style='font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=MsoNormal style='margin-left:.5in'><font size=3 face="Times New Roman"><span
style='font-size:12.0pt'><br>
</span></font><font size=2 face="Courier New"><span style='font-size:10.0pt;
font-family:"Courier New"'>One thing you can try, is that since you have to
return the jigs anyway to the beginning of the wave solder process, you might
want to use a conveyor with fans on top so that the fans will cool off the
pallets as they go through the conveyor. </span></font><br>
<font size=2 face="Courier New"><span style='font-size:10.0pt;font-family:"Courier New"'>Ivan</span></font>
<br>
<br>
<br>
<font size=2 face="Courier New"><span style='font-size:10.0pt;font-family:"Courier New"'>Date:
Mon, 26 Nov 2001 23:44:19 -0800<br>
From: Peter Lee <[log in to unmask]><br>
Subject: Wave soldeing jig thickness<br>
<br>
Hello,<br>
<br>
Has anyone experienced problems with running boards through wave<br>
soldering in a pallet with deep machined pockets?<br>
<br>
My jigs are quite thick (~0.5") in order to mask off the high filter<br>
components on the solder side. As a result the jigs get very hot after<br>
soldering and takes long time to cool down to be feed back to the cycle.<br>
It also affects my profiling, throughput, and seems to create more dross<br>
than usual.<br>
<br>
Any comment or advice?<br>
<br>
Rgds,<br>
Peter</span></font><o:p></o:p></p>
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========================================================================Date: Wed, 28 Nov 2001 12:08:29 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Hmmm, seems I'm the only one who adviced not to worry about long term storage of BGA's. I must admit that I never stored a BGA for 10 years to see how it solders, but I really don't expect the solderability to decrease to such an extend that the balls will not solder anymore.
According to Klein Wassink the oxidation layer on solder will grow approximately logarithmically with time, resulting in about 6nm after 20 years which is just twice as thick as after one year !
So my question is: are nitrogen cabinets, ROSA-technology or redesigns REALLY necesarry ?
Maybe one of the metallurgists on this forum can add a few words ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Graham Collins <[log in to unmask]> 11/27 1:02 pm >>>
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use (unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm thick document describing some experiments and results with it. Very interesting machine. Do you know if anything ever come of the work to produce a commercial (non-lab) version of this? Hmm... wonder what happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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========================================================================Date: Wed, 28 Nov 2001 08:27:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
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Mike,
I think that a good board shop should be able to avoid contaminating the pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of shorts.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 5:15 PM
To: [log in to unmask]
Subject: [TN] Solder Resist and QFP's
Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this matter?
Cheers
Mike
------_=_NextPart_001_01C17810.6CDDF560
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charset="iso-8859-1"
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<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classC5102313-28112001>Mike,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classC5102313-28112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classC5102313-28112001>I
think that a good board shop should be able to avoid contaminating the pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of
shorts.</SPAN></FONT></DIV>
<P><FONT face="Times New Roman">Thanks,</FONT> <BR><I><FONT color=#000080
face="Comic Sans MS">Robert Furrow</FONT></I> <BR><FONT face=Arial
size=2>Printed Wiring Board Engineer</FONT> <BR><FONT face=Arial
size=2>Strategic Supply Global Account Manager</FONT> <BR><FONT face=Arial
size=2>Supply Chain Networks</FONT> <BR><FONT face=Arial size=2>Lucent
Technologies</FONT> <BR><FONT face=Arial
size=2>978-960-3224 <U> </U></FONT><U><FONT color=#0000ff
face=Arial size=2>[log in to unmask]</FONT></U> </P>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Michael Bell
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 27, 2001
5:15 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Solder Resist
and QFP's<BR><BR></DIV></FONT>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classV0331122-27112001>Hi
all,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN classV0331122-27112001>What
are peoples thoughts on solder resist between fine pitch micro pads??? I
have recently heard two differing theories regarding this matter, one is that
solder resist between the pads on some very fine pitch QFP's will reduce the
risk of solder shorts. The other theory was that with solder resist between
these pads you could risk getting the resist onto the pads and reducing the
soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this
matter?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001>Cheers</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
classV0331122-27112001>Mike</SPAN></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 28 Nov 2001 08:22:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
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IMHO it doesn't really matter. You need to have different controls built in depending which method you are using.
Kathy
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<DIV>IMHO it doesn't really matter. You need to have different controls
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========================================================================Date: Wed, 28 Nov 2001 07:44:14 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ou Sokkhon-R5AALJ <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
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May be you need to look for different material for your jig so that the jig is thinner and carry less heat. Also you probably need to build more jig to allow cool off time before use it again.
Regards
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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<DIV><FONT face=Arial color=#0000ff size=2><SPAN class=194354114-28112001>May be
you need to look for different material for your jig so that the jig is thinner
and carry less heat. Also you probably need to build more jig to allow cool off
time before use it again.</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=194354114-28112001>Regards</SPAN></FONT></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Arial
color=#0000ff size=2></FONT><BR><BR><FONT face="Courier New" size=2><SPAN
style="FONT-SIZE: 10pt; FONT-FAMILY: 'Courier New'">Date: Mon, 26
Nov 2001 23:44:19 -0800<BR>From: Peter Lee
<[log in to unmask]><BR>Subject: Wave soldeing jig
thickness<BR><BR>Hello,<BR><BR>Has anyone experienced problems with running
boards through wave<BR>soldering in a pallet with deep machined
pockets?<BR><BR>My jigs are quite thick (~0.5") in order to mask off the high
filter<BR>components on the solder side. As a result the jigs get very hot
after<BR>soldering and takes long time to cool down to be feed back to the
cycle.<BR>It also affects my profiling, throughput, and seems to create more
dross<BR>than usual.<BR><BR>Any comment or
advice?<BR><BR>Rgds,<BR>Peter</SPAN></FONT><o:p></o:p></DIV></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 28 Nov 2001 10:05:16 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: BGA long term storage?
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Graham,
You should be aware of the following information relative to dry storage for
moisture-sensitive devices:
Contrary to popular belief, it is not safe to assume that all MSDs can be
stored in a dry cabinet for an extended period of time. Over time the
components will saturate to the ambient conditions inside the dry box (10%
RH is common) and this actually exceeds the critical level for many devices.
The level of risk and the time required to exceed the critical level are
directly related to the MS level and body thickness of the components and to
the RH level in the dry box.
To account for this situation, the IPC/JEDEC standard J-STD-033 is currently
being revised to include a limit of 90 days maximum of storage in a dry
cabinet. (I can send you a copy of the proposed revision if you want).
A better option for long term dry storage is to keep MSDs inside a dry bag
with desiccant and optionally to place this dry bag in a dry environment. Of
course the bags are not perfectly moisture-proof but they will offer a drier
environment than a standard dry box for a longer period of time. They are
designed to protect the components for a minimum of 12 months in a
non-condensing environment of <40C/90%RH. The drier the environment around
the bags the longer it will take before too much moisture gets inside. When
you open the bag, the Humidity Indicator Card (HIC) inside will indicate if
parts need to be baked before processing.
I am in the process of putting the finishing touch to a technical paper on
the subject of MSD dry storage that will be presented at the upcoming APEX
technical conference. I would be glad to send you a copy of this paper if
you are interested.
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
Date: Tue, 27 Nov 2001 07:02:57 -0500
From: Graham Collins <[log in to unmask]>
Subject: Re: BGA long term storage?
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use (unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm thick document describing some experiments and results with it. Very interesting machine. Do you know if anything ever come of the work to produce a commercial (non-lab) version of this? Hmm... wonder what happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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========================================================================Date: Wed, 28 Nov 2001 09:32:36 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Heinz Mader <[log in to unmask]>
Subject: Adhesion problems of galvanic gold on electroless nickel gold
Hallo outthere in the big pcb world
A qestion from switzerland
We produce a board(material G 10) After full plating electroless nickel
gold the adhesion is good.Then we laminate fotoresist film for goldmask and
develope with soda.
We let plate the bond gold externel. This Gold has not enough adhesion
with tape test We see that not later not after Galvanic plating
Has anyone some experince solving that problem
With kind regards
Heinz Mader
Ascom AG
3000 Berne
Switzerland
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========================================================================Date: Wed, 28 Nov 2001 10:57:17 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
MIME-Version: 1.0
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In a message dated 11/27/2001 2:35:13 AM US Eastern Standard Time,
[log in to unmask] writes:
<< As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual. >>
I have seen all of the effects you describe. I believe the dross increase is
due to a small amount of moisture absorption by the pallet material, but I
have never taken the steps to prove it out. The pallet will definitely make
a large difference in your profile. As for cooling, I think the idea already
suggested of a rack with fans will work best. You can also get conveyors or
buffers with built in fans, and even programmable to hold each pallet for a
set amount of time. Then you can profile the cool down time with your KIC or
whatever profiler, and get a good estimate for exactly how long to cool each
one before reusing. I don't recommend any kind of quenching or other forced
cooling with liquid.
Jon Moore
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========================================================================Date: Wed, 28 Nov 2001 11:19:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Schaefer <[log in to unmask]>
Subject: Component Area Usage - Reality Check
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We are working on the early stages of a very densely populated design, and are looking at
area estimations. Is there any specification / rule of thumb which defines the maximum
component placement area usage (percentage or ratio)?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
1000 Waverley Street
Winnipeg, MB R3T 0P3
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<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV><FONT size=1>We are working on the early stages of a very densely
populated design, and are looking at</FONT></DIV>
<DIV><FONT size=1>area estimations. </FONT><FONT size=1>Is there any
specification / rule of thumb which defines the maximum</FONT></DIV>
<DIV><FONT size=1>component placement area usage (percentage or
ratio)?</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>Thanks,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1>Dave
Schaefer
Voice: (204)478-8059<BR>Senior PCB
Designer
FAX: (204)942-3001<BR>Symbol
Technologies
Email: <A href="mailto:[log in to unmask]">[log in to unmask]</A> <BR>1000
Waverley
Street
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1></FONT> </DIV></BODY></HTML>
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========================================================================Date: Wed, 28 Nov 2001 08:58:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brooks,Bill" <[log in to unmask]>
Subject: Re: Component Area Usage - Reality Check
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Hi David ,
In my opinion, this is not easily defined as a rule of thumb. Component
placement is limited by the machine that does the placement. The land area
and clearances must take into account the processes that need to be applied
to the components. IPC-SM-782 has recommendations for placement 'corrals' or
clearances. Many designers build this clearance into their cad footprints to
make it easier to prevent manufacturing problems on the pick and place
machines, and soldering machines. The minimums are rarely desirable, but
what you can get away with based on the volumes of boards you will make and
the tolerances you have allowed for your machines will affect the yields you
get on the manufacturing floor. Your manufacturing engineers will know more
about the limitations of the machines they have access to and what they can
get away with for clearances.... Sorry there is no silver bullet for this
problem. I would suggest you use the IPC spec as the worst case estimate for
component area and address the clearance issues when you get into the
design. Overlapping spaces can be accommodated by some machines in some axis
orientations under certain conditions... for example.
Just as a side note.... Back when I was hand taping artworks, I used to
estimate board area by figuring how many discrete components would fit into
a IC foot print and then applying that to a ratio of IC units per square
inch,,, I could be sure it was a tougher board if the IC units per square
in was in excess of 1/2 a sq. in. per IC unit ...(those were based on a 16
pin DIP package) or some other unreasonable amount.... Based on previous
design densities... The newer components can be deceiving in their apparent
real estate requirements, BGA's need more room to allow access to the parts
for removal or rework, for example... tolerances for fine pitch parts make
them more difficult to place, 0402 discrete are the size of a grain of
pepper... the machines that handle, test and rework these parts will define
your clearances for you... in the end. Diligent research will pay for itself
in the long run... with better yields and less rework on the manufacturing
floor. I hope this helps a little... :-)
Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask] <mailto:[log in to unmask]>
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/ <http://www.ipc.org/SanDiego/>
http://home.fda.net/bbrooks/pca/pca.htm
<http://home.fda.net/bbrooks/pca/pca.htm>
-----Original Message-----
From: David Schaefer [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 8:19 AM
To: [log in to unmask]
Subject: [TN] Component Area Usage - Reality Check
We are working on the early stages of a very densely populated design, and
are looking at
area estimations. Is there any specification / rule of thumb which defines
the maximum
component placement area usage (percentage or ratio)?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
<mailto:[log in to unmask]>
1000 Waverley Street
Winnipeg, MB R3T 0P3
------_=_NextPart_001_01C1782D.DEEBA090
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charset="iso-8859-1"
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<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV><SPAN class`4512916-28112001><FONT size=1>Hi </FONT><FONT face=Tahoma
size=2>David , </FONT></SPAN></DIV>
<DIV><SPAN class`4512916-28112001><FONT face=Tahoma
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class`4512916-28112001><FONT size=1>In my opinion, this is not
easily defined as a rule of thumb. Component placement is limited by the machine
that does the placement. The land area and clearances must take into account the
processes that need to be applied to the components. IPC-SM-782 has
recommendations for placement 'corrals' or clearances. Many designers build this
clearance into their cad footprints to make it easier to prevent manufacturing
problems on the pick and place machines, and soldering machines. The
minimums are rarely desirable, but what you can get away with based on the
volumes of boards you will make and the tolerances you have allowed for your
machines will affect the yields you get on the manufacturing floor. Your
manufacturing engineers will know more about the limitations of the machines
they have access to and what they can get away with for clearances.... Sorry
there is no silver bullet for this problem. I would suggest you use the IPC spec
as the worst case estimate for component area and address the clearance issues
when you get into the design. Overlapping spaces can be accommodated by some
machines in some axis orientations under certain conditions... for
example.</FONT></SPAN></DIV>
<DIV><SPAN class`4512916-28112001><FONT size=1>Just as a side note.... Back
when I was hand taping artworks, I used to estimate board area by figuring how
many discrete components would fit into a IC foot print and then applying
that to a ratio of IC units per square inch,,, I could be sure it was a
tougher board if the IC units per square in was in excess of 1/2 a sq. in. per
IC unit ...(those were based on a 16 pin DIP package) or some
other unreasonable amount.... Based on previous design densities... The
newer components can be deceiving in their apparent real estate requirements,
BGA's need more room to allow access to the parts for removal or rework, for
example... tolerances for fine pitch parts make them more difficult to place,
0402 discrete are the size of a grain of pepper... the machines that handle,
test and rework these parts will define your clearances for you... in the end.
</FONT></SPAN><SPAN class`4512916-28112001><FONT size=1>Diligent research will
pay for itself in the long run... with better yields and less rework on the
manufacturing floor. I hope this helps a little... </FONT></SPAN><SPAN
class`4512916-28112001><FONT size=1>:-)</FONT></SPAN></DIV>
<DIV><SPAN class`4512916-28112001><B><FONT face=Arial
size=5></FONT></B></SPAN> </DIV>
<DIV><SPAN class`4512916-28112001><B><FONT face=Arial size=5>Bill
Brooks</FONT><FONT face=Arial color=#000000
size=5><I><BR></I></FONT><I></I></B><I></I><FONT face=Arial size=2>PCB Design
Engineer , C.I.D.<BR><U></U></FONT><U><FONT face=Arial color=#0000ff
size=2>DATRON WORLD COMMUNICATIONS, INC</FONT></U><BR><FONT face=Arial
size=2>3030 Enterprise Court<BR>Vista, CA 92083<BR>Tel: (760)597-1500 Ext 3772
Fax: (760)597-1510<BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR>IPC Designers
Council, San Diego Chapter<BR><A href="http://www.ipc.org/SanDiego/"
target=_blank>http://www.ipc.org/SanDiego/</A><BR><A
href="http://home.fda.net/bbrooks/pca/pca.htm"
target=_blank>http://home.fda.net/bbrooks/pca/pca.htm</A></FONT> </DIV></SPAN>
<DIV><SPAN class`4512916-28112001><FONT size=1></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> David Schaefer
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, November 28, 2001 8:19
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Component Area Usage
- Reality Check<BR><BR></FONT></DIV>
<DIV><FONT size=1>We are working on the early stages of a very densely
populated design, and are looking at</FONT></DIV>
<DIV><FONT size=1>area estimations. </FONT><FONT size=1>Is there any
specification / rule of thumb which defines the maximum</FONT></DIV>
<DIV><FONT size=1>component placement area usage (percentage or
ratio)?</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>Thanks,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1>Dave
Schaefer
Voice: (204)478-8059<BR>Senior PCB
Designer
FAX: (204)942-3001<BR>Symbol
Technologies
Email: <A href="mailto:[log in to unmask]">[log in to unmask]</A> <BR>1000
Waverley
Street
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1></FONT> </DIV></BLOCKQUOTE></BODY></HTML>
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========================================================================Date: Wed, 28 Nov 2001 12:04:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Vandendolder, Ron" <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Heinz
A couple of ideas;
There may be a slight resist residue from the photoresist developing step
inhibiting adhesion.
A longer, warmer rinse may alleviate this problem followed by a quick
neutralizing dip in
10% HCL. Also a preclean/acid pickle and initial plating in a gold strike
tank with a below 7 ph will also help adhesion.
A quick experiment involving a stand alone coupon, that witnesses identical
processing as the board in one case and in the other case forgoes the
secondary photo-lamination with all other
variables the same (including time between initial electroless nickel/gold
and final gold plate, bakes, rinses,G10 material etc.) should help pin point
the problem....
Regards,
Ron VandenDolder
Product Development Manager
Telaxis Communications
SouthDeerfield, Ma 01375
413-665-8551
[log in to unmask]
-----Original Message-----
From: Heinz Mader [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 10:33 AM
To: [log in to unmask]
Subject: [TN] Adhesion problems of galvanic gold on electroless nickel
gold
Hallo outthere in the big pcb world
A qestion from switzerland
We produce a board(material G 10) After full plating electroless nickel
gold the adhesion is good.Then we laminate fotoresist film for goldmask and
develope with soda.
We let plate the bond gold externel. This Gold has not enough adhesion
with tape test We see that not later not after Galvanic plating
Has anyone some experince solving that problem
With kind regards
Heinz Mader
Ascom AG
3000 Berne
Switzerland
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========================================================================Date: Wed, 28 Nov 2001 10:14:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Smith, Russell (US LA)" <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
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----Thanks to everyone for the info , I was a weak on Cupric, (I spent
my life using mostly Ammonium and Ferric, amongst other more exotic
etches)
Any way one more simple or not so simple question :
Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?
Is It a correct assumption that somewhat lower N, and higher
copper would , provide faster etch rate. It just seems to me that
operating at an extreme N will basically just cost money in the form of
excess HCL usage , not to mention the wear and tear on the equipment,
and operators.,
Again thanks for the information!
Russell Smith
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========================================================================Date: Wed, 28 Nov 2001 13:33:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Need Help with 85-15 Altera QFPs
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Have not seen the problem you describe.
You're probably forming a solder alloy with your paste and the 85 Sn/15 Pb
on your Altera leads that has a different [most likely higher] liquidus
temperature than you expect or that is defined by your paste supplier's
recommended profile.
Run a profile on the Altera leads that are not soldering. Probably should
get to 240°C
Look here for solder materials properties
http://www.technicalmaterials.com/metal_prop/soldera.html
Dave Fish
----- Original Message -----
From: "Jorge Rodriguez" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 27, 2001 2:17 PM
Subject: [TN] Need Help with 85-15 Altera QFPs
> > Fellow Technetters:
> >
> > I am sending this looking for any help, I guess I've done
everything
> > as far as the process and I haven't been able to resolve the issue.
We've
> > been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> > finish on the leads. The solder doesn't flow properly and an acceptable
> > solder joint is not formed, the leads can be sometimes lifted with no
> > effort. The solder paste was checked after the screen printer operation
> > and it looked alright, the oven profile was also verified and it's
always
> > within the solder paste manufacturer's recommendations. This problem
seems
> > to be affecting all the different products with this type of component.
> > These part numbers are manufactured by Altera. Has anybody experienced
> > similar problems with QFPs from this manufacturer?, Does anybody have
> > recommendations as far as the reflow oven profile?. I read somewhere
that
> > this particular alloy has the liquidus temperature at 205 degrees, is
this
> > accurate?
> >
> Any help would be really appreciated
>
> > Jorge Rodriguez
> > Process Engineer
> > Varian Electronics Manufacturing
> > E-mail: [log in to unmask]
> >
>
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========================================================================Date: Thu, 29 Nov 2001 07:59:57 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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========================================================================Date: Wed, 28 Nov 2001 10:54:40 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Mazzoli <[log in to unmask]>
Subject: Re: Cu CL etcher
In-Reply-To: <[log in to unmask]
rp.local>
Mime-Version: 1.0
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Hi Russ,
I used to run about 1.3-1.5N and about 165g/l Cu with an ORP of 550-580 or
so. It would seem to me that the parameters you listed would lead to a
very fast but somewhat less precise etchant. You may experience undercut
and/or poor conductor edge quality. And you're right about potential
equipment problems, particularly titanium shafts, nuts, bolts, etc. But it
would be fast......... If you're working with 1/4 ounce copper you may want
to stand back a few feet to catch the layers as they fly off.....
Check with Mr. Sedlak..... he is The Man for cupric questions.
Mark
At 10:14 AM 11/28/01 -0800, you wrote:
>----Thanks to everyone for the info , I was a weak on Cupric, (I spent
>my life using mostly Ammonium and Ferric, amongst other more exotic
>etches)
>
>Any way one more simple or not so simple question :
>
> Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?
>
> Is It a correct assumption that somewhat lower N, and higher
>copper would , provide faster etch rate. It just seems to me that
>operating at an extreme N will basically just cost money in the form of
>excess HCL usage , not to mention the wear and tear on the equipment,
>and operators.,
>
>
>Again thanks for the information!
>
>Russell Smith
>
>
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========================================================================Date: Wed, 28 Nov 2001 15:33:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward H. Uslar" <[log in to unmask]>
Subject: FW: Autocad to Solidworks
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
> Does anyone know how to import an AutoCAD *.dwg or *.dxf file into
> Solidworks?
>
Thanks,
Ed
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========================================================================Date: Wed, 28 Nov 2001 13:27:44 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Igor Bjekic <[log in to unmask]>
Subject: Re: Organic Silver PCB's
Question is what type of the flux you are using?
What is the activation temperature and what is required soaking time for the
flux that you are using?
The flux's that I am working with activates at 190 but not to exceed
210F(88-99C) and 210 not to exceed 230F (99-110C). My soaking goal is
minimum 10 seconds.
As much I am able to see from your description, it appears to me that you
are overheating assembly and burning off flux before your board hits the
wave's.
Thank you,
Igor . . .
-----Original Message-----
From: Michael Bell [SMTP:[log in to unmask]]
Sent: Wednesday, November 28, 2001 12:00 PM
To: [log in to unmask]
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H)
of some
RF Organic Silver PCB's we are currently making. Every attempt to
improve
the solderability has had no impact. The soldered PCB's show very
poor
wetting, partial joints and in some areas there is no evidence of
solder.
The PCB is curretly being pre-heated to around 160 deg. C topside
and a bath
temperature of 256 deg. C. Is there something I am over looking
with the
Organic Silver? Is there any special method/ or profile for Organic
SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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========================================================================Date: Wed, 28 Nov 2001 13:28:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Igor Bjekic <[log in to unmask]>
Subject: Re: Organic Silver PCB's
Question is what type of the flux you are using?
What is the activation temperature and what is required soaking time
for the flux that you are using?
The flux's that I am working with activates at 190 but not to exceed
210F(88-99C) and 210 not to exceed 230F (99-110C). My soaking goal is
minimum 10 seconds.
As much I am able to see from your description, it appears to me
that you are overheating assembly and burning off flux before your board
hits the wave's.
Thank you,
Igor . . .
-----Original Message-----
From: Michael Bell [SMTP:[log in to unmask]]
Sent: Wednesday, November 28, 2001 12:00 PM
To: [log in to unmask]
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the
solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every
attempt to improve
the solderability has had no impact. The soldered PCB's
show very poor
wetting, partial joints and in some areas there is no
evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C
topside and a bath
temperature of 256 deg. C. Is there something I am over
looking with the
Organic Silver? Is there any special method/ or profile for
Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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========================================================================Date: Wed, 28 Nov 2001 15:44:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Decray <[log in to unmask]>
Subject: Re: FW: Autocad to Solidworks
In-Reply-To: <B17D7B877D07D211AA1D0008C76C52DA05CF8F@COMPAQSR>
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yes Ed Give me a call
*GOD BLESS AMERICA*
William W. DeCray III
Waytec Electronics Corp
CAD/CAM & Engineering Services Manager
PHONE:(434) 237-6391 ext 115
CELL: (804) 851-6115
FAX: (434) 237-1324
E-mail:<[log in to unmask]>
Web http://www.waytec.com <http://www.waytec.com/>
FTP ftp://ftp.waytec.com <ftp://ftp.waytec.com/>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Edward H. Uslar
Sent: Wednesday, November 28, 2001 3:34 PM
To: [log in to unmask]
Subject: [TN] FW: Autocad to Solidworks
> Does anyone know how to import an AutoCAD *.dwg or *.dxf file into
> Solidworks?
>
Thanks,
Ed
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========================================================================Date: Wed, 28 Nov 2001 15:51:07 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
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Heinz:
It is almost certain that some residue is on the surface, which is causing
the non-adherent Gold.
Please review the process again....you are putting galvanic Gold (I think it
is more commonly called "immersion gold") on to electroless Nickel, long
after the electroless Nickel has been plated?
If this is the case, this pretty well explains it right there. Electroless
Nickel set up one of the more passive oxide films known, and if you do not go
directly from the Nickel plating tank to the Gold tank, you are asking for
almost exactly what you are getting.
You will have to do drastic things, consider even a brief gold/nickel
stripper, to reactivate the Nickel enough to give you adherent Gold plating.
If I am understanding this correctly, and you are applying dryfilm to the
electroless Nickel, (heat and time = very passive oxide finish on the
Nickel), you may be facing an very difficult activation process to get the
Gold to adhere.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Wed, 28 Nov 2001 15:56:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
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Thanks to Mark M for the compliment.
Generally, the lower the acid, the better the "etch ratio", or the less the
"undercut", and the slower the etch....
The higher the Copper, the faster the etch.
And, yes, Mark is right, high acid can lead to attack on Titanium.
And in the US, the cost of the HCl is a trivial part of the cost of the etch,
the oxidizer (Peroxide, or Chlorate) is the costly part, so that should
really not be the deciding factor.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Thu, 29 Nov 2001 07:47:57 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0
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How about our afvourite IMC's building up within the component -
ball/component interface for example? Will that affect long term
reliability/solderabity after a long period of storage?
Just thought I'ld throw that one into the pot.
Peter Duncan
"d. terstegge"
<[log in to unmask] To: [log in to unmask]
GROUP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] BGA long term storage?
11/28/01 07:08 PM
Please respond to
"TechNet E-Mail Forum."
Hmmm, seems I'm the only one who adviced not to worry about long term
storage of BGA's. I must admit that I never stored a BGA for 10 years to
see how it solders, but I really don't expect the solderability to decrease
to such an extend that the balls will not solder anymore.
According to Klein Wassink the oxidation layer on solder will grow
approximately logarithmically with time, resulting in about 6nm after 20
years which is just twice as thick as after one year !
So my question is: are nitrogen cabinets, ROSA-technology or redesigns
REALLY necesarry ?
Maybe one of the metallurgists on this forum can add a few words ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Graham Collins <[log in to unmask]> 11/27 1:02 pm >>>
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. It's
just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use
(unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm
thick document describing some experiments and results with it. Very
interesting machine. Do you know if anything ever come of the work to
produce a commercial (non-lab) version of this? Hmm... wonder what
happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is the
plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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========================================================================Date: Wed, 28 Nov 2001 17:50:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Mike! Please give us a description of "organic" silver. Are you talking
about one of the three immersion silver pwb finishes currently found in the
industry?
Dave Hillman
Rockwell Collins
[log in to unmask]
Michael Bell <[log in to unmask]>@ipc.org> on 11/29/2001 01:59:57 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of
some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a
bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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========================================================================Date: Wed, 28 Nov 2001 17:56:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Need Help with 85-15 Altera QFPs
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Jorge! An 85Sn/15Pb solder alloy has a melting (pasty) range of 183C -
209C. Have you checked the solderability of the QFP leads? An 85Sn/15Pb
solder alloy is going to be more prone to having oxidation problems because
of the higher Sn content. Are other components on the same assembly having
similar problems or do you get acceptable solder joints? If the other
components are ok I would investigate the QFP solderability using the
JSTD-002A specification. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Jorge Rodriguez <[log in to unmask]>@ipc.org> on 11/27/2001
04:17:09 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Need Help with 85-15 Altera QFPs
> Fellow Technetters:
>
> I am sending this looking for any help, I guess I've done
everything
> as far as the process and I haven't been able to resolve the issue. We've
> been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> finish on the leads. The solder doesn't flow properly and an acceptable
> solder joint is not formed, the leads can be sometimes lifted with no
> effort. The solder paste was checked after the screen printer operation
> and it looked alright, the oven profile was also verified and it's always
> within the solder paste manufacturer's recommendations. This problem
seems
> to be affecting all the different products with this type of component.
> These part numbers are manufactured by Altera. Has anybody experienced
> similar problems with QFPs from this manufacturer?, Does anybody have
> recommendations as far as the reflow oven profile?. I read somewhere that
> this particular alloy has the liquidus temperature at 205 degrees, is
this
> accurate?
>
Any help would be really appreciated
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> E-mail: [log in to unmask]
>
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========================================================================Date: Wed, 28 Nov 2001 18:15:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Thanks Everyone: Re: [TN] Looking for Information
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! Just a quick thanks to everyone for the Altos contact info. I was
able to obtain the information I needed in record time.
Dave Hillman
Rockwell Collins
[log in to unmask]
"Stephen R. Gregory" <[log in to unmask]>@ipc.org> on 11/26/2001 05:30:45 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Looking for Information
Hi Dave!
Wasn't able to find anything on Altos Engineering directly, but found what
I think is a rep firm that offers the Altos Engineering Thermal Vacuum
Drying ovens. You might want to contact them to get a contact directly at
Altos. Go to:
http://www.sicoast.com/companies.html
-Steve Gregory-
Hi folks! I'm looking for contact information for Altos Engineering and
their TVP Baking process - anyone have a good email or phone number? Also -
anyone using the TVP Baking process and could share their experiences with
it?
Dave Hillman
Rockwell Collins
[log in to unmask]
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========================================================================Date: Wed, 28 Nov 2001 19:56:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Ahem, Sir Dave:
How many immersion Silver systems did you say there were?
Ever heard of SilveR ShielD?
Do the capitolized last letters of the name give you a hint?
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Wed, 28 Nov 2001 17:47:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Flexible PC Board
MIME-Version: 1.0
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Howdy All,
I am new to this list and I thank the folks at 3M's
Microflex division for pointing me here. Y'all can blame
them later after reading this lengthily post...
The acceptance of my lousy prototype was excellent, so I was
looking at ideas for a more robust and fine-tuned design
using a flexible circuit.
I need a flexible PC board operating at 12v DC. Size is
about 1/2" x 6" or 8". The mounting is static, but the
flexible shape is required because of the variety of
mountings. Also, the outdoor environment will be greasy,
dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
needs to be durable. There will be no direct abrasives.
The board and protection should be no more than about
2/10ths thick.
Is there something like that out there? You've probably
seen that "soft-touch" switch rubber used on keypads. A
slightly firmer version of that with copper cladding (or
something to etch) would be about perfect, as long as it's
tough stuff.
Thanks in advance and I appreciate your guidance.
- Scott
(775) 849-2030
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========================================================================Date: Wed, 28 Nov 2001 19:24:21 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
Mime-Version: 1.0
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I've seen what I think is a similar problem. I'll describe it and how I
cured it and see if it will help you.
Problem: 50% of surface pads wetted on ENIG surfaces at customer location.
Research: LPI coated panels were ENIG plated. Found peeling LPI and panels
were stripped in an alkaline solution and then LPI reapplied. Suspected that
the alkaline stripping solution or the LPI developer solution (potassium
carbonate ?) had somehow remained on the immersion gold surface.
Cure: After panels are recoated with LPI they must be processed in a hot
alkaline cleaner(cleaner on our black oxide process)then rinsed well and
100% wetting was restored.
Theory: Alkaline contamination was not rinsed from either the stripper or
the developer and ruined the gold surface for solderability. On the chemical
principal that likes-dissolve-likes the hot alkaline cleaner removed this
contaminant and with proper rinsing no residueS remained.
I hope this is helpful.
Russ Burdick
>From: Heinz Mader <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] Adhesion problems of galvanic gold on electroless nickel gold
>Date: Wed, 28 Nov 2001 09:32:36 -0600
>
>Hallo outthere in the big pcb world
>A qestion from switzerland
>We produce a board(material G 10) After full plating electroless nickel
>gold the adhesion is good.Then we laminate fotoresist film for goldmask and
>develope with soda.
>We let plate the bond gold externel. This Gold has not enough adhesion
>with tape test We see that not later not after Galvanic plating
>
>Has anyone some experince solving that problem
>
>
>With kind regards
>
>Heinz Mader
>Ascom AG
>3000 Berne
>Switzerland
>
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========================================================================Date: Thu, 29 Nov 2001 07:53:57 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have always seen fairly good wetting of immersion silver PCBs and whilst
they may not be as good as HASL this is usually only evident on the lack of
wetting to the outer edges of lands on the topside of PTH boards and less
fill on larger hole sizes. I have certainly never seen anything like you
are describing.
My first question would be what flux are you using? 160degC topside
temperature after preheat sounds very hot (regardless of finish) and it may
be that a problem with your profile is more evident on the immersion silver
boards.
Regards,
Neil Atkinson
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: 28 November 2001 19:00
Subject: Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
_____________________________________________________________________
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========================================================================Date: Thu, 29 Nov 2001 03:16:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Heinz Mader <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
X-To: "<Rudy Sedlak>" <[log in to unmask]>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
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Rudy
I must say ,that we make full ENIG (electroless Nickel-with immersion
gold).Then after laminating and developing dry-film-resist there comes the
galvanic (electrolycal gold) from about 3 µm Au)
Heinz Mader
Ascom AG
300 Berne
Switzerland
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========================================================================Date: Thu, 29 Nov 2001 10:42:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Re: Fiducial Markings - do they mean anything?
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
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Peter,
Use the type that your equipments' vision system prefers. Just for info we
use diamonds (well, 1mm squares turned at 45 deg. actually). Something else
to bear in mind is surface finish and contrast with the surrounding
background. If using HASL make sure your PCB supplier can give a relatively
flat finish. If excessively applied you end up with a 'domed' effect and the
vision system may have difficulty with that as the greyscale values will
vary as the illumination is reflected all over the place (I've had no end of
trouble with this!). Also leave a nice big clearance in your resist if you
can. In the end, give your equipment as much chance as possible to recognise
the marks, whatever the preferred shape.
From what you say you are somewhat hamstrung by what your customer has
designed in. Try to exert some influence on their designers if you can. It
works wonders in the longer run.
Best regards,
===== Original Message from [log in to unmask] at 28/11/01 11:23
>Hot on the heels of the smelly paste saga (some of the new ones that you
>turned up are great - we haven't come off the ceiling yet).
>
>Fiducials - just a quick survey (and Bob you may already have posted
>something similar so apologies if the answer is staring me in the face). We
>don't use them - yet - as most stuff here is hand placed but as we venture
>into the twilight zone of automated production I am starting to take an
>interest in them. Up to now they were just pretty little signs that we
>thought were ancient runic inscriptions from the days of the early Viking
>coastal raids - Ericsson the Mobile and Nokia the Trendy being just two
>names that have come forward.
>
>Question is - what is the most popular - I would have said that crosses were
>the most common but I looked back over several boards from different places
>and found circles and the occasional butterfly were more common than I
>thought.
>
>As the machine we have in mind (yes its an old one) doesn't like crosses we
>would prefer circles but we mostly have to smile sweetly and say thank you
>for whatever we get. So what does everyone else use? And given the chance,
>would you use a different shape?
>
>regards
>
>Peter Allgood
>
>Allgood Technology Ltd, 1 Horton Court, Hortonwood 50, Telford, TF1 7GY
>Tel and Fax 01952 677145 Web: www.allgoodsmt.com
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========================================================================Date: Thu, 29 Nov 2001 11:10:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Apologies
Mime-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
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Please ignore message sent re: Fiducials. I inadvertently sent this to the
wrong discussion forum.
Apologies for any inconvenience caused.
Regards,
PEter Barton
Peter Barton
Senior Process Engineer
ACW Technology Limited
Tel: 01443 425275
Fax: 01443 436882
E-mail [log in to unmask]
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========================================================================Date: Thu, 29 Nov 2001 11:35:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: (none)
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Mike,
I have used immersion silver (Alpha Level) at times in the past using the
same temperature profile as for HASL finished boards and had good wetting at
both bottom and topside. Are you subjecting this assembly to any surface
mount processes before wave soldering? Multiple processing of this type of
finish can progressively degrade the solderability at each stage but you'd
have to be pretty aggressive.
What is the state of the unpopulated PCB's? Is the finish bright or dull
with black or dark areas on the solderable surfaces? What is the finish
called?
Also,like other responses on this forum your preheat temperature seems
excessively high, even if you were using a water based VOC free flux you'd
only need a max. of around 110-115 deg. C topside. What flux are you using?
Regards
Peter Barton
ACW Technology Limited
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
28/11/01 18:59
>Hi there Technetters,
>
>I have now exhausted my efforts of improving the solderability (T/H) of some
>RF Organic Silver PCB's we are currently making. Every attempt to improve
>the solderability has had no impact. The soldered PCB's show very poor
>wetting, partial joints and in some areas there is no evidence of solder.
>The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
>temperature of 256 deg. C. Is there something I am over looking with the
>Organic Silver? Is there any special method/ or profile for Organic SIlver
>finished PCB's??? Any feedback would be appreciated.
>
>Cheers
>
>Mike
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========================================================================Date: Thu, 29 Nov 2001 08:43:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Russell,
I've run a VCM etcher at upwards of 2 N (our target had always been 1 N) but
we had to - long lead-time on a replacement metering pump and a shorter
delivery date. The operators asked, "How come we can do it at 2 N all of a
sudden?" My quick answer was "You've got to pick some number to run it at
and this one minimized process variation" but I'm glad to learn a better
answer. I'm always learning something new from the list.
Thanks guys!
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Smith, Russell (US LA) [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 1:15 PM
To: [log in to unmask]
Subject: Re: [TN] Cu CL etcher
----Thanks to everyone for the info , I was a weak on Cupric, (I spent
my life using mostly Ammonium and Ferric, amongst other more exotic
etches)
Any way one more simple or not so simple question :
Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?
Is It a correct assumption that somewhat lower N, and higher
copper would , provide faster etch rate. It just seems to me that
operating at an extreme N will basically just cost money in the form of
excess HCL usage , not to mention the wear and tear on the equipment,
and operators.,
Again thanks for the information!
Russell Smith
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========================================================================Date: Thu, 29 Nov 2001 07:08:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Wave Solder Profiling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good morning Technetters.
Is there anyone that could provide some good advise on Wave solder
profiling. I am not sure
of what kind of parameters to try to maintain. I really would be interested
in any documentation
that would break down min/max preheat temps vs. times etc. Dwell times on
the pot and so
forth.
all help will be greatly appreciated.
Thank you in advance.
Barry Gallegos
Process Engineer
Western Electronics
1550 South Tech Lane
Meridian, Idaho 83642
Phone: 208/955-9771
Fax: 208/955-9755
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========================================================================Date: Thu, 29 Nov 2001 08:32:03 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Rudy! Sorry, I was just thinking about the three immersion silver
finishes I have worked with - you are correct, there are several other
immersion silver finishes available on the market. My big confusion was the
term "organic" silver - is there two types of immersion silver finishes:
organic versus metallic? Or is the use of the term "organic" describing
some of the codeposited constituents of an immersion silver finish?
Dave Hillman
Rockwell Collins
[log in to unmask]
"<Rudy Sedlak>" <[log in to unmask]>@ipc.org> on 11/28/2001 06:56:39 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Organic Silver PCB's
Ahem, Sir Dave:
How many immersion Silver systems did you say there were?
Ever heard of SilveR ShielD?
Do the capitolized last letters of the name give you a hint?
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Thu, 29 Nov 2001 08:32:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Barry Gallegos <[log in to unmask]>
Barry,
You, me, and everyone else knows I've no business contributing to this
discussion and your question. Well, just so happens, I have little else to
do at this moment. Also, I love wave soldering because it is so, how shall I
say it, mechanical and straightforward. My problems is a lack of any type
understanding about IMC stuff. No matter1
You know the mechanisms as flux type and quality/composition, activation
temperature, preheater temperature required to ensure the top side board
temperature is properly reached as an indication of flux activation as
specified, conveyor speed relateive to the foregoing and its relationship to
dwell time on the solder pot, board parallelism on the wave, angle on the
wave, and all the rest.
I like wave soldering because all the above must be interoperable and
correlate with each function, mechanism, time, and chemistry in the whole
process. I call each function, again as above, sub-processes because that's
what they are. Each sub-process must be managed independently and
associatively for the "whole" process to work. If it works, solder joints
meet specified requirements. If it, or any one of the "independent"
sub-processes, don't work, solder joints suck.
To your original question, I make a matrix including all the above
parameters and include the board thermal mass (single, double, MLB, etc.)
and go out and measure each function in each sub-process in the process and
see what happens.
Most new/automatic machines as Electras and the like have computerized
matrices included. However, I always "calibrate" the automated sub-processes
and ensure they meet specified requirements.
Anyway, the process is cool though being pushed to the limits with very high
layer count MLB's with incredibly high thermal masses. Simpler 12 layer
boards used to run at predetermined speed between 3-6 feet/minute and you
could set your watch by it. Now, with some of the 40 and 50 plus layer
boards I, and some of you, have been working, speeds are much slower and
flux often is very active. You can imaging the preheat temps with some of
these things and no IPC through hole acceptance criteria comes close to reality.
And on it goes. Life and the wave soldering process is a continuing
experiment with CPI as its goal - though not often enough realized.
MoonMan
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========================================================================Date: Thu, 29 Nov 2001 10:00:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tech <[log in to unmask]>
Subject: Dielectric constant vs degree of cure , FR4
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Does the dielectric constant ( and resultant impedance results) of FR4
vary with degree of cure of the resin system ? I.e can multi layer press
parameters influence finished board impedances ? Any info. will be
appreciated.
Paul Greene
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========================================================================Date: Thu, 29 Nov 2001 09:09:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
X-To: Paul Greene <[log in to unmask]>
DC calculations are made for core material as such. This means the DC does
not change for it in whatever MLB structure.
For prepregs, DC is calculated based on expected effects after cure in the
press - in the book - in the MLB. Variations are minor, within but a percent
or two, for the same glass styles and resin contents used in the structures.
"Good" board shops will provide pre-calculated DC numbers both for core and
prepregs used. Still, the numbers vary minimally and your overall impedance
will be little affected. However, for very high speed stuff, this can be
critical though little FR4 is used in these designs. You can then calculate
the requirements based on DC, thickness, trace widths (for differential
pairs as stripline [boradside and edge rate requirements] and microstrip
requirements).
MoonMan
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========================================================================Date: Thu, 29 Nov 2001 15:08:20 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
MIME-Version: 1.0
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From a fabricator viewpoint, there are one or two things to bear in mind.
Firstly the accuracy of print registration will at best be +/-50um (+/-
2mil) if your fab house uses automatic registration, secondly, the minimum
'web' width that will remain through subsequent processing is about 85um
(2.5 mil) AT THE BOARD SOLDERMASK INTERFACE - this is important because
most masks will be undercut during developing, and may require an artwork
width of 6mils to achieve the web. Add these two factors together, and this
means the only chance of getting a web between pads is if the gap between
pads is 10mils minimum. If your QFP is on a 20 mil pitch (actually 19.6
mil), the pad width will have to be designed at 8 mil (there is an etch
tolerance and you need to understand that the top of the pad and bottom of
the pad will be different widths - which do you specify?). Now most
designers with a 12mil gap will want to run a 4/4 track and gap in there -
now you have soldermask covering the track and the soldermask height is
over the track and therefore the soldermask MUST BE HIGHER than the pad you
wish to solder to. This will create a problem with solder pasting, so the
answer is don't run tracks between these pads if you want to have high
assembly yields.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Furrow, Robert Gordon (Bob) [SMTP:[log in to unmask]]
Sent: 28 November 2001 13:27
To: [log in to unmask]
Subject: Re: [TN] Solder Resist and QFP's
Mike,
I think that a good board shop should be able to avoid contaminating the
pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of shorts.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 5:15 PM
To: [log in to unmask]
Subject: [TN] Solder Resist and QFP's
Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on
this
matter??? Which approach to others take on this matter?
Cheers
Mike
<< File: ATT00000.htm >>
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========================================================================Date: Thu, 29 Nov 2001 09:29:00 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen S. Schiera" <[log in to unmask]>
Subject: Color additives for conformal coat
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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========================================================================Date: Thu, 29 Nov 2001 07:58:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Flexible PC Board
MIME-Version: 1.0
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Scott,
2/10s of a mil? Like .0002"? You need a dielectric to hold the conductor and I don't think
you will find anything that thin. We work with thinner materials than most and we make a
number or parts on .0005" polyimide with 3 microns of copper. If anyone has anything less
than that I would like to talk to them.
Chuck Brummer
Acuson (818)734-4930
"Scott R. Madans" wrote:
> Howdy All,
>
> I am new to this list and I thank the folks at 3M's
> Microflex division for pointing me here. Y'all can blame
> them later after reading this lengthily post...
>
> The acceptance of my lousy prototype was excellent, so I was
> looking at ideas for a more robust and fine-tuned design
> using a flexible circuit.
>
> I need a flexible PC board operating at 12v DC. Size is
> about 1/2" x 6" or 8". The mounting is static, but the
> flexible shape is required because of the variety of
> mountings. Also, the outdoor environment will be greasy,
> dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
> needs to be durable. There will be no direct abrasives.
> The board and protection should be no more than about
> 2/10ths thick.
>
> Is there something like that out there? You've probably
> seen that "soft-touch" switch rubber used on keypads. A
> slightly firmer version of that with copper cladding (or
> something to etch) would be about perfect, as long as it's
> tough stuff.
>
> Thanks in advance and I appreciate your guidance.
>
> - Scott
> (775) 849-2030
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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========================================================================Date: Thu, 29 Nov 2001 08:08:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Sorry, the world of mils and microns is new to me. It is
0.2 inches!
- Scott
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
Brummer
Sent: Thursday, November 29, 2001 07:58 AM
To: [log in to unmask]
Subject: Re: [TN] Flexible PC Board
Scott,
2/10s of a mil? Like .0002"? You need a dielectric to hold
the conductor and I don't think
you will find anything that thin. We work with thinner
materials than most and we make a
number or parts on .0005" polyimide with 3 microns of
copper. If anyone has anything less
than that I would like to talk to them.
Chuck Brummer
Acuson (818)734-4930
"Scott R. Madans" wrote:
> Howdy All,
>
> I am new to this list and I thank the folks at 3M's
> Microflex division for pointing me here. Y'all can blame
> them later after reading this lengthily post...
>
> The acceptance of my lousy prototype was excellent, so I
was
> looking at ideas for a more robust and fine-tuned design
> using a flexible circuit.
>
> I need a flexible PC board operating at 12v DC. Size is
> about 1/2" x 6" or 8". The mounting is static, but the
> flexible shape is required because of the variety of
> mountings. Also, the outdoor environment will be greasy,
> dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
it
> needs to be durable. There will be no direct abrasives.
> The board and protection should be no more than about
> 2/10ths thick.
>
> Is there something like that out there? You've probably
> seen that "soft-touch" switch rubber used on keypads. A
> slightly firmer version of that with copper cladding (or
> something to etch) would be about perfect, as long as it's
> tough stuff.
>
> Thanks in advance and I appreciate your guidance.
>
> - Scott
> (775) 849-2030
>
> ----------------------------------------------------------
-----------------------
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LISTSERV 1.8d
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> Please visit IPC web site
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> information, or contact Keach Sasamori at [log in to unmask]
or 847-509-9700 ext.5315
> ----------------------------------------------------------
-----------------------
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========================================================================Date: Thu, 29 Nov 2001 08:25:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Flexible PC Board
MIME-Version: 1.0
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Scott,
0.2 inches is not going to be very flexible. There are other options like rigid flex,
circuits that are polyimide glass at the ends but have a flex conection. Can you tell us more
about your needs. How many layers, what weight of copper, conductor requirements
(line/space)? Maybe someone has some other ideas for you.
Chuck Brummer
"Scott R. Madans" wrote:
> Sorry, the world of mils and microns is new to me. It is
> 0.2 inches!
>
> - Scott
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
> Brummer
> Sent: Thursday, November 29, 2001 07:58 AM
> To: [log in to unmask]
> Subject: Re: [TN] Flexible PC Board
>
> Scott,
>
> 2/10s of a mil? Like .0002"? You need a dielectric to hold
> the conductor and I don't think
> you will find anything that thin. We work with thinner
> materials than most and we make a
> number or parts on .0005" polyimide with 3 microns of
> copper. If anyone has anything less
> than that I would like to talk to them.
>
> Chuck Brummer
> Acuson (818)734-4930
>
> "Scott R. Madans" wrote:
>
> > Howdy All,
> >
> > I am new to this list and I thank the folks at 3M's
> > Microflex division for pointing me here. Y'all can blame
> > them later after reading this lengthily post...
> >
> > The acceptance of my lousy prototype was excellent, so I
> was
> > looking at ideas for a more robust and fine-tuned design
> > using a flexible circuit.
> >
> > I need a flexible PC board operating at 12v DC. Size is
> > about 1/2" x 6" or 8". The mounting is static, but the
> > flexible shape is required because of the variety of
> > mountings. Also, the outdoor environment will be greasy,
> > dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
> it
> > needs to be durable. There will be no direct abrasives.
> > The board and protection should be no more than about
> > 2/10ths thick.
> >
> > Is there something like that out there? You've probably
> > seen that "soft-touch" switch rubber used on keypads. A
> > slightly firmer version of that with copper cladding (or
> > something to etch) would be about perfect, as long as it's
> > tough stuff.
> >
> > Thanks in advance and I appreciate your guidance.
> >
> > - Scott
> > (775) 849-2030
> >
> > ----------------------------------------------------------
> -----------------------
> > Technet Mail List provided as a free service by IPC using
> LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with
> following text in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> message: SET Technet NOMAIL
> > Search previous postings at: www.ipc.org > On-Line
> Resources & Databases > E-mail Archives
> > Please visit IPC web site
> (http://www.ipc.org/html/forum.htm) for additional
> > information, or contact Keach Sasamori at [log in to unmask]
> or 847-509-9700 ext.5315
> > ----------------------------------------------------------
> -----------------------
>
> ------------------------------------------------------------
> ---------------------
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> ------------------------------------------------------------
> ---------------------
>
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========================================================================Date: Thu, 29 Nov 2001 11:39:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
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Content-Transfer-Encoding: 7bit
FR4 will not change Er due to cure temp at fabrication, however the press
cycle may. Total dielectric constant (Er) is a function of the main
ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the
Eglass content the higher resultant Er. Hence, any "above normal" squeeze
out of resin will have the propensity to increase resultant Er for B-stage,
C-stage is a little different. I say "propensity" for the Er is estimating
averages and empiric data that over time develops a heritage of dependable
predictability. Sameness is good.
Copper thickness may be a culprit if impedance are varying. >.0007 and edges
can start getting ragged. I introduce this relative to fixed cycles of press
times and the amount of field support for dielectric materials. Copper
etching may be more subjective and susceptible to OE (Operator Error). Given
that the fabrication is repeatable, which it is, deliverable impedance can go
significantly below the standard +/-10%, otherwise we couldn't deliver 25 ohm
boards.
Brad
--part1_15d.4df7eba.2937bed4_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>FR4 will not change Er due to cure temp at fabrication, however the press cycle may. Total dielectric constant (Er) is a function of the main ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the Eglass content the higher resultant Er. Hence, any "above normal" squeeze out of resin will have the propensity to increase resultant Er for B-stage, C-stage is a little different. I say "propensity" for the Er is estimating averages and empiric data that over time develops a heritage of dependable predictability. Sameness is good.
<BR>
<BR>Copper thickness may be a culprit if impedance are varying. >.0007 and edges can start getting ragged. I introduce this relative to fixed cycles of press times and the amount of field support for dielectric materials. Copper etching may be more subjective and susceptible to OE (Operator Error). Given that the fabrication is repeatable, which it is, deliverable impedance can go significantly below the standard +/-10%, otherwise we couldn't deliver 25 ohm boards.
<BR>
<BR>Brad</FONT></HTML>
--part1_15d.4df7eba.2937bed4_boundary--
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========================================================================Date: Thu, 29 Nov 2001 08:50:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
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Chuck,
0.2 inches is the max I can work with. Anything less would
be fine, as long as it can handle the extremes of the
environment.
The item needed is very crude, I think, compared to what
y'all are doing. I am probably in the wrong forum for this.
If so, perhaps someone can point me in the right direction.
The finished product will be about 0.5 inches wide and 6.0
to 8.0 inches long (by any thickness up to 0.2").
Edge-mounted will be a dozen, to two dozen, LEDs.
Flexibility, long-term weather resistance, and 12vDC are
just about my only specs. It would be a huge plus if it
would retain the curve when bent.
Unfortunately, I don't have enough background in EE to be
much more specific. From the posts I have received since
subscribing yesterday, this group is clearly THE PLACE for
the coolest electronics manufacturing technology. I didn't
know what Polyimide was until yesterday!
Thanks for the help,
Scott
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
Brummer
Sent: Thursday, November 29, 2001 08:25 AM
To: [log in to unmask]
Subject: Re: [TN] Flexible PC Board
Scott,
0.2 inches is not going to be very flexible. There are
other options like rigid flex,
circuits that are polyimide glass at the ends but have a
flex conection. Can you tell us more
about your needs. How many layers, what weight of copper,
conductor requirements
(line/space)? Maybe someone has some other ideas for you.
Chuck Brummer
"Scott R. Madans" wrote:
> Sorry, the world of mils and microns is new to me. It is
> 0.2 inches!
>
> - Scott
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
> Brummer
> Sent: Thursday, November 29, 2001 07:58 AM
> To: [log in to unmask]
> Subject: Re: [TN] Flexible PC Board
>
> Scott,
>
> 2/10s of a mil? Like .0002"? You need a dielectric to
hold
> the conductor and I don't think
> you will find anything that thin. We work with thinner
> materials than most and we make a
> number or parts on .0005" polyimide with 3 microns of
> copper. If anyone has anything less
> than that I would like to talk to them.
>
> Chuck Brummer
> Acuson (818)734-4930
>
> "Scott R. Madans" wrote:
>
> > Howdy All,
> >
> > I am new to this list and I thank the folks at 3M's
> > Microflex division for pointing me here. Y'all can
blame
> > them later after reading this lengthily post...
> >
> > The acceptance of my lousy prototype was excellent, so I
> was
> > looking at ideas for a more robust and fine-tuned design
> > using a flexible circuit.
> >
> > I need a flexible PC board operating at 12v DC. Size is
> > about 1/2" x 6" or 8". The mounting is static, but the
> > flexible shape is required because of the variety of
> > mountings. Also, the outdoor environment will be
greasy,
> > dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
> it
> > needs to be durable. There will be no direct abrasives.
> > The board and protection should be no more than about
> > 2/10ths thick.
> >
> > Is there something like that out there? You've probably
> > seen that "soft-touch" switch rubber used on keypads. A
> > slightly firmer version of that with copper cladding (or
> > something to etch) would be about perfect, as long as
it's
> > tough stuff.
> >
> > Thanks in advance and I appreciate your guidance.
> >
> > - Scott
> > (775) 849-2030
> >
>
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========================================================================Date: Thu, 29 Nov 2001 10:51:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: FTIR Cards
MIME-Version: 1.0
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I have a question for the chemists in the crowd. 3M used to make
disposable cards for FT-IR analysis with polyethylene or PTFE meshes to
hold liquid samples. VWR tells me that 3M no longer makes such a product
and I can't seem to find them anywhere else. A company called Spectra-tech
makes something similar, but much more expensive. Does anyone know if
there are other manufacturers of these products? I could go to a
demountable liquid cell, but there would be lots of time rinsing cells
between analyses and I have a bunch to go through. Any help would be
appreciated.
Doug Pauls
Rockwell Collins
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========================================================================Date: Thu, 29 Nov 2001 16:53:51 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
MIME-Version: 1.0
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perhaps someone from the laminate industry can explain why if you draw a
straight line graph between all e glass @ 6.28 and all resin @3.6 , the
resulting line is parallel to but not overlaying the Dk graph for your
material.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Brad Saunders [SMTP:[log in to unmask]]
Sent: 29 November 2001 16:40
To: [log in to unmask]
Subject: Re: [TN] Dielectric constant vs degree of cure , FR4
FR4 will not change Er due to cure temp at fabrication, however the press
cycle may. Total dielectric constant (Er) is a function of the main
ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the
Eglass content the higher resultant Er. Hence, any "above normal" squeeze
out of resin will have the propensity to increase resultant Er for B-stage,
C-stage is a little different. I say "propensity" for the Er is estimating
averages and empiric data that over time develops a heritage of dependable
predictability. Sameness is good.
Copper thickness may be a culprit if impedance are varying. >.0007 and
edges
can start getting ragged. I introduce this relative to fixed cycles of
press
times and the amount of field support for dielectric materials. Copper
etching may be more subjective and susceptible to OE (Operator Error).
Given
that the fabrication is repeatable, which it is, deliverable impedance can
go
significantly below the standard +/-10%, otherwise we couldn't deliver 25
ohm
boards.
Brad
<< File: ATT00002.htm >>
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========================================================================Date: Thu, 29 Nov 2001 09:10:26 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: FTIR Cards
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Doug,
Even though the Spectra-tech cards are more expensive, I would go with
those. Actually, I think other card makers also raised their prices...of
the few makers that are out there. The spectra-tech ones come closest to
the 3M cards.
There are also cards that have a metallic wire mesh...but they don't work
too well.
Hans Shin
Pacific Testing Laboratories
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Thursday, November 29, 2001 8:51 AM
To: [log in to unmask]
Subject: [TN] FTIR Cards
I have a question for the chemists in the crowd. 3M used to make
disposable cards for FT-IR analysis with polyethylene or PTFE meshes to
hold liquid samples. VWR tells me that 3M no longer makes such a product
and I can't seem to find them anywhere else. A company called Spectra-tech
makes something similar, but much more expensive. Does anyone know if
there are other manufacturers of these products? I could go to a
demountable liquid cell, but there would be lots of time rinsing cells
between analyses and I have a bunch to go through. Any help would be
appreciated.
Doug Pauls
Rockwell Collins
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========================================================================Date: Thu, 29 Nov 2001 11:37:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
X-To: Brad Saunders <[log in to unmask]>
This serious discussion could be fun.
Considering today's single ply designs and requirements for constructions
as, say, 4 mil dielectrics using, say, 2113 glass, there's not a lot of
"squeeze out" happening. The resin to glass ratio is moderate or about ideal
and when a specified press cycle is used, variations are minimal. Few folks
are going to high pressure, not that it matters, or are changing recommended
press cycles so few negative, or out of tolerance, changes should be
observed concerning impedance.
As you said, the press cycle is pretty much pre-determined for time, temp,
and pressure. Therefore, as little consequence is observable, there should
be very little change in the dielectric constant or the final impedance effects.
Foil thickness and, more importantly, edge raggedness, as a result of
operator process management ineffectiveness certainly is a major contributor
to wider changes in the final outcome. With all this, I don't believe the
press cycle to be a major factor unless it is greatly mis-managed. Getting
to 25 ohms impedance, depending on design requirements, is a trick unto itself.
MoonMan
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========================================================================Date: Thu, 29 Nov 2001 11:55:52 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Rusty
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_81DCB6A5.B9D8B5E6"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_81DCB6A5.B9D8B5E6
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I was asked a question today and I can't seem to find the answer. I think I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
--=_81DCB6A5.B9D8B5E6
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I was asked a question today and I can't seem to find the answer. I
think I know but I need more then a gut feel.</DIV>
<DIV> </DIV>
<DIV>Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance. </DIV>
<DIV> </DIV>
<DIV>Kat</DIV></BODY></HTML>
--=_81DCB6A5.B9D8B5E6--
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========================================================================Date: Thu, 29 Nov 2001 18:20:19 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
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Phone: +44 (0)1276 691100
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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========================================================================Date: Thu, 29 Nov 2001 10:40:35 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Rusty
In-Reply-To: <[log in to unmask]>
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Cannot resist: For those in the rust business, rust is a product. For most
of us it is just a nuisance to be prevented.
But from somebody in the rust (iron oxide) business
(http://www.sh.com/ie/yht.htm) I found this:
Iron Oxide Yellow 313C
Specification: Matter volatile at 105 degrees centigrade (m/m)<%: 0.8 Water
soluble matter% : 0.15 Sieve residue on 0.045mm (m/m) < %:0.3 PH of water
suspension: 5.2 Fe2O3 (m/m) > %:87.1 conductivity us/cm: 175
And then a little more to confuse the issue:
Introduction
Electrochemical studies of Fe oxides have been surely initiated in corrosion
science. Formation of Fe oxides and their further reactions were
characterized in aim to learn more about corrosion resistance of steel. The
first reports were almost exclusively focused on magnetite, Fe3O4, because
it is sufficiently conductive to permit the direct study with a bulk
electrode, i.e. a piece of magnetite attached to the potentiostat, and it
yields several electrochemical reactions. Magnetite is the best starting
point to learn more about electrochemistry of Fe oxides. Lately it was found
that Fe3O4 and different polymorphs of Fe2O3 and FeOOH behave differently
(Keiser et al.).
Related to this topic is the reductive dissolution of Fe(III) oxides, whose
impact significantly exceeds the scope of pure electrochemistry (for a
review of metal oxide dissolution see Blesa et al. 1994). Reductive
dissolution is important in energy production (cleaning steel surfaces
corroded by hot water), environmental analysis (speciation of metals in
sediments and wastes) and also in the cycle of Fe oxides in natural
environment (mineral weathering, soil chemistry).
Another phenomenon studied is electrolysis of water on Fe-oxide electrodes,
which accidentally lead to discovery of oxygen insertion into Co and also Fe
oxides.
The electrochemical properties of Fe oxides are mainly controlled by two
factors: the phase composition and substitution of Fe by other metals. The
most important phases are Fe3O4 (magnetite), Fe2O3 (hematite and maghemite),
FeOOH (goethite, lepidocrocite, and few others), spinels such as MeFe2O4,
and perovskites such as SrFeO3. The commonest metals substituting Fe are Al
and Cr. The sensitivity of electrochemical properties to the oxide structure
has been proposed several times for electroanalysis, but since now other
techniques, in particular X-ray diffraction and Mössbauer spectroscopy, have
won. However, reductive dissolution of Fe(III) oxides by chemical agents is
a generally accepted analytical tool in soil and environemntal chemistry.
Good luck with the micro Siemens.
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kathy Kuhlow
Sent: Thursday, November 29, 2001 09:56
To: [log in to unmask]
Subject: [TN] Rusty
<< File: TEXT.htm >> I was asked a question today and I can't seem to find
the answer. I think I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
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========================================================================Date: Thu, 29 Nov 2001 10:52:07 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: FTIR Cards
MIME-Version: 1.0
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hi,
two responses from chris murphy in our chemistry lab.
phil
---------------------
Hi Phil,
I haven't heard of these disposable mesh cards. Our typical sources for infrared accessories are Thermo Nicolet, Thermo Spectra-Tech, Perkin Elmer, Harrick Scientific or Janos Technology.
<http://www.photonics.com/>
<http://www.thermonicolet.com>
http://www.thermospectra-tech.com
<http://www.harricksci.com>
http://www.perkinelmer.com
Chris Murphy
TRW Chemistry Technology Department
310-813-9355
Phil,
Could this be what he is looking for?
http://www.janostech.com/products/screencell.html
Rockwell Collins
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========================================================================Date: Thu, 29 Nov 2001 13:57:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Rusty
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boundary="part1_f6.13221ee2.2937df00_boundary"
--part1_f6.13221ee2.2937df00_boundary
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Content-Transfer-Encoding: quoted-printable
Content-Language: en
Hi Kat!
Rust is not conductive...I tried to find something on the web that states
that precisely, and found this, not exactly scientific, but sounds to me like
a voice of experience...
-Steve Gregory-
Using O Gauge Outdoors: Some Do’s and Don’ts
by <A HREF="http://www.trainweb.org/ttos-pnw/former_officers.htm">Doug Gray</A>
Perhaps you have toyed with the outdoor railroad ideas, but dismissed them
having heard somewhere that only G Scale can be used outdoors. And, since
many of us have collections of O Gauge trains, the added expense of starting
a new G Gauge collection deters you from outdoor railroading. The solution?
Use your O gauge outdoors! A great advantage is that you can finally have the
long right of ways that you have no room for indoors. Based upon my decade of
experience, it does work, but there are some precautions to observe.First,
let us start with the track system. Gargraves, and other manufacturers, make
track designed for outdoors, utilizing stainless steel rails and UV treated
plastic ties. Ordinary sectional indoor track will last about a week before
rust takes over. It will first appear on the rail surfaces, and soon the pins
will rust and there will be no electrical conductivity.
> I was asked a question today and I can't seem to find the answer. I think I
> know but I need more then a gut feel.
>
> Is rust conductive, just a by product, or both? The materials we were
> discussing are phosphorus, bronze, iron. Thanks in advance.
>
> Kat
>
--part1_f6.13221ee2.2937df00_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Hi Kat!
<BR>
<BR>Rust is not conductive...I tried to find something on the web that states that precisely, and found this, not exactly scientific, but sounds to me like a voice of experience...
<BR>
<BR>-Steve Gregory-
<BR>
<BR></FONT><FONT COLOR="#ff0000" SIZE=4 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B>Using O Gauge Outdoors: Some Do’s and Don’ts
<BR><P ALIGN=CENTER></FONT><FONT COLOR="#ff0000" SIZE=3 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">by <A HREF="http://www.trainweb.org/ttos-pnw/former_officers.htm">Doug Gray</A></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0">
<BR><P ALIGN=LEFT>
<BR></B>Perhaps you have toyed with the outdoor railroad ideas, but dismissed them having heard somewhere that only G Scale can be used outdoors. And, since many of us have collections of O Gauge trains, the added expense of starting a new G Gauge collection deters you from outdoor railroading. The solution? Use your O gauge outdoors! A great advantage is that you can finally have the long right of ways that you have no room for indoors. Based upon my decade of experience, it does work, but there are some precautions to observe.First, let us start with the track system. Gargraves, and other manufacturers, make track designed for outdoors, utilizing stainless steel rails and UV treated plastic ties. Ordinary sectional indoor track will last about a week before rust takes over. It will first appear on the rail surfaces, and soon the pins will rust and there will be no electrical conductivity.
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I was asked a question today and I can't seem to find the answer. I think I know but I need more then a gut feel.
<BR>
<BR>Is rust conductive, just a by product, or both? The materials we were discussing are phosphorus, bronze, iron. Thanks in advance.
<BR>
<BR>Kat
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR>
<BR>
<BR>
<BR>
<BR></P></P></FONT></HTML>
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========================================================================Date: Thu, 29 Nov 2001 12:01:02 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: FTIR Cards
In-Reply-To: <45EC695FE212D311A49D0000D11BAF7C053C6C6F@MBRC02>
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If you're looking for residues, I wouldn't recommend the ones from
Janostech. Those may be useful for analyzing solvents.
Hans Shin
Pacific Testing Laboratories
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Crepeau, Phil
Sent: Thursday, November 29, 2001 10:52 AM
To: [log in to unmask]
Subject: Re: [TN] FTIR Cards
hi,
two responses from chris murphy in our chemistry lab.
phil
---------------------
Hi Phil,
I haven't heard of these disposable mesh cards. Our typical sources for
infrared accessories are Thermo Nicolet, Thermo Spectra-Tech, Perkin Elmer,
Harrick Scientific or Janos Technology.
<http://www.photonics.com/>
<http://www.thermonicolet.com>
http://www.thermospectra-tech.com
<http://www.harricksci.com>
http://www.perkinelmer.com
Chris Murphy
TRW Chemistry Technology Department
310-813-9355
Phil,
Could this be what he is looking for?
http://www.janostech.com/products/screencell.html
Rockwell Collins
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========================================================================Date: Thu, 29 Nov 2001 18:39:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: board dunked in wave solder
TechNetters, I know there was discussion of this before, many months ago,
but I can't track down the postings in the archives. Please comment.
We have with solder on some of the top side, surrounding some components
(ICs and passives). It was dunked in wave solder. Are boards that have
"submarined" (I think someone used this term in the earlier discussion)
useable if excess solder is removed? Never useable? Sometimes?
I could say it's OK, since submarining shouldn't be as bad as HASL, but
would like some expert comments.
Lou Hart
Compunetix Quality Assurance
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========================================================================Date: Fri, 30 Nov 2001 08:18:37 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Rusty
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Hi, Kathy,
Rust is a very poor conductor, as anyone with a rusty car and wiring
trouble can testify. Corrosion on battery terminals can ruin a connection,
and where oxidisation is deliberate, such as in anodising of aluminium,
electrical conductivity is poor to non-existant, depending on the thickness
of the oxide layer.
Peter Duncan
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Rusty
<[log in to unmask]
ORG>
11/30/01
01:55 AM
Please
respond to
"TechNet
E-Mail
Forum."
I was asked a question today and I can't seem to find the answer. I think
I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
(See attached file: TEXT.htm)
[This e-mail is confidential and may also be privileged. If you are not the
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========================================================================Date: Fri, 30 Nov 2001 08:29:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: board dunked in wave solder
MIME-Version: 1.0
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Some years ago, I was faced with a few flooded boards (conventional
through-hole stuff), and the recovery operation involved removing the
excess solder by reflowing it upside down, removing the components and
putting the now-bare boards through the recently-remembered hydrosqueegee
process to re-level the solder and clear the holes. I shudder slightly at
the mere thought of all those high thermal excursions, but it did return us
useable boards.
Peter Duncan
Lou Hart
<lhart@COMPUN To: [log in to unmask]
ETIX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] board dunked in wave solder
<[log in to unmask]
ORG>
11/30/01
07:39 AM
Please
respond to
"TechNet
E-Mail
Forum."
TechNetters, I know there was discussion of this before, many months ago,
but I can't track down the postings in the archives. Please comment.
We have with solder on some of the top side, surrounding some components
(ICs and passives). It was dunked in wave solder. Are boards that have
"submarined" (I think someone used this term in the earlier discussion)
useable if excess solder is removed? Never useable? Sometimes?
I could say it's OK, since submarining shouldn't be as bad as HASL, but
would like some expert comments.
Lou Hart
Compunetix Quality Assurance
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========================================================================Date: Thu, 29 Nov 2001 18:32:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: board dunked in wave solder
X-To: "<Peter George Duncan>" <[log in to unmask]>
Shudder slightly indeed Peter. We all wish we could garner such results.
Isn't it amazing how much abuse well designed and processed boards can endure?
MoonMan
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========================================================================Date: Thu, 29 Nov 2001 19:41:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: board dunked in wave solder
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Hi Lou!
I think that this is the one event when it happens, eclipses any other event
in printed circuit assembly manufacturing, that brings forth a flood (no pun
intended) of intense emotions from the observer...shock, horror, terror,
regret, desperation, depression (it's not for the faint hearted). Those
emotions multiply exponentially depending on the assemblies complexity and
value. It does happen though...I think some of my gray hair has come from a
few of those over the years.
But in those times when it came down to having to salvage the mess, I would
say there were no problems. The decision would always be made based on
dollars. Did it make more economic sense to put the extensive labor needed to
clean-up everything, or just start from scratch again...
One thing to do if you're quick enough when it happens, is to try and grab
the board as it comes off the conveyer and "pour" the solder off as quickly
as you can, and in such a way to involve the least number of components, or
the obviously complex ones, PGA's, BGA's, etc...takes for some quick thinking
when you're staring in horror as the event unfolds!
Molten solder on top of the board hasn't ruined the PCB in my experience,
it's just a matter of cleaning-up all the shorts that happen...again, it's a
economics thing. If you want/need to salvage a board that's "sub'ed", I don't
think quality is that much of a concern if it's done by someone who can
handle something like this.
It's happened a time or two with me, and I've bought more than a few lunches
for a few ladies that were magicians with soldering irons and solder
extractors...they are worth their weight in gold.
-Steve Gregory-
> TechNetters, I know there was discussion of this before, many months ago,
> but I can't track down the postings in the archives. Please comment.
>
> We have with solder on some of the top side, surrounding some components
> (ICs and passives). It was dunked in wave solder. Are boards that have
> "submarined" (I think someone used this term in the earlier discussion)
> useable if excess solder is removed? Never useable? Sometimes?
>
> I could say it's OK, since submarining shouldn't be as bad as HASL, but
> would like some expert comments.
>
> Lou Hart
> Compunetix Quality Assurance
>
--part1_6b.1e7c58d0.29382fc9_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Lou!<BR>
<BR>
I think that this is the one event when it happens, eclipses any other event in printed circuit assembly manufacturing, that brings forth a flood (no pun intended) of intense emotions from the observer...shock, horror, terror, regret, desperation, depression (it's not for the faint hearted). Those emotions multiply exponentially depending on the assemblies complexity and value. It does happen though...I think some of my gray hair has come from a few of those over the years.<BR>
<BR>
But in those times when it came down to having to salvage the mess, I would say there were no problems. The decision would always be made based on dollars. Did it make more economic sense to put the extensive labor needed to clean-up everything, or just start from scratch again...<BR>
<BR>
One thing to do if you're quick enough when it happens, is to try and grab the board as it comes off the conveyer and "pour" the solder off as quickly as you can, and in such a way to involve the least number of components, or the obviously complex ones, PGA's, BGA's, etc...takes for some quick thinking when you're staring in horror as the event unfolds!<BR>
<BR>
Molten solder on top of the board hasn't ruined the PCB in my experience, it's just a matter of cleaning-up all the shorts that happen...again, it's a economics thing. If you want/need to salvage a board that's "sub'ed", I don't think quality is that much of a concern if it's done by someone who can handle something like this.<BR>
<BR>
It's happened a time or two with me, and I've bought more than a few lunches for a few ladies that were magicians with soldering irons and solder extractors...they are worth their weight in gold.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">TechNetters, I know there was discussion of this before, many months ago,<BR>
but I can't track down the postings in the archives. Please comment.<BR>
<BR>
We have with solder on some of the top side, surrounding some components<BR>
(ICs and passives). It was dunked in wave solder. Are boards that have<BR>
"submarined" (I think someone used this term in the earlier discussion)<BR>
useable if excess solder is removed? Never useable? Sometimes?<BR>
<BR>
I could say it's OK, since submarining shouldn't be as bad as HASL, but<BR>
would like some expert comments.<BR>
<BR>
Lou Hart<BR>
Compunetix Quality Assurance<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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========================================================================Date: Thu, 29 Nov 2001 17:05:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: board dunked in wave solder
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hi,
i don't know. i think that getting boards-bonded-to-core assemblies back from the field when the boards have fallen off the core eclipses a board-in-the-solder-pot problem any day for angst. not that this ever happened to me you understand.
phil
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<BODY>
<DIV><SPAN classe1560101-30112001><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN classe1560101-30112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN classe1560101-30112001><FONT face=Arial color=#0000ff size=2>i
don't know. i think that getting boards-bonded-to-core
assemblies back from the field when the boards have fallen off the
core eclipses a board-in-the-solder-pot problem any day for angst. not
that this ever happened to me you understand.</FONT></SPAN></DIV>
<DIV><SPAN classe1560101-30112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN classe1560101-30112001><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN><FONT face=arial,helvetica><FONT
size=2></DIV></FONT></FONT></BODY></HTML>
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========================================================================Date: Thu, 29 Nov 2001 23:33:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
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Dave:
Some of the immersion Silver finishes have a co-deposited organic
anti-tarnish in them.
Rudy Sedlak
RD Chemical Company
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========================================================================Date: Thu, 29 Nov 2001 21:53:57 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Pick & place equipment process control
In-Reply-To: <002301c17910$9323a930$0c140a0a@hshin>
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Hello,
I have asked this question before but did not receive many replies.
Does anyone have any success or suggestion on measuring P&P machine
parameters in line? Such as vacuum pressures, vision alignment error and
placement compensation, placement pressure, drive speed and movement.
Obviously I am setup SPC for my P&P process.
P&P machines that we have in our company do not seem to be "opened"
systems. The only parameters I can measure are indirect - pickup error%,
reject rate, and I went as far as using test vehicles to verify
placement accuracy with AOI. These are however, not direct machine
parameters and do not give me a clear picture of the major moving parts
on the machine.
What other variations within a chip shooting process can one measure and
control?
Rgds,
Peter
_________________________________________________________
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========================================================================Date: Fri, 30 Nov 2001 15:52:05 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anil Kher <[log in to unmask]>
Organization: Micro Interconnexion Pvt. Ltd
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUED ASSOCIATES.
X-To: "Stephen R. Gregory" <[log in to unmask]>
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boundary="----=_NextPart_000_005A_01C179B6.F5E7C320"
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charset="UTF-8"
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Dear All
I was out of office for the last ten days. I regret the inconvenience this worm has caused to you.
I am surprised my virus shield did not work nor did the on line sacn on the day following
Sorry
Anil Kher
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<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF">Dear All</FONT></FONT></DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF">I was out of office for the last ten days. I regret the
inconvenience this worm has caused to you.</FONT></FONT></DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF">I am surprised my virus shield did not work nor did the on
line sacn on the day following</FONT></FONT></DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF">Sorry</FONT></FONT></DIV>
<DIV><FONT face=arial,helvetica><FONT lang=0 face=Arial color=#000000 size=2
FAMILY="SANSSERIF">Anil Kher</DIV></FONT></FONT></BODY></HTML>
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========================================================================Date: Fri, 30 Nov 2001 06:53:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: board dunked in wave solder
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Hi Lou, Steve
I agree with Steve - if it makes sense $$$ or schedule / parts availability - salvage it. If it's a cheapo then the decision is obvious.
My "best" submarine experience: first month on the new job. Been in tweaking the wave machine all morning, and the boss wanders in looking for me. While chatting he watches a board going over the wave... SWOOSH.
Actually - if I'd been thinking fast I would have parlayed that into retrofitting the chain with L fingers (it's got V on it). I suspect I had not quite fitted the board into the V... but as Steve says - the shock and horror...
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/29/01 08:41PM >>>
Hi Lou!
I think that this is the one event when it happens, eclipses any other event
in printed circuit assembly manufacturing, that brings forth a flood (no pun
intended) of intense emotions from the observer...shock, horror, terror,
regret, desperation, depression (it's not for the faint hearted). Those
emotions multiply exponentially depending on the assemblies complexity and
value. It does happen though...I think some of my gray hair has come from a
few of those over the years.
But in those times when it came down to having to salvage the mess, I would
say there were no problems. The decision would always be made based on
dollars. Did it make more economic sense to put the extensive labor needed to
clean-up everything, or just start from scratch again...
One thing to do if you're quick enough when it happens, is to try and grab
the board as it comes off the conveyer and "pour" the solder off as quickly
as you can, and in such a way to involve the least number of components, or
the obviously complex ones, PGA's, BGA's, etc...takes for some quick thinking
when you're staring in horror as the event unfolds!
Molten solder on top of the board hasn't ruined the PCB in my experience,
it's just a matter of cleaning-up all the shorts that happen...again, it's a
economics thing. If you want/need to salvage a board that's "sub'ed", I don't
think quality is that much of a concern if it's done by someone who can
handle something like this.
It's happened a time or two with me, and I've bought more than a few lunches
for a few ladies that were magicians with soldering irons and solder
extractors...they are worth their weight in gold.
-Steve Gregory-
> TechNetters, I know there was discussion of this before, many months ago,
> but I can't track down the postings in the archives. Please comment.
>
> We have with solder on some of the top side, surrounding some components
> (ICs and passives). It was dunked in wave solder. Are boards that have
> "submarined" (I think someone used this term in the earlier discussion)
> useable if excess solder is removed? Never useable? Sometimes?
>
> I could say it's OK, since submarining shouldn't be as bad as HASL, but
> would like some expert comments.
>
> Lou Hart
> Compunetix Quality Assurance
>
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========================================================================Date: Fri, 30 Nov 2001 07:07:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Barry Gallegos <[log in to unmask]>
Got distracted by work, if you can believe that, and didn't finish.
You know all this stuff but if your conveyor is traveling at 4'/minute, that
means 1'/15 seconds (great math, eh?). If you use your Lev Chek glass one
inch grid plate and you verify your contact area is parallel and is about
1.5" across, then you can determine your contact time. For more "normal"
boards, depending on your matrix indicators, your contact time should be
about 1.5 - 3 seconds - depending on conveyor speed.
For massive boards, thermally speeking, the contact time may be much longer
as the conveyor speed may be as slow as 1'/minute or less. Scary stuff these
boards and conditions.
Of course, with all this stuff, I'm using through hole technology as the
baseline for the settings. Mixed technoloty will be the same though SMT ohly
types can be more "normally" profiled.
Once sub-process and process "calibration" is done manually, profilometers
may be used as well. Of course, many "trust" the machine's computer if so
equipped. No matter, I still do manual "calibrations" on a regular basis for
computer controlled machines and I do this at the beginning of each new
product lot on less automated machines - all a function of my trusty matrix
having all the "numbers"/paramaters for each board type required. My matrix
then is converted to SPC information as process control charts based on
process effects as acceptable quality solder joints.
I'm done and distracted by work again. Just killing a little time on a very
old subject I don't get to visit that much anymore. What's the company that
makes the Lev Check glass plate again?
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 08:42:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Wave Solder Profiling
MIME-Version: 1.0
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Mornin' Earl,
That would be Hexacon Electric out of NJ.
Steve
-----Original Message-----
What's the company that
makes the Lev Check glass plate again?
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 07:47:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Pelchat, Janice" <[log in to unmask]>
Subject: Conformal Coat House
MIME-Version: 1.0
Content-Type: text/plain
Does anyone have any recommendations they can make about coating houses in
the New England area?
You can contact me offline if you prefer.
Jan Pelchat
[log in to unmask]
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========================================================================Date: Fri, 30 Nov 2001 09:01:31 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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If you need some design help on materials you can call me.
Steve Kelly
PFC Flexible Circuits Ltd.
(416) 750-8433
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Scott R. Madans
Sent: Wednesday, November 28, 2001 8:48 PM
To: [log in to unmask]
Subject: [TN] Flexible PC Board
Howdy All,
I am new to this list and I thank the folks at 3M's
Microflex division for pointing me here. Y'all can blame
them later after reading this lengthily post...
The acceptance of my lousy prototype was excellent, so I was
looking at ideas for a more robust and fine-tuned design
using a flexible circuit.
I need a flexible PC board operating at 12v DC. Size is
about 1/2" x 6" or 8". The mounting is static, but the
flexible shape is required because of the variety of
mountings. Also, the outdoor environment will be greasy,
dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
needs to be durable. There will be no direct abrasives.
The board and protection should be no more than about
2/10ths thick.
Is there something like that out there? You've probably
seen that "soft-touch" switch rubber used on keypads. A
slightly firmer version of that with copper cladding (or
something to etch) would be about perfect, as long as it's
tough stuff.
Thanks in advance and I appreciate your guidance.
- Scott
(775) 849-2030
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========================================================================Date: Fri, 30 Nov 2001 13:52:11 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Rusty
In-Reply-To: <[log in to unmask]>
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The term rust may be used slightly differently UK/US, so I dredge up from
memory what I was taught sometime ago in last century England:
Strictly only iron can rust, but it is more than just iron oxide. It is a
dynamic mixture of iron oxides and water which perpetuates itself as long as
there is a supply of oxygen in damp conditions.
Non ferrous metals don't rust therefore but they may tarnish. Phosphorus is
not a metal, so it can neither rust nor tarnish to oxide, it actually burns
quite vigorously.
As mentioned below generally oxides do not conduct, the only one I can think
of off hand that does is silver. Some oxides in conjunction with the base
metal can make rectifiers so conduct in one direction only. In iron oxide
terms old fashioned cast iron drainpipes used to accidentally act as simple
radio receivers and re-transmitters due to this rectification phenomenon.
Confession time: when I get asked this sort of "I ought to/used to know this
basic sort of stuff" question, or need to know enough to ask a harder one
myself, I quite often visit www.howstuffworks.com
You can ask almost anything you like and it usually comes back quickly with
the answer you were thinking of. More importantly it assumes almost no prior
knowledge so you can understand it.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
Sent: Friday, November 30, 2001 12:19 AM
To: [log in to unmask]
Subject: Re: [TN] Rusty
Hi, Kathy,
Rust is a very poor conductor, as anyone with a rusty car and wiring
trouble can testify. Corrosion on battery terminals can ruin a connection,
and where oxidisation is deliberate, such as in anodising of aluminium,
electrical conductivity is poor to non-existant, depending on the thickness
of the oxide layer.
Peter Duncan
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Rusty
<[log in to unmask]
ORG>
11/30/01
01:55 AM
Please
respond to
"TechNet
E-Mail
Forum."
I was asked a question today and I can't seem to find the answer. I think
I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
(See attached file: TEXT.htm)
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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========================================================================Date: Fri, 30 Nov 2001 08:22:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: board dunked in wave solder
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We rework them but very carefully. With SOIC, QFP, etc solder can cause a lot of solder shorting underneath that isn't visible. Either xray to confirm all solder removeal underneath or remove to confirm.
Kathy
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<DIV>We rework them but very carefully. With SOIC, QFP, etc solder can
cause a lot of solder shorting underneath that isn't visible. Either xray
to confirm all solder removeal underneath or remove to confirm. </DIV>
<DIV> </DIV>
<DIV>Kathy</DIV></BODY></HTML>
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========================================================================Date: Fri, 30 Nov 2001 09:47:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anita Sargent <[log in to unmask]>
Subject: Anita Sargent/Endicott/IBM is out of the office.
MIME-Version: 1.0
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I will be out of the office starting November 30, 2001 and will not return
until December 3, 2001.
I will respond to your message when I return.
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========================================================================Date: Fri, 30 Nov 2001 08:52:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Steve Sauer <[log in to unmask]>
Steve,
Can't thank you enough. Probably never will use or see one again but good to
know as I always forget or loose that name. My other problem with thest
plates is my inept handling of them. I must clamp them too hard in the
fingers or they just break because of thermal shock. Tried preheating them
but still kept breaking them when they hit the wave. Any suggestions beside
buying several as spares?
Earl
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========================================================================Date: Fri, 30 Nov 2001 08:56:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Rusty
X-To: mike Fenner <[log in to unmask]>
Mike,
That was interesting stuff as is the site you indicated. Very interesting
and useful.
One thing: Phosphorous burns - ok - so it oxidizes, right? Webster, or some
such dictionary, defines oxidation as burning. Not too interesting but
factual, eh?
Earl
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========================================================================Date: Fri, 30 Nov 2001 09:52:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Westheimer <[log in to unmask]>
Subject: Fw: Differential impedance
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From: Scott Westheimer
To: Technet
Sent: Friday, November 30, 2001 9:06 AM
Subject: Differential impedance
I have a question regarding differential signal pairs and differential impedance that I hope someone can help me with. We are designing a 14 layer board and the finished thickness needs to .062" and we require 100 ohms. Some of the internal layers we have split planes. Would these be considered strip line or microstrips?
Thanks
Scott
------=_NextPart_000_0060_01C17984.A9219980
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charset="iso-8859-1"
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</HEAD>
<BODY bgColor=#ffffff>
<DIV> </DIV>
<DIV style="FONT: 10pt arial">
<DIV style="BACKGROUND: #e4e4e4; font-color: black"><B>From:</B> <A
href="mailto:[log in to unmask]" [log in to unmask]>Scott
Westheimer</A> </DIV>
<DIV><B>To:</B> <A href="mailto:[log in to unmask]"
[log in to unmask]>Technet</A> </DIV>
<DIV><B>Sent:</B> Friday, November 30, 2001 9:06 AM</DIV>
<DIV><B>Subject:</B> Differential impedance</DIV></DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>I have a question regarding differential signal
pairs and differential impedance that I hope someone can help me with. We are
designing a 14 layer board and the finished thickness needs to .062" and we
require 100 ohms. Some of the internal layers we have split planes. Would these
be considered strip line or microstrips?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Thanks </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Scott</FONT></DIV></BODY></HTML>
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========================================================================Date: Fri, 30 Nov 2001 09:05:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary McCauley <[log in to unmask]>
Subject: Re: Rusty
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Explosion, burning, oxidation. It's a
matter of time. ;-)
gary mccauley
PC Boards, Inc.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 8:56 AM
To: [log in to unmask]
Subject: Re: [TN] Rusty
Mike,
That was interesting stuff as is the site you indicated. Very interesting
and useful.
One thing: Phosphorous burns - ok - so it oxidizes, right? Webster, or some
such dictionary, defines oxidation as burning. Not too interesting but
factual, eh?
Earl
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========================================================================Date: Fri, 30 Nov 2001 09:06:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
X-To: Scott Wesheimer <[log in to unmask]>
I know you remember the classic definition of microstrip as a function of
surface traces referenced only to one internal plane - either exposed to air
or buried by solder mask. Likewise, stripline is a function of traces
between two reference planes either centered or offset. Don't know what
difference continuous or split planes make to these definitions but for
possible functionality and performance factors.
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 10:15:56 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: board dunked in wave solder
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I have reworked many like this, and the comments already offered regarding
cost analysis are important to consider. Also verify that the components
involved can take the heat cycle of the rework, or else replace them.
Kathy's comment about x-ray for SOIC's etc. was right on the mark. Little
slivers of solder bridging under those parts can be nearly impossible to see.
Jon Moore
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========================================================================Date: Fri, 30 Nov 2001 09:10:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Rusty
X-To: Gary McCauley <[log in to unmask]>
Yes, but not to get carried away, while attempting to stay within the realm
of this forum, isn't an explosion nothing more than rapid burning.
Therefore, oxidation must be really fast burning when an explosion is effected.
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 15:10:13 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Rusty
MIME-Version: 1.0
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Two things to add to this Friday afternoon discussion.
I was taught in my chemistry class the following mnemonics:
LEO - Loss of Electrons = Oxidation
GER - Gain of Electrons = Reduction
So oxidation may result in burning or even an explosion. But not everything that oxidises
burns.
The difference between burning and exploding is the rate at which the chemical reaction
proceeds. My unreliable memory reminds me that in burning the reaction passes from molecule to
molecule while in an explosion the reaction proceeds through the medium at the speed of sound.
Have a nice weekend,
[log in to unmask] wrote:
> Yes, but not to get carried away, while attempting to stay within the realm
> of this forum, isn't an explosion nothing more than rapid burning.
> Therefore, oxidation must be really fast burning when an explosion is effected.
>
> MoonMan
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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========================================================================Date: Fri, 30 Nov 2001 07:53:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: Fw: Differential impedance
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
There is a large body of free information on the UltraCAD website:
http://www.ultracad.com/homepage.htm
that deals with trace impedance and other layout issues. They also have
several free calculator programs, including one to verify or aid impedance -
vs. - geometry tradeoffs. Try it . . . you'll like it!
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 7:07 AM
To: [log in to unmask]
Subject: Re: [TN] Fw: Differential impedance
I know you remember the classic definition of microstrip as a function of
surface traces referenced only to one internal plane - either exposed to air
or buried by solder mask. Likewise, stripline is a function of traces
between two reference planes either centered or offset. Don't know what
difference continuous or split planes make to these definitions but for
possible functionality and performance factors.
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 08:24:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: Fw: Differential impedance
In-Reply-To: <006301c179ae$92055d20$7801a8c0@GULTECHGM>
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Micro strip is an external transmission line referenced to an internal
plane/dielectric & air.
Stripline in an internal transmission line referenced between two planes
and dielectric.
-Denis
At 09:52 AM 11/30/2001 -0500, you wrote:
>
>From: <mailto:[log in to unmask]>Scott Westheimer
>To: <mailto:[log in to unmask]>Technet
>Sent: Friday, November 30, 2001 9:06 AM
>Subject: Differential impedance
>
>I have a question regarding differential signal pairs and differential
>impedance that I hope someone can help me with. We are designing a 14
>layer board and the finished thickness needs to .062" and we require 100
>ohms. Some of the internal layers we have split planes. Would these be
>considered strip line or microstrips?
>
>Thanks
>
>Scott
--=====================_10662161==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
Micro strip is an external transmission line referenced to an internal
plane/dielectric & air.<br>
Stripline in an internal transmission line referenced between two planes
and dielectric.<br>
-Denis<br>
At 09:52 AM 11/30/2001 -0500, you wrote:<br>
<blockquote type=cite class=cite cite> <br>
<b>From:</b> <a href="mailto:[log in to unmask]">Scott
Westheimer</a> <br>
<b>To:</b> <a href="mailto:[log in to unmask]">Technet</a> <br>
<b>Sent:</b> Friday, November 30, 2001 9:06 AM<br>
<b>Subject:</b> Differential impedance<br><br>
<font face="arial" size=2>I have a question regarding differential signal
pairs and differential impedance that I hope someone can help me with. We
are designing a 14 layer board and the finished thickness needs to
.062" and we require 100 ohms. Some of the internal layers we have
split planes. Would these be considered strip line or
microstrips?</font><br>
<br>
<font face="arial" size=2>Thanks </font><br>
<br>
<font face="arial" size=2>Scott</font></blockquote></html>
--=====================_10662161==_.ALT--
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========================================================================Date: Fri, 30 Nov 2001 10:36:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Thanks you
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_451873A3.4F2E431E"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_451873A3.4F2E431E
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This forum is the best out there. Thanks to all who responded to the rusty question.
Kathy
--=_451873A3.4F2E431E
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<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>This forum is the best out there. Thanks to all who responded to the
rusty question. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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========================================================================Date: Fri, 30 Nov 2001 10:39:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
X-To: Denis Lefebvre <[log in to unmask]>
Denis,
Your definition certainly is simpler than mine. I'll keep yours.
Did I get you all you needed in addition to the check list? Let me know off
line what I owe you.
Concerning the 14 layer .062 MLB, I must be living in another world. Hell, I
was just getting over 10 layer types that thick notwithstanding impedance.
This 14 layer thing went right over my head.
I know we all are using single ply constructions but isn't this pushing it
just a bit. I mean you'd have to use 3 mil stuff, whatever the core and preg
would be, to get this done regardless of the split plane and trace width
considerations.
Someone please tell me how this board would be made, and made to work.
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 17:39:21 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Martyn Gaudion <[log in to unmask]>
Subject: Re: Fw: Differential impedance
In-Reply-To: <006301c179ae$92055d20$7801a8c0@GULTECHGM>
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Scott,
You may also like to look at the application notes
on the Polar site:
www.polarinstruments.com/support/cits/cits_index.html
Kind regards
Martyn Gaudion
Polar Instruments
T: + 44 1481 253081
F: + 44 1481 252476
M: +44 7710 522748
E: [log in to unmask]
www.polarinstruments.com
At 09:52 30/11/01 -0500, you wrote:
>
>From: <mailto:[log in to unmask]>Scott Westheimer
>To: <mailto:[log in to unmask]>Technet
>Sent: Friday, November 30, 2001 9:06 AM
>Subject: Differential impedance
>
>I have a question regarding differential signal pairs and differential
>impedance that I hope someone can help me with. We are designing a 14
>layer board and the finished thickness needs to .062" and we require 100
>ohms. Some of the internal layers we have split planes. Would these be
>considered strip line or microstrips?
>
>Thanks
>
>Scott
--=====================_6843055==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
Scott,<br>
<br>
You may also like to look at the application notes<br>
on the Polar site:<br>
<br>
<a href="http://www.polarinstruments.com/support/cits/cits_index.html" eudora="autourl">www.polarinstruments.com/support/cits/cits_index.</a><a href="http://www.polarinstruments.com/support/cits/cits_index.html" eudora="autourl">html<br>
<br>
<br>
<br>
</a>Kind regards<br>
Martyn Gaudion <br>
Polar Instruments<br>
<br>
T: + 44 1481 253081<br>
F: + 44 1481 252476<br>
M: +44 7710 522748<br>
E: [log in to unmask]<br>
<a href="http://www.polarinstruments.com/" eudora="autourl">www.polarinstruments.com</a>
<br>
<br>
<br>
At 09:52 30/11/01 -0500, you wrote:<br>
<blockquote type=cite cite> <br>
<b>From:</b> <a href="mailto:[log in to unmask]">Scott Westheimer</a> <br>
<b>To:</b> <a href="mailto:[log in to unmask]">Technet</a> <br>
<b>Sent:</b> Friday, November 30, 2001 9:06 AM<br>
<b>Subject:</b> Differential impedance<br>
<br>
<font face="arial" size=2>I have a question regarding differential signal pairs and differential impedance that I hope someone can help me with. We are designing a 14 layer board and the finished thickness needs to .062" and we require 100 ohms. Some of the internal layers we have split planes. Would these be considered strip line or microstrips?</font><br>
<br>
<font face="arial" size=2>Thanks </font><br>
<br>
<font face="arial" size=2>Scott</font></blockquote></html>
--=====================_6843055==_.ALT--
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========================================================================Date: Fri, 30 Nov 2001 11:30:13 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
Just one more thing concerning split planes. Has 274x been fixed to handle
them or do we have to continue using 274d to view them without the mush? I
know the answer must be using ODB++ instead of Gerber output, but some
aren't there yet.
MoonMan
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========================================================================Date: Fri, 30 Nov 2001 12:46:28 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen S. Schiera" <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: Graham Naisbitt <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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========================================================================Date: Fri, 30 Nov 2001 13:34:37 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lefebvre, Scott" <[log in to unmask]>
Subject: LLP Leadless LeadFrame Package
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have been asked if engineering could use this package on their new
designs. I've used LCC before and had no real problems but they were not
blind connections like this package.
I have concerns that the center pad on the bottom of the component would be
susceptible to shorting to the adjacent outer pads. Do any of you have
other concerns that you could share with me, it would be greatly
appreciated.
Scott Lefebvre
> F (530)265-1041
> 8 (530)265-1012
> * [log in to unmask]
>
>
>
>
>
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========================================================================Date: Fri, 30 Nov 2001 19:51:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Steve
Then my best recommendation is to use the black-light in a suitable
inspection chamber. This will show exactly where the coating is and isn't.
We have special units for this, but if you want details, please let me know
off-line.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Friday, November 30, 2001 06:46
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
----------------------------------------------------------------------------
-----
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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----------------------------------------------------------------------------
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========================================================================Date: Fri, 30 Nov 2001 15:07:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Red plaque on Silver plated wire?
MIME-Version: 1.0
Content-Type: text/plain
Anybody out there ever hear about having to control red plaque on silver
plated wire?
This showed up on a spec for a job we're contemplating.
Any and all ('cept wisecracks) responses appreciated. Thanks.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
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========================================================================Date: Fri, 30 Nov 2001 15:45:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Color additives for conformal coat
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
I have to second Graham's Black Light suggestion. We had the same
problem/learning curve in a manual coating operation I ran. The Coaters
didn't realize coating on the pins/connectors would be a problem. Sometimes
they were cleaning it best they could but leaving a residue. We'd plug the
assembly in for testing and it would fail. We only had to show them the
assembly under blacklight once to solve the problem.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 2:52 PM
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Steve
Then my best recommendation is to use the black-light in a suitable
inspection chamber. This will show exactly where the coating is and isn't.
We have special units for this, but if you want details, please let me know
off-line.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Friday, November 30, 2001 06:46
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
---------------------------------------------------------------------------------
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
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---------------------------------------------------------------------------------
========================================================================Date: Fri, 30 Nov 2001 15:52:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Seeger <[log in to unmask]>
Organization: Applied CAD Knowledge Inc
Subject: IPCDC Boston mtg 11-Dec, Current Carrying update
X-To: [log in to unmask], [log in to unmask],
[log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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,
A Current Topic
The Greater Boston Chapter of the IPC Designer's Council will
hold its next meeting on Tuesday, December 11th at the Four
Points Hotel on Totten Pond Rd in Waltham MA at 6pm.
Topic and Speaker:
Michael Jouppi of Coretec, Chairman of the IPC 1-10b Task Group
will present the latest developments in said groups efforts to
update the time honored and widely referenced current carrying
conductor charts. This long needed revamp will shed new light
on everyone's favorite look-up. Most designers have found the
age old charts lacking for current (sorry!) packaging trends.
With today's densities and new and fine geometries (fine lines,
micro or blind vias, embedded passives) new understanding must
be brought to the problems of power handling, including effects
of transients and planes. Tools will be provided.
Agenda:
Please note there is a $15 meeting fee for members, $20 for
non-members. Pizza/soft drinks will be served.
6:00 Arrivals and Pizza
6:45 Chapter Business
7:00 Michael Jouppi, Coretec
Location/Directions:
The Four Points Hotel (fka the Wyndham) in Waltham is located
at exit 27A off route 95/128, proceed east on Totten Pond Rd
and the hotel is on the right.
RSVP's requested:
Please RSVP by sending an email to [log in to unmask] with
the subject "RSVP IPC/DC" or phone Judy Horn at 781 942 7471
by Friday 5pm, Dec 7th. Please treat an RSVP as a commitment
to attend as the food order is based on this.
President's Note:
I'm very glad to have Mr Jouppi available for a presentation,
his background as a Thermal Engineer in several aerospace firms
allows him great insight into the problems of current handling.
His works to date on the Current Carrying Charts update have
made great progress and we can look forward to very insightful
perspective on what may become next year's widely distributed
new standard.
As this meeting falls the day after the normal Steering date
I'd like to ask Steering Committee, and any willing member, to
stay a few minutes after for chapter business.
Mission:
PCB Design is not called "do" for a reason. Done properly,the
design process is a creative problem solving discipline. To
address the packaging needs of electronics for today and to-
morrow, the physical designer needs an avenue to get exposed
and familiar with many different techniques and technologies.
The Greater Boston Chapter of the IPC Designer's Council is
committed to presenting stake holders from every aspect of the
packaging realm. Our hope is to help you gain insight and un-
derstanding of the many possibilities in solving core problems.
Your attendance, help and participation are most welcome.
Thanks and regards,
--
Jeff Seeger Applied CAD Knowledge Inc
Chief Technical Officer Tyngsboro, MA 01879
jseeger "at" appliedcad "dot" com 978 649 9800
President, Greater Boston Chapter, IPC Designer's Council
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========================================================================Date: Fri, 30 Nov 2001 16:13:35 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: LLP Leadless LeadFrame Package
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_14e.4e610f8.2939507f_boundary"
--part1_14e.4e610f8.2939507f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
From the design perspective, I don't agree with the supplier recommended data
sheets regarding footprint criteria. As you point out the separation between
large land area and individual I/O lands is very small (ie .002-.005) I
beefed mine up to something like .010. I don't like the solder stencil
pattern either; they would have the paste offset onto the mask by .010-.025.
I didn't do that. The LLP doesn't require special surface finish or exclude
any as some would indicate. First pass success is needed due to quite
challenging to rework. We built quite a few parts to shorts adding the LLP
by hand, never do that it was ugly.
Those are the areas of "gotcha" concerns; every component has their own
gotcha's. I like the LLP package, used as intended it is very nice.
Especially if it is replacing odd form parts.
Brad
--part1_14e.4e610f8.2939507f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>From the design perspective, I don't agree with the supplier recommended data sheets regarding footprint criteria. As you point out the separation between large land area and individual I/O lands is very small (ie .002-.005) I beefed mine up to something like .010. I don't like the solder stencil pattern either; they would have the paste offset onto the mask by .010-.025. I didn't do that. The LLP doesn't require special surface finish or exclude any as some would indicate. First pass success is needed due to quite challenging to rework. We built quite a few parts to shorts adding the LLP by hand, never do that it was ugly.
<BR>
<BR>Those are the areas of "gotcha" concerns; every component has their own gotcha's. I like the LLP package, used as intended it is very nice. Especially if it is replacing odd form parts.
<BR>
<BR>Brad</FONT></HTML>
--part1_14e.4e610f8.2939507f_boundary--
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========================================================================Date: Fri, 30 Nov 2001 21:09:57 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Red plaque on Silver plated wire?
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Could "Red Plaque" be another way of saying "tarnish"?
If so, dipping the Silver into an antitarnish sounds too easy, there must be
something wrong with this idea?
Rudy Sedlak
RD Chemical Company
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