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Date: Fri, 16 Nov 2001 07:52:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Conformal Coating to IPC Class 3
MIME-Version: 1.0
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When I read IPC Standards regarding conformal coating requirements for the
different classes, all I can find is coating thickness on a board.
**Mike, I feel your pain. You can find the materials requirements, the
minimum that conformal coating materials must do, in IPC-CC-830. The B
revision should be released in the next few months. That is primarily a
materials procurement or qualification document. The two standards dealing
with coating after it is put on are IPC-A-610 and J-STD-001. Both
documents boil down to the same thing: put coating down where the drawing
says, keep coating off where it ain't supposed to be, and make sure the
coating film has a certain thickness and a certain quality, i.e. no
pinholes, cracks wrinkles, etc. It is left to the user to determine what a
coating needs to do for their hardware. You might find some more insight
if you look at the latest draft of the Conformal Coating Handbook, which
should be nearing publication.
I'm trying to work to class 3 standards for conformal coating and am
meeting those thickness requirements, however, I have to wonder how it
works on a BGA for example, where the coating thickness is sufficient but
doesn't completely cover and encapsulate the component. In other words,
there is a gap between the top of the BGA and the PCB.
**Thicknesses are measured on a flat unencumbered surface, not on just any
surface on the board. You may have the minimum 2 mils of acrylic coating
on the board, but it won't be that thick on sharp component edges, or tops
of components, and certainly not on the underside of the components. The
only coating that will get the bottom side of components is
paralene/parylene/paralyne (I never can remember which one is right).
Any thoughts on this would be appreciated.
**If'n ya want, give me response off-line if there was something more
specific you need.
Doug Pauls
Rockwell Collins
"Conformal Coating - The Great Career Limiting Move"
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Date: Fri, 16 Nov 2001 08:53:36 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have nothing
to do!
Removing warp is actually rather simple, and is an IPC documented procedure.
I've attached a link to our online procedure with more details. We find that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Fri, 16 Nov 2001 08:03:30 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeffery,
I certainly apreciate your posting as a reminder to me as well. I would add,
from a DFM point of view concerning materials and their processing:
Getek has good electrical properties, as you say, but processing and some
results associated with it can be dissapointing. This material must be
processed more along the lines of polyimide. It requires a more damanding
press cycle than those for FR4 types using simple straight up processing
from 0 to 90 minutes or so. Therefore, not all shops like or do well with it.
The Rogers and Arlon (liscensed from Rogers but with slight variations
concerning properties) material is really neat stuff. It has processing
drawbacks as well as being limited in prepreg glass styles and thicknesses
when reinforced. If improperly processed, as with any material type, it has
several failing characteristics. As is widely known, this type material
often is married/laminated to Getek to meet design and performance
requirements. Really low DC and loss tangents.
My money is on BT epoxy blends when and where possible. It has high
performance characteristics and is easily processed. I have designed it in
and used in in very complex, large, high layer count MLB's with great
success. It is/was used in some Cray designs built by IBM, as one example.
Just wanted to add to your good comments,
MoonMan
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Date: Fri, 16 Nov 2001 08:23:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: solderability
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_EFB52C68.4F2E4308"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_EFB52C68.4F2E4308
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
I would suggest the IPC-TM-650. There are several test methods listed =
there. =20
Kathy=20
--=_EFB52C68.4F2E4308
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I would suggest the IPC-TM-650. There are several test methods listed
there. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_EFB52C68.4F2E4308--
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Date: Fri, 16 Nov 2001 08:33:17 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Board Warp
X-To: Jeff Ferry <[log in to unmask]>
Jeff,
Meant in the kindess possible way, us DFM/CE fanatics would love to put you
folks out of business knowing full well YOU could do anything else very
well, as well. Well damn!
Earl
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Date: Fri, 16 Nov 2001 10:17:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: OA & LCCs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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We are looking to mount a GPS receiver that is constructed similar to an LCC
type package. That is, it is an FR-4 board with gold terminations on the
side. These terminations also wrap under the board about .035". The
underside of the board has traces covered with soldermask. Has anybody ever
used a package such as this with water soluble flux cleaned with DI water
(we have an in-line system)? When soldered, there is virtually no standoff
of the receiver. Is there a danger of flux being trapped underneath and
causing potential problems? Or is this a non-issue. I am thinking that
resistors and capacitors have terminations that wrap underneath and they do
not seem to be a problem. Thanks.
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
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Date: Fri, 16 Nov 2001 09:15:12 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ashok Dhawan <[log in to unmask]>
Subject: Re: WaveSolder Process Monitoring Tools
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I am using Wave Optimizer supplied by ECD. There could be other suppliers as
well.
Ashok Dhawan P.Eng.
Engineering
C-MAC Network Systems Inc.
1455 Mountain Roar
Winnipeg Manitoba R2X 2Y9
WWW.CMAC.COM
TEL (204) 631 7208
FAX (204) 631 7294
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
> Sent: Thursday, November 15, 2001 4:25 PM
> To: [log in to unmask]
> Subject: [TN] WaveSolder Process Monitoring Tools
>
>
> Does anyone know of profiling devices or tools that you run through a
> wavesolder machine that will capture preheat temperature & wave height?
> Thanks,
>
> ------------------------------------------------------------------
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>
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Date: Fri, 16 Nov 2001 10:23:33 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
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This MAY be so simple, we will wonder why/how they did not see the problem...
To understand this analysis/suggestion, you have to understand the difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a similar
design? (In other words, is the problem one of process/board design, or one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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Date: Fri, 16 Nov 2001 10:28:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Peter,
I'm probably out of my league here, but the board house may be able to
compensate somewhat with "etch compensation", adding copper width where the
most etching will take place. If you know you're going to lose 2 or 3 mils
[.05-.08mm] per side in the final etch, add on copper before the
lam/drill/plate processes to get what you want. Check with your supplier
to see if this would work. I know this doesn't help you with this board
now, but may fix future problems. Time for Tums...(or Rolaids, Ativan,
Guinness, etc.).
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
"<Peter
George To: [log in to unmask]
Duncan>" cc:
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/16/01
03:04 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi, Rudy,
The boards are ENIG finished, the ENIG plating being carried out
post-solder-mask, which must be after final copper etch, so No, there is no
other metal in the area, unless my understanding of the plating/etching
sequence is all wrong. My understanding (faulty or otherwise) of what the
fab house has done, is that they laminate, drill and plate the layers with
the first suite of blind vias, then laminate, drill and plate for the
second suite of blind vias, then again for the 3rd suite until everything
is stacked up, pressed, drilled and plated for the through-holes. I haven't
quite been able to make sense of it all yet, but I think what I'm being
told is that the plating becomes "stepped" somehow. I have 3 sets of blind
vias from each outer surface (for ease of argument), making 4 plating
sessions on each side by the time the through-hole group is done. The first
areas to be drilled and plated are therefore plated 4 times, while the last
areas to be drilled are only plated once, with the groups in between
getting their proportional share of multiple plating.
Thus at final etch, there is, I am told, a compromise to be reached - how
to achieve the correct widths and spacings on the heavily plated areas
without over-etching the lightly-plated areas. In my simple way, I would
have expected the entire board surface to have an even plating thickness,
however thick, but seemingly not. The compromise hasn't worked for the
number of blind via groups featured in this board, and I need to try to
find out how to address a solution without solely relying on what our fab
house tells me.
In my entire life, I never had to worry about the processes involved in
fabricating PCB's - only that components could be soldered to them, that
they passed test and proved to be reliable in the field. I only ever worked
with good boards - the ones that passed in-coming inspection - in an
assembly environment, so my experience of board design and PCB fab is
limited to the past 8 or 9 months, in a company that has no previous
convictions for designing this type of board, so it's a case of the blind
leading the blind to a certain extent.
Any further help in this area would be greatly appreciated.
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch
ORG>
11/16/01
02:13 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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Date: Fri, 16 Nov 2001 07:53:22 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wildes, Earl" <[log in to unmask]>
Subject: handling single parts
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi there. I sent this out once before, but it might have bounced.
Is there any guideline or procedure detailing how to handle single surface
mount parts, especially fine pitch. I've found several on moisture and ESD,
but none on re-packaging. Our production numbers are rather low, so it is
not always best to issue the whole tray of parts to the board shop. We need
a document to teach the stockroom personnel how to pick up and package
individual parts without bending the leads.
Thanks for your help.
Earl Wildes
Sr. Component Engineer
Korry Electronics Co.
901 Dexter Ave N.
Seattle, WA 98109
206-694-1398
[log in to unmask]
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Date: Fri, 16 Nov 2001 10:02:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Donaldson <[log in to unmask]>
Subject: Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two small wires
to a PWB assembly while we are reflow soldering the other SMT parts to the
board. So far we have not found a wire type that a manufacturer will ensure
will survive the reflow temperatures. Solid wire with insulation is needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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Date: Fri, 16 Nov 2001 16:39:12 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: solderability
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solderabilityShine Wang
I can. Let me have your mailing and emailing details and I will forward the
info to you directly.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk
For instant access to Product Data Sheets register on the Tech-Shot area of
http://www.concoat.co.uk
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Shine Wang-0337CE
Sent: Friday, November 16, 2001 07:37
To: [log in to unmask]
Subject: [TN] solderability
who can tell me about how to do a solderability test?
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<HTML><HEAD><TITLE>solderability</TITLE>
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http-equiv=3DContent-Type>
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<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D070093716-16112001><STRONG>Shine =
Wang</STRONG></SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D070093716-16112001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D070093716-16112001><STRONG>I can. Let me have your mailing and =
emailing=20
details and I will forward the info to you=20
directly.</STRONG></SPAN></FONT></DIV>
<DIV> </DIV>
<P><FONT face=3DArial size=3D2><STRONG>Regards, Graham=20
Naisbitt<BR><BR>[log in to unmask]<BR></STRONG><A=20
href=3D"http://www.concoat.co.uk/"><STRONG>www.concoat.co.uk</STRONG></A>=
</FONT></P>
<DIV><FONT face=3DArial size=3D2>For instant access to Product Data =
Sheets register=20
on the Tech-Shot area of http://<A=20
href=3D"http://www.concoat.co.uk/">www.concoat.co.uk</A> </FONT></DIV>
<DIV><BR><FONT face=3DArial size=3D2><STRONG>Concoat=20
Limited =
<BR>Alasan=20
House, Albany Park<BR>CAMBERLEY GU16 7PH UK<BR>Phone: +44 (0)1276 =
691100<BR>Fax:=20
+44 (0)1276 691227<BR>Mobile: +44 (0)79 6858 2121 </STRONG></FONT></DIV>
<DIV> </DIV>
<DIV><B><FONT size=3D2>
<P> </P></B></FONT></DIV>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Shine =
Wang-0337CE<BR><B>Sent:</B>=20
Friday, November 16, 2001 07:37<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] =
solderability<BR><BR></DIV></FONT><!-- Converted from text/rtf format =
-->
<P><FONT face=3DArial size=3D2>who can tell me about how to do a =
solderability=20
test?</FONT> </P></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 16 Nov 2001 16:45:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Conformal Coating to IPC Class 3
In-Reply-To: <[log in to unmask]>
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Mike
Following on from Doug's response, I have customers in 2 camps:
#1 : "We require the coating to be under low stand-off devices but with no
filleting. So we apply a thinned dip coat first, and then top-off with a
proper spray coat"
#2 : "We want no coating under the components so we only dip with high
viscosity material"
I guess the issue they have concern about is TCE mis-match, however the
coating SHOULD be forgiving in this sense. Silicones, as I learnt from Brian
Ellis, are not suitable for such requirements/applications.
If you want to ensure that all the solder joints are protected under a BGA,
my suggestion is to dip coat. This may well cause you major problems with
component masking, but is the only easy way to get the coating penetration
under such devices.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Manwell
Sent: Friday, November 16, 2001 12:15
To: [log in to unmask]
Subject: [TN] Conformal Coating to IPC Class 3
When I read IPC Standards regarding conformal coating requirements for the
different classes, all I can find is coating thickness on a board.
I'm trying to work to class 3 standards for conformal coating and am
meeting those thickness requirements, however, I have to wonder how it
works on a BGA for example, where the coating thickness is sufficient but
doesn't completely cover and encapsulate the component. In other words,
there is a gap between the top of the BGA and the PCB.
Any thoughts on this would be appreciated.
Thanks,
Mike Manwell
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Date: Fri, 16 Nov 2001 11:52:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
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What about using Teflon insulated wires?
-----Original Message-----
From: Bob Donaldson [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 11:03 AM
To: [log in to unmask]
Subject: [TN] Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two small
wires
to a PWB assembly while we are reflow soldering the other SMT parts to
the
board. So far we have not found a wire type that a manufacturer will
ensure
will survive the reflow temperatures. Solid wire with insulation is
needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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Date: Fri, 16 Nov 2001 11:21:01 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: solderability
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Hi! I recommend you look at the IPC JSTD 002A specification for component
solderability and the IPC JSTD 003 specification for printed wiring board
solderability.
Dave Hillman
002A/003 Committee Chairman
[log in to unmask]
Shine Wang-0337CE <[log in to unmask]>@ipc.org> on 11/16/2001 01:37:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] solderability
who can tell me about how to do a solderability test?
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Date: Fri, 16 Nov 2001 09:24:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Land size for wave soldering
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Hi ALll,
Should the land size be different for wave soldering? Suggestions are
appreciated.
Is there a standard glue dot size?
Thanks,
Patrick
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Date: Fri, 16 Nov 2001 12:30:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
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Hi Bob,
I've reflowed a lot of air and core wound inductors that are made with
magnet wire that has polyimide (type ML) insulation. This is straight =
from
the spec sheet "ML is a film coated magnet wire made with polyimide =
resin.
It is a Class 220=B0C thermal life insulation with exceptional =
resistance to
chemical solvents and burnout. It will operate at temperatures up to =
240=B0C.
The outstanding cut-thru of over 400=B0C and its ability to withstand
excessiver overloads extends the use of magnet wire in extreme =
conditions.
ML is unaffected by prolonged exposure to varnish solvents and is =
compatible
with virtually all systems."=20
There are multiple mfr's but MWS Wire Industries (www.mwswire.com) is =
one
that I use the most.
Steve Sauer
Mfg Engineer
Xetron Corporation
-----Original Message-----
We have a application where it would be very nice to solder two small =
wires
to a PWB assembly while we are reflow soldering the other SMT parts to =
the
board. So far we have not found a wire type that a manufacturer will =
ensure
will survive the reflow temperatures. Solid wire with insulation is =
needed
in the 22-24 awg. size. Does anybody have experience soldering wires to
assemblies in reflow processes?
---------------------------------------------------------------------------------
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Date: Fri, 16 Nov 2001 09:48:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Soldering wires to PWB with SMT Reflow process
X-To: Bob Donaldson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bob,
I have had good results with Teflon and I-PVC insulated wires in a
reflow application. We even wave soldered a few applications. (sub-merged)
Through testing I found we could a use pin-in-paste method and the
insulation held up well. If you are doing a Pb-free reflow, there may be
issues, as the temps are higher than SnPb.
Do some testing, with TC's attached to the wires. You may be
surprised to see the results.
Good Luck,
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Bob Donaldson [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 8:03 AM
To: [log in to unmask]
Subject: [TN] Soldering wires to PWB with SMT Reflow process
To All,
We have a application where it would be very nice to solder two
small wires
to a PWB assembly while we are reflow soldering the other SMT parts
to the
board. So far we have not found a wire type that a manufacturer will
ensure
will survive the reflow temperatures. Solid wire with insulation is
needed
in the 22-24 awg. size. Does anybody have experience soldering wires
to
assemblies in reflow processes?
Any leads would be appreciated.
Thanks,
Bob Donaldson
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Date: Fri, 16 Nov 2001 17:58:30 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
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We have experienced voiding with via in pad, I know it ws stated that =
the pads don't have vias in them but if they did they can somtimes gass =
through the plating, its not the air traped by the paste. I have =
investigated this with my old outgassing oil test which showes up the =
problem and will contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Peter George [log in to unmask]
To: [log in to unmask]
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder =
joints
were discussed at some length. The received wisdom is that voids in =
solder
joints are not of themselves a 'defect' unless they break out through =
the
side of the ball. In fact, they make the joint more "flexible" - =
better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste =
flux
during the reflow process, though the size and shape of voids =
increases and
changes when there are via-in-pad features as well. About the only way =
to
detect them is by X-ray, and to judge from previous TechNet postings, =
there
are some pretty fancy machines around now that can give you a very =
much
clearer view of the balls than is normally the case ... if you have =
cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN =
Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to =
as high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right =
at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on =
pad.
Does anyone know the possible reasons for voids formation in BGA =
(micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are =
not the
intended recipient, please delete it and notify us immediately; you =
should
not copy or use it for any purpose, nor disclose its contents to any =
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<META content=3D"text/html; charset=3Diso-2022-jp" =
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>We have experienced voiding with via in =
pad, I know=20
it ws stated that the pads don't have vias in them but if they did they =
can=20
somtimes gass through the plating, its not the air traped by the paste. =
I have=20
investigated this with my old outgassing oil test which showes up the =
problem=20
and will contribute to voiding.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:Peter George [log in to unmask]"=20
title=3D"Peter George [log in to unmask]">Peter George=20
[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, November 16, 2001 =
8:52=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] BGA =
voids</DIV>
<DIV><BR></DIV>Hi, Peter,<BR><BR>I was at a seminar earlier this year =
where=20
BGA's and their solder joints<BR>were discussed at some length. The =
received=20
wisdom is that voids in solder<BR>joints are not of themselves a =
'defect'=20
unless they break out through the<BR>side of the ball. In fact, they =
make the=20
joint more "flexible" - better<BR>able to withstand creep fatigue - so =
are=20
beneficial, up to a point.<BR><BR>What causes them is often outgassing =
of=20
volatiles in the solder paste flux<BR>during the reflow process, =
though the=20
size and shape of voids increases and<BR>changes when there are =
via-in-pad=20
features as well. About the only way to<BR>detect them is by X-ray, =
and to=20
judge from previous TechNet postings, there<BR>are some pretty fancy =
machines=20
around now that can give you a very much<BR>clearer view of the balls =
than is=20
normally the case ... if you have cash to<BR>splash!<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
Peter=20
=
Lee<BR> =
=20
<ppwlee@YAHOO =20
To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR> =
&=
nbsp; =20
=
.COM>  =
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cc: (bcc: DUNCAN Peter/Asst Prin=20
=
Engr/ST<BR> &n=
bsp; =20
Sent=20
=
by: &nbs=
p;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
=
TechNet =
=20
Subject: [TN] BGA=20
=
voids<BR> &nbs=
p; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/16/01<BR> &=
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PM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
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E-Mail<BR> &nb=
sp; =20
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am=20
encountering voids after reflow on several micro BGAs on one =
PCA<BR>product.=20
The voids that I $B!G (Bve observed (with Xray) contribute to as high=20
as<BR>60-70% of the joint area. My reflow profile was designed by =
running=20
a<BR>sample board with dummy components and thermalcouples attached =
right at=20
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see any =
via on=20
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for =
voids=20
formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, =
in step=20
by step how would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
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Date: Fri, 16 Nov 2001 12:17:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Intermetallic Layers
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! Intermetallic layers are alloys (at least per the ASMI definition
of an "alloy") but that is another discussion topic. Eric - take a look
section 6.5.5 in the book : The Mechanics of Solder Alloy Wetting &
Spreading, ISBN 0-442-01752-9. Several very controlled experiments have
been conducted by Dr. Tench showing what happens with the Cu3Sn and Cu6Sn5
IMCs. The data shows that the Cu3Sn oxidizes in only 10 minutes and is
very unsolderable. Also check out the information in Soldering In
Electronics, Klein Wassink, ISBN0-901150-14-2, section 4.2.5.3 which
discusses oxidation and Cu/Sn IMCs. The key looks to be which intermetallic
is present - a good deal of the published data I have been reading defines
the "bad" IMC as the Cu3Sn. The consensus trends to the Cu6Sn5 IMC as the
IMC the fluxes can deal with. The SERA testing I have participated in also
trends the same direction. Did you identify the which of the Cu/Sn IMCs
were on your samples? If the IMC was Cu6Sn5 then that would fit the
literature trend. George's ideal of the diffusion kinetics is another
possible detail which may play a part - I am pretty well versed in Sn
oxidation because of my master thesis but the kinetics of copper/tin I need
to do some reading. One interesting point from George's idea - Sn
preferentially oxidizes at the expense of Pb on a tin/lead surface so I
would guess that the copper/tin diffusion kinetics are playing a role too.
Take a look at those references and let me know what you think - oxidation
and IMCs - wonderful discussion topics.
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 11/14/2001 02:59:20 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Intermetallic Layers
Hi George,
One pertinent point here is that the intermetallic layers are compounds not
alloys. Thus their oxidising and other chemical reactions will probably be
different from those of their constituent metals.
The surface activation energies may be the key, can you give me references
please George? I would like to follow them up. (See my other reply!)
One point though, I would expect the copper rich compound to lie adjacent
to
the copper interface and the copper deficient one next to the solder
interface. My microsections after solder etching showed that the normally
visible two layers were still present, so I must have been soldering the
copper deficient layer, which, as you say, is the easiest one to solder.
Also, since the melting points of these compounds are higher than soldering
temperatures we would always be soldering to the copper deficient layer. Or
are we? So, open question, can the copper deficient, aka easily solderable,
compound turn into a copper rich layer. Has anybody reading this discussion
got access to a well equipped laboratory?
Regards
Eric Dawson
> -----Original Message-----
> From: Franck, George [SMTP:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 7:20 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
> During my PWB education I learned that there are at least three "alloys"
> of
> copper and tin that are formed as the Copper diffuses into the solder.
> The
> first alloy formed (and I don't remember the ratios) has the highest tin
> to
> copper ratio, and has surface activation energies within the range of
most
> fluxes. Therefore, this first tin copper alloy, or IMC, is solderable.
> All
> the others alloys, with higher amounts of copper in them, are not.
>
> Activation energies reflect how strongly attached the Oxygen atom are on
> the
> surface of the metal. The more copper on the surface alloy, the tighter
> the
> oxygen is attached, the stronger the flux needed to break the oxygen from
> the surface.
>
> While the copper is diffusing into the Solder, the Tin is also diffusing
> into the copper surface, lowering the % tin in the solder alloy, which
> raises the melt temperature of the remaining solder. It is all quite an
> interesting solid state diffusion system. By the way, for all intents
and
> purposes, the lead is just too big (physical size of the atom) to
> participate in this diffusion system much, except to get in the way.
>
> It is possible that Eric only exposed the "solderable" tin-copper
> intermetallic in his tests, i.e. the one with the least amount of copper
> in
> it.
>
> What was the magic chemical I played with in my old PWB shop to make
> boards
> solderable, Thiourea hydrochloride? Wasn't that the active chemical in
> Tarnex also?
>
> George Franck, CID+
> who recalls his "PWB as Black Magic" roots.
>
> --------------------
> Disclaimers:
> 1) If Dave Hillman says I am wrong, then I probably am.
> 2) My company will neither confirm nor deny the existence of any of my
> opinions.
> 3) Tin-copper alloys are commonly referred to as Bronze.
>
> -----Original Message-----
> From: David Hillman [mailto:[log in to unmask]]
> Sent: Tuesday, November 13, 2001 12:25 PM
> To: [log in to unmask]
> Subject: Re: [TN] Intermetallic Layers
>
>
> Hi Eric! Sorry but I humbly disagree. There is an abundance of published
> industry data which shows that oxidized Sn/Cu intermetallic is one of the
> more unsolderable surfaces encountered on an assembly. Problems with poor
> plated thru hole fill due to "weak knees" (thin solder causes the Sn/Cu
> intermetallic at the hole rim to become oxidized) and thin HASL coatings
> are just two examples of everyday industry solderability issues
associated
> with Sn/Cu IMCs. What type of flux did you use in your testing? Very
> aggressive flux chemistries will allow the soldering of Sn/Cu IMCs but a
> fair majority of the industry is moving away from these types of flux
> formulations. With all that being said, without the Sn/Cu IMC we would
> have
> no solder joints so it is a critical part of a solder joint.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 11/12/2001 07:49:56 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [TN] Intermetallic Layers
>
>
> Hi All,
>
> I notice that a few new references have been made to the above subject
and
> thought I would share some of my early work with you.
>
> In my first post as a graduate, I researched the causes of dewetting on
> circuit boards. I came across a solution, the make-up of which I have
> since
> lost, which dissolved the tin lead alloy but left the two intermetallic
> layers.
>
> I produced a number of one inch square coupons which I soldered using
> 63/37
> alloy, RMA flux and a Tri Moore Rotary Dip Tester.
>
> These were divided into three categories:
>
> 1 Control
> 2 Remove tin lead and re test in the Rotary Dip.
> 3 Remove tin lead, Several hours steam ageing and re test.
>
> Microsections showed that I had taken off the alloy successfully and left
> the IMC.s.
>
> All of the re tested coupons soldered successfully, including the steam
> aged
> ones.
>
> This was some years ago so I cannot remember the etchant nor the hours
and
> conditions in the steam ageing equipment. I do remember that the IMC
> soldered very well so I am always dubious when somebody blames the
> intermetallic for poor soldering.
>
> I seem to be alone in my faith that the IMC solders but this was the
> result
> of my very own work and I stand by it.
>
> Regards
> Eric Dawson, Defender of the IMC.
>
>
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Date: Fri, 16 Nov 2001 13:24:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
Earl -
I agree that many shops do not do well with the more exotic laminates, but
we can not let that determine our choices. BT epoxy is better than FR4 in
some ways but it is still not up to performance standards needed to play in
the 1GHz *clock* range which necessitates a sub .5 nanosecond rise time for
signals. The loss tangent is the limiting factor for BT, with a range of
0.015-0.022 it is still to high for these designs. PPO's lower this
somewhat, 0.01-0.015, and are "flatter" in the Er curve with regard to
frequency. Cynate Ester maybe an answer to the problems, but when it comes
to cost vs. functionality the hands down winner is the ceramic-filled, glass
reinforced thermoset plastics (Rogers 4003/4350 and the like). Hopefully
the commercial fabricators will catch up with the prototype houses in
delivering quality product in the more "bleeding" edge materials.
None of this is meant to say that FR4 can not be used in
high-speed/high-frequency design just that it is easier to get the
performance from other products. I have seen/heard of/worked on designs in
the 2+ GHz range on multilayer FR4 laminates. These can/do work but design
becomes super-critical, and it is not a simple place and autoroute routine.
Not all designer or engineers understand the parameters and attention to
detail required to make it work.
Jeffrey
[log in to unmask]
4-7582
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 9:04 AM
To: [log in to unmask]
Subject: Re: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Jeffery,
I certainly apreciate your posting as a reminder to me as well. I would add,
from a DFM point of view concerning materials and their processing:
Getek has good electrical properties, as you say, but processing and some
results associated with it can be dissapointing. This material must be
processed more along the lines of polyimide. It requires a more damanding
press cycle than those for FR4 types using simple straight up processing
from 0 to 90 minutes or so. Therefore, not all shops like or do well with
it.
The Rogers and Arlon (liscensed from Rogers but with slight variations
concerning properties) material is really neat stuff. It has processing
drawbacks as well as being limited in prepreg glass styles and thicknesses
when reinforced. If improperly processed, as with any material type, it has
several failing characteristics. As is widely known, this type material
often is married/laminated to Getek to meet design and performance
requirements. Really low DC and loss tangents.
My money is on BT epoxy blends when and where possible. It has high
performance characteristics and is easily processed. I have designed it in
and used in in very complex, large, high layer count MLB's with great
success. It is/was used in some Cray designs built by IBM, as one example.
Just wanted to add to your good comments,
MoonMan
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Date: Fri, 16 Nov 2001 13:13:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeff,
I agree with most all you say. Just can't buy the thought of not considering
who and who cannot work with what materials. To ignore this is violating one
of many important rules of DFM/CE. The very high speed requirements, as in
Jim Marsico's pending designs, certainly demand high performance, exotic
materials. Not having a highly qualified supplier puts these requirements in
great jeopardy. Of course, this should not be the case for Jim - should it Jim?
I certainly agree with your technical assessment of material performance
properties. Some other physical properties simply add to the extent of the
compromise.
I started working with Arlon's CLTE material, I belive in 1997, before
Rogers had its own treaters and presses to make this type prepreg and core
material (though they own the patents for it), respectively, and had mixed
results. It must be said, that in the begining, there were but two or three
shops capable of successfully processing CLTE. It must also be said that
material was hard to come by and deliveries were slow.
Now, Rogers is making its prepreg and core as well, so deliveries and
material consistency is much better though the glass styles still (typically
106, or there abouts, glass styles) can cause issues especially when thicker
layer structures are needed. However, most high speed dielectric thicknesses
are in the 4 to 6 mil range so this is not such a big problem. Also, there
are fab shops more capable of managing their processes properly and ensuring
some initial "defects" I found do not occur. Initial defects, and currently
potential types, consisted of very low foil and innerlaminar bond strengths
as well as some a little wierd looking like "mush" on the surface layers.
In agreeing with most all you say, part of that means compromise always is a
factor in any design. The compromises here are, as always, design rules,
materials selections based on design need, fabrication process capabilities,
and assembly process capabilities.
What ultimately must come out of all this is quality, and reliability - over
a long performance period, meeting clearly specified contract requirements.
Other factors must enter the equation as well and, of course, are
availability, delivery, and cost.
DFM/CE, when properly practiced, ensures all this is taken into
consideration. Many other issues must be considered at the design level as
well. Plated holes, blind vias, buried vias, micro vias and the impact they
have on the critical, high speed equation and, again, reliabilty together
with specified performance. All this, and so much more, is part of the
designer's realm while working concurrently with everyone else on the DFM/CE
team as board fab and assembly process and manufacturing engineers
notwithstanding component engineers plus many others.
There's so much more for another discussion, but you say it well,
Earl
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Date: Fri, 16 Nov 2001 11:38:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Wong <[log in to unmask]>
Subject: Cab Maestro 2M blades
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charset="iso-8859-1"
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Has anyone bothered to sharpen their CAB Maestro blades or did you just =
order replacements? If so, who did you get the replacements from? We =
bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
------=_NextPart_000_010A_01C16E93.3381D880
Content-Type: text/html;
charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Has anyone bothered to sharpen their =
CAB Maestro=20
blades or did you just order replacements? If so, who did you get =
the=20
replacements from? We bought our 2M used and don't know of any =
local reps=20
in WA/OR.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Peter</FONT></DIV></BODY></HTML>
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Date: Fri, 16 Nov 2001 13:02:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Conformal Coating to IPC Class 3
MIME-Version: 1.0
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Doug,
"Conformal Coating - The Great Career Limiting Move"
May I use this for the title of my book! ;-)
David A. Douthit
Manager
LoCan LLC
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Date: Fri, 16 Nov 2001 13:54:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "Jeffrey A. McGlaughlin" <[log in to unmask]>
Jeff,
This is the part of you message I agree with most:
None of this is meant to say that FR4 can not be used in
high-speed/high-frequency design just that it is easier to get the
performance from other products. I have seen/heard of/worked on designs in
the 2+ GHz range on multilayer FR4 laminates. These can/do work but design
becomes super-critical, and it is not a simple place and autoroute routine.
Not all designer or engineers understand the parameters and attention to
detail required to make it work.
I especially mean the last sentence. Got some great stories to tell here.
Earl
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Date: Thu, 15 Nov 2001 07:30:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: conformal coating
MIME-Version: 1.0
Content-Type: text/plain
A few months ago someone (Mike) from Technet said that they would send me
info on a water soluble acrylic conformal coating that meets NASA outgassing
requirements. Would you please contact me off line?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 15 Nov 2001 07:53:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board materials (organic?) and
design that can handle clock speeds up to 1GHz? Or another question, what
aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Fri, 16 Nov 2001 08:33:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: PWB MATERIALS, DESIGNS AND TECHNOLOGY
X-To: "McGlaughlin, Jeffrey A" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jeff, thanks for the response... I'm sending this to you directly because
I'm having trouble sending anything to IPC. (Maybe this will get through,
who knows!)
What about PWB design/fab techniques. Does thinner lines, microvias, buried
vias, embedded discretes, etc. affect signal speed? What about a 'power
mesh architecture' technology?
We're presently in production with a polyimide multilayer PWB which has an
MCM at 560 MHz. We think we're pushing the limit. Our next generation
designs might be up to I gig... I'm looking for board materials, designs,
etc. to accommodate.
Thanks again,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: McGlaughlin, Jeffrey A [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 8:15 AM
To: [log in to unmask]
Subject: Re: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Not having seen any other responses to this posting I will take a
*SWAG* at it.
1) The clock speed is not the most damning part of the "high speed
design" problem. Look at the rise time of the primary signals on the board
and convert that in to frequency. Your speed issue is probably much worse
than you think.
2) The material properties that you need to be concerned about are
the dielectric constant (variable for FR4) and the loss tangent. The loss
tangent of the material becomes especially important when working with low
level signals and narrow noise to signal ratios.
3) There are several levels of solution you can explore to get out
of FR4 and in to a more stable material. The first are the PPO materials
like GeTek. They are an epoxy-glass material with the resin being highly
modified, to improve electrical and temperature performance. Next there are
the co-laminates like Speedboard N and C, prepreg only, which are used to
create a better final laminated board. Next in line would be the more exotic
ceramic-filled thermoplastics like Roger's RO4003/4350 materials.
Good Luck
Jeffrey A. McGlaughlin CID
Sr. Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 10:43 AM
To: [log in to unmask]
Subject: [TN] PWB MATERIALS, DESIGNS AND TECHNOLOGY
Hey Steve, for some reason IPC can't receive my e-mails.
Could you post
this for me?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Marsico, James
Sent: Thursday, November 15, 2001 7:54 AM
To: 'Technet'
Subject: PWB MATERIALS, DESIGNS AND TECHNOLOGY
OK, here's another hi-tech topic...
What's the latest and greatest in multilayer board
materials
(organic?) and design that can handle clock speeds up to
1GHz? Or another
question, what aspects of the PWB affects signal speed?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask]
<mailto:[log in to unmask]>
631-595-5879
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Date: Fri, 16 Nov 2001 15:46:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Help me out with this technetters,
The problem: BGA opens on a HASL board.
The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
0.28mm.
Management's solution is to increase the pad size to 0.4mm. I say to look
elsewhere in the process for the problem.
I'd like to hear the opinions of my esteemed colleagues. What do you say folks?
Thanks in advance,
Tom
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Date: Fri, 16 Nov 2001 16:33:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Peter,
Symmetrical stack-up is crucial and I've seen a few designs where it just
couldn't be helped (impedance). Rapid or uncontrolled cool down during
lamination can also contribute to bow/twist in a balanced construction.
I've successfully used post lamination dewarp procedures similar to Jeff's
suggestion but that was for Class 2 stuff. The trick is making the dewarp
last through subsequent high temp. assembly steps (soldering).
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Fri, 16 Nov 2001 15:07:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Harinder Jassal <[log in to unmask]>
Subject: Re: Cab Maestro 2M blades
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Peter,
Contact Cab Technologies headquarters directly http://www.cabtechn.com/
<http://www.cabtechn.com/>
Harinder
-----Original Message-----
From: Peter Wong [mailto:[log in to unmask]]
Sent: Friday, November 16, 2001 11:38 AM
To: [log in to unmask]
Subject: [TN] Cab Maestro 2M blades
Has anyone bothered to sharpen their CAB Maestro blades or did you just
order replacements? If so, who did you get the replacements from? We
bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
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<BODY bgColor=#ffffff>
<DIV><SPAN class=495280423-16112001><FONT face=Arial color=#0000ff
size=2>Peter,</FONT></SPAN></DIV>
<DIV><SPAN class=495280423-16112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=495280423-16112001><FONT face=Arial color=#0000ff
size=2>Contact Cab Technologies headquarters directly <A
href="http://www.cabtechn.com/">http://www.cabtechn.com/</A></FONT></SPAN></DIV>
<DIV><SPAN class=495280423-16112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=495280423-16112001><FONT face=Arial color=#0000ff
size=2>Harinder</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Peter Wong
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, November 16, 2001 11:38
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Cab Maestro 2M
blades<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Has anyone bothered to sharpen their CAB Maestro
blades or did you just order replacements? If so, who did you get the
replacements from? We bought our 2M used and don't know of any local
reps in WA/OR.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Thanks</FONT></DIV>
<DIV><FONT face=Arial
size=2>Peter</FONT></DIV>---------------------------------------------------------------------------------
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Date: Fri, 16 Nov 2001 17:05:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Cab Maestro 2M blades
X-To: Peter Wong <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
We did both. Sharpened the old and purchased new form CAB (costly).
Sharpening will work until you hit the end of the adjustment slots.
I don't currently know of any after-market parts.
Hope that helps.
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Peter Wong [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 11:38 AM
To: [log in to unmask]
Subject: [TN] Cab Maestro 2M blades
Has anyone bothered to sharpen their CAB Maestro blades or did you
just order replacements? If so, who did you get the replacements from? We
bought our 2M used and don't know of any local reps in WA/OR.
Thanks
Peter
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Date: Sat, 17 Nov 2001 10:15:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: solderability
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charset="us-ascii"
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Graham Naisbitt,
I am Tony ,shine 's college I am sorry to tell that Shine is
sick now and you can forward the information to the address
[log in to unmask] and pls cc to [log in to unmask]
Thanks for your help
Tony Zhang
Process Engineer=20
Hangzhou Motorola=20
> -----Original Message-----
> From: Graham Naisbitt [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 4:39 PM
> To: [log in to unmask]
> Subject: Re: [TN] solderability
>=20
> Shine Wang
> =20
> I can. Let me have your mailing and emailing details and I will
> forward the info to you directly.
> =20
>=20
> Regards, Graham Naisbitt
>=20
> [log in to unmask]
> www.concoat.co.uk <http://www.concoat.co.uk/>
>=20
> For instant access to Product Data Sheets register on the Tech-Shot
> area of http://www.concoat.co.uk <http://www.concoat.co.uk/>=20
>=20
> Concoat Limited =20
> Alasan House, Albany Park
> CAMBERLEY GU16 7PH UK
> Phone: +44 (0)1276 691100
> Fax: +44 (0)1276 691227
> Mobile: +44 (0)79 6858 2121=20
> =20
> =20
>=20
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Shine
> Wang-0337CE
> Sent: Friday, November 16, 2001 07:37
> To: [log in to unmask]
> Subject: [TN] solderability
> =09
> =09
>=20
> who can tell me about how to do a solderability test?=20
>=20
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<TITLE>RE: Re: [TN] solderability</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<P><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 FACE=3D"Arial">Graham =
Naisbitt,</FONT></B></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Arial"> </FONT></B> <FONT =
COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">I am Tony ,shine 's =
college I am sorry to tell that Shine is sick now and you can =
forward the information to the address [log in to unmask] and pls cc =
to [log in to unmask]</FONT></SPAN></P>
<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">Thanks for your help</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Tahoma">Tony =
Zhang</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Tahoma">Process Engineer =
</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Tahoma">Hangzhou =
Motorola</FONT> </SPAN>
</P>
<BR>
<BR>
<UL>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D1 FACE=3D"Arial">-----Original =
Message-----</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">From: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Graham Naisbitt =
[SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Sent: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Friday, November 16, 2001 4:39 PM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Subject: </FONT><=
/B> <FONT SIZE=3D1 FACE=3D"Arial"> Re: [TN] =
solderability</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><B><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Arial">Shine Wang</FONT></B></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT FACE=3D"Arial">=A0</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Arial">I can. Let me have your mailing and emailing details and =
I will forward the info to you directly.</FONT></B></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT FACE=3D"Arial">=A0</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 FACE=3D"Arial">Regards, Graham =
Naisbitt<BR>
<BR>
[log in to unmask]<BR>
</FONT></B><FONT SIZE=3D2 FACE=3D"Arial">www.concoat.co.uk =
<<U></U></FONT><U><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial"><A =
HREF=3D"http://www.concoat.co.uk/">http://www.concoat.co.uk/</A></FONT></=
U><FONT SIZE=3D2 FACE=3D"Arial">></FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">For instant access =
to Product Data Sheets register on the Tech-Shot area of</FONT><U> <FONT =
COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial"><A =
HREF=3D"http://www.concoat.co.uk">http://www.concoat.co.uk</A> <<A =
HREF=3D"http://www.concoat.co.uk/">http://www.concoat.co.uk/</A>></FON=
T></U><FONT SIZE=3D2 FACE=3D"Arial"></FONT> </SPAN></P>
<P><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 FACE=3D"Arial">Concoat =
Limited=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0<BR>
Alasan House, Albany Park<BR>
CAMBERLEY GU16 7PH UK<BR>
Phone: +44 (0)1276 691100<BR>
Fax: +44 (0)1276 691227<BR>
Mobile: +44 (0)79 6858 2121</FONT></B> </SPAN>
<BR><SPAN LANG=3D"en-us"><FONT FACE=3D"Arial">=A0</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D2 =
FACE=3D"Arial">=A0</FONT></B></SPAN>
</P>
<UL>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Tahoma">-----Original =
Message-----<BR>
</FONT><B><FONT SIZE=3D2 FACE=3D"Tahoma">From:</FONT></B><FONT SIZE=3D2 =
FACE=3D"Tahoma"> TechNet [</FONT><U><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Tahoma"><A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT></U><U>=
<B><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Tahoma">On</FONT></B></U><B><FONT SIZE=3D2 FACE=3D"Tahoma"> =
Behalf Of</FONT></B> <FONT SIZE=3D2 FACE=3D"Tahoma">Shine =
Wang-0337CE<BR>
</FONT><B><FONT SIZE=3D2 FACE=3D"Tahoma">Sent:</FONT></B><FONT SIZE=3D2 =
FACE=3D"Tahoma"> Friday, November 16, 2001 07:37<BR>
</FONT><B><FONT SIZE=3D2 FACE=3D"Tahoma">To:</FONT></B><FONT SIZE=3D2 =
FACE=3D"Tahoma"> [log in to unmask]<BR>
</FONT><B><FONT SIZE=3D2 FACE=3D"Tahoma">Subject:</FONT></B><FONT =
SIZE=3D2 FACE=3D"Tahoma"> [TN] solderability<BR>
<BR>
</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">who can tell me =
about how to do a solderability test?</FONT><FONT FACE=3D"Arial"> =
</FONT></SPAN>
</P>
</UL></UL>
</BODY>
</HTML>
------_=_NextPart_001_01C16F0D.C35E9670--
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Date: Fri, 16 Nov 2001 21:41:03 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
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Date: Sat, 17 Nov 2001 08:43:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
awarding business on the basis of price tag. Instead, minimize total cost.
Move toward a single supplier for any one item, on a long-term
relationship of loyalty and trust." Lou Hart
-----Original Message-----
From: Stephen R. Gregory [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 9:41 PM
To: [log in to unmask]
Subject: [TN] E-Business auctions for EMS providers...
Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty
closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any
of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
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Date: Sat, 17 Nov 2001 09:07:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles McMahon <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
I support Lou's contribution to the e-business auction discussion.
As a proponent of W. Edwards Deming's 14 points of management, I am
gratified to see there are others in the US (I think Lou is US based) who
believe in his teachings. I carry the 14 points with me on calls to
clients to provide a continuous reminder of the added
value we all hope to provide those whom we supply.
The reality is it takes more effort on behalf of the manufacturing world
that they are willing to expend to become more profitable. If we all
followed the principals.
the benefits would be proven by empirical data and increased profitability.
There appears to be little interest however.
Even though the results would be, in my view , demonstrably superior and
profitable as compared to the current paradigm, the only issue that
matters to the customer is can we built it for less v. (my view), can we
help you design it so that we can THEN build it for less.
As an advocate for co-operative engineering, I can only aspire to the
hope that more will move in this direction in order to meet the global
competive challenge.
Steve....ignore the auction.. Leave it for those unwilling to do the
work needed to build a successful product. They won't survive anyway.
Charlie McMahon
Lou Hart wrote:
>Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
>awarding business on the basis of price tag. Instead, minimize total cost.
> Move toward a single supplier for any one item, on a long-term
>relationship of loyalty and trust." Lou Hart
>
>-----Original Message-----
>From: Stephen R. Gregory [SMTP:[log in to unmask]]
>Sent: Friday, November 16, 2001 9:41 PM
>To: [log in to unmask]
>Subject: [TN] E-Business auctions for EMS providers...
>
>Hey all,
>
>Today, just learned about E-Business auctions for contracts for work in the
>EMS industry. It's been going on for a little while I guess, but I just
>learned about it today...new stuff for me...
>
>Watched how different companies were bidding for work from a OEM...I have
>mixed feelings about this. It was for work that we looked at pretty
>closely,
>priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
>be competitive, but make a fair profit...
>
>I just learned about this, and watched for a bit how things went (this was
>all real-time), companies were bidding lower and lower, fighting each
>other...making bids for the business that would cut into the profit margins
>that was originally quoted...
>
>I guess this is the future of significant orders for us EMS guys, have any
>of
>you been involved with this?
>
>What are your thoughts? Just curious?
>
>-Steve Gregory-
>
>------------------------------------------------------------------------
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>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
>
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=========================================================================
Date: Sat, 17 Nov 2001 11:02:45 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
X-To: "Stephen R. Gregory" <[log in to unmask]>
Couple of years ago appeared an online auction for independent consultants.
Might still be ghere, who cares. Just saw an on line auction for contract
employes. This observation and yours shows a sign of the times.
Right now, anything is fair game for auctioneers. Like EMS work, contract
hourly rates, and consulting rates are down the tubes but for the good guys.
No big deal this phenomonon. The economy, however, is.
MoonMan
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Date: Sat, 17 Nov 2001 17:07:55 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
I couldn't agree more with Lou's view, but would question why all the large
OEMs who compete for the Demming award (including among others, Motorola),
send all their production offshore, where the low labour cost is the
driving force, and quality is enforced. The European PCB industry has been
decimated by the global telecomms full stop, but when the business comes
back it will be made in China. Why? Not for quality, but purely for low
PRICE. The E-auction is a buyers dream - keep screwing the price until it
goes no lower, THEN impose horrendous contract conditions just to guarantee
that the poor supplier goes bust. We are all guilty of wanting everything
free, perfect and now, but until we change our attitude and put a VALUE,
not a price on what we buy, the current third world countries (China) will
become first order countries, and the US and Europe will become 3rd rate
economies.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Lou Hart [SMTP:[log in to unmask]]
Sent: 17 November 2001 13:43
To: [log in to unmask]
Subject: Re: [TN] E-Business auctions for EMS providers...
Steve, I'm reminded of #4 of Deming's 14 points. "End the practice of
awarding business on the basis of price tag. Instead, minimize total cost.
Move toward a single supplier for any one item, on a long-term
relationship of loyalty and trust." Lou Hart
-----Original Message-----
From: Stephen R. Gregory [SMTP:[log in to unmask]]
Sent: Friday, November 16, 2001 9:41 PM
To: [log in to unmask]
Subject: [TN] E-Business auctions for EMS providers...
Hey all,
Today, just learned about E-Business auctions for contracts for work in the
EMS industry. It's been going on for a little while I guess, but I just
learned about it today...new stuff for me...
Watched how different companies were bidding for work from a OEM...I have
mixed feelings about this. It was for work that we looked at pretty
closely,
priced the BOM (it's turn-key), and looked at labor pretty close. Wanted to
be competitive, but make a fair profit...
I just learned about this, and watched for a bit how things went (this was
all real-time), companies were bidding lower and lower, fighting each
other...making bids for the business that would cut into the profit margins
that was originally quoted...
I guess this is the future of significant orders for us EMS guys, have any
of
you been involved with this?
What are your thoughts? Just curious?
-Steve Gregory-
------------------------------------------------------------------------
---------
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=========================================================================
Date: Sat, 17 Nov 2001 23:02:00 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: conformal coating
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Jim
It twas I!
But, I did not say that it meets NASA outgassing, but that we think it
might. You should have received samples by now, maybe locked-up in customs
since Sep 11th? I will send more.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Thursday, November 15, 2001 12:30
To: [log in to unmask]
Subject: [TN] conformal coating
A few months ago someone (Mike) from Technet said that they would send me
info on a water soluble acrylic conformal coating that meets NASA outgassing
requirements. Would you please contact me off line?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Sun, 18 Nov 2001 09:08:05 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Peter,
Let me refrase your question from plating point of view since you rised =
1
milion dollar question:
How to plate the holes without plating the surface.
As far as I know,the best equipment,the best technologies,the best =
chemistry
etc have limitited capacity in terms of throwing capability ( ratio of =
metal
plated inside the hole to metal plated on the surface).The best figure =
is
slighty above 1.0 , usually is less than 1.0 .
No magic in this area:if the design requires to plate 3 times at least =
20
microns or so in the holes, the surface will get additional around 60 =
-70
microns of copper before plating and etching of the final pattern.
PCB designer should know this basic fact of life while imposing fancy
construction.
Of course PCB manufacturer has some possibilities to manipulate artwork
compensations according to copper thickness to be etched, but etching
factors are also fact of life.
There are some tricky ways,but most of them are not working well on HDI
boards with fine lines.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: =E5 =F0=E5=E1=EE=E1=F8 16 2001 10:04
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>=20
> Hi, Rudy,
>=20
> The boards are ENIG finished, the ENIG plating being carried out
> post-solder-mask, which must be after final copper etch, so No, there =
is
> no
> other metal in the area, unless my understanding of the =
plating/etching
> sequence is all wrong. My understanding (faulty or otherwise) of what =
the
> fab house has done, is that they laminate, drill and plate the layers =
with
> the first suite of blind vias, then laminate, drill and plate for =
the
> second suite of blind vias, then again for the 3rd suite until =
everything
> is stacked up, pressed, drilled and plated for the through-holes. I
> haven't
> quite been able to make sense of it all yet, but I think what I'm =
being
> told is that the plating becomes "stepped" somehow. I have 3 sets of =
blind
> vias from each outer surface (for ease of argument), making 4 plating
> sessions on each side by the time the through-hole group is done. The
> first
> areas to be drilled and plated are therefore plated 4 times, while =
the
> last
> areas to be drilled are only plated once, with the groups in between
> getting their proportional share of multiple plating.
>=20
> Thus at final etch, there is, I am told, a compromise to be reached - =
how
> to achieve the correct widths and spacings on the heavily plated =
areas
> without over-etching the lightly-plated areas. In my simple way, I =
would
> have expected the entire board surface to have an even plating =
thickness,
> however thick, but seemingly not. The compromise hasn't worked for =
the
> number of blind via groups featured in this board, and I need to try =
to
> find out how to address a solution without solely relying on what our =
fab
> house tells me.
>=20
> In my entire life, I never had to worry about the processes involved =
in
> fabricating PCB's - only that components could be soldered to them, =
that
> they passed test and proved to be reliable in the field. I only ever
> worked
> with good boards - the ones that passed in-coming inspection - in an
> assembly environment, so my experience of board design and PCB fab is
> limited to the past 8 or 9 months, in a company that has no previous
> convictions for designing this type of board, so it's a case of the =
blind
> leading the blind to a certain extent.
>=20
> Any further help in this area would be greatly appreciated.
>=20
> Best regards
>=20
> Peter Duncan
>=20
>=20
>=20
>=20
> "<Rudy
> Sedlak>" To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN =
Peter/Asst
> Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN] =
Over-etch
> ORG>
>=20
>=20
> 11/16/01
> 02:13 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>=20
>=20
>=20
>=20
>=20
>=20
> Peter:
>=20
> I am not sure if I fully understand the process you are using....so I =
am
> going to ask a dumb question, that may shed some light on the =
issue...
>=20
> Is there, anywhere in electrical contact with Copper being etched any
> other
> metal excepting Tin?
>=20
> This sort of thing, selective over-etch, is classically seen when =
there is
> some other metal, (Nickel, Gold, or???) than Tin in electrical =
contact
> with
> the over-etched Copper, and also in contact with the etchant.
>=20
> And if I am completely out in space with this question, please =
forgive the
> intrusion.
>=20
> Rudy Sedlak
>=20
> =
------------------------------------------------------------------------=
--
> -------
>=20
> Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d
> To unsubscribe, send a message to [log in to unmask] with following =
text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: =
SET
> Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & =
Databases >
> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700
> ext.5315
> =
------------------------------------------------------------------------=
--
> -------
>=20
>=20
>=20
>=20
>=20
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Date: Mon, 19 Nov 2001 10:49:56 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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Date: Mon, 19 Nov 2001 11:06:55 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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Date: Mon, 19 Nov 2001 11:30:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Thanks for your advice, Roger. I have looked into this already, but the
spacing available on the over-etched area isn't enough to widen the pads by
the 4 mils or so needed without winding up with a solid copper strip.
Will continue the quest!
Best regards
Peter Duncan
"Roger M. Stoops"
<rstoops@SPECTRAPRECISI To: [log in to unmask]
ONDAY.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Over-etch
11/16/01 11:28 PM
Please respond to
"TechNet E-Mail Forum."
Peter,
I'm probably out of my league here, but the board house may be able to
compensate somewhat with "etch compensation", adding copper width where the
most etching will take place. If you know you're going to lose 2 or 3 mils
[.05-.08mm] per side in the final etch, add on copper before the
lam/drill/plate processes to get what you want. Check with your supplier
to see if this would work. I know this doesn't help you with this board
now, but may fix future problems. Time for Tums...(or Rolaids, Ativan,
Guinness, etc.).
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
"<Peter
George To: [log in to unmask]
Duncan>" cc:
Sent by: Subject: Re: [TN] Over-etch
TechNet
<[log in to unmask]
ORG>
11/16/01
03:04 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi, Rudy,
The boards are ENIG finished, the ENIG plating being carried out
post-solder-mask, which must be after final copper etch, so No, there is no
other metal in the area, unless my understanding of the plating/etching
sequence is all wrong. My understanding (faulty or otherwise) of what the
fab house has done, is that they laminate, drill and plate the layers with
the first suite of blind vias, then laminate, drill and plate for the
second suite of blind vias, then again for the 3rd suite until everything
is stacked up, pressed, drilled and plated for the through-holes. I haven't
quite been able to make sense of it all yet, but I think what I'm being
told is that the plating becomes "stepped" somehow. I have 3 sets of blind
vias from each outer surface (for ease of argument), making 4 plating
sessions on each side by the time the through-hole group is done. The first
areas to be drilled and plated are therefore plated 4 times, while the last
areas to be drilled are only plated once, with the groups in between
getting their proportional share of multiple plating.
Thus at final etch, there is, I am told, a compromise to be reached - how
to achieve the correct widths and spacings on the heavily plated areas
without over-etching the lightly-plated areas. In my simple way, I would
have expected the entire board surface to have an even plating thickness,
however thick, but seemingly not. The compromise hasn't worked for the
number of blind via groups featured in this board, and I need to try to
find out how to address a solution without solely relying on what our fab
house tells me.
In my entire life, I never had to worry about the processes involved in
fabricating PCB's - only that components could be soldered to them, that
they passed test and proved to be reliable in the field. I only ever worked
with good boards - the ones that passed in-coming inspection - in an
assembly environment, so my experience of board design and PCB fab is
limited to the past 8 or 9 months, in a company that has no previous
convictions for designing this type of board, so it's a case of the blind
leading the blind to a certain extent.
Any further help in this area would be greatly appreciated.
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch
ORG>
11/16/01
02:13 PM
Please
respond to
"TechNet
E-Mail
Forum."
Peter:
I am not sure if I fully understand the process you are using....so I am
going to ask a dumb question, that may shed some light on the issue...
Is there, anywhere in electrical contact with Copper being etched any other
metal excepting Tin?
This sort of thing, selective over-etch, is classically seen when there is
some other metal, (Nickel, Gold, or???) than Tin in electrical contact with
the over-etched Copper, and also in contact with the etchant.
And if I am completely out in space with this question, please forgive the
intrusion.
Rudy Sedlak
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Date: Mon, 19 Nov 2001 13:47:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA bone of contention
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I would say use another board finish - ENIG or similar - as you may have a
flatness problem with HASL. Or you can think about answers to the following
questions and see if they give you any other clues, or help us to give you
better answers:
What substrate are you using?
Are the opens occuring at first test after assembly, or in qualification
testing or are they field returns? Has any temperature cycling been carried
out?
How old are the PCB's you're using - have they become oxidised?
Have the BGA's been re-worked/replaced?
Do the opens occur with the same contacts or are they more random?
Do you have any thermally assymetrical design features near the problem
area(s) such as heavy traces running nearby, or some longer traces and some
shorter traces? These can contribute to theft of heat, which may result in
there being insufficient heat left to make a proper solder joint,
especially if they're connected to thermal, voltage or ground planes, which
will dissipate the heat even more. You may have to reduce your peak
soldering temperature and increase its duration to compensate.
How was the thermal profiling carried out? Are you certain that all the BGA
contacts are reaching proper soldering temperature?
BGA pads in general are smaller than the ball diameter. Why did
"management" pick on 0.4mm as a pad size that would improve the situation?
If you are not using via-in-pad, 0.4mm pad sizes are going to interfere
with the offset vias and probably lead to greater problems of
solderability.
What other possible causes have been considered? What causes have you
rejected?
Good Luck - you may find there is no quick answer to this problem, but I
hope for your sake it's easily solved.
Peter Duncan
Tom Colby
<tcolby@CREST To: [log in to unmask]
RON.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA bone of contention
<[log in to unmask]
ORG>
11/17/01
04:46 AM
Please
respond to
"TechNet
E-Mail
Forum."
Help me out with this technetters,
The problem: BGA opens on a HASL board.
The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
0.28mm.
Management's solution is to increase the pad size to 0.4mm. I say to look
elsewhere in the process for the problem.
I'd like to hear the opinions of my esteemed colleagues. What do you say
folks?
Thanks in advance,
Tom
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Date: Mon, 19 Nov 2001 13:54:51 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Hans,
Uncontrolled or too rapid cool-down during lamination is what I thought had
probably caused the warp in the first place, and you're right - the trick
with de-warping is not getting the warp back again as soon as you go near
reflow or wave soldering. I suspect a lot of finger crossing and whispered
prayers are likely the main means of passing that hurdle successfully, as
there are no guarantees that a flattened board will stay flattened.
I'm going to follow Jeff's guideline - it's not so different from what I
used years ago on "conventional" technology boards - to try and straighten
out some of the boards we have as a back-up in case we can't get good
boards even after a second re-make. I'm three and a half months into a 2
week delivery on these little b----rs!
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Board Warp
<[log in to unmask]>
11/17/01 05:33 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter,
Symmetrical stack-up is crucial and I've seen a few designs where it just
couldn't be helped (impedance). Rapid or uncontrolled cool down during
lamination can also contribute to bow/twist in a balanced construction.
I've successfully used post lamination dewarp procedures similar to Jeff's
suggestion but that was for Class 2 stuff. The trick is making the dewarp
last through subsequent high temp. assembly steps (soldering).
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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Date: Mon, 19 Nov 2001 14:24:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Hi, Edward,
The heavy copper weight resulting from all these plating processes was
recognised early on, but a) we assumed it would be reasonably even acro=
ss
the board surface, and b) was not so heavy that the required widths and=
spacings couldn't achieved after final etch. Certainly it wasn't flagge=
d up
to us by the fab house as being a problem.
A very similar board was made by another fab house with no problem, apa=
rt
from the boards being warped. The etching was fine - it's just that the=
y
took 7 weeks to make them on priority, which we couldn't afford again.
Hmmm! The things we have to find out the hard way.
Peter Duncan
=
=20
Edward =
=20
Szpruch To: [log in to unmask] =
=20
<edward@ELTEK cc: (bcc: DUNCAN Peter/Ass=
t Prin Engr/ST =20
.CO.IL> Aero/ST Group) =
=20
Sent by: Subject: Re: [TN] Over-etc=
h =20
TechNet =
=20
<[log in to unmask] =
=20
ORG> =
=20
=
=20
=
=20
11/18/01 =
=20
03:08 PM =
=20
Please =
=20
respond to =
=20
"TechNet =
=20
E-Mail =
=20
Forum." =
=20
=
=20
=
=20
Peter,
Let me refrase your question from plating point of view since you rised=
1
milion dollar question:
How to plate the holes without plating the surface.
As far as I know,the best equipment,the best technologies,the best
chemistry
etc have limitited capacity in terms of throwing capability ( ratio of
metal
plated inside the hole to metal plated on the surface).The best figure =
is
slighty above 1.0 , usually is less than 1.0 .
No magic in this area:if the design requires to plate 3 times at least =
20
microns or so in the holes, the surface will get additional around 60 -=
70
microns of copper before plating and etching of the final pattern.
PCB designer should know this basic fact of life while imposing fancy
construction.
Of course PCB manufacturer has some possibilities to manipulate artwork=
compensations according to copper thickness to be etched, but etching
factors are also fact of life.
There are some tricky ways,but most of them are not working well on HDI=
boards with fine lines.
Edward
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: =E5 =F0=E5=E1=EE=E1=F8 16 2001 10:04
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Rudy,
>
> The boards are ENIG finished, the ENIG plating being carried out
> post-solder-mask, which must be after final copper etch, so No, there=
is
> no
> other metal in the area, unless my understanding of the plating/etchi=
ng
> sequence is all wrong. My understanding (faulty or otherwise) of what=
the
> fab house has done, is that they laminate, drill and plate the layers=
with
> the first suite of blind vias, then laminate, drill and plate for th=
e
> second suite of blind vias, then again for the 3rd suite until everyt=
hing
> is stacked up, pressed, drilled and plated for the through-holes. I
> haven't
> quite been able to make sense of it all yet, but I think what I'm bei=
ng
> told is that the plating becomes "stepped" somehow. I have 3 sets of
blind
> vias from each outer surface (for ease of argument), making 4 plating=
> sessions on each side by the time the through-hole group is done. The=
> first
> areas to be drilled and plated are therefore plated 4 times, while th=
e
> last
> areas to be drilled are only plated once, with the groups in between
> getting their proportional share of multiple plating.
>
> Thus at final etch, there is, I am told, a compromise to be reached -=
how
> to achieve the correct widths and spacings on the heavily plated area=
s
> without over-etching the lightly-plated areas. In my simple way, I wo=
uld
> have expected the entire board surface to have an even plating thickn=
ess,
> however thick, but seemingly not. The compromise hasn't worked for th=
e
> number of blind via groups featured in this board, and I need to try =
to
> find out how to address a solution without solely relying on what our=
fab
> house tells me.
>
> In my entire life, I never had to worry about the processes involved =
in
> fabricating PCB's - only that components could be soldered to them, t=
hat
> they passed test and proved to be reliable in the field. I only ever
> worked
> with good boards - the ones that passed in-coming inspection - in an
> assembly environment, so my experience of board design and PCB fab is=
> limited to the past 8 or 9 months, in a company that has no previous
> convictions for designing this type of board, so it's a case of the b=
lind
> leading the blind to a certain extent.
>
> Any further help in this area would be greatly appreciated.
>
> Best regards
>
> Peter Duncan
>
>
>
>
> "<Rudy
> Sedlak>" To: [log in to unmask]
> Sent by: cc: (bcc: DUNCAN Peter/A=
sst
> Prin Engr/ST
> TechNet Aero/ST Group)
> <[log in to unmask] Subject: Re: [TN] Over-e=
tch
> ORG>
>
>
> 11/16/01
> 02:13 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> Peter:
>
> I am not sure if I fully understand the process you are using....so I=
am
> going to ask a dumb question, that may shed some light on the issue..=
.
>
> Is there, anywhere in electrical contact with Copper being etched any=
> other
> metal excepting Tin?
>
> This sort of thing, selective over-etch, is classically seen when the=
re
is
> some other metal, (Nickel, Gold, or???) than Tin in electrical contac=
t
> with
> the over-etched Copper, and also in contact with the etchant.
>
> And if I am completely out in space with this question, please forgiv=
e
the
> intrusion.
>
> Rudy Sedlak
>
>
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Date: Mon, 19 Nov 2001 15:48:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: No power on after underfill
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C170CE.97A1C470"
This is a multi-part message in MIME format.
------_=_NextPart_001_01C170CE.97A1C470
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
3513 and the curing condition is 115C , 15 minutes , the BGA' s package
is below .
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3
; pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3
; pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good ones
.But after curing , some phone failed because "can not power on ", and
some failed for "check SIM card ", the defect sample is closed to 3%. I
think "check card "issue" may caused by the underfill material emission
which cover the SIM card lead .
But I can not get any idea for further.
Thanks=20
Tony
------_=_NextPart_001_01C170CE.97A1C470
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<TITLE>No power on after underfill</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial">Pls help me to solve =
this issue</FONT>
</P>
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial">We use undefilll for =
two BGA in one product ,the epoxy is Loctite LPD 3513 and the curing =
condition is 115C , 15 minutes , the BGA' s package is below =
.</FONT></P>
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New =
Roman"> U3 information : Body size, 9*9mm =
; height 1.7 ; bump diameter 0.3 ; pitch, 0.8*0.8 ;bump array =
10*10</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New =
Roman"> U1 information : Body size, 12*12 =
; heigh t1.7 ; bump diameter 0.3 ; pitch, 0.8*0.8 ; bump array =
14*14</FONT>
</P>
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial">Before the underfilll =
we check the electric function .All are good ones .</FONT><FONT =
COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">But after curing , =
some phone failed because "can not power on ", and some failed =
for "check SIM card ", the defect sample is closed to 3%. I =
think "check card "issue" may caused by the underfill =
material emission which cover the SIM card lead .</FONT></P>
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">But I can =
not get any idea for further.</FONT>
</P>
<P><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New Roman">Thanks =
</FONT>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times New =
Roman">Tony</FONT>
</P>
</BODY>
</HTML>
------_=_NextPart_001_01C170CE.97A1C470--
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Date: Mon, 19 Nov 2001 07:50:44 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: handling single parts
MIME-Version: 1.0
Content-Type: text/plain
Hi Earl,
I've experienced the same problem in the past. My solution was to write my
own short training program and deliver it to manufacturing, test and stores.
This gives them the idea that there is a need to handle the components in a
sympathetic way, but the best bit was the follow up.
With the permission of their Management, I gave them conducted tours of the
SMT line and showed them, first hand, what excellent quality we can achieve
when all goes well and, more importantly, what problems we have when things
go wrong; bent legs, mis-orientated components, shortages etc.
I'm a great believer in the idea that nobody comes to work to do a bad job,
they just lack information. If I can give them that information in a
positive way they nearly always respond.
Oh dear! This now sounds like a lecture, sorry, but communications is a
passion with me.
Regards
Eric Dawson
> -----Original Message-----
> From: Wildes, Earl [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 3:53 PM
> To: [log in to unmask]
> Subject: [TN] handling single parts
>
> Hi there. I sent this out once before, but it might have bounced.
> Is there any guideline or procedure detailing how to handle single surface
> mount parts, especially fine pitch. I've found several on moisture and
> ESD,
> but none on re-packaging. Our production numbers are rather low, so it is
> not always best to issue the whole tray of parts to the board shop. We
> need
> a document to teach the stockroom personnel how to pick up and package
> individual parts without bending the leads.
> Thanks for your help.
>
>
> Earl Wildes
> Sr. Component Engineer
> Korry Electronics Co.
> 901 Dexter Ave N.
> Seattle, WA 98109
> 206-694-1398
> [log in to unmask]
>
> --------------------------------------------------------------------------
> -------
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Date: Mon, 19 Nov 2001 08:20:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: BGA bone of contention
MIME-Version: 1.0
Content-Type: text/plain
Hi Tom,
Are you wave soldering the other side of the board with the reflow soldered
bga.s on top? I have come across this practice and it definitely disturbs
the bga joints causing opens which cannot be detected by ordinary X ray
inspection.
Hope this helps.
Regards
Eric Dawson
> -----Original Message-----
> From: Tom Colby [SMTP:[log in to unmask]]
> Sent: Friday, November 16, 2001 8:47 PM
> To: [log in to unmask]
> Subject: [TN] BGA bone of contention
>
> Help me out with this technetters,
>
> The problem: BGA opens on a HASL board.
>
> The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
> 0.28mm.
>
> Management's solution is to increase the pad size to 0.4mm. I say to look
> elsewhere in the process for the problem.
>
> I'd like to hear the opinions of my esteemed colleagues. What do you say
> folks?
>
> Thanks in advance,
>
> Tom
>
> --------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 09:16:53 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Stencil Reductions
MIME-Version: 1.0
Content-Type: text/plain
Hi,
Does any standard/procedure exist in relation to stencil reductions on a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
for the stated addressee(s) and access to it by any other person is
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The views expressed in this E-mail are those of the author, and do not
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Date: Mon, 19 Nov 2001 10:33:15 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] handling single parts
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi Earl,
I don=B4t think it=B4s any good what you have in mind with your fine =
pitch
parts. If you have them in a tray better leave them there, supply only =
trays
to your line, handle them according their moisture level, reseal the =
bags
and send the remaining parts back to your stock.
For safe repacking you will need to have some kind of equipment, a
manipulator seems to be the minimum requirement for that task, all =
necessary
ESD measures and operators with enough sensitiveness to handle those
delicate parts, all things that normally aren=B4t found in stockrooms.
Don=B4t get yourself in trouble
Wolfgang=20
-----Urspr=FCngliche Nachricht-----
Von: Wildes, Earl [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 16:53
An: [log in to unmask]
Betreff: [TN] handling single parts
Hi there. I sent this out once before, but it might have bounced.
Is there any guideline or procedure detailing how to handle single =
surface
mount parts, especially fine pitch. I've found several on moisture and =
ESD,
but none on re-packaging. Our production numbers are rather low, so it =
is
not always best to issue the whole tray of parts to the board shop. We =
need
a document to teach the stockroom personnel how to pick up and package
individual parts without bending the leads.
Thanks for your help.
Earl Wildes
Sr. Component Engineer
Korry Electronics Co.
901 Dexter Ave N.
Seattle, WA 98109
206-694-1398
[log in to unmask]
------------------------------------------------------------------------=
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----
-----
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Date: Mon, 19 Nov 2001 10:45:36 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] BGA voids
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-2022-jp"
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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=========================================================================
Date: Mon, 19 Nov 2001 18:27:10 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably doesn't
matter. The main thing I can think of that would cause your problem is the
thermal excursions needed to apply and cure the underfill. Am I correct to
say that the boards passed test at room temperature before the underfill is
applied?
You may have a manufacturing problem where the balls make contact enough to
pass test, but fail at elevated temperature. I would try testing the boards
at 100 or 115 degrees C prior to underfilling them and see if they still
pass. If they do, but fail again after underfilling, then the problem is
probably related to your underfilling process. It is quite easy to apply
too much if you're not using an automated process or have not correctly
calculated the amount of material to apply. It does flow more prior to
curing at curing temperature, and if it's getting into nearby interface
contacts as a result, you will need to look at damming the area around the
BGA with a peelable masking to contain the underfill until it's cured, or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have any
conductive residues left on the board, especially if you use no-clean
soldering processes, they may be picked up by the underfill and there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance of the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No power on after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD 3513
and the curing condition is 115C , 15 minutes , the BGA' s package is below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good ones .
But after curing , some phone failed because "can not power on ", and some
failed for "check SIM card ", the defect sample is closed to 3%. I think
"check card "issue" may caused by the underfill material emission which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
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=========================================================================
Date: Mon, 19 Nov 2001 12:45:48 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
MIME-Version: 1.0
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boundary="----=_NextPart_000_00E8_01C170F8.1D369040"
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The outgassin test for blowhole in printed boards was developed in the =
years gone bye after it appeared in and Italian PCB specification I was =
asked to review. After some testing I did it ended up in the IEC =
specification.
The same oil can be used effectivly for outgassing tests with via in =
pad. In the last test I did with ten scrap boards dfrom different =
suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias =
is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Busko, Wolfgang=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not =
Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a =
bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that =
the
pads don't have vias in them but if they did they can somtimes gass =
through
the plating, its not the air traped by the paste. I have investigated =
this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder =
joints
were discussed at some length. The received wisdom is that voids in =
solder
joints are not of themselves a 'defect' unless they break out through =
the
side of the ball. In fact, they make the joint more "flexible" - =
better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste =
flux
during the reflow process, though the size and shape of voids =
increases and
changes when there are via-in-pad features as well. About the only way =
to
detect them is by X-ray, and to judge from previous TechNet postings, =
there
are some pretty fancy machines around now that can give you a very =
much
clearer view of the balls than is normally the case ... if you have =
cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN =
Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to =
as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right =
at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on =
pad.
Does anyone know the possible reasons for voids formation in BGA =
(micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are =
not the
intended recipient, please delete it and notify us immediately; you =
should
not copy or use it for any purpose, nor disclose its contents to any =
other
person. Thank you.]
=
-------------------------------------------------------------------------=
---
-----
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1.8d
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<mailto:[log in to unmask]>
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Technet NOMAIL
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Please visit IPC web site ( http://www.ipc.org/html/forum.htm
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<mailto:[log in to unmask]
org> or 847-509-9700 ext.5315
=
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in
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charset="iso-2022-jp"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-2022-jp" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>The outgassin test for blowhole in =
printed boards=20
was developed in the years gone bye after it appeared in and Italian PCB =
specification I was asked to review. After some testing I did it ended =
up in the=20
IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The same oil can be used effectivly for =
outgassing=20
tests with via in pad. In the last test I did with ten scrap boards =
dfrom=20
different suppliers 2 outgassed on the pads from the vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The procedure for through hole which =
could and has=20
been applied to vias is on my web site which is in the download=20
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 =
9:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA =
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil =
trick I=20
recently cited ond not Earl the<BR>Moonman, sorry for not remembering =
and=20
citing correct.<BR>Although I often remember the good things my memory =
for=20
names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive=20
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche =
Nachricht-----<BR>Von: Bob=20
Willis [<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Ge=
sendet=20
am: Freitag, 16. November 2001 18:59<BR>An: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: =
[TN] BGA=20
voids<BR><BR><BR>We have experienced voiding with via in pad, I know =
it ws=20
stated that the<BR>pads don't have vias in them but if they did they =
can=20
somtimes gass through<BR>the plating, its not the air traped by the =
paste. I=20
have investigated this<BR>with my old outgassing oil test which showes =
up the=20
problem and will<BR>contribute to voiding.<BR><BR>Bob =
Willis<BR><BR>See us at=20
APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A><BR><<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A=20
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR=
>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to =
your=20
seminar, conference or roadshow<BR><A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A>=20
<<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>><BR><BR>-----=20
Original Message -----<BR>From: Peter George <<A=20
href=3D"mailto:Peter">mailto:Peter</A> George <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR><A=
=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>To: =
<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent: =
Friday,=20
November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA voids<BR><BR>Hi,=20
Peter,<BR><BR>I was at a seminar earlier this year where BGA's and =
their=20
solder joints<BR>were discussed at some length. The received wisdom is =
that=20
voids in solder<BR>joints are not of themselves a 'defect' unless they =
break=20
out through the<BR>side of the ball. In fact, they make the joint more =
"flexible" - better<BR>able to withstand creep fatigue - so are =
beneficial, up=20
to a point.<BR><BR>What causes them is often outgassing of volatiles =
in the=20
solder paste flux<BR>during the reflow process, though the size and =
shape of=20
voids increases and<BR>changes when there are via-in-pad features as =
well.=20
About the only way to<BR>detect them is by X-ray, and to judge from =
previous=20
TechNet postings, there<BR>are some pretty fancy machines around now =
that can=20
give you a very much<BR>clearer view of the balls than is normally the =
case=20
... if you have cash to<BR>splash!<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
Peter=20
=
Lee<BR> =
=20
<ppwlee@YAHOO =20
To: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR> &=
nbsp; &n=
bsp; =20
=
.COM>  =
; =20
cc: (bcc: DUNCAN Peter/Asst<BR>Prin=20
=
Engr/ST<BR> &n=
bsp; =20
Sent=20
=
by: &nbs=
p;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
=
TechNet =
=20
Subject: [TN] BGA=20
=
voids<BR> &nbs=
p; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/16/01<BR> &=
nbsp; =20
04:25=20
=
PM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am=20
encountering voids after reflow on several micro BGAs on one =
PCA<BR>product.=20
The voids that I $B!G (Bve observed (with Xray) contribute to =
as<BR>high=20
as<BR>60-70% of the joint area. My reflow profile was designed by =
running=20
a<BR>sample board with dummy components and thermalcouples attached =
right at=20
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see any =
via on=20
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons for =
voids=20
formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, =
in step=20
by step how would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
This=20
e-mail is confidential and may also be privileged. If you are not=20
the<BR>intended recipient, please delete it and notify us immediately; =
you=20
should<BR>not copy or use it for any purpose, nor disclose its =
contents to any=20
other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
----------------<BR>-----<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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On-Line<BR>Resources & Databases > E-mail Archives<BR>Please =
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Date: Mon, 19 Nov 2001 12:52:06 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Stencil Reductions
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If you call Peter Swanson at Intertronics in the UK he can supply you =
the IPC Standard document.
Many thanks
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Cathy Killen=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:16 AM
Subject: [TN] Stencil Reductions
Hi,
Does any standard/procedure exist in relation to stencil reductions on =
a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is =
intended only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries, =
unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for =
viruses.
=
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>If you call Peter Swanson at =
Intertronics in the UK=20
he can supply you the IPC Standard document.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Many thanks</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Cathy=20
Killen</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 =
9:16=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Stencil =
Reductions</DIV>
<DIV><BR></DIV>Hi,<BR>Does any standard/procedure exist in relation to =
stencil=20
reductions on a<BR>paste screen? If so, where can I source them. If =
there are=20
no<BR>standards/procedures what reductions would you=20
recommend?<BR>Thanks.<BR><BR>Cathy Killen<BR>Training =
Instructor<BR>Smtek=20
Europe Ltd.<BR>The information contained in the E-mail is =
confidential. It is=20
intended only<BR>for the stated addressee(s) and access to it by any =
other=20
person is<BR>unauthorised.<BR>The views expressed in this E-mail are =
those of=20
the author, and do not<BR>represent the views of Smtek Europe, its =
associates=20
or subsidiaries, unless<BR>otherwise expressly indicated.<BR>Please =
note: It=20
is your responsibility to scan this E-mail for=20
=
viruses.<BR><BR>---------------------------------------------------------=
------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
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IPC web=20
site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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Date: Mon, 19 Nov 2001 08:15:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: E-Business auctions for EMS providers...
Mime-Version: 1.0
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What site is doing this? Interesting concept but way too many risks. =20
Kathy=20
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<DIV>What site is doing this? Interesting concept but way too many
risks. </DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Mon, 19 Nov 2001 10:16:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
(#2001-713)
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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I'm not that far up in the food chain to know all of the particulars, but
it wouldn't surprise me if that were the case.
What I'm looking for is comments on the increase of pad size and
corroboration in my belief that it's the wrong solution to this problem.
Tom
At 04:20 AM 11/19/01 -0600, you wrote:
>Date: Mon, 19 Nov 2001 08:20:31 -0000
>From: Eric Dawson <[log in to unmask]>
>Subject: Re: BGA bone of contention
>
>Hi Tom,
>Are you wave soldering the other side of the board with the reflow soldered
>bga.s on top? I have come across this practice and it definitely disturbs
>the bga joints causing opens which cannot be detected by ordinary X ray
>inspection.
>Hope this helps.
>Regards
>Eric Dawson
>
> > -----Original Message-----
> > From: Tom Colby [SMTP:[log in to unmask]]
> > Sent: Friday, November 16, 2001 8:47 PM
> > To: [log in to unmask]
> > Subject: [TN] BGA bone of contention
> >
> > Help me out with this technetters,
> >
> > The problem: BGA opens on a HASL board.
> >
> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
> > 0.28mm.
> >
> > Management's solution is to increase the pad size to 0.4mm. I say to look
> > elsewhere in the process for the problem.
> >
> > I'd like to hear the opinions of my esteemed colleagues. What do you say
> > folks?
> >
> > Thanks in advance,
> >
> > Tom
> >
> > --------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 07:27:17 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Stencil Reductions
X-cc: [log in to unmask]
In-Reply-To: <010e01c170f9$00a58660$0300a8c0@dell>
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The document you probably are referring to is IPC7525. It describes stencil
design GUIDELINES. Because of all the variables in the printing process you
can not come up with design RULES.
If you design and assemble your own boards you can establish in-house rules
for stencil design, but for a contract manufacturer that is a different
story. He has to look at the board that is provided and choose the best
design rules that than fit his process.
As far as aperture reductions go, some assemblers (very few) reduce all
their apertures by 1mil, most reduce only some apertures to eliminate
bridging.
Look at your own assembly process, determine what works best and write a set
of "design rules" as your own addendum to IPC7525 to match that in order to
get to World Class production quality.
Good luck,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bob Willis
Sent: Monday, November 19, 2001 04:52
To: [log in to unmask]
Subject: Re: [TN] Stencil Reductions
If you call Peter Swanson at Intertronics in the UK he can supply you the
IPC Standard document.
Many thanks
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
----- Original Message -----
From: Cathy Killen
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:16 AM
Subject: [TN] Stencil Reductions
Hi,
Does any standard/procedure exist in relation to stencil reductions on a
paste screen? If so, where can I source them. If there are no
standards/procedures what reductions would you recommend?
Thanks.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended
only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries,
unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for viruses.
------------------------------------------------------------------------
---------
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> E-mail Archives
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>The=20
document you probably are referring to is IPC7525. It describes stencil =
design=20
GUIDELINES. Because of all the variables in the printing process you can =
not=20
come up with design RULES. </FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>If you=20
design and assemble your own boards you can establish in-house rules for =
stencil=20
design, but for a contract manufacturer that is a different story. He =
has to=20
look at the board that is provided and choose the best design rules that =
than=20
fit his process.</FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>As far=20
as aperture reductions go, some assemblers (very few) reduce all their =
apertures=20
by 1mil, most reduce only some apertures to eliminate=20
bridging.</FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>Look=20
at your own assembly process, determine what works best and write a set =
of=20
"design rules" as your own addendum to IPC7525 to match that in order to =
get to=20
World Class production quality.</FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>Good=20
luck,</FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2>Ahne.</FONT></SPAN></DIV>
<DIV><SPAN class=3D490331415-19112001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Bob Willis<BR><B>Sent:</B> =
Monday,=20
November 19, 2001 04:52<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> Re:=20
[TN] Stencil Reductions<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>If you call Peter Swanson at =
Intertronics in the=20
UK he can supply you the IPC Standard document.</FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Many thanks</FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,=20
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT> </DIV>
<DIV>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">Cathy=20
Killen</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, =
2001 9:16=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Stencil =
Reductions</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT><FONT =
face=3DArial=20
color=3D#0000ff size=3D2></FONT><BR></DIV>Hi,<BR>Does any =
standard/procedure=20
exist in relation to stencil reductions on a<BR>paste screen? If so, =
where=20
can I source them. If there are no<BR>standards/procedures what =
reductions=20
would you recommend?<BR>Thanks.<BR><BR>Cathy Killen<BR>Training=20
Instructor<BR>Smtek Europe Ltd.<BR>The information contained in the =
E-mail=20
is confidential. It is intended only<BR>for the stated addressee(s) =
and=20
access to it by any other person is<BR>unauthorised.<BR>The views =
expressed=20
in this E-mail are those of the author, and do not<BR>represent the =
views of=20
Smtek Europe, its associates or subsidiaries, unless<BR>otherwise =
expressly=20
indicated.<BR>Please note: It is your responsibility to scan this =
E-mail for=20
=
viruses.<BR><BR>---------------------------------------------------------=
------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
unsubscribe, send a message to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
text=20
in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To =
temporarily=20
halt delivery of Technet send the following message: SET Technet=20
NOMAIL<BR>Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
=
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Date: Mon, 19 Nov 2001 07:42:59 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
(#2001-713)
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
As a layout designer, I am surprised that they used such small land areas.
Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
See attached PDF from Motorola.
Denis Lefebvre, C.I.D.
Senior PCB Designer
Finisar Corporation
(408)542-3832
http://www.finisar.com
At 10:16 AM 11/19/2001 -0500, you wrote:
>I'm not that far up in the food chain to know all of the particulars, but
>it wouldn't surprise me if that were the case.
>
>What I'm looking for is comments on the increase of pad size and
>corroboration in my belief that it's the wrong solution to this problem.
>
>Tom
>
>At 04:20 AM 11/19/01 -0600, you wrote:
>>Date: Mon, 19 Nov 2001 08:20:31 -0000
>>From: Eric Dawson <[log in to unmask]>
>>Subject: Re: BGA bone of contention
>>
>>Hi Tom,
>>Are you wave soldering the other side of the board with the reflow soldered
>>bga.s on top? I have come across this practice and it definitely disturbs
>>the bga joints causing opens which cannot be detected by ordinary X ray
>>inspection.
>>Hope this helps.
>>Regards
>>Eric Dawson
>>
>> > -----Original Message-----
>> > From: Tom Colby [SMTP:[log in to unmask]]
>> > Sent: Friday, November 16, 2001 8:47 PM
>> > To: [log in to unmask]
>> > Subject: [TN] BGA bone of contention
>> >
>> > Help me out with this technetters,
>> >
>> > The problem: BGA opens on a HASL board.
>> >
>> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
>> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad of
>> > 0.28mm.
>> >
>> > Management's solution is to increase the pad size to 0.4mm. I say to look
>> > elsewhere in the process for the problem.
>> >
>> > I'd like to hear the opinions of my esteemed colleagues. What do you say
>> > folks?
>> >
>> > Thanks in advance,
>> >
>> > Tom
>> >
>> > --------------------------------------------------------------------------
>
>---------------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 09:21:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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Date: Mon, 19 Nov 2001 11:26:31 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
MIME-Version: 1.0
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boundary="----=_NextPart_000_0008_01C170ED.09B1ECA0"
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charset="iso-2022-jp"
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Who are suppliers of inspection quality oils [Canadian Balson??] the =
bear the heat of soldering well?
----- Original Message -----=20
From: Bob Willis=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the =
years gone bye after it appeared in and Italian PCB specification I was =
asked to review. After some testing I did it ended up in the IEC =
specification.
The same oil can be used effectivly for outgassing tests with via in =
pad. In the last test I did with ten scrap boards dfrom different =
suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to =
vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Busko, Wolfgang=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond =
not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems =
a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated =
that the
pads don't have vias in them but if they did they can somtimes gass =
through
the plating, its not the air traped by the paste. I have =
investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder =
joints
were discussed at some length. The received wisdom is that voids in =
solder
joints are not of themselves a 'defect' unless they break out =
through the
side of the ball. In fact, they make the joint more "flexible" - =
better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder =
paste flux
during the reflow process, though the size and shape of voids =
increases and
changes when there are via-in-pad features as well. About the only =
way to
detect them is by X-ray, and to judge from previous TechNet =
postings, there
are some pretty fancy machines around now that can give you a very =
much
clearer view of the balls than is normally the case ... if you have =
cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN =
Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one =
PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute =
to as
high as
60-70% of the joint area. My reflow profile was designed by running =
a
sample board with dummy components and thermalcouples attached right =
at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via =
on pad.
Does anyone know the possible reasons for voids formation in BGA =
(micro)
reflow?
In general, in step by step how would one trouble shoot such a =
defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are =
not the
intended recipient, please delete it and notify us immediately; you =
should
not copy or use it for any purpose, nor disclose its contents to any =
other
person. Thank you.]
=
-------------------------------------------------------------------------=
---
-----
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1.8d
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<mailto:[log in to unmask]>
with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following message: =
SET
Technet NOMAIL
Search previous postings at: www.ipc.org <http://www.ipc.org> > =
On-Line
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Please visit IPC web site ( http://www.ipc.org/html/forum.htm
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<mailto:[log in to unmask]
org> or 847-509-9700 ext.5315
=
-------------------------------------------------------------------------=
---
-----
=
-------------------------------------------------------------------------=
--------
Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d
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text in
the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
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Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
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847-509-9700 ext.5315
=
-------------------------------------------------------------------------=
--------
------=_NextPart_000_0008_01C170ED.09B1ECA0
Content-Type: text/html;
charset="iso-2022-jp"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Who are suppliers of inspection quality =
oils=20
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Bob =
Willis</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 =
4:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA=20
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2>The outgassin test for blowhole in =
printed boards=20
was developed in the years gone bye after it appeared in and Italian =
PCB=20
specification I was asked to review. After some testing I did it ended =
up in=20
the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The same oil can be used effectivly =
for=20
outgassing tests with via in pad. In the last test I did with ten =
scrap boards=20
dfrom different suppliers 2 outgassed on the pads from the =
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The procedure for through hole which =
could and=20
has been applied to vias is on my web site which is in the download=20
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,=20
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, =
2001 9:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA =
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil =
trick I=20
recently cited ond not Earl the<BR>Moonman, sorry for not =
remembering and=20
citing correct.<BR>Although I often remember the good things my =
memory for=20
names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive=20
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche =
Nachricht-----<BR>Von:=20
Bob Willis [<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Ge=
sendet=20
am: Freitag, 16. November 2001 18:59<BR>An: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: =
[TN] BGA=20
voids<BR><BR><BR>We have experienced voiding with via in pad, I know =
it ws=20
stated that the<BR>pads don't have vias in them but if they did they =
can=20
somtimes gass through<BR>the plating, its not the air traped by the =
paste. I=20
have investigated this<BR>with my old outgassing oil test which =
showes up=20
the problem and will<BR>contribute to voiding.<BR><BR>Bob =
Willis<BR><BR>See=20
us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A><BR><<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A=20
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR=
>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to =
your=20
seminar, conference or roadshow<BR><A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A>=20
<<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>><BR><BR>-----=20
Original Message -----<BR>From: Peter George <<A=20
href=3D"mailto:Peter">mailto:Peter</A> George <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR><A=
=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>To: =
<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:=20
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA =
voids<BR><BR>Hi,=20
Peter,<BR><BR>I was at a seminar earlier this year where BGA's and =
their=20
solder joints<BR>were discussed at some length. The received wisdom =
is that=20
voids in solder<BR>joints are not of themselves a 'defect' unless =
they break=20
out through the<BR>side of the ball. In fact, they make the joint =
more=20
"flexible" - better<BR>able to withstand creep fatigue - so are =
beneficial,=20
up to a point.<BR><BR>What causes them is often outgassing of =
volatiles in=20
the solder paste flux<BR>during the reflow process, though the size =
and=20
shape of voids increases and<BR>changes when there are via-in-pad =
features=20
as well. About the only way to<BR>detect them is by X-ray, and to =
judge from=20
previous TechNet postings, there<BR>are some pretty fancy machines =
around=20
now that can give you a very much<BR>clearer view of the balls than =
is=20
normally the case ... if you have cash to<BR>splash!<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
Peter=20
=
Lee<BR> =
=20
<ppwlee@YAHOO =20
To: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR> &=
nbsp; &n=
bsp; =20
=
.COM>  =
; =20
cc: (bcc: DUNCAN Peter/Asst<BR>Prin=20
=
Engr/ST<BR> &n=
bsp; =20
Sent=20
=
by: &nbs=
p;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
=
TechNet =
=20
Subject: [TN] BGA=20
=
voids<BR> &nbs=
p; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/16/01<BR> &=
nbsp; =20
04:25=20
=
PM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I =
am=20
encountering voids after reflow on several micro BGAs on one =
PCA<BR>product.=20
The voids that I $B!G (Bve observed (with Xray) contribute to =
as<BR>high=20
as<BR>60-70% of the joint area. My reflow profile was designed by =
running=20
a<BR>sample board with dummy components and thermalcouples attached =
right at=20
the<BR>joint. I also inspected the PCB lands and didn $B!G (Bt see =
any via=20
on pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible reasons =
for=20
voids formation in BGA (micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In =
general,=20
in step by step how would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
This=20
e-mail is confidential and may also be privileged. If you are not=20
the<BR>intended recipient, please delete it and notify us =
immediately; you=20
should<BR>not copy or use it for any purpose, nor disclose its =
contents to=20
any other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
----------------<BR>-----<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
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NOMAIL<BR>Search previous postings at: <A=20
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&=20
Databases > E-mail Archives<BR>Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
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href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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=========================================================================
Date: Mon, 19 Nov 2001 16:42:43 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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Its the standard oil you use with a microscope when you are using a 100x =
objective for immersion.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: David Fish=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 7:26 PM
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the =
bear the heat of soldering well?
----- Original Message -----=20
From: Bob Willis=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in =
the years gone bye after it appeared in and Italian PCB specification I =
was asked to review. After some testing I did it ended up in the IEC =
specification.
The same oil can be used effectivly for outgassing tests with via in =
pad. In the last test I did with ten scrap boards dfrom different =
suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to =
vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Busko, Wolfgang=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond =
not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names =
seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated =
that the
pads don't have vias in them but if they did they can somtimes =
gass through
the plating, its not the air traped by the paste. I have =
investigated this
with my old outgassing oil test which showes up the problem and =
will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com =
<http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder =
joints
were discussed at some length. The received wisdom is that voids =
in solder
joints are not of themselves a 'defect' unless they break out =
through the
side of the ball. In fact, they make the joint more "flexible" - =
better
able to withstand creep fatigue - so are beneficial, up to a =
point.
What causes them is often outgassing of volatiles in the solder =
paste flux
during the reflow process, though the size and shape of voids =
increases and
changes when there are via-in-pad features as well. About the only =
way to
detect them is by X-ray, and to judge from previous TechNet =
postings, there
are some pretty fancy machines around now that can give you a very =
much
clearer view of the balls than is normally the case ... if you =
have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN =
Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA =
voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one =
PCA
product. The voids that I $B!G (Bve observed (with Xray) =
contribute to as
high as
60-70% of the joint area. My reflow profile was designed by =
running a
sample board with dummy components and thermalcouples attached =
right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any =
via on pad.
Does anyone know the possible reasons for voids formation in BGA =
(micro)
reflow?
In general, in step by step how would one trouble shoot such a =
defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you =
are not the
intended recipient, please delete it and notify us immediately; =
you should
not copy or use it for any purpose, nor disclose its contents to =
any other
person. Thank you.]
=
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<mailto:[log in to unmask]>
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To temporarily halt delivery of Technet send the following =
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Technet NOMAIL
Search previous postings at: www.ipc.org <http://www.ipc.org> > =
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Please visit IPC web site ( http://www.ipc.org/html/forum.htm
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<mailto:[log in to unmask]
org> or 847-509-9700 ext.5315
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--------
Technet Mail List provided as a free service by IPC using LISTSERV =
1.8d
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text in
the BODY (NOT the subject field): SIGNOFF Technet
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
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charset="iso-2022-jp"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-2022-jp" =
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<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Its the standard oil you use with a =
microscope when=20
you are using a 100x objective for immersion.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>David =
Fish</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 =
7:26=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA=20
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2>Who are suppliers of inspection =
quality oils=20
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Bob=20
Willis</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, =
2001 4:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] =
BGA=20
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2>The outgassin test for blowhole in =
printed=20
boards was developed in the years gone bye after it appeared in and =
Italian=20
PCB specification I was asked to review. After some testing I did it =
ended=20
up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The same oil can be used effectivly =
for=20
outgassing tests with via in pad. In the last test I did with ten =
scrap=20
boards dfrom different suppliers 2 outgassed on the pads from the=20
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The procedure for through hole =
which could and=20
has been applied to vias is on my web site which is in the download=20
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- =
</DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>Busko, Wolfgang</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, =
2001 9:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA=20
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J =
oil trick=20
I recently cited ond not Earl the<BR>Moonman, sorry for not =
remembering=20
and citing correct.<BR>Although I often remember the good things =
my memory=20
for names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt =
forgive=20
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche =
Nachricht-----<BR>Von:=20
Bob Willis [<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Ge=
sendet=20
am: Freitag, 16. November 2001 18:59<BR>An: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: =
Re: [TN] BGA=20
voids<BR><BR><BR>We have experienced voiding with via in pad, I =
know it ws=20
stated that the<BR>pads don't have vias in them but if they did =
they can=20
somtimes gass through<BR>the plating, its not the air traped by =
the paste.=20
I have investigated this<BR>with my old outgassing oil test which =
showes=20
up the problem and will<BR>contribute to voiding.<BR><BR>Bob=20
Willis<BR><BR>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A><BR><<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A =
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR=
>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to =
your=20
seminar, conference or roadshow<BR><A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A>=20
<<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>><BR><BR>-----=20
Original Message -----<BR>From: Peter George <<A=20
href=3D"mailto:Peter">mailto:Peter</A> George <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR><A=
=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>To: =
<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:=20
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA=20
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this =
year where=20
BGA's and their solder joints<BR>were discussed at some length. =
The=20
received wisdom is that voids in solder<BR>joints are not of =
themselves a=20
'defect' unless they break out through the<BR>side of the ball. In =
fact,=20
they make the joint more "flexible" - better<BR>able to withstand =
creep=20
fatigue - so are beneficial, up to a point.<BR><BR>What causes =
them is=20
often outgassing of volatiles in the solder paste flux<BR>during =
the=20
reflow process, though the size and shape of voids increases=20
and<BR>changes when there are via-in-pad features as well. About =
the only=20
way to<BR>detect them is by X-ray, and to judge from previous =
TechNet=20
postings, there<BR>are some pretty fancy machines around now that =
can give=20
you a very much<BR>clearer view of the balls than is normally the =
case ...=20
if you have cash to<BR>splash!<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
Peter=20
=
Lee<BR> =
=20
<ppwlee@YAHOO =20
To: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR> &=
nbsp; &n=
bsp; =20
=
.COM>  =
; =20
cc: (bcc: DUNCAN Peter/Asst<BR>Prin=20
=
Engr/ST<BR> &n=
bsp; =20
Sent=20
=
by: &nbs=
p;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
=
TechNet =
=20
Subject: [TN] BGA=20
=
voids<BR> &nbs=
p; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/16/01<BR> &=
nbsp; =20
04:25=20
=
PM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I =
am=20
encountering voids after reflow on several micro BGAs on one=20
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray) =
contribute=20
to as<BR>high as<BR>60-70% of the joint area. My reflow profile =
was=20
designed by running a<BR>sample board with dummy components and=20
thermalcouples attached right at the<BR>joint. I also inspected =
the PCB=20
lands and didn $B!G (Bt see any via on =
pad.<BR><BR><BR><BR><BR><BR>Does=20
anyone know the possible reasons for voids formation in BGA=20
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by =
step how=20
would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
This=20
e-mail is confidential and may also be privileged. If you are not=20
the<BR>intended recipient, please delete it and notify us =
immediately; you=20
should<BR>not copy or use it for any purpose, nor disclose its =
contents to=20
any other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
----------------<BR>-----<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
unsubscribe, send a message to <A=20
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=
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Date: Mon, 19 Nov 2001 08:47:52 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brooks,Bill" <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
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We used to make PCB's back in the mid 1970's and used a fusing oil produced
by Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut
oil... but I can't remember for sure... Those were my High School years...
:)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the bear
the heat of soldering well?
----- Original Message -----
From: Bob <mailto:[log in to unmask]> Willis
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the years
gone bye after it appeared in and Italian PCB specification I was asked to
review. After some testing I did it ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with via in pad. In
the last test I did with ten scrap boards dfrom different suppliers 2
outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias is
on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Busko, Wolfgang <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond not Earl
the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [ mailto:[log in to unmask] <mailto:[log in to unmask]> ]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask] <mailto:[log in to unmask]>
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated that the
pads don't have vias in them but if they did they can somtimes gass through
the plating, its not the air traped by the paste. I have investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
< http://www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm> >
www.bobwillis.co.uk <http://www.bobwillis.co.uk> < http://www.bobwillis.co.
uk <http://www.bobwillis.co.uk> >
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com> <
http://www.seminar-registrations.com <http://www.seminar-registrations.com>
>
----- Original Message -----
From: Peter George < mailto:Peter <mailto:Peter> George [log in to unmask]
ORG <mailto:[log in to unmask]> >
[log in to unmask] <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]> < mailto:[log in to unmask]
<mailto:[log in to unmask]> >
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder joints
were discussed at some length. The received wisdom is that voids in solder
joints are not of themselves a 'defect' unless they break out through the
side of the ball. In fact, they make the joint more "flexible" - better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder paste flux
during the reflow process, though the size and shape of voids increases and
changes when there are via-in-pad features as well. About the only way to
detect them is by X-ray, and to judge from previous TechNet postings, there
are some pretty fancy machines around now that can give you a very much
clearer view of the balls than is normally the case ... if you have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
< mailto:[log in to unmask] <mailto:[log in to unmask]> >
.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute to as
high as
60-70% of the joint area. My reflow profile was designed by running a
sample board with dummy components and thermalcouples attached right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via on pad.
Does anyone know the possible reasons for voids formation in BGA (micro)
reflow?
In general, in step by step how would one trouble shoot such a defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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<DIV><SPAN class=196294316-19112001><FONT face=Arial color=#0000ff size=2>We
used to make PCB's back in the mid 1970's and used a fusing oil produced by
Shell Oil in our Hydro-squeegee. I want to say it was some sort of Peanut oil...
but I can't remember for sure... Those were my High School years...
:)</FONT></SPAN></DIV>
<DIV><SPAN class=196294316-19112001><FONT face=Arial color=#0000ff size=2>Good
luck... - Bill Brooks</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> David Fish
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, November 19, 2001 11:27
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Who are suppliers of inspection quality oils
[Canadian Balson??] the bear the heat of soldering well?</FONT></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">Bob
Willis</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 4:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=Arial size=2>The outgassin test for blowhole in printed
boards was developed in the years gone bye after it appeared in and Italian
PCB specification I was asked to review. After some testing I did it ended
up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The same oil can be used effectivly for
outgassing tests with via in pad. In the last test I did with ten scrap
boards dfrom different suppliers 2 outgassed on the pads from the
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>The procedure for through hole which could and
has been applied to vias is on my web site which is in the download
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave,
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A></DIV>
<BLOCKQUOTE
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask]
href="mailto:[log in to unmask]">Busko, Wolfgang</A> </DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Monday, November 19, 2001 9:45
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] BGA
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J oil trick
I recently cited ond not Earl the<BR>Moonman, sorry for not remembering
and citing correct.<BR>Although I often remember the good things my memory
for names seems a bit<BR>weak.<BR><BR>Hope you don $B!- (Jt forgive
me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche Nachricht-----<BR>Von:
Bob Willis [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Gesendet
am: Freitag, 16. November 2001 18:59<BR>An: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: Re: [TN] BGA
voids<BR><BR><BR>We have experienced voiding with via in pad, I know it ws
stated that the<BR>pads don't have vias in them but if they did they can
somtimes gass through<BR>the plating, its not the air traped by the paste.
I have investigated this<BR>with my old outgassing oil test which showes
up the problem and will<BR>contribute to voiding.<BR><BR>Bob
Willis<BR><BR>See us at APEX 2002 <A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis.co.uk/workshops/apex/apex.htm</A><BR><<A
href="http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bobwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A
href="http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> <<A
href="http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR>Tel:
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution to your
seminar, conference or roadshow<BR><A
href="http://www.seminar-registrations.com">www.seminar-registrations.com</A>
<<A
href="http://www.seminar-registrations.com">http://www.seminar-registrations.com</A>><BR><BR>-----
Original Message -----<BR>From: Peter George <<A
href="mailto:Peter">mailto:Peter</A> George <A
href="mailto:[log in to unmask]">[log in to unmask]</A>><BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR>To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A> <<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this year where
BGA's and their solder joints<BR>were discussed at some length. The
received wisdom is that voids in solder<BR>joints are not of themselves a
'defect' unless they break out through the<BR>side of the ball. In fact,
they make the joint more "flexible" - better<BR>able to withstand creep
fatigue - so are beneficial, up to a point.<BR><BR>What causes them is
often outgassing of volatiles in the solder paste flux<BR>during the
reflow process, though the size and shape of voids increases
and<BR>changes when there are via-in-pad features as well. About the only
way to<BR>detect them is by X-ray, and to judge from previous TechNet
postings, there<BR>are some pretty fancy machines around now that can give
you a very much<BR>clearer view of the balls than is normally the case ...
if you have cash to<BR>splash!<BR><BR>Peter
Duncan<BR><BR><BR><BR><BR>
Peter
Lee<BR>
<ppwlee@YAHOO
To: <A
href="mailto:[log in to unmask]">[log in to unmask]</A><BR><<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>
.COM>
cc: (bcc: DUNCAN Peter/Asst<BR>Prin
Engr/ST<BR>
Sent
by:
Aero/ST
Group)<BR>
TechNet
Subject: [TN] BGA
voids<BR>
<[log in to unmask]<BR>
ORG><BR><BR><BR>
11/16/01<BR>
04:25
PM<BR>
Please<BR>
respond
to<BR>
"TechNet<BR>
E-Mail<BR>
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am
encountering voids after reflow on several micro BGAs on one
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray) contribute
to as<BR>high as<BR>60-70% of the joint area. My reflow profile was
designed by running a<BR>sample board with dummy components and
thermalcouples attached right at the<BR>joint. I also inspected the PCB
lands and didn $B!G (Bt see any via on pad.<BR><BR><BR><BR><BR><BR>Does
anyone know the possible reasons for voids formation in BGA
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by step how
would one trouble shoot such a
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[This
e-mail is confidential and may also be privileged. If you are not
the<BR>intended recipient, please delete it and notify us immediately; you
should<BR>not copy or use it for any purpose, nor disclose its contents to
any other<BR>person. Thank
you.]<BR><BR>----------------------------------------------------------------------------<BR>-----<BR>Technet
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Date: Mon, 19 Nov 2001 09:06:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Glynn Shaw <[log in to unmask]>
Subject: Re: Over-etch
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hello Peter.
I have been building complex boards seems like all my life. I understand
completely how the processes your fab shop used could result in difficulty
etching the patterns. I also understand how designers are capable of making
board production nearly impossible. If you are serious and would like real
help in determining if a better process exists for this particular board
then I am willing to devote a few hours of study to your problem-- but I
will need real information. I invite you to send me a fab drawing showing
the stack-ups and finished hole sizes, the various layer interconnections,
etc. In addition, if there aren't major confidentiality issues, I also
invite you to visit our web site and use the Data Transfer Menu to send us
the CAD Data for the part. We will load it onto our systems and check the
layout for plating-related issues.
It could well be that there is no better process than the fab house has
already chosen, but I also think they might have "overlooked" some viable
solutions to the problem. Only your fab drawing and data will tell for sure.
My web site is: www.protoengineering.com
My fax is USA: (408) 738-1290
At 10:26 AM 11/16/01 +0800, you wrote:
>Dear All,
>
>I have another problem for you PCB Fab guru's. The sister board to the
>warped one of my previous posting has the problem of being over-etched in
>some areas. Some pads are half the width they should be. It is 12 layer,
>ENIG finished, with 3 different blind via depths from the bottom of the
>board and two from the top, as well as the through-hole group. They are
>laminated conventionally - i.e. each blind group is laminated. drilled and
>plated before lamination for the next hole group, and so on, so there is
>considerable variance in surface copper weight by the time the board is
>fully laminated.
>
>Our fab house tried remaking the boards by laminating the entire board at
>once, then laser drilling to depth and plating. The result was a total
>failure, and once again we're faced with a re-make using the previous
>processes.
>
>Does anyone know how we can reduce the variance in surface copper weight
>such that, in final etch, there isn't such a poor compromise between
>getting the widths and spacings of the heavier copper areas right, without
>over-etching the lighter copper areas? I tentatively suggested selective
>masking of some kind for the areas already plated, but I have no idea if
>that's feasible or not. How do other fab houses deal with this situation?
>
>Thanks as ever for your invaluable help.
>
>Peter Duncan
>
>[This e-mail is confidential and may also be privileged. If you are not the
>intended recipient, please delete it and notify us immediately; you should
>not copy or use it for any purpose, nor disclose its contents to any other
>person. Thank you.]
>
>---------------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 11:42:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: AW: [TN] BGA voids
In-Reply-To: <72F8793F1F00D411BE2D00805FA7C0EBCD7B38@DATRON1>
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Used to purchase fusing oil with a Chevron label. They had a water soluble
as well as solvent oil but seems to me that the WS was at a significantly
higher price. Hollis used to carry oil for their oil injection wave
machines which was basically the same thing. Think it was Hollis 225. Did
a very nice job of wave soldering and reducing dross on the pot but sure was
messy.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Brooks,Bill
Sent: Monday, November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some sort
of Peanut oil... but I can't remember for sure... Those were my High School
years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the
bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the
years gone bye after it appeared in and Italian PCB specification I was
asked to review. After some testing I did it ended up in the IEC
specification.
The same oil can be used effectivly for outgassing tests with via in
pad. In the last test I did with ten scrap boards dfrom different suppliers
2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to
vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
----- Original Message -----
From: Busko, Wolfgang
To: [log in to unmask]
Sent: Monday, November 19, 2001 9:45 AM
Subject: [TN] AW: [TN] BGA voids
Hi Bob,
so it was you with this ol $B!- (J oil trick I recently cited ond
not Earl the
Moonman, sorry for not remembering and citing correct.
Although I often remember the good things my memory for names seems
a bit
weak.
Hope you don $B!- (Jt forgive me
Wolfgang
-----Ursprungliche Nachricht-----
Von: Bob Willis [mailto:[log in to unmask]]
Gesendet am: Freitag, 16. November 2001 18:59
An: [log in to unmask]
Betreff: Re: [TN] BGA voids
We have experienced voiding with via in pad, I know it ws stated
that the
pads don't have vias in them but if they did they can somtimes gass
through
the plating, its not the air traped by the paste. I have
investigated this
with my old outgassing oil test which showes up the problem and will
contribute to voiding.
Bob Willis
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----
From: Peter George <mailto:Peter George [log in to unmask]>
[log in to unmask]
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids
Hi, Peter,
I was at a seminar earlier this year where BGA's and their solder
joints
were discussed at some length. The received wisdom is that voids in
solder
joints are not of themselves a 'defect' unless they break out
through the
side of the ball. In fact, they make the joint more "flexible" -
better
able to withstand creep fatigue - so are beneficial, up to a point.
What causes them is often outgassing of volatiles in the solder
paste flux
during the reflow process, though the size and shape of voids
increases and
changes when there are via-in-pad features as well. About the only
way to
detect them is by X-ray, and to judge from previous TechNet
postings, there
are some pretty fancy machines around now that can give you a very
much
clearer view of the balls than is normally the case ... if you have
cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
<mailto:[log in to unmask]>
.COM> cc: (bcc: DUNCAN
Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on one
PCA
product. The voids that I $B!G (Bve observed (with Xray) contribute
to as
high as
60-70% of the joint area. My reflow profile was designed by running
a
sample board with dummy components and thermalcouples attached right
at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any via
on pad.
Does anyone know the possible reasons for voids formation in BGA
(micro)
reflow?
In general, in step by step how would one trouble shoot such a
defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you are
not the
intended recipient, please delete it and notify us immediately; you
should
not copy or use it for any purpose, nor disclose its contents to any
other
person. Thank you.]
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<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D304383519-19112001><FONT face=3DTahoma =
color=3D#000080 size=3D2>Used=20
to purchase fusing oil with a Chevron label. They had a water soluble as =
well as=20
solvent oil but seems to me that the WS was at a significantly =
higher price. Hollis used to carry oil for their oil =
injection wave=20
machines which was basically the same thing. Think it was Hollis=20
225. Did a very nice job of wave soldering and reducing dross on =
the pot=20
but sure was messy. </FONT></SPAN></DIV>
<DIV><SPAN class=3D304383519-19112001>
<P><FONT size=3D2>Mel Parrish<BR>Soldering Technology =
International<BR>Madison,=20
AL<BR>256 705 5530<BR>256 705 5538=20
Fax<BR>[log in to unmask]<BR> </FONT> </P></SPAN></DIV>
<DIV><SPAN class=3D304383519-19112001><FONT size=3D2><BR> </FONT> =
</DIV></SPAN>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of =
</B>Brooks,Bill<BR><B>Sent:</B>=20
Monday, November 19, 2001 8:48 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: [TN] BGA=20
voids<BR><BR></FONT></DIV>
<DIV><SPAN class=3D196294316-19112001><FONT face=3DArial =
color=3D#0000ff size=3D2>We=20
used to make PCB's back in the mid 1970's and used a fusing oil =
produced by=20
Shell Oil in our Hydro-squeegee. I want to say it was some sort of =
Peanut=20
oil... but I can't remember for sure... Those were my High School =
years...=20
:)</FONT></SPAN></DIV>
<DIV><SPAN class=3D196294316-19112001><FONT face=3DArial =
color=3D#0000ff size=3D2>Good=20
luck... - Bill Brooks</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> David Fish=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, November 19, 2001 =
11:27=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] AW: =
[TN] BGA=20
voids<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Who are suppliers of inspection =
quality oils=20
[Canadian Balson??] the bear the heat of soldering =
well?</FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- =
</DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">Bob=20
Willis</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November 19, =
2001 4:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] AW: [TN] =
BGA=20
voids</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2>The outgassin test for blowhole =
in printed=20
boards was developed in the years gone bye after it appeared in =
and=20
Italian PCB specification I was asked to review. After some =
testing I did=20
it ended up in the IEC specification.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The same oil can be used =
effectivly for=20
outgassing tests with via in pad. In the last test I did with ten =
scrap=20
boards dfrom different suppliers 2 outgassed on the pads from the=20
vias.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The procedure for through hole =
which could=20
and has been applied to vias is on my web site which is in the =
download=20
section.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Hope this helps.</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth =
Ave,=20
Chelmsford, Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- =
</DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">Busko, Wolfgang</A> =
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
[log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, November =
19, 2001=20
9:45 AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] AW: [TN] =
BGA=20
voids</DIV>
<DIV><BR></DIV>Hi Bob,<BR><BR>so it was you with this ol $B!- (J =
oil=20
trick I recently cited ond not Earl the<BR>Moonman, sorry for =
not=20
remembering and citing correct.<BR>Although I often remember the =
good=20
things my memory for names seems a bit<BR>weak.<BR><BR>Hope you =
don $B!-=20
(Jt forgive me<BR><BR>Wolfgang<BR><BR> -----Ursprungliche=20
Nachricht-----<BR>Von: Bob Willis [<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<BR>Ge=
sendet=20
am: Freitag, 16. November 2001 18:59<BR>An: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Betreff: =
Re: [TN]=20
BGA voids<BR><BR><BR>We have experienced voiding with via in =
pad, I know=20
it ws stated that the<BR>pads don't have vias in them but if =
they did=20
they can somtimes gass through<BR>the plating, its not the air =
traped by=20
the paste. I have investigated this<BR>with my old outgassing =
oil test=20
which showes up the problem and will<BR>contribute to=20
voiding.<BR><BR>Bob Willis<BR><BR>See us at APEX 2002 <A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A><BR><<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>><BR><BR><A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A> =
<<A=20
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>><BR=
>Tel:=20
(44) 01245 351502 Fax: (44) 01245 496123<BR><BR>Single solution =
to your=20
seminar, conference or roadshow<BR><A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A>=20
<<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>><BR><BR>-----=20
Original Message -----<BR>From: Peter George <<A=20
href=3D"mailto:Peter">mailto:Peter</A> George <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>><BR><A=
=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>To: =
<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR>Sent:=20
Friday, November 16, 2001 8:52 AM<BR>Subject: Re: [TN] BGA=20
voids<BR><BR>Hi, Peter,<BR><BR>I was at a seminar earlier this =
year=20
where BGA's and their solder joints<BR>were discussed at some =
length.=20
The received wisdom is that voids in solder<BR>joints are not of =
themselves a 'defect' unless they break out through the<BR>side =
of the=20
ball. In fact, they make the joint more "flexible" - =
better<BR>able to=20
withstand creep fatigue - so are beneficial, up to a =
point.<BR><BR>What=20
causes them is often outgassing of volatiles in the solder paste =
flux<BR>during the reflow process, though the size and shape of =
voids=20
increases and<BR>changes when there are via-in-pad features as =
well.=20
About the only way to<BR>detect them is by X-ray, and to judge =
from=20
previous TechNet postings, there<BR>are some pretty fancy =
machines=20
around now that can give you a very much<BR>clearer view of the =
balls=20
than is normally the case ... if you have cash=20
to<BR>splash!<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
Peter=20
=
Lee<BR> =
=20
<ppwlee@YAHOO =20
To: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><BR> &=
nbsp; &n=
bsp; =20
=
.COM>  =
; =20
cc: (bcc: DUNCAN Peter/Asst<BR>Prin=20
=
Engr/ST<BR> &n=
bsp; =20
Sent=20
=
by: &nbs=
p;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
=
TechNet =
=20
Subject: [TN] BGA=20
=
voids<BR> &nbs=
p; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/16/01<BR> &=
nbsp; =20
04:25=20
=
PM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
=
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am=20
encountering voids after reflow on several micro BGAs on one=20
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray)=20
contribute to as<BR>high as<BR>60-70% of the joint area. My =
reflow=20
profile was designed by running a<BR>sample board with dummy =
components=20
and thermalcouples attached right at the<BR>joint. I also =
inspected the=20
PCB lands and didn $B!G (Bt see any via on=20
pad.<BR><BR><BR><BR><BR><BR>Does anyone know the possible =
reasons for=20
voids formation in BGA =
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In=20
general, in step by step how would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
This=20
e-mail is confidential and may also be privileged. If you are =
not=20
the<BR>intended recipient, please delete it and notify us =
immediately;=20
you should<BR>not copy or use it for any purpose, nor disclose =
its=20
contents to any other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
----------------<BR>-----<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
unsubscribe, send a message to <A=20
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Date: Mon, 19 Nov 2001 12:42:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Colby <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
The rule of thumb, as I understand it, is 80% of the smallest ball size or
preferably the same size as the substrate land. The object being to control
the collapse of the solderball.
If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a
pad size of 0.4-0.5mm?
At 10:40 AM 11/19/01 -0600, you wrote:
>Date: Mon, 19 Nov 2001 07:42:59 -0800
>From: Denis Lefebvre <[log in to unmask]>
>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
> (#2001-713)
>
>As a layout designer, I am surprised that they used such small land areas.
>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
>See attached PDF from Motorola.
>
>Denis Lefebvre, C.I.D.
>Senior PCB Designer
>Finisar Corporation
>(408)542-3832
>http://www.finisar.com
>
>At 10:16 AM 11/19/2001 -0500, you wrote:
> >I'm not that far up in the food chain to know all of the particulars, but
> >it wouldn't surprise me if that were the case.
> >
> >What I'm looking for is comments on the increase of pad size and
> >corroboration in my belief that it's the wrong solution to this problem.
> >
> >Tom
> >
> >At 04:20 AM 11/19/01 -0600, you wrote:
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> >>From: Eric Dawson <[log in to unmask]>
> >>Subject: Re: BGA bone of contention
> >>
> >>Hi Tom,
> >>Are you wave soldering the other side of the board with the reflow soldered
> >>bga.s on top? I have come across this practice and it definitely disturbs
> >>the bga joints causing opens which cannot be detected by ordinary X ray
> >>inspection.
> >>Hope this helps.
> >>Regards
> >>Eric Dawson
> >>
> >> > -----Original Message-----
> >> > From: Tom Colby [SMTP:[log in to unmask]]
> >> > Sent: Friday, November 16, 2001 8:47 PM
> >> > To: [log in to unmask]
> >> > Subject: [TN] BGA bone of contention
> >> >
> >> > Help me out with this technetters,
> >> >
> >> > The problem: BGA opens on a HASL board.
> >> >
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a
> pad of
> >> > 0.28mm.
> >> >
> >> > Management's solution is to increase the pad size to 0.4mm. I say to
> look
> >> > elsewhere in the process for the problem.
> >> >
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you say
> >> > folks?
> >> >
> >> > Thanks in advance,
> >> >
> >> > Tom
> >> >
> >> >
> --------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 10:41:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
What is the recommended pre-bake of multilayer boards prior to insertion and
wave. 221F for 1hour??? Or would this be a little extreme?
Thanks,
Rick
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Date: Mon, 19 Nov 2001 12:56:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul <[log in to unmask]>
Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
issue (#2001-713)
MIME-Version: 1.0
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In reference to the pad layout for the Motorola MCF5272, from many years
of experience in process engineering within a prominent PCB layout design
firm, a pad design of .28mm on this device would warrant extensive process
control to provide for an exceptable yield of soldering this device.
1. This would force manufacturing to perform solder paste stenciling thru
.28mm round apertures.(very difficult)
2. Secondly, If pcb is HASL processed, excess solder could hinder an
already difficult process of paste stenciling.
3. Mechanical reliability of these solder joints would be questionable in
my opinion because of the small surface area provided on the pcb.
4. Component mounting would have to be very accurate and repeatable since
the small surface area on the pcb would decrease the dynamic centering where
BGAs would center on solder reflow.
In conclusion, I think that Motorola recommends approximately .5mm pad
layout and .35mm via pad connections. Our designers would probably follow
what Motorola has recommended and we would require a reputable pcb house
that had good controls over its HASL process or require a different pcb
process that would provide flatter pad surfaces.
Paul Peltier,
Senior Process Manager
----- Original Message -----
From: Denis Lefebvre <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 19, 2001 10:42 AM
Subject: Re: [TN] TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
issue (#2001-713)
> As a layout designer, I am surprised that they used such small land areas.
> Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
> See attached PDF from Motorola.
>
> Denis Lefebvre, C.I.D.
> Senior PCB Designer
> Finisar Corporation
> (408)542-3832
> http://www.finisar.com
>
> At 10:16 AM 11/19/2001 -0500, you wrote:
> >I'm not that far up in the food chain to know all of the particulars, but
> >it wouldn't surprise me if that were the case.
> >
> >What I'm looking for is comments on the increase of pad size and
> >corroboration in my belief that it's the wrong solution to this problem.
> >
> >Tom
> >
> >At 04:20 AM 11/19/01 -0600, you wrote:
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> >>From: Eric Dawson <[log in to unmask]>
> >>Subject: Re: BGA bone of contention
> >>
> >>Hi Tom,
> >>Are you wave soldering the other side of the board with the reflow
soldered
> >>bga.s on top? I have come across this practice and it definitely
disturbs
> >>the bga joints causing opens which cannot be detected by ordinary X ray
> >>inspection.
> >>Hope this helps.
> >>Regards
> >>Eric Dawson
> >>
> >> > -----Original Message-----
> >> > From: Tom Colby [SMTP:[log in to unmask]]
> >> > Sent: Friday, November 16, 2001 8:47 PM
> >> > To: [log in to unmask]
> >> > Subject: [TN] BGA bone of contention
> >> >
> >> > Help me out with this technetters,
> >> >
> >> > The problem: BGA opens on a HASL board.
> >> >
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a pad
of
> >> > 0.28mm.
> >> >
> >> > Management's solution is to increase the pad size to 0.4mm. I say to
look
> >> > elsewhere in the process for the problem.
> >> >
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you
say
> >> > folks?
> >> >
> >> > Thanks in advance,
> >> >
> >> > Tom
> >> >
> >>
> --------------------------------------------------------------------------
> >
>
>---------------------------------------------------------------------------
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>
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Date: Mon, 19 Nov 2001 13:09:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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Date: Mon, 19 Nov 2001 10:22:56 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
I guess that's a good question for Motorola.
We (designers) have used a "rule of thumb" that says the land size should
be no larger than 1/2 of the ball pitch. Diameter .4mm fits that rule. I
cannot testify as to whether or not it's a good rule... I'm just parroting
what I've been told. We also TEND to follow the manufacturer's
recommendations (when they are given).
-Denis
At 12:42 PM 11/19/2001 -0500, you wrote:
>The rule of thumb, as I understand it, is 80% of the smallest ball size or
>preferably the same size as the substrate land. The object being to control
>the collapse of the solderball.
>
>If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a
>pad size of 0.4-0.5mm?
>
>At 10:40 AM 11/19/01 -0600, you wrote:
>>Date: Mon, 19 Nov 2001 07:42:59 -0800
>>From: Denis Lefebvre <[log in to unmask]>
>>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue
>> (#2001-713)
>>
>>As a layout designer, I am surprised that they used such small land areas.
>>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.
>>See attached PDF from Motorola.
>>
>>Denis Lefebvre, C.I.D.
>>Senior PCB Designer
>>Finisar Corporation
>>(408)542-3832
>>http://www.finisar.com
>>
>>At 10:16 AM 11/19/2001 -0500, you wrote:
>> >I'm not that far up in the food chain to know all of the particulars, but
>> >it wouldn't surprise me if that were the case.
>> >
>> >What I'm looking for is comments on the increase of pad size and
>> >corroboration in my belief that it's the wrong solution to this problem.
>> >
>> >Tom
>> >
>> >At 04:20 AM 11/19/01 -0600, you wrote:
>> >>Date: Mon, 19 Nov 2001 08:20:31 -0000
>> >>From: Eric Dawson <[log in to unmask]>
>> >>Subject: Re: BGA bone of contention
>> >>
>> >>Hi Tom,
>> >>Are you wave soldering the other side of the board with the reflow
>> soldered
>> >>bga.s on top? I have come across this practice and it definitely disturbs
>> >>the bga joints causing opens which cannot be detected by ordinary X ray
>> >>inspection.
>> >>Hope this helps.
>> >>Regards
>> >>Eric Dawson
>> >>
>> >> > -----Original Message-----
>> >> > From: Tom Colby [SMTP:[log in to unmask]]
>> >> > Sent: Friday, November 16, 2001 8:47 PM
>> >> > To: [log in to unmask]
>> >> > Subject: [TN] BGA bone of contention
>> >> >
>> >> > Help me out with this technetters,
>> >> >
>> >> > The problem: BGA opens on a HASL board.
>> >> >
>> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of
>> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a
>>pad of
>> >> > 0.28mm.
>> >> >
>> >> > Management's solution is to increase the pad size to 0.4mm. I say to
>>look
>> >> > elsewhere in the process for the problem.
>> >> >
>> >> > I'd like to hear the opinions of my esteemed colleagues. What do
>> you say
>> >> > folks?
>> >> >
>> >> > Thanks in advance,
>> >> >
>> >> > Tom
>> >> >
>> >> >
>>--------------------------------------------------------------------------
>
>---------------------------------------------------------------------------------
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Date: Mon, 19 Nov 2001 14:20:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: ion chromatography
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
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Good day TechNet
I'm looking for a recommendation for a lab to do ion chromatography =
testing for me. Small job, 3 lots of 4 pieces each. I'm looking to =
verify that our cleaning process can properly clean under a BGA module.
Reminder - anyone recommending themselves - no ads on TechNet, please =
contact me direct.
Thanks!
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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Date: Mon, 19 Nov 2001 14:46:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Re: ion chromatography
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Graham,
You could try http://www.tracelaboratories.com/ or IBM labs in Bromont (not
sure if they do chromatography testing) at 1 888 IBM LABO ( 1 888 426-5226 )
Regards,
Mario Dion
Prod. Technologist
Mediatrix Telecom Inc
-----Original Message-----
From: Graham Collins [mailto:[log in to unmask]]
Sent: 19 novembre, 2001 14:20
To: [log in to unmask]
Subject: [TN] ion chromatography
Good day TechNet
I'm looking for a recommendation for a lab to do ion chromatography testing
for me. Small job, 3 lots of 4 pieces each. I'm looking to verify that our
cleaning process can properly clean under a BGA module.
Reminder - anyone recommending themselves - no ads on TechNet, please
contact me direct.
Thanks!
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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Date: Mon, 19 Nov 2001 15:30:05 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: ion chromatography
MIME-Version: 1.0
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In the past I have regularly used CSL in kokomo IN for this work.
Jon Moore
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Date: Mon, 19 Nov 2001 15:41:07 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jan Satterfield <[log in to unmask]>
Subject: Circuit Repair Facility
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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Date: Mon, 19 Nov 2001 15:17:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David North <[log in to unmask]>
Subject: Re: Circuit Repair Facility
In-Reply-To: <[log in to unmask]>
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If you can't find someone in the Salt Lake City area, there's a company in
Seattle, Schippers & Crew, Inc. that recently introduced a service to do
this. 206-782-2325.
David North
Qualitel Corporation
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jan Satterfield
Sent: Monday, November 19, 2001 2:41 PM
To: [log in to unmask]
Subject: [TN] Circuit Repair Facility
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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Date: Mon, 19 Nov 2001 18:34:36 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Circuit Repair Facility
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_b9.16fb3357.292af10c_boundary"
--part1_b9.16fb3357.292af10c_boundary
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Hi Jan!
Why send them out when you can do it yourself? Go to:
http://www.hunterproducts.com/micro-metallizer.htm
I've got their system and it works like a charm...you'll get a nickel plating
pen, and a gold pen. There's really good instructions that come with the
system, even a knot-head like me can use it hehehe....you can do a finger in
about 10-minutes.
The thing I like about their system is that all the plating solutions are in
self-contained pens, so you don't have to worry about spilling it.
-Steve Gregory-
> My company was using Pacific Meta Corp for replating of gold fingers after
> solder was accidentally deposited. They are no longer doing repairs. Can
> someone guide me to a new company that can replate a single gold finger.
> We
> are located in Salt Lake City.
> Jan Satterfield
> Process Engineer
> L-3 Communications
>
--part1_b9.16fb3357.292af10c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jan!<BR>
<BR>
Why send them out when you can do it yourself? Go to:<BR>
<BR>
http://www.hunterproducts.com/micro-metallizer.htm<BR>
<BR>
I've got their system and it works like a charm...you'll get a nickel plating pen, and a gold pen. There's really good instructions that come with the system, even a knot-head like me can use it hehehe....you can do a finger in about 10-minutes.<BR>
<BR>
The thing I like about their system is that all the plating solutions are in self-contained pens, so you don't have to worry about spilling it.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">My company was using Pacific Meta Corp for replating of gold fingers after<BR>
solder was accidentally deposited. They are no longer doing repairs. Can<BR>
someone guide me to a new company that can replate a single gold finger. We<BR>
are located in Salt Lake City.<BR>
Jan Satterfield<BR>
Process Engineer<BR>
L-3 Communications<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_b9.16fb3357.292af10c_boundary--
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Date: Mon, 19 Nov 2001 19:22:55 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: CCGA's, the good, the bad, and the ugly...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi all!
May be getting the opportunity to assemble some boards with CCGA's on them.
Don't have any direct experience with these puppies. Downloaded IBM's
application *.PDF on assembling and reworking them (it's pretty good by the
way), and seems that basically, you would do the same thing assembling these
guys as you do when working with BGA's...am I over-simplifiying things too
much?
Any advice, or "gotcha's" I should look out for would be appreciated...
As always, thanks a bunch!!!
-Steve Gregory-
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Date: Tue, 20 Nov 2001 08:37:30 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
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> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] No power on after underfill
>=20
> Hi, Joseph,
>=20
> I cannot find the 3513 material data sheet, but that probably doesn't
> matter. The main thing I can think of that would cause your problem is
> the
> thermal excursions needed to apply and cure the underfill. Am I
> correct to
> say that the boards passed test at room temperature before the
> underfill is
> applied?
>=20
> You may have a manufacturing problem where the balls make contact
> enough to
> pass test, but fail at elevated temperature. I would try testing the
> boards
> at 100 or 115 degrees C prior to underfilling them and see if they
> still
> pass. If they do, but fail again after underfilling, then the problem
> is
> probably related to your underfilling process. It is quite easy to
> apply
> too much if you're not using an automated process or have not
> correctly
> calculated the amount of material to apply. It does flow more prior to
> curing at curing temperature, and if it's getting into nearby
> interface
> contacts as a result, you will need to look at damming the area around
> the
> BGA with a peelable masking to contain the underfill until it's cured,
> or
> reducing the amount of material applied.
>=20
> One other thing might be contamination under the BGA. If you have any
> conductive residues left on the board, especially if you use no-clean
> soldering processes, they may be picked up by the underfill and
> there's a
> chance you're suffering from short circuits through the increased
> conductivity of the epoxy. It's very important to the performance of
> the
> underfill that the underneath of the BGA's are very clean.
>=20
> Hope this gives you some clues and you find a solution.
>=20
> Peter Duncan
>=20
>=20
>=20
>=20
> "Joseph H.
> Smith" To: [log in to unmask]
> <Tony_Zhang@H cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> ZMOT.COM> Aero/ST Group)
> Sent by: Subject: [TN] No power on
> after underfill
> TechNet
> <[log in to unmask]
> ORG>
>=20
>=20
> 11/19/01
> 03:48 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>=20
>=20
>=20
>=20
>=20
>=20
> Pls help me to solve this issue
>=20
>=20
> We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
> 3513
> and the curing condition is 115C , 15 minutes , the BGA' s package is
> below
> .
>=20
>=20
> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ;bump array 10*10
> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ; bump array 14*14
>=20
>=20
> Before the underfilll we check the electric function .All are good
> ones .
> But after curing , some phone failed because "can not power on ", and
> some
> failed for "check SIM card ", the defect sample is closed to 3%. I
> think
> "check card "issue" may caused by the underfill material emission
> which
> cover the SIM card lead .
>=20
>=20
> But I can not get any idea for further.
>=20
>=20
> Thanks
> Tony
>=20
>=20
>=20
>=20
>=20
>=20
>=20
> [This e-mail is confidential and may also be privileged. If you are
> not the
> intended recipient, please delete it and notify us immediately; you
> should
> not copy or use it for any purpose, nor disclose its contents to any
> other
> person. Thank you.]
>=20
> ----------------------------------------------------------------------
> -----------
> Technet Mail List provided as a free service by IPC using LISTSERV
> 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text
> in
> the BODY (NOT the subject field): SIGNOFF Technet
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> SET Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources &
> Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or
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> ----------------------------------------------------------------------
> -----------
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<HTML>
<HEAD>
<TITLE>RE: Re: [TN] No power on after underfill</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<BR>
<BR>
<UL>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D1 FACE=3D"Arial">-----Original =
Message-----</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">From: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial"><Peter George Duncan> =
[SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Sent: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Monday, November 19, 2001 10:27 AM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Subject: </FONT><=
/B> <FONT SIZE=3D1 FACE=3D"Arial"> Re: [TN] No =
power on after underfill</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Hi, =
Joseph,</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">I cannot find the =
3513 material data sheet, but that probably doesn't</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">matter. The main =
thing I can think of that would cause your problem is the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">thermal =
excursions needed to apply and cure the underfill. Am I correct =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">say that the =
boards passed test at room temperature before the underfill =
is</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">applied?</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">You may have a =
manufacturing problem where the balls make contact enough =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pass test, but =
fail at elevated temperature. I would try testing the =
boards</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">at 100 or 115 =
degrees C prior to underfilling them and see if they still</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pass. If they =
do, but fail again after underfilling, then the problem is</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">probably related =
to your underfilling process. It is quite easy to apply</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">too much if =
you're not using an automated process or have not =
correctly</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">calculated the =
amount of material to apply. It does flow more prior to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">curing at curing =
temperature, and if it's getting into nearby interface</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">contacts as a =
result, you will need to look at damming the area around =
the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">BGA with a =
peelable masking to contain the underfill until it's cured, =
or</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">reducing the =
amount of material applied.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">One other thing =
might be contamination under the BGA. If you have any</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">conductive =
residues left on the board, especially if you use no-clean</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">soldering =
processes, they may be picked up by the underfill and there's =
a</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">chance you're =
suffering from short circuits through the increased</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">conductivity of =
the epoxy. It's very important to the performance of the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">underfill that =
the underneath of the BGA's are very clean.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Hope this gives =
you some clues and you find a solution.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Peter =
Duncan</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; "Joseph =
H.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Smith" &n=
bsp; To: =
[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
<Tony_Zhang@H =
cc: (bcc: DUNCAN Peter/Asst Prin =
Engr/ST</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
ZMOT.COM> &=
nbsp; Aero/ST Group)</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; Sent =
by: &nbs=
p; Subject: [TN] No power on after =
underfill</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
TechNet</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
<[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
ORG></FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
11/19/01</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; 03:48 =
PM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Please</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; respond =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
"TechNet</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
E-Mail</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Forum."</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Pls help me to =
solve this issue</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">We use undefilll =
for two BGA in one product ,the epoxy is Loctite LPD 3513</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">and the curing =
condition is 115C , 15 minutes , the BGA' s package is =
below</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> U3 information : Body =
size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pitch, 0.8*0.8 =
;bump array 10*10</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> U1 information : Body =
size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pitch, 0.8*0.8 ; =
bump array 14*14</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Before the =
underfilll we check the electric function .All are good ones =
.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">But after curing =
, some phone failed because "can not power on ", and =
some</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">failed for =
"check SIM card ", the defect sample is closed to 3%. I =
think</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">"check card =
"issue" may caused by the underfill material emission =
which</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">cover the SIM =
card lead .</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">But I can not get =
any idea for further.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">Thanks</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">Tony</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">[This e-mail is =
confidential and may also be privileged. If you are not =
the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">intended =
recipient, please delete it and notify us immediately; you =
should</FONT></SPAN>
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Date: Tue, 20 Nov 2001 08:58:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: No power on after underfill
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1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and
the solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill 50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no
effective
4. what is conductive residues when we applying no-clean soldering
process ?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony=20
> -----Original Message-----
> From: <Peter George Duncan> [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] No power on after underfill
>=20
> Hi, Joseph,
>=20
> I cannot find the 3513 material data sheet, but that probably doesn't
> matter. The main thing I can think of that would cause your problem is
> the
> thermal excursions needed to apply and cure the underfill. Am I
> correct to
> say that the boards passed test at room temperature before the
> underfill is
> applied?
>=20
> You may have a manufacturing problem where the balls make contact
> enough to
> pass test, but fail at elevated temperature. I would try testing the
> boards
> at 100 or 115 degrees C prior to underfilling them and see if they
> still
> pass. If they do, but fail again after underfilling, then the problem
> is
> probably related to your underfilling process. It is quite easy to
> apply
> too much if you're not using an automated process or have not
> correctly
> calculated the amount of material to apply. It does flow more prior to
> curing at curing temperature, and if it's getting into nearby
> interface
> contacts as a result, you will need to look at damming the area around
> the
> BGA with a peelable masking to contain the underfill until it's cured,
> or
> reducing the amount of material applied.
>=20
> One other thing might be contamination under the BGA. If you have any
> conductive residues left on the board, especially if you use no-clean
> soldering processes, they may be picked up by the underfill and
> there's a
> chance you're suffering from short circuits through the increased
> conductivity of the epoxy. It's very important to the performance of
> the
> underfill that the underneath of the BGA's are very clean.
>=20
> Hope this gives you some clues and you find a solution.
>=20
> Peter Duncan
>=20
>=20
>=20
>=20
> "Joseph H.
> Smith" To: [log in to unmask]
> <Tony_Zhang@H cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> ZMOT.COM> Aero/ST Group)
> Sent by: Subject: [TN] No power on
> after underfill
> TechNet
> <[log in to unmask]
> ORG>
>=20
>=20
> 11/19/01
> 03:48 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>=20
>=20
>=20
>=20
>=20
>=20
> Pls help me to solve this issue
>=20
>=20
> We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
> 3513
> and the curing condition is 115C , 15 minutes , the BGA' s package is
> below
> .
>=20
>=20
> U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ;bump array 10*10
> U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
> 0.3 ;
> pitch, 0.8*0.8 ; bump array 14*14
>=20
>=20
> Before the underfilll we check the electric function .All are good
> ones .
> But after curing , some phone failed because "can not power on ", and
> some
> failed for "check SIM card ", the defect sample is closed to 3%. I
> think
> "check card "issue" may caused by the underfill material emission
> which
> cover the SIM card lead .
>=20
>=20
> But I can not get any idea for further.
>=20
>=20
> Thanks
> Tony
>=20
>=20
>=20
>=20
>=20
>=20
>=20
> [This e-mail is confidential and may also be privileged. If you are
> not the
> intended recipient, please delete it and notify us immediately; you
> should
> not copy or use it for any purpose, nor disclose its contents to any
> other
> person. Thank you.]
>=20
> ----------------------------------------------------------------------
> -----------
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or
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------_=_NextPart_001_01C1715E.7979C9F0
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charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<TITLE>RE: Re: [TN] No power on after underfill</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->
<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">1.The PCB we use is Ni/Au but there is Tin plated on the BGA =
side and the solder paster type is Alpha RMA 9147</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">2. we have done the experiement for letting the epoxy only =
underfill 50% BGA size , the result is still bad</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">3. we reduce the curing temperature from 150 C to 120C =
, also no effective</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">4. what is</FONT> <FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Times New Roman">conductive residues when we applying no-clean =
soldering process ?</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">By the way, if you need MDS of 3513, I can send to you =
.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">Thanks for your great help.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">Tony</FONT> </SPAN>
<UL>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D1 FACE=3D"Arial">-----Original =
Message-----</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">From: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial"><Peter George Duncan> =
[SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Sent: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Monday, November 19, 2001 10:27 AM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Subject: </FONT><=
/B> <FONT SIZE=3D1 FACE=3D"Arial"> Re: [TN] No =
power on after underfill</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Hi, =
Joseph,</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">I cannot find the =
3513 material data sheet, but that probably doesn't</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">matter. The main =
thing I can think of that would cause your problem is the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">thermal =
excursions needed to apply and cure the underfill. Am I correct =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">say that the =
boards passed test at room temperature before the underfill =
is</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">applied?</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">You may have a =
manufacturing problem where the balls make contact enough =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pass test, but =
fail at elevated temperature. I would try testing the =
boards</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">at 100 or 115 =
degrees C prior to underfilling them and see if they still</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pass. If they =
do, but fail again after underfilling, then the problem is</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">probably related =
to your underfilling process. It is quite easy to apply</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">too much if =
you're not using an automated process or have not =
correctly</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">calculated the =
amount of material to apply. It does flow more prior to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">curing at curing =
temperature, and if it's getting into nearby interface</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">contacts as a =
result, you will need to look at damming the area around =
the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">BGA with a =
peelable masking to contain the underfill until it's cured, =
or</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">reducing the =
amount of material applied.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">One other thing =
might be contamination under the BGA. If you have any</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">conductive =
residues left on the board, especially if you use no-clean</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">soldering =
processes, they may be picked up by the underfill and there's =
a</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">chance you're =
suffering from short circuits through the increased</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">conductivity of =
the epoxy. It's very important to the performance of the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">underfill that =
the underneath of the BGA's are very clean.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Hope this gives =
you some clues and you find a solution.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Peter =
Duncan</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; "Joseph =
H.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Smith" &n=
bsp; To: =
[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
<Tony_Zhang@H =
cc: (bcc: DUNCAN Peter/Asst Prin =
Engr/ST</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
ZMOT.COM> &=
nbsp; Aero/ST Group)</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; Sent =
by: &nbs=
p; Subject: [TN] No power on after =
underfill</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
TechNet</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
<[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
ORG></FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
11/19/01</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; 03:48 =
PM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Please</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; respond =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
"TechNet</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
E-Mail</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> &nb=
sp; =
Forum."</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Pls help me to =
solve this issue</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">We use undefilll =
for two BGA in one product ,the epoxy is Loctite LPD 3513</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">and the curing =
condition is 115C , 15 minutes , the BGA' s package is =
below</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> U3 information : Body =
size, 9*9mm ; height 1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pitch, 0.8*0.8 =
;bump array 10*10</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun"> U1 information : Body =
size, 12*12 ; heigh t1.7 ; bump diameter 0.3 ;</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pitch, 0.8*0.8 ; =
bump array 14*14</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">Before the =
underfilll we check the electric function .All are good ones =
.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">But after curing =
, some phone failed because "can not power on ", and =
some</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">failed for =
"check SIM card ", the defect sample is closed to 3%. I =
think</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">"check card =
"issue" may caused by the underfill material emission =
which</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">cover the SIM =
card lead .</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">But I can not get =
any idea for further.</FONT></SPAN>
</P>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">Thanks</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">Tony</FONT></SPAN>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>
<BR>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">[This e-mail is =
confidential and may also be privileged. If you are not =
the</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">intended =
recipient, please delete it and notify us immediately; you =
should</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">not copy or use =
it for any purpose, nor disclose its contents to any other</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">person. Thank =
you.]</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">---------------------------------------------------------=
------------------------</FONT></SPAN>
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=========================================================================
Date: Tue, 20 Nov 2001 10:16:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Joseph H. Smith" <[log in to unmask]>
Subject: Re: BGA bone of contention
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As I know, 80% of the smallest ball size or preferably the same size
should be as the stencil aperture size not as the pad size.
> -----Original Message-----
> From: Tom Colby [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 5:42 PM
> To: [log in to unmask]
> Subject: Re: [TN] BGA bone of contention
>=20
> The rule of thumb, as I understand it, is 80% of the smallest ball
> size or
> preferably the same size as the substrate land. The object being to
> control
> the collapse of the solderball.
>=20
> If the minimum ball size is 0.35mm, how can you (or Mortorola) justify
> a
> pad size of 0.4-0.5mm?
>=20
> At 10:40 AM 11/19/01 -0600, you wrote:
> >Date: Mon, 19 Nov 2001 07:42:59 -0800
> >From: Denis Lefebvre <[log in to unmask]>
> >Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special
> issue
> > (#2001-713)
> >
> >As a layout designer, I am surprised that they used such small land
> areas.
> >Motorola recommends a land of .40 to .50mm. IMO .28mm is
> insufficient.
> >See attached PDF from Motorola.
> >
> >Denis Lefebvre, C.I.D.
> >Senior PCB Designer
> >Finisar Corporation
> >(408)542-3832
> >http://www.finisar.com
> >
> >At 10:16 AM 11/19/2001 -0500, you wrote:
> > >I'm not that far up in the food chain to know all of the
> particulars, but
> > >it wouldn't surprise me if that were the case.
> > >
> > >What I'm looking for is comments on the increase of pad size and
> > >corroboration in my belief that it's the wrong solution to this
> problem.
> > >
> > >Tom
> > >
> > >At 04:20 AM 11/19/01 -0600, you wrote:
> > >>Date: Mon, 19 Nov 2001 08:20:31 -0000
> > >>From: Eric Dawson <[log in to unmask]>
> > >>Subject: Re: BGA bone of contention
> > >>
> > >>Hi Tom,
> > >>Are you wave soldering the other side of the board with the reflow
> soldered
> > >>bga.s on top? I have come across this practice and it definitely
> disturbs
> > >>the bga joints causing opens which cannot be detected by ordinary
> X ray
> > >>inspection.
> > >>Hope this helps.
> > >>Regards
> > >>Eric Dawson
> > >>
> > >> > -----Original Message-----
> > >> > From: Tom Colby [SMTP:[log in to unmask]]
> > >> > Sent: Friday, November 16, 2001 8:47 PM
> > >> > To: [log in to unmask]
> > >> > Subject: [TN] BGA bone of contention
> > >> >
> > >> > Help me out with this technetters,
> > >> >
> > >> > The problem: BGA opens on a HASL board.
> > >> >
> > >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball
> size of
> > >> > 0.35/0.65. Substrate land size unknown. Footprint designed with
> a
> > pad of
> > >> > 0.28mm.
> > >> >
> > >> > Management's solution is to increase the pad size to 0.4mm. I
> say to
> > look
> > >> > elsewhere in the process for the problem.
> > >> >
> > >> > I'd like to hear the opinions of my esteemed colleagues. What
> do you say
> > >> > folks?
> > >> >
> > >> > Thanks in advance,
> > >> >
> > >> > Tom
> > >> >
> > >> >
> >
> ----------------------------------------------------------------------
> ----
>=20
> ----------------------------------------------------------------------
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<P><SPAN LANG=3D"en-us"><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Times =
New Roman">As I know, 80% of the smallest ball size or preferably the =
same size should be as the stencil aperture size not as the pad =
size.</FONT></SPAN></P>
<UL>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D1 FACE=3D"Arial">-----Original =
Message-----</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">From: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Tom Colby [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Sent: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">Monday, November 19, 2001 5:42 PM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D1 =
FACE=3D"Arial">[log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><B><FONT SIZE=3D1 =
FACE=3D"Arial">Subject: </FONT><=
/B> <FONT SIZE=3D1 FACE=3D"Arial"> Re: [TN] BGA =
bone of contention</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">The rule of =
thumb, as I understand it, is 80% of the smallest ball size =
or</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">preferably the =
same size as the substrate land. The object being to =
control</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">the collapse of =
the solderball.</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">If the minimum =
ball size is 0.35mm, how can you (or Mortorola) justify a</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">pad size of =
0.4-0.5mm?</FONT></SPAN>
</P>
<P><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">At 10:40 AM =
11/19/01 -0600, you wrote:</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">>Date: Mon, 19 Nov 2001 07:42:59 =
-0800</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">>From: Denis Lefebvre =
<[log in to unmask]></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>Subject: Re: =
TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special =
issue</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">>  =
; (#2001-713)</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>As a layout =
designer, I am surprised that they used such small land =
areas.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>Motorola =
recommends a land of .40 to .50mm. IMO .28mm is =
insufficient.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>See attached =
PDF from Motorola.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>Denis =
Lefebvre, C.I.D.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>Senior PCB =
Designer</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>Finisar =
Corporation</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">>(408)542-3832</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">><U></U></FONT><U><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"SimSun"><A =
HREF=3D"http://www.finisar.com">http://www.finisar.com</A></FONT></U></SP=
AN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"SimSun">></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">>At 10:16 AM =
11/19/2001 -0500, you wrote:</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >I'm not =
that far up in the food chain to know all of the particulars, =
but</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >it =
wouldn't surprise me if that were the case.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >What =
I'm looking for is comments on the increase of pad size =
and</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>corroboration in my belief that it's the wrong solution to this =
problem.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>Tom</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >At =
04:20 AM 11/19/01 -0600, you wrote:</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>Date: Mon, 19 Nov 2001 08:20:31 =
-0000</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>From: Eric Dawson =
<[log in to unmask]></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>Subject: Re: BGA bone of contention</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >>Hi =
Tom,</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >>Are =
you wave soldering the other side of the board with the reflow =
soldered</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>bga.s on top? I have come across this practice and it definitely =
disturbs</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >>the =
bga joints causing opens which cannot be detected by ordinary X =
ray</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>inspection.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>Hope this helps.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>Regards</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>>Eric Dawson</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
>></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> -----Original Message-----</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> From: Tom Colby [SMTP:[log in to unmask]]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Sent: Friday, November 16, 2001 8:47 PM</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> To: [log in to unmask]</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Subject: [TN] BGA bone of =
contention</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Help me out with this technetters,</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> The problem: BGA opens on a HASL board.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size =
of</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> 0.35/0.65. Substrate land size unknown. Footprint designed with =
a</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> pad =
of</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> 0.28mm.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Management's solution is to increase the pad size to 0.4mm. I say =
to</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
look</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> elsewhere in the process for the problem.</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> I'd like to hear the opinions of my esteemed colleagues. What do =
you say</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> folks?</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Thanks in advance,</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
> Tom</FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> >> =
></FONT></SPAN>
<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"SimSun">> =
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=========================================================================
Date: Tue, 20 Nov 2001 11:47:26 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Mario,
Don't you carry out EMC/EMI test on your products to determine if they are
sensitive to incoming radiation? Try taking a few working examples along to
your local airport and ask to have them put through the X-ray machines a
few times, then see if they still work afterwards. Easier to do first than
doing a whole lot of theoretical research which may show nothing in the
end.
Good luck
Peter Duncan
Mario Dion
<mdion@MEDIAT To: [log in to unmask]
RIX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Is X-RAY can damaged Flash IC
<[log in to unmask] i.e. imbeded program ?
ORG>
11/19/01
11:21 PM
Please
respond to
"TechNet
E-Mail
Forum."
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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Date: Tue, 20 Nov 2001 12:12:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Our std at BAE Systems was 90 deg C (194 F) for 1 hour, though since I have
achieved greater enlightenment, I would suggest that you have your boards
packed by your fab house in sealed bags with desiccant, you keep them in a
dry cabinet and that you don't open them until needed on the line. That way
you won't have to pre-bake them, and they won't have to go through an
avoidable thermal excursion.
Peter Duncan
Rick Howieson
<RHowieson@DELTAGRO To: [log in to unmask]
UPINC.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Pre-bake
11/20/01 01:41 AM
Please respond to
"TechNet E-Mail
Forum."
What is the recommended pre-bake of multilayer boards prior to insertion
and
wave. 221F for 1hour??? Or would this be a little extreme?
Thanks,
Rick
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Date: Tue, 20 Nov 2001 13:02:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
A very big thanks to you all, especially Edward, Rummy, Hans, Jeff, Moonman
and many others for all the help and advice I've received on this topic. In
spite of Moonman's reaching near-critical mass to start with, this thread
became a rope, so there was obviously a lot of information and several
issues that were worth sharing.
I had a long and expensive discussion by phone with the fab house this
morning and they're proceeding with conventional sequential lamination of
the boards with selective plating of holes and pads. At each stage they
will grind the plated copper off the pads on each side of the laminated
stack to maintain thickness until they get to the final, through-hole
group, where the plating will be left to bring the outer surface copper
weight up to intended design thickness. They are now very confident about
being able to produce good boards, though why they couldn't have done all
this to start with and saved me a lot of grief and black marks, I can't
say.
I will follow up Hans's lead on plating holes only, not surface pads, as
this would obviously be an ideal solution for this type of board, as long
as the hole plating still connects well with the inner edge of the pads on
the outer layers. It sounds as though it will save a lot of process time
and reduce risk by removing the unnecessary filling and grinding
operations, which are what has extended the time of the third attempt to
make these boards.
I join those who have gone before me in being in the position of having
received tremendous support, and no small amount of valuable help. My
heartfelt gratitude and thanks to all the TNagers for their generosity.
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Over-etch II
<[log in to unmask]>
11/20/01 02:09 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass
Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The
down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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Date: Tue, 20 Nov 2001 13:40:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hmmm! I can't see anything in your points 1 to 3 that would directly cause
you any trouble, and the conductive residues I had in mind ranged from
ionic contaminants on the surfaces to any solder balls that might have
become lodged underneath.
You didn't answer if you've tried testing at elevated temperature prior to
underfilling, and one thing I didn't ask (because I 99.99...% know the
answer) is are your devices hermetically sealed? I'ld try doing a
cross-section of some of the BGA's that failed after underfilling and see
if any of the epoxy has got inside and damaged anything.
More things spring to mind - like did you bake out the assemblies prior to
underfilling? The Dexter Hysol (sorry, Loctite) underfill that I use
recommends pre-baking of assemblies prior to underfilling. If the BGA's
have been out of their bag longer than a couple of days before
underfilling, they have probably absorbed a lot of moisture. I can't say
for sure what effect heating moisture-laden components to 120 or even 150
deg for 20 minutes or so would have, but your 3% may have suffered some
delam at some point. Or it may be warping and breaking/losing contact and
underfill is getting between the contact surfaces and isolating them.
Cross-sectioning and analysis should show this up too.
About tapped out of ideas again for now. Good luck with your search for a
cause - I'ld be interested in hearing what you find.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] No power on after underfill
TechNet
<[log in to unmask]
ORG>
11/20/01
08:58 AM
Please
respond to
"TechNet
E-Mail
Forum."
1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and the
solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill 50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no effective
4. what is conductive residues when we applying no-clean soldering process
?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony
-----Original Message-----
From: <Peter George Duncan> [SMTP:[log in to unmask]]
Sent: Monday, November 19, 2001 10:27 AM
To: [log in to unmask]
Subject: Re: [TN] No power on after underfill
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably doesn't
matter. The main thing I can think of that would cause your problem is
the
thermal excursions needed to apply and cure the underfill. Am I
correct to
say that the boards passed test at room temperature before the
underfill is
applied?
You may have a manufacturing problem where the balls make contact
enough to
pass test, but fail at elevated temperature. I would try testing the
boards
at 100 or 115 degrees C prior to underfilling them and see if they
still
pass. If they do, but fail again after underfilling, then the problem
is
probably related to your underfilling process. It is quite easy to
apply
too much if you're not using an automated process or have not
correctly
calculated the amount of material to apply. It does flow more prior to
curing at curing temperature, and if it's getting into nearby
interface
contacts as a result, you will need to look at damming the area around
the
BGA with a peelable masking to contain the underfill until it's cured,
or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have any
conductive residues left on the board, especially if you use no-clean
soldering processes, they may be picked up by the underfill and
there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance of
the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No power on
after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite LPD
3513
and the curing condition is 115C , 15 minutes , the BGA' s package is
below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump diameter
0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are good
ones .
But after curing , some phone failed because "can not power on ", and
some
failed for "check SIM card ", the defect sample is closed to 3%. I
think
"check card "issue" may caused by the underfill material emission
which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
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=========================================================================
Date: Tue, 20 Nov 2001 13:53:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
A very big thanks to you all, especially Edward, Rummy, Hans, Jeff, Moonman
and many others for all the help and advice I've received on this topic. In
spite of Moonman's reaching near-critical mass to start with, this thread
became a rope, so there was obviously a lot of information and several
issues that were worth sharing.
I had a long and expensive discussion by phone with the fab house this
morning and they're proceeding with conventional sequential lamination of
the boards with selective plating of holes and pads. They are now very
confident about being able to produce good boards, though why they couldn't
have done all this to start with and saved me a lot of grief and black
marks, I can't say.
I will follow up Hans's lead on plating holes only, not surface pads, as
this would obviously be an ideal solution for this type of board, as long
as the hole plating still connects well with the inner edge of the pads on
the outer layers. It sounds as though it will save a lot of process time
and reduce risk by removing the unnecessary filling and grinding
operations.
I join those who have gone before me in being in the position of having
received tremendous support, and no small amount of valuable help. My
heartfelt gratitude and thanks to all the TNagers for their generosity.
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Over-etch II
<[log in to unmask]>
11/20/01 02:09 AM
Please respond to
"TechNet E-Mail
Forum."
Hello Peter!
There are several ways to skin this cat (plating-etch dilemma) and it
depends on where you look for the answer.
Short Term - Etch: Assuming there is some uniformity to the thicker copper
plating it could be etched in a double pass
Image-Develop-Etch-Strip-Repeat.
We used to etch the outer portion of the core where the plating was thicker
and then go back to etch the finer circuitry during a second pass. The
down
side was adding processing steps and more handling.
Medium Term - Plating: If the plating distributions are design related then
the plating line needs to be tweaked. Pulse and Reverse -Pulse Plating can
do some amazing things but it takes development time to dial-in.
Long Term Alt. Plating: There are alternatives to Electroless Cu that only
plate the drilled hole not the surface copper. Where's Michael Carano
hiding? He can answer that one in his sleep.
And as you know, once it's over etched your done.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 10:07 PM
To: [log in to unmask]
Subject: Re: [TN] Over-etch II
Hi, Rudy,
Assumption is correct - over-etch occurs in the same place on all boards of
the same design, and is on the patterns. Masked traces are in good
condition. Fab house has not suggested a change of design as a solution to
the problem - in fact they didn't even want the over-etched boards back, so
my belief is that they knew about the problem even before they shipped the
product.
I myself need to learn a lot more about what is a produceable design and
what isn't as far as this sort of thing is concerned, though I would trust
that our board designers should know more about that than I. They
supposedly followed IPC-2221 & 2222 when putting the design together, but
who knows what was missed (if anything).
Does anyone else have this problem with boards with blind vias? Or if it's
DFM'd, what steps were taken to avoid this issue?
Best regards
Peter Duncan
"<Rudy
Sedlak>" To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: Re: [TN] Over-etch II
ORG>
11/16/01
11:23 PM
Please
respond to
"TechNet
E-Mail
Forum."
This MAY be so simple, we will wonder why/how they did not see the
problem...
To understand this analysis/suggestion, you have to understand the
difference
between pattern plating (which is done after photoresist application) and
panel plating (which is done before photoresist application).
Again, I am grasping/guessing here, as I really do not understand the
process
well enough to give "expert" advice....
If they are doing a "selective" panel plate, which would make the Copper
selectively thicker, this would be an obvious answer...
I assume that the over etch problem occurs at the same place on all the
boards of the same design? And it occurs on 100% of the boards of a
similar
design? (In other words, is the problem one of process/board design, or
one
related to equipment used in fabrication?)
If the problem is not always in the same place, this would speak to
equipment
issues at their facility...and even if the the problem occurs at the same
place on all boards, it could still POSSIBLY be equipment issues at the
fabrication facility.
Rudy Sedlak
RD Chemical Company
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=========================================================================
Date: Mon, 19 Nov 2001 22:29:55 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: BGA voids
In-Reply-To: <72F8793F1F00D411BE2D00805FA7C0EBCD7B38@DATRON1>
MIME-Version: 1.0
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boundary="----=_NextPart_000_0001_01C17149.B6C29000"
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How would one rework an assembly with micro BGA voiding due to several
micro vias on pad?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some
sort of Peanut oil... but I can't remember for sure... Those were my
High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the
bear the heat of soldering well?
----- Original Message -----
From: Bob Willis <mailto:[log in to unmask]>
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed in the
years gone bye after it appeared in and Italian PCB specification I was
asked to review. After some testing I did it ended up in the IEC
specification.
The same oil can be used effectivly for outgassing tests with via in
pad. In the last test I did with ten scrap boards dfrom different
suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied to vias
is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
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<body bgcolor=3Dwhite lang=3DEN-US link=3Dblue vlink=3Dblue =
style=3D'tab-interval:.5in'>
<div class=3DSection1>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>How would one rework an assembly =
with
micro BGA voiding due to several micro <span class=3DSpellE>vias</span> =
on pad?<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><span class=3DSpellE><font size=3D2 color=3Dnavy =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;color:navy'>Rgds</span></font=
></span><font
size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial;
color:navy'>,<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>Peter<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'>-----Original =
Message-----<br>
<b><span style=3D'font-weight:bold'>From:</span></b> TechNet
[mailto:[log in to unmask]] <b><span style=3D'font-weight:bold'>On Behalf =
Of </span></b>Brooks,Bill<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> =
</span></font><st1:date
Month=3D"11" Day=3D"19" Year=3D"2001"><font size=3D2 face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'>November 19, =
2001</span></font></st1:date><font
size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour=3D"8" Minute=3D"48"><font size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;
font-family:Tahoma'>8:48 AM</span></font></st1:time><font size=3D2 =
face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'><br>
<b><span style=3D'font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> Re: [TN] AW: =
[TN] BGA
voids</span></font></p>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;color:blue'>We used to make =
PCB's
back in the mid 1970's and used a fusing oil produced by Shell Oil in =
our
Hydro-squeegee. I want to say it was some sort of Peanut oil... but I =
can't
remember for sure... Those were my High School years... =
:)</span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;color:blue'>Good luck... - =
Bill
Brooks</span></font><o:p></o:p></p>
</div>
<blockquote =
style=3D'margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>
<p class=3DMsoNormal =
style=3D'mso-margin-top-alt:0in;margin-right:0in;margin-bottom:
12.0pt;margin-left:.5in'><font size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;
font-family:Tahoma'>-----Original Message-----<br>
<b><span style=3D'font-weight:bold'>From:</span></b> David Fish
[mailto:[log in to unmask]]<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> =
</span></font><st1:date
Month=3D"11" Day=3D"19" Year=3D"2001"><font size=3D2 face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'>Monday, November 19, =
2001</span></font></st1:date><font
size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour=3D"11" Minute=3D"27"><font size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;
font-family:Tahoma'>11:27 AM</span></font></st1:time><font size=3D2 =
face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'><br>
<b><span style=3D'font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> Re: [TN] AW: =
[TN] BGA
voids</span></font><o:p></o:p></p>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>Who are suppliers of =
inspection
quality oils [Canadian Balson??] the bear the heat of soldering =
well?</span></font><o:p></o:p></p>
</div>
<blockquote style=3D'border:none;border-left:solid black =
1.5pt;padding:0in 0in 0in 3.0pt;
margin-left:3.0pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>=
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>----- Original Message =
----- <o:p></o:p></span></font></p>
</div>
<div style=3D'font-color:black'>
<p class=3DMsoNormal =
style=3D'margin-left:.5in;background:#E4E4E4'><b><font size=3D2
face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial;font-weight:bold'>From:</span=
></font></b><font
size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial'> <a
href=3D"mailto:[log in to unmask]" title=3D"[log in to unmask]">Bob =
Willis</a> <o:p></o:p></span></font></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><b><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;font-weight:bold'>To:</span><=
/font></b><font
size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial'> <a
href=3D"mailto:[log in to unmask]" =
title=3D"[log in to unmask]">[log in to unmask]</a> =
<o:p></o:p></span></font></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><b><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;font-weight:bold'>Sent:</span=
></font></b><font
size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial'> </span></font><st1:date
Month=3D"11" Day=3D"19" Year=3D"2001"><font size=3D2 face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial'>Monday, November 19, =
2001</span></font></st1:date><font
size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial'> </span></font><st1:time
Hour=3D"4" Minute=3D"45"><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>4:45 AM</span></font></st1:time><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'><o:p></o:p></span></font></p=
>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><b><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;font-weight:bold'>Subject:</s=
pan></font></b><font
size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial'> Re: [TN]
AW: [TN] BGA voids<o:p></o:p></span></font></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>The outgassin test for =
blowhole in
printed boards was developed in the years gone bye after it appeared in =
and
Italian PCB specification I was asked to review. After some testing I =
did it
ended up in the IEC specification.</span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>The same oil can be used =
effectivly
for outgassing tests with via in pad. In the last test I did with ten =
scrap
boards dfrom different suppliers 2 outgassed on the pads from the =
vias.</span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>The procedure for through =
hole which
could and has been applied to vias is on my web site which is in the =
download
section.</span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial'>Hope this =
helps.</span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'>Bob Willis<br>
Electronic Presentation Services<br>
</span></font><st1:address><st1:Street>2 Fourth Ave</st1:Street>, =
<st1:City>Chelmsford</st1:City></st1:address>,
<st1:place><st1:City>Essex</st1:City>, <st1:PostalCode>CM1 =
4HA</st1:PostalCode>
=
<st1:country-region>England</st1:country-region></st1:place><o:p></o:p></=
p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'>See us at APEX 2002</span></font><font
face=3D"Times New Roman"><span style=3D'font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS PGothic"'> </span></font> <a
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</a><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'><a =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</a><br>
Tel: (44) 01245 351502 Fax: (44) 01245 =
496123<o:p></o:p></span></font></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt;font-family:"Times New =
Roman";mso-ascii-font-family:
"MS PGothic";mso-bidi-font-family:"MS =
PGothic"'> </span></font><o:p></o:p></p>
</div>
<div>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'>Single solution to your seminar, conference =
or
roadshow <a =
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</a><o:p></o:p></span></font></p>
</div>
<blockquote style=3D'border:none;border-left:solid black =
1.5pt;padding:0in 0in 0in 3.0pt;
margin-left:3.0pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt'>=
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"MS PGothic"><span
style=3D'font-size:12.0pt'>---<o:p></o:p></span></font></p>
</blockquote>
</blockquote>
</blockquote>
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=========================================================================
Date: Tue, 20 Nov 2001 07:09:51 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
MIME-Version: 1.0
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If you have voiding from the via due to outgassing you could bake the =
board prior to rework.
You first should ask the question are the voids significant.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Peter Lee=20
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 6:29 AM
Subject: Re: [TN] BGA voids
How would one rework an assembly with micro BGA voiding due to several =
micro vias on pad?
=20
Rgds,
Peter
=20
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
=20
We used to make PCB's back in the mid 1970's and used a fusing oil =
produced by Shell Oil in our Hydro-squeegee. I want to say it was some =
sort of Peanut oil... but I can't remember for sure... Those were my =
High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??] the =
bear the heat of soldering well?
----- Original Message -----=20
From: Bob Willis=20
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
=20
The outgassin test for blowhole in printed boards was developed in =
the years gone bye after it appeared in and Italian PCB specification I =
was asked to review. After some testing I did it ended up in the IEC =
specification.
=20
The same oil can be used effectivly for outgassing tests with via =
in pad. In the last test I did with ten scrap boards dfrom different =
suppliers 2 outgassed on the pads from the vias.
=20
The procedure for through hole which could and has been applied to =
vias is on my web site which is in the download section.
=20
Hope this helps.
=20
=20
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
=20
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
=20
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
=20
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
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<DIV><FONT face=3DArial size=3D2>If you have voiding from the via due to =
outgassing=20
you could bake the board prior to rework.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>You first should ask the question are =
the voids=20
significant.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Peter =
Lee</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, =
2001 6:29=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] BGA =
voids</DIV>
<DIV><BR></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT color=3Dnavy face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: 10pt">How would =
one rework=20
an assembly with micro BGA voiding due to several micro <SPAN=20
class=3DSpellE>vias</SPAN> on pad?<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3Dnavy face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DSpellE><FONT color=3Dnavy =
face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: =
10pt">Rgds</SPAN></FONT></SPAN><FONT=20
color=3Dnavy face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: =
10pt">,<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3Dnavy face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: =
10pt">Peter<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT color=3Dnavy face=3DArial size=3D2><SPAN=20
style=3D"COLOR: navy; FONT-FAMILY: Arial; FONT-SIZE: =
10pt"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3DTahoma =
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">-----Original=20
Message-----<BR><B><SPAN style=3D"FONT-WEIGHT: bold">From:</SPAN></B> =
TechNet=20
[<A href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>] =
<B><SPAN=20
style=3D"FONT-WEIGHT: bold">On Behalf Of =
</SPAN></B>Brooks,Bill<BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">Sent:</SPAN></B> </SPAN></FONT><st1:date =
Year=3D"2001"=20
Day=3D"19" Month=3D"11"><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">November 19,=20
2001</SPAN></FONT></st1:date><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"> =
</SPAN></FONT><st1:time=20
Minute=3D"48" Hour=3D"8"><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">8:48=20
AM</SPAN></FONT></st1:time><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"><BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">To:</SPAN></B> <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">Subject:</SPAN></B> Re: [TN] AW: [TN] BGA=20
voids</SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN style=3D"FONT-SIZE: =
12pt"><o:p> </o:p></SPAN></FONT></P>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT color=3Dblue =
face=3DArial=20
size=3D2><SPAN style=3D"COLOR: blue; FONT-FAMILY: Arial; FONT-SIZE: =
10pt">We used=20
to make PCB's back in the mid 1970's and used a fusing oil produced by =
Shell=20
Oil in our Hydro-squeegee. I want to say it was some sort of Peanut =
oil... but=20
I can't remember for sure... Those were my High School years...=20
:)</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT color=3Dblue =
face=3DArial=20
size=3D2><SPAN style=3D"COLOR: blue; FONT-FAMILY: Arial; FONT-SIZE: =
10pt">Good=20
luck... - Bill Brooks</SPAN></FONT><o:p></o:p></P></DIV>
<BLOCKQUOTE style=3D"MARGIN-BOTTOM: 5pt; MARGIN-RIGHT: 0in; =
MARGIN-TOP: 5pt">
<P class=3DMsoNormal=20
style=3D"MARGIN-BOTTOM: 12pt; MARGIN-LEFT: 0.5in; MARGIN-RIGHT: 0in; =
mso-margin-top-alt: 0in"><FONT=20
face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">-----Original=20
Message-----<BR><B><SPAN style=3D"FONT-WEIGHT: =
bold">From:</SPAN></B> David=20
Fish [mailto:[log in to unmask]]<BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">Sent:</SPAN></B> </SPAN></FONT><st1:date =
Year=3D"2001" Day=3D"19" Month=3D"11"><FONT face=3DTahoma =
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">Monday, November 19,=20
2001</SPAN></FONT></st1:date><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"> =
</SPAN></FONT><st1:time=20
Minute=3D"27" Hour=3D"11"><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt">11:27=20
AM</SPAN></FONT></st1:time><FONT face=3DTahoma size=3D2><SPAN=20
style=3D"FONT-FAMILY: Tahoma; FONT-SIZE: 10pt"><BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">To:</SPAN></B> =
[log in to unmask]<BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">Subject:</SPAN></B> Re: [TN] AW: [TN] =
BGA=20
voids</SPAN></FONT><o:p></o:p></P>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3DArial =
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">Who are suppliers of =
inspection=20
quality oils [Canadian Balson??] the bear the heat of soldering=20
well?</SPAN></FONT><o:p></o:p></P></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-BOTTOM: medium none; BORDER-LEFT: black 1.5pt solid; =
BORDER-RIGHT: medium none; BORDER-TOP: medium none; MARGIN: 5pt 0in 5pt =
3pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 3pt; PADDING-RIGHT: 0in; =
PADDING-TOP: 0in">
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">----- =
Original=20
Message ----- <o:p></o:p></SPAN></FONT></P></DIV>
<DIV style=3D"font-color: black">
<P class=3DMsoNormal=20
style=3D"BACKGROUND: #e4e4e4; MARGIN-LEFT: 0.5in"><B><FONT =
face=3DArial=20
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: =
bold">From:</SPAN></FONT></B><FONT=20
face=3DArial size=3D2><SPAN style=3D"FONT-FAMILY: Arial; =
FONT-SIZE: 10pt"> <A=20
href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Bob Willis</A>=20
<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><B><FONT =
face=3DArial=20
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: =
bold">To:</SPAN></FONT></B><FONT=20
face=3DArial size=3D2><SPAN style=3D"FONT-FAMILY: Arial; =
FONT-SIZE: 10pt"> <A=20
href=3D"mailto:[log in to unmask]" =
[log in to unmask]>[log in to unmask]</A>=20
<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><B><FONT =
face=3DArial=20
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: =
bold">Sent:</SPAN></FONT></B><FONT=20
face=3DArial size=3D2><SPAN style=3D"FONT-FAMILY: Arial; =
FONT-SIZE: 10pt">=20
</SPAN></FONT><st1:date Year=3D"2001" Day=3D"19" =
Month=3D"11"><FONT face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: =
10pt">Monday, November=20
19, 2001</SPAN></FONT></st1:date><FONT face=3DArial size=3D2><SPAN =
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt"> =
</SPAN></FONT><st1:time=20
Minute=3D"45" Hour=3D"4"><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">4:45=20
AM</SPAN></FONT></st1:time><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: =
10pt"><o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><B><FONT =
face=3DArial=20
size=3D2><SPAN=20
style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt; FONT-WEIGHT: =
bold">Subject:</SPAN></FONT></B><FONT=20
face=3DArial size=3D2><SPAN style=3D"FONT-FAMILY: Arial; =
FONT-SIZE: 10pt"> Re:=20
[TN] AW: [TN] BGA voids<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN=20
style=3D"FONT-SIZE: =
12pt"><o:p> </o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">The =
outgassin=20
test for blowhole in printed boards was developed in the years =
gone bye=20
after it appeared in and Italian PCB specification I was asked to =
review.=20
After some testing I did it ended up in the IEC=20
specification.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">The =
same oil can=20
be used effectivly for outgassing tests with via in pad. In the =
last test=20
I did with ten scrap boards dfrom different suppliers 2 outgassed =
on the=20
pads from the vias.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">The =
procedure for=20
through hole which could and has been applied to vias is on my web =
site=20
which is in the download =
section.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-FAMILY: Arial; FONT-SIZE: 10pt">Hope =
this=20
helps.</SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN style=3D"FONT-SIZE: 12pt">Bob Willis<BR>Electronic =
Presentation=20
Services<BR></SPAN></FONT><st1:address><st1:Street>2 Fourth=20
Ave</st1:Street>, <st1:City>Chelmsford</st1:City></st1:address>,=20
<st1:place><st1:City>Essex</st1:City>, <st1:PostalCode>CM1=20
4HA</st1:PostalCode>=20
=
<st1:country-region>England</st1:country-region></st1:place><o:p></o:p></=
P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN style=3D"FONT-SIZE: 12pt">See us at APEX=20
2002</SPAN></FONT><FONT face=3D"Times New Roman"><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; mso-ascii-font-family: =
'MS PGothic'; mso-bidi-font-family: 'MS PGothic'"> </SPAN></FONT>=20
<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN style=3D"FONT-SIZE: 12pt"><A=20
=
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 =
496123<o:p></o:p></SPAN></FONT></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN=20
style=3D"FONT-FAMILY: 'Times New Roman'; FONT-SIZE: 12pt; =
mso-ascii-font-family: 'MS PGothic'; mso-bidi-font-family: 'MS =
PGothic'"> </SPAN></FONT><o:p></o:p></P></DIV>
<DIV>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT face=3D"MS =
PGothic"=20
size=3D3><SPAN style=3D"FONT-SIZE: 12pt">Single solution to your =
seminar,=20
conference or roadshow <A=20
=
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A><o:p></o:p></SPAN></FONT></P></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-BOTTOM: medium none; BORDER-LEFT: black 1.5pt =
solid; BORDER-RIGHT: medium none; BORDER-TOP: medium none; MARGIN: 5pt =
0in 5pt 3pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 3pt; PADDING-RIGHT: 0in; =
PADDING-TOP: 0in">
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"MS PGothic"=20
size=3D3><SPAN=20
style=3D"FONT-SIZE: =
12pt">---<o:p></o:p></SPAN></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQU=
OTE></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_001D_01C17192.590D6AE0--
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Date: Tue, 20 Nov 2001 09:31:14 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit
Bravo, Peter, for the obvious answer. I have been thoroughly opposed to
prebaking ever since I first started using G-10 PTH boards in the 1960s.
Not only should it not be necessary, it is, as you say, an extra and
unnecessary thermal cycle AND it causes sufficient oxidation of the
finish on the pads (including the nickel under the porous gold with ENIG
or electrolytic) that you are giving the flux a lot of extra work to do.
Unfortunately, not all PCB fab shops realise that they, too, sometimes
ship boards with built-in blow-holing etc., so proper packing (rare) is
not going to help in these cases. However, this is one of those cases
where prevention is better than cure.
IMHO, purchasing contracts for bare boards should include a clause,
especially for value-added multilayers, to the effect that any boards
that are up to n months old that are removed from their original
packaging and blowholes occur during soldering within, say, 24 hours
shall be replaced free-of-charge. This will place the ball fairly in the
PCB fab's court and we'll get better boards which are correctly packed.
This will mean the demise of polyethylene as a packing material, because
it is as porous to humidity as a kitchen sieve. To boot, it will make a
small contribution to a better environment because if you add up all the
energy required to heat up x million boards per day throughout the world
some 80°C for an hour, it will represent so much less CO2 (and reduce
costs).
Voila, Brian can now get off his soap-box :-)
Brian
Rick Howieson wrote:
>
> What is the recommended pre-bake of multilayer boards prior to insertion and
> wave. 221F for 1hour??? Or would this be a little extreme?
> Thanks,
> Rick
>
> ---------------------------------------------------------------------------------
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Date: Tue, 20 Nov 2001 17:03:48 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA voids
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Peter,
I can't help you with how to rework a micro BGA, never having dealt with
them, but I ask a question: Are you wanting to rework them just because
they have voids, or have the voids broken through the side of the balls?
Voids in themselves are not necessarily to be taken as being defects unless
they do break through.
Having had larger BGA's reworked, I can say that changing BGA's is an
expensive pain and better avoided if possible.
My tuppence worth only
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] BGA voids
<[log in to unmask]
ORG>
11/20/01
02:29 PM
Please
respond to
"TechNet
E-Mail
Forum."
How would one rework an assembly with micro BGA voiding due to several
micro vias on pad?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: November 19, 2001 8:48 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
We used to make PCB's back in the mid 1970's and used a fusing oil
produced by Shell Oil in our Hydro-squeegee. I want to say it was some
sort of Peanut oil... but I can't remember for sure... Those were my
High School years... :)
Good luck... - Bill Brooks
-----Original Message-----
From: David Fish [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 11:27 AM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] BGA voids
Who are suppliers of inspection quality oils [Canadian Balson??]
the bear the heat of soldering well?
----- Original Message -----
From: Bob Willis
To: [log in to unmask]
Sent: Monday, November 19, 2001 4:45 AM
Subject: Re: [TN] AW: [TN] BGA voids
The outgassin test for blowhole in printed boards was developed
in the years gone bye after it appeared in and Italian PCB
specification I was asked to review. After some testing I did it
ended up in the IEC specification.
The same oil can be used effectivly for outgassing tests with
via in pad. In the last test I did with ten scrap boards dfrom
different suppliers 2 outgassed on the pads from the vias.
The procedure for through hole which could and has been applied
to vias is on my web site which is in the download section.
Hope this helps.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow
www.seminar-registrations.com
---
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date: Tue, 20 Nov 2001 16:02:00 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anil Kher <[log in to unmask]>
Subject: O. MATERIALS. TO : VALUED ASSOCIATES.
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Dear Sir ,
Due to space problem we have now moved from G-4A,Kalkaji to the following address.:-
BHARTI TELETECH LTD.
C-87, BASEMENT
NEAR PETROL PUMP/
POLICE STATION
KALKAJI
NEW DELHI – 19.
TELPHONE NO. : 6233113
CONTACT PERSON: MR. VIJAY SINGH NEGI.
WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING TO LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
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Date: Tue, 20 Nov 2001 06:45:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Steve
I got to observe some CCGA work several years back, and the one big gotcha =
is that they are much less robust than a BGA part - the columns bend =
pretty easy. Not that I'm saying you should juggle BGAs - but treat these =
puppies like you would a QFP. And as they are heavy - make sure you have =
a good vacuum pen...
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/19/01 08:22PM >>>
Hi all!
May be getting the opportunity to assemble some boards with CCGA's on =
them.
Don't have any direct experience with these puppies. Downloaded IBM's
application *.PDF on assembling and reworking them (it's pretty good by =
the
way), and seems that basically, you would do the same thing assembling =
these
guys as you do when working with BGA's...am I over-simplifiying things too
much?
Any advice, or "gotcha's" I should look out for would be appreciated...
As always, thanks a bunch!!!
-Steve Gregory-
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Date: Tue, 20 Nov 2001 07:22:16 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Mario
I agree with Dave,, check out for yourself if the data is getting corrupted.
I worked for a company a few years ago were we had a similar problem with
EEPROMS we would send to customers for program upgrades. The customer
would get them and they wouldn't function. Verifying the programs would
show that the data was corrupted. The same thing would happen with UV-
erasable EPLDs.
As a test we ran many samples of programmed devices through our Circuit
Scan machine with no effect but when run through the Airport's Machines we
did have some random failures. The manufacture couldn't explain it.
We started packaging spares in a heavier silver ESD packaging and the
problem mysteriously went away.
We never had a problem with completely assembled units, possibly because
they were in metal cabinets.
I don't know if this helps at all but good luck
Hope you solve the problem.
---------------------------------------------------------------------------------
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Date: Tue, 20 Nov 2001 07:24:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
Sorry I meant Peter Duncan not Dave.. I work with a Dave.
Again Good luck
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Date: Tue, 20 Nov 2001 08:32:54 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Fjelstad <[log in to unmask]>
Subject: Re: No power on after underfill
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_f4.1299e863.292bb586_boundary"
--part1_f4.1299e863.292bb586_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hello Tony,
You may wish to look at using components which do not require underfill such
as the compliant package structures manufactured by licensees of Tessera's
technologies
(most of the major semiconductor supplier make such offerings). They are cost
competitive when you consider all of the extra steps you avoid (and in light
of the problems you are experiencing). Sometimes apparently cheaper solutions
are more expensive when viewed at the system level. It is a value/price
consideration. If you are not familiar with their technology you can visit
their web site to learn more.
www.tessera.com.
Kind regards,
Joe
--part1_f4.1299e863.292bb586_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Tony,
<BR>
<BR>You may wish to look at using components which do not require underfill such as the compliant package structures manufactured by licensees of Tessera's technologies
<BR>(most of the major semiconductor supplier make such offerings). They are cost competitive when you consider all of the extra steps you avoid (and in light of the problems you are experiencing). Sometimes apparently cheaper solutions are more expensive when viewed at the system level. It is a value/price consideration. If you are not familiar with their technology you can visit their web site to learn more.
<BR>
<BR>www.tessera.com.
<BR>
<BR>Kind regards,
<BR>Joe</FONT></HTML>
--part1_f4.1299e863.292bb586_boundary--
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Date: Tue, 20 Nov 2001 08:46:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbedded program ?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Greetings and Hallucinations,
Perhaps it isn't the X-rays but the strong EM field the X-ray machine is
generating that could be causing the trouble? I know we used to kill credit
cards in the ole physics lab with some of the coils we used. This is a
blind guess.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Andre Leclair [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 8:22 AM
To: [log in to unmask]
Subject: Re: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Mario
I agree with Dave,, check out for yourself if the data is getting corrupted.
I worked for a company a few years ago were we had a similar problem with
EEPROMS we would send to customers for program upgrades. The customer
would get them and they wouldn't function. Verifying the programs would
show that the data was corrupted. The same thing would happen with UV-
erasable EPLDs.
As a test we ran many samples of programmed devices through our Circuit
Scan machine with no effect but when run through the Airport's Machines we
did have some random failures. The manufacture couldn't explain it.
We started packaging spares in a heavier silver ESD packaging and the
problem mysteriously went away.
We never had a problem with completely assembled units, possibly because
they were in metal cabinets.
I don't know if this helps at all but good luck
Hope you solve the problem.
----------------------------------------------------------------------------
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Date: Tue, 20 Nov 2001 08:49:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
MIME-Version: 1.0
Content-Type: text/plain
Hi Steve,
there is something you should consider about CCGAs, and that is $$$!!! You
must read this literally and make sure that everybody in the company, from
the Incoming inspectors, through the kitting persons and to the operators
know it. If you run a small prototype batch, contact the supplier (or worse,
the broker) and make sure the parts come in the original trays and they are
properly strapped. If you end up getting the parts in hand made boxes,
because the broker divided the stuff from one tray between several
customers, there are big chances that you get them with bent leads. And if
the leads are bent more than 10 degrees, they exceed the elastic zone and
there is no point in trying to straighten them up, the reliability is gone.
Of course, they are reworkable, the manufacturer can replace the columns,
but the cost is almost like buying new parts.
Besides that, make sure that the design of the land pattern complies with
the guidelines in the IBM document you have. We once had to assemble on pads
that were a lot smaller and don't ask me how I had them pass the QA.
Assembly concerns:
- if you cannot see the leads during machine inspection, a tough job, since
the body is white, go with the body check, you can't miss
- some packages are pretty high, more than the 10mm that Fuji moves around
with the regular 26mm long nozzles, so, if you have some IP3s, or if this
applies to your machines, you might have to buy the shorter nozzles.
That's pretty much it. No other particular concerns, other than making sure
the side with this part is the last one to assemble, hehehe. Or the good old
DFM.
Have fun,
Ioan
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Monday, November 19, 2001 7:23 PM
> To: [log in to unmask]
> Subject: [TN] CCGA's, the good, the bad, and the ugly...
>
> Hi all!
>
> May be getting the opportunity to assemble some boards with CCGA's on
> them.
> Don't have any direct experience with these puppies. Downloaded IBM's
> application *.PDF on assembling and reworking them (it's pretty good by
> the
> way), and seems that basically, you would do the same thing assembling
> these
> guys as you do when working with BGA's...am I over-simplifiying things too
> much?
>
> Any advice, or "gotcha's" I should look out for would be appreciated...
>
> As always, thanks a bunch!!!
>
> -Steve Gregory-
>
> --------------------------------------------------------------------------
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Date: Tue, 20 Nov 2001 08:59:21 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Fjelstad <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
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Hello Mario
It is good question to ask but look about and you will note that there are
tens of thousands of digital devices with flash memory run through x-ray
every day (cell phones, cameras, MP3, memory cards) at airports around the
globe every day. We would likely have had bell ringing by now if there were
any significant risk.
Kind regards,
Joe
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Mario
<BR>
<BR>It is good question to ask but look about and you will note that there are tens of thousands of digital devices with flash memory run through x-ray every day (cell phones, cameras, MP3, memory cards) at airports around the globe every day. We would likely have had bell ringing by now if there were any significant risk.
<BR>
<BR>Kind regards,
<BR>Joe </FONT></HTML>
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Date: Tue, 20 Nov 2001 06:38:32 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: BGA bone of contention
In-Reply-To: <[log in to unmask]>
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An 80% paste aperture certainly makes more sense than an 80% land. I'm just
trying to answer answer Tom's original question- "...BGA opens on a HASL
board."..."What I'm looking for is comments on the increase of pad size and
corroboration in my belief that it's the wrong solution to this problem."
They are using 80% lands now - and they're having problems. Motorola
recommends a .4mm land. I don't need to justify anything... I believe I've
already done that. Tom - you asked for comments, you got mine.. and
Motorolas'. Do with it as you please.
-Denis
At 10:16 AM 11/20/2001 +0800, you wrote:
>As I know, 80% of the smallest ball size or preferably the same size
>should be as the stencil aperture size not as the pad size.
>-----Original Message----- From: Tom Colby
>[SMTP:[log in to unmask]] Sent: Monday, November 19, 2001 5:42
>PM To: [log in to unmask] Subject: Re: [TN] BGA bone of
>contention
>
>The rule of thumb, as I understand it, is 80% of the smallest ball size
>or preferably the same size as the substrate land. The object being to
>control the collapse of the solderball.
>
>If the minimum ball size is 0.35mm, how can you (or Mortorola) justify
>a pad size of 0.4-0.5mm?
>
>At 10:40 AM 11/19/01 -0600, you wrote: >Date: Mon, 19 Nov 2001
>07:42:59 -0800 >From: Denis Lefebvre
><[log in to unmask]> >Subject: Re: TechNet Digest - 18 Nov 2001
>to 19 Nov 2001 - Special issue > (#2001-713) > >As a layout
>designer, I am surprised that they used such small land areas. >Motorola
>recommends a land of .40 to .50mm. IMO .28mm is insufficient. >See
>attached PDF from Motorola. > >Denis Lefebvre, C.I.D. >Senior PCB
>Designer >Finisar
>Corporation >(408)542-3832
> ><http://www.finisar.com>http://www.finisar.com > >At 10:16 AM
>11/19/2001 -0500, you wrote: > >I'm not that far up in the food chain to
>know all of the particulars, but > >it wouldn't surprise me if that were
>the case. > > > >What I'm looking for is comments on the increase of pad
>size and > >corroboration in my belief that it's the wrong solution to
>this problem. > > > >Tom > > > >At 04:20 AM 11/19/01 -0600, you
>wrote: > >>Date: Mon, 19 Nov 2001 08:20:31 -0000 > >>From: Eric
>Dawson <[log in to unmask]> > >>Subject: Re: BGA bone of
>contention > >> > >>Hi Tom, > >>Are you wave soldering the other side
>of the board with the reflow soldered > >>bga.s on top? I have come
>across this practice and it definitely disturbs > >>the bga joints
>causing opens which cannot be detected by ordinary X
>ray > >>inspection. > >>Hope this helps. > >>Regards > >>Eric
>Dawson > >> > >> > -----Original Message----- > >> > From: Tom Colby
>[SMTP:[log in to unmask]] > >> > Sent: Friday, November 16, 2001 8:47
>PM > >> > To: [log in to unmask] > >> > Subject: [TN] BGA bone of
>contention > >> > > >> > Help me out with this
>technetters, > >> > > >> > The problem: BGA opens on a HASL
>board. > >> > > >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm
>pitch, ball size of > >> > 0.35/0.65. Substrate land size unknown.
>Footprint designed with a > pad of > >> > 0.28mm. > >> > > >> >
>Management's solution is to increase the pad size to 0.4mm. I say to >
>look > >> > elsewhere in the process for the problem. > >> > > >> > I'd
>like to hear the opinions of my esteemed colleagues. What do you
>say > >> > folks? > >> > > >> > Thanks in advance, > >> > > >> >
>Tom > >> > > >> > >
>--------------------------------------------------------------------------
>
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<html>
An 80% paste aperture certainly makes more sense than an 80% land. I'm
just trying to answer answer Tom's original question-
"...<font face="SimSun" size=2>BGA opens on a HASL
board.</font>"<font face="SimSun" size=2>...</font>"<font face="SimSun" size=2>What
I'm looking for is comments on the increase of pad size and</font>
<font face="SimSun" size=2>corroboration in my belief that it's the wrong
solution to this problem." </font>They are using 80% lands now - and
they're having problems. Motorola recommends a .4mm land. I don't need to
justify anything... I believe I've already done that. Tom - you asked for
comments, you got mine.. and Motorolas'. Do with it as you please.<br>
-Denis<br>
At 10:16 AM 11/20/2001 +0800, you wrote:<br><br>
<blockquote type=cite class=cite cite><font face="Times New Roman, Times" size=2 color="#0000FF">As
I know, 80% of the smallest ball size or preferably the same size should
be as the stencil aperture size not as the pad size.<br>
</font>
<ul><font face="Arial, Helvetica" size=1>
-----Original Message-----</font>
<font face="Arial, Helvetica" size=1><b>
From: </b></font> <font face="Arial, Helvetica" size=1>Tom Colby
[SMTP:[log in to unmask]]</font>
<font face="Arial, Helvetica" size=1><b>
Sent: </b></font> <font face="Arial, Helvetica" size=1>Monday,
November 19, 2001 5:42 PM</font>
<font face="Arial, Helvetica" size=1><b>
To: </b></font>
<font face="Arial, Helvetica" size=1>[log in to unmask]</font>
<font face="Arial, Helvetica" size=1><b>
Subject: </b></font> <font face="Arial, Helvetica" size=1> Re: [TN] BGA bone of contention</font> <br><br>
<font face="SimSun" size=2>
The rule of thumb, as I understand it, is 80% of the smallest ball size or</font> <font face="SimSun" size=2>
preferably the same size as the substrate land. The object being to control</font> <font face="SimSun" size=2>
the collapse of the solderball.</font> <br><br>
<font face="SimSun" size=2>
If the minimum ball size is 0.35mm, how can you (or Mortorola) justify a</font> <font face="SimSun" size=2>
pad size of 0.4-0.5mm?</font> <br><br>
<font face="SimSun" size=2>
At 10:40 AM 11/19/01 -0600, you wrote:</font> <font face="SimSun" size=2>
>Date: Mon, 19 Nov 2001 07:42:59 -0800</font> <font face="SimSun" size=2>
>From: Denis Lefebvre <[log in to unmask]></font> <font face="SimSun" size=2>
>Subject: Re: TechNet Digest - 18 Nov 2001 to 19 Nov 2001 - Special issue</font> <font face="SimSun" size=2>
> (#2001-713)</font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>As a layout designer, I am surprised that they used such small land areas.</font> <font face="SimSun" size=2>
>Motorola recommends a land of .40 to .50mm. IMO .28mm is insufficient.</font> <font face="SimSun" size=2>
>See attached PDF from Motorola.</font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>Denis Lefebvre, C.I.D.</font> <font face="SimSun" size=2>
>Senior PCB Designer</font> <font face="SimSun" size=2>
>Finisar Corporation</font> <font face="SimSun" size=2>
>(408)542-3832</font> <font face="SimSun" size=2>
></font><a href="http://www.finisar.com"><font face="SimSun" size=2 color="#0000FF"><u>http://www.finisar.com</a></u></font> <font face="SimSun" size=2>
></font> <font face="SimSun" size=2>
>At 10:16 AM 11/19/2001 -0500, you wrote:</font> <font face="SimSun" size=2>
> >I'm not that far up in the food chain to know all of the particulars, but</font> <font face="SimSun" size=2>
> >it wouldn't surprise me if that were the case.</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >What I'm looking for is comments on the increase of pad size and</font> <font face="SimSun" size=2>
> >corroboration in my belief that it's the wrong solution to this problem.</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >Tom</font> <font face="SimSun" size=2>
> ></font> <font face="SimSun" size=2>
> >At 04:20 AM 11/19/01 -0600, you wrote:</font> <font face="SimSun" size=2>
> >>Date: Mon, 19 Nov 2001 08:20:31 -0000</font> <font face="SimSun" size=2>
> >>From: Eric Dawson <[log in to unmask]></font> <font face="SimSun" size=2>
> >>Subject: Re: BGA bone of contention</font> <font face="SimSun" size=2>
> >></font> <font face="SimSun" size=2>
> >>Hi Tom,</font> <font face="SimSun" size=2>
> >>Are you wave soldering the other side of the board with the reflow soldered</font> <font face="SimSun" size=2>
> >>bga.s on top? I have come across this practice and it definitely disturbs</font> <font face="SimSun" size=2>
> >>the bga joints causing opens which cannot be detected by ordinary X ray</font> <font face="SimSun" size=2>
> >>inspection.</font> <font face="SimSun" size=2>
> >>Hope this helps.</font> <font face="SimSun" size=2>
> >>Regards</font> <font face="SimSun" size=2>
> >>Eric Dawson</font> <font face="SimSun" size=2>
> >></font> <font face="SimSun" size=2>
> >> > -----Original Message-----</font> <font face="SimSun" size=2>
> >> > From: Tom Colby [SMTP:[log in to unmask]]</font> <font face="SimSun" size=2>
> >> > Sent: Friday, November 16, 2001 8:47 PM</font> <font face="SimSun" size=2>
> >> > To: [log in to unmask]</font> <font face="SimSun" size=2>
> >> > Subject: [TN] BGA bone of contention</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Help me out with this technetters,</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > The problem: BGA opens on a HASL board.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > The device: Motorola MCF5272, a 196 MAPBGA, 1mm pitch, ball size of</font> <font face="SimSun" size=2>
> >> > 0.35/0.65. Substrate land size unknown. Footprint designed with a</font> <font face="SimSun" size=2>
> pad of</font> <font face="SimSun" size=2>
> >> > 0.28mm.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Management's solution is to increase the pad size to 0.4mm. I say to</font> <font face="SimSun" size=2>
> look</font> <font face="SimSun" size=2>
> >> > elsewhere in the process for the problem.</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > I'd like to hear the opinions of my esteemed colleagues. What do you say</font> <font face="SimSun" size=2>
> >> > folks?</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Thanks in advance,</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> > Tom</font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> >> ></font> <font face="SimSun" size=2>
> --------------------------------------------------------------------------</font> <br><br>
<font face="SimSun" size=2>
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Please visit IPC web site (</font><a href="http://www.ipc.org/html/forum.htm"><font face="SimSun" size=2 color="#0000FF"><u>http://www.ipc.org/html/forum.htm</a></u></font><font face="SimSun" size=2>) for additional</font> <font face="SimSun" size=2>
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Date: Tue, 20 Nov 2001 09:45:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Circuit Repair Facility
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jan,
We may be able to help with either the equipment or the service.
For services see: http://www.circuittechctr.com/services/gold.htm
For equipment see: http://www.circuittechctr.com/products/115-1702.htm
Please contact us offline for additional info.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
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-----Original Message-----
From: Jan Satterfield [mailto:[log in to unmask]]
Sent: Monday, November 19, 2001 5:41 PM
To: [log in to unmask]
Subject: [TN] Circuit Repair Facility
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
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Date: Tue, 20 Nov 2001 09:54:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
If the clamping/baking doesn't remove the warp on the first try, you could
give it one more try. What we do in these cases is to slightly bend a pair
of tool steel bars. We then clamp these bars to the warped edge bowing that
edge in the opposite direction. Go through the baking cycle again and cross
your fingers.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 9:50 PM
To: [log in to unmask]
Subject: Re: [TN] Board Warp
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board
Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
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-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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Date: Tue, 20 Nov 2001 20:22:10 +0530
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From: "Anil K. Singh" <[log in to unmask]>
Organization: Linaks Microelectronics Ltd
Subject: Re: O. MATERIALS. TO : VALUED ASSOCIATES.
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Anil Kher wrote:
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>
> Due to space problem we have now moved from G-4A,Kalkaji to the following address.:-
>
> BHARTI TELETECH LTD.
> C-87, BASEMENT
> NEAR PETROL PUMP/
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> KALKAJI
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> TELPHONE NO. : 6233113
>
> CONTACT PERSON: MR. VIJAY SINGH NEGI.
>
> WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING TO LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
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Date: Tue, 20 Nov 2001 09:44:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Pre-bake
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I to have never suggested that baking is right or necessary for standard =
boards. It should not be required on a well produced board with =
satisfactory plating thickness.
The old oil test is simply used were there is a debate on the quality =
and demostrating the route cause. Brian could of course reserect his =
faamouse Plop O Meter for testing for out gassing ?
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Brian Ellis=20
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 7:31 AM
Subject: Re: [TN] Pre-bake
Bravo, Peter, for the obvious answer. I have been thoroughly opposed =
to
prebaking ever since I first started using G-10 PTH boards in the =
1960s.
Not only should it not be necessary, it is, as you say, an extra and
unnecessary thermal cycle AND it causes sufficient oxidation of the
finish on the pads (including the nickel under the porous gold with =
ENIG
or electrolytic) that you are giving the flux a lot of extra work to =
do.
Unfortunately, not all PCB fab shops realise that they, too, sometimes
ship boards with built-in blow-holing etc., so proper packing (rare) =
is
not going to help in these cases. However, this is one of those cases
where prevention is better than cure.
IMHO, purchasing contracts for bare boards should include a clause,
especially for value-added multilayers, to the effect that any boards
that are up to n months old that are removed from their original
packaging and blowholes occur during soldering within, say, 24 hours
shall be replaced free-of-charge. This will place the ball fairly in =
the
PCB fab's court and we'll get better boards which are correctly =
packed.
This will mean the demise of polyethylene as a packing material, =
because
it is as porous to humidity as a kitchen sieve. To boot, it will make =
a
small contribution to a better environment because if you add up all =
the
energy required to heat up x million boards per day throughout the =
world
some 80=B0C for an hour, it will represent so much less CO2 (and =
reduce
costs).
Voila, Brian can now get off his soap-box :-)
Brian
Rick Howieson wrote:
>
> What is the recommended pre-bake of multilayer boards prior to =
insertion and
> wave. 221F for 1hour??? Or would this be a little extreme?
> Thanks,
> Rick
>
> =
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<DIV><FONT face=3DArial size=3D2>I to have never suggested that baking =
is right or=20
necessary for standard boards. It should not be required on a well =
produced=20
board with satisfactory plating thickness.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The old oil test is simply used were =
there is a=20
debate on the quality and demostrating the route cause. Brian could of =
course=20
reserect his faamouse Plop O Meter for testing for out gassing =
?</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Brian=20
Ellis</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, =
2001 7:31=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] =
Pre-bake</DIV>
<DIV><BR></DIV>Bravo, Peter, for the obvious answer. I have been =
thoroughly=20
opposed to<BR>prebaking ever since I first started using G-10 PTH =
boards in=20
the 1960s.<BR>Not only should it not be necessary, it is, as you say, =
an extra=20
and<BR>unnecessary thermal cycle AND it causes sufficient oxidation of =
the<BR>finish on the pads (including the nickel under the porous gold =
with=20
ENIG<BR>or electrolytic) that you are giving the flux a lot of extra =
work to=20
do.<BR>Unfortunately, not all PCB fab shops realise that they, too,=20
sometimes<BR>ship boards with built-in blow-holing etc., so proper =
packing=20
(rare) is<BR>not going to help in these cases. However, this is one of =
those=20
cases<BR>where prevention is better than cure.<BR><BR>IMHO, purchasing =
contracts for bare boards should include a clause,<BR>especially for=20
value-added multilayers, to the effect that any boards<BR>that are up =
to n=20
months old that are removed from their original<BR>packaging and =
blowholes=20
occur during soldering within, say, 24 hours<BR>shall be replaced=20
free-of-charge. This will place the ball fairly in the<BR>PCB fab's =
court and=20
we'll get better boards which are correctly packed.<BR>This will mean =
the=20
demise of polyethylene as a packing material, because<BR>it is as =
porous to=20
humidity as a kitchen sieve. To boot, it will make a<BR>small =
contribution to=20
a better environment because if you add up all the<BR>energy required =
to heat=20
up x million boards per day throughout the world<BR>some 80=B0C for an =
hour, it=20
will represent so much less CO2 (and reduce<BR>costs).<BR><BR>Voila, =
Brian can=20
now get off his soap-box :-)<BR><BR>Brian<BR><BR>Rick Howieson=20
wrote:<BR>><BR>> What is the recommended pre-bake of multilayer =
boards=20
prior to insertion and<BR>> wave. 221F for 1hour??? Or would this =
be a=20
little extreme?<BR>> Thanks,<BR>> Rick<BR>><BR>>=20
=
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To=20
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Technet=20
NOMAIL<BR>> Search previous postings at: <A=20
href=3D"http://www.ipc.org">www.ipc.org</A> > On-Line Resources =
&=20
Databases > E-mail Archives<BR>> Please visit IPC web site (<A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
for additional<BR>> information, or contact Keach Sasamori at <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> or 847-509-9700=20
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Date: Tue, 20 Nov 2001 09:53:09 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: No power on after underfill
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One of the reasons that people bake boards prior to underfilling is to =
overcome moisture and outgassing. Recent work in the UK has demonstrated =
that moisture comes out of the solder mask and can cause voiding in the =
underfill and cause part movement if a no flow material is used as the =
solder joints will not have been produced at this stage.
I am working with the NPL in UK on a solder mask project at the moment, =
if its of interest check out the NPL web site =
www.npl.co.uk/npl/ei/studio/
I have produces some video clips showing the outgassing from masks which =
I can put on line if people wish in RealPlayer format.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Peter George [log in to unmask]
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 5:40 AM
Subject: Re: [TN] No power on after underfill
Hmmm! I can't see anything in your points 1 to 3 that would directly =
cause
you any trouble, and the conductive residues I had in mind ranged from
ionic contaminants on the surfaces to any solder balls that might have
become lodged underneath.
You didn't answer if you've tried testing at elevated temperature =
prior to
underfilling, and one thing I didn't ask (because I 99.99...% know the
answer) is are your devices hermetically sealed? I'ld try doing a
cross-section of some of the BGA's that failed after underfilling and =
see
if any of the epoxy has got inside and damaged anything.
More things spring to mind - like did you bake out the assemblies =
prior to
underfilling? The Dexter Hysol (sorry, Loctite) underfill that I use
recommends pre-baking of assemblies prior to underfilling. If the =
BGA's
have been out of their bag longer than a couple of days before
underfilling, they have probably absorbed a lot of moisture. I can't =
say
for sure what effect heating moisture-laden components to 120 or even =
150
deg for 20 minutes or so would have, but your 3% may have suffered =
some
delam at some point. Or it may be warping and breaking/losing contact =
and
underfill is getting between the contact surfaces and isolating them.
Cross-sectioning and analysis should show this up too.
About tapped out of ideas again for now. Good luck with your search =
for a
cause - I'ld be interested in hearing what you find.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN =
Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] No =
power on after underfill
TechNet
<[log in to unmask]
ORG>
11/20/01
08:58 AM
Please
respond to
"TechNet
E-Mail
Forum."
1.The PCB we use is Ni/Au but there is Tin plated on the BGA side and =
the
solder paster type is Alpha RMA 9147
2. we have done the experiement for letting the epoxy only underfill =
50%
BGA size , the result is still bad
3. we reduce the curing temperature from 150 C to 120C , also no =
effective
4. what is conductive residues when we applying no-clean soldering =
process
?
By the way, if you need MDS of 3513, I can send to you .
Thanks for your great help.
Tony
-----Original Message-----
From: <Peter George Duncan> [SMTP:[log in to unmask]]
Sent: Monday, November 19, 2001 10:27 AM
To: [log in to unmask]
Subject: Re: [TN] No power on after underfill
Hi, Joseph,
I cannot find the 3513 material data sheet, but that probably =
doesn't
matter. The main thing I can think of that would cause your =
problem is
the
thermal excursions needed to apply and cure the underfill. Am I
correct to
say that the boards passed test at room temperature before the
underfill is
applied?
You may have a manufacturing problem where the balls make contact
enough to
pass test, but fail at elevated temperature. I would try testing =
the
boards
at 100 or 115 degrees C prior to underfilling them and see if =
they
still
pass. If they do, but fail again after underfilling, then the =
problem
is
probably related to your underfilling process. It is quite easy =
to
apply
too much if you're not using an automated process or have not
correctly
calculated the amount of material to apply. It does flow more =
prior to
curing at curing temperature, and if it's getting into nearby
interface
contacts as a result, you will need to look at damming the area =
around
the
BGA with a peelable masking to contain the underfill until it's =
cured,
or
reducing the amount of material applied.
One other thing might be contamination under the BGA. If you have =
any
conductive residues left on the board, especially if you use =
no-clean
soldering processes, they may be picked up by the underfill and
there's a
chance you're suffering from short circuits through the increased
conductivity of the epoxy. It's very important to the performance =
of
the
underfill that the underneath of the BGA's are very clean.
Hope this gives you some clues and you find a solution.
Peter Duncan
"Joseph H.
Smith" To: [log in to unmask]
<Tony_Zhang@H cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
ZMOT.COM> Aero/ST Group)
Sent by: Subject: [TN] No =
power on
after underfill
TechNet
<[log in to unmask]
ORG>
11/19/01
03:48 PM
Please
respond to
"TechNet
E-Mail
Forum."
Pls help me to solve this issue
We use undefilll for two BGA in one product ,the epoxy is Loctite =
LPD
3513
and the curing condition is 115C , 15 minutes , the BGA' s =
package is
below
.
U3 information : Body size, 9*9mm ; height 1.7 ; bump =
diameter
0.3 ;
pitch, 0.8*0.8 ;bump array 10*10
U1 information : Body size, 12*12 ; heigh t1.7 ; bump =
diameter
0.3 ;
pitch, 0.8*0.8 ; bump array 14*14
Before the underfilll we check the electric function .All are =
good
ones .
But after curing , some phone failed because "can not power on ", =
and
some
failed for "check SIM card ", the defect sample is closed to 3%. =
I
think
"check card "issue" may caused by the underfill material emission
which
cover the SIM card lead .
But I can not get any idea for further.
Thanks
Tony
[This e-mail is confidential and may also be privileged. If you =
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<DIV><FONT face=3DArial size=3D2>One of the reasons that people bake =
boards prior to=20
underfilling is to overcome moisture and outgassing. Recent work in the =
UK has=20
demonstrated that moisture comes out of the solder mask and can cause =
voiding in=20
the underfill and cause part movement if a no flow material is used as =
the=20
solder joints will not have been produced at this stage.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I am working with the NPL in UK on a =
solder mask=20
project at the moment, if its of interest check out the NPL web site <A=20
href=3D"http://www.npl.co.uk/npl/ei/">www.npl.co.uk/npl/ei/</A>studio/</F=
ONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I have produces some video clips =
showing the=20
outgassing from masks which I can put on line if people wish in =
RealPlayer=20
format.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:Peter George [log in to unmask]"=20
title=3D"Peter George [log in to unmask]">Peter George=20
[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, =
2001 5:40=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] No power on =
after=20
underfill</DIV>
<DIV><BR></DIV>Hmmm! I can't see anything in your points 1 to 3 that =
would=20
directly cause<BR>you any trouble, and the conductive residues I had =
in mind=20
ranged from<BR>ionic contaminants on the surfaces to any solder balls =
that=20
might have<BR>become lodged underneath.<BR><BR>You didn't answer if =
you've=20
tried testing at elevated temperature prior to<BR>underfilling, and =
one thing=20
I didn't ask (because I 99.99...% know the<BR>answer) is are your =
devices=20
hermetically sealed? I'ld try doing a<BR>cross-section of some of the =
BGA's=20
that failed after underfilling and see<BR>if any of the epoxy has got =
inside=20
and damaged anything.<BR><BR>More things spring to mind - like did you =
bake=20
out the assemblies prior to<BR>underfilling? The Dexter Hysol (sorry, =
Loctite)=20
underfill that I use<BR>recommends pre-baking of assemblies prior to=20
underfilling. If the BGA's<BR>have been out of their bag longer than a =
couple=20
of days before<BR>underfilling, they have probably absorbed a lot of =
moisture.=20
I can't say<BR>for sure what effect heating moisture-laden components =
to 120=20
or even 150<BR>deg for 20 minutes or so would have, but your 3% may =
have=20
suffered some<BR>delam at some point. Or it may be warping and =
breaking/losing=20
contact and<BR>underfill is getting between the contact surfaces and =
isolating=20
them.<BR>Cross-sectioning and analysis should show this up =
too.<BR><BR>About=20
tapped out of ideas again for now. Good luck with your search for =
a<BR>cause -=20
I'ld be interested in hearing what you find.<BR><BR>Peter=20
=
Duncan<BR><BR><BR><BR><BR>  =
; =20
"Joseph=20
=
H.<BR> &=
nbsp; =20
=
Smith" &=
nbsp; =20
To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR> =
&=
nbsp; =20
<Tony_Zhang@H =20
cc: (bcc: DUNCAN Peter/Asst Prin=20
=
Engr/ST<BR> &n=
bsp; =20
=
ZMOT.COM> &=
nbsp;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; =20
Sent=20
=
by: &nbs=
p;=20
Subject: Re: [TN] No power on after=20
=
underfill<BR> =
=20
=
TechNet<BR> &n=
bsp; =20
=
<[log in to unmask]<BR>  =
; =20
=
ORG><BR><BR><BR> =
=20
=
11/20/01<BR> &=
nbsp; =20
08:58=20
=
AM<BR> &=
nbsp; =20
=
Please<BR> &nb=
sp; =20
respond=20
=
to<BR> &=
nbsp; =20
=
"TechNet<BR> &=
nbsp; =20
=
E-Mail<BR> &nb=
sp; =20
Forum."<BR><BR><BR><BR><BR><BR><BR>1.The PCB we use is Ni/Au but there =
is Tin=20
plated on the BGA side and the<BR>solder paster type is Alpha RMA =
9147<BR>2.=20
we have done the experiement for letting the epoxy only underfill =
50%<BR>BGA=20
size , the result is still bad<BR>3. we reduce the curing =
temperature =20
from 150 C to 120C , also no effective<BR><BR>4. what is conductive =
residues=20
when we applying no-clean soldering process<BR>?<BR><BR><BR>By the =
way, if you=20
need MDS of 3513, I can send to you .<BR><BR><BR>Thanks for your great =
help.<BR><BR><BR>Tony<BR><BR><BR> =
-----Original=20
Message-----<BR> From: <Peter =
George=20
Duncan> [<A=20
=
href=3D"mailto:SMTP:[log in to unmask]">SMTP:[log in to unmask]</=
A>]<BR> =20
Sent: Monday, November 19, 2001 10:27=20
AM<BR> To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR> =
=20
=
Subject:  =
; =20
Re: [TN] No power on after =
underfill<BR><BR><BR> Hi,=20
Joseph,<BR><BR><BR> I cannot find the 3513 =
material=20
data sheet, but that probably doesn't<BR> =
matter. The=20
main thing I can think of that would cause your problem=20
is<BR> the<BR> thermal =
excursions needed to apply and cure the underfill. Am=20
I<BR> correct to<BR> =
say that=20
the boards passed test at room temperature before=20
the<BR> underfill =
is<BR> =20
applied?<BR><BR><BR> You may have a =
manufacturing=20
problem where the balls make contact<BR> =
enough=20
to<BR> pass test, but fail at elevated =
temperature. I=20
would try testing the<BR> =20
boards<BR> at 100 or 115 degrees C prior to=20
underfilling them and see if they<BR> =20
still<BR> pass. If they do, but fail again =
after=20
underfilling, then the problem<BR> =20
is<BR> probably related to your underfilling =
process.=20
It is quite easy to<BR> =20
apply<BR> too much if you're not using an =
automated=20
process or have not<BR> =20
correctly<BR> calculated the amount of =
material to=20
apply. It does flow more prior to<BR><BR> =
curing at=20
curing temperature, and if it's getting into=20
nearby<BR> =
interface<BR> =20
contacts as a result, you will need to look at damming the area=20
around<BR> the<BR> BGA =
with a=20
peelable masking to contain the underfill until it's=20
cured,<BR> or<BR> =
reducing the=20
amount of material applied.<BR><BR><BR> One =
other=20
thing might be contamination under the BGA. If you have=20
any<BR> conductive residues left on the board, =
especially if you use no-clean<BR> soldering=20
processes, they may be picked up by the underfill=20
and<BR> there's a<BR> =
chance=20
you're suffering from short circuits through the=20
increased<BR> conductivity of the epoxy. It's =
very=20
important to the performance of<BR> =20
the<BR> underfill that the underneath of the =
BGA's are=20
very clean.<BR><BR><BR> Hope this gives you =
some clues=20
and you find a solution.<BR><BR><BR> Peter=20
=
Duncan<BR><BR><BR><BR><BR><BR><BR><BR>  =
; =
=20
"Joseph=20
=
H.<BR> &=
nbsp; &n=
bsp;=20
=
Smith" &=
nbsp; =20
To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR> =
&=
nbsp; =20
<Tony_Zhang@H =20
cc: (bcc: DUNCAN<BR> =20
Peter/Asst Prin=20
=
Engr/ST<BR> &n=
bsp; &nb=
sp; =20
=
ZMOT.COM> &=
nbsp;=20
Aero/ST=20
=
Group)<BR> &nb=
sp; &nbs=
p; =20
Sent=20
=
by: &nbs=
p;=20
Subject: [TN] No power =
on<BR> =20
after=20
=
underfill<BR> =
&=
nbsp; =20
=
TechNet<BR> &n=
bsp; &nb=
sp; =20
=
<[log in to unmask]<BR>  =
; =
=20
=
ORG><BR><BR><BR><BR><BR><BR> =
&=
nbsp; =20
=
11/19/01<BR> &=
nbsp; &n=
bsp; =20
03:48=20
=
PM<BR> &=
nbsp; &n=
bsp;=20
=
Please<BR> &nb=
sp; &nbs=
p; =20
respond=20
=
to<BR> &=
nbsp; &n=
bsp;=20
=
"TechNet<BR> &=
nbsp; &n=
bsp; =20
=
E-Mail<BR> &nb=
sp; &nbs=
p; =20
=
Forum."<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR> =
Pls=20
help me to solve this =
issue<BR><BR><BR><BR><BR><BR> We=20
use undefilll for two BGA in one product ,the epoxy is Loctite=20
LPD<BR> 3513<BR> and =
the=20
curing condition is 115C , 15 minutes , the BGA' s package=20
is<BR> below<BR> =20
=
.<BR><BR><BR><BR><BR><BR> =
=20
U3 information : Body size, 9*9mm ; height 1.7 ; bump=20
diameter<BR> 0.3 ;<BR> =
pitch,=20
0.8*0.8 ;bump array=20
10*10<BR> U1 =
information=20
: Body size, 12*12 ; heigh t1.7 ; bump=20
diameter<BR> 0.3 ;<BR> =
pitch,=20
0.8*0.8 ; bump array =
14*14<BR><BR><BR><BR><BR><BR> =20
Before the underfilll we check the electric function .All are=20
good<BR> ones .<BR> =
But after=20
curing , some phone failed because "can not power on ",=20
and<BR> some<BR> =
failed for=20
"check SIM card ", the defect sample is closed to 3%.=20
I<BR> think<BR> "check =
card=20
"issue" may caused by the underfill material=20
emission<BR> which<BR> =
cover=20
the SIM card lead .<BR><BR><BR><BR><BR><BR> =
But I can=20
not get any idea for =
further.<BR><BR><BR><BR><BR><BR> =20
Thanks<BR> =20
=
Tony<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR> =
[This=20
e-mail is confidential and may also be privileged. If you=20
are<BR> not the<BR> =
intended=20
recipient, please delete it and notify us immediately;=20
you<BR> should<BR> not =
copy or=20
use it for any purpose, nor disclose its contents to=20
any<BR> other<BR> =
person.=20
Thank you.]<BR><BR><BR> =20
=
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---------------------------------------------------------------------------------
=========================================================================
Date: Tue, 20 Nov 2001 10:13:41 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: BGA voids
X-To: [log in to unmask]
MIME-Version: 1.0
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RE: Re: [TN] BGA voidsThe test procedure is on the web site to download. =
The procedure will be adapted for the boards but its the boards you are =
testing.
The issue of paste and voids in joints due to the air trapped in the via =
during printing is a separate issue.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: [log in to unmask]
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 1:47 AM
Subject: RE: Re: [TN] BGA voids
I have gone to your website today and downloaded some data what I =
need. What I still want to know is,=20
1, how to do outgassing oil test=20
2, it is plated in via, so what is the rootcause of void? Do you =
agree it cause by the solder paste flux during the reflow process
Thanks=20
tony=20
-----Original Message-----=20
From: Bob Willis [SMTP:[log in to unmask]]=20
Sent: Monday, November 19, 2001 12:17 PM=20
To: Tony Zhang-0343CE=20
Subject: Re: Re: [TN] BGA voids=20
I may be able to send you information but you need to tell me what =
you want or wait till your server is working.=20
=20
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England=20
=20
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm =
<http://www.bobwillis.co.uk/workshops/apex/apex.htm>=20
=20
www.bobwillis.co.uk <http://www.bobwillis.co.uk>
Tel: (44) 01245 351502 Fax: (44) 01245 496123=20
=20
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com <http://www.seminar-registrations.com>
----- Original Message -----=20
From: [log in to unmask] <mailto:[log in to unmask]>=20
To: [log in to unmask] <mailto:[log in to unmask]>=20
Sent: Monday, November 19, 2001 2:48 AM=20
Subject: RE: Re: [TN] BGA voids=20
Willis,
Our sever downed for daoys, so I can not go to your website =
to see the detail information, Could you pls send the information to me?
Thanks
Tony Zhang
Process Engineer
Hangzhou Motorola=20
-----Original Message-----
From: Bob Willis [SMTP:[log in to unmask] =
<mailto:SMTP:[log in to unmask]>]
Sent: Friday, November 16, 2001 5:59 PM
To: [log in to unmask]
Subject: Re: [TN] BGA voids=20
We have experienced voiding with via in pad, I know it ws =
stated that the pads don't have vias in them but if they did they can =
somtimes gass through the plating, its not the air traped by the paste. =
I have investigated this with my old outgassing oil test which showes up =
the problem and will contribute to voiding.
=20
Bob Willis
=20
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm =
<<http://www.bobwillis.co.uk/workshops/apex/apex.htm>>
=20
www.bobwillis.co.uk <<http://www.bobwillis.co.uk>>
Tel: (44) 01245 351502 Fax: (44) 01245 496123
=20
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com <<http://www.seminar-registrations.com>>
----- Original Message -----
From: Peter George [log in to unmask] <<mailto:Peter> George =
[log in to unmask]>
To: [log in to unmask] <<mailto:[log in to unmask]>>
Sent: Friday, November 16, 2001 8:52 AM
Subject: Re: [TN] BGA voids=20
Hi, Peter,
I was at a seminar earlier this year where BGA's and their =
solder joints
were discussed at some length. The received wisdom is that voids =
in solder
joints are not of themselves a 'defect' unless they break out =
through the
side of the ball. In fact, they make the joint more "flexible" - =
better
able to withstand creep fatigue - so are beneficial, up to a =
point.
What causes them is often outgassing of volatiles in the solder =
paste flux
during the reflow process, though the size and shape of voids =
increases and
changes when there are via-in-pad features as well. About the =
only way to
detect them is by X-ray, and to judge from previous TechNet =
postings, there
are some pretty fancy machines around now that can give you a =
very much
clearer view of the balls than is normally the case ... if you =
have cash to
splash!
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask] =
<<mailto:[log in to unmask]>>
.COM> cc: (bcc: DUNCAN =
Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] BGA =
voids
<[log in to unmask]
ORG>
11/16/01
04:25 PM
Please
respond to
"TechNet
E-Mail
Forum."
Hello,
I am encountering voids after reflow on several micro BGAs on =
one PCA
product. The voids that I $B!G (Bve observed (with Xray) =
contribute to as high as
60-70% of the joint area. My reflow profile was designed by =
running a
sample board with dummy components and thermalcouples attached =
right at the
joint. I also inspected the PCB lands and didn $B!G (Bt see any =
via on pad.
Does anyone know the possible reasons for voids formation in BGA =
(micro)
reflow?
In general, in step by step how would one trouble shoot such a =
defect?
Rgds,
Peter
[This e-mail is confidential and may also be privileged. If you =
are not the
intended recipient, please delete it and notify us immediately; =
you should
not copy or use it for any purpose, nor disclose its contents to =
any other
person. Thank you.]
=
-------------------------------------------------------------------------=
--------
Technet Mail List provided as a free service by IPC using =
LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] =
<<mailto:[log in to unmask]>> with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send the following =
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Search previous postings at: www.ipc.org <<http://www.ipc.org>> =
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Please visit IPC web site =
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<HTML><HEAD><TITLE>RE: Re: [TN] BGA voids</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
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<DIV><FONT face=3DArial size=3D2>The test procedure is on the web site =
to download.=20
The procedure will be adapted for the boards but its the boards you are=20
testing.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The issue of paste and voids in joints =
due to the=20
air trapped in the via during printing is a separate issue.</FONT></DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, =
2001 1:47=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> RE: Re: [TN] BGA =
voids</DIV>
<DIV><BR></DIV><!-- Converted from text/rtf format -->
<P><SPAN lang=3Den-us><FONT color=3D#0000ff face=3D"Times New Roman" =
size=3D2>I have=20
gone to your website today and downloaded some data what I need. =
What I=20
still want to know is,</FONT></SPAN> <BR><SPAN lang=3Den-us><FONT =
color=3D#0000ff=20
face=3D"Times New Roman" size=3D2>1, how to do</FONT> <FONT =
color=3D#0000ff=20
face=3D"Times New Roman" size=3D2>outgassing oil test</FONT> =
</SPAN><BR><SPAN=20
lang=3Den-us><FONT color=3D#0000ff face=3D"Times New Roman" =
size=3D2>2, it is=20
plated in via, so what is the rootcause of void? Do you agree it cause =
by</FONT> <FONT color=3D#0000ff face=3D"Times New Roman" size=3D2>the =
solder paste=20
flux during the reflow process</FONT></SPAN></P>
<P><SPAN lang=3Den-us><FONT color=3D#0000ff face=3D"Times New Roman"=20
size=3D2>Thanks</FONT></SPAN> <BR><SPAN lang=3Den-us><FONT =
color=3D#0000ff=20
face=3D"Times New Roman" size=3D2>tony</FONT></SPAN>=20
<UL>
<P><SPAN lang=3Den-us><FONT face=3DArial size=3D1>-----Original=20
Message-----</FONT></SPAN> <BR><SPAN lang=3Den-us><B><FONT =
face=3DArial=20
size=3D1>From: </FONT></B> <FONT face=3DArial =
size=3D1>Bob Willis=20
[SMTP:[log in to unmask]]</FONT></SPAN> <BR><SPAN =
lang=3Den-us><B><FONT=20
face=3DArial size=3D1>Sent: </FONT></B> <FONT =
face=3DArial=20
size=3D1>Monday, November 19, 2001 12:17 PM</FONT></SPAN> <BR><SPAN=20
lang=3Den-us><B><FONT face=3DArial =
size=3D1>To: </FONT></B>=20
<FONT face=3DArial size=3D1>Tony Zhang-0343CE</FONT></SPAN> =
<BR><SPAN=20
lang=3Den-us><B><FONT face=3DArial=20
=
size=3D1>Subject: </FONT></B> =
<FONT=20
face=3DArial size=3D1>Re: Re: [TN] BGA voids</FONT></SPAN> </P>
<P><SPAN lang=3Den-us><FONT face=3DArial size=3D2>I may be able to =
send you=20
information but you need to tell me what you want or wait till your =
server=20
is working.</FONT></SPAN> <BR><SPAN lang=3Den-us><FONT=20
face=3DArial> </FONT></SPAN> <BR><SPAN lang=3Den-us><FONT =
face=3DArial>Bob=20
Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</FONT></SPAN> <BR><SPAN lang=3Den-us><FONT=20
face=3DArial> </FONT></SPAN> <BR><SPAN lang=3Den-us><FONT =
face=3DArial>See us=20
at APEX 2002 <U> </U></FONT><U><FONT color=3D#0000ff=20
face=3DArial>www.bobwillis.co.uk/workshops/apex/apex.htm <<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>></FONT></U></SPAN>=20
<BR><SPAN lang=3Den-us><FONT face=3DArial> </FONT></SPAN> =
<BR><SPAN=20
lang=3Den-us><U><FONT color=3D#0000ff =
face=3DArial>www.bobwillis.co.uk <<A=20
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>></F=
ONT></U><BR><FONT=20
face=3DArial>Tel: (44) 01245 351502 Fax: (44) 01245 =
496123</FONT></SPAN>=20
<BR><SPAN lang=3Den-us><FONT face=3DArial> </FONT></SPAN> =
<BR><SPAN=20
lang=3Den-us><FONT face=3DArial>Single solution to your seminar, =
conference or=20
roadshow</FONT><U> <FONT color=3D#0000ff=20
face=3DArial>www.seminar-registrations.com <<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>></FONT></U></SPAN></P>
<UL>
<P><SPAN lang=3Den-us><FONT face=3DArial>----- Original Message =
-----=20
</FONT></SPAN><BR><SPAN lang=3Den-us><B><FONT=20
face=3DArial>From:</FONT></B><FONT face=3DArial></FONT><U> <FONT =
color=3D#0000ff=20
face=3DArial>[log in to unmask] <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>><=
/FONT></U><FONT=20
face=3DArial> </FONT></SPAN><BR><SPAN lang=3Den-us><B><FONT=20
face=3DArial>To:</FONT></B><FONT face=3DArial></FONT><U> <FONT =
color=3D#0000ff=20
face=3DArial>[log in to unmask] <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>></F=
ONT></U><FONT=20
face=3DArial> </FONT></SPAN><BR><SPAN lang=3Den-us><B><FONT=20
face=3DArial>Sent:</FONT></B><FONT face=3DArial> Monday, November =
19, 2001=20
2:48 AM</FONT></SPAN> <BR><SPAN lang=3Den-us><B><FONT=20
face=3DArial>Subject:</FONT></B><FONT face=3DArial> RE: Re: [TN] =
BGA=20
voids</FONT></SPAN> </P><BR>
<P><SPAN lang=3Den-us><FONT color=3D#0000ff face=3D"Times New =
Roman"=20
size=3D2>Willis,</FONT><FONT face=3DArial><BR></FONT><FONT =
color=3D#0000ff=20
face=3D"Times New Roman" size=3D2> Our =
sever downed=20
for daoys, so I can not go to your website to see the detail =
information,=20
Could you pls send the information to me?</FONT></SPAN></P>
<P><SPAN lang=3Den-us><FONT color=3D#0000ff face=3D"Times New =
Roman"=20
size=3D2>Thanks</FONT><FONT face=3DArial><BR></FONT><FONT =
face=3DTahoma=20
size=3D2>Tony Zhang</FONT><FONT face=3DArial><BR></FONT><FONT =
face=3DTahoma=20
size=3D2>Process Engineer</FONT><BR><FONT face=3DTahoma =
size=3D2>Hangzhou=20
Motorola</FONT><FONT face=3DArial> </FONT></SPAN></P><BR><BR><BR>
<P><SPAN lang=3Den-us> =
<FONT=20
face=3DArial size=3D1>-----Original Message-----</FONT><FONT=20
face=3DArial><BR></FONT><B><FONT face=3DArial=20
size=3D1>From: </FONT></B><FONT face=3DArial> =
</FONT><FONT=20
face=3DArial size=3D1>Bob Willis [</FONT><U><FONT color=3D#0000ff =
face=3DArial=20
size=3D1>SMTP:[log in to unmask] <<A=20
=
href=3D"mailto:SMTP:[log in to unmask]">mailto:SMTP:[log in to unmask]<=
/A>></FONT></U><FONT=20
face=3DArial size=3D1>]</FONT><FONT =
face=3DArial><BR></FONT><B><FONT face=3DArial=20
size=3D1>Sent: </FONT></B><FONT face=3DArial> =
</FONT><FONT=20
face=3DArial size=3D1>Friday, November 16, 2001 5:59 =
PM</FONT><FONT=20
face=3DArial><BR></FONT><B><FONT face=3DArial=20
size=3D1>To: </FONT></B><FONT face=3DArial> =
</FONT><FONT face=3DArial size=3D1>[log in to unmask]</FONT><FONT=20
face=3DArial><BR></FONT><B><FONT face=3DArial=20
=
size=3D1>Subject: </FONT></B><FO=
NT=20
face=3DArial> </FONT><FONT face=3DArial =
size=3D1> Re:=20
[TN] BGA voids</FONT><FONT face=3DArial> </FONT></SPAN></P>
<P><SPAN lang=3Den-us> =
<FONT=20
face=3DArial size=3D2>We have experienced voiding with via in pad, =
I know it=20
ws stated that the pads don't have vias in them but if they did =
they can=20
somtimes gass through the plating, its not the air traped by the =
paste. I=20
have investigated this with my old outgassing oil test which =
showes up the=20
problem and will contribute to voiding.</FONT></SPAN></P>
<P><SPAN lang=3Den-us> =
<FONT=20
face=3DArial> <BR></FONT><FONT face=3D"MS Mincho">Bob =
Willis</FONT><FONT=20
face=3DArial><BR> <BR></FONT><FONT face=3D"MS Mincho">See us =
at APEX=20
2002</FONT><FONT face=3DArial> </FONT><U></U><U><FONT =
face=3D"MS Mincho">=20
</FONT><FONT color=3D#0000ff=20
face=3D"MS Mincho">www.bobwillis.co.uk/workshops/apex/apex.htm =
<<<A=20
=
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">http://www.bo=
bwillis.co.uk/workshops/apex/apex.htm</A>>></FONT></U><FONT=20
face=3DArial><BR> <BR></FONT><U></U><U><FONT color=3D#0000ff=20
face=3D"MS Mincho">www.bobwillis.co.uk <<<A=20
=
href=3D"http://www.bobwillis.co.uk">http://www.bobwillis.co.uk</A>>>=
;</FONT></U><BR><FONT=20
face=3D"MS Mincho">Tel: (44) 01245 351502 Fax: (44) 01245 =
496123</FONT><FONT=20
face=3DArial><BR> <BR></FONT><FONT face=3D"MS Mincho">Single =
solution to=20
your seminar, conference or roadshow</FONT><U></U><U><FONT=20
face=3DArial></FONT> <FONT color=3D#0000ff=20
face=3D"MS Mincho">www.seminar-registrations.com <<<A=20
=
href=3D"http://www.seminar-registrations.com">http://www.seminar-registra=
tions.com</A>>></FONT></U></SPAN></P>
<UL>
<P><SPAN lang=3Den-us> =
<FONT=20
face=3D"MS Mincho">----- Original Message =
-----</FONT><BR><B></B><B><FONT=20
face=3D"MS Mincho">From:</FONT></B><FONT face=3D"MS Mincho"> =
Peter George=20
[log in to unmask] <</FONT><U><FONT color=3D#0000ff=20
face=3D"MS Mincho"><<A =
href=3D"mailto:Peter">mailto:Peter</A>> George=20
[log in to unmask]</FONT></U><FONT=20
face=3D"MS Mincho">></FONT><BR><B></B><B><FONT=20
face=3D"MS Mincho">To:</FONT></B><B><U></U></B><U></U><U><FONT=20
face=3DArial></FONT> <FONT color=3D#0000ff face=3D"MS =
Mincho">[log in to unmask]
<<<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>>></FONT>=
</U><FONT=20
face=3D"MS Mincho"></FONT><BR><B></B><B><FONT=20
face=3D"MS Mincho">Sent:</FONT></B><FONT face=3D"MS Mincho"> =
Friday,=20
November 16, 2001 8:52 AM</FONT><FONT=20
face=3DArial><BR></FONT><B></B><B><FONT=20
face=3D"MS Mincho">Subject:</FONT></B><FONT face=3D"MS Mincho"> =
Re: [TN] BGA=20
voids</FONT><FONT face=3DArial> </FONT></SPAN></P>
<P><SPAN lang=3Den-us> =
<FONT=20
face=3D"MS Mincho">Hi, Peter,<BR><BR>I was at a seminar earlier =
this year=20
where BGA's and their solder joints<BR>were discussed at some =
length.=20
The received wisdom is that voids in solder<BR>joints are not of =
themselves a 'defect' unless they break out through the<BR>side =
of the=20
ball. In fact, they make the joint more "flexible" - =
better<BR>able to=20
withstand creep fatigue - so are beneficial, up to a =
point.<BR><BR>What=20
causes them is often </FONT><FONT color=3D#ff0000=20
face=3D"MS Mincho">outgassing</FONT><FONT face=3D"MS Mincho"> of =
volatiles=20
in the solder paste flux<BR>during the reflow process, though =
the size=20
and shape of voids increases and<BR>changes when there are =
via-in-pad=20
features as well. About the only way to<BR>detect them is by =
X-ray, and=20
to judge from previous TechNet postings, there<BR>are some =
pretty fancy=20
machines around now that can give you a very much<BR>clearer =
view of the=20
balls than is normally the case ... if you have cash=20
to<BR>splash!<BR><BR>Peter =
Duncan<BR><BR><BR><BR><BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> Peter=20
Lee<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho">=20
<ppwlee@YAHOO</FONT><FONT=20
face=3D"Courier =
New"> </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
To:</FONT><FONT=20
face=3D"Courier New"> </FONT><FONT=20
face=3DArial> </FONT><U><FONT face=3DArial></FONT> <FONT =
color=3D#0000ff=20
face=3D"MS Mincho">[log in to unmask] <<<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>>></FONT>=
</U><BR><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
.COM></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
cc:</FONT><FONT=20
face=3D"Courier New"> </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> (bcc: DUNCAN =
Peter/Asst=20
Prin Engr/ST<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> Sent =
by:</FONT><FONT=20
face=3D"Courier =
New"> </=
FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> Aero/ST=20
Group)<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
TechNet</FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp;</FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
Subject:</FONT><FONT=20
face=3D"Courier New"> </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> [TN] BGA=20
voids<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho">=20
<[log in to unmask]<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho">=20
ORG><BR><BR><BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
11/16/01<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> 04:25 =
PM<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
Please<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> respond=20
to<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
"TechNet<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho"> =
E-Mail<BR></FONT><FONT=20
face=3D"Courier =
New"> &n=
bsp; </FONT><FONT=20
face=3DArial> </FONT><FONT face=3D"MS Mincho">=20
=
Forum."<BR><BR><BR><BR><BR><BR><BR>Hello,<BR><BR><BR><BR><BR><BR>I am=20
encountering voids after reflow on several micro BGAs on one=20
PCA<BR>product. The voids that I $B!G (Bve observed (with Xray)=20
contribute to as high as<BR>60-70% of the joint area. My reflow =
profile=20
was designed by running a<BR>sample board with dummy components =
and=20
thermalcouples attached right at the<BR>joint. I also inspected =
the PCB=20
lands and didn $B!G (Bt see any via on =
pad.<BR><BR><BR><BR><BR><BR>Does=20
anyone know the possible reasons for voids formation in BGA=20
(micro)<BR>reflow?<BR><BR><BR><BR><BR><BR>In general, in step by =
step=20
how would one trouble shoot such a=20
=
defect?<BR><BR><BR><BR><BR><BR>Rgds,<BR><BR><BR>Peter<BR><BR><BR><BR><BR>=
<BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR><BR>[=
This=20
e-mail is confidential and may also be privileged. If you are =
not=20
the<BR>intended recipient, please delete it and notify us =
immediately;=20
you should<BR>not copy or use it for any purpose, nor disclose =
its=20
contents to any other<BR>person. Thank=20
=
you.]<BR><BR>------------------------------------------------------------=
---------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
1.8d<BR>To=20
unsubscribe, send a message to</FONT><U></U><U><FONT =
face=3DArial></FONT>=20
<FONT color=3D#0000ff face=3D"MS Mincho">[log in to unmask] =
<<<A=20
=
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T></U><FONT=20
face=3D"MS Mincho"> with following text in<BR>the BODY (NOT the =
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=
href=3D"http://www.ipc.org">http://www.ipc.org</A>>></FONT></U><FON=
T=20
face=3D"MS Mincho"> > On-Line Resources & Databases > =
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Archives<BR>Please visit IPC web site (</FONT><U><FONT =
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=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>>></FONT></U><FONT=20
face=3D"MS Mincho">) for additional<BR>information, or contact =
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Sasamori at</FONT><U></U><U><FONT face=3DArial></FONT> <FONT =
color=3D#0000ff=20
face=3D"MS Mincho">[log in to unmask] <<<A=20
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U><FONT=20
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</FONT></SPAN></P></UL></UL></UL></BLOCKQUOTE></BODY></HTML>
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---------------------------------------------------------------------------------
=========================================================================
Date: Tue, 20 Nov 2001 11:00:56 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUED ASSOCIATES.
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_81.135596c4.292bd838_boundary"
--part1_81.135596c4.292bd838_boundary
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
I got this email sent directly to me and it had an attachment, the attachmen=
t=20
was a virus, it was the W32.Magistr.24876@mm worm. If any of you get this=20
email sent directly to you, don't run the attachment!!!=20
The attached file will be named: Kalkaji.com
Below is a paste from Symantec about the virus...
-Steve Gregory-
When a file that is infected by W32.Magistr.24876@mm is executed, it searche=
s=20
in memory for a readable, writable, initialized section inside the memory=20
space of Explorer.exe. If one is found, a 110-byte routine is inserted into=20
that area, and the TranslateMessage function is hooked to point to that=20
routine. This code first appeared in W32.Dengue.
When the inserted code gains control, a thread is created and the original=20
TranslateMessage function is called. The thread waits for three minutes=20
before activating. Then the virus obtains the name of the computer, converts=
=20
it to a base64 string, and depending on the first character of the name,=20
creates a file in either the \Windows folder, the \Program Files folder, or=20
the root folder. This file contains certain information, such as the locatio=
n=20
of the email address books and the date of initial infection. Then it=20
retrieves the current user's email name and address information from the=20
registry (Outlook, Exchange, Internet Mail and News), or the Prefs.js file=20
(Netscape). The virus keeps in its body a history of the 10 most recently=20
infected users, and these names are visible in infected files when the virus=
=20
is decrypted. After this, the virus searches for the Sent file in the=20
Netscape folder, and for .wab, .mbx, and .dbx files in the \Windows and=20
\Program Files folders.
If an active Internet connection exists, the virus searches for up to five=20
.doc and .txt files and chooses a random number of words from one of these=20
files. These words are used to construct the subject and message body of the=
=20
email message. Then the virus searches for up to 20 .exe and .scr files=20
smaller than 128 KB, infects one of these files, attaches the infected file=20
to the new message, and sends this message to up to 100 people from the=20
address books. In addition there is a 20-percent chance that it will attach=20
the file from which the subject and message body was taken, and an 80-percen=
t=20
chance that it will add the number 1 to the second character of the sender=20
address. This last change prevents replies from being returned to you and=20
possibly alerting you to the infection.
=20
> ??????
>=20
> Anil Kher wrote:
>=20
> > Dear Sir ,
> >
> > Due to space problem we have now moved from G-4A,Kalkaji to the followin=
g=20
> address.:-
> >
> > BHARTI TELETECH LTD.
> > C-87, BASEMENT
> > NEAR PETROL PUMP/
> > POLICE STATION
> > KALKAJI
> > NEW DELHI =E2=80=93 19.
> > TELPHONE NO. : 6233113
> >
> > CONTACT PERSON: MR. VIJAY SINGH NEGI.
> >
> > WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAINING T=
O=20
> LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
>=20
--part1_81.135596c4.292bd838_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2>I got this email sent dir=
ectly to me and it had an attachment, the attachment was a virus, it was the=
W32.Magistr.24876@mm worm. If any of you get this email sent directly to yo=
u, don't run the attachment!!!=20
<BR>
<BR>The attached file will be named: Kalkaji.com
<BR>
<BR>Below is a paste from Symantec about the virus...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>When a file that is infected by W32.Magistr.24876@mm is executed, it sea=
rches in memory for a readable, writable, initialized section inside the mem=
ory space of Explorer.exe. If one is found, a 110-byte routine is inserted i=
nto that area, and the TranslateMessage function is hooked to point to that=20=
routine. This code first appeared in W32.Dengue.
<BR>
<BR>When the inserted code gains control, a thread is created and the origin=
al TranslateMessage function is called. The thread waits for three minutes b=
efore activating. Then the virus obtains the name of the computer, converts=20=
it to a base64 string, and depending on the first character of the name, cre=
ates a file in either the \Windows folder, the \Program Files folder, or the=
root folder. This file contains certain information, such as the location o=
f the email address books and the date of initial infection. Then it retriev=
es the current user's email name and address information from the registry (=
Outlook, Exchange, Internet Mail and News), or the Prefs.js file (Netscape).=
The virus keeps in its body a history of the 10 most recently infected user=
s, and these names are visible in infected files when the virus is decrypted=
. After this, the virus searches for the Sent file in the Netscape folder, a=
nd for .wab, .mbx, and .dbx files in the \Windows and \Program Files folders=
.
<BR>
<BR>If an active Internet connection exists, the virus searches for up to fi=
ve .doc and .txt files and chooses a random number of words from one of thes=
e files. These words are used to construct the subject and message body of t=
he email message. Then the virus searches for up to 20 .exe and .scr files s=
maller than 128 KB, infects one of these files, attaches the infected file t=
o the new message, and sends this message to up to 100 people from the addre=
ss books. In addition there is a 20-percent chance that it will attach the f=
ile from which the subject and message body was taken, and an 80-percent cha=
nce that it will add the number 1 to the second character of the sender addr=
ess. This last change prevents replies from being returned to you and possib=
ly alerting you to the infection.
<BR> =20
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">??????
<BR>
<BR>Anil Kher wrote:
<BR>
<BR>> Dear Sir ,
<BR>>
<BR>> Due to space problem we have now moved from G-4A,Kalkaji to the fol=
lowing address.:-
<BR>>
<BR>> BHARTI TELETECH LTD.
<BR>> C-87, BASEMENT
<BR>> NEAR PETROL PUMP/
<BR>> POLICE STATION
<BR>> KALKAJI
<BR>> NEW DELHI =E2=80=93 19.
<BR>> TELPHONE NO. : 6233113
<BR>>
<BR>> CONTACT PERSON: MR. VIJAY SINGH NEGI.
<BR>>
<BR>> WE HOPE THAT YOU SURELY SUPPORT US IN SENDING THE MATERIALS PERTAIN=
ING TO LUDHIANA FACTORY IN THE ABOVE ADDRESS WITH IMMEEIDATE EFFECT.
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR>
<BR></FONT></HTML>
--part1_81.135596c4.292bd838_boundary--
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=========================================================================
Date: Tue, 20 Nov 2001 11:06:23 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
In CCGA, it's important to:
* Have pads on the board that are the same size as the pads on the ceramic
imterposer.
* Have pads on the board that are in the same location as the pads on the
ceramic interposer.
* Apply 4800 to 5500 thou^3 of near eutectic solder paste on each pad.
* Show discipline. Longer at lower temps is better than shorter at higher
temps. There is a tendency to rush the profile in order to get more
throughput. Resist the temptation!
Dave Fish
----- Original Message -----
From: "Stephen R. Gregory" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 19, 2001 4:22 PM
Subject: [TN] CCGA's, the good, the bad, and the ugly...
> Hi all!
>
> May be getting the opportunity to assemble some boards with CCGA's on
them.
> Don't have any direct experience with these puppies. Downloaded IBM's
> application *.PDF on assembling and reworking them (it's pretty good by
the
> way), and seems that basically, you would do the same thing assembling
these
> guys as you do when working with BGA's...am I over-simplifiying things too
> much?
>
> Any advice, or "gotcha's" I should look out for would be appreciated...
>
> As always, thanks a bunch!!!
>
> -Steve Gregory-
>
> --------------------------------------------------------------------------
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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Date: Tue, 20 Nov 2001 18:43:33 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Pre-bake
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Gawd, Bob! You've got a fantastic memory! The prototype Plopometer
worked fine, but I never got round to writing a good analytical software
for it. As it never saw the light of a commercial day, I don't think
"faamouse" is exactly the best adjective to describe it.
Best regards,
Brian
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Date: Tue, 20 Nov 2001 08:56:03 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Solder spikes and icicling
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Hello,
Can someone explain what are possible causes for wave
soldering spikes and icicling on the assemblies?
I am encountering this defect on boards with larger
BNC connectors and fuse jumpers. Could this be a
pre-heating issue? How would one resolve this?
Rgds,
Peter
__________________________________________________
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Yahoo! GeoCities - quick and easy web site hosting, just $8.95/month.
http://geocities.yahoo.com/ps/info1
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=========================================================================
Date: Tue, 20 Nov 2001 16:44:25 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUEDASSOCIATES.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hmmm,
At first I thought this must be a joke but now I wonder if it was sent
by a competitor of this company...
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Tue, 20 Nov 2001 09:11:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: How to remove silk screen from the plated area
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I have received boards from my fab suppliers and found with silk screen
on plated area where EMI shield is mounted. The fabs are ENIG
processed. Is there any solution or method to remove white silk screen?
re,
Ken Patel
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Date: Tue, 20 Nov 2001 11:09:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Solder spikes and icicling
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_742EB853.AACBA6F3"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_742EB853.AACBA6F3
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
Nitrogen at wave not on, lack of flux, large lead diameters with pointy =
apex's, flux type. Those are the culprits I have found that resolved past =
problems for me. =20
Kathy=20
--=_742EB853.AACBA6F3
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Nitrogen at wave not on, lack of flux, large lead diameters with pointy
apex's, flux type. Those are the culprits I have found that resolved past
problems for me. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_742EB853.AACBA6F3--
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=========================================================================
Date: Tue, 20 Nov 2001 12:03:33 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neda Thrash <[log in to unmask]>
Subject: Re: Circuit Repair Facility
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
We can help you.=20
Call 601-486-1700.
<<< [log in to unmask] 11/19 4:56p >>>
My company was using Pacific Meta Corp for replating of gold fingers after
solder was accidentally deposited. They are no longer doing repairs. Can
someone guide me to a new company that can replate a single gold finger. =
We
are located in Salt Lake City.
Jan Satterfield
Process Engineer
L-3 Communications
---------------------------------------------------------------------------=
------
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E-mail Archives
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additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 =
ext.5315
---------------------------------------------------------------------------=
------
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Date: Tue, 20 Nov 2001 12:17:51 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO :
VALUEDASSOCIATES.
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
And here I thought it was just another misuse of the forum to advertise
company capability or to make a business announcement.
Mel Parrish
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Christison
Sent: Tuesday, November 20, 2001 8:44 AM
To: [log in to unmask]
Subject: Re: [TN] (VIRUS ALERT!!!) [TN] O. MATERIALS. TO :
VALUEDASSOCIATES.
Hmmm,
At first I thought this must be a joke but now I wonder if it was sent
by a competitor of this company...
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
----------------------------------------------------------------------------
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----------------------------------------------------------------------------
-----
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Date: Tue, 20 Nov 2001 19:11:28 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bob Willis <[log in to unmask]>
Subject: Re: Solder mask outgassing
X-To: "Creswick, Steven" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_01C0_01C171F7.27D02DE0"
This is a multi-part message in MIME format.
------=_NextPart_000_01C0_01C171F7.27D02DE0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
The video clips are on my sever to access them now use the following =
links. You will need RealPlayer to view the clips.
www.seminar-registrations.com/bw508.rm
www.seminar-registrations.com/bw507.rm
I produced the video clips for a flip chip and underfill workshop I was =
organising with Speedline Technologies in the UK at the start of the =
year. I was trying to show the problems of outgassing from the mask =
during reflow of no-flow underfills. The same issue can occur with =
traditional underfill but these can cause misaligment of the devices =
before the solder joint is formed on the connection pads.
I am currently conducting a project as part of team at NPL on solder =
mask related problems related to cure of masks.
The text below outlines the project and I have also used it for a =
abstract for the Printed Circuit Board World Convention.
Hope this all of interest.
Characterising Solder Resist/Mask Performance and Degree of Cure
Chris Hunt, Alan Brewing and Bob Willis=20
National Physical Laboratory Teddington, Middlesex, England
Industry currently uses a number of simple ad-hoc evaluation test =
methods that correlate poorly with the mask performance during assembly. =
The industry has long understood that the test methods contained in =
national and international specifications to be inadequate. NPL is to =
evaluate a number of test methods and show the relevance to issues =
experienced during assembly operations. The project will also bench-mark =
the current test methods with new procedures.
Issues with voiding during underfill cure have been documented, where =
out-gassing from the solder mask has occurred. Voids in the underfill =
can dramatically impact on the reliability performance of the solder =
joints and the mechanical strength of devices to the resist surface. =
This is particularly important with modern electronics. Evolution of gas =
and changes in surface tension can significantly influence the =
occurrence, or the adhesion of solder balls, during soldering. =
Absorption by solder masks of solvents and other components from =
cleaning, which then can be desorbed, will significantly impinge on =
solder wetting.
The aim of the NPL project in conjunction to leading solder mask =
supplier and soldering material manufacturers will help to achieve the =
following project goals:
Produce a code of practice to define test methods and criteria to allow =
companies to simply define and test printed circuit boards prior to =
assembly or supply.
Investigate current and new methods of assessing the degree of cure of =
solder masks after fabrication and prior to assembly. Define test =
methods which could be economically introduced to assembly and =
fabrication operations.
Compare assembly defects like resist out-gassing, underfill voiding and =
solder balling and the variations on selected solder resist surfaces.
Propose these test methods and procedures to national and international =
standards committees to incorporate into future standards to reduce the =
variation of test results in the industry.
This technical paper will outline the work conducted and the results =
obtained.
Bob Willis
Electronic Presentation Services
2 Fourth Ave, Chelmsford, Essex, CM1 4HA England
See us at APEX 2002 www.bobwillis.co.uk/workshops/apex/apex.htm
www.bobwillis.co.uk
Tel: (44) 01245 351502 Fax: (44) 01245 496123
Single solution to your seminar, conference or roadshow =
www.seminar-registrations.com
----- Original Message -----=20
From: Creswick, Steven=20
To: [log in to unmask]
Sent: Tuesday, November 20, 2001 3:40 PM
Subject: Solder mask outgassing
Bob,
I for one am interested in seeing the RealTime video clip/s on solder =
mask
outgassing
Steven Creswick - Gentex Corp
------=_NextPart_000_01C0_01C171F7.27D02DE0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>The video clips are on my sever to =
access them now=20
use the following links. You will need RealPlayer to view the=20
clips.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.seminar-registrations.com/bw508.rm">www.seminar-regist=
rations.com/bw508.rm</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.seminar-registrations.com/bw507.rm">www.seminar-regist=
rations.com/bw507.rm</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I produced the video clips for a flip =
chip and=20
underfill workshop I was organising with Speedline Technologies in the =
UK at the=20
start of the year. I was trying to show the problems of outgassing from =
the mask=20
during reflow of no-flow underfills. The same issue can occur with =
traditional=20
underfill but these can cause misaligment of the devices before the =
solder joint=20
is formed on the connection pads.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>I am currently conducting a project as =
part of team=20
at NPL on solder mask related problems related to cure of =
masks.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The text below outlines the project and =
I have also=20
used it for a abstract for the Printed Circuit Board World=20
Convention.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Hope this all of interest.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><BR>Characterising Solder Resist/Mask =
Performance=20
and Degree of Cure</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Chris Hunt, Alan Brewing and Bob Willis =
<BR>National Physical Laboratory Teddington, Middlesex, =
England</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Industry currently uses a number of =
simple ad-hoc=20
evaluation test methods that correlate poorly with the mask performance =
during=20
assembly. The industry has long understood that the test methods =
contained in=20
national and international specifications to be inadequate. NPL is to =
evaluate a=20
number of test methods and show the relevance to issues experienced =
during=20
assembly operations. The project will also bench-mark the current test =
methods=20
with new procedures.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Issues with voiding during underfill =
cure have been=20
documented, where out-gassing from the solder mask has occurred. Voids =
in the=20
underfill can dramatically impact on the reliability performance of the =
solder=20
joints and the mechanical strength of devices to the resist surface. =
This is=20
particularly important with modern electronics. Evolution of gas and =
changes in=20
surface tension can significantly influence the occurrence, or the =
adhesion of=20
solder balls, during soldering. Absorption by solder masks of solvents =
and other=20
components from cleaning, which then can be desorbed, will significantly =
impinge=20
on solder wetting.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>The aim of the NPL project in =
conjunction to=20
leading solder mask supplier and soldering material manufacturers will =
help to=20
achieve the following project goals:</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Produce a code of practice to define =
test methods=20
and criteria to allow companies to simply define and test printed =
circuit boards=20
prior to assembly or supply.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Investigate current and new methods of =
assessing=20
the degree of cure of solder masks after fabrication and prior to=20
assembly. Define test methods which could be economically =
introduced to=20
assembly and fabrication operations.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Compare assembly defects like resist =
out-gassing,=20
underfill voiding and solder balling and the variations on selected =
solder=20
resist surfaces.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Propose these test methods and =
procedures to=20
national and international standards committees to incorporate into =
future=20
standards to reduce the variation of test results in the =
industry.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>This technical paper will outline the =
work=20
conducted and the results obtained.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><BR></FONT> </DIV>
<DIV> </DIV>
<DIV>Bob Willis<BR>Electronic Presentation Services<BR>2 Fourth Ave, =
Chelmsford,=20
Essex, CM1 4HA England</DIV>
<DIV> </DIV>
<DIV>See us at APEX 2002 <A=20
href=3D"http://www.bobwillis.co.uk/workshops/apex/apex.htm">www.bobwillis=
.co.uk/workshops/apex/apex.htm</A></DIV>
<DIV> </DIV>
<DIV><A =
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245 351502 Fax: (44) 01245 496123</DIV>
<DIV> </DIV>
<DIV>Single solution to your seminar, conference or roadshow <A=20
href=3D"http://www.seminar-registrations.com">www.seminar-registrations.c=
om</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Creswick,=20
Steven</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A=20
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 20, =
2001 3:40=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Solder mask =
outgassing</DIV>
<DIV><BR></DIV>Bob,<BR><BR>I for one am interested in seeing the =
RealTime=20
video clip/s on solder mask<BR>outgassing<BR><BR>Steven Creswick - =
Gentex=20
Corp</BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_01C0_01C171F7.27D02DE0--
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Date: Mon, 19 Nov 2001 07:48:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: test e-mail
MIME-Version: 1.0
Content-Type: text/plain
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Tue, 20 Nov 2001 15:28:45 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: How to remove silk screen from the plated area
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Send them back to their maker.
Dave Fish
----- Original Message -----
From: "Ken Patel" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 20, 2001 9:11 AM
Subject: [TN] How to remove silk screen from the plated area
> I have received boards from my fab suppliers and found with silk screen
> on plated area where EMI shield is mounted. The fabs are ENIG
> processed. Is there any solution or method to remove white silk screen?
>
> re,
> Ken Patel
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>
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Date: Tue, 20 Nov 2001 14:42:47 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: test e-mail
MIME-Version: 1.0
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So Jim, did we pass, huh, did we did we did we????? Are you grading on a
curve? Was it a life test and do you consider a sample size of one to be
an adequate test? What standards exist for an e-mail test......
Yup, definitely time to lay off the Dew for the day.......
Doug Pauls
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Date: Tue, 20 Nov 2001 17:38:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_120.76ac8fb.292c3576_boundary"
--part1_120.76ac8fb.292c3576_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels
of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse
in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way
ENIG always plates, and it's just the way it always looks down inside holes,
I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
--part1_120.76ac8fb.292c3576_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Just recieved a bare fab that I noticed some very rough walls of the barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse in the smaller diameter holes than do the larger holes. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com/
<BR>
<BR>and look at the two pics titled "rough walls"...
<BR>
<BR>Didn't see any real voids, or fibers protruding...just maybe this is the way ENIG always plates, and it's just the way it always looks down inside holes, I've never noticed it being this rough before...See any problems?
<BR>
<BR>Thanks!
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_120.76ac8fb.292c3576_boundary--
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Date: Wed, 21 Nov 2001 07:52:22 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch II
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, All,
I want to thank all of you, especially Hans, Rummy, Edward, Moonman who
reached near-critical mass early on, Ian Hanna and others for taking time
and trouble on and off line to offer me so much valuable help and advice on
my board problems. In spite of the fundemental nature of the original
questions, this thread became a rope - a sure sign that there are still
issues and information our there to be shared and discussed on "old-hat"
topics, even if they only serve to educate the novices and act as reminders
to the more expert.
This is an excellent forum - long may it continue to be so. I've found a
way forward again as a result of all the help, and will follow up on Hans's
lead about the technique of plating holes only as a way of keeping copper
weights down in boards with multiple blind via groups. This sounds like an
ideal way to build this type of PCB if the process is reliable and provides
good connectivity to the outside layers.
Again my profound thanks and appreciation.
Peter Duncan
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Thu, 26 Oct 2000 10:15:32 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: chris johnston <[log in to unmask]>
Subject: Re: thermistors
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I have need of some design information on thermistors, having never
designed with such devices before, I would like to know the technically
correct way to do things, I mean common sense tells me quite a lot, but the
proper way does not go astray. If any one can point me in the right
direction for some design information, it would be greatly appreciated, or
even email, [log in to unmask], please remember, I live in Australia,
electricity was only invented here last week, and the horseless carriage the
week before.
Christopher Johnston.
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Date: Tue, 20 Nov 2001 18:59:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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In a message dated 11/20/01 2:40:04 PM Pacific Standard Time,
[log in to unmask] writes:
Steve:
Do not know if this roughness is a problem, as that ain't my area of
expertise, (if I have one....) but, the "The roughness seems worse in the
smaller diameter holes than do the larger holes" statement yells that the
problem is caused by gas bubbles trapped in the holes....and thus could
probably be remedied (minimized) by "canting" or tipping the boards during
Nickel plating, to allow the bubbles to come out of the holes.
Rudy Sedlak
RD Chemical Company
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Date: Tue, 20 Nov 2001 16:01:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
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boundary="----_=_NextPart_001_01C1721F.A3612590"
This message is in MIME format. Since your mail reader does not understand
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------_=_NextPart_001_01C1721F.A3612590
Content-Type: text/plain;
charset="iso-8859-1"
hi,
they look somewhat what a hole looks like when it comes out of the electroless copper bath and strike bath. i'd say it looks okay. do you have the mounts that the fabricator, hopefully, sent to you when you got the boards? that should be the final word.
phil
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 2:39 PM
To: [log in to unmask]
Subject: [TN] Rough PTH barrel walls in ENIG plated PCB...
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness seems worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way ENIG always plates, and it's just the way it always looks down inside holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
------_=_NextPart_001_01C1721F.A3612590
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=294125823-20112001><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=294125823-20112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=294125823-20112001><FONT face=Arial color=#0000ff size=2>they
look somewhat what a hole looks like when it comes out of the electroless copper
bath and strike bath. i'd say it looks okay. do you have the mounts
that the fabricator, hopefully, sent to you when you got the boards? that
should be the final word.</FONT></SPAN></DIV>
<DIV><SPAN class=294125823-20112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=294125823-20112001><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 20, 2001 2:39
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Rough PTH barrel
walls in ENIG plated PCB...<BR><BR></FONT></DIV><FONT
face=arial,helvetica><FONT size=2>Hi all! <BR><BR>Just recieved a bare fab
that I noticed some very rough walls of the barrels of the PTH's. This is a
ENIG plated PCB by the way. The roughness seems worse in the smaller diameter
holes than do the larger holes. Go to:
<BR><BR>http://www.stevezeva.homestead.com/ <BR><BR>and look at the two pics
titled "rough walls"... <BR><BR>Didn't see any real voids, or fibers
protruding...just maybe this is the way ENIG always plates, and it's
just the way it always looks down inside holes, I've never noticed it being
this rough before...See any problems? <BR><BR>Thanks! <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1721F.A3612590--
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Date: Wed, 21 Nov 2001 08:06:07 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Board Warp
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Thanks, Jeff. Sorry, I missed you from my list of special thankees, but
your help has been tremendous. I should know today if I have boards that
are flat enough to use.
Cheers
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board Warp
11/20/01 10:54 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
If the clamping/baking doesn't remove the warp on the first try, you could
give it one more try. What we do in these cases is to slightly bend a pair
of tool steel bars. We then clamp these bars to the warped edge bowing that
edge in the opposite direction. Go through the baking cycle again and cross
your fingers.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, November 18, 2001 9:50 PM
To: [log in to unmask]
Subject: Re: [TN] Board Warp
Dear All,
Thanks a lot for all the info and feedback. It seems to me that things
haven't changed a lot over the years as far as trying to straighten boards
is concerned - it's still a matter of clamping the boards flat, heating
them up and cooling them down again, and hoping you've taken out more bow
and twist than you've added.
Couple of quick supplementary questions: if the clamping, heating and
cooling doesn't quite work first time, will it make any difference to try
the technique again? I wouldn't like to repeat it too often because of all
the effects on stresses, IMC's and so forth that frequent thermal
excursions will promote - is the board straightening method a one-shot try,
or how many times would you risk repeating the technique to try and make
things right?
Many thanks again to all who responded to my distress call.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN
Peter/Asst
Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] Board
Warp
11/16/01 09:53 PM
Please respond to
"TechNet E-Mail
Forum."
Peter,
As MoonMan says, this type of problem is preventable by using proper DFM
procedures, but then folks in the repair business like us would have
nothing
to do!
Removing warp is actually rather simple, and is an IPC documented
procedure.
I've attached a link to our online procedure with more details. We find
that
about 80% of the time we can remove warp and bring bare, or assembled,
boards into spec. However, sometimes the inherent stress in the remaining
20% is just too great to overcome.
Bow and Twist Repair Procedure
http://www.circuittechctr.com/guides/3-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Thursday, November 15, 2001 9:11 PM
To: [log in to unmask]
Subject: [TN] Board Warp
Hi, All,
We have received a number of 12 layer ENIG-finished MLB's with blind via
hole groups, and which are destined to have BGA's (1.27mm pitch) populated
onto them. The boards measure 8.2" x 5.7" and they are warped to the extent
of one corner being raised by between 1.5mm and about 3mm. The axis of the
warp is the long side of a triangle whose other two sides measure about 5.7
x 5.7.
In this age of sensitive boards, does a technology or technique exist for
straightening the boards back into spec - they are class 3 boards - or is
this an area where angels still fear to tread?
The boards are desperately urgent, which is why I'm asking this rather than
simply rejecting them and having them re-made (which takes about a month).
TIA for any help.
Peter Duncan
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Date: Wed, 21 Nov 2001 08:38:50 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
I've had a number of ENIG boards made, and they don't look THAT rough.
Looks like someone's run a blunt drill through the board very fast.
Problems? - apart from "Are the holes cleaned and conditioned properly for
plating in the first place?":
Ductility of the copper, or at least its ability to stretch as much as it
could in the Z, perhaps.
Reliability of interconnection between layers?
Local delam behind the plating if the drill did have a rough ride?
Dunno.
Do you have any test coupons exhibiting the same phenomenon to cross
section?
Peter Duncan
"Stephen R.
Gregory" To: TechNet@IPC.ORG
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
L.COM> Aero/ST Group)
Sent by: Subject: [TN] Rough PTH barrel walls in ENIG
TechNet plated PCB...
<[log in to unmask]
ORG>
11/21/01
06:38 AM
Please
respond to
"TechNet
E-Mail
Forum."
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the
barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness
seems worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the
way ENIG always plates, and it's just the way it always looks down inside
holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
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Date: Tue, 20 Nov 2001 21:08:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Steve
ENIG don't usually appear like yours. As the others - have you got cross
sections?
Holes can be rough and still have intact plating - or there may be some many
folds and microvoids that you may have problems
Susan Mansilla
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Date: Tue, 20 Nov 2001 21:18:26 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: RF "Black Magic", why do vias need to be beneath components?
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves lucky...
-Steve Gregory-
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Date: Tue, 20 Nov 2001 21:45:58 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_5b.1f040796.292c6f66_boundary"
--part1_5b.1f040796.292c6f66_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Steve,
The holes on your site look like rough drilling.
ENIG mimicks the appeareance of whatever substarte it is plated on. These
holes were rough before ENIG plating.
If a crossection shows adequate copper plate then the roughness could be non
consequential. If u need to talk more about this e-mail me at [log in to unmask]
George Milad
Shipley
--part1_5b.1f040796.292c6f66_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Steve,
<BR>The holes on your site look like rough drilling.
<BR>ENIG mimicks the appeareance of whatever substarte it is plated on. These holes were rough before ENIG plating.
<BR>If a crossection shows adequate copper plate then the roughness could be non consequential. If u need to talk more about this e-mail me at [log in to unmask]
<BR>George Milad
<BR>Shipley</FONT></HTML>
--part1_5b.1f040796.292c6f66_boundary--
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Date: Wed, 21 Nov 2001 08:02:50 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Steve,
I completly agree with George.It has nothing with ENIG.Probably too =
rough
drilling or too agresive desmear.
ENIG finishing does follow surface geometry.This is contrary to =
HASL,that
fill some of valleys giving impression that the hole is smooth.
By the way,if the cross sections are OK, solder float tests wre OK ( =
copper
mechanical properties) and they do not create problems in soldering (
cleaning etc) ,and if there diameter is OK, I do not see reasons for =
reject.
Edward=20
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: George Milad [SMTP:[log in to unmask]]
> Sent: =E3 =F0=E5=E1=EE=E1=F8 21 2001 4:46
> To: [log in to unmask]
> Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
>=20
> Steve,=20
> The holes on your site look like rough drilling.=20
> ENIG mimicks the appeareance of whatever substarte it is plated on. =
These
> holes were rough before ENIG plating.=20
> If a crossection shows adequate copper plate then the roughness could =
be
> non consequential. If u need to talk more about this e-mail me at
> [log in to unmask]
> George Milad=20
> Shipley
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Date: Tue, 20 Nov 2001 23:51:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
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Date: Wed, 21 Nov 2001 08:12:51 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: Solder spikes and icicling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter,
Did some work recently on large BNC connectors, the trouble with them is
that the body of the connector acts as a great heat sink thus drawing heat
away from the solder land and connector lead I was trying to solder.
P.s when I contacted the component supplier's they informed me that the
component in question was not suitable for wave solder. We now solder them
with an RF soldering iron.
Hope this is of some use.
Steve.
-----Original Message-----
From: peter lee [mailto:[log in to unmask]]
Sent: 20 November 2001 16:56
To: [log in to unmask]
Subject: [TN] Solder spikes and icicling
Hello,
Can someone explain what are possible causes for wave
soldering spikes and icicling on the assemblies?
I am encountering this defect on boards with larger
BNC connectors and fuse jumpers. Could this be a
pre-heating issue? How would one resolve this?
Rgds,
Peter
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Date: Wed, 21 Nov 2001 08:26:45 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Brown <[log in to unmask]>
Organization: Xyratex
Subject: Raw Card Track Repairs
MIME-Version: 1.0
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People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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Date: Wed, 21 Nov 2001 08:54:35 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brown <[log in to unmask]>
Subject: Non-wetting
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Good Morning, this is my first posting to this forum I hope to get some
help. We are building a small PWB with 4 per panel. The problems we are
encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
are all located near to or the center of the PWB. There is paste on the pad
and the component placed properly but the paste will not wet onto the leads
or terminations.
What have we done?
1. Run the PWB at various profiles even the highest. Still have problem.
2. Changed from no clean to aqueous with an agressive flux. Still have
problem.
3. Changed screen apertures. Still have problem.
This PWB is multi layer and heavily populated.
Are there any hints as to what we do next?
_________________________________________________________________
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Date: Wed, 21 Nov 2001 17:35:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Solutions may be more elegant these days, but a mechanical guard screen
coupled to an interlock used to be the method of preventing squashed
operators. In position, the screen prevented the operator getting access to
the moving parts of the machine while it was operating, and with the screen
raised, the interlock prevented the machine from operating by activating a
cut-out. Not fool-proof, as ingenious operators on piece-work would bypass
the interlock to keep the machine functioning with the screen raised to
increase throughput rather than spending time raising and lowering a screen
for each piece of work. Bear in mind that "bolt-on" safety mechanisms are
never as good as mechanisms that are designed in with the machine to start
with.
Special fixtures will be required anyway, but if you use them without a
guard screen of some kind as well, the operator can still get access while
the machine is capable of being operated. The risk of injury is reduced but
still present. I'm not up on current safety methods in this situation, so
can't advise alternatives, but a light curtain that comes on when the start
button is pressed sounds like a neat way of achieving the desired result.
At least if it gets too dirty or fails, the machine will be inoperable,
which is erring on the side of safety.
Peter Duncan
Peter Lee
<ppwlee@YAHOO To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Manual Press for PEM PCB
<[log in to unmask] fastener
ORG>
11/21/01
03:51 PM
Please
respond to
"TechNet
E-Mail
Forum."
My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
_________________________________________________________
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Date: Wed, 21 Nov 2001 17:52:58 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
The number of track repairs allowable is normally a matter between the
contractor and the customer and depends to some extent on the design and
its operating environment. I once had a customer who insisted on reviewing
the situation if the number of track repairs, cuts or jumpers went above 3,
and the board had to be re-routed if the number of track mods exceeded 5.
On the other hand, I have seen customer-owned card assemblies with a
veritable wiring harness of repair and mod wires, so there are no fixed
rules.
You have to assess the situation on its own merits, rather than relying on
specs to tell you the road out. All things being equal, though, if the
repairs are carried out well to a spec such as IPC-7721, and they don't
interfere with, or reduce the reliable mountability of components, you
should not have much of an issue. Having said that, and not knowing the
extent of the track repairs being proposed, I would not like to accept new
boards with long stretches of repaired track (greater that, say, half an
inch) or more than about 6 repairs, but that's just my personal view.
It's not always an easy call to make, but discuss it with the designers,
the customer if need be, and the assembly line. Repaired tracks are weaker
than original track, and this must be borne in mind for processing as well
as reliability in the field. If in doubt, let the fab house repair one or
two (best and worst case) and see how they fare through the production
cycle. Then you can better determine what level of repair you can accept.
Good luck!
Peter Duncan
Stephen Brown
<[log in to unmask] To: [log in to unmask]
RATEX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Raw Card Track Repairs
11/21/01 04:26 PM
Please respond to
"TechNet E-Mail
Forum."
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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Date: Wed, 21 Nov 2001 18:31:52 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Non-wetting
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, John,
Welcome to TN. I have to answer your question with more questions, like:
1) Are the problem components used anywhere else on the board and are they
being properly wetted in those other positions?
2) What board finish are you using?
3) What is the termination finish of the components? Do they have any
silver content for any reason?
4) How old are the components and what conditions have they been stored
under?
5) Are the same locations failing to wet each time, or are some wetting in
some cases and others in others?
6) What solder are you using?
I suspect you have an oxidisation problem with the component leads, perhaps
leeching of silver if there is any silver content. If it's a silver
problem, try using a 2% silver solder to redress the balance. If it's
oxide, you will have to replace the components or re-tin them in a solder
pot with a very aggressive flux.
Maybe I can help more with more detail.
Peter Duncan
John Brown
<johnbrown118@HO To: [log in to unmask]
TMAIL.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Non-wetting
>
11/21/01 04:54
PM
Please respond
to "TechNet
E-Mail Forum."
Good Morning, this is my first posting to this forum I hope to get some
help. We are building a small PWB with 4 per panel. The problems we are
encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
are all located near to or the center of the PWB. There is paste on the pad
and the component placed properly but the paste will not wet onto the leads
or terminations.
What have we done?
1. Run the PWB at various profiles even the highest. Still have problem.
2. Changed from no clean to aqueous with an agressive flux. Still have
problem.
3. Changed screen apertures. Still have problem.
This PWB is multi layer and heavily populated.
Are there any hints as to what we do next?
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
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Date: Wed, 21 Nov 2001 10:14:57 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
The best method I've seen of protecting press equipment is to wire the
equipment so that the operator has to press two buttons simultaneously
to operate the equipment and that the buttons are far enough apart that
both hands are required. Of course this is in addition to rather than
instead of the usual guards etc. A really determined idiot will always
find a way to bypass safety guards but this way seemed elegant and
effective.
Regards,
"" wrote:
>
> Solutions may be more elegant these days, but a mechanical guard screen
> coupled to an interlock used to be the method of preventing squashed
> operators. In position, the screen prevented the operator getting access to
> the moving parts of the machine while it was operating, and with the screen
> raised, the interlock prevented the machine from operating by activating a
> cut-out. Not fool-proof, as ingenious operators on piece-work would bypass
> the interlock to keep the machine functioning with the screen raised to
> increase throughput rather than spending time raising and lowering a screen
> for each piece of work. Bear in mind that "bolt-on" safety mechanisms are
> never as good as mechanisms that are designed in with the machine to start
> with.
>
> Special fixtures will be required anyway, but if you use them without a
> guard screen of some kind as well, the operator can still get access while
> the machine is capable of being operated. The risk of injury is reduced but
> still present. I'm not up on current safety methods in this situation, so
> can't advise alternatives, but a light curtain that comes on when the start
> button is pressed sounds like a neat way of achieving the desired result.
> At least if it gets too dirty or fails, the machine will be inoperable,
> which is erring on the side of safety.
>
> Peter Duncan
>
> Peter Lee
> <ppwlee@YAHOO To: [log in to unmask]
> .COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
> Sent by: Aero/ST Group)
> TechNet Subject: Re: [TN] Manual Press for PEM PCB
> <[log in to unmask] fastener
> ORG>
>
> 11/21/01
> 03:51 PM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
> My application requires operator to support and locate the board
> assembly with one hand while activating the start button on the press to
> install the PEM fasteners.
>
> For safety reason I am considering limiting operator access while the
> machine is in operation.
>
> What is the normal practice? Installing a light curtain sensor around
> the area? Or multi-purpose fixtures that will secure the board to ensure
> a "hands free" operation?
>
> Any input is greatly appreciated.
>
> Rgd,
> Peter
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
> Sent: November 14, 2001 6:16 AM
> To: [log in to unmask]
> Subject: Re: [TN] Manual Press for PEM PCB fastener
>
> Peter,
>
> Might suggest you look over Janesville Tool at
> http://www.janesvilletool.com/.
> We use their presses for setting eyelets.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
> www.circuittechctr.com
> [log in to unmask]
> 978-374-5000
>
> Sign up for our Free E-mail Newsletter at:
> www.circuittechctr.com/general/free_email.htm
>
> -----Original Message-----
> From: Peter Lee [mailto:[log in to unmask]]
> Sent: Wednesday, November 14, 2001 2:46 AM
> To: [log in to unmask]
> Subject: [TN] Manual Press for PEM PCB fastener
>
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
> Rgds,
> Peter
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
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> -----
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>
> ---------------------------------------------------------------------------------
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> [This e-mail is confidential and may also be privileged. If you are not the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
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>
> ---------------------------------------------------------------------------------
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--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Wed, 21 Nov 2001 07:24:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Non-wetting
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I am assuming that you actually profiled the board and know that the
temperature profile conforms to the recomendations of the paste
manufacturer.
You need to determine if the board or components are at fault. J-STD-002 and
J-STD-003 provide test methods for the components and the board,
respectively. Did the paste wet to the board and leave the component
non-wetted? I would check the parts.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of John Brown
> Sent: Wednesday, November 21, 2001 3:55 AM
> To: [log in to unmask]
> Subject: [TN] Non-wetting
>
>
> Good Morning, this is my first posting to this forum I hope to get some
> help. We are building a small PWB with 4 per panel. The problems we are
> encountering are on 0603 resistors & capacitors and SOIC (8pin) etc. These
> are all located near to or the center of the PWB. There is paste
> on the pad
> and the component placed properly but the paste will not wet onto
> the leads
> or terminations.
> What have we done?
> 1. Run the PWB at various profiles even the highest. Still have problem.
> 2. Changed from no clean to aqueous with an agressive flux. Still have
> problem.
> 3. Changed screen apertures. Still have problem.
> This PWB is multi layer and heavily populated.
> Are there any hints as to what we do next?
>
> _________________________________________________________________
> Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> additional
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> ------------------------------------------------------------------
> ---------------
>
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Date: Wed, 21 Nov 2001 07:24:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve
I hear your agony almost anybody who assembles RF boards have to face with
these difficulties
The main reason is RF parts need good ground and a good ground for RF
designers means
many vias to provide this.
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 9:18 PM
To: [log in to unmask]
Subject: [TN] RF "Black Magic", why do vias need to be beneath
components?
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been
bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive
that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves
lucky...
-Steve Gregory-
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Date: Wed, 21 Nov 2001 14:38:26 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: sedat bayar <[log in to unmask]>
Subject: nitrogen purity
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Hello All,
What is the minimum nitrogen purity to use in the convection reflow system?
Thanks
Sedat BAYAR
Aselsan Inc.
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Date: Wed, 21 Nov 2001 13:36:07 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Non-wetting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi John,
some questions:
- have you tried to handsolder and did you get good wetting ?
- did you profile for this particular area ?
- what kind of surface do you have?
- have you checked for contamination?
- are you sure what you see is non-wetting or could it be dewetting ?
- how about the wetting in other areas than in the center ?
- how old are the parts/boards ?
- were they stored properly ?
- tell us more about your profile, is your equipment capable of handling
those assemblies ?
- if you are sure you have done your best, have you thought of giving this
to a laboratory for further investigations?
- what is so special with the area, the parts ?
A lot of questions and there may be some more
Tell us more
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Date: Wed, 21 Nov 2001 08:13:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brewer <[log in to unmask]>
Subject: grounds....
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Steve,
As a ham radio operator, all I could say is that at RF (and especially very high freq RF), if
you make
a ground a significant distance away (in relation to the wavelength of the RF signal) it
becomes NOT a ground. Getting ground CLOSE to the point being grounded
is essential. At DC, it doesnt matter...ground's ground as long as there's ANY path
(within reason) to get there.
That'd be my guess.
Happy VF (Virtual Friday!)
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Date: Wed, 21 Nov 2001 08:21:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
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Peter,
The Cambridge Automatic press (AE2000) has a nice safety interlock for
keeping the fingers out of the press area. They use an air driven ring
which comes down around the work piece and has a normally open magnetic
air switch which prevents movement of the main ram until it is within
about 1/4" of the board surface. It works very well.
Phil Nutting
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 2:51 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
My application requires operator to support and locate the board
assembly with one hand while activating the start button on the press to
install the PEM fasteners.
For safety reason I am considering limiting operator access while the
machine is in operation.
What is the normal practice? Installing a light curtain sensor around
the area? Or multi-purpose fixtures that will secure the board to ensure
a "hands free" operation?
Any input is greatly appreciated.
Rgd,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
Sent: November 14, 2001 6:16 AM
To: [log in to unmask]
Subject: Re: [TN] Manual Press for PEM PCB fastener
Peter,
Might suggest you look over Janesville Tool at
http://www.janesvilletool.com/.
We use their presses for setting eyelets.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, November 14, 2001 2:46 AM
To: [log in to unmask]
Subject: [TN] Manual Press for PEM PCB fastener
Thanks Earl for your extensive report on NPI which will keep me tied up
for a while in reading through it. I appreciate you for sharing your
experience and information in this forum.
I have another question for the day: Does anyone know of a good and
reliable machine for press-in PEM PCB fasteners?
I am considering machines from PENN ENGINEERING and SCHMIDT but like to
get more inputs on both the press machine and the process. Would a
manual press be able to put out ~2200 lbs at the fastener in practice?
What are some common application problems that one should look out for?
Rgds,
Peter
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Date: Wed, 21 Nov 2001 08:26:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Goldman, Patricia J." <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
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Steve,
I agree with both George and Edward. =20
The best clue (even before looking at the pictures) was your statement =
that the smaller size hole was affected. Smaller holes are more =
difficult to drill smoothly, shall we say. When looking at the rows of =
holes, note that the roughness defect looks nearly identical in each =
hole. Regarding ENIG, it is a pretty thin coating - too thin to add =
significantly to topography. Any defect from it would more likely show =
up as poor coverage or as a salting-out (sanding?) type of defect. A =
gas bubble defect normally shows up as a perfect ring somewhere in the =
hole barrel and usually would prevent plating coverage in that area. =20
Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]
-----Original Message-----
From: Edward Szpruch [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 1:03 AM
To: [log in to unmask]
Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
Steve,
I completly agree with George.It has nothing with ENIG.Probably too =
rough
drilling or too agresive desmear.
ENIG finishing does follow surface geometry.This is contrary to =
HASL,that
fill some of valleys giving impression that the hole is smooth.
By the way,if the cross sections are OK, solder float tests wre OK ( =
copper
mechanical properties) and they do not create problems in soldering (
cleaning etc) ,and if there diameter is OK, I do not see reasons for =
reject.
Edward=20
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: George Milad [SMTP:[log in to unmask]]
> Sent: =E3 =F0=E5=E1=EE=E1=F8 21 2001 4:46
> To: [log in to unmask]
> Subject: Re: [TN] Rough PTH barrel walls in ENIG plated PCB...
>=20
> Steve,=20
> The holes on your site look like rough drilling.=20
> ENIG mimicks the appeareance of whatever substarte it is plated on. =
These
> holes were rough before ENIG plating.=20
> If a crossection shows adequate copper plate then the roughness could =
be
> non consequential. If u need to talk more about this e-mail me at
> [log in to unmask]
> George Milad=20
> Shipley
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Date: Wed, 21 Nov 2001 08:33:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
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Steve,
I don't have a hard and fast number, but for new bare boards we like no
etch (track) cuts or repairs. For production stuffed PTH boards we try
to keep the number of rework cuts and jumpers to a minimum partially for
reliability reasons but also for the labor cost reasons. Hand rework
can get expensive not to mention the "artwork" some reworks take on
depending on the complexity. For R&D boards, well... there R&D boards.
Need I say more?
Phil Nutting
-----Original Message-----
From: Stephen Brown [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 3:27 AM
To: [log in to unmask]
Subject: [TN] Raw Card Track Repairs
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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Date: Wed, 21 Nov 2001 08:29:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Rough PTH barrel walls in ENIG plated PCB...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C17290.83A17C20"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------_=_NextPart_001_01C17290.83A17C20
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charset="iso-8859-1"
I've been using ENIG on holes from .008 to .040 for three years. These look
fine. I call the roughness "barrelling". You still have plenty of Au in
the holes.
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 5:39 PM
To: [log in to unmask]
Subject: [TN] Rough PTH barrel walls in ENIG plated PCB...
Hi all!
Just recieved a bare fab that I noticed some very rough walls of the barrels
of the PTH's. This is a ENIG plated PCB by the way. The roughness seems
worse in the smaller diameter holes than do the larger holes. Go to:
http://www.stevezeva.homestead.com/
and look at the two pics titled "rough walls"...
Didn't see any real voids, or fibers protruding...just maybe this is the way
ENIG always plates, and it's just the way it always looks down inside
holes, I've never noticed it being this rough before...See any problems?
Thanks!
-Steve Gregory-
------_=_NextPart_001_01C17290.83A17C20
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.2314.1000" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=750383013-21112001>I've
been using ENIG on holes from .008 to .040 for three years. These look
fine. I call the roughness "barrelling". You still have plenty of Au
in the holes.</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr></FONT><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 20, 2001 5:39
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Rough PTH barrel
walls in ENIG plated PCB...<BR><BR></DIV></BLOCKQUOTE></DIV>
<BLOCKQUOTE></FONT><FONT face=arial,helvetica><FONT size=2>Hi all!
<BR><BR>Just recieved a bare fab that I noticed some very rough walls of the
barrels of the PTH's. This is a ENIG plated PCB by the way. The roughness
seems worse in the smaller diameter holes than do the larger holes. Go to:
<BR><BR>http://www.stevezeva.homestead.com/ <BR><BR>and look at the two pics
titled "rough walls"... <BR><BR>Didn't see any real voids, or fibers
protruding...just maybe this is the way ENIG always plates, and it's
just the way it always looks down inside holes, I've never noticed it being
this rough before...See any problems? <BR><BR>Thanks! <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C17290.83A17C20--
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Date: Wed, 21 Nov 2001 07:41:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Thomas Highland <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Steve:
Try IPC-600.
Thomas C. Highland
Quality Assurance Manager
Innovatec Communications
-----Original Message-----
From: Stephen Brown [mailto:[log in to unmask]]
Sent: Wednesday, November 21, 2001 02:27
To: [log in to unmask]
Subject: [TN] Raw Card Track Repairs
People.
We get our PCB's assembled to IPC-610 class 2. We have recently been
approached by our vendor regarding track repairs on our raw cards. Now I
personally am not keen on allowing this, but is there a standard for raw
cards similar to 610 which states an allowable quantity of track
repairs, if any?
Regards.
Steve Brown.
Commodity Specialist
Xyratex.
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Date: Wed, 21 Nov 2001 09:36:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lik-Jen Wu <[log in to unmask]>
Organization: Alcatel BND
Subject: Re: thermistors
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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You can find information regarding NTC thermistor on
http://www.chipcenter.com/eexpert/akruger/archive.html
Also, you can usually find an article or two on how to use thermistor at thermistor
manufacturer websites.
chris johnston wrote:
> I have need of some design information on thermistors, having never
> designed with such devices before, I would like to know the technically
> correct way to do things, I mean common sense tells me quite a lot, but the
> proper way does not go astray. If any one can point me in the right
> direction for some design information, it would be greatly appreciated, or
> even email, [log in to unmask], please remember, I live in Australia,
> electricity was only invented here last week, and the horseless carriage the
> week before.
>
> Christopher Johnston.
>
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Date: Wed, 21 Nov 2001 08:50:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Mario! I have a reference which may be helpful. A number of years ago
Nicolet Instruments (they are an xray equipment supplier) worked with
Sandia National Labs on the effects of ionizing radiation on electronic
components. They used a 100KV anode voltage and exposed a variety of
components to ionizing radiation for various dwell times. Their conclusion
was that it would require 43 days of direct exposure to damage a component
(for the testing conditions and specific components selected). Contact
Nicolet Test Instruments Division and obtain a copy of their Application
Notes titled "Ionizing Radiation and Its Effects Upon Electronic
Components" for the details. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Mario Dion <[log in to unmask]>@ipc.org> on 11/19/2001 09:21:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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Date: Wed, 21 Nov 2001 06:57:14 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Kimmey <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
MIME-Version: 1.0
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Steve,
Bear with me while I try this.
First of all there is an issue in RF design that has priority over
just about everything, that is the "return path". As a signal is sent down a
RF pathway (components, transmission lines, etc.) there is an equivalent
signal traveling the return path. If the return path is of a different
length than the signal path then there is a degradation of the signal (this
is a bad thing). So as RF goes the closer I get ground (my return path of
choice) the better integrity I have for my RF signal.
Secondly, there is the issue of RF ground as a part of the RF magic
(I think it is mostly the return path issue) having an effect on the
electromagnetic fields surrounding the RF signal path. Any disruption in
this field can cause integrity issues and performance failures.
Thirdly, there is the need to develop and market product rapidly in
todays world that tends to make the extra XXX hours needed to refine a
circuit enough to pull vias back impossible to get.
Lastly there is the RF factor. This is the fact that even the top RF
guys will admit to "it's magic" sometimes.
Even though as designers we hate to make the boards harder for you to
assemble, we must make the circuit work. This means vias near lands, poor
thermal relief around components (poor hell, usually none), and extremely
tight component placements are all caused by the driving need to maintain
the signal's integrity (so you can hear that cell call, static and all).
Though as a designer I feel bad for what we do to guys like you, know you
are appreciated for making us look good when the customer has a product that
achieves spec.
Hope it helps,
FNK
Frank N Kimmey, C.I.D.+
Senior PCB Designer
Powerwave Technologies
PH. 916-941-3159
Fax 916-941-3195
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, November 20, 2001 6:18 PM
To: [log in to unmask]
Subject: [TN] RF "Black Magic", why do vias need to be beneath
components?
Hi all!
I'm a ignorant process guy, I just build stuff. Don't have the "wizard"
knowledge about RF stuff. I gotta question though...
Why do RF components HAVE to have vias beneath the footprint of the devices?
This creates a problem with certain conductive adhesives that are used to
bond the PCA's to the chassis, from what I'm seeing, trying to adhere to
solder that has flowed out from initial reflow, or during rework when trying
to change a suspected failed component after the bloody thing has been
bonded
to the chassis.
Solder flows out and wets to the gold planes and de-bonds the adhesive
that's
been used to provide ground to the chassis.
Why the 'friggen vias? Can't they be placed just outside the component
footprint where the solder if it goes to the bottomside won't interfere with
whatever black-magic the the RF stuff needs?
Conductive adhesives don't seem to like solder that is liquidous, which will
naturally flow and spread during rework of a suspected failed part...if you
lose ground, you lose god...I've at least learned that, don't quite still
understand it, but ground is god in RF talk...
Those of you that haven't had to deal with this, consider yourselves
lucky...
-Steve Gregory-
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Date: Wed, 21 Nov 2001 10:22:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Dion <[log in to unmask]>
Subject: Re: Is X-RAY can damaged Flash IC i.e. imbeded program ?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bonjour David,
Thks for the information. In fact I got the report from Nicolet (Great
Mister Messerschmidt !) 2 days ago. Even though the report is dated from few
years already, it contains as you mentionned interesting information about
the effects of X-RAY on electronic components. Unfortunately it seems it is
not available in electronic format so if someone needs a copy I suggest to
contact Teradyne who now own Genrad which own Nicolet Imaging Systems....
My contact is M.Ken Messerschmidt, mailto:[log in to unmask]
Thks to all for your feedback about the subject,
Regards
Mario Dion
Mediatrix Telecom Inc
[log in to unmask]
--------------------------------------------------------
-----Original Message-----
From: David Hillman [mailto:[log in to unmask]]
Sent: 21 novembre, 2001 09:50
To: [log in to unmask]
Subject: Re: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Hi Mario! I have a reference which may be helpful. A number of years ago
Nicolet Instruments (they are an xray equipment supplier) worked with
Sandia National Labs on the effects of ionizing radiation on electronic
components. They used a 100KV anode voltage and exposed a variety of
components to ionizing radiation for various dwell times. Their conclusion
was that it would require 43 days of direct exposure to damage a component
(for the testing conditions and specific components selected). Contact
Nicolet Test Instruments Division and obtain a copy of their Application
Notes titled "Ionizing Radiation and Its Effects Upon Electronic
Components" for the details. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Mario Dion <[log in to unmask]>@ipc.org> on 11/19/2001 09:21:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Is X-RAY can damaged Flash IC i.e. imbeded program ?
Bonjour,
Is there any study done about the effects of X-RAYs (INCLUDING
Airports/Customs systems) on electronic assembly ??
We have had few problems with products recently where the programmed flash
was not functionnal (corrupted data) when tested at customer site (foreign
countries). The flash used is from 29F016 family. We are wandering about
the multiple X-RAY inspection the products is submitted through during
transportation.
Thanks for your help,
Mario
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Date: Wed, 21 Nov 2001 09:39:05 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Gleason <[log in to unmask]>
Subject: Re: Manual Press for PEM PCB fastener
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
FYI,
I recommend making a press block that holds the pins so that the operator
hands are out of the press area. Once this is done, a two button start is
the most economical. Call me if you'd like I can show you a digital picture
of ours.
Jim
972-494-1911
----- Original Message -----
From: "Peter Lee" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 20, 2001 11:51 PM
Subject: Re: [TN] Manual Press for PEM PCB fastener
> My application requires operator to support and locate the board
> assembly with one hand while activating the start button on the press to
> install the PEM fasteners.
>
> For safety reason I am considering limiting operator access while the
> machine is in operation.
>
> What is the normal practice? Installing a light curtain sensor around
> the area? Or multi-purpose fixtures that will secure the board to ensure
> a "hands free" operation?
>
> Any input is greatly appreciated.
>
> Rgd,
> Peter
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeff Ferry
> Sent: November 14, 2001 6:16 AM
> To: [log in to unmask]
> Subject: Re: [TN] Manual Press for PEM PCB fastener
>
> Peter,
>
> Might suggest you look over Janesville Tool at
> http://www.janesvilletool.com/.
> We use their presses for setting eyelets.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
> www.circuittechctr.com
> [log in to unmask]
> 978-374-5000
>
> Sign up for our Free E-mail Newsletter at:
> www.circuittechctr.com/general/free_email.htm
>
>
>
> -----Original Message-----
> From: Peter Lee [mailto:[log in to unmask]]
> Sent: Wednesday, November 14, 2001 2:46 AM
> To: [log in to unmask]
> Subject: [TN] Manual Press for PEM PCB fastener
>
>
> Thanks Earl for your extensive report on NPI which will keep me tied up
> for a while in reading through it. I appreciate you for sharing your
> experience and information in this forum.
>
> I have another question for the day: Does anyone know of a good and
> reliable machine for press-in PEM PCB fasteners?
>
> I am considering machines from PENN ENGINEERING and SCHMIDT but like to
> get more inputs on both the press machine and the process. Would a
> manual press be able to put out ~2200 lbs at the fastener in practice?
> What are some common application problems that one should look out for?
>
>
> Rgds,
> Peter
>
>
> _________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at http://mail.yahoo.com
>
> ------------------------------------------------------------------------
> ----
> -----
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> -----
>
> ------------------------------------------------------------------------
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> ---------
>
>
> _________________________________________________________
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>
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=========================================================================
Date: Wed, 21 Nov 2001 17:00:51 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Earl, Brad,
Thank you for the answers. Obviously, there is no a lots of experiences=
on
this area among TechNetters or the question itself wasn't interesting
enough. :)
However I just want to follow up this subject with the experiences that=
I
gained during the testing of the PCB in vacuum chamber. I hope that thi=
s is
going to help someone in the future.
I found that the best solution was to add two extra layers (top and bot=
tom)
to the PCBs that are only containing pads and annular rings for the pla=
ted
holes. Pads are connected with the layers with hidden vias. That way, I=
minimised the amount of the exposed copper/ENIG on the surface of the P=
CB.
There is no coating on the laminate at all, which minimises outgassing =
(I
wouldn't believe this if I haven't seen it myself).
I'm washing the flux residues away directly after the reflow, first wit=
h
Zestron and than with not-ionised water. After this, the PCBs are baked=
and
stored in the nitrogen atmosphere. Before mounting the PCBs in to the
vacuum the PCBs are stored in the vacuum chamber during the 8 hours per=
iod,
outgassing as much as possible. When this procedure is finnished and th=
e
PCBs are mounted in to the vacuum, make little prayer and hope for the =
best
when you push "ON" button. :)
Sasha Miladinovic
**********************************************************************
Sasha Miladinovic - Production Engineering
Amersham Biosciences, PCB Production, Ume=E5
Tel: +46 (0) 90 150 232
Fax: +46 (0) 90 138 372
E-mail: [log in to unmask]
**********************************************************************
=
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Date: Wed, 21 Nov 2001 09:41:25 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Bergman <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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IPC-6012A describes the characteristic "circuit repairs" as being acceptable in Class 1, 2,
and 3 only "As agreed by user and supplier." Generally these repairs, if done properly, are
reliable. See IPC 7721 for methods. It is your call, basically.
K. Bergman
Stephen Brown wrote:
> People.
>
> We get our PCB's assembled to IPC-610 class 2. We have recently been
> approached by our vendor regarding track repairs on our raw cards. Now I
> personally am not keen on allowing this, but is there a standard for raw
> cards similar to 610 which states an allowable quantity of track
> repairs, if any?
>
> Regards.
>
> Steve Brown.
> Commodity Specialist
> Xyratex.
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 21 Nov 2001 13:38:37 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: RF "Black Magic", why do vias need to be beneath compone nts?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_11f.79b58a3.292d4ead_boundary"
--part1_11f.79b58a3.292d4ead_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Frank!
Thank-you very much for taking the time to explain things for me, makes
things more understandable now...not easier to deal with (GRIN), but more
understandable.
-Steve Gregory-
> Steve,
> Bear with me while I try this.
> First of all there is an issue in RF design that has priority over
> just about everything, that is the "return path". As a signal is sent down a
> RF pathway (components, transmission lines, etc.) there is an equivalent
> signal traveling the return path. If the return path is of a different
> length than the signal path then there is a degradation of the signal (this
> is a bad thing). So as RF goes the closer I get ground (my return path of
> choice) the better integrity I have for my RF signal.
> Secondly, there is the issue of RF ground as a part of the RF magic
> (I think it is mostly the return path issue) having an effect on the
> electromagnetic fields surrounding the RF signal path. Any disruption in
> this field can cause integrity issues and performance failures.
> Thirdly, there is the need to develop and market product rapidly in
> todays world that tends to make the extra XXX hours needed to refine a
> circuit enough to pull vias back impossible to get.
> Lastly there is the RF factor. This is the fact that even the top RF
> guys will admit to "it's magic" sometimes.
> Even though as designers we hate to make the boards harder for you to
> assemble, we must make the circuit work. This means vias near lands, poor
> thermal relief around components (poor hell, usually none), and extremely
> tight component placements are all caused by the driving need to maintain
> the signal's integrity (so you can hear that cell call, static and all).
> Though as a designer I feel bad for what we do to guys like you, know you
> are appreciated for making us look good when the customer has a product that
> achieves spec.
> Hope it helps,
> FNK
>
> Frank N Kimmey, C.I.D.+
> Senior PCB Designer
> Powerwave Technologies
> PH. 916-941-3159
> Fax 916-941-3195
>
--part1_11f.79b58a3.292d4ead_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Frank!
<BR>
<BR>Thank-you very much for taking the time to explain things for me, makes things more understandable now...not easier to deal with (GRIN), but more understandable.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve,
<BR>Bear with me while I try this.
<BR> First of all there is an issue in RF design that has priority over
<BR>just about everything, that is the "return path". As a signal is sent down a
<BR>RF pathway (components, transmission lines, etc.) there is an equivalent
<BR>signal traveling the return path. If the return path is of a different
<BR>length than the signal path then there is a degradation of the signal (this
<BR>is a bad thing). So as RF goes the closer I get ground (my return path of
<BR>choice) the better integrity I have for my RF signal.
<BR> Secondly, there is the issue of RF ground as a part of the RF magic
<BR>(I think it is mostly the return path issue) having an effect on the
<BR>electromagnetic fields surrounding the RF signal path. Any disruption in
<BR>this field can cause integrity issues and performance failures.
<BR> Thirdly, there is the need to develop and market product rapidly in
<BR>todays world that tends to make the extra XXX hours needed to refine a
<BR>circuit enough to pull vias back impossible to get.
<BR> Lastly there is the RF factor. This is the fact that even the top RF
<BR>guys will admit to "it's magic" sometimes.
<BR>Even though as designers we hate to make the boards harder for you to
<BR>assemble, we must make the circuit work. This means vias near lands, poor
<BR>thermal relief around components (poor hell, usually none), and extremely
<BR>tight component placements are all caused by the driving need to maintain
<BR>the signal's integrity (so you can hear that cell call, static and all).
<BR>Though as a designer I feel bad for what we do to guys like you, know you
<BR>are appreciated for making us look good when the customer has a product that
<BR>achieves spec.
<BR>Hope it helps,
<BR>FNK
<BR>
<BR>Frank N Kimmey, C.I.D.+
<BR>Senior PCB Designer
<BR>Powerwave Technologies
<BR>PH. 916-941-3159
<BR>Fax 916-941-3195
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_11f.79b58a3.292d4ead_boundary--
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=========================================================================
Date: Wed, 21 Nov 2001 15:24:30 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: nitrogen purity
X-To: Sedat Cbayar <[log in to unmask]>
After a brief 3.5 day trip from BF Montana to Eastern Michigan, I'm back.
Big whoop! How 'bout those Chicago commuters! Never again as long as I live
will I take the 80 anywhere near that city. Trains only, thank you.
You measure the amount of oxygen (%), not the nitrogen purity or amount -
can't be done. The oxygen content should be as specified for the type
soldering you are attempting. Usually, below 20% oxygen content is acceptable.
MoonMan
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Date: Wed, 21 Nov 2001 15:32:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: CCGA's, the good, the bad, and the ugly...
X-To: "David H. Fish" <[log in to unmask]>
All that's been said about CCGA's, by all saying it, is true. Not much
bigger deal than BGA's but bigger and much heavier parts. Best solder joints
possible with those "flexible" columns and solder fillets at joint level.
Machine vision offers biggest challenge, as someone said. Rework must be
considered as well. That's the most fun but very doable.
Done hundreds of these using cast, not clasp, columns from IBM. With columns
about .070" long, inspection not too tough. Whoever noted it very important
to ensure columns straight said it right. When bent, I used an engineering
scale to "comb" the little muthas straight again. Pretty forgiving those
columns when a little bent but not so when abused.
MoonMan
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Date: Wed, 21 Nov 2001 15:41:02 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Over-etch
X-To: [log in to unmask]
Not a paid endorsement for Glynn. However, I must say among many others, he
runs the best little board house in the country. He does a lot of things for
free, as well, that saves you lot's of money. He's a real board guy.
Earl Moon
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Date: Wed, 21 Nov 2001 16:49:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Peter
I think we now know why you've had warpage problems on the other boards.
Building up unequally thick sequentially laminated parts then laminating
them together is likely the underlying asymmetry that's warping the boards.
Even if in the final stackup appears symmetric the fact that the "building
blocks" were unbalanced is enough to warp the final boards.
By the way, I think 7 weeks seems about right for building something like
this the first time. If at all possible, I'd try to simplify the structure
to reduce the sequential lamination sequences. Laser microvias and
controlled depth drills can be helpful in doing this.
I saw from your other posting that your fabricator is going to try to grind
down the accumulated plating thickness. I don't want to dash your hopes but
there is a fair amount of risk in doing so. One of the challenges in
building a multi-level board like this is understanding how the different
layers move through each level of the build. That's part of what takes 7
weeks. You have to build the board almost all the way through the process
to monitor and correct for the shifts that occur. On something this complex
even the second pass might not be correct. Except for the line width issues
your fabricator has presumably gone through this process and learned all of
this. But now they are going to grind off the plating. Unfortunately,
grinding also stretches the panel, which means the data they collected on
the previous builds likely won't be applicable. It's not unheard of to have
1 mm or more of growth on a panel. I'm guessing your IL pads and clearances
weren't designed to accommodate such misregistration. They'll likely have
to re-characterize the movement of the board and re-size the IL accordingly.
Good luck, but don't be surprised if the first re-build has some
registration issues.
> ----------
> From: <Peter George Duncan>[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Sunday, November 18, 2001 10:24 PM
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Edward,
>
> The heavy copper weight resulting from all these plating processes was
> recognised early on, but a) we assumed it would be reasonably even across
> the board surface, and b) was not so heavy that the required widths and
> spacings couldn't achieved after final etch. Certainly it wasn't flagged
> up
> to us by the fab house as being a problem.
>
> A very similar board was made by another fab house with no problem, apart
> from the boards being warped. The etching was fine - it's just that they
> took 7 weeks to make them on priority, which we couldn't afford again.
>
> Hmmm! The things we have to find out the hard way.
>
> Peter Duncan
>
>
>
>
>
> Edward
>
> Szpruch To: [log in to unmask]
>
> <edward@ELTEK cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> .CO.IL> Aero/ST Group)
>
> Sent by: Subject: Re: [TN] Over-etch
>
> TechNet
>
> <[log in to unmask]
>
> ORG>
>
>
>
>
>
> 11/18/01
>
> 03:08 PM
>
> Please
>
> respond to
>
> "TechNet
>
> E-Mail
>
> Forum."
>
>
>
>
>
>
>
>
>
> Peter,
> Let me refrase your question from plating point of view since you rised 1
> milion dollar question:
> How to plate the holes without plating the surface.
> As far as I know,the best equipment,the best technologies,the best
> chemistry
> etc have limitited capacity in terms of throwing capability ( ratio of
> metal
> plated inside the hole to metal plated on the surface).The best figure is
> slighty above 1.0 , usually is less than 1.0 .
> No magic in this area:if the design requires to plate 3 times at least 20
> microns or so in the holes, the surface will get additional around 60 -70
> microns of copper before plating and etching of the final pattern.
> PCB designer should know this basic fact of life while imposing fancy
> construction.
> Of course PCB manufacturer has some possibilities to manipulate artwork
> compensations according to copper thickness to be etched, but etching
> factors are also fact of life.
> There are some tricky ways,but most of them are not working well on HDI
> boards with fine lines.
> Edward
>
> Edward Szpruch
> Eltek Ltd
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>
> > -----Original Message-----
> > From: <Peter George Duncan> [SMTP:[log in to unmask]]
> > Sent: å ðåáîáø 16 2001 10:04
> > To: [log in to unmask]
> > Subject: Re: [TN] Over-etch
> >
> > Hi, Rudy,
> >
> > The boards are ENIG finished, the ENIG plating being carried out
> > post-solder-mask, which must be after final copper etch, so No, there is
> > no
> > other metal in the area, unless my understanding of the plating/etching
> > sequence is all wrong. My understanding (faulty or otherwise) of what
> the
> > fab house has done, is that they laminate, drill and plate the layers
> with
> > the first suite of blind vias, then laminate, drill and plate for the
> > second suite of blind vias, then again for the 3rd suite until
> everything
> > is stacked up, pressed, drilled and plated for the through-holes. I
> > haven't
> > quite been able to make sense of it all yet, but I think what I'm being
> > told is that the plating becomes "stepped" somehow. I have 3 sets of
> blind
> > vias from each outer surface (for ease of argument), making 4 plating
> > sessions on each side by the time the through-hole group is done. The
> > first
> > areas to be drilled and plated are therefore plated 4 times, while the
> > last
> > areas to be drilled are only plated once, with the groups in between
> > getting their proportional share of multiple plating.
> >
> > Thus at final etch, there is, I am told, a compromise to be reached -
> how
> > to achieve the correct widths and spacings on the heavily plated areas
> > without over-etching the lightly-plated areas. In my simple way, I would
> > have expected the entire board surface to have an even plating
> thickness,
> > however thick, but seemingly not. The compromise hasn't worked for the
> > number of blind via groups featured in this board, and I need to try to
> > find out how to address a solution without solely relying on what our
> fab
> > house tells me.
> >
> > In my entire life, I never had to worry about the processes involved in
> > fabricating PCB's - only that components could be soldered to them, that
> > they passed test and proved to be reliable in the field. I only ever
> > worked
> > with good boards - the ones that passed in-coming inspection - in an
> > assembly environment, so my experience of board design and PCB fab is
> > limited to the past 8 or 9 months, in a company that has no previous
> > convictions for designing this type of board, so it's a case of the
> blind
> > leading the blind to a certain extent.
> >
> > Any further help in this area would be greatly appreciated.
> >
> > Best regards
> >
> > Peter Duncan
> >
> >
> >
> >
> > "<Rudy
> > Sedlak>" To: [log in to unmask]
> > Sent by: cc: (bcc: DUNCAN Peter/Asst
> > Prin Engr/ST
> > TechNet Aero/ST Group)
> > <[log in to unmask] Subject: Re: [TN] Over-etch
> > ORG>
> >
> >
> > 11/16/01
> > 02:13 PM
> > Please
> > respond to
> > "TechNet
> > E-Mail
> > Forum."
> >
> >
> >
> >
> >
> >
> > Peter:
> >
> > I am not sure if I fully understand the process you are using....so I am
> > going to ask a dumb question, that may shed some light on the issue...
> >
> > Is there, anywhere in electrical contact with Copper being etched any
> > other
> > metal excepting Tin?
> >
> > This sort of thing, selective over-etch, is classically seen when there
> is
> > some other metal, (Nickel, Gold, or???) than Tin in electrical contact
> > with
> > the over-etched Copper, and also in contact with the etchant.
> >
> > And if I am completely out in space with this question, please forgive
> the
> > intrusion.
> >
> > Rudy Sedlak
> >
> >
> --------------------------------------------------------------------------
> > -------
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> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
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> >
> >
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> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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=========================================================================
Date: Thu, 22 Nov 2001 07:54:31 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: Raw Card Track Repairs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I think this one depends on which side of the fence you are on.
I personally would prefer not to have any track repairs. If you do decide
to allow repairs then I would get a copy of IPC7721 and decide which of the
many methods in the standard you want your supplier to use. I would also
insist that any repaired boards are segregated from normal production with a
list of the locations of the repairs.
If you make the procedure complex enough your supplier may just decide it's
not worth the bother and scrap them / improve his yield!!
Neil
-----Original Message-----
From: Kathy Bergman [mailto:[log in to unmask]]
Sent: 21 November 2001 17:41
Subject: Re: Raw Card Track Repairs
IPC-6012A describes the characteristic "circuit repairs" as being acceptable
in Class 1, 2,
and 3 only "As agreed by user and supplier." Generally these repairs, if
done properly, are
reliable. See IPC 7721 for methods. It is your call, basically.
K. Bergman
Stephen Brown wrote:
> People.
>
> We get our PCB's assembled to IPC-610 class 2. We have recently been
> approached by our vendor regarding track repairs on our raw cards. Now I
> personally am not keen on allowing this, but is there a standard for raw
> cards similar to 610 which states an allowable quantity of track
> repairs, if any?
>
> Regards.
>
> Steve Brown.
> Commodity Specialist
> Xyratex.
>
>
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Date: Thu, 22 Nov 2001 17:07:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Hi, Michael,
Thanks very much indeed for your input, even though it looks as though
you're confirming my worst fears. I made a phone call to the States
specifically on the grinding issue on Tuesday morning, as I was concern=
ed,
not about stretch, as I didn't know to consider that, but about the ris=
k of
over-doing it and removing pads or making them too thin.
I honestly believe that the design itself is balanced in terms of coppe=
r
distribution, as I calculated the copper volume for each layer and comp=
ared
each to its opposite number in the stack-up. But I see and understand t=
hat
the increasing weight on the outer layers with the number of sequential=
plating processes could warp those layers already laminated. I was cros=
sing
my fingers and hoping that the opposing bows of the two halves of the b=
oard
would cancel each other out and relieve the stresses in the final press=
ing
that joins them together. Is that being naive?
I'll warn our fab house about the stretch and registration issues, and =
note
their response. That is a real concern, though having said that, all th=
e
boards on this project have a grinding operation to level silver epoxy =
in
the thermal vias with the surface of the board, and those boards have b=
een
very successful, albeit all the holes are through-holes (no blinds apar=
t
from these two boards).
The fab house's current attempt is their third - the second one took th=
em
(via a subcontractor) into laser drilling for the first time, and it wa=
s a
disaster. Every board failed electrical test big time with missing
connectivity, and drilling too deep and contacting other layers. Put me=
off
laser drilling rather, though I understand from fab houses with more
experience of this that after some practice it is a very reliable proce=
ss,
as are the subsequent plating operations.
The bottom line is that we didn't know enough about the pitfalls with t=
his
type of design to take steps to counteract them. We learn the hard way,=
but
still have to get the darned things made somehow!
My profound thanks again for taking the trouble to write.
Best regards
Peter
ST Aerospace
=
=20
"Mcmaster, =
=20
Michael" To: [log in to unmask] =
=20
<michaelm@MER cc: (bcc: DUNCAN Peter/Ass=
t Prin Engr/ST =20
IX.COM> Aero/ST Group) =
=20
Sent by: Subject: Re: [TN] Over-etc=
h =20
TechNet =
=20
<[log in to unmask] =
=20
ORG> =
=20
=
=20
=
=20
11/22/01 =
=20
08:49 AM =
=20
Please =
=20
respond to =
=20
"TechNet =
=20
E-Mail =
=20
Forum." =
=20
=
=20
=
=20
Peter
I think we now know why you've had warpage problems on the other boards=
.
Building up unequally thick sequentially laminated parts then laminatin=
g
them together is likely the underlying asymmetry that's warping the boa=
rds.
Even if in the final stackup appears symmetric the fact that the "build=
ing
blocks" were unbalanced is enough to warp the final boards.
By the way, I think 7 weeks seems about right for building something li=
ke
this the first time. If at all possible, I'd try to simplify the struc=
ture
to reduce the sequential lamination sequences. Laser microvias and
controlled depth drills can be helpful in doing this.
I saw from your other posting that your fabricator is going to try to g=
rind
down the accumulated plating thickness. I don't want to dash your hope=
s
but
there is a fair amount of risk in doing so. One of the challenges in
building a multi-level board like this is understanding how the differe=
nt
layers move through each level of the build. That's part of what takes=
7
weeks. You have to build the board almost all the way through the proc=
ess
to monitor and correct for the shifts that occur. On something this
complex
even the second pass might not be correct. Except for the line width
issues
your fabricator has presumably gone through this process and learned al=
l of
this. But now they are going to grind off the plating. Unfortunately,=
grinding also stretches the panel, which means the data they collected =
on
the previous builds likely won't be applicable. It's not unheard of to=
have
1 mm or more of growth on a panel. I'm guessing your IL pads and
clearances
weren't designed to accommodate such misregistration. They'll likely h=
ave
to re-characterize the movement of the board and re-size the IL
accordingly.
Good luck, but don't be surprised if the first re-build has some
registration issues.
> ----------
> From: <Peter George Duncan>[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Sunday, November 18, 2001 10:24 PM
> To: [log in to unmask]
> Subject: Re: [TN] Over-etch
>
> Hi, Edward,
>
> The heavy copper weight resulting from all these plating processes wa=
s
> recognised early on, but a) we assumed it would be reasonably even ac=
ross
> the board surface, and b) was not so heavy that the required widths a=
nd
> spacings couldn't achieved after final etch. Certainly it wasn't flag=
ged
> up
> to us by the fab house as being a problem.
>
> A very similar board was made by another fab house with no problem, a=
part
> from the boards being warped. The etching was fine - it's just that t=
hey
> took 7 weeks to make them on priority, which we couldn't afford again=
.
>
> Hmmm! The things we have to find out the hard way.
>
> Peter Duncan
>
>
>
>
>
> Edward
>
> Szpruch To: [log in to unmask]
>
> <edward@ELTEK cc: (bcc: DUNCAN Peter/A=
sst
> Prin Engr/ST
> .CO.IL> Aero/ST Group)
>
> Sent by: Subject: Re: [TN] Over-e=
tch
>
> TechNet
>
> <[log in to unmask]
>
> ORG>
>
>
>
>
>
> 11/18/01
>
> 03:08 PM
>
> Please
>
> respond to
>
> "TechNet
>
> E-Mail
>
> Forum."
>
>
>
>
>
>
>
>
>
> Peter,
> Let me refrase your question from plating point of view since you ris=
ed 1
> milion dollar question:
> How to plate the holes without plating the surface.
> As far as I know,the best equipment,the best technologies,the best
> chemistry
> etc have limitited capacity in terms of throwing capability ( ratio o=
f
> metal
> plated inside the hole to metal plated on the surface).The best figur=
e is
> slighty above 1.0 , usually is less than 1.0 .
> No magic in this area:if the design requires to plate 3 times at leas=
t 20
> microns or so in the holes, the surface will get additional around 60=
-70
> microns of copper before plating and etching of the final pattern.
> PCB designer should know this basic fact of life while imposing fancy=
> construction.
> Of course PCB manufacturer has some possibilities to manipulate artwo=
rk
> compensations according to copper thickness to be etched, but etching=
> factors are also fact of life.
> There are some tricky ways,but most of them are not working well on H=
DI
> boards with fine lines.
> Edward
>
> Edward Szpruch
> Eltek Ltd
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>
> > -----Original Message-----
> > From: <Peter George Duncan> [SMTP:[log in to unmask]]
> > Sent: =E5 =F0=E5=E1=EE=E1=F8 16 2001 10:04
> > To: [log in to unmask]
> > Subject: Re: [TN] Over-etch
> >
> > Hi, Rudy,
> >
> > The boards are ENIG finished, the ENIG plating being carried out
> > post-solder-mask, which must be after final copper etch, so No, the=
re
is
> > no
> > other metal in the area, unless my understanding of the plating/etc=
hing
> > sequence is all wrong. My understanding (faulty or otherwise) of wh=
at
> the
> > fab house has done, is that they laminate, drill and plate the laye=
rs
> with
> > the first suite of blind vias, then laminate, drill and plate for =
the
> > second suite of blind vias, then again for the 3rd suite until
> everything
> > is stacked up, pressed, drilled and plated for the through-holes. I=
> > haven't
> > quite been able to make sense of it all yet, but I think what I'm b=
eing
> > told is that the plating becomes "stepped" somehow. I have 3 sets o=
f
> blind
> > vias from each outer surface (for ease of argument), making 4 plati=
ng
> > sessions on each side by the time the through-hole group is done. T=
he
> > first
> > areas to be drilled and plated are therefore plated 4 times, while =
the
> > last
> > areas to be drilled are only plated once, with the groups in betwee=
n
> > getting their proportional share of multiple plating.
> >
> > Thus at final etch, there is, I am told, a compromise to be reached=
-
> how
> > to achieve the correct widths and spacings on the heavily plated ar=
eas
> > without over-etching the lightly-plated areas. In my simple way, I
would
> > have expected the entire board surface to have an even plating
> thickness,
> > however thick, but seemingly not. The compromise hasn't worked for =
the
> > number of blind via groups featured in this board, and I need to tr=
y to
> > find out how to address a solution without solely relying on what o=
ur
> fab
> > house tells me.
> >
> > In my entire life, I never had to worry about the processes involve=
d in
> > fabricating PCB's - only that components could be soldered to them,=
that
> > they passed test and proved to be reliable in the field. I only eve=
r
> > worked
> > with good boards - the ones that passed in-coming inspection - in a=
n
> > assembly environment, so my experience of board design and PCB fab =
is
> > limited to the past 8 or 9 months, in a company that has no previou=
s
> > convictions for designing this type of board, so it's a case of the=
> blind
> > leading the blind to a certain extent.
> >
> > Any further help in this area would be greatly appreciated.
> >
> > Best regards
> >
> > Peter Duncan
> >
> >
> >
> >
> > "<Rudy
> > Sedlak>" To: [log in to unmask]
> > Sent by: cc: (bcc: DUNCAN
Peter/Asst
> > Prin Engr/ST
> > TechNet Aero/ST Group)
> > <[log in to unmask] Subject: Re: [TN]
Over-etch
> > ORG>
> >
> >
> > 11/16/01
> > 02:13 PM
> > Please
> > respond to
> > "TechNet
> > E-Mail
> > Forum."
> >
> >
> >
> >
> >
> >
> > Peter:
> >
> > I am not sure if I fully understand the process you are using....so=
I
am
> > going to ask a dumb question, that may shed some light on the issue=
...
> >
> > Is there, anywhere in electrical contact with Copper being etched a=
ny
> > other
> > metal excepting Tin?
> >
> > This sort of thing, selective over-etch, is classically seen when t=
here
> is
> > some other metal, (Nickel, Gold, or???) than Tin in electrical cont=
act
> > with
> > the over-etched Copper, and also in contact with the etchant.
> >
> > And if I am completely out in space with this question, please forg=
ive
> the
> > intrusion.
> >
> > Rudy Sedlak
> >
> >
>
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Date: Thu, 22 Nov 2001 08:49:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ian Hanna <[log in to unmask]>
Subject: Re: Over-etch
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
just a quick note on lasing...i found it, once dialed in, to be a very good
process. the biggest deal besides ablating the holes is plating
them...sounds like an old song now. it took me less than a week to work up
a very wide process window for 1080 fr-4 with an nd/yag UV laser.
everything looked great on the microsections but we found we had about .5%
fall out due to plating voids in the finished boards...a difficult number to
really work with, too slim for easy failure analysis yet one or two opens
per board didn't work...used really low amps and a couple of 'cheats' at
electroless (metalization) to get the job out...and ended up going to
complex waveform reverse pulse plating...which made things more or less a
cake-walk...bottom line is that if i was to bring laser drilling in house
again i'd sub-contract the drilling (that is hold off on the rather
substantial capitol investment in a laser via machine) until i had the rest
of my processes dialed in...registration on n-1 layers...coordinating the
registration between the mechanical hole grid and the micro-via
placement...and of course reliable process....one of the more 'holistic'
processes i've worked with...everything needs to work together, you can't
just ship out panels for drilling and process them the same old way...
might as well throw in my $.02 worth on your grinding idea....i'm a little
concerned about the integrity of the 'knees' of the plated barrels...it's
always nice to see an even coating of rich, thick, well leveled copper going
from the surface all the way into the barrel of the hole...interrupting
this, then re-plating over top -might- not give you as solid a 'knee' and
with board expansion from z-axis CTE mismatches so common in fr-4
construction, you might see a higher than normal drop out well after the
fabrication fact...i'd do some fairly aggressive solder floats, at least 5x
10 seconds in a pot of 550 degrees and look for any signs of failure...to
ensure that there are no long-term reliability issuesthat being said,
i've plated, filled and ground lots of blind vias without too many
reliability issues in avionics applications...so it's do-able...just so
you're aware of potential pit-falls really...
good luck...sounds like an exciting project
ian
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Date: Thu, 22 Nov 2001 12:12:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: another one bites the dust
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Dear Technetters,
I'm sorry to report that my current employer has closed down. Mosaic Printed
Circuits (formerly Quality Printed Circuits) shut down November 16, 2001.
I am still on techet and will contribute as I can while searching for new
employment. Hopefully, this will be a temporary condition.
Chemically yours,
Russell Burdick
Process Engineer
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
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Date: Thu, 22 Nov 2001 15:56:26 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Crain <[log in to unmask]>
Subject: best finish for through hole boards
Good day tech-net
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Date: Thu, 22 Nov 2001 16:14:22 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Crain <[log in to unmask]>
Subject: best finish for through hole boards
I am not sure why an empty message just got posted. Anyway, here is my
question: We are looking to standardize our board finish for all of our
through-hole boards. We have many types of finishes (mat or flat,gloss,
semi-gloss, dark green, light green)and are looking to change to the mat
finish to cover, um hide, the little bit of flux residue that we find
exceptable. We use a no-clean flux.
Is there any difference in solderability when using different finishes. Do
the profiles change between board finishes? Does the type of finish affect
defect rate? What are other's using and finding best results?
Thanks
---------------------------------------------------------------------------------
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Date: Fri, 23 Nov 2001 12:15:34 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Over-etch
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Ian,
I've attracted a remarkable amount of correspondence on this subject, and
have been very impressed with the help and information received. Laser
drilling is brand new to me, and with everyone's help, I feel I'm building
up a pretty comprehensive overview of this technology, which is very
interesting learning. It's a tricky process, it seems in inexperienced
hands, but for people who know it, they say it's every bit as reliable as
more conventional methods and much cheaper. Hopefully we won't have too
many projects that require it, unless we do find a fab house at the right
price who can successfully handle all the processes.
On the grinding thang, your concern was exactly mine when it was first
proposed by the fab house - by grinding off the plated copper, I'ld be left
with plated copper joined to the inside thickness of the original pad. I've
seen enough microsections in my time to know that there is a "weakness" at
the interface of these two metalisations. Although there is a final plating
session that will cover a lot of this, still it is a concern.
Thanks again to you and all the others who have responded on this issue. I
hope it's helped more people than just me.
Best regards
Peter Duncan
Ian Hanna
<ianh@LAZER-T To: [log in to unmask]
ECH.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Over-etch
<[log in to unmask]
ORG>
11/22/01
09:49 PM
Please
respond to
"TechNet
E-Mail
Forum."
just a quick note on lasing...i found it, once dialed in, to be a very good
process. the biggest deal besides ablating the holes is plating
them...sounds like an old song now. it took me less than a week to work up
a very wide process window for 1080 fr-4 with an nd/yag UV laser.
everything looked great on the microsections but we found we had about .5%
fall out due to plating voids in the finished boards...a difficult number
to
really work with, too slim for easy failure analysis yet one or two opens
per board didn't work...used really low amps and a couple of 'cheats' at
electroless (metalization) to get the job out...and ended up going to
complex waveform reverse pulse plating...which made things more or less a
cake-walk...bottom line is that if i was to bring laser drilling in house
again i'd sub-contract the drilling (that is hold off on the rather
substantial capitol investment in a laser via machine) until i had the rest
of my processes dialed in...registration on n-1 layers...coordinating the
registration between the mechanical hole grid and the micro-via
placement...and of course reliable process....one of the more 'holistic'
processes i've worked with...everything needs to work together, you can't
just ship out panels for drilling and process them the same old way...
might as well throw in my $.02 worth on your grinding idea....i'm a little
concerned about the integrity of the 'knees' of the plated barrels...it's
always nice to see an even coating of rich, thick, well leveled copper
going
from the surface all the way into the barrel of the hole...interrupting
this, then re-plating over top -might- not give you as solid a 'knee' and
with board expansion from z-axis CTE mismatches so common in fr-4
construction, you might see a higher than normal drop out well after the
fabrication fact...i'd do some fairly aggressive solder floats, at least 5x
10 seconds in a pot of 550 degrees and look for any signs of failure...to
ensure that there are no long-term reliability issuesthat being said,
i've plated, filled and ground lots of blind vias without too many
reliability issues in avionics applications...so it's do-able...just so
you're aware of potential pit-falls really...
good luck...sounds like an exciting project
ian
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Date: Fri, 23 Nov 2001 09:07:54 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Storage of moisture sensitive components
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)"
This is a multi-part message in MIME format.
--Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)
Content-type: text/plain; charset=windows-1255
Content-transfer-encoding: 7BIT
How long and in what conditions may moisture sensitive components be stored in their original package?
Thank.you,
Gaby
--Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)
Content-type: text/html; charset=windows-1255
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=windows-1255">
<META content="MSHTML 5.50.4207.2601" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>How long and in what conditions may moisture
sensitive components be stored in their original
package?<BR>Thank.you,<BR>Gaby</FONT></DIV></BODY></HTML>
--Boundary_(ID_i4efUeZRkbTpvI6C9gkZhQ)--
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Date: Fri, 23 Nov 2001 10:05:11 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"
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Gaby,
=20
that should be written on the label of the original package ( if it=B4s
according to J-STD-033 ). In most cases dependend on the material used =
it
reads 12 month from packing date (bag seal date) which also should be =
on
that label.
You may get yourself a copy of J-STD-033 which can be downloaded ( for =
free
:-) ) from JEDEC or IPC, don=B4t remember which one it was.
In case of doubt get and follow the manufacturers recommendations.
=20
Wolfgang
=20
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Friday, November 23, 2001 8:08 AM
To: [log in to unmask]
Subject: [TN] Storage of moisture sensitive components
How long and in what conditions may moisture sensitive components be =
stored
in their original package?
Thank.you,
Gaby
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Date: Fri, 23 Nov 2001 11:14:12 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
MIME-version: 1.0
Content-type: text/plain; charset=windows-1255
Content-transfer-encoding: 8BIT
Thanks!
Gaby
----- Original Message -----
From: "Busko, Wolfgang" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, November 23, 2001 11:05 AM
Subject: Re: [TN] Storage of moisture sensitive components
> Gaby,
>
> that should be written on the label of the original package ( if it´s
> according to J-STD-033 ). In most cases dependend on the material used it
> reads 12 month from packing date (bag seal date) which also should be on
> that label.
> You may get yourself a copy of J-STD-033 which can be downloaded ( for
free
> :-) ) from JEDEC or IPC, don´t remember which one it was.
> In case of doubt get and follow the manufacturers recommendations.
>
> Wolfgang
>
>
> -----Original Message-----
> From: Gaby Bogdan [mailto:[log in to unmask]]
> Sent: Friday, November 23, 2001 8:08 AM
> To: [log in to unmask]
> Subject: [TN] Storage of moisture sensitive components
>
>
> How long and in what conditions may moisture sensitive components be
stored
> in their original package?
> Thank.you,
> Gaby
>
> --------------------------------------------------------------------------
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>
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Date: Fri, 23 Nov 2001 12:30:48 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: best finish for through hole boards
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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I think that this is a chicken and egg question and needs to be considered
from a PCB fab viewpoint as well. It is expensive for a pcb fab house to
have more than one soldermask, because they have to pay for UL approval,
because they cannot 'leverage' their supply as well (lower volume), because
they either have to have seperate equipment or incur set up costs every
time they change ink, and because they have to change their exposure,
developing and cure cycle settings for different inks. The metal finish
required by the customer - HASL, ENIG, Immersion silver, immersion tin,
entek - also has an effect on the ink that can be used - many inks do not
withstand the chemical attack from these finishes, so I would suggest you
go back to your PCB supplier(s) and ask the question how will this affect
their supply to you (and ask the Operations or Technical Director, not the
sales guy who will say no problem - I speak from experience) and by how it
may affect their supply, I include lead time, UL certification, metal
finish options, SIR and SECC conformity. It may just be green paint to you,
but it has a major impact on the fab process.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Peter Crain [SMTP:[log in to unmask]]
Sent: 22 November 2001 22:14
To: [log in to unmask]
Subject: [TN] best finish for through hole boards
I am not sure why an empty message just got posted. Anyway, here is my
question: We are looking to standardize our board finish for all of our
through-hole boards. We have many types of finishes (mat or flat,gloss,
semi-gloss, dark green, light green)and are looking to change to the mat
finish to cover, um hide, the little bit of flux residue that we find
exceptable. We use a no-clean flux.
Is there any difference in solderability when using different finishes. Do
the profiles change between board finishes? Does the type of finish affect
defect rate? What are other's using and finding best results?
Thanks
------------------------------------------------------------------------
---------
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Date: Sat, 24 Nov 2001 07:36:52 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
MIME-Version: 1.0
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Sasha,
Congrats on being the new senior fellow regarding PCB for vacuum (not to be
confused with designing in a vacuum). If you have a need for non outgassing
soldermask in future let me know, my fab house in Denver uses it on a regular
basis. Glad to hear it was a happy ending.
Coretec Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Sasha,
<BR>
<BR>Congrats on being the new senior fellow regarding PCB for vacuum (not to be confused with designing in a vacuum). If you have a need for non outgassing soldermask in future let me know, my fab house in Denver uses it on a regular basis. Glad to hear it was a happy ending.
<BR>
<BR>Coretec Brad</FONT></HTML>
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Date: Sat, 24 Nov 2001 13:27:05 -0800
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Dorothy Lush
Solectron
408 957 2736
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Date: Sun, 25 Nov 2001 00:57:42 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
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Sasha,
I don't have experience with PCB's in a vacuum system, but I do have some
experience with lots of other materials in high vacuum as I used to work
designing electronics for mass spectrometers. I'm an EE, not a materials
person, but a few insights rubbed off on me while I worked with them. The
high vacuum part of our system was around 10exp(-9) torr, so I don't know if
this is the same range that you are concerned with.
However, in this range of vacuum, the main problem was any surface
irregularities that could contain bits of material that slowly but steadily
vaporize at this low pressure level. If you inserted a "dirty" piece into
the vacuum system, you could wait days for the pressure to approach the
final value. If the part was dirty enough, you could wait a week or more
and perhaps never get there. We called this phenomenon a virtual leak.
That is, when a part has enough material with low volatility in it, the
steady outgassing acts similarly to a small leak in the chamber. Heating
the vacuum chamber and the parts inside it speeds up this process quite a
bit. Since the parts in our system were made of stainless steel, ceramics
and glasses, we could heat the system to 350 degrees C. for several days to
get everything clean and the pressures stable. Since the instrument was a
mass spectrometer, we had the luxury of being able to monitor the
composition of the outgassed material and it was usually water! Even at 350
degrees C. and high vacuum, it could take days for most of the water to come
off. Obviously, you can't do this with a PCB but heating helps get the
outgassing over with sooner.
The bottom line is that any rough or porous materials are bad news in a high
vacuum system, as it makes it very difficult to get them truly clean. That
is why I'm not surprised that boards with solder mask performed worse than
boards with no mask. We look at solder mask and think of it as a smooth
"sealing" layer, but on a micro scale, I bet it looks like a piece of
Muenster cheese. The board itself will entrap material in its surface, then
you cover it up with another porous layer that entraps more material and the
composite will outgas for a long time. Also, any uncured mask would
probably outgas badly for a long period.
If I were to guess how to improve things, I might try using the thinnest
laminate possible so entrapped material had the best chance to get out.
Beyond that, I'm on pretty thin ice. I would guess you want a resin
material that has the fewest voids and the lowest gas diffusion rate, but I
could be way off on this. Also, I don't know the properties of the copper
foils and the electrodeposited copper used in PCB fabrication with respect
to outgassing. Any materials scientists out there care to pick this up?
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Sasha Miladinovic
> Sent: Wednesday, November 21, 2001 10:01 AM
> To: [log in to unmask]
> Subject: Re: [TN] HELP <=> PCB vs. High Vacuum <=> HELP
>
>
> Earl, Brad,
>
> Thank you for the answers. Obviously, there is no a lots of experiences on
> this area among TechNetters or the question itself wasn't interesting
> enough. :)
> However I just want to follow up this subject with the experiences that I
> gained during the testing of the PCB in vacuum chamber. I hope
> that this is
> going to help someone in the future.
> I found that the best solution was to add two extra layers (top
> and bottom)
> to the PCBs that are only containing pads and annular rings for the plated
> holes. Pads are connected with the layers with hidden vias. That way, I
> minimised the amount of the exposed copper/ENIG on the surface of the PCB.
> There is no coating on the laminate at all, which minimises outgassing (I
> wouldn't believe this if I haven't seen it myself).
> I'm washing the flux residues away directly after the reflow, first with
> Zestron and than with not-ionised water. After this, the PCBs are
> baked and
> stored in the nitrogen atmosphere. Before mounting the PCBs in to the
> vacuum the PCBs are stored in the vacuum chamber during the 8
> hours period,
> outgassing as much as possible. When this procedure is finnished and the
> PCBs are mounted in to the vacuum, make little prayer and hope
> for the best
> when you push "ON" button. :)
>
> Sasha Miladinovic
>
>
> **********************************************************************
> Sasha Miladinovic - Production Engineering
> Amersham Biosciences, PCB Production, Umeå
> Tel: +46 (0) 90 150 232
> Fax: +46 (0) 90 138 372
> E-mail: [log in to unmask]
> **********************************************************************
>
> ------------------------------------------------------------------
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Date: Mon, 26 Nov 2001 16:00:47 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: Re: HELP <=> PCB vs. High Vacuum <=> HELP
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Thanks on the promotion. :)
Sasha
***********************************************************************=
**
Sasha Miladinovic - Production Engineering
Amersham Biosciences, PCB Production, Ume=E5
Tel: +46 (0) 90 150 232
Fax: +46 (0) 90 138 372
E-mail: [log in to unmask]
***********************************************************************=
**
=
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Date: Mon, 26 Nov 2001 10:07:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: BGA long term storage?
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Good day Technet! Hope my friends to the south had a good Thanksgiving =
holiday!
A question today concerning shelf life and storage. We build equipment =
that is expected to be supported for a fairly long time - say a decade or =
more. We are also as an industry moving to using COTS (commercial) =
components to reduce cost. Fine and good, but the life cycle for =
commercial parts is often pretty short compared with a military spec'd =
component - which puts us into a life time buy situation earlier rather =
than later.
My question:
Is there a good method to use to store BGA type components for long term =
storage? E.G. I build board X using a particular BGA part. It goes "end =
of life" a couple of years later, but I'm expected to support repair and =
overhaul for another few years yet, so I buy as many as I predict I'll =
need. As the time goes on, the solder balls oxidize. How should I store =
the spare parts? In nitrogen? Cold environment? Will it even be a =
problem?
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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Date: Mon, 26 Nov 2001 16:31:35 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: BGA long term storage?
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Hi Graham,
Long term storage is more a problem for QFP's and other leaded parts, =
where intermetallics can make the parts unsolderable.
The oxidation that you will have on the BGA's balls is what you're using =
flux for. I don't think you will have any soldering problem at all, as =
long as you bake before soldering.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
=20
>>> Graham Collins <[log in to unmask]> 11/26 4:07 pm >>>
Good day Technet! Hope my friends to the south had a good Thanksgiving =
holiday!
A question today concerning shelf life and storage. We build equipment =
that is expected to be supported for a fairly long time - say a decade or =
more. We are also as an industry moving to using COTS (commercial) =
components to reduce cost. Fine and good, but the life cycle for =
commercial parts is often pretty short compared with a military spec'd =
component - which puts us into a life time buy situation earlier rather =
than later.
My question:
Is there a good method to use to store BGA type components for long term =
storage? E.G. I build board X using a particular BGA part. It goes "end =
of life" a couple of years later, but I'm expected to support repair and =
overhaul for another few years yet, so I buy as many as I predict I'll =
need. As the time goes on, the solder balls oxidize. How should I store =
the spare parts? In nitrogen? Cold environment? Will it even be a =
problem?
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
---------------------------------------------------------------------------=
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Technet NOMAIL
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E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
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ext.5315
---------------------------------------------------------------------------=
------
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Date: Mon, 26 Nov 2001 16:45:47 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Isolation between connector pins
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Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between =
two pins of a SMD-connector with a spacing between the pins of about 0.5 =
mm.=20
This seems a bit on the critical side, and the designer asked me if it is =
possible to have some extra isolation between these pins. I was thinking =
that a drop of solderresist that we sometimes use for repairs would do the =
job, but I'm not sure that it'll work. Maybe someone can give me a better =
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Mon, 26 Nov 2001 11:40:13 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: BGA long term storage?
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Welcome to the COTS catch 22,
My experience is the best laid plans of "buy out and save" haven't worked.
What I've seen is the need to "Revision" spin for parts acceptibility or
repackage die either from the silicin to the package needed or have the sub
harvest from one package to the one needed. It just doesn't seem reasonable
to store piece parts for more than three years never mind ten plus.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Welcome to the COTS catch 22,
<BR>My experience is the best laid plans of "buy out and save" haven't worked. What I've seen is the need to "Revision" spin for parts acceptibility or repackage die either from the silicin to the package needed or have the sub harvest from one package to the one needed. It just doesn't seem reasonable to store piece parts for more than three years never mind ten plus.
<BR>
<BR>Brad</FONT></HTML>
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Date: Mon, 26 Nov 2001 11:45:50 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Isolation between connector pins
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I am seeing this 200 volt requirement everywhere. Hopefully you separate the
two signals in the schematic. Hopefully it isn't two adjacent pins
regardless of signal. Loctite, E/C or the equivalent source will have an
electrically isolating compound (such as used in backshells); but the
application is going to very costly in ongoing assemblies.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I am seeing this 200 volt requirement everywhere. Hopefully you separate the two signals in the schematic. Hopefully it isn't two adjacent pins regardless of signal. Loctite, E/C or the equivalent source will have an electrically isolating compound (such as used in backshells); but the application is going to very costly in ongoing assemblies.
<BR>
<BR>Brad</FONT></HTML>
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Date: Mon, 26 Nov 2001 12:18:02 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Buried Capacitance - unlicensed
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Sorry for the tardy reply, I am just affording some time now.
Coretec is a licensed PWB/PCB supplier of the buried capacitance material
"BC2000" (the Z has been dropped). Suppliers of substrate material are
required to report all shipments of clad 1-3 core. There is sufficient fines
that board suppliers will not risk doing quasi capacitance boards. Over .003
thick there is little capacitance gain (no pun intended), the patent
threshold. There is the propensity, which isn't bad. I know folks in the
business do not like nor agree with the patent and I am aware of and been to
the seminar where it is insinuated that the patent rights can be side
stepped. I personally feel the rights of the patentee must be respected and
in a business sense it just isn't worth the risk (monetarily).
Lastly, those who know how to build are successful, those who don't; aren't.
It is not like traces, opposing planes are different; hence the patent.
If there are any technical questions please contact me.
Best Regards,
Coretec's Boston Brad
781-858-0783
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Sorry for the tardy reply, I am just affording some time now.
<BR>
<BR>Coretec is a licensed PWB/PCB supplier of the buried capacitance material "BC2000" (the Z has been dropped). Suppliers of substrate material are required to report all shipments of clad 1-3 core. There is sufficient fines that board suppliers will not risk doing quasi capacitance boards. Over .003 thick there is little capacitance gain (no pun intended), the patent threshold. There is the propensity, which isn't bad. I know folks in the business do not like nor agree with the patent and I am aware of and been to the seminar where it is insinuated that the patent rights can be side stepped. I personally feel the rights of the patentee must be respected and in a business sense it just isn't worth the risk (monetarily).
<BR>Lastly, those who know how to build are successful, those who don't; aren't. It is not like traces, opposing planes are different; hence the patent.
<BR>If there are any technical questions please contact me.
<BR>
<BR>Best Regards,
<BR>Coretec's Boston Brad
<BR>781-858-0783</FONT></HTML>
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Date: Mon, 26 Nov 2001 12:29:09 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Copper Invar Copper and BGA's
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I have used both core and foil CIC boards and it is more challenging than non
metal boards. The rework was easier than the original profiling. That is
good. The need for touch up after reflow was common place. I never did
BGAs, but the need for heat in a BGA and the need for heat in CIC combined
with elongation of duration lends this CIC/BGA configuration as a predictable
need for touch up (can't touch up under a BGA easily). I might advise to
attach the BGAs after initial solder float. It is not very economical, but
then again neither is CIC.
I have had success with CIC and Thermount. Thermount has all but killed CIC
although there are moisture issues with Thermount. I say this relative to
the ongoing existence of CIC. The rumor mill had it that CIC was going the
way of Howefill... discontinued.
Coretec Brad
781 858 0783
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I have used both core and foil CIC boards and it is more challenging than non metal boards. The rework was easier than the original profiling. That is good. The need for touch up after reflow was common place. I never did BGAs, but the need for heat in a BGA and the need for heat in CIC combined with elongation of duration lends this CIC/BGA configuration as a predictable need for touch up (can't touch up under a BGA easily). I might advise to attach the BGAs after initial solder float. It is not very economical, but then again neither is CIC.
<BR>
<BR>I have had success with CIC and Thermount. Thermount has all but killed CIC although there are moisture issues with Thermount. I say this relative to the ongoing existence of CIC. The rumor mill had it that CIC was going the way of Howefill... discontinued.
<BR>
<BR>Coretec Brad
<BR>781 858 0783</FONT></HTML>
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Date: Mon, 26 Nov 2001 12:46:51 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Copper Invar Copper and BGA's
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_38.1f927e8d.2933da0b_boundary"
--part1_38.1f927e8d.2933da0b_boundary
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
Hi Brad!
Have you heard anything about StableCor=E2=84=A2 PCB's? Go to:
-Steve Gregory-
> I have used both core and foil CIC boards and it is more challenging than=20
> non metal boards. The rework was easier than the original profiling. Tha=
t=20
> is good. The need for touch up after reflow was common place. I never di=
d=20
> BGAs, but the need for heat in a BGA and the need for heat in CIC combined=
=20
> with elongation of duration lends this CIC/BGA configuration as a=20
> predictable need for touch up (can't touch up under a BGA easily). I migh=
t=20
> advise to attach the BGAs after initial solder float. It is not very=20
> economical, but then again neither is CIC.=20
>=20
> I have had success with CIC and Thermount. Thermount has all but killed=20
> CIC although there are moisture issues with Thermount. I say this relativ=
e=20
> to the ongoing existence of CIC. The rumor mill had it that CIC was going=
=20
> the way of Howefill... discontinued.=20
>=20
> Coretec Brad=20
>=20
--part1_38.1f927e8d.2933da0b_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2>Hi Brad!
<BR>
<BR>Have you heard anything about StableCor=E2=84=A2 PCB's? Go to:
<BR>
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I have used both core and f=
oil CIC boards and it is more challenging than non metal boards. The r=
ework was easier than the original profiling. That is good. The=20=
need for touch up after reflow was common place. I never did BGAs, but=
the need for heat in a BGA and the need for heat in CIC combined with elong=
ation of duration lends this CIC/BGA configuration as a predictable need for=
touch up (can't touch up under a BGA easily). I might advise to attac=
h the BGAs after initial solder float. It is not very economical, but then a=
gain neither is CIC.=20
<BR>
<BR>I have had success with CIC and Thermount. Thermount has all but k=
illed CIC although there are moisture issues with Thermount. I say thi=
s relative to the ongoing existence of CIC. The rumor mill had it that=
CIC was going the way of Howefill... discontinued.=20
<BR>
<BR>Coretec Brad=20
<BR>781 858 0783 </BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
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Date: Mon, 26 Nov 2001 13:58:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Subject: Silicones in Printed Wiring Board Assembly
MIME-Version: 1.0
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Technetters,
The "silicone contamination" question has been raised in my plant
again. An end user has requested that we certify that we don't use ANY
silicones in our electronic assembly facility (they have paint lines).
In various locations we use silicone RTVs and the like to seal face
plates, in addition to using RTVs in the maintenance areas for gasketing.
Are these "silicones" a threat to our customer regarding carrying
contamination into their plant?
And, knowing that various silicone oils and mold releases are a
definite no-no, are there other classes of silicones that are
dangerous/safe?
Where does one find references to such?
Thanks,
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 434-978-5181
FAX: 434-978-5898
e-mail: [log in to unmask]
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Date: Mon, 26 Nov 2001 14:14:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tom Parkinson - Quality System Manager <[log in to unmask]>
Subject: Re: Silicones in Printed Wiring Board Assembly
MIME-Version: 1.0
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Greg
You might also want to check the hand lotion your employees are using.
There are some out there that still have Silicone in them. Most do not,
but I'd check anyway.
Tom
"Anderson, Greg (IndSys, GEFanuc, NA)" wrote:
>
> Technetters,
> The "silicone contamination" question has been raised in my plant
> again. An end user has requested that we certify that we don't use ANY
> silicones in our electronic assembly facility (they have paint lines).
> In various locations we use silicone RTVs and the like to seal face
> plates, in addition to using RTVs in the maintenance areas for gasketing.
> Are these "silicones" a threat to our customer regarding carrying
> contamination into their plant?
> And, knowing that various silicone oils and mold releases are a
> definite no-no, are there other classes of silicones that are
> dangerous/safe?
> Where does one find references to such?
>
> Thanks,
>
> Greg Anderson
> Senior Advanced Manufacturing Engineer
> GE Fanuc Automation
> Charlottesville, VA 22911
> Phone: 434-978-5181
> FAX: 434-978-5898
> e-mail: [log in to unmask]
>
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Date: Mon, 26 Nov 2001 11:18:06 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Isolation between connector pins
In-Reply-To: <[log in to unmask]>
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Hi Daan,
That 220V sounds an awful lot like MAINS voltage. If that is the case you
probably need to worry a lot more about spacings dictated by safety
agencies, like UL in the USA or KEMA in The Netherlands, rather than
following the common V/mm guidelines.
On top of setting the rules for proper spacing between those pins they also
have rules regarding the spacing between those two pins and everything
else!!
The actual values depend on the purpose for which the board is being used.
Veel plezier,
Ahne,
A-Laser, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of d. terstegge
Sent: Monday, November 26, 2001 07:46
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Mon, 26 Nov 2001 13:34:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Silicones in Printed Wiring Board Assembly
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
The "silicone contamination" question has been raised in my plant
again. An end user has requested that we certify that we don't use ANY
silicones in our electronic assembly facility (they have paint lines).
In various locations we use silicone RTVs and the like to seal face
plates, in addition to using RTVs in the maintenance areas for gasketing.
Are these "silicones" a threat to our customer regarding carrying
contamination into their plant?
*In a word, yes. I know that in our facility, silicones are a major
contributor to conformal coating adhesion problems, which rapidly become MY
problem. Paint would likely be similar. Coatings do not like to adhere to
silicone RTVs, or to any outgassing or exuded oils or cure byproducts, or
"re-distributed" silicones.
And, knowing that various silicone oils and mold releases are a
definite no-no, are there other classes of silicones that are
dangerous/safe?
*The two most common here are silicone RTV adhesives and silicone thermal
grease (silicone gel filled with zinc oxide particles). Our manufacturing
procedures make sure these are very closely watched items, and life in
manufacturing would be easier if we could get certain concepts through to
certain design engineers (e.g. with a baseball bat). RTVs are mildly
cleaned before coating to get the exuded alcohol cure byproducts and the
silicone thermal grease does not go on until the automated wash processes
are over. This prevents our saponifier chemicals from washing the stuff
out. We also maintain a very aggressive preventative maintenance schedule
to make sure that even if there is silicone contamination, it does not
build to problem proportions. We are currently looking at non-silicone
alternatives to both materials.
*As far as mold release agents go, PTFE agents are more common, but
represent the same threat of adhesion loss that silicone does. If you are
using circuit boards, be advised that the use of silicones sometimes occurs
in PWB manufacturing, so you may have silicone surface residues coming in
from the boards shop and not know it. While not a common occurrance, it is
something to think about.
Where does one find references to such?
*Well, you just asked the best source for technical advise (TechNet, not
me). I don't know if you will find published articles on the topic. The
best experience in manufacturing problems comes from bad experiences in
manufacturing. Because of the "L" word (liability), most manufacturers do
not publish articles admitting they EVER had a manufacturing problem. You
might look for technical bulletins on Dow Corning's web site.
Doug Pauls
Rockwell Collins
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Date: Mon, 26 Nov 2001 12:51:02 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------98D42CC7E1B4C83717C878DB"
--------------98D42CC7E1B4C83717C878DB
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Brad,
I agree with your assessment but if management does not listen then
calculate the cost of 10 years worth of storage in dry nitrogen. If that
is not acceptable then plan be gone from the company before the contract
"clock" runs out.
David A. Douthit
Manager
LoCan LLC
Brad Saunders wrote:
> Welcome to the COTS catch 22,
> My experience is the best laid plans of "buy out and save" haven't
> worked. What I've seen is the need to "Revision" spin for parts
> acceptibility or repackage die either from the silicin to the package
> needed or have the sub harvest from one package to the one needed. It
> just doesn't seem reasonable to store piece parts for more than three
> years never mind ten plus.
>
> Brad
--------------98D42CC7E1B4C83717C878DB
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Brad,
<p>I agree with your assessment but if management does not listen then
calculate the cost of 10 years worth of storage in dry nitrogen. If that
is not acceptable then plan be gone from the company before the contract
"clock" runs out.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Brad Saunders wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Welcome
to the COTS catch 22,</font></font>
<br><font face="arial,helvetica"><font size=-1>My experience is the best
laid plans of "buy out and save" haven't worked. What I've seen is
the need to "Revision" spin for parts acceptibility or repackage die either
from the silicin to the package needed or have the sub harvest from one
package to the one needed. It just doesn't seem reasonable to store
piece parts for more than three years never mind ten plus.</font></font>
<p><font face="arial,helvetica"><font size=-1>Brad</font></font></blockquote>
</html>
--------------98D42CC7E1B4C83717C878DB--
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Date: Mon, 26 Nov 2001 14:49:04 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: Storage of moisture sensitive components
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-version: 1.0
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Dear Gaby,
Take note that the shelf life and the seal date on the package are only
there for information purpose. This is not an expiration date since it only
represents the minimum calculated shelf life, when stored in a noncondensing
atmospheric environment of <40C/90%RH. The Humidity Indicator Card (HIC)
inside the bag should always be the proper method to find out if parts need
to be baked before processing.
Ref: J-STD-033, section 6.3.4 Shelf life and section 8.5.1 Excessive
humidity in the dry pack
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Friday, November 23, 2001 8:08 AM
To: [log in to unmask]
Subject: [TN] Storage of moisture sensitive components
How long and in what conditions may moisture sensitive components be =
stored
in their original package?
Thank.you,
Gaby
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Date: Mon, 26 Nov 2001 12:11:06 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: Isolation between connector pins
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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For external layers, the minimum spacing for uncoated leads is 1.25mm, but
for coated leads it is .4mm. I'm sure someone here can suggest a good
permanent polymer coating. Also, if you can route a slot between the pins,
the numbers will change in your favor, but I'm not sure by how much.
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of d. terstegge
Sent: Monday, November 26, 2001 7:46 AM
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Mon, 26 Nov 2001 14:11:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: BGA long term storage?
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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Date: Mon, 26 Nov 2001 15:49:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bissonnette, Jean-Francois" <[log in to unmask]>
Subject: Acceptability of flex boards
MIME-Version: 1.0
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Is there a document giving detailed information on acceptability of
flexible printed circuit (like IPC-A-600 but on flex only).
If not what is the document closest to it?
Thanks!
JF
WABTEC CORPORATION CONFIDENTIALITY NOTE
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Date: Mon, 26 Nov 2001 15:56:02 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Acceptability of flex boards
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_105.ce830ef.29340662_boundary"
--part1_105.ce830ef.29340662_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Jean-Francois!
Sure is! Go to:
http://www.ipc.org/html/IPC-6013Amendment1Published4-00.pdf
and download it, it's free!
-Steve Gregory-
> Is there a document giving detailed information on acceptability of
> flexible printed circuit (like IPC-A-600 but on flex only).
>
> If not what is the document closest to it?
>
> Thanks!
>
> JF
>
--part1_105.ce830ef.29340662_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jean-Francois!
<BR>
<BR>Sure is! Go to:
<BR>
<BR>http://www.ipc.org/html/IPC-6013Amendment1Published4-00.pdf
<BR>
<BR>and download it, it's free!
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Is there a document giving detailed information on acceptability of
<BR>flexible printed circuit (like IPC-A-600 but on flex only).
<BR>
<BR>If not what is the document closest to it?
<BR>
<BR>Thanks!
<BR>
<BR>JF
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Mon, 26 Nov 2001 14:54:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Smith, Russell (US LA)" <[log in to unmask]>
Subject: Re: CuCl etch normality
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Any one out there have a good chart showing etch rate versus
acid normality in a Cupric Bath ?=20
=09
Thanks=20
Russell Smith
[log in to unmask]
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Date: Mon, 26 Nov 2001 16:57:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Looking for Information
MIME-Version: 1.0
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Hi folks! I'm looking for contact information for Altos Engineering and
their TVP Baking process - anyone have a good email or phone number? Also -
anyone using the TVP Baking process and could share their experiences with
it?
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Mon, 26 Nov 2001 16:53:25 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Yu-Hung Shiau <[log in to unmask]>
Subject: IPC SM-782 on-line calculator
Hi,
Does anyone know how to use the on-line SM-782 calculator? There are few
fields I don't know what numbers should I plug in.
1-1. Man. Allowance- P Place Accuracy
1-2. Man. Allowance- J/T Toe Min.
2-1. Solder Joint Design Goal- J/T Toe Min
2-1. Solder Joint Design Goal- J/H Heel Min
2-1. Solder Joint Design Goal- J/S Side Min
I have lost my hard copy of my IPC SM-782 standard for a while.
By the way, which category I should go for the resistor array (resistor
network) while I use the SM-782 calculator?
Thank you all for any feedback.
YH Shiau
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Date: Tue, 27 Nov 2001 10:29:31 +1100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: DUTTON Phil <[log in to unmask]>
Subject: Re: Isolation between connector pins
MIME-Version: 1.0
Content-Type: text/plain
Hello Daan,
This sounds like a connection to mains supply. In which case there are
safety compliance issues that must be addressed. I've just been designing
some power supply boards with 240V AC input voltages (our mains voltage in
Australia)We have a compliance engineer in our company who makes sure that
we do the right thing with respect to safety compliance and EMC. The
Comparative Tracking Index of the board material and the environment it is
used in comes into play. This can become a complex issue. Our Australian
Standard AS3260 is closely based on IEC-950, which would be a good place to
start looking. (As an example, our spacing for 240V AC is at least 2.5mm.)
regards,
Phil.
-----Original Message-----
From: d. terstegge [mailto:[log in to unmask]]
Sent: Tuesday, 27 November 2001 02:16
To: [log in to unmask]
Subject: [TN] Isolation between connector pins
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5 mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Mon, 26 Nov 2001 18:30:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Looking for Information
MIME-Version: 1.0
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Hi Dave!
Wasn't able to find anything on Altos Engineering directly, but found what I
think is a rep firm that offers the Altos Engineering Thermal Vacuum Drying
ovens. You might want to contact them to get a contact directly at Altos. Go
to:
http://www.sicoast.com/companies.html
-Steve Gregory-
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number? Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
--part1_f6.12f24d84.29342aa5_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Dave!<BR>
<BR>
Wasn't able to find anything on Altos Engineering directly, but found what I think is a rep firm that offers the Altos Engineering Thermal Vacuum Drying ovens. You might want to contact them to get a contact directly at Altos. Go to:<BR>
<BR>
http://www.sicoast.com/companies.html<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi folks! I'm looking for contact information for Altos Engineering and<BR>
their TVP Baking process - anyone have a good email or phone number? Also -<BR>
anyone using the TVP Baking process and could share their experiences with<BR>
it?<BR>
<BR>
Dave Hillman<BR>
Rockwell Collins<BR>
[log in to unmask]<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Mon, 26 Nov 2001 15:48:13 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Mazzoli <[log in to unmask]>
Subject: Re: CuCl etch normality
In-Reply-To: <[log in to unmask]
rp.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hey Russ,
Here's a link that might be what you're looking for:
http://www.circuitresearch.com/cupric_chloride_options.htm
At 02:54 PM 11/26/01 -0800, you wrote:
> Any one out there have a good chart showing etch rate versus
>acid normality in a Cupric Bath ?
>
>
> Thanks
>
> Russell Smith
> [log in to unmask]
>
>---------------------------------------------------------------------------------
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
>
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Date: Mon, 26 Nov 2001 20:31:46 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: CuCl etch normality
MIME-Version: 1.0
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If Mark Mazzoli's graph is not good enough....Don Ball of Atotech (formerly
Chemcut) in State College PA has a graph on data he generated with his own
hands...
Remember, that absolute etch rate is also a function of ORP, so one man's one
normal acid etch rate may not be the same as your results.
Rudy Sedlak
RD Chemical Company
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Date: Tue, 27 Nov 2001 08:35:02 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: Looking for Information
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
http://digital.ni.com/alliance.nsf/b7d49ea02c8aa32c8625642f007e2ba6/cbaf76de
5445e3c88625652a006fbff7?OpenDocument
Here is the wb site
Gaby
----- Original Message -----
From: "David Hillman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 27, 2001 12:57 AM
Subject: [TN] Looking for Information
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number?
Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
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>
>
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Date: Mon, 26 Nov 2001 23:44:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
In-Reply-To: <000801c1770d$a5e7da00$8655003e@gabriela>
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Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
_________________________________________________________
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Date: Tue, 27 Nov 2001 06:49:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
Mime-Version: 1.0
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Peter
I agree - cooling the jigs can be a big problem for throughput. One =
solution I've seen was to have a rack at the unload end, the operators =
would put the jigs in it and a fan directed at the rack would convection =
cool them faster than just sitting.
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/27/01 03:44AM >>>
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com=20
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E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
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Date: Tue, 27 Nov 2001 07:02:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: BGA long term storage?
Mime-Version: 1.0
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Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. =
It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use =
(unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm =
thick document describing some experiments and results with it. Very =
interesting machine. Do you know if anything ever come of the work to =
produce a commercial (non-lab) version of this? Hmm... wonder what =
happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is =
the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX =
missile)
and decreaseing market clout, has had to deal with lifetime buys for a =
long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell =
is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that =
much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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Date: Tue, 27 Nov 2001 12:13:43 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Adrian Irwin <[log in to unmask]>
Subject: Re: Wave soldering jig thickness
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
There are exit conveyors you can purchase that have fans installed. We have
recently purchased one from GWB. The size of the pallet will have an effect
on the profile so this must be checked, with regards to the dross I can not
comment as we always use pallets.
Adrian Irwin
New Products Manager
Lambda UK
Graham Collins
<Collins.Graham@LITT To: [log in to unmask]
ONLSL.COM> cc:
Sent by: TechNet Subject: Re: [TN] Wave soldeing jig thickness
<[log in to unmask]>
11/27/01 11:49 AM
Please respond to
"TechNet E-Mail
Forum."
Peter
I agree - cooling the jigs can be a big problem for throughput. One
solution I've seen was to have a rack at the unload end, the operators
would put the jigs in it and a fan directed at the rack would convection
cool them faster than just sitting.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/27/01 03:44AM >>>
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
_________________________________________________________
Do You Yahoo!?
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Date: Wed, 27 Nov 2002 13:37:29 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rajkumar <[log in to unmask]>
Subject: University web page
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_000F_01C2961A.217CAC50"
This is a multi-part message in MIME format.
------=_NextPart_000_000F_01C2961A.217CAC50
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Dear Technet members
Can you pls check the following website
http://www.acme.salford.ac.uk/research/emerg/home.htm
Regards
Raj
Rajkumar Durairaj
Electronics Manufacturing Engineering Research Group
School of Aeronautical, Civil and Mechanical Engineering
University of Salford
http://www.acme.salford.ac.uk/emerg
Salford, UK, M5 4WT
Tel: +44-161-2954696
Fax: +44-161-2955575/5060
------=_NextPart_000_000F_01C2961A.217CAC50
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Dear Technet members</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Can you pls check the following=20
website</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.acme.salford.ac.uk/research/emerg/home.htm">http://www=
.acme.salford.ac.uk/research/emerg/home.htm</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Raj</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Rajkumar Durairaj<BR>Electronics =
Manufacturing=20
Engineering Research Group<BR>School of Aeronautical, Civil and =
Mechanical=20
Engineering<BR>University of Salford<BR><A=20
href=3D"http://www.acme.salford.ac.uk/emerg">http://www.acme.salford.ac.u=
k/emerg</A><BR>Salford,=20
UK, M5 4WT<BR>Tel: +44-161-2954696<BR>Fax: =
+44-161-2955575/5060</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV></BODY></HTML>
------=_NextPart_000_000F_01C2961A.217CAC50--
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Date: Tue, 27 Nov 2001 07:22:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Organization: Ventura Electronics Assembly
Subject: Pick-and-Place Evaluation Checklist?
MIME-Version: 1.0
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I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Tue, 27 Nov 2001 10:58:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Looking for Information
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Try:
Altos Engineering [500-9 TVP Demoisturizing System] 6009 North 61st Ave
Glendale AZ 85301 602-931-8434 fax 602-937-6396
Can't comment on their product.
Dave Fish
----- Original Message -----
From: "David Hillman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, November 26, 2001 2:57 PM
Subject: [TN] Looking for Information
> Hi folks! I'm looking for contact information for Altos Engineering and
> their TVP Baking process - anyone have a good email or phone number?
Also -
> anyone using the TVP Baking process and could share their experiences with
> it?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
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Date: Tue, 27 Nov 2001 11:03:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
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Rick,
The important question is SMT or PTH?
We are using Contact Systems PTH equipment (5 systems) are very happy
with them.
One question that becomes important is, what means is used to go from
your PCB layout program to making a working machine placement program?
We ended up creating a custom Microsoft Access=AE module that made =
several
comparisons and ran several filters to output those components that were
machine inserted and a separate list of the non-machine insertable
parts.
Phil Nutting=20
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 10:22 AM
To: [log in to unmask]
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Tue, 27 Nov 2001 11:22:31 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gary Bremer <[log in to unmask]>
Mime-Version: 1.0
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Whith the removal of all the good cleaning solvents, what is
recommended for cleaning gold card edge fingers? IPA electronic
grade does not work any suggestions?
Gary Bremer
Manufacturing Engineer
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Date: Tue, 27 Nov 2001 10:33:26 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
In-Reply-To: <001001c17757$4dc6aa50$3d00a8c0@rick>
MIME-Version: 1.0
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Try the IPC-9850 document.
The scope statement is attached below.
1.1 Scope
This standard establishes the procedures to characterize machine placement
capability of surface mount assembly
equipment in specification documents, as well as in documentation used to
verify a specific machine's placement
capability conformance to the specification, while maintaining a placement
accuracy to placement speed
relationship.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Thompson
Sent: Tuesday, November 27, 2001 7:22 AM
To: [log in to unmask]
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Tue, 27 Nov 2001 12:50:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Circuits Assembly Magazine, www.circuitsassembly.com, has an annual
comparison guide on its website. I believe the document is in .pdf format
that can be downloaded or viewed on-line. It gives side by side comparisons
of all the machines from placement speed to feeder changeover time,
including some aspects that you may not think of.
Steve Sauer
Mfg. Engineer
Xetron Corporation
-----Original Message-----
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines.
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Date: Tue, 27 Nov 2001 14:32:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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There was a post on this last year. And a good response. I do not remember
all the fields.
P Place accuracy is an allowance for your pick and place equipment.
The solder joint design goals are derived from the component and the type of
solder fillet you want. Minimum Heel fillet height for example, Class 3 is
the thickness of the solder under the lead plus the thickness of the lead .
. . I wouldn't expect there to be too much solder under the lead. So, the
thickness of the lead would be an appropriate value to place there.
If this was not enough help try the archive . . . If that doesn't help. Post
back and I will try harder.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Yu-Hung Shiau
> Sent: Monday, November 26, 2001 5:53 PM
> To: [log in to unmask]
> Subject: [TN] IPC SM-782 on-line calculator
>
>
> Hi,
> Does anyone know how to use the on-line SM-782 calculator? There are few
> fields I don't know what numbers should I plug in.
>
> 1-1. Man. Allowance- P Place Accuracy
> 1-2. Man. Allowance- J/T Toe Min.
>
> 2-1. Solder Joint Design Goal- J/T Toe Min
> 2-1. Solder Joint Design Goal- J/H Heel Min
> 2-1. Solder Joint Design Goal- J/S Side Min
>
> I have lost my hard copy of my IPC SM-782 standard for a while.
>
> By the way, which category I should go for the resistor array (resistor
> network) while I use the SM-782 calculator?
>
> Thank you all for any feedback.
> YH Shiau
>
> ------------------------------------------------------------------
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> ---------------
>
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Date: Tue, 27 Nov 2001 15:02:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
MIME-Version: 1.0
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There are three items that are required to be filled in when using the
calculator.
The first is the allowances for fabrication (etch factor). The second is the
pick and place accuracy. If you are unsure what number to actually use, you
may select the default for that component group as shown in the online
assumptions block.
Next you will have to indicate what your desire solder joint fillet sizes
are. These are for the toe, heel and side. These values usually come from
your manufacturing assemblers. However, you may again utilize the default
values for that specific component family as shown in the assumptions table
or in similar components within the family in the calculator.
You will be required to make adjustments so that the resulting land pattern
fits comfortably on an even grid increment. Make sure you consider which
joint provides the greatest strength to the connection and make your
adjustments so as not to violate that particular minimum joint requirement.
The other two joints are not as significant and therefore may go on the
negative side in relation to the lead size.
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Date: Tue, 27 Nov 2001 15:21:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lee Whiteman <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
X-cc: Jeff Stong <[log in to unmask]>
In-Reply-To: <001001c17757$4dc6aa50$3d00a8c0@rick>
MIME-Version: 1.0
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Rick,
You may want to check out the following website from SMT In Focus:
http://www.smtinfocus.com/processguide_placement.html.
One thing that you may also wish to consider is the health of the company
that you're buying your equipment from. In these times, it would be
unfortunate if you purchased a very sophisticated piece of hardware only to
find out that the company you purchased it from went out of business.
Good Luck
Lee Whiteman
Senior Manufacturing Engineer
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x208
Fax: (610) 362-1290
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Thompson
> Sent: Tuesday, November 27, 2001 10:22 AM
> To: [log in to unmask]
> Subject: [TN] Pick-and-Place Evaluation Checklist?
>
>
> I'm in the process of looking for new equipment and was wondering if
> there are any online resources such as checklists or evaluation guides
> for features, etc. to use when comparing machines. I realize that a lot
> of it depends on individual needs but was hoping there may be some
> generic guidelines available as a good starting point. Can anyone point
> me in the right direction or perhaps be willing to share something
> you've used?
>
> Thanks in advance for any help you might be able to provide.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2655 Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 x-304 voice
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Date: Tue, 27 Nov 2001 15:04:36 -0600
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Date: Tue, 27 Nov 2001 22:53:05 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Pick-and-Place Evaluation Checklist?
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See http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html for =
a survey of pick&place machines.
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: Rick Thompson=20
To: [log in to unmask]
Sent: Tuesday, November 27, 2001 4:22 PM
Subject: [TN] Pick-and-Place Evaluation Checklist?
I'm in the process of looking for new equipment and was wondering if
there are any online resources such as checklists or evaluation guides
for features, etc. to use when comparing machines. I realize that a =
lot
of it depends on individual needs but was hoping there may be some
generic guidelines available as a good starting point. Can anyone =
point
me in the right direction or perhaps be willing to share something
you've used?
Thanks in advance for any help you might be able to provide.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
=
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in
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To temporarily halt delivery of Technet send the following message: =
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Databases > E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for =
additional
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>See <A=20
href=3D"http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html">=
http://www.smtinline.com/html-en/NewProducts/p-p-survey-en.html</A> =
for=20
a survey of pick&place machines.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Daan Terstegge</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">Rick Thompson</A> =
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 27, =
2001 4:22=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Pick-and-Place =
Evaluation=20
Checklist?</DIV>
<DIV><BR></DIV>I'm in the process of looking for new equipment and was =
wondering if<BR>there are any online resources such as checklists or=20
evaluation guides<BR>for features, etc. to use when comparing =
machines. I=20
realize that a lot<BR>of it depends on individual needs but was hoping =
there=20
may be some<BR>generic guidelines available as a good starting point. =
Can=20
anyone point<BR>me in the right direction or perhaps be willing to =
share=20
something<BR>you've used?<BR><BR>Thanks in advance for any help you =
might be=20
able to provide.<BR><BR><BR>Rick Thompson<BR>Ventura Electronics=20
Assembly<BR>2655 Park Center Dr.<BR>Simi Valley, CA 93065<BR><BR>+1 =
(805)=20
584-9858 x-304 voice<BR>+1 (805) 584-1529 fax<BR><A=20
=
href=3D"mailto:[log in to unmask]">rthompson@venturaelectro=
nics.com</A><BR><BR>-----------------------------------------------------=
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Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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Date: Tue, 27 Nov 2001 13:57:41 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Other than utilizing exit cooling fans, what other
cooling medium and method would be considered
practical?
Rgds,
Peter
--- Graham Collins <[log in to unmask]>
wrote:
> Peter
> I agree - cooling the jigs can be a big problem for
> throughput. One solution I've seen was to have a
> rack at the unload end, the operators would put the
> jigs in it and a fan directed at the rack would
> convection cool them faster than just sitting.
>
> regards
>
> Graham Collins
> Process Engineer,
> Northrop Grumman
> Atlantic Facility of Litton Systems Canada
> (902) 873-2000 ext 6215
>
> >>> [log in to unmask] 11/27/01 03:44AM >>>
> Hello,
>
> Has anyone experienced problems with running boards
> through wave
> soldering in a pallet with deep machined pockets?
>
> My jigs are quite thick (~0.5") in order to mask off
> the high filter
> components on the solder side. As a result the jigs
> get very hot after
> soldering and takes long time to cool down to be
> feed back to the cycle.
> It also affects my profiling, throughput, and seems
> to create more dross
> than usual.
>
> Any comment or advice?
>
> Rgds,
> Peter
>
>
>
_________________________________________________________
> Do You Yahoo!?
> Get your free @yahoo.com address at
> http://mail.yahoo.com
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>
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>
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Date: Tue, 27 Nov 2001 17:12:15 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: SSOP to SOIC adaptors...
MIME-Version: 1.0
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Hey All!!
Getting ready for our first winter blast here in "Okra-homie"...supposed to
get sleet, freezing rain, and snow starting tonight and lasting through
tomorrow night. Funny thing is, it was in the 70's this past weekend????
On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build
3-boards that uses three RS-232 Transceivers per board (this is the first
build of these boards), and the problem is that these parts are 20-pin
SSOP's, but the footprint on the board is standard 20-pin SOIC's. I know
that's NEVER happened to any of you before, huh?
Tried Adapters.Com, and they don't have anything off-the-shelf...they'll make
us some, at $80 each, with a two-week turn...no good.
Aries has one that will work, the SSOP will have some toe overhang, but not
real bad. Trying to find stock somewhere...
Is there anyplace else that I might look in case we can't find stock on the
Aries part?
Thanks a bunch!!!
-Steve Gregory-
--part1_86.134574c7.293569bf_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey All!!
<BR>
<BR>Getting ready for our first winter blast here in "Okra-homie"...supposed to get sleet, freezing rain, and snow starting tonight and lasting through tomorrow night. Funny thing is, it was in the 70's this past weekend????
<BR>
<BR>On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build 3-boards that uses three RS-232 Transceivers per board (this is the first build of these boards), and the problem is that these parts are 20-pin SSOP's, but the footprint on the board is standard 20-pin SOIC's. I know that's NEVER happened to any of you before, huh?
<BR>
<BR>Tried Adapters.Com, and they don't have anything off-the-shelf...they'll make us some, at $80 each, with a two-week turn...no good.
<BR>
<BR>Aries has one that will work, the SSOP will have some toe overhang, but not real bad. Trying to find stock somewhere...
<BR>
<BR>Is there anyplace else that I might look in case we can't find stock on the Aries part?
<BR>
<BR>Thanks a bunch!!!
<BR>
<BR>-Steve Gregory-</FONT></HTML>
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Date: Wed, 28 Nov 2001 11:14:44 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Solder Resist and QFP's
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Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this matter?
Cheers
Mike
------_=_NextPart_001_01C17790.EAFF4B40
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=560331122-27112001>Hi
all,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=560331122-27112001>What
are peoples thoughts on solder resist between fine pitch micro pads??? I
have recently heard two differing theories regarding this matter, one is that
solder resist between the pads on some very fine pitch QFP's will reduce the
risk of solder shorts. The other theory was that with solder resist between
these pads you could risk getting the resist onto the pads and reducing the
soldering surface??? What is the general consensus on this matter???
Which approach to others take on this matter?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001>Cheers</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001>Mike</SPAN></FONT></DIV></BODY></HTML>
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Date: Tue, 27 Nov 2001 15:17:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: Need Help with 85-15 Altera QFPs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
> Fellow Technetters:
>
> I am sending this looking for any help, I guess I've done everything
> as far as the process and I haven't been able to resolve the issue. We've
> been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> finish on the leads. The solder doesn't flow properly and an acceptable
> solder joint is not formed, the leads can be sometimes lifted with no
> effort. The solder paste was checked after the screen printer operation
> and it looked alright, the oven profile was also verified and it's always
> within the solder paste manufacturer's recommendations. This problem seems
> to be affecting all the different products with this type of component.
> These part numbers are manufactured by Altera. Has anybody experienced
> similar problems with QFPs from this manufacturer?, Does anybody have
> recommendations as far as the reflow oven profile?. I read somewhere that
> this particular alloy has the liquidus temperature at 205 degrees, is this
> accurate?
>
Any help would be really appreciated
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> E-mail: [log in to unmask]
>
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Date: Tue, 27 Nov 2001 15:52:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivan Barrios <[log in to unmask]>
Subject: Wave soldeing jig thickness
MIME-Version: 1.0
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One thing you can try, is that since you have to return the jigs anyway to
the beginning of the wave solder process, you might want to use a conveyor
with fans on top so that the fans will cool off the pallets as they go
through the conveyor.
Ivan
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
--=_alternative 007DEF6487256B11_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="Courier New">One thing you can try, is that since you have to return the jigs anyway to the beginning of the wave solder process, you might want to use a conveyor with fans on top so that the fans will cool off the pallets as they go through the conveyor. </font>
<br><font size=2 face="Courier New">Ivan</font>
<br>
<br>
<br><font size=2 face="Courier New">Date: Mon, 26 Nov 2001 23:44:19 -0800<br>
From: Peter Lee <[log in to unmask]><br>
Subject: Wave soldeing jig thickness<br>
<br>
Hello,<br>
<br>
Has anyone experienced problems with running boards through wave<br>
soldering in a pallet with deep machined pockets?<br>
<br>
My jigs are quite thick (~0.5") in order to mask off the high filter<br>
components on the solder side. As a result the jigs get very hot after<br>
soldering and takes long time to cool down to be feed back to the cycle.<br>
It also affects my profiling, throughput, and seems to create more dross<br>
than usual.<br>
<br>
Any comment or advice?<br>
<br>
Rgds,<br>
Peter</font>
--=_alternative 007DEF6487256B11_=--
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Date: Tue, 27 Nov 2001 17:09:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: Re: E-mail Address Changed
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Carl,
You are indeed subscribed as [log in to unmask] for Technet.
No action is necessary.
Keach=20
>>> [log in to unmask] 11/27/01 15:17 PM >>>
My new e-mail address will be [log in to unmask] . Please ensure you
have changed my address in your files or there is a fellow at SCI who
will receive my e-mails.
This will take effect Friday November 30th.
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Date: Wed, 28 Nov 2001 08:31:25 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Isolation between connector pins
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Hi, Daan,
Are all the connector pins being used? Frequently, several to many pins are
not used, in which case why not design so that pins adjacent to the 220V AC
connection are not connected to anything else. This will effectively
increase the spacing between the high voltage and other signals.
Peter Duncan
"d. terstegge"
<[log in to unmask] To: [log in to unmask]
GROUP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Isolation between connector pins
11/26/01 11:45 PM
Please respond to
"TechNet E-Mail Forum."
Hi Technetters,
On one of our new designs must be able to withstand a 220 Volt AC between
two pins of a SMD-connector with a spacing between the pins of about 0.5
mm.
This seems a bit on the critical side, and the designer asked me if it is
possible to have some extra isolation between these pins. I was thinking
that a drop of solderresist that we sometimes use for repairs would do the
job, but I'm not sure that it'll work. Maybe someone can give me a better
advice ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Tue, 27 Nov 2001 22:34:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: SSOP to SOIC adaptors...
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charset="iso-8859-1"
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Try:
Aries 908.996.6841
Antona 310.473.8995
Oztech 510.782.2654fax2656
Emulation Technology 408.982.0660 800.232.7837 fax 0664 =
www.emulation.com
Interconnect Systems 708 Via Alondra Camarillo CA 93012 805.482.2870 fax =
8470 www.isipkg.com
Dave Fish
----- Original Message -----=20
From: Stephen R. Gregory=20
To: [log in to unmask]
Sent: Tuesday, November 27, 2001 2:12 PM
Subject: [TN] SSOP to SOIC adaptors...
Hey All!!=20
Getting ready for our first winter blast here in =
"Okra-homie"...supposed to get sleet, freezing rain, and snow starting =
tonight and lasting through tomorrow night. Funny thing is, it was in =
the 70's this past weekend????=20
On to my question; looking for a SSOP-to-SOIC adaptor. Trying to build =
3-boards that uses three RS-232 Transceivers per board (this is the =
first build of these boards), and the problem is that these parts are =
20-pin SSOP's, but the footprint on the board is standard 20-pin SOIC's. =
I know that's NEVER happened to any of you before, huh?=20
Tried Adapters.Com, and they don't have anything =
off-the-shelf...they'll make us some, at $80 each, with a two-week =
turn...no good.=20
Aries has one that will work, the SSOP will have some toe overhang, =
but not real bad. Trying to find stock somewhere...=20
Is there anyplace else that I might look in case we can't find stock =
on the Aries part?=20
Thanks a bunch!!!=20
-Steve Gregory-=20
------=_NextPart_000_0014_01C17793.A4FE1F60
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Try:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Aries 908.996.6841<BR>Antona =
310.473.8995<BR>Oztech=20
510.782.2654fax2656<BR>Emulation Technology 408.982.0660 800.232.7837 =
fax 0664=20
<A =
href=3D"http://www.emulation.com">www.emulation.com</A><BR>Interconnect =
Systems=20
708 Via Alondra Camarillo CA 93012 805.482.2870 fax 8470 <A=20
href=3D"http://www.isipkg.com">www.isipkg.com</A></FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Dave Fish</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Stephen =
R.=20
Gregory</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, November 27, =
2001 2:12=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] SSOP to SOIC=20
adaptors...</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Hey All!!=20
<BR><BR>Getting ready for our first winter blast here in=20
"Okra-homie"...supposed to get sleet, freezing rain, and snow starting =
tonight=20
and lasting through tomorrow night. Funny thing is, it was in the 70's =
this=20
past weekend???? <BR><BR>On to my question; looking for a SSOP-to-SOIC =
adaptor. Trying to build 3-boards that uses three RS-232 Transceivers =
per=20
board (this is the first build of these boards), and the problem is =
that these=20
parts are 20-pin SSOP's, but the footprint on the board is standard =
20-pin=20
SOIC's. I know that's NEVER happened to any of you before, huh? =
<BR><BR>Tried=20
Adapters.Com, and they don't have anything off-the-shelf...they'll =
make us=20
some, at $80 each, with a two-week turn...no good. <BR><BR>Aries has =
one that=20
will work, the SSOP will have some toe overhang, but not real bad. =
Trying to=20
find stock somewhere... <BR><BR>Is there anyplace else that I might =
look in=20
case we can't find stock on the Aries part? <BR><BR>Thanks a bunch!!!=20
<BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0014_01C17793.A4FE1F60--
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Date: Wed, 28 Nov 2001 12:25:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: IPC SM-782 on-line calculator
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Yu-Hung Shiau
<yshiau@ATPUS To: [log in to unmask]
A.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] IPC SM-782 on-line calculator
<[log in to unmask]
ORG>
11/27/01
06:53 AM
Please
respond to
"TechNet
E-Mail
Forum."
Land Pattern calculation is still an artform, not a science and depends on
a number of parameters such as board material, component package (often
manufacturer-specific), assembly process to be used (Wave or CR, etc), P&P
machines being used to populate the boards and your own design rules.
I raised this issue on TechNet a few weeks ago, especially since I was
getting different answers for land pattern sizes depending on which method
I used ( component data sheets, SM-782 or calculators). IPC stated that
they are working to address these issues. However, to answer your specific
questions, see comments below, PLUS the 4 main factors to consider are the
board manufacturing tolerence, the component placement tolerence and the
tolerence of the component itself, as well as the component's actual
lead:board contact area and component dimensions.
If you have any experience of determining land patterns that work, use that
background to judge the "reasonableness" of the calculated results. For
example, the larger allowance between heel and toe has to go to the end
where max stress is going to be experienced. Usually this is the end where
the lead goes on to join the component body, if you follow.
Hi,
Does anyone know how to use the on-line SM-782 calculator? There are few
fields I don't know what numbers should I plug in.
1-1. Man. Allowance- P Place Accuracy **FIND OUT FROM YOUR ASSEMBLY PEOPLE
WHAT THE PLACEMENT ACCURACY IS OF THE PICK AND PLACE MACHINES THEY USE AND
PLUG THAT FIGURE IN.**
1-2. Man. Allowance- J/T Toe Min. ** FROM YOU FAB HOUSE, OBTAIN THE PAD
POSITIONAL TOLERENCE THEY ARE WORKING TO WHEN FABRICATING THE BOARDS AND
PLUG THAT FIGURE IN.**
2-1. Solder Joint Design Goal- J/T Toe Min **IN THE ABSENCE OF COMPONENT
DATA SHEET INFORMATION OR SPECIFIC DATA FOR THE PACKAGE FROM SM-782, MIN.
TOE ALLOWANCE CAN BE TAKEN FROM TABLE 3.4 (NEAR THE FRONT) OF SM-782. I
DON'T BELIEVE IT'S ACCURATE FOR ALL PURPOSES, BUT IT'S THE BEST AVAILABLE
IN THE ABSENCE OF ANY OTHER INFO.**
2-1. Solder Joint Design Goal- J/H Heel Min ** SAME AS FOR TOE-TAKE FROM
THE SPEC TABLE**
2-1. Solder Joint Design Goal- J/S Side Min ** SIDE ALLOWANCE DEPENDS ON
THE COMPONENT PITCH AND LAND SPACING REQUIREMENTS OF THE DESIGN. FIND A
COMPROMISE BETWEEN YOUR DESIGN RULES AND THE REQUIREMENTS OF THE COMPONENT.
OFTEN THE SIDE ALLOWANCE IS ZERO BECAUSE THERE ISN'T ROOM TO HAVE THE PAD
ANY WIDER THAN THE COMPONENT LEAD, BUT ARE ALSO NOT MUCH LARGER IN MANY
CASES THAN ABOUT 0.02MM. I THINK A SIDE ALLOWANCE IS ALSO GIVEN IN THE SPEC
TABLE **
**IN SUMMARY, YOU HAVE YOU USE YOUR OWN BEST KNOWLEDGE/JUDGEMENT TO OBTAIN
THE FINAL PATTERN. DON'T MAKE THEM TOO LONG AT EITHER END, OR TOO SHORT
EITHER, BUT DETERMINING WHAT IS TOO LONG AND WHAT IS TOO SHORT COMES DOWN
TO EXPERIENCE, TRIAL AND ERROR.**
I have lost my hard copy of my IPC SM-782 standard for a while. **I DON'T
HAVE A COPY OF THE SPEC TO HAND EITHER, OR I WOULD BE ABLE TO REPRODUCE THE
TABLE FOR YOU - IT'S NOT VERY LARGE.**
By the way, which category I should go for the resistor array (resistor
network) while I use the SM-782 calculator? **SORRY, CAN'T HELP YOU HERE**
Thank you all for any feedback.
YH Shiau
Best of luck
Peter Duncan
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Date: Tue, 27 Nov 2001 23:49:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
In-Reply-To: <[log in to unmask]>
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How about industrial air/water chiller small enough to stack several
jigs in for a short period of time? Has anyone come across something
like that?
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ivan Barrios
Sent: November 27, 2001 2:53 PM
To: [log in to unmask]
Subject: [TN] Wave soldeing jig thickness
One thing you can try, is that since you have to return the jigs anyway
to the beginning of the wave solder process, you might want to use a
conveyor with fans on top so that the fans will cool off the pallets as
they go through the conveyor.
Ivan
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'>How about industrial air/water chiller small =
enough
to stack several jigs in for a short period of time? Has anyone come =
across something
like that?<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><span class=3DSpellE><font size=3D2 color=3Dnavy =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;mso-fareast-font-family:PMing=
LiU;
color:navy;mso-fareast-language:ZH-TW'>Rgds</span></font></span><font =
size=3D2
color=3Dnavy face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial;
mso-fareast-font-family:PMingLiU;color:navy;mso-fareast-language:ZH-TW'>,=
<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'>Peter<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;mso-fareast-font-family:PMingLiU;color:navy;
mso-fareast-language:ZH-TW'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D2 =
face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'>-----Original =
Message-----<br>
<b><span style=3D'font-weight:bold'>From:</span></b> TechNet
[mailto:[log in to unmask]] <b><span style=3D'font-weight:bold'>On Behalf =
Of </span></b>Ivan
Barrios<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> =
</span></font><st1:date
Month=3D"11" Day=3D"27" Year=3D"2001"><font size=3D2 face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'>November 27, =
2001</span></font></st1:date><font
size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;font-family:Tahoma'> </span></font><st1:time
Hour=3D"14" Minute=3D"53"><font size=3D2 face=3DTahoma><span =
style=3D'font-size:10.0pt;
font-family:Tahoma'>2:53 PM</span></font></st1:time><font size=3D2 =
face=3DTahoma><span
style=3D'font-size:10.0pt;font-family:Tahoma'><br>
<b><span style=3D'font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> [TN] Wave =
soldeing jig
thickness</span></font></p>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal style=3D'margin-left:.5in'><font size=3D3 =
face=3D"Times New Roman"><span
style=3D'font-size:12.0pt'><br>
</span></font><font size=3D2 face=3D"Courier New"><span =
style=3D'font-size:10.0pt;
font-family:"Courier New"'>One thing you can try, is that since you have =
to
return the jigs anyway to the beginning of the wave solder process, you =
might
want to use a conveyor with fans on top so that the fans will cool off =
the
pallets as they go through the conveyor. </span></font><br>
<font size=3D2 face=3D"Courier New"><span =
style=3D'font-size:10.0pt;font-family:"Courier New"'>Ivan</span></font>
<br>
<br>
<br>
<font size=3D2 face=3D"Courier New"><span =
style=3D'font-size:10.0pt;font-family:"Courier New"'>Date:
Mon, 26 Nov 2001 23:44:19 -0800<br>
From: Peter Lee <[log in to unmask]><br>
Subject: Wave soldeing jig thickness<br>
<br>
Hello,<br>
<br>
Has anyone experienced problems with running boards through wave<br>
soldering in a pallet with deep machined pockets?<br>
<br>
My jigs are quite thick (~0.5") in order to mask off the high =
filter<br>
components on the solder side. As a result the jigs get very hot =
after<br>
soldering and takes long time to cool down to be feed back to the =
cycle.<br>
It also affects my profiling, throughput, and seems to create more =
dross<br>
than usual.<br>
<br>
Any comment or advice?<br>
<br>
Rgds,<br>
Peter</span></font><o:p></o:p></p>
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Date: Wed, 28 Nov 2001 12:08:29 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Hmmm, seems I'm the only one who adviced not to worry about long term =
storage of BGA's. I must admit that I never stored a BGA for 10 years to =
see how it solders, but I really don't expect the solderability to =
decrease to such an extend that the balls will not solder anymore.
According to Klein Wassink the oxidation layer on solder will grow =
approximately logarithmically with time, resulting in about 6nm after 20 =
years which is just twice as thick as after one year !
So my question is: are nitrogen cabinets, ROSA-technology or redesigns =
REALLY necesarry ?
Maybe one of the metallurgists on this forum can add a few words ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Graham Collins <[log in to unmask]> 11/27 1:02 pm >>>
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. =
It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use =
(unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm =
thick document describing some experiments and results with it. Very =
interesting machine. Do you know if anything ever come of the work to =
produce a commercial (non-lab) version of this? Hmm... wonder what =
happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is =
the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX =
missile)
and decreaseing market clout, has had to deal with lifetime buys for a =
long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell =
is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that =
much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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Date: Wed, 28 Nov 2001 08:27:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
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Mike,
I think that a good board shop should be able to avoid contaminating the pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of shorts.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 5:15 PM
To: [log in to unmask]
Subject: [TN] Solder Resist and QFP's
Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this matter?
Cheers
Mike
------_=_NextPart_001_01C17810.6CDDF560
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.3315.2870" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=435102313-28112001>Mike,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=435102313-28112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=435102313-28112001>I
think that a good board shop should be able to avoid contaminating the pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of
shorts.</SPAN></FONT></DIV>
<P><FONT face="Times New Roman">Thanks,</FONT> <BR><I><FONT color=#000080
face="Comic Sans MS">Robert Furrow</FONT></I> <BR><FONT face=Arial
size=2>Printed Wiring Board Engineer</FONT> <BR><FONT face=Arial
size=2>Strategic Supply Global Account Manager</FONT> <BR><FONT face=Arial
size=2>Supply Chain Networks</FONT> <BR><FONT face=Arial size=2>Lucent
Technologies</FONT> <BR><FONT face=Arial
size=2>978-960-3224 <U> </U></FONT><U><FONT color=#0000ff
face=Arial size=2>[log in to unmask]</FONT></U> </P>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Michael Bell
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, November 27, 2001
5:15 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Solder Resist
and QFP's<BR><BR></DIV></FONT>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=560331122-27112001>Hi
all,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=560331122-27112001>What
are peoples thoughts on solder resist between fine pitch micro pads??? I
have recently heard two differing theories regarding this matter, one is that
solder resist between the pads on some very fine pitch QFP's will reduce the
risk of solder shorts. The other theory was that with solder resist between
these pads you could risk getting the resist onto the pads and reducing the
soldering surface??? What is the general consensus on this
matter??? Which approach to others take on this
matter?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001>Cheers</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=560331122-27112001>Mike</SPAN></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 28 Nov 2001 08:22:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
Mime-Version: 1.0
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IMHO it doesn't really matter. You need to have different controls built =
in depending which method you are using. =20
Kathy=20
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<DIV>IMHO it doesn't really matter. You need to have different controls
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<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 28 Nov 2001 07:44:14 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ou Sokkhon-R5AALJ <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
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May be you need to look for different material for your jig so that the jig is thinner and carry less heat. Also you probably need to build more jig to allow cool off time before use it again.
Regards
Date: Mon, 26 Nov 2001 23:44:19 -0800
From: Peter Lee <[log in to unmask]>
Subject: Wave soldeing jig thickness
Hello,
Has anyone experienced problems with running boards through wave
soldering in a pallet with deep machined pockets?
My jigs are quite thick (~0.5") in order to mask off the high filter
components on the solder side. As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual.
Any comment or advice?
Rgds,
Peter
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<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D194354114-28112001>May be=20
you need to look for different material for your jig so that the jig is =
thinner=20
and carry less heat. Also you probably need to build more jig to allow =
cool off=20
time before use it again.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D194354114-28112001>Regards</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DArial=20
color=3D#0000ff size=3D2></FONT><BR><BR><FONT face=3D"Courier New" =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: 'Courier New'">Date: =
Mon, 26=20
Nov 2001 23:44:19 -0800<BR>From: Peter Lee=20
<[log in to unmask]><BR>Subject: Wave soldeing jig=20
thickness<BR><BR>Hello,<BR><BR>Has anyone experienced problems with =
running=20
boards through wave<BR>soldering in a pallet with deep machined=20
pockets?<BR><BR>My jigs are quite thick (~0.5") in order to mask off =
the high=20
filter<BR>components on the solder side. As a result the jigs get =
very hot=20
after<BR>soldering and takes long time to cool down to be feed back =
to the=20
cycle.<BR>It also affects my profiling, throughput, and seems to =
create more=20
dross<BR>than usual.<BR><BR>Any comment or=20
=
advice?<BR><BR>Rgds,<BR>Peter</SPAN></FONT><o:p></o:p></DIV></BLOCKQUOTE=
></BODY></HTML>
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Date: Wed, 28 Nov 2001 10:05:16 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: BGA long term storage?
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Graham,
You should be aware of the following information relative to dry storage for
moisture-sensitive devices:
Contrary to popular belief, it is not safe to assume that all MSDs can be
stored in a dry cabinet for an extended period of time. Over time the
components will saturate to the ambient conditions inside the dry box (10%
RH is common) and this actually exceeds the critical level for many devices.
The level of risk and the time required to exceed the critical level are
directly related to the MS level and body thickness of the components and to
the RH level in the dry box.
To account for this situation, the IPC/JEDEC standard J-STD-033 is currently
being revised to include a limit of 90 days maximum of storage in a dry
cabinet. (I can send you a copy of the proposed revision if you want).
A better option for long term dry storage is to keep MSDs inside a dry bag
with desiccant and optionally to place this dry bag in a dry environment. Of
course the bags are not perfectly moisture-proof but they will offer a drier
environment than a standard dry box for a longer period of time. They are
designed to protect the components for a minimum of 12 months in a
non-condensing environment of <40C/90%RH. The drier the environment around
the bags the longer it will take before too much moisture gets inside. When
you open the bag, the Humidity Indicator Card (HIC) inside will indicate if
parts need to be baked before processing.
I am in the process of putting the finishing touch to a technical paper on
the subject of MSD dry storage that will be presented at the upcoming APEX
technical conference. I would be glad to send you a copy of this paper if
you are interested.
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
Date: Tue, 27 Nov 2001 07:02:57 -0500
From: Graham Collins <[log in to unmask]>
Subject: Re: BGA long term storage?
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. =
It's just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use =
(unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm =
thick document describing some experiments and results with it. Very =
interesting machine. Do you know if anything ever come of the work to =
produce a commercial (non-lab) version of this? Hmm... wonder what =
happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is =
the plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
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Date: Wed, 28 Nov 2001 09:32:36 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Heinz Mader <[log in to unmask]>
Subject: Adhesion problems of galvanic gold on electroless nickel gold
Hallo outthere in the big pcb world
A qestion from switzerland
We produce a board(material G 10) After full plating electroless nickel
gold the adhesion is good.Then we laminate fotoresist film for goldmask and
develope with soda.
We let plate the bond gold externel. This Gold has not enough adhesion
with tape test We see that not later not after Galvanic plating
Has anyone some experince solving that problem
With kind regards
Heinz Mader
Ascom AG
3000 Berne
Switzerland
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Date: Wed, 28 Nov 2001 10:57:17 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: Wave soldeing jig thickness
MIME-Version: 1.0
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In a message dated 11/27/2001 2:35:13 AM US Eastern Standard Time,
[log in to unmask] writes:
<< As a result the jigs get very hot after
soldering and takes long time to cool down to be feed back to the cycle.
It also affects my profiling, throughput, and seems to create more dross
than usual. >>
I have seen all of the effects you describe. I believe the dross increase is
due to a small amount of moisture absorption by the pallet material, but I
have never taken the steps to prove it out. The pallet will definitely make
a large difference in your profile. As for cooling, I think the idea already
suggested of a rack with fans will work best. You can also get conveyors or
buffers with built in fans, and even programmable to hold each pallet for a
set amount of time. Then you can profile the cool down time with your KIC or
whatever profiler, and get a good estimate for exactly how long to cool each
one before reusing. I don't recommend any kind of quenching or other forced
cooling with liquid.
Jon Moore
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Date: Wed, 28 Nov 2001 11:19:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Schaefer <[log in to unmask]>
Subject: Component Area Usage - Reality Check
Mime-Version: 1.0
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We are working on the early stages of a very densely populated design, and =
are looking at
area estimations. Is there any specification / rule of thumb which =
defines the maximum
component placement area usage (percentage or ratio)?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
1000 Waverley Street =20
Winnipeg, MB R3T 0P3 =20
--=_E5B8D1BA.F091DD76
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Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1>We are working on the early stages of a very =
densely=20
populated design, and are looking at</FONT></DIV>
<DIV><FONT size=3D1>area estimations. </FONT><FONT size=3D1>Is there =
any=20
specification / rule of thumb which defines the maximum</FONT></DIV>
<DIV><FONT size=3D1>component placement area usage (percentage or=20
ratio)?</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Thanks,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Dave=20
Schaefer &=
nbsp; &nbs=
p; =20
Voice: (204)478-8059<BR>Senior PCB=20
Designer &=
nbsp; =20
FAX: (204)942-3001<BR>Symbol=20
Technologies &nb=
sp; =20
Email: <A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
<BR>1000=20
Waverley=20
Street &nb=
sp; =20
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1></FONT> </DIV></BODY></HTML>
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Date: Wed, 28 Nov 2001 08:58:15 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brooks,Bill" <[log in to unmask]>
Subject: Re: Component Area Usage - Reality Check
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Hi David ,
In my opinion, this is not easily defined as a rule of thumb. Component
placement is limited by the machine that does the placement. The land area
and clearances must take into account the processes that need to be applied
to the components. IPC-SM-782 has recommendations for placement 'corrals' or
clearances. Many designers build this clearance into their cad footprints to
make it easier to prevent manufacturing problems on the pick and place
machines, and soldering machines. The minimums are rarely desirable, but
what you can get away with based on the volumes of boards you will make and
the tolerances you have allowed for your machines will affect the yields you
get on the manufacturing floor. Your manufacturing engineers will know more
about the limitations of the machines they have access to and what they can
get away with for clearances.... Sorry there is no silver bullet for this
problem. I would suggest you use the IPC spec as the worst case estimate for
component area and address the clearance issues when you get into the
design. Overlapping spaces can be accommodated by some machines in some axis
orientations under certain conditions... for example.
Just as a side note.... Back when I was hand taping artworks, I used to
estimate board area by figuring how many discrete components would fit into
a IC foot print and then applying that to a ratio of IC units per square
inch,,, I could be sure it was a tougher board if the IC units per square
in was in excess of 1/2 a sq. in. per IC unit ...(those were based on a 16
pin DIP package) or some other unreasonable amount.... Based on previous
design densities... The newer components can be deceiving in their apparent
real estate requirements, BGA's need more room to allow access to the parts
for removal or rework, for example... tolerances for fine pitch parts make
them more difficult to place, 0402 discrete are the size of a grain of
pepper... the machines that handle, test and rework these parts will define
your clearances for you... in the end. Diligent research will pay for itself
in the long run... with better yields and less rework on the manufacturing
floor. I hope this helps a little... :-)
Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask] <mailto:[log in to unmask]>
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/ <http://www.ipc.org/SanDiego/>
http://home.fda.net/bbrooks/pca/pca.htm
<http://home.fda.net/bbrooks/pca/pca.htm>
-----Original Message-----
From: David Schaefer [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 8:19 AM
To: [log in to unmask]
Subject: [TN] Component Area Usage - Reality Check
We are working on the early stages of a very densely populated design, and
are looking at
area estimations. Is there any specification / rule of thumb which defines
the maximum
component placement area usage (percentage or ratio)?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
<mailto:[log in to unmask]>
1000 Waverley Street
Winnipeg, MB R3T 0P3
------_=_NextPart_001_01C1782D.DEEBA090
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV><SPAN class=604512916-28112001><FONT size=1>Hi </FONT><FONT face=Tahoma
size=2>David , </FONT></SPAN></DIV>
<DIV><SPAN class=604512916-28112001><FONT face=Tahoma
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=604512916-28112001><FONT size=1>In my opinion, this is not
easily defined as a rule of thumb. Component placement is limited by the machine
that does the placement. The land area and clearances must take into account the
processes that need to be applied to the components. IPC-SM-782 has
recommendations for placement 'corrals' or clearances. Many designers build this
clearance into their cad footprints to make it easier to prevent manufacturing
problems on the pick and place machines, and soldering machines. The
minimums are rarely desirable, but what you can get away with based on the
volumes of boards you will make and the tolerances you have allowed for your
machines will affect the yields you get on the manufacturing floor. Your
manufacturing engineers will know more about the limitations of the machines
they have access to and what they can get away with for clearances.... Sorry
there is no silver bullet for this problem. I would suggest you use the IPC spec
as the worst case estimate for component area and address the clearance issues
when you get into the design. Overlapping spaces can be accommodated by some
machines in some axis orientations under certain conditions... for
example.</FONT></SPAN></DIV>
<DIV><SPAN class=604512916-28112001><FONT size=1>Just as a side note.... Back
when I was hand taping artworks, I used to estimate board area by figuring how
many discrete components would fit into a IC foot print and then applying
that to a ratio of IC units per square inch,,, I could be sure it was a
tougher board if the IC units per square in was in excess of 1/2 a sq. in. per
IC unit ...(those were based on a 16 pin DIP package) or some
other unreasonable amount.... Based on previous design densities... The
newer components can be deceiving in their apparent real estate requirements,
BGA's need more room to allow access to the parts for removal or rework, for
example... tolerances for fine pitch parts make them more difficult to place,
0402 discrete are the size of a grain of pepper... the machines that handle,
test and rework these parts will define your clearances for you... in the end.
</FONT></SPAN><SPAN class=604512916-28112001><FONT size=1>Diligent research will
pay for itself in the long run... with better yields and less rework on the
manufacturing floor. I hope this helps a little... </FONT></SPAN><SPAN
class=604512916-28112001><FONT size=1>:-)</FONT></SPAN></DIV>
<DIV><SPAN class=604512916-28112001><B><FONT face=Arial
size=5></FONT></B></SPAN> </DIV>
<DIV><SPAN class=604512916-28112001><B><FONT face=Arial size=5>Bill
Brooks</FONT><FONT face=Arial color=#000000
size=5><I><BR></I></FONT><I></I></B><I></I><FONT face=Arial size=2>PCB Design
Engineer , C.I.D.<BR><U></U></FONT><U><FONT face=Arial color=#0000ff
size=2>DATRON WORLD COMMUNICATIONS, INC</FONT></U><BR><FONT face=Arial
size=2>3030 Enterprise Court<BR>Vista, CA 92083<BR>Tel: (760)597-1500 Ext 3772
Fax: (760)597-1510<BR><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR>IPC Designers
Council, San Diego Chapter<BR><A href="http://www.ipc.org/SanDiego/"
target=_blank>http://www.ipc.org/SanDiego/</A><BR><A
href="http://home.fda.net/bbrooks/pca/pca.htm"
target=_blank>http://home.fda.net/bbrooks/pca/pca.htm</A></FONT> </DIV></SPAN>
<DIV><SPAN class=604512916-28112001><FONT size=1></FONT></SPAN> </DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> David Schaefer
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, November 28, 2001 8:19
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Component Area Usage
- Reality Check<BR><BR></FONT></DIV>
<DIV><FONT size=1>We are working on the early stages of a very densely
populated design, and are looking at</FONT></DIV>
<DIV><FONT size=1>area estimations. </FONT><FONT size=1>Is there any
specification / rule of thumb which defines the maximum</FONT></DIV>
<DIV><FONT size=1>component placement area usage (percentage or
ratio)?</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>Thanks,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1>Dave
Schaefer
Voice: (204)478-8059<BR>Senior PCB
Designer
FAX: (204)942-3001<BR>Symbol
Technologies
Email: <A href="mailto:[log in to unmask]">[log in to unmask]</A> <BR>1000
Waverley
Street
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=1></FONT> </DIV></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1782D.DEEBA090--
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Date: Wed, 28 Nov 2001 12:04:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Vandendolder, Ron" <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Heinz
A couple of ideas;
There may be a slight resist residue from the photoresist developing step
inhibiting adhesion.
A longer, warmer rinse may alleviate this problem followed by a quick
neutralizing dip in
10% HCL. Also a preclean/acid pickle and initial plating in a gold strike
tank with a below 7 ph will also help adhesion.
A quick experiment involving a stand alone coupon, that witnesses identical
processing as the board in one case and in the other case forgoes the
secondary photo-lamination with all other
variables the same (including time between initial electroless nickel/gold
and final gold plate, bakes, rinses,G10 material etc.) should help pin point
the problem....
Regards,
Ron VandenDolder
Product Development Manager
Telaxis Communications
SouthDeerfield, Ma 01375
413-665-8551
[log in to unmask]
-----Original Message-----
From: Heinz Mader [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 10:33 AM
To: [log in to unmask]
Subject: [TN] Adhesion problems of galvanic gold on electroless nickel
gold
Hallo outthere in the big pcb world
A qestion from switzerland
We produce a board(material G 10) After full plating electroless nickel
gold the adhesion is good.Then we laminate fotoresist film for goldmask and
develope with soda.
We let plate the bond gold externel. This Gold has not enough adhesion
with tape test We see that not later not after Galvanic plating
Has anyone some experince solving that problem
With kind regards
Heinz Mader
Ascom AG
3000 Berne
Switzerland
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Date: Wed, 28 Nov 2001 10:14:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Smith, Russell (US LA)" <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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----Thanks to everyone for the info , I was a weak on Cupric, (I spent
my life using mostly Ammonium and Ferric, amongst other more exotic
etches)=20
Any way one more simple or not so simple question :
Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?=20
Is It a correct assumption that somewhat lower N, and higher
copper would , provide faster etch rate. It just seems to me that
operating at an extreme N will basically just cost money in the form of
excess HCL usage , not to mention the wear and tear on the equipment,
and operators.,
Again thanks for the information!
Russell Smith
=09
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Date: Wed, 28 Nov 2001 13:33:16 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Need Help with 85-15 Altera QFPs
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Have not seen the problem you describe.
You're probably forming a solder alloy with your paste and the 85 Sn/15 Pb
on your Altera leads that has a different [most likely higher] liquidus
temperature than you expect or that is defined by your paste supplier's
recommended profile.
Run a profile on the Altera leads that are not soldering. Probably should
get to 240°C
Look here for solder materials properties
http://www.technicalmaterials.com/metal_prop/soldera.html
Dave Fish
----- Original Message -----
From: "Jorge Rodriguez" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 27, 2001 2:17 PM
Subject: [TN] Need Help with 85-15 Altera QFPs
> > Fellow Technetters:
> >
> > I am sending this looking for any help, I guess I've done
everything
> > as far as the process and I haven't been able to resolve the issue.
We've
> > been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> > finish on the leads. The solder doesn't flow properly and an acceptable
> > solder joint is not formed, the leads can be sometimes lifted with no
> > effort. The solder paste was checked after the screen printer operation
> > and it looked alright, the oven profile was also verified and it's
always
> > within the solder paste manufacturer's recommendations. This problem
seems
> > to be affecting all the different products with this type of component.
> > These part numbers are manufactured by Altera. Has anybody experienced
> > similar problems with QFPs from this manufacturer?, Does anybody have
> > recommendations as far as the reflow oven profile?. I read somewhere
that
> > this particular alloy has the liquidus temperature at 205 degrees, is
this
> > accurate?
> >
> Any help would be really appreciated
>
> > Jorge Rodriguez
> > Process Engineer
> > Varian Electronics Manufacturing
> > E-mail: [log in to unmask]
> >
>
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Date: Thu, 29 Nov 2001 07:59:57 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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Date: Wed, 28 Nov 2001 10:54:40 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Mazzoli <[log in to unmask]>
Subject: Re: Cu CL etcher
In-Reply-To: <[log in to unmask]
rp.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hi Russ,
I used to run about 1.3-1.5N and about 165g/l Cu with an ORP of 550-580 or
so. It would seem to me that the parameters you listed would lead to a
very fast but somewhat less precise etchant. You may experience undercut
and/or poor conductor edge quality. And you're right about potential
equipment problems, particularly titanium shafts, nuts, bolts, etc. But it
would be fast......... If you're working with 1/4 ounce copper you may want
to stand back a few feet to catch the layers as they fly off.....
Check with Mr. Sedlak..... he is The Man for cupric questions.
Mark
At 10:14 AM 11/28/01 -0800, you wrote:
>----Thanks to everyone for the info , I was a weak on Cupric, (I spent
>my life using mostly Ammonium and Ferric, amongst other more exotic
>etches)
>
>Any way one more simple or not so simple question :
>
> Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?
>
> Is It a correct assumption that somewhat lower N, and higher
>copper would , provide faster etch rate. It just seems to me that
>operating at an extreme N will basically just cost money in the form of
>excess HCL usage , not to mention the wear and tear on the equipment,
>and operators.,
>
>
>Again thanks for the information!
>
>Russell Smith
>
>
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Date: Wed, 28 Nov 2001 15:33:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward H. Uslar" <[log in to unmask]>
Subject: FW: Autocad to Solidworks
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
> Does anyone know how to import an AutoCAD *.dwg or *.dxf file into
> Solidworks?
>
Thanks,
Ed
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Date: Wed, 28 Nov 2001 13:27:44 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Igor Bjekic <[log in to unmask]>
Subject: Re: Organic Silver PCB's
Question is what type of the flux you are using?
What is the activation temperature and what is required soaking time for the
flux that you are using?
The flux's that I am working with activates at 190 but not to exceed
210F(88-99C) and 210 not to exceed 230F (99-110C). My soaking goal is
minimum 10 seconds.
As much I am able to see from your description, it appears to me that you
are overheating assembly and burning off flux before your board hits the
wave's.
Thank you,
Igor . . .
-----Original Message-----
From: Michael Bell [SMTP:[log in to unmask]]
Sent: Wednesday, November 28, 2001 12:00 PM
To: [log in to unmask]
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H)
of some
RF Organic Silver PCB's we are currently making. Every attempt to
improve
the solderability has had no impact. The soldered PCB's show very
poor
wetting, partial joints and in some areas there is no evidence of
solder.
The PCB is curretly being pre-heated to around 160 deg. C topside
and a bath
temperature of 256 deg. C. Is there something I am over looking
with the
Organic Silver? Is there any special method/ or profile for Organic
SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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Date: Wed, 28 Nov 2001 13:28:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Igor Bjekic <[log in to unmask]>
Subject: Re: Organic Silver PCB's
Question is what type of the flux you are using?
What is the activation temperature and what is required soaking time
for the flux that you are using?
The flux's that I am working with activates at 190 but not to exceed
210F(88-99C) and 210 not to exceed 230F (99-110C). My soaking goal is
minimum 10 seconds.
As much I am able to see from your description, it appears to me
that you are overheating assembly and burning off flux before your board
hits the wave's.
Thank you,
Igor . . .
-----Original Message-----
From: Michael Bell [SMTP:[log in to unmask]]
Sent: Wednesday, November 28, 2001 12:00 PM
To: [log in to unmask]
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the
solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every
attempt to improve
the solderability has had no impact. The soldered PCB's
show very poor
wetting, partial joints and in some areas there is no
evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C
topside and a bath
temperature of 256 deg. C. Is there something I am over
looking with the
Organic Silver? Is there any special method/ or profile for
Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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Date: Wed, 28 Nov 2001 15:44:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Decray <[log in to unmask]>
Subject: Re: FW: Autocad to Solidworks
In-Reply-To: <B17D7B877D07D211AA1D0008C76C52DA05CF8F@COMPAQSR>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
yes Ed Give me a call
*GOD BLESS AMERICA*
William W. DeCray III
Waytec Electronics Corp
CAD/CAM & Engineering Services Manager
PHONE:(434) 237-6391 ext 115
CELL: (804) 851-6115
FAX: (434) 237-1324
E-mail:<[log in to unmask]>
Web http://www.waytec.com <http://www.waytec.com/>
FTP ftp://ftp.waytec.com <ftp://ftp.waytec.com/>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Edward H. Uslar
Sent: Wednesday, November 28, 2001 3:34 PM
To: [log in to unmask]
Subject: [TN] FW: Autocad to Solidworks
> Does anyone know how to import an AutoCAD *.dwg or *.dxf file into
> Solidworks?
>
Thanks,
Ed
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Date: Wed, 28 Nov 2001 15:51:07 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Heinz:
It is almost certain that some residue is on the surface, which is causing
the non-adherent Gold.
Please review the process again....you are putting galvanic Gold (I think it
is more commonly called "immersion gold") on to electroless Nickel, long
after the electroless Nickel has been plated?
If this is the case, this pretty well explains it right there. Electroless
Nickel set up one of the more passive oxide films known, and if you do not go
directly from the Nickel plating tank to the Gold tank, you are asking for
almost exactly what you are getting.
You will have to do drastic things, consider even a brief gold/nickel
stripper, to reactivate the Nickel enough to give you adherent Gold plating.
If I am understanding this correctly, and you are applying dryfilm to the
electroless Nickel, (heat and time = very passive oxide finish on the
Nickel), you may be facing an very difficult activation process to get the
Gold to adhere.
Rudy Sedlak
RD Chemical Company
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Date: Wed, 28 Nov 2001 15:56:25 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Thanks to Mark M for the compliment.
Generally, the lower the acid, the better the "etch ratio", or the less the
"undercut", and the slower the etch....
The higher the Copper, the faster the etch.
And, yes, Mark is right, high acid can lead to attack on Titanium.
And in the US, the cost of the HCl is a trivial part of the cost of the etch,
the oxidizer (Peroxide, or Chlorate) is the costly part, so that should
really not be the deciding factor.
Rudy Sedlak
RD Chemical Company
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Date: Thu, 29 Nov 2001 07:47:57 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA long term storage?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
How about our afvourite IMC's building up within the component -
ball/component interface for example? Will that affect long term
reliability/solderabity after a long period of storage?
Just thought I'ld throw that one into the pot.
Peter Duncan
"d. terstegge"
<[log in to unmask] To: [log in to unmask]
GROUP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: Re: [TN] BGA long term storage?
11/28/01 07:08 PM
Please respond to
"TechNet E-Mail Forum."
Hmmm, seems I'm the only one who adviced not to worry about long term
storage of BGA's. I must admit that I never stored a BGA for 10 years to
see how it solders, but I really don't expect the solderability to decrease
to such an extend that the balls will not solder anymore.
According to Klein Wassink the oxidation layer on solder will grow
approximately logarithmically with time, resulting in about 6nm after 20
years which is just twice as thick as after one year !
So my question is: are nitrogen cabinets, ROSA-technology or redesigns
REALLY necesarry ?
Maybe one of the metallurgists on this forum can add a few words ?
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Graham Collins <[log in to unmask]> 11/27 1:02 pm >>>
Hi Doug!
Indeed - not a new problem - and one we have faced on other programs. It's
just the BGAs that are new to us for this problem.
Nitrogen storage is available here and I expect that's what we will use
(unless some other TechNet guru has a better idea!).
I've heard of ROSA, and in fact Dave was kind enough to send me a 35mm
thick document describing some experiments and results with it. Very
interesting machine. Do you know if anything ever come of the work to
produce a commercial (non-lab) version of this? Hmm... wonder what
happened to Bev's?
Anyway - thanks to everyone for the responses. Nitrogen storage was/is the
plan, but it is always good to have a sanity check with some experts.
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/26/01 04:11PM >>>
The issue of long term storage of parts or boards is not a new one. The
military, faced with REALLY long lifetimes (e.g. 50 years for a MX missile)
and decreaseing market clout, has had to deal with lifetime buys for a long
time. In my mind, there are two possibilities: (1) preserve the original
solderability for as long as possible, or (2) plan on restoring the
solderability at some point in the future when the part is needed.
In the first case, you will have to setup some fairly elaborate storage
conditions where oxygen and moisture are excluded. Dry nitrogen is most
common, but alternatives could include dessicated conditions or coverage
with a heavy noble gas like argon. You will have to setup incoming and
outgoing logs that tightly control the inventory, and you have to have
floor space for the storage for the life span of the part.
In the second case, you restore the solderable surface. Some people do
this using aggressive fluxes and re-tinning, with limited success. An
alternative to this is to use an electrochemical reduction process called
ROSA to change the surface oxides to the base metal, restoring
solderability. ROSA can be done on many parts at the same time, it is
electroless, and is not too capital intensive. Dave Hillman of Rockwell is
the master of ROSA and has published a number of papers on the topic. He
would probably answer more fully but he is currently putting the finishing
touches on his Master's thesis and so won't stick his head out of his
cubicle for another few days. And when he does, if he sees his shadow,
there will be 5 more months of winter (in Iowa, that's a safe bet). Where
was I?
The advantage of the ROSA approach is that it does not matter all that much
what the solderability condition was when the part was received, and the
storage conditions do not have to be draconian.
As the commercial goes, you can pay me now or pay me later.....
Doug Pauls
Rockwell Collins
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Date: Wed, 28 Nov 2001 17:50:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Mike! Please give us a description of "organic" silver. Are you talking
about one of the three immersion silver pwb finishes currently found in the
industry?
Dave Hillman
Rockwell Collins
[log in to unmask]
Michael Bell <[log in to unmask]>@ipc.org> on 11/29/2001 01:59:57 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of
some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a
bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
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Date: Wed, 28 Nov 2001 17:56:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Need Help with 85-15 Altera QFPs
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Jorge! An 85Sn/15Pb solder alloy has a melting (pasty) range of 183C -
209C. Have you checked the solderability of the QFP leads? An 85Sn/15Pb
solder alloy is going to be more prone to having oxidation problems because
of the higher Sn content. Are other components on the same assembly having
similar problems or do you get acceptable solder joints? If the other
components are ok I would investigate the QFP solderability using the
JSTD-002A specification. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Jorge Rodriguez <[log in to unmask]>@ipc.org> on 11/27/2001
04:17:09 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Need Help with 85-15 Altera QFPs
> Fellow Technetters:
>
> I am sending this looking for any help, I guess I've done
everything
> as far as the process and I haven't been able to resolve the issue. We've
> been having soldering problems for a while with QFPs with 85 Sn/15 Pb
> finish on the leads. The solder doesn't flow properly and an acceptable
> solder joint is not formed, the leads can be sometimes lifted with no
> effort. The solder paste was checked after the screen printer operation
> and it looked alright, the oven profile was also verified and it's always
> within the solder paste manufacturer's recommendations. This problem
seems
> to be affecting all the different products with this type of component.
> These part numbers are manufactured by Altera. Has anybody experienced
> similar problems with QFPs from this manufacturer?, Does anybody have
> recommendations as far as the reflow oven profile?. I read somewhere that
> this particular alloy has the liquidus temperature at 205 degrees, is
this
> accurate?
>
Any help would be really appreciated
> Jorge Rodriguez
> Process Engineer
> Varian Electronics Manufacturing
> E-mail: [log in to unmask]
>
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Date: Wed, 28 Nov 2001 18:15:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Thanks Everyone: Re: [TN] Looking for Information
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi folks! Just a quick thanks to everyone for the Altos contact info. I was
able to obtain the information I needed in record time.
Dave Hillman
Rockwell Collins
[log in to unmask]
"Stephen R. Gregory" <[log in to unmask]>@ipc.org> on 11/26/2001 05:30:45 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
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cc:
Subject: Re: [TN] Looking for Information
Hi Dave!
Wasn't able to find anything on Altos Engineering directly, but found what
I think is a rep firm that offers the Altos Engineering Thermal Vacuum
Drying ovens. You might want to contact them to get a contact directly at
Altos. Go to:
http://www.sicoast.com/companies.html
-Steve Gregory-
Hi folks! I'm looking for contact information for Altos Engineering and
their TVP Baking process - anyone have a good email or phone number? Also -
anyone using the TVP Baking process and could share their experiences with
it?
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Wed, 28 Nov 2001 19:56:39 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Ahem, Sir Dave:
How many immersion Silver systems did you say there were?
Ever heard of SilveR ShielD?
Do the capitolized last letters of the name give you a hint?
Rudy Sedlak
RD Chemical Company
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Date: Wed, 28 Nov 2001 17:47:33 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Flexible PC Board
MIME-Version: 1.0
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Howdy All,
I am new to this list and I thank the folks at 3M's
Microflex division for pointing me here. Y'all can blame
them later after reading this lengthily post...
The acceptance of my lousy prototype was excellent, so I was
looking at ideas for a more robust and fine-tuned design
using a flexible circuit.
I need a flexible PC board operating at 12v DC. Size is
about 1/2" x 6" or 8". The mounting is static, but the
flexible shape is required because of the variety of
mountings. Also, the outdoor environment will be greasy,
dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
needs to be durable. There will be no direct abrasives.
The board and protection should be no more than about
2/10ths thick.
Is there something like that out there? You've probably
seen that "soft-touch" switch rubber used on keypads. A
slightly firmer version of that with copper cladding (or
something to etch) would be about perfect, as long as it's
tough stuff.
Thanks in advance and I appreciate your guidance.
- Scott
(775) 849-2030
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Date: Wed, 28 Nov 2001 19:24:21 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
Mime-Version: 1.0
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I've seen what I think is a similar problem. I'll describe it and how I
cured it and see if it will help you.
Problem: 50% of surface pads wetted on ENIG surfaces at customer location.
Research: LPI coated panels were ENIG plated. Found peeling LPI and panels
were stripped in an alkaline solution and then LPI reapplied. Suspected that
the alkaline stripping solution or the LPI developer solution (potassium
carbonate ?) had somehow remained on the immersion gold surface.
Cure: After panels are recoated with LPI they must be processed in a hot
alkaline cleaner(cleaner on our black oxide process)then rinsed well and
100% wetting was restored.
Theory: Alkaline contamination was not rinsed from either the stripper or
the developer and ruined the gold surface for solderability. On the chemical
principal that likes-dissolve-likes the hot alkaline cleaner removed this
contaminant and with proper rinsing no residueS remained.
I hope this is helpful.
Russ Burdick
>From: Heinz Mader <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] Adhesion problems of galvanic gold on electroless nickel gold
>Date: Wed, 28 Nov 2001 09:32:36 -0600
>
>Hallo outthere in the big pcb world
>A qestion from switzerland
>We produce a board(material G 10) After full plating electroless nickel
>gold the adhesion is good.Then we laminate fotoresist film for goldmask and
>develope with soda.
>We let plate the bond gold externel. This Gold has not enough adhesion
>with tape test We see that not later not after Galvanic plating
>
>Has anyone some experince solving that problem
>
>
>With kind regards
>
>Heinz Mader
>Ascom AG
>3000 Berne
>Switzerland
>
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Date: Thu, 29 Nov 2001 07:53:57 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Atkinson, Neil" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have always seen fairly good wetting of immersion silver PCBs and whilst
they may not be as good as HASL this is usually only evident on the lack of
wetting to the outer edges of lands on the topside of PTH boards and less
fill on larger hole sizes. I have certainly never seen anything like you
are describing.
My first question would be what flux are you using? 160degC topside
temperature after preheat sounds very hot (regardless of finish) and it may
be that a problem with your profile is more evident on the immersion silver
boards.
Regards,
Neil Atkinson
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: 28 November 2001 19:00
Subject: Organic Silver PCB's
Hi there Technetters,
I have now exhausted my efforts of improving the solderability (T/H) of some
RF Organic Silver PCB's we are currently making. Every attempt to improve
the solderability has had no impact. The soldered PCB's show very poor
wetting, partial joints and in some areas there is no evidence of solder.
The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
temperature of 256 deg. C. Is there something I am over looking with the
Organic Silver? Is there any special method/ or profile for Organic SIlver
finished PCB's??? Any feedback would be appreciated.
Cheers
Mike
_____________________________________________________________________
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Date: Thu, 29 Nov 2001 03:16:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Heinz Mader <[log in to unmask]>
Subject: Re: Adhesion problems of galvanic gold on electroless nickel gold
X-To: "<Rudy Sedlak>" <[log in to unmask]>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
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Rudy
I must say ,that we make full ENIG (electroless Nickel-with immersion
gold).Then after laminating and developing dry-film-resist there comes the
galvanic (electrolycal gold) from about 3 =B5m Au)
Heinz Mader
Ascom AG
300 Berne
Switzerland
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Date: Thu, 29 Nov 2001 10:42:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Re: Fiducial Markings - do they mean anything?
X-To: [log in to unmask]
Mime-Version: 1.0
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Peter,
Use the type that your equipments' vision system prefers. Just for info we
use diamonds (well, 1mm squares turned at 45 deg. actually). Something else
to bear in mind is surface finish and contrast with the surrounding
background. If using HASL make sure your PCB supplier can give a relatively
flat finish. If excessively applied you end up with a 'domed' effect and the
vision system may have difficulty with that as the greyscale values will
vary as the illumination is reflected all over the place (I've had no end of
trouble with this!). Also leave a nice big clearance in your resist if you
can. In the end, give your equipment as much chance as possible to recognise
the marks, whatever the preferred shape.
From what you say you are somewhat hamstrung by what your customer has
designed in. Try to exert some influence on their designers if you can. It
works wonders in the longer run.
Best regards,
===== Original Message from [log in to unmask] at 28/11/01 11:23
>Hot on the heels of the smelly paste saga (some of the new ones that you
>turned up are great - we haven't come off the ceiling yet).
>
>Fiducials - just a quick survey (and Bob you may already have posted
>something similar so apologies if the answer is staring me in the face). We
>don't use them - yet - as most stuff here is hand placed but as we venture
>into the twilight zone of automated production I am starting to take an
>interest in them. Up to now they were just pretty little signs that we
>thought were ancient runic inscriptions from the days of the early Viking
>coastal raids - Ericsson the Mobile and Nokia the Trendy being just two
>names that have come forward.
>
>Question is - what is the most popular - I would have said that crosses were
>the most common but I looked back over several boards from different places
>and found circles and the occasional butterfly were more common than I
>thought.
>
>As the machine we have in mind (yes its an old one) doesn't like crosses we
>would prefer circles but we mostly have to smile sweetly and say thank you
>for whatever we get. So what does everyone else use? And given the chance,
>would you use a different shape?
>
>regards
>
>Peter Allgood
>
>Allgood Technology Ltd, 1 Horton Court, Hortonwood 50, Telford, TF1 7GY
>Tel and Fax 01952 677145 Web: www.allgoodsmt.com
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Date: Thu, 29 Nov 2001 11:10:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Apologies
Mime-Version: 1.0
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Please ignore message sent re: Fiducials. I inadvertently sent this to the
wrong discussion forum.
Apologies for any inconvenience caused.
Regards,
PEter Barton
Peter Barton
Senior Process Engineer
ACW Technology Limited
Tel: 01443 425275
Fax: 01443 436882
E-mail [log in to unmask]
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Date: Thu, 29 Nov 2001 11:35:00 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: (none)
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Mike,
I have used immersion silver (Alpha Level) at times in the past using the
same temperature profile as for HASL finished boards and had good wetting at
both bottom and topside. Are you subjecting this assembly to any surface
mount processes before wave soldering? Multiple processing of this type of
finish can progressively degrade the solderability at each stage but you'd
have to be pretty aggressive.
What is the state of the unpopulated PCB's? Is the finish bright or dull
with black or dark areas on the solderable surfaces? What is the finish
called?
Also,like other responses on this forum your preheat temperature seems
excessively high, even if you were using a water based VOC free flux you'd
only need a max. of around 110-115 deg. C topside. What flux are you using?
Regards
Peter Barton
ACW Technology Limited
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
28/11/01 18:59
>Hi there Technetters,
>
>I have now exhausted my efforts of improving the solderability (T/H) of some
>RF Organic Silver PCB's we are currently making. Every attempt to improve
>the solderability has had no impact. The soldered PCB's show very poor
>wetting, partial joints and in some areas there is no evidence of solder.
>The PCB is curretly being pre-heated to around 160 deg. C topside and a bath
>temperature of 256 deg. C. Is there something I am over looking with the
>Organic Silver? Is there any special method/ or profile for Organic SIlver
>finished PCB's??? Any feedback would be appreciated.
>
>Cheers
>
>Mike
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Date: Thu, 29 Nov 2001 08:43:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Cu CL etcher
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Russell,
I've run a VCM etcher at upwards of 2 N (our target had always been 1 N) but
we had to - long lead-time on a replacement metering pump and a shorter
delivery date. The operators asked, "How come we can do it at 2 N all of a
sudden?" My quick answer was "You've got to pick some number to run it at
and this one minimized process variation" but I'm glad to learn a better
answer. I'm always learning something new from the list.
Thanks guys!
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Smith, Russell (US LA) [mailto:[log in to unmask]]
Sent: Wednesday, November 28, 2001 1:15 PM
To: [log in to unmask]
Subject: Re: [TN] Cu CL etcher
----Thanks to everyone for the info , I was a weak on Cupric, (I spent
my life using mostly Ammonium and Ferric, amongst other more exotic
etches)
Any way one more simple or not so simple question :
Would you run a Cupric etcher @ 140g/l Cu and 5N HCl .?
Is It a correct assumption that somewhat lower N, and higher
copper would , provide faster etch rate. It just seems to me that
operating at an extreme N will basically just cost money in the form of
excess HCL usage , not to mention the wear and tear on the equipment,
and operators.,
Again thanks for the information!
Russell Smith
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Date: Thu, 29 Nov 2001 07:08:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: Wave Solder Profiling
MIME-Version: 1.0
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Good morning Technetters.
Is there anyone that could provide some good advise on Wave solder
profiling. I am not sure
of what kind of parameters to try to maintain. I really would be interested
in any documentation
that would break down min/max preheat temps vs. times etc. Dwell times on
the pot and so
forth.
all help will be greatly appreciated.
Thank you in advance.
Barry Gallegos
Process Engineer
Western Electronics
1550 South Tech Lane
Meridian, Idaho 83642
Phone: 208/955-9771
Fax: 208/955-9755
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Date: Thu, 29 Nov 2001 08:32:03 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Organic Silver PCB's
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Hi Rudy! Sorry, I was just thinking about the three immersion silver
finishes I have worked with - you are correct, there are several other
immersion silver finishes available on the market. My big confusion was the
term "organic" silver - is there two types of immersion silver finishes:
organic versus metallic? Or is the use of the term "organic" describing
some of the codeposited constituents of an immersion silver finish?
Dave Hillman
Rockwell Collins
[log in to unmask]
"<Rudy Sedlak>" <[log in to unmask]>@ipc.org> on 11/28/2001 06:56:39 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Organic Silver PCB's
Ahem, Sir Dave:
How many immersion Silver systems did you say there were?
Ever heard of SilveR ShielD?
Do the capitolized last letters of the name give you a hint?
Rudy Sedlak
RD Chemical Company
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Date: Thu, 29 Nov 2001 08:32:28 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Barry Gallegos <[log in to unmask]>
Barry,
You, me, and everyone else knows I've no business contributing to this
discussion and your question. Well, just so happens, I have little else to
do at this moment. Also, I love wave soldering because it is so, how shall I
say it, mechanical and straightforward. My problems is a lack of any type
understanding about IMC stuff. No matter1
You know the mechanisms as flux type and quality/composition, activation
temperature, preheater temperature required to ensure the top side board
temperature is properly reached as an indication of flux activation as
specified, conveyor speed relateive to the foregoing and its relationship to
dwell time on the solder pot, board parallelism on the wave, angle on the
wave, and all the rest.
I like wave soldering because all the above must be interoperable and
correlate with each function, mechanism, time, and chemistry in the whole
process. I call each function, again as above, sub-processes because that's
what they are. Each sub-process must be managed independently and
associatively for the "whole" process to work. If it works, solder joints
meet specified requirements. If it, or any one of the "independent"
sub-processes, don't work, solder joints suck.
To your original question, I make a matrix including all the above
parameters and include the board thermal mass (single, double, MLB, etc.)
and go out and measure each function in each sub-process in the process and
see what happens.
Most new/automatic machines as Electras and the like have computerized
matrices included. However, I always "calibrate" the automated sub-processes
and ensure they meet specified requirements.
Anyway, the process is cool though being pushed to the limits with very high
layer count MLB's with incredibly high thermal masses. Simpler 12 layer
boards used to run at predetermined speed between 3-6 feet/minute and you
could set your watch by it. Now, with some of the 40 and 50 plus layer
boards I, and some of you, have been working, speeds are much slower and
flux often is very active. You can imaging the preheat temps with some of
these things and no IPC through hole acceptance criteria comes close to reality.
And on it goes. Life and the wave soldering process is a continuing
experiment with CPI as its goal - though not often enough realized.
MoonMan
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Date: Thu, 29 Nov 2001 10:00:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tech <[log in to unmask]>
Subject: Dielectric constant vs degree of cure , FR4
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Does the dielectric constant ( and resultant impedance results) of FR4
vary with degree of cure of the resin system ? I.e can multi layer press
parameters influence finished board impedances ? Any info. will be
appreciated.
Paul Greene
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Date: Thu, 29 Nov 2001 09:09:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
X-To: Paul Greene <[log in to unmask]>
DC calculations are made for core material as such. This means the DC does
not change for it in whatever MLB structure.
For prepregs, DC is calculated based on expected effects after cure in the
press - in the book - in the MLB. Variations are minor, within but a percent
or two, for the same glass styles and resin contents used in the structures.
"Good" board shops will provide pre-calculated DC numbers both for core and
prepregs used. Still, the numbers vary minimally and your overall impedance
will be little affected. However, for very high speed stuff, this can be
critical though little FR4 is used in these designs. You can then calculate
the requirements based on DC, thickness, trace widths (for differential
pairs as stripline [boradside and edge rate requirements] and microstrip
requirements).
MoonMan
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Date: Thu, 29 Nov 2001 15:08:20 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Solder Resist and QFP's
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From a fabricator viewpoint, there are one or two things to bear in mind.
Firstly the accuracy of print registration will at best be +/-50um (+/-
2mil) if your fab house uses automatic registration, secondly, the minimum
'web' width that will remain through subsequent processing is about 85um
(2.5 mil) AT THE BOARD SOLDERMASK INTERFACE - this is important because
most masks will be undercut during developing, and may require an artwork
width of 6mils to achieve the web. Add these two factors together, and this
means the only chance of getting a web between pads is if the gap between
pads is 10mils minimum. If your QFP is on a 20 mil pitch (actually 19.6
mil), the pad width will have to be designed at 8 mil (there is an etch
tolerance and you need to understand that the top of the pad and bottom of
the pad will be different widths - which do you specify?). Now most
designers with a 12mil gap will want to run a 4/4 track and gap in there -
now you have soldermask covering the track and the soldermask height is
over the track and therefore the soldermask MUST BE HIGHER than the pad you
wish to solder to. This will create a problem with solder pasting, so the
answer is don't run tracks between these pads if you want to have high
assembly yields.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Furrow, Robert Gordon (Bob) [SMTP:[log in to unmask]]
Sent: 28 November 2001 13:27
To: [log in to unmask]
Subject: Re: [TN] Solder Resist and QFP's
Mike,
I think that a good board shop should be able to avoid contaminating the
pad
surface with resist. The larger concern I would have is if in any areas the
solder resist height is above the surface of the pad, your stencil will not
gasket properly and you can actually increase the number of shorts.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Michael Bell [mailto:[log in to unmask]]
Sent: Tuesday, November 27, 2001 5:15 PM
To: [log in to unmask]
Subject: [TN] Solder Resist and QFP's
Hi all,
What are peoples thoughts on solder resist between fine pitch micro pads???
I have recently heard two differing theories regarding this matter, one is
that solder resist between the pads on some very fine pitch QFP's will
reduce the risk of solder shorts. The other theory was that with solder
resist between these pads you could risk getting the resist onto the pads
and reducing the soldering surface??? What is the general consensus on
this
matter??? Which approach to others take on this matter?
Cheers
Mike
<< File: ATT00000.htm >>
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Date: Thu, 29 Nov 2001 09:29:00 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen S. Schiera" <[log in to unmask]>
Subject: Color additives for conformal coat
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I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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Date: Thu, 29 Nov 2001 07:58:24 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Flexible PC Board
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Scott,
2/10s of a mil? Like .0002"? You need a dielectric to hold the conductor and I don't think
you will find anything that thin. We work with thinner materials than most and we make a
number or parts on .0005" polyimide with 3 microns of copper. If anyone has anything less
than that I would like to talk to them.
Chuck Brummer
Acuson (818)734-4930
"Scott R. Madans" wrote:
> Howdy All,
>
> I am new to this list and I thank the folks at 3M's
> Microflex division for pointing me here. Y'all can blame
> them later after reading this lengthily post...
>
> The acceptance of my lousy prototype was excellent, so I was
> looking at ideas for a more robust and fine-tuned design
> using a flexible circuit.
>
> I need a flexible PC board operating at 12v DC. Size is
> about 1/2" x 6" or 8". The mounting is static, but the
> flexible shape is required because of the variety of
> mountings. Also, the outdoor environment will be greasy,
> dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
> needs to be durable. There will be no direct abrasives.
> The board and protection should be no more than about
> 2/10ths thick.
>
> Is there something like that out there? You've probably
> seen that "soft-touch" switch rubber used on keypads. A
> slightly firmer version of that with copper cladding (or
> something to etch) would be about perfect, as long as it's
> tough stuff.
>
> Thanks in advance and I appreciate your guidance.
>
> - Scott
> (775) 849-2030
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Thu, 29 Nov 2001 08:08:58 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Sorry, the world of mils and microns is new to me. It is
0.2 inches!
- Scott
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
Brummer
Sent: Thursday, November 29, 2001 07:58 AM
To: [log in to unmask]
Subject: Re: [TN] Flexible PC Board
Scott,
2/10s of a mil? Like .0002"? You need a dielectric to hold
the conductor and I don't think
you will find anything that thin. We work with thinner
materials than most and we make a
number or parts on .0005" polyimide with 3 microns of
copper. If anyone has anything less
than that I would like to talk to them.
Chuck Brummer
Acuson (818)734-4930
"Scott R. Madans" wrote:
> Howdy All,
>
> I am new to this list and I thank the folks at 3M's
> Microflex division for pointing me here. Y'all can blame
> them later after reading this lengthily post...
>
> The acceptance of my lousy prototype was excellent, so I
was
> looking at ideas for a more robust and fine-tuned design
> using a flexible circuit.
>
> I need a flexible PC board operating at 12v DC. Size is
> about 1/2" x 6" or 8". The mounting is static, but the
> flexible shape is required because of the variety of
> mountings. Also, the outdoor environment will be greasy,
> dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
it
> needs to be durable. There will be no direct abrasives.
> The board and protection should be no more than about
> 2/10ths thick.
>
> Is there something like that out there? You've probably
> seen that "soft-touch" switch rubber used on keypads. A
> slightly firmer version of that with copper cladding (or
> something to etch) would be about perfect, as long as it's
> tough stuff.
>
> Thanks in advance and I appreciate your guidance.
>
> - Scott
> (775) 849-2030
>
> ----------------------------------------------------------
-----------------------
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LISTSERV 1.8d
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> Please visit IPC web site
(http://www.ipc.org/html/forum.htm) for additional
> information, or contact Keach Sasamori at [log in to unmask]
or 847-509-9700 ext.5315
> ----------------------------------------------------------
-----------------------
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Date: Thu, 29 Nov 2001 08:25:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Flexible PC Board
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Scott,
0.2 inches is not going to be very flexible. There are other options like rigid flex,
circuits that are polyimide glass at the ends but have a flex conection. Can you tell us more
about your needs. How many layers, what weight of copper, conductor requirements
(line/space)? Maybe someone has some other ideas for you.
Chuck Brummer
"Scott R. Madans" wrote:
> Sorry, the world of mils and microns is new to me. It is
> 0.2 inches!
>
> - Scott
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
> Brummer
> Sent: Thursday, November 29, 2001 07:58 AM
> To: [log in to unmask]
> Subject: Re: [TN] Flexible PC Board
>
> Scott,
>
> 2/10s of a mil? Like .0002"? You need a dielectric to hold
> the conductor and I don't think
> you will find anything that thin. We work with thinner
> materials than most and we make a
> number or parts on .0005" polyimide with 3 microns of
> copper. If anyone has anything less
> than that I would like to talk to them.
>
> Chuck Brummer
> Acuson (818)734-4930
>
> "Scott R. Madans" wrote:
>
> > Howdy All,
> >
> > I am new to this list and I thank the folks at 3M's
> > Microflex division for pointing me here. Y'all can blame
> > them later after reading this lengthily post...
> >
> > The acceptance of my lousy prototype was excellent, so I
> was
> > looking at ideas for a more robust and fine-tuned design
> > using a flexible circuit.
> >
> > I need a flexible PC board operating at 12v DC. Size is
> > about 1/2" x 6" or 8". The mounting is static, but the
> > flexible shape is required because of the variety of
> > mountings. Also, the outdoor environment will be greasy,
> > dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
> it
> > needs to be durable. There will be no direct abrasives.
> > The board and protection should be no more than about
> > 2/10ths thick.
> >
> > Is there something like that out there? You've probably
> > seen that "soft-touch" switch rubber used on keypads. A
> > slightly firmer version of that with copper cladding (or
> > something to etch) would be about perfect, as long as it's
> > tough stuff.
> >
> > Thanks in advance and I appreciate your guidance.
> >
> > - Scott
> > (775) 849-2030
> >
> > ----------------------------------------------------------
> -----------------------
> > Technet Mail List provided as a free service by IPC using
> LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with
> following text in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send the following
> message: SET Technet NOMAIL
> > Search previous postings at: www.ipc.org > On-Line
> Resources & Databases > E-mail Archives
> > Please visit IPC web site
> (http://www.ipc.org/html/forum.htm) for additional
> > information, or contact Keach Sasamori at [log in to unmask]
> or 847-509-9700 ext.5315
> > ----------------------------------------------------------
> -----------------------
>
> ------------------------------------------------------------
> ---------------------
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> ------------------------------------------------------------
> ---------------------
>
> ---------------------------------------------------------------------------------
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Date: Thu, 29 Nov 2001 11:39:48 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
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FR4 will not change Er due to cure temp at fabrication, however the press
cycle may. Total dielectric constant (Er) is a function of the main
ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the
Eglass content the higher resultant Er. Hence, any "above normal" squeeze
out of resin will have the propensity to increase resultant Er for B-stage,
C-stage is a little different. I say "propensity" for the Er is estimating
averages and empiric data that over time develops a heritage of dependable
predictability. Sameness is good.
Copper thickness may be a culprit if impedance are varying. >.0007 and edges
can start getting ragged. I introduce this relative to fixed cycles of press
times and the amount of field support for dielectric materials. Copper
etching may be more subjective and susceptible to OE (Operator Error). Given
that the fabrication is repeatable, which it is, deliverable impedance can go
significantly below the standard +/-10%, otherwise we couldn't deliver 25 ohm
boards.
Brad
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>FR4 will not change Er due to cure temp at fabrication, however the press cycle may. Total dielectric constant (Er) is a function of the main ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the Eglass content the higher resultant Er. Hence, any "above normal" squeeze out of resin will have the propensity to increase resultant Er for B-stage, C-stage is a little different. I say "propensity" for the Er is estimating averages and empiric data that over time develops a heritage of dependable predictability. Sameness is good.
<BR>
<BR>Copper thickness may be a culprit if impedance are varying. >.0007 and edges can start getting ragged. I introduce this relative to fixed cycles of press times and the amount of field support for dielectric materials. Copper etching may be more subjective and susceptible to OE (Operator Error). Given that the fabrication is repeatable, which it is, deliverable impedance can go significantly below the standard +/-10%, otherwise we couldn't deliver 25 ohm boards.
<BR>
<BR>Brad</FONT></HTML>
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Date: Thu, 29 Nov 2001 08:50:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Scott R. Madans" <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
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Chuck,
0.2 inches is the max I can work with. Anything less would
be fine, as long as it can handle the extremes of the
environment.
The item needed is very crude, I think, compared to what
y'all are doing. I am probably in the wrong forum for this.
If so, perhaps someone can point me in the right direction.
The finished product will be about 0.5 inches wide and 6.0
to 8.0 inches long (by any thickness up to 0.2").
Edge-mounted will be a dozen, to two dozen, LEDs.
Flexibility, long-term weather resistance, and 12vDC are
just about my only specs. It would be a huge plus if it
would retain the curve when bent.
Unfortunately, I don't have enough background in EE to be
much more specific. From the posts I have received since
subscribing yesterday, this group is clearly THE PLACE for
the coolest electronics manufacturing technology. I didn't
know what Polyimide was until yesterday!
Thanks for the help,
Scott
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
Brummer
Sent: Thursday, November 29, 2001 08:25 AM
To: [log in to unmask]
Subject: Re: [TN] Flexible PC Board
Scott,
0.2 inches is not going to be very flexible. There are
other options like rigid flex,
circuits that are polyimide glass at the ends but have a
flex conection. Can you tell us more
about your needs. How many layers, what weight of copper,
conductor requirements
(line/space)? Maybe someone has some other ideas for you.
Chuck Brummer
"Scott R. Madans" wrote:
> Sorry, the world of mils and microns is new to me. It is
> 0.2 inches!
>
> - Scott
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Chuck
> Brummer
> Sent: Thursday, November 29, 2001 07:58 AM
> To: [log in to unmask]
> Subject: Re: [TN] Flexible PC Board
>
> Scott,
>
> 2/10s of a mil? Like .0002"? You need a dielectric to
hold
> the conductor and I don't think
> you will find anything that thin. We work with thinner
> materials than most and we make a
> number or parts on .0005" polyimide with 3 microns of
> copper. If anyone has anything less
> than that I would like to talk to them.
>
> Chuck Brummer
> Acuson (818)734-4930
>
> "Scott R. Madans" wrote:
>
> > Howdy All,
> >
> > I am new to this list and I thank the folks at 3M's
> > Microflex division for pointing me here. Y'all can
blame
> > them later after reading this lengthily post...
> >
> > The acceptance of my lousy prototype was excellent, so I
> was
> > looking at ideas for a more robust and fine-tuned design
> > using a flexible circuit.
> >
> > I need a flexible PC board operating at 12v DC. Size is
> > about 1/2" x 6" or 8". The mounting is static, but the
> > flexible shape is required because of the variety of
> > mountings. Also, the outdoor environment will be
greasy,
> > dusty, wet, cold (-50F), sunny (UV) and hot (120F). So,
> it
> > needs to be durable. There will be no direct abrasives.
> > The board and protection should be no more than about
> > 2/10ths thick.
> >
> > Is there something like that out there? You've probably
> > seen that "soft-touch" switch rubber used on keypads. A
> > slightly firmer version of that with copper cladding (or
> > something to etch) would be about perfect, as long as
it's
> > tough stuff.
> >
> > Thanks in advance and I appreciate your guidance.
> >
> > - Scott
> > (775) 849-2030
> >
>
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Date: Thu, 29 Nov 2001 10:51:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: FTIR Cards
MIME-Version: 1.0
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I have a question for the chemists in the crowd. 3M used to make
disposable cards for FT-IR analysis with polyethylene or PTFE meshes to
hold liquid samples. VWR tells me that 3M no longer makes such a product
and I can't seem to find them anywhere else. A company called Spectra-tech
makes something similar, but much more expensive. Does anyone know if
there are other manufacturers of these products? I could go to a
demountable liquid cell, but there would be lots of time rinsing cells
between analyses and I have a bunch to go through. Any help would be
appreciated.
Doug Pauls
Rockwell Collins
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Date: Thu, 29 Nov 2001 16:53:51 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
MIME-Version: 1.0
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perhaps someone from the laminate industry can explain why if you draw a
straight line graph between all e glass @ 6.28 and all resin @3.6 , the
resulting line is parallel to but not overlaying the Dk graph for your
material.
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Brad Saunders [SMTP:[log in to unmask]]
Sent: 29 November 2001 16:40
To: [log in to unmask]
Subject: Re: [TN] Dielectric constant vs degree of cure , FR4
FR4 will not change Er due to cure temp at fabrication, however the press
cycle may. Total dielectric constant (Er) is a function of the main
ingredients of Eglass (6.28 Er) and Resin (3.6 for epoxy). The higher the
Eglass content the higher resultant Er. Hence, any "above normal" squeeze
out of resin will have the propensity to increase resultant Er for B-stage,
C-stage is a little different. I say "propensity" for the Er is estimating
averages and empiric data that over time develops a heritage of dependable
predictability. Sameness is good.
Copper thickness may be a culprit if impedance are varying. >.0007 and
edges
can start getting ragged. I introduce this relative to fixed cycles of
press
times and the amount of field support for dielectric materials. Copper
etching may be more subjective and susceptible to OE (Operator Error).
Given
that the fabrication is repeatable, which it is, deliverable impedance can
go
significantly below the standard +/-10%, otherwise we couldn't deliver 25
ohm
boards.
Brad
<< File: ATT00002.htm >>
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Date: Thu, 29 Nov 2001 09:10:26 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: FTIR Cards
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Doug,
Even though the Spectra-tech cards are more expensive, I would go with
those. Actually, I think other card makers also raised their prices...of
the few makers that are out there. The spectra-tech ones come closest to
the 3M cards.
There are also cards that have a metallic wire mesh...but they don't work
too well.
Hans Shin
Pacific Testing Laboratories
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Thursday, November 29, 2001 8:51 AM
To: [log in to unmask]
Subject: [TN] FTIR Cards
I have a question for the chemists in the crowd. 3M used to make
disposable cards for FT-IR analysis with polyethylene or PTFE meshes to
hold liquid samples. VWR tells me that 3M no longer makes such a product
and I can't seem to find them anywhere else. A company called Spectra-tech
makes something similar, but much more expensive. Does anyone know if
there are other manufacturers of these products? I could go to a
demountable liquid cell, but there would be lots of time rinsing cells
between analyses and I have a bunch to go through. Any help would be
appreciated.
Doug Pauls
Rockwell Collins
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Date: Thu, 29 Nov 2001 11:37:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Dielectric constant vs degree of cure , FR4
X-To: Brad Saunders <[log in to unmask]>
This serious discussion could be fun.
Considering today's single ply designs and requirements for constructions
as, say, 4 mil dielectrics using, say, 2113 glass, there's not a lot of
"squeeze out" happening. The resin to glass ratio is moderate or about ideal
and when a specified press cycle is used, variations are minimal. Few folks
are going to high pressure, not that it matters, or are changing recommended
press cycles so few negative, or out of tolerance, changes should be
observed concerning impedance.
As you said, the press cycle is pretty much pre-determined for time, temp,
and pressure. Therefore, as little consequence is observable, there should
be very little change in the dielectric constant or the final impedance effects.
Foil thickness and, more importantly, edge raggedness, as a result of
operator process management ineffectiveness certainly is a major contributor
to wider changes in the final outcome. With all this, I don't believe the
press cycle to be a major factor unless it is greatly mis-managed. Getting
to 25 ohms impedance, depending on design requirements, is a trick unto itself.
MoonMan
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Date: Thu, 29 Nov 2001 11:55:52 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Rusty
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_81DCB6A5.B9D8B5E6"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_81DCB6A5.B9D8B5E6
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Content-Transfer-Encoding: quoted-printable
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I was asked a question today and I can't seem to find the answer. I think =
I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were =
discussing are phosphorus, bronze, iron. Thanks in advance. =20
Kat
--=_81DCB6A5.B9D8B5E6
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I was asked a question today and I can't seem to find the answer. I
think I know but I need more then a gut feel.</DIV>
<DIV> </DIV>
<DIV>Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance. </DIV>
<DIV> </DIV>
<DIV>Kat</DIV></BODY></HTML>
--=_81DCB6A5.B9D8B5E6--
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Date: Thu, 29 Nov 2001 18:20:19 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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Date: Thu, 29 Nov 2001 10:40:35 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Rusty
In-Reply-To: <[log in to unmask]>
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Cannot resist: For those in the rust business, rust is a product. For most
of us it is just a nuisance to be prevented.
But from somebody in the rust (iron oxide) business
(http://www.sh.com/ie/yht.htm) I found this:
Iron Oxide Yellow 313C
Specification: Matter volatile at 105 degrees centigrade (m/m)<%: 0.8 Water
soluble matter% : 0.15 Sieve residue on 0.045mm (m/m) < %:0.3 PH of water
suspension: 5.2 Fe2O3 (m/m) > %:87.1 conductivity us/cm: 175
And then a little more to confuse the issue:
Introduction
Electrochemical studies of Fe oxides have been surely initiated in corrosion
science. Formation of Fe oxides and their further reactions were
characterized in aim to learn more about corrosion resistance of steel. The
first reports were almost exclusively focused on magnetite, Fe3O4, because
it is sufficiently conductive to permit the direct study with a bulk
electrode, i.e. a piece of magnetite attached to the potentiostat, and it
yields several electrochemical reactions. Magnetite is the best starting
point to learn more about electrochemistry of Fe oxides. Lately it was found
that Fe3O4 and different polymorphs of Fe2O3 and FeOOH behave differently
(Keiser et al.).
Related to this topic is the reductive dissolution of Fe(III) oxides, whose
impact significantly exceeds the scope of pure electrochemistry (for a
review of metal oxide dissolution see Blesa et al. 1994). Reductive
dissolution is important in energy production (cleaning steel surfaces
corroded by hot water), environmental analysis (speciation of metals in
sediments and wastes) and also in the cycle of Fe oxides in natural
environment (mineral weathering, soil chemistry).
Another phenomenon studied is electrolysis of water on Fe-oxide electrodes,
which accidentally lead to discovery of oxygen insertion into Co and also Fe
oxides.
The electrochemical properties of Fe oxides are mainly controlled by two
factors: the phase composition and substitution of Fe by other metals. The
most important phases are Fe3O4 (magnetite), Fe2O3 (hematite and maghemite),
FeOOH (goethite, lepidocrocite, and few others), spinels such as MeFe2O4,
and perovskites such as SrFeO3. The commonest metals substituting Fe are Al
and Cr. The sensitivity of electrochemical properties to the oxide structure
has been proposed several times for electroanalysis, but since now other
techniques, in particular X-ray diffraction and Mössbauer spectroscopy, have
won. However, reductive dissolution of Fe(III) oxides by chemical agents is
a generally accepted analytical tool in soil and environemntal chemistry.
Good luck with the micro Siemens.
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kathy Kuhlow
Sent: Thursday, November 29, 2001 09:56
To: [log in to unmask]
Subject: [TN] Rusty
<< File: TEXT.htm >> I was asked a question today and I can't seem to find
the answer. I think I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
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Date: Thu, 29 Nov 2001 10:52:07 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: FTIR Cards
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hi,
two responses from chris murphy in our chemistry lab.
phil
---------------------
Hi Phil,
I haven't heard of these disposable mesh cards. Our typical sources for infrared accessories are Thermo Nicolet, Thermo Spectra-Tech, Perkin Elmer, Harrick Scientific or Janos Technology.
<http://www.photonics.com/>
<http://www.thermonicolet.com>
http://www.thermospectra-tech.com
<http://www.harricksci.com>
http://www.perkinelmer.com
Chris Murphy
TRW Chemistry Technology Department
310-813-9355
Phil,
Could this be what he is looking for?
http://www.janostech.com/products/screencell.html
Rockwell Collins
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Date: Thu, 29 Nov 2001 13:57:04 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Rusty
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_f6.13221ee2.2937df00_boundary"
--part1_f6.13221ee2.2937df00_boundary
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
Hi Kat!
Rust is not conductive...I tried to find something on the web that states=20
that precisely, and found this, not exactly scientific, but sounds to me lik=
e=20
a voice of experience...
-Steve Gregory-
Using O Gauge Outdoors: Some Do=E2=80=99s and Don=E2=80=99ts
by <A HREF=3D"http://www.trainweb.org/ttos-pnw/former_officers.htm">Doug Gra=
y</A>=20
Perhaps you have toyed with the outdoor railroad ideas, but dismissed them=20
having heard somewhere that only G Scale can be used outdoors. And, since=20
many of us have collections of O Gauge trains, the added expense of starting=
=20
a new G Gauge collection deters you from outdoor railroading. The solution?=20
Use your O gauge outdoors! A great advantage is that you can finally have th=
e=20
long right of ways that you have no room for indoors. Based upon my decade o=
f=20
experience, it does work, but there are some precautions to observe.First,=20
let us start with the track system. Gargraves, and other manufacturers, make=
=20
track designed for outdoors, utilizing stainless steel rails and UV treated=20
plastic ties. Ordinary sectional indoor track will last about a week before=20
rust takes over. It will first appear on the rail surfaces, and soon the pin=
s=20
will rust and there will be no electrical conductivity. =20
> I was asked a question today and I can't seem to find the answer. I think=
I=20
> know but I need more then a gut feel.
>=20
> Is rust conductive, just a by product, or both? The materials we were=20
> discussing are phosphorus, bronze, iron. Thanks in advance. =20
>=20
> Kat
>=20
--part1_f6.13221ee2.2937df00_boundary
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Content-Language: en
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=
=3D"Arial" LANG=3D"0">Hi Kat!
<BR>
<BR>Rust is not conductive...I tried to find something on the web that state=
s that precisely, and found this, not exactly scientific, but sounds to me l=
ike a voice of experience...
<BR>
<BR>-Steve Gregory-
<BR>
<BR></FONT><FONT COLOR=3D"#ff0000" SIZE=3D4 FAMILY=3D"SCRIPT" FACE=3D"Comic=
Sans MS" LANG=3D"0"><B>Using O Gauge Outdoors: Some Do=E2=80=99s and Don=
=E2=80=99ts
<BR><P ALIGN=3DCENTER></FONT><FONT COLOR=3D"#ff0000" SIZE=3D3 FAMILY=3D"SCR=
IPT" FACE=3D"Comic Sans MS" LANG=3D"0">by <A HREF=3D"http://www.trainweb.org=
/ttos-pnw/former_officers.htm">Doug Gray</A></FONT><FONT COLOR=3D"#000000"=20=
SIZE=3D2 FAMILY=3D"SCRIPT" FACE=3D"Comic Sans MS" LANG=3D"0">=20
<BR><P ALIGN=3DLEFT>
<BR></B>Perhaps you have toyed with the outdoor railroad ideas, but dismisse=
d them having heard somewhere that only G Scale can be used outdoors. And, s=
ince many of us have collections of O Gauge trains, the added expense of sta=
rting a new G Gauge collection deters you from outdoor railroading. The solu=
tion? Use your O gauge outdoors! A great advantage is that you can finally h=
ave the long right of ways that you have no room for indoors. Based upon my=20=
decade of experience, it does work, but there are some precautions to observ=
e.First, let us start with the track system. Gargraves, and other manufactur=
ers, make track designed for outdoors, utilizing stainless steel rails and U=
V treated plastic ties. Ordinary sectional indoor track will last about a we=
ek before rust takes over. It will first appear on the rail surfaces, and so=
on the pins will rust and there will be no electrical conductivity. =20
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I was asked a question toda=
y and I can't seem to find the answer. I think I know but I need more=20=
then a gut feel.
<BR>
<BR>Is rust conductive, just a by product, or both? The materials we w=
ere discussing are phosphorus, bronze, iron. Thanks in advance.
<BR>
<BR>Kat
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR>
<BR>
<BR>
<BR>
<BR>
<BR></P></P></FONT></HTML>
--part1_f6.13221ee2.2937df00_boundary--
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Date: Thu, 29 Nov 2001 12:01:02 -0800
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: FTIR Cards
In-Reply-To: <45EC695FE212D311A49D0000D11BAF7C053C6C6F@MBRC02>
MIME-Version: 1.0
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If you're looking for residues, I wouldn't recommend the ones from
Janostech. Those may be useful for analyzing solvents.
Hans Shin
Pacific Testing Laboratories
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Crepeau, Phil
Sent: Thursday, November 29, 2001 10:52 AM
To: [log in to unmask]
Subject: Re: [TN] FTIR Cards
hi,
two responses from chris murphy in our chemistry lab.
phil
---------------------
Hi Phil,
I haven't heard of these disposable mesh cards. Our typical sources for
infrared accessories are Thermo Nicolet, Thermo Spectra-Tech, Perkin Elmer,
Harrick Scientific or Janos Technology.
<http://www.photonics.com/>
<http://www.thermonicolet.com>
http://www.thermospectra-tech.com
<http://www.harricksci.com>
http://www.perkinelmer.com
Chris Murphy
TRW Chemistry Technology Department
310-813-9355
Phil,
Could this be what he is looking for?
http://www.janostech.com/products/screencell.html
Rockwell Collins
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Date: Thu, 29 Nov 2001 18:39:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: board dunked in wave solder
TechNetters, I know there was discussion of this before, many months ago,
but I can't track down the postings in the archives. Please comment.
We have with solder on some of the top side, surrounding some components
(ICs and passives). It was dunked in wave solder. Are boards that have
"submarined" (I think someone used this term in the earlier discussion)
useable if excess solder is removed? Never useable? Sometimes?
I could say it's OK, since submarining shouldn't be as bad as HASL, but
would like some expert comments.
Lou Hart
Compunetix Quality Assurance
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Date: Fri, 30 Nov 2001 08:18:37 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Rusty
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Content-type: text/plain; charset=us-ascii
Hi, Kathy,
Rust is a very poor conductor, as anyone with a rusty car and wiring
trouble can testify. Corrosion on battery terminals can ruin a connection,
and where oxidisation is deliberate, such as in anodising of aluminium,
electrical conductivity is poor to non-existant, depending on the thickness
of the oxide layer.
Peter Duncan
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Rusty
<[log in to unmask]
ORG>
11/30/01
01:55 AM
Please
respond to
"TechNet
E-Mail
Forum."
I was asked a question today and I can't seem to find the answer. I think
I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
(See attached file: TEXT.htm)
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
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Date: Fri, 30 Nov 2001 08:29:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: board dunked in wave solder
MIME-Version: 1.0
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Some years ago, I was faced with a few flooded boards (conventional
through-hole stuff), and the recovery operation involved removing the
excess solder by reflowing it upside down, removing the components and
putting the now-bare boards through the recently-remembered hydrosqueegee
process to re-level the solder and clear the holes. I shudder slightly at
the mere thought of all those high thermal excursions, but it did return us
useable boards.
Peter Duncan
Lou Hart
<lhart@COMPUN To: [log in to unmask]
ETIX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] board dunked in wave solder
<[log in to unmask]
ORG>
11/30/01
07:39 AM
Please
respond to
"TechNet
E-Mail
Forum."
TechNetters, I know there was discussion of this before, many months ago,
but I can't track down the postings in the archives. Please comment.
We have with solder on some of the top side, surrounding some components
(ICs and passives). It was dunked in wave solder. Are boards that have
"submarined" (I think someone used this term in the earlier discussion)
useable if excess solder is removed? Never useable? Sometimes?
I could say it's OK, since submarining shouldn't be as bad as HASL, but
would like some expert comments.
Lou Hart
Compunetix Quality Assurance
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---------------------------------------------------------------------------------
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Date: Thu, 29 Nov 2001 18:32:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: board dunked in wave solder
X-To: "<Peter George Duncan>" <[log in to unmask]>
Shudder slightly indeed Peter. We all wish we could garner such results.
Isn't it amazing how much abuse well designed and processed boards can endure?
MoonMan
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Date: Thu, 29 Nov 2001 19:41:45 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: board dunked in wave solder
MIME-Version: 1.0
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boundary="part1_6b.1e7c58d0.29382fc9_boundary"
--part1_6b.1e7c58d0.29382fc9_boundary
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Hi Lou!
I think that this is the one event when it happens, eclipses any other event
in printed circuit assembly manufacturing, that brings forth a flood (no pun
intended) of intense emotions from the observer...shock, horror, terror,
regret, desperation, depression (it's not for the faint hearted). Those
emotions multiply exponentially depending on the assemblies complexity and
value. It does happen though...I think some of my gray hair has come from a
few of those over the years.
But in those times when it came down to having to salvage the mess, I would
say there were no problems. The decision would always be made based on
dollars. Did it make more economic sense to put the extensive labor needed to
clean-up everything, or just start from scratch again...
One thing to do if you're quick enough when it happens, is to try and grab
the board as it comes off the conveyer and "pour" the solder off as quickly
as you can, and in such a way to involve the least number of components, or
the obviously complex ones, PGA's, BGA's, etc...takes for some quick thinking
when you're staring in horror as the event unfolds!
Molten solder on top of the board hasn't ruined the PCB in my experience,
it's just a matter of cleaning-up all the shorts that happen...again, it's a
economics thing. If you want/need to salvage a board that's "sub'ed", I don't
think quality is that much of a concern if it's done by someone who can
handle something like this.
It's happened a time or two with me, and I've bought more than a few lunches
for a few ladies that were magicians with soldering irons and solder
extractors...they are worth their weight in gold.
-Steve Gregory-
> TechNetters, I know there was discussion of this before, many months ago,
> but I can't track down the postings in the archives. Please comment.
>
> We have with solder on some of the top side, surrounding some components
> (ICs and passives). It was dunked in wave solder. Are boards that have
> "submarined" (I think someone used this term in the earlier discussion)
> useable if excess solder is removed? Never useable? Sometimes?
>
> I could say it's OK, since submarining shouldn't be as bad as HASL, but
> would like some expert comments.
>
> Lou Hart
> Compunetix Quality Assurance
>
--part1_6b.1e7c58d0.29382fc9_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Lou!<BR>
<BR>
I think that this is the one event when it happens, eclipses any other event in printed circuit assembly manufacturing, that brings forth a flood (no pun intended) of intense emotions from the observer...shock, horror, terror, regret, desperation, depression (it's not for the faint hearted). Those emotions multiply exponentially depending on the assemblies complexity and value. It does happen though...I think some of my gray hair has come from a few of those over the years.<BR>
<BR>
But in those times when it came down to having to salvage the mess, I would say there were no problems. The decision would always be made based on dollars. Did it make more economic sense to put the extensive labor needed to clean-up everything, or just start from scratch again...<BR>
<BR>
One thing to do if you're quick enough when it happens, is to try and grab the board as it comes off the conveyer and "pour" the solder off as quickly as you can, and in such a way to involve the least number of components, or the obviously complex ones, PGA's, BGA's, etc...takes for some quick thinking when you're staring in horror as the event unfolds!<BR>
<BR>
Molten solder on top of the board hasn't ruined the PCB in my experience, it's just a matter of cleaning-up all the shorts that happen...again, it's a economics thing. If you want/need to salvage a board that's "sub'ed", I don't think quality is that much of a concern if it's done by someone who can handle something like this.<BR>
<BR>
It's happened a time or two with me, and I've bought more than a few lunches for a few ladies that were magicians with soldering irons and solder extractors...they are worth their weight in gold.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">TechNetters, I know there was discussion of this before, many months ago,<BR>
but I can't track down the postings in the archives. Please comment.<BR>
<BR>
We have with solder on some of the top side, surrounding some components<BR>
(ICs and passives). It was dunked in wave solder. Are boards that have<BR>
"submarined" (I think someone used this term in the earlier discussion)<BR>
useable if excess solder is removed? Never useable? Sometimes?<BR>
<BR>
I could say it's OK, since submarining shouldn't be as bad as HASL, but<BR>
would like some expert comments.<BR>
<BR>
Lou Hart<BR>
Compunetix Quality Assurance<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Thu, 29 Nov 2001 17:05:42 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: board dunked in wave solder
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hi,
i don't know. i think that getting boards-bonded-to-core assemblies back from the field when the boards have fallen off the core eclipses a board-in-the-solder-pot problem any day for angst. not that this ever happened to me you understand.
phil
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charset="iso-8859-1"
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<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
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<BODY>
<DIV><SPAN class=651560101-30112001><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=651560101-30112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=651560101-30112001><FONT face=Arial color=#0000ff size=2>i
don't know. i think that getting boards-bonded-to-core
assemblies back from the field when the boards have fallen off the
core eclipses a board-in-the-solder-pot problem any day for angst. not
that this ever happened to me you understand.</FONT></SPAN></DIV>
<DIV><SPAN class=651560101-30112001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=651560101-30112001><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN><FONT face=arial,helvetica><FONT
size=2></DIV></FONT></FONT></BODY></HTML>
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Date: Thu, 29 Nov 2001 23:33:29 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Organic Silver PCB's
MIME-Version: 1.0
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Dave:
Some of the immersion Silver finishes have a co-deposited organic
anti-tarnish in them.
Rudy Sedlak
RD Chemical Company
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Date: Thu, 29 Nov 2001 21:53:57 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: Pick & place equipment process control
In-Reply-To: <002301c17910$9323a930$0c140a0a@hshin>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Hello,
I have asked this question before but did not receive many replies.
Does anyone have any success or suggestion on measuring P&P machine
parameters in line? Such as vacuum pressures, vision alignment error and
placement compensation, placement pressure, drive speed and movement.
Obviously I am setup SPC for my P&P process.
P&P machines that we have in our company do not seem to be "opened"
systems. The only parameters I can measure are indirect - pickup error%,
reject rate, and I went as far as using test vehicles to verify
placement accuracy with AOI. These are however, not direct machine
parameters and do not give me a clear picture of the major moving parts
on the machine.
What other variations within a chip shooting process can one measure and
control?
Rgds,
Peter
_________________________________________________________
Do You Yahoo!?
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Date: Fri, 30 Nov 2001 15:52:05 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anil Kher <[log in to unmask]>
Organization: Micro Interconnexion Pvt. Ltd
Subject: Re: (VIRUS ALERT!!!) [TN] O. MATERIALS. TO : VALUED ASSOCIATES.
X-To: "Stephen R. Gregory" <[log in to unmask]>
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Dear All
I was out of office for the last ten days. I regret the inconvenience =
this worm has caused to you.
I am surprised my virus shield did not work nor did the on line sacn on =
the day following
Sorry
Anil Kher
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charset="UTF-8"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<META http-equiv=3DContent-Type content=3D"text/html; charset=3Dutf-8">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF">Dear All</FONT></FONT></DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF">I was out of office for the last ten days. I regret =
the=20
inconvenience this worm has caused to you.</FONT></FONT></DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF">I am surprised my virus shield did not work nor did =
the on=20
line sacn on the day following</FONT></FONT></DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF"></FONT></FONT> </DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF">Sorry</FONT></FONT></DIV>
<DIV><FONT face=3Darial,helvetica><FONT lang=3D0 face=3DArial =
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF">Anil Kher</DIV></FONT></FONT></BODY></HTML>
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Date: Fri, 30 Nov 2001 06:53:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: board dunked in wave solder
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Hi Lou, Steve
I agree with Steve - if it makes sense $$$ or schedule / parts availability=
- salvage it. If it's a cheapo then the decision is obvious.
My "best" submarine experience: first month on the new job. Been in =
tweaking the wave machine all morning, and the boss wanders in looking for =
me. While chatting he watches a board going over the wave... SWOOSH. =
=20
Actually - if I'd been thinking fast I would have parlayed that into =
retrofitting the chain with L fingers (it's got V on it). I suspect I had =
not quite fitted the board into the V... but as Steve says - the shock =
and horror...
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 11/29/01 08:41PM >>>
Hi Lou!
I think that this is the one event when it happens, eclipses any other =
event
in printed circuit assembly manufacturing, that brings forth a flood (no =
pun
intended) of intense emotions from the observer...shock, horror, terror,
regret, desperation, depression (it's not for the faint hearted). Those
emotions multiply exponentially depending on the assemblies complexity and
value. It does happen though...I think some of my gray hair has come from =
a
few of those over the years.
But in those times when it came down to having to salvage the mess, I =
would
say there were no problems. The decision would always be made based on
dollars. Did it make more economic sense to put the extensive labor needed =
to
clean-up everything, or just start from scratch again...
One thing to do if you're quick enough when it happens, is to try and grab
the board as it comes off the conveyer and "pour" the solder off as =
quickly
as you can, and in such a way to involve the least number of components, =
or
the obviously complex ones, PGA's, BGA's, etc...takes for some quick =
thinking
when you're staring in horror as the event unfolds!
Molten solder on top of the board hasn't ruined the PCB in my experience,
it's just a matter of cleaning-up all the shorts that happen...again, it's =
a
economics thing. If you want/need to salvage a board that's "sub'ed", I =
don't
think quality is that much of a concern if it's done by someone who can
handle something like this.
It's happened a time or two with me, and I've bought more than a few =
lunches
for a few ladies that were magicians with soldering irons and solder
extractors...they are worth their weight in gold.
-Steve Gregory-
> TechNetters, I know there was discussion of this before, many months =
ago,
> but I can't track down the postings in the archives. Please comment.
>
> We have with solder on some of the top side, surrounding some components
> (ICs and passives). It was dunked in wave solder. Are boards that have
> "submarined" (I think someone used this term in the earlier discussion)
> useable if excess solder is removed? Never useable? Sometimes?
>
> I could say it's OK, since submarining shouldn't be as bad as HASL, but
> would like some expert comments.
>
> Lou Hart
> Compunetix Quality Assurance
>
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Date: Fri, 30 Nov 2001 07:07:46 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Barry Gallegos <[log in to unmask]>
Got distracted by work, if you can believe that, and didn't finish.
You know all this stuff but if your conveyor is traveling at 4'/minute, that
means 1'/15 seconds (great math, eh?). If you use your Lev Chek glass one
inch grid plate and you verify your contact area is parallel and is about
1.5" across, then you can determine your contact time. For more "normal"
boards, depending on your matrix indicators, your contact time should be
about 1.5 - 3 seconds - depending on conveyor speed.
For massive boards, thermally speeking, the contact time may be much longer
as the conveyor speed may be as slow as 1'/minute or less. Scary stuff these
boards and conditions.
Of course, with all this stuff, I'm using through hole technology as the
baseline for the settings. Mixed technoloty will be the same though SMT ohly
types can be more "normally" profiled.
Once sub-process and process "calibration" is done manually, profilometers
may be used as well. Of course, many "trust" the machine's computer if so
equipped. No matter, I still do manual "calibrations" on a regular basis for
computer controlled machines and I do this at the beginning of each new
product lot on less automated machines - all a function of my trusty matrix
having all the "numbers"/paramaters for each board type required. My matrix
then is converted to SPC information as process control charts based on
process effects as acceptable quality solder joints.
I'm done and distracted by work again. Just killing a little time on a very
old subject I don't get to visit that much anymore. What's the company that
makes the Lev Check glass plate again?
MoonMan
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Date: Fri, 30 Nov 2001 08:42:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Wave Solder Profiling
MIME-Version: 1.0
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Mornin' Earl,
That would be Hexacon Electric out of NJ.
Steve
-----Original Message-----
What's the company that
makes the Lev Check glass plate again?
MoonMan
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Date: Fri, 30 Nov 2001 07:47:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Pelchat, Janice" <[log in to unmask]>
Subject: Conformal Coat House
MIME-Version: 1.0
Content-Type: text/plain
Does anyone have any recommendations they can make about coating houses in
the New England area?
You can contact me offline if you prefer.
Jan Pelchat
[log in to unmask]
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Date: Fri, 30 Nov 2001 09:01:31 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Flexible PC Board
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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If you need some design help on materials you can call me.
Steve Kelly
PFC Flexible Circuits Ltd.
(416) 750-8433
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Scott R. Madans
Sent: Wednesday, November 28, 2001 8:48 PM
To: [log in to unmask]
Subject: [TN] Flexible PC Board
Howdy All,
I am new to this list and I thank the folks at 3M's
Microflex division for pointing me here. Y'all can blame
them later after reading this lengthily post...
The acceptance of my lousy prototype was excellent, so I was
looking at ideas for a more robust and fine-tuned design
using a flexible circuit.
I need a flexible PC board operating at 12v DC. Size is
about 1/2" x 6" or 8". The mounting is static, but the
flexible shape is required because of the variety of
mountings. Also, the outdoor environment will be greasy,
dusty, wet, cold (-50F), sunny (UV) and hot (120F). So, it
needs to be durable. There will be no direct abrasives.
The board and protection should be no more than about
2/10ths thick.
Is there something like that out there? You've probably
seen that "soft-touch" switch rubber used on keypads. A
slightly firmer version of that with copper cladding (or
something to etch) would be about perfect, as long as it's
tough stuff.
Thanks in advance and I appreciate your guidance.
- Scott
(775) 849-2030
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Date: Fri, 30 Nov 2001 13:52:11 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Rusty
In-Reply-To: <[log in to unmask]>
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The term rust may be used slightly differently UK/US, so I dredge up from
memory what I was taught sometime ago in last century England:
Strictly only iron can rust, but it is more than just iron oxide. It is a
dynamic mixture of iron oxides and water which perpetuates itself as long as
there is a supply of oxygen in damp conditions.
Non ferrous metals don't rust therefore but they may tarnish. Phosphorus is
not a metal, so it can neither rust nor tarnish to oxide, it actually burns
quite vigorously.
As mentioned below generally oxides do not conduct, the only one I can think
of off hand that does is silver. Some oxides in conjunction with the base
metal can make rectifiers so conduct in one direction only. In iron oxide
terms old fashioned cast iron drainpipes used to accidentally act as simple
radio receivers and re-transmitters due to this rectification phenomenon.
Confession time: when I get asked this sort of "I ought to/used to know this
basic sort of stuff" question, or need to know enough to ask a harder one
myself, I quite often visit www.howstuffworks.com
You can ask almost anything you like and it usually comes back quickly with
the answer you were thinking of. More importantly it assumes almost no prior
knowledge so you can understand it.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
Sent: Friday, November 30, 2001 12:19 AM
To: [log in to unmask]
Subject: Re: [TN] Rusty
Hi, Kathy,
Rust is a very poor conductor, as anyone with a rusty car and wiring
trouble can testify. Corrosion on battery terminals can ruin a connection,
and where oxidisation is deliberate, such as in anodising of aluminium,
electrical conductivity is poor to non-existant, depending on the thickness
of the oxide layer.
Peter Duncan
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Rusty
<[log in to unmask]
ORG>
11/30/01
01:55 AM
Please
respond to
"TechNet
E-Mail
Forum."
I was asked a question today and I can't seem to find the answer. I think
I know but I need more then a gut feel.
Is rust conductive, just a by product, or both? The materials we were
discussing are phosphorus, bronze, iron. Thanks in advance.
Kat
(See attached file: TEXT.htm)
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Fri, 30 Nov 2001 08:22:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: board dunked in wave solder
Mime-Version: 1.0
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We rework them but very carefully. With SOIC, QFP, etc solder can cause a =
lot of solder shorting underneath that isn't visible. Either xray to =
confirm all solder removeal underneath or remove to confirm. =20
Kathy
--=_C29FF407.8EEF82D0
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style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>We rework them but very carefully. With SOIC, QFP, etc solder can
cause a lot of solder shorting underneath that isn't visible. Either xray
to confirm all solder removeal underneath or remove to confirm. </DIV>
<DIV> </DIV>
<DIV>Kathy</DIV></BODY></HTML>
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Date: Fri, 30 Nov 2001 09:47:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anita Sargent <[log in to unmask]>
Subject: Anita Sargent/Endicott/IBM is out of the office.
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I will be out of the office starting November 30, 2001 and will not return
until December 3, 2001.
I will respond to your message when I return.
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Date: Fri, 30 Nov 2001 08:52:20 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Wave Solder Profiling
X-To: Steve Sauer <[log in to unmask]>
Steve,
Can't thank you enough. Probably never will use or see one again but good to
know as I always forget or loose that name. My other problem with thest
plates is my inept handling of them. I must clamp them too hard in the
fingers or they just break because of thermal shock. Tried preheating them
but still kept breaking them when they hit the wave. Any suggestions beside
buying several as spares?
Earl
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Date: Fri, 30 Nov 2001 08:56:04 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Rusty
X-To: mike Fenner <[log in to unmask]>
Mike,
That was interesting stuff as is the site you indicated. Very interesting
and useful.
One thing: Phosphorous burns - ok - so it oxidizes, right? Webster, or some
such dictionary, defines oxidation as burning. Not too interesting but
factual, eh?
Earl
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Date: Fri, 30 Nov 2001 09:52:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Westheimer <[log in to unmask]>
Subject: Fw: Differential impedance
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0060_01C17984.A9219980"
This is a multi-part message in MIME format.
------=_NextPart_000_0060_01C17984.A9219980
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
From: Scott Westheimer=20
To: Technet=20
Sent: Friday, November 30, 2001 9:06 AM
Subject: Differential impedance
I have a question regarding differential signal pairs and differential =
impedance that I hope someone can help me with. We are designing a 14 =
layer board and the finished thickness needs to .062" and we require 100 =
ohms. Some of the internal layers we have split planes. Would these be =
considered strip line or microstrips?
Thanks=20
Scott
------=_NextPart_000_0060_01C17984.A9219980
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3315.2870" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV> </DIV>
<DIV style=3D"FONT: 10pt arial">
<DIV style=3D"BACKGROUND: #e4e4e4; font-color: black"><B>From:</B> <A=20
href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Scott=20
Westheimer</A> </DIV>
<DIV><B>To:</B> <A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>Technet</A> </DIV>
<DIV><B>Sent:</B> Friday, November 30, 2001 9:06 AM</DIV>
<DIV><B>Subject:</B> Differential impedance</DIV></DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2>I have a question regarding =
differential signal=20
pairs and differential impedance that I hope someone can help me with. =
We are=20
designing a 14 layer board and the finished thickness needs to .062" and =
we=20
require 100 ohms. Some of the internal layers we have split planes. =
Would these=20
be considered strip line or microstrips?</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Scott</FONT></DIV></BODY></HTML>
------=_NextPart_000_0060_01C17984.A9219980--
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Date: Fri, 30 Nov 2001 09:05:59 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary McCauley <[log in to unmask]>
Subject: Re: Rusty
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Explosion, burning, oxidation. It's a
matter of time. ;-)
gary mccauley
PC Boards, Inc.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 8:56 AM
To: [log in to unmask]
Subject: Re: [TN] Rusty
Mike,
That was interesting stuff as is the site you indicated. Very interesting
and useful.
One thing: Phosphorous burns - ok - so it oxidizes, right? Webster, or some
such dictionary, defines oxidation as burning. Not too interesting but
factual, eh?
Earl
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Date: Fri, 30 Nov 2001 09:06:40 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
X-To: Scott Wesheimer <[log in to unmask]>
I know you remember the classic definition of microstrip as a function of
surface traces referenced only to one internal plane - either exposed to air
or buried by solder mask. Likewise, stripline is a function of traces
between two reference planes either centered or offset. Don't know what
difference continuous or split planes make to these definitions but for
possible functionality and performance factors.
MoonMan
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Date: Fri, 30 Nov 2001 10:15:56 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: board dunked in wave solder
MIME-Version: 1.0
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I have reworked many like this, and the comments already offered regarding
cost analysis are important to consider. Also verify that the components
involved can take the heat cycle of the rework, or else replace them.
Kathy's comment about x-ray for SOIC's etc. was right on the mark. Little
slivers of solder bridging under those parts can be nearly impossible to see.
Jon Moore
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Date: Fri, 30 Nov 2001 09:10:00 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Rusty
X-To: Gary McCauley <[log in to unmask]>
Yes, but not to get carried away, while attempting to stay within the realm
of this forum, isn't an explosion nothing more than rapid burning.
Therefore, oxidation must be really fast burning when an explosion is effected.
MoonMan
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Date: Fri, 30 Nov 2001 15:10:13 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Rusty
MIME-Version: 1.0
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Two things to add to this Friday afternoon discussion.
I was taught in my chemistry class the following mnemonics:
LEO - Loss of Electrons = Oxidation
GER - Gain of Electrons = Reduction
So oxidation may result in burning or even an explosion. But not everything that oxidises
burns.
The difference between burning and exploding is the rate at which the chemical reaction
proceeds. My unreliable memory reminds me that in burning the reaction passes from molecule to
molecule while in an explosion the reaction proceeds through the medium at the speed of sound.
Have a nice weekend,
[log in to unmask] wrote:
> Yes, but not to get carried away, while attempting to stay within the realm
> of this forum, isn't an explosion nothing more than rapid burning.
> Therefore, oxidation must be really fast burning when an explosion is effected.
>
> MoonMan
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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Date: Fri, 30 Nov 2001 07:53:30 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: Fw: Differential impedance
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
There is a large body of free information on the UltraCAD website:
http://www.ultracad.com/homepage.htm
that deals with trace impedance and other layout issues. They also have
several free calculator programs, including one to verify or aid impedance -
vs. - geometry tradeoffs. Try it . . . you'll like it!
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 7:07 AM
To: [log in to unmask]
Subject: Re: [TN] Fw: Differential impedance
I know you remember the classic definition of microstrip as a function of
surface traces referenced only to one internal plane - either exposed to air
or buried by solder mask. Likewise, stripline is a function of traces
between two reference planes either centered or offset. Don't know what
difference continuous or split planes make to these definitions but for
possible functionality and performance factors.
MoonMan
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Date: Fri, 30 Nov 2001 08:24:02 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Denis Lefebvre <[log in to unmask]>
Subject: Re: Fw: Differential impedance
In-Reply-To: <006301c179ae$92055d20$7801a8c0@GULTECHGM>
Mime-Version: 1.0
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--=====================_10662161==_.ALT
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Micro strip is an external transmission line referenced to an internal
plane/dielectric & air.
Stripline in an internal transmission line referenced between two planes
and dielectric.
-Denis
At 09:52 AM 11/30/2001 -0500, you wrote:
>
>From: <mailto:[log in to unmask]>Scott Westheimer
>To: <mailto:[log in to unmask]>Technet
>Sent: Friday, November 30, 2001 9:06 AM
>Subject: Differential impedance
>
>I have a question regarding differential signal pairs and differential
>impedance that I hope someone can help me with. We are designing a 14
>layer board and the finished thickness needs to .062" and we require 100
>ohms. Some of the internal layers we have split planes. Would these be
>considered strip line or microstrips?
>
>Thanks
>
>Scott
--=====================_10662161==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
Micro strip is an external transmission line referenced to an internal
plane/dielectric & air.<br>
Stripline in an internal transmission line referenced between two planes
and dielectric.<br>
-Denis<br>
At 09:52 AM 11/30/2001 -0500, you wrote:<br>
<blockquote type=cite class=cite cite> <br>
<b>From:</b> <a href="mailto:[log in to unmask]">Scott
Westheimer</a> <br>
<b>To:</b> <a href="mailto:[log in to unmask]">Technet</a> <br>
<b>Sent:</b> Friday, November 30, 2001 9:06 AM<br>
<b>Subject:</b> Differential impedance<br><br>
<font face="arial" size=2>I have a question regarding differential signal
pairs and differential impedance that I hope someone can help me with. We
are designing a 14 layer board and the finished thickness needs to
.062" and we require 100 ohms. Some of the internal layers we have
split planes. Would these be considered strip line or
microstrips?</font><br>
<br>
<font face="arial" size=2>Thanks </font><br>
<br>
<font face="arial" size=2>Scott</font></blockquote></html>
--=====================_10662161==_.ALT--
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Date: Fri, 30 Nov 2001 10:36:57 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Thanks you
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_451873A3.4F2E431E"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_451873A3.4F2E431E
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
This forum is the best out there. Thanks to all who responded to the =
rusty question. =20
Kathy=20
--=_451873A3.4F2E431E
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>This forum is the best out there. Thanks to all who responded to the
rusty question. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_451873A3.4F2E431E--
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Date: Fri, 30 Nov 2001 10:39:09 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
X-To: Denis Lefebvre <[log in to unmask]>
Denis,
Your definition certainly is simpler than mine. I'll keep yours.
Did I get you all you needed in addition to the check list? Let me know off
line what I owe you.
Concerning the 14 layer .062 MLB, I must be living in another world. Hell, I
was just getting over 10 layer types that thick notwithstanding impedance.
This 14 layer thing went right over my head.
I know we all are using single ply constructions but isn't this pushing it
just a bit. I mean you'd have to use 3 mil stuff, whatever the core and preg
would be, to get this done regardless of the split plane and trace width
considerations.
Someone please tell me how this board would be made, and made to work.
MoonMan
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Date: Fri, 30 Nov 2001 17:39:21 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Martyn Gaudion <[log in to unmask]>
Subject: Re: Fw: Differential impedance
In-Reply-To: <006301c179ae$92055d20$7801a8c0@GULTECHGM>
Mime-Version: 1.0
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Scott,
You may also like to look at the application notes
on the Polar site:
www.polarinstruments.com/support/cits/cits_index.html
Kind regards
Martyn Gaudion
Polar Instruments
T: + 44 1481 253081
F: + 44 1481 252476
M: +44 7710 522748
E: [log in to unmask]
www.polarinstruments.com
At 09:52 30/11/01 -0500, you wrote:
>
>From: <mailto:[log in to unmask]>Scott Westheimer
>To: <mailto:[log in to unmask]>Technet
>Sent: Friday, November 30, 2001 9:06 AM
>Subject: Differential impedance
>
>I have a question regarding differential signal pairs and differential
>impedance that I hope someone can help me with. We are designing a 14
>layer board and the finished thickness needs to .062" and we require 100
>ohms. Some of the internal layers we have split planes. Would these be
>considered strip line or microstrips?
>
>Thanks
>
>Scott
--=====================_6843055==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
Scott,<br>
<br>
You may also like to look at the application notes<br>
on the Polar site:<br>
<br>
<a href="http://www.polarinstruments.com/support/cits/cits_index.html" eudora="autourl">www.polarinstruments.com/support/cits/cits_index.</a><a href="http://www.polarinstruments.com/support/cits/cits_index.html" eudora="autourl">html<br>
<br>
<br>
<br>
</a>Kind regards<br>
Martyn Gaudion <br>
Polar Instruments<br>
<br>
T: + 44 1481 253081<br>
F: + 44 1481 252476<br>
M: +44 7710 522748<br>
E: [log in to unmask]<br>
<a href="http://www.polarinstruments.com/" eudora="autourl">www.polarinstruments.com</a>
<br>
<br>
<br>
At 09:52 30/11/01 -0500, you wrote:<br>
<blockquote type=cite cite> <br>
<b>From:</b> <a href="mailto:[log in to unmask]">Scott Westheimer</a> <br>
<b>To:</b> <a href="mailto:[log in to unmask]">Technet</a> <br>
<b>Sent:</b> Friday, November 30, 2001 9:06 AM<br>
<b>Subject:</b> Differential impedance<br>
<br>
<font face="arial" size=2>I have a question regarding differential signal pairs and differential impedance that I hope someone can help me with. We are designing a 14 layer board and the finished thickness needs to .062" and we require 100 ohms. Some of the internal layers we have split planes. Would these be considered strip line or microstrips?</font><br>
<br>
<font face="arial" size=2>Thanks </font><br>
<br>
<font face="arial" size=2>Scott</font></blockquote></html>
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Date: Fri, 30 Nov 2001 11:30:13 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Fw: Differential impedance
Just one more thing concerning split planes. Has 274x been fixed to handle
them or do we have to continue using 274d to view them without the mush? I
know the answer must be using ODB++ instead of Gerber output, but some
aren't there yet.
MoonMan
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Date: Fri, 30 Nov 2001 12:46:28 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen S. Schiera" <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: Graham Naisbitt <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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Date: Fri, 30 Nov 2001 13:34:37 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lefebvre, Scott" <[log in to unmask]>
Subject: LLP Leadless LeadFrame Package
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have been asked if engineering could use this package on their new
designs. I've used LCC before and had no real problems but they were not
blind connections like this package.
I have concerns that the center pad on the bottom of the component would be
susceptible to shorting to the adjacent outer pads. Do any of you have
other concerns that you could share with me, it would be greatly
appreciated.
Scott Lefebvre
> F (530)265-1041
> 8 (530)265-1012
> * [log in to unmask]
>
>
>
>
>
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Date: Fri, 30 Nov 2001 19:51:35 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: Color additives for conformal coat
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Steve
Then my best recommendation is to use the black-light in a suitable
inspection chamber. This will show exactly where the coating is and isn't.
We have special units for this, but if you want details, please let me know
off-line.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Friday, November 30, 2001 06:46
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
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-----
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=========================================================================
Date: Fri, 30 Nov 2001 15:07:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Red plaque on Silver plated wire?
MIME-Version: 1.0
Content-Type: text/plain
Anybody out there ever hear about having to control red plaque on silver
plated wire?
This showed up on a spec for a job we're contemplating.
Any and all ('cept wisecracks) responses appreciated. Thanks.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
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Date: Fri, 30 Nov 2001 15:45:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Color additives for conformal coat
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
I have to second Graham's Black Light suggestion. We had the same
problem/learning curve in a manual coating operation I ran. The Coaters
didn't realize coating on the pins/connectors would be a problem. Sometimes
they were cleaning it best they could but leaving a residue. We'd plug the
assembly in for testing and it would fail. We only had to show them the
assembly under blacklight once to solve the problem.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Friday, November 30, 2001 2:52 PM
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Steve
Then my best recommendation is to use the black-light in a suitable
inspection chamber. This will show exactly where the coating is and isn't.
We have special units for this, but if you want details, please let me know
off-line.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Friday, November 30, 2001 06:46
To: [log in to unmask]
Subject: Re: [TN] Color additives for conformal coat
Graham,
My understanding is that the customer has had problems in the past with a
supplier coating connector pins and is looking for a means to poke-a-yoke
this step for this new board. It does not have to be opaque per say, since
their intent is to look for coverage and excess on the pins.
Thanks for the information.
Steve
-----Original Message-----
From: Graham Naisbitt [mailto:[log in to unmask]]
Sent: Thursday, November 29, 2001 12:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: RE: [TN] Color additives for conformal coat
Steve
Adding anything to the coating after approvals testing will negate its
qualification / approval status.
Why does the customer want a color? Does he want it to be opaque?
We have experimented with pigments and some of them work - what color would
you like? However, they do cause a major problem for the manufacturer,
because that color does not go easily away for subsequent batches.
More particularly, adding pigments can disturb the dielectrical and other
protective characteristics that might be desirable. Check this before you
jump.
If we are talking opaque - then we have to add fillers. These greatly
influence the moisture protection that you DO want from the coating because
they cause an easier path for moist air / water to move through the film.
This is not good and is why the US military called for the use of UV
tracers.
If the customer is trying to hide something - forget it! We can remove any
coating with enough time, patience and enthusiasm!
Hope this helps.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen S. Schiera
Sent: Thursday, November 29, 2001 03:29
To: [log in to unmask]
Subject: [TN] Color additives for conformal coat
I have a current request from a customer for a conformal coat that has a
visible coloring agent such as "red or blue". We currently use an acrylic
coating with a UV trace and UL approval. Does anyone use or know of visible
color traces for coatings?
Thanks in advance
Steve
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 30 Nov 2001 15:52:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Seeger <[log in to unmask]>
Organization: Applied CAD Knowledge Inc
Subject: IPCDC Boston mtg 11-Dec, Current Carrying update
X-To: [log in to unmask], [log in to unmask],
[log in to unmask]
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,
A Current Topic
The Greater Boston Chapter of the IPC Designer's Council will
hold its next meeting on Tuesday, December 11th at the Four
Points Hotel on Totten Pond Rd in Waltham MA at 6pm.
Topic and Speaker:
Michael Jouppi of Coretec, Chairman of the IPC 1-10b Task Group
will present the latest developments in said groups efforts to
update the time honored and widely referenced current carrying
conductor charts. This long needed revamp will shed new light
on everyone's favorite look-up. Most designers have found the
age old charts lacking for current (sorry!) packaging trends.
With today's densities and new and fine geometries (fine lines,
micro or blind vias, embedded passives) new understanding must
be brought to the problems of power handling, including effects
of transients and planes. Tools will be provided.
Agenda:
Please note there is a $15 meeting fee for members, $20 for
non-members. Pizza/soft drinks will be served.
6:00 Arrivals and Pizza
6:45 Chapter Business
7:00 Michael Jouppi, Coretec
Location/Directions:
The Four Points Hotel (fka the Wyndham) in Waltham is located
at exit 27A off route 95/128, proceed east on Totten Pond Rd
and the hotel is on the right.
RSVP's requested:
Please RSVP by sending an email to [log in to unmask] with
the subject "RSVP IPC/DC" or phone Judy Horn at 781 942 7471
by Friday 5pm, Dec 7th. Please treat an RSVP as a commitment
to attend as the food order is based on this.
President's Note:
I'm very glad to have Mr Jouppi available for a presentation,
his background as a Thermal Engineer in several aerospace firms
allows him great insight into the problems of current handling.
His works to date on the Current Carrying Charts update have
made great progress and we can look forward to very insightful
perspective on what may become next year's widely distributed
new standard.
As this meeting falls the day after the normal Steering date
I'd like to ask Steering Committee, and any willing member, to
stay a few minutes after for chapter business.
Mission:
PCB Design is not called "do" for a reason. Done properly,the
design process is a creative problem solving discipline. To
address the packaging needs of electronics for today and to-
morrow, the physical designer needs an avenue to get exposed
and familiar with many different techniques and technologies.
The Greater Boston Chapter of the IPC Designer's Council is
committed to presenting stake holders from every aspect of the
packaging realm. Our hope is to help you gain insight and un-
derstanding of the many possibilities in solving core problems.
Your attendance, help and participation are most welcome.
Thanks and regards,
--
Jeff Seeger Applied CAD Knowledge Inc
Chief Technical Officer Tyngsboro, MA 01879
jseeger "at" appliedcad "dot" com 978 649 9800
President, Greater Boston Chapter, IPC Designer's Council
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=========================================================================
Date: Fri, 30 Nov 2001 16:13:35 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: LLP Leadless LeadFrame Package
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_14e.4e610f8.2939507f_boundary"
--part1_14e.4e610f8.2939507f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
From the design perspective, I don't agree with the supplier recommended data
sheets regarding footprint criteria. As you point out the separation between
large land area and individual I/O lands is very small (ie .002-.005) I
beefed mine up to something like .010. I don't like the solder stencil
pattern either; they would have the paste offset onto the mask by .010-.025.
I didn't do that. The LLP doesn't require special surface finish or exclude
any as some would indicate. First pass success is needed due to quite
challenging to rework. We built quite a few parts to shorts adding the LLP
by hand, never do that it was ugly.
Those are the areas of "gotcha" concerns; every component has their own
gotcha's. I like the LLP package, used as intended it is very nice.
Especially if it is replacing odd form parts.
Brad
--part1_14e.4e610f8.2939507f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>From the design perspective, I don't agree with the supplier recommended data sheets regarding footprint criteria. As you point out the separation between large land area and individual I/O lands is very small (ie .002-.005) I beefed mine up to something like .010. I don't like the solder stencil pattern either; they would have the paste offset onto the mask by .010-.025. I didn't do that. The LLP doesn't require special surface finish or exclude any as some would indicate. First pass success is needed due to quite challenging to rework. We built quite a few parts to shorts adding the LLP by hand, never do that it was ugly.
<BR>
<BR>Those are the areas of "gotcha" concerns; every component has their own gotcha's. I like the LLP package, used as intended it is very nice. Especially if it is replacing odd form parts.
<BR>
<BR>Brad</FONT></HTML>
--part1_14e.4e610f8.2939507f_boundary--
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Date: Fri, 30 Nov 2001 21:09:57 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Red plaque on Silver plated wire?
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Could "Red Plaque" be another way of saying "tarnish"?
If so, dipping the Silver into an antitarnish sounds too easy, there must be
something wrong with this idea?
Rudy Sedlak
RD Chemical Company
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