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Date: Thu, 18 Oct 2001 08:30:51 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Winslow, Hal" <[log in to unmask]>
Subject: Re: HASL Plating Thickness
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Christopher,
I'm not sure if there is an industry standard (from IPC or the like) on
HASL, but I'm sure you can get good information from the HASL User's Group.
Their web page is http://huggroup.org/
I have seen a spec from Teledyne Halco (manufacturer of HASL machines)
giving process guidelines that was pretty good. I imagine you can find a
link to Halco from the HUG site.
You can pretty much spec whatever you like (and your supplier agrees they
can meet) on your fab drawings. I'd be sure to spec both a max and min
thickness, and also define HOW thickness will be measured, as that leads to
another whole area of confusion.
Hal Winslow
Mfg Engineer
Lightchip Optical Networking
-----Original Message-----
From: Christopher Lampron [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 6:02 AM
To: [log in to unmask]
Subject: [TN] HASL Plating Thickness
Hello All,
Is there any specification regarding the max thickness of HASL plated
PCB's. We have recently received a lot of boards where the HASL plating on
the fine pitch device exceeds 3.5 mils. He have an extensive amount of
bridging on these devices now. Any help would be greatly appreciated.
Thanks
Christopher Lampron
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Date: Thu, 18 Oct 2001 08:48:25 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Trimming Leads...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Thomas:
IPC-A-610 is an "acceptability standard" or "workmanship standard" not a
process requirements standard. As you pointed out, rev B attempted to
require a soldering touch-up operation. Rev C properly set the standard
straight by requiring the leads to be visually inspected at 10X and follows
with the words, "as an alternative to visual inspection, the solder
connections may be reflowed." This all comes down to the process being
employed: "solder/cut/solder/inspect" or "solder/cut/inspect" by the
manufacturer, not by a workmanship standard trying to dictate process
requirements. The objective of 610 is provide accept/reject criteria after
processing -- which has been accomplished quite well in Rev C and the
proposed Amendment 1.
Steve Sauer
-----Original Message-----
Subject: Re: [TN] Trimming Leads...
Cutting the leads to length PRIOR to soldering is the best practice.
However, per IPC-A-610B, Section 4.2.2, if you clip leads after soldering
you will need to perform a re-solder function on each lead or inspect each
clipped lead at 10X.
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Date: Thu, 18 Oct 2001 08:50:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lampron, Chris" <[log in to unmask]>
Subject: Re: HASL Plating Thickness
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Thank you Hal
Chris
-----Original Message-----
From: Winslow, Hal [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 8:31 AM
To: [log in to unmask]
Subject: Re: [TN] HASL Plating Thickness
Christopher,
I'm not sure if there is an industry standard (from IPC or the like) on
HASL, but I'm sure you can get good information from the HASL User's Group.
Their web page is http://huggroup.org/
I have seen a spec from Teledyne Halco (manufacturer of HASL machines)
giving process guidelines that was pretty good. I imagine you can find a
link to Halco from the HUG site.
You can pretty much spec whatever you like (and your supplier agrees they
can meet) on your fab drawings. I'd be sure to spec both a max and min
thickness, and also define HOW thickness will be measured, as that leads to
another whole area of confusion.
Hal Winslow
Mfg Engineer
Lightchip Optical Networking
-----Original Message-----
From: Christopher Lampron [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 6:02 AM
To: [log in to unmask]
Subject: [TN] HASL Plating Thickness
Hello All,
Is there any specification regarding the max thickness of HASL plated
PCB's. We have recently received a lot of boards where the HASL plating on
the fine pitch device exceeds 3.5 mils. He have an extensive amount of
bridging on these devices now. Any help would be greatly appreciated.
Thanks
Christopher Lampron
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Date: Thu, 18 Oct 2001 08:51:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Trimming Leads...
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0008_01C157B2.12A234E0"
This is a multi-part message in MIME format.
------=_NextPart_000_0008_01C157B2.12A234E0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I'm with you Steve (going senile, that is.) I consider components like
connectors, sockets, etc. to be in the category of "pre-established lead
lengths." I do not touch them unless there is a special requirement due to
electrical spacing constraints. If that is the case, it should be clearly
defined on the assembly drawing (or better yet designed out before it gets
that far.) Also, cutting tempered leads leads (pun intended) to more
problems than it solves, as others have mentioned.
Speaking of senile, what was the writer thinking of when he or she put a
number like .0591 in 610 and 001? Is it just me, or is four decimal places
inappropriate here? Don't they know there are inspectors who will actually
try to measure that? Yeah, I know the short answer is that it is the decimal
equivalent of 1.5mm. But, couldn't it have been rounded to a more realistic
figure like .06 without losing the intent? The spec seems somewhat
inconsistent in this regard. In other sections, mm equivalents are rounded
to two places (such as .5mm becoming .02") and three places (such as .8mm
becoming .031".) Hopefully future revisions will have pity on us hapless
manufacturing engineers and change things like this. Sorry for the
diversion.
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Wednesday, October 17, 2001 6:05 PM
To: [log in to unmask]
Subject: Re: [TN] Trimming Leads...
Hi David,
Oh yes, I would do that. But again, I'm asking if clipping triple row DIN
connectors, PGA's, machine pin sockets, etc. is a normal deal? Just as a
past practice, I've never clipped leads on devices like that unless it was
specifically called out...and I can't recall if there is something out there
that recommends not clipping devices like that...or that it is not required
because of the design of the leads.
The only thing I can find documented is .0591" max for class-3 boards...
I can understand clipping less robust leads to less than .0591" because of
the possibility that they can be bent and possibly short to each other.
I don't know where I picked it up, but somewhere in the past I was always
under the impression that you didn't clip leads on connectors, PGA's, or
machine pin sockets unless it was specifically called out on a drawing...
I must be going senile...
-Steve Gregory-
------=_NextPart_000_0008_01C157B2.12A234E0
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D310052212-18102001><FONT face=3DArial size=3D2>I'm =
with you=20
Steve (going senile, that is.) I consider components like =
connectors,=20
sockets, etc. to be in the category of "pre-established lead lengths." I =
do not=20
touch them unless there is a special requirement due to electrical =
spacing=20
constraints. If that is the case, it should be clearly defined on the =
assembly=20
drawing (or better yet designed out before it gets that far.) Also, =
cutting=20
tempered leads leads (pun intended) to more problems than it solves, as =
others=20
have mentioned.</FONT></SPAN></DIV>
<DIV><SPAN class=3D310052212-18102001><FONT face=3DArial=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D310052212-18102001><FONT face=3DArial =
size=3D2>Speaking of senile,=20
what was the writer thinking of when he or she put a number like .0591 =
in 610=20
and 001? Is it just me, or is four decimal places inappropriate here? =
Don't they=20
know there are inspectors who will actually try to measure that? Yeah, I =
know=20
the short answer is that it is the decimal equivalent of 1.5mm. But,=20
couldn't it have been rounded to a more realistic figure like =
.06=20
without losing the intent? The spec seems somewhat inconsistent in =
this=20
regard. In other sections, mm equivalents are rounded to two =
places (such=20
as .5mm becoming .02") and three places (such as .8mm becoming .031".) =
Hopefully=20
future revisions will have pity on us hapless manufacturing =
engineers and=20
change things like this. Sorry for the =
diversion. </FONT></SPAN></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV><FONT face=3DArial=20
size=3D2></FONT><FONT face=3DArial size=3D2></FONT><FONT face=3DArial =
size=3D2></FONT><BR>
<P><FONT size=3D2>Bob<BR><BR><BR>Robert Barr<BR>Manufacturing=20
Engineering<BR>Formation, Inc.</FONT> </P>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. =
Gregory<BR><B>Sent:</B>=20
Wednesday, October 17, 2001 6:05 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Trimming=20
Leads...<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi David,=20
<BR><BR>Oh yes, I would do that. But again, I'm asking if clipping =
triple row=20
DIN connectors, PGA's, machine pin sockets, etc. is a normal deal? =
Just as a=20
past practice, I've never clipped leads on devices like that unless it =
was=20
specifically called out...and I can't recall if there is something out =
there=20
that recommends not clipping devices like that...or that it is not =
required=20
because of the design of the leads. <BR><BR>The only thing I can find=20
documented is .0591" max for class-3 boards... <BR><BR>I can =
understand=20
clipping less robust leads to less than .0591" because of the =
possibility that=20
they can be bent and possibly short to each other. <BR><BR>I don't =
know where=20
I picked it up, but somewhere in the past I was always under the =
impression=20
that you didn't clip leads on connectors, PGA's, or machine pin =
sockets unless=20
it was specifically called out on a drawing... <BR><BR>I must be going =
senile... <BR><BR>-Steve Gregory- </FONT><FONT lang=3D0 face=3DArial =
size=3D2=20
FAMILY=3D"SANSSERIF"></BLOCKQUOTE></FONT></FONT></BODY></HTML>
------=_NextPart_000_0008_01C157B2.12A234E0--
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Date: Thu, 18 Oct 2001 13:46:50 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: double sided BGAs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Larry,
Concerning inspection of BGA's I have just purchased kit supplied by a
company called Ersa. They use a form of endoscope that is able to look
between the pcb and the underside of the BGA between the rows of solder
balls. To check if the device has reflowed properly. It also comes with an
extensive fault library wihin it's software.
-----Original Message-----
From: Bill Raymond [mailto:[log in to unmask]]
Sent: 18 October 2001 13:08
To: [log in to unmask]
Subject: Re: [TN] double sided BGAs
I've done up to 35 mm packages (PBGA) with 492 balls, 1.27 mm pitch... the
surface tension was plenty to hold them in place.
Bill...
At 10:51 AM 10/18/2001 +0800, you wrote:
>..........................................................How big are the
>BGA's? It's
>possible that they're light enough for surface tension to hold them in
>place while up-side down during the second solder pass without them falling
>off. Steve Gregory, I think it was, once gave a figure of how much weight
>per contact can be held in place by surface tension of molten solder - was
>it 5 grams per contact? But I don't know if this figure can be applied to
>BGA's with their all-solder contacts. The effects of gravity and other
>forces may distort the solder joints' form enough to reduce their
>reliability.
>
>My tuppence worth (UK value), but hope it helps a little.
>
>Peter Duncan
>
>
>
>
> Larry Koens
> <lwkoens@EIMI To: [log in to unmask]
> CRO.COM> cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> Sent by: Aero/ST Group)
> TechNet Subject: [TN] double sided
BGAs
> <[log in to unmask]
> ORG>
>
>
> 10/18/01
> 12:32 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
>Dear TechNet,
>My company has been asked to bid on assembling a board that would have
>two BGAs on the topside and two more BGAs mirrored on the bottomside.
>That is, they will be directly across from each other on both sides. I
>never done them on both sides. So far, everything that I have done has
>been on one side only. Has anyone done them on both sides before?
>
> I am figuring xray will be a problem as after the second side is
>placed, because the pads/balls will mirror each other on both sides.
>Would I be able to tell the difference between the two BGA connections?
>Suggestions?
>
>Will I need to epoxy the first side BGAs so they would not drop off
>during my second reflow? Wouldn't I need to epoxy them after first
>reflow so that the balls could collapse?
>
>Thanks,
>Larry Koens
>SMT Manufacturing Engineer
>E.I. Microcircuits
>Mankato, MN
>
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Date: Thu, 18 Oct 2001 08:59:41 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Solder Joint Defects
In-Reply-To: <A1630D6F27C0D21198AF00805F613595465847@DDLSBS>
MIME-Version: 1.0
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If you are the customer, the acceptable defect level is 0, regardless of
class. But seriously, I have seen figures published that indicate visual
inspection to be, at best, 80% effective. I think that number probably
varies a lot based on time of day, day before or after a weekend or holiday,
complexity of the board, etc. Rather than setting an acceptable level, I
would concentrate on having a process that is as robust as possible and
having a system that identifies defects before they get out the door.
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Cathy Killen
Sent: Thursday, October 18, 2001 7:34 AM
To: [log in to unmask]
Subject: [TN] Solder Joint Defects
Importance: High
Could anyone help with this.
When visually inspecting PCBs to class 3, is there an acceptable percentage
of faults missed? Also is there an acceptable defect level considering PPM
with regards to soldered joints.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
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Date: Thu, 18 Oct 2001 08:06:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Thomas Highland <[log in to unmask]>
Subject: Re: Trimming Leads...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve:
You are correct. Thanks for your in depth elaboration on the subject matter.
Tom Highland
-----Original Message-----
From: Sauer, Steven T. [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 07:48
To: [log in to unmask]
Subject: Re: [TN] Trimming Leads...
Thomas:
IPC-A-610 is an "acceptability standard" or "workmanship standard" not a
process requirements standard. As you pointed out, rev B attempted to
require a soldering touch-up operation. Rev C properly set the standard
straight by requiring the leads to be visually inspected at 10X and follows
with the words, "as an alternative to visual inspection, the solder
connections may be reflowed." This all comes down to the process being
employed: "solder/cut/solder/inspect" or "solder/cut/inspect" by the
manufacturer, not by a workmanship standard trying to dictate process
requirements. The objective of 610 is provide accept/reject criteria after
processing -- which has been accomplished quite well in Rev C and the
proposed Amendment 1.
Steve Sauer
-----Original Message-----
Subject: Re: [TN] Trimming Leads...
Cutting the leads to length PRIOR to soldering is the best practice.
However, per IPC-A-610B, Section 4.2.2, if you clip leads after soldering
you will need to perform a re-solder function on each lead or inspect each
clipped lead at 10X.
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Date: Thu, 18 Oct 2001 09:06:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: PCMCIA ENCLOSURES
In-Reply-To: <008101c15761$63d2fb20$041e5b0c@pavilion>
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Not sure if this is the correct forum, but I'm in need of some education in
regards to the final stages of packaging a PCMCIA card. I'm specifically
looking for information in regards to the metal case enclosures and
shielding options for the assy once the electronic card is stuffed. Also
looking for leads of vendors who sell the cases and for ballpark average of
cost for the enclosure. Any information is greatly appreciated.
Thanks.
Dean Lillibridge
NEWvENTURE TECHNOLOGIES
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<DIV><SPAN class=3D996030213-18102001><FONT color=3D#0000ff face=3DArial =
size=3D2>Not=20
sure if this is the correct forum, but I'm in need of some education in =
regards=20
to the final stages of packaging a PCMCIA card. I'm specifically =
looking=20
for information in regards to the metal case enclosures and shielding =
options=20
for the assy once the electronic card is stuffed. Also looking for =
leads=20
of vendors who sell the cases and for ballpark average of cost for the=20
enclosure. Any information is greatly=20
appreciated. =20
Thanks.</FONT></SPAN></DIV>
<DIV><SPAN class=3D996030213-18102001><FONT color=3D#0000ff face=3DArial =
size=3D2> &nbs=
p;  =
; =
=20
Dean Lillibridge</FONT></SPAN></DIV>
<DIV><SPAN class=3D996030213-18102001><FONT color=3D#0000ff face=3DArial =
size=3D2> &nbs=
p;  =
; =
=20
NEWvENTURE TECHNOLOGIES</FONT></SPAN></DIV>
<DIV><SPAN class=3D996030213-18102001><FONT color=3D#0000ff face=3DArial =
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Date: Thu, 18 Oct 2001 08:15:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: Trimming Leads...
In-Reply-To: <[log in to unmask]>
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There are a lot of reasons not to trim these types of leads among them are
mechanical shock to the component, damage to the solder connection if
soldered in place (causes fractures during operational cycling), Exposed
base material (usually not copper for these), Damage to the board, etc.
Years past we had specific shear cutters that could perform an OK job on
leads such as DIPs without transferring as much shock to the component but I
would certainly not attempt their use on PGAs.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Charles Caswell
Sent: Wednesday, October 17, 2001 3:47 PM
To: [log in to unmask]
Subject: Re: [TN] Trimming Leads...
If the pins are tempered they should not be trimmed. Also IPC 610 and
J-STD 001 say " should" a recomendation. If they don't cause a problem
in processing. Like catching on the fluxer at wave solder and do not
pose a problem mechanically in the end item you "should not" ( my
recomendation) have to trim. We don't unless specified on the
documentation except where the lenghth causes a problem later.
Charles Caswell
Process Lead, PCB
Frontier Electronic Systems
-----Original Message-----
From: TechNet E-Mail Forum. [mailto:[log in to unmask]]
Sent: Wednesday, October 17, 2001 4:58 PM
To: [log in to unmask]
Subject: [TN] Trimming Leads...
Hi All,
I've got a question about trimming leads on components such as three-row
DIN
connectors, machine pin sockets, PGA devices, things like that...
In the past, I've never trimmed the leads on components like that. But I
can't find any reference that says those are things that you don't lead
clip...
The reason I'm asking is the -610 and J-STD say that for class-3, the
leads
are not supposed to be longer than 1.5mm (.0591"). Should leads be
clipped on
the kind of components I outlined above if they exceed that?
Thanks!!
-Steve Gregory-
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Date: Thu, 18 Oct 2001 14:14:56 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Davies <[log in to unmask]>
Subject: Re: HASL Plating Thickness
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-----Original Message-----
From: Christopher Lampron <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Thursday, October 18, 2001 11:31 AM
Subject: [TN] HASL Plating Thickness
------------------
Christopher
You may look at Chapter 30 of Printed Circuits Materials Handbook
HOT AIR LEVELING
Sherry Goodell
Teledyne Electronic Technologies, Halco
Londonderry, New Hampshire
Frank
----------------------------------
>Hello All,
>
>Is there any specification regarding the max thickness of HASL plated
>PCB's. We have recently received a lot of boards where the HASL plating on
>the fine pitch device exceeds 3.5 mils. He have an extensive amount of
>bridging on these devices now. Any help would be greatly appreciated.
>
>Thanks
>
>Christopher Lampron
>
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Date: Thu, 18 Oct 2001 08:39:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Trimming Leads...
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Is it possible that the customer or end use doesn't need that stingent of =
lead requirments? I have had class 3 where the customer waived the =
requirements for devices like this because the class was mainly chosen for =
placement, cleanliness, and solder but lead length wasn't an issue. It =
also costed more to have them trimemd then to leave them alone so the =
custoemr wanted to save some money.=20
Kathy=20
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style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Is it possible that the customer or end use doesn't need that stingent of
lead requirments? I have had class 3 where the customer waived the
requirements for devices like this because the class was mainly chosen for
placement, cleanliness, and solder but lead length wasn't an issue. It
also costed more to have them trimemd then to leave them alone so the custoemr
wanted to save some money. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 18 Oct 2001 09:41:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Nancy Trumbull <[log in to unmask]>
Subject: Re: Solder Joint Defects
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Cathy,
I was in the process of writing almost the same statement as Bob, when I =
stopped to check and see if any one had answered you yet. I started in =
this field around 1979. I'm not sure when I picked it up first but I have =
always heard that 15 to 20% of defects are leaked by visual inspection.
Therefore my action has always been to try and control the process. I will =
amit that this does get hard sometimes. There are steps you can take to =
aid with your inspection. As a standard process flow, to always view the =
part in the same pattern. But I have always been a person that deals with =
root cause. As you know Leakage perversion will increase as you decrease =
your defects. Hope I said that right.
Just backing up Bob.
Have a good day
Nancy T.
>>> [log in to unmask] 10/18/01 07:33AM >>>
Could anyone help with this.
When visually inspecting PCBs to class 3, is there an acceptable percentage=
of faults missed? Also is there an acceptable defect level considering PPM
with regards to soldered joints.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended =
only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries, =
unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for viruses.
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Date: Thu, 18 Oct 2001 08:45:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Trimming Leads...
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Steve,=20
Are you thinking about the lead length exception for components with =
predefined lead lenths? This is when the PCB is too thick but that is an =
allowance for minimum length not max. =20
Kathy=20
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<DIV>Steve, </DIV>
<DIV> </DIV>
<DIV>Are you thinking about the lead length exception for components with
predefined lead lenths? This is when the PCB is too thick but that is an
allowance for minimum length not max. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 18 Oct 2001 08:30:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Hafften <[log in to unmask]>
Subject: Reject Marking
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Presently we identify rejected parts on multiple up panels after lamination
by using an "X" made with a metal stamp. This stamped "X" creates other
problems during the subsequent circuit board manufacturing process steps
such as an uneven surface for imaging. Does anyone have another method for
marking rejects at lamination.
Thanks in advance for any assistance.
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Date: Thu, 18 Oct 2001 10:00:59 -0400
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Francois Monette <[log in to unmask]>
Subject: Re: double side BGAs
In-Reply-To: <[log in to unmask]>
MIME-version: 1.0
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Larry,
Another major issue is often overlooked for double side boards with moisture
sensitive components on both sides, as in this case.
The key point is that the first reflow does not bake the moisture out of the
components. Moisture diffusion inside a plastic package is a very slow
process and a reflow cycle is much too fast to have any significant impact.
The net result is that the components on the first side continue to absorb
moisture after they are reflowed on the board, in addition to what they had
already absorbed prior to placement. Of course, you need to make sure that
the board will go back through the second reflow before any of the
components, one the top and bottom side have reached the limit of their
floor life.
The outcome is that for double-sided boards you have to account for the
overall exposure time, from the time that all parts were originally taken
out of their dry bags, until the final reflow is complete. This means that
whatever system or procedure you had in place for controlling
moisture-sensitive components must be extended to track partially assembled
boards and their remaining floor life in addition to the remaining floor
life of components prior to placement.
The above requirements are clearly defined in the joint IPC/JEDEC standard
J-STD-033, section 8.4.4 : "If more than one reflow pass is used, care must
be taken to ensure that no moisture sensitive components, mounted or
unmounted, have exceeded their floor life prior to the final pass".
I hope this information is helpful,
Regards,
Francois Monette
Cogiscan Inc.
50 De Gaspe, Suite A5
Bromont, Quebec, Canada, J2L 2N8
Tel : (450)534-2644
Fax: (450)534-0092
www.cogiscan.com
>Dear TechNet,
>My company has been asked to bid on assembling a board that would have
>two BGAs on the topside and two more BGAs mirrored on the bottomside.
>That is, they will be directly across from each other on both sides. I
>never done them on both sides. So far, everything that I have done has
>been on one side only. Has anyone done them on both sides before?
>
> I am figuring xray will be a problem as after the second side is
>placed, because the pads/balls will mirror each other on both sides.
>Would I be able to tell the difference between the two BGA connections?
>Suggestions?
>
>Will I need to epoxy the first side BGAs so they would not drop off
>during my second reflow? Wouldn't I need to epoxy them after first
>reflow so that the balls could collapse?
>
>Thanks,
>Larry Koens
>SMT Manufacturing Engineer
>E.I. Microcircuits
>Mankato, MN
***************
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Date: Thu, 18 Oct 2001 15:43:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: HASL Plating Thickness
X-To: [log in to unmask]
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Even better: you don't have to buy the book, as this chapter 30 is =
available on-line at http://people.ne.mediaone.net/sgoodell/chapter30/ch30.=
html
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Frank Davies <[log in to unmask]> 10/18 2:14 pm >>>
-----Original Message-----
From: Christopher Lampron <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Thursday, October 18, 2001 11:31 AM
Subject: [TN] HASL Plating Thickness
------------------
Christopher
You may look at Chapter 30 of Printed Circuits Materials Handbook
HOT AIR LEVELING
Sherry Goodell
Teledyne Electronic Technologies, Halco
Londonderry, New Hampshire
Frank
----------------------------------
>Hello All,
>
>Is there any specification regarding the max thickness of HASL plated
>PCB's. We have recently received a lot of boards where the HASL plating =
on
>the fine pitch device exceeds 3.5 mils. He have an extensive amount of
>bridging on these devices now. Any help would be greatly appreciated.
>
>Thanks
>
>Christopher Lampron
>
>--------------------------------------------------------------------------=
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>
E-mail Archives
>Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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>
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Date: Thu, 18 Oct 2001 09:33:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Long, Thomas" <[log in to unmask]>
Subject: Aqueous Technologies Corrosion Issue
MIME-Version: 1.0
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We are currently using two separate SMT600CL DI water cleaners to
remove ionics from printed circuit assemblies after a defluxing operation.
The system is strictly DI water since we are not performing any flux removal
during this process. After only 6 months of usage we discovered a
Black-Brown-Orange solid particulate being deposited in the wash chamber on
both machines. Analysis determined the material is Iron Oxide, or more
commonly called "RUST". It turns out that the heating element used during
the drying cycle has become corroded. I don't think that I need to tell all
of you how alarming this is, blowing a metallic oxide onto hardware that is
only being put in this machine to remove ionics. I send this e-mail to the
rest of TechNet to first warn others of a potential design issue with
Aqueous Tech DI cleaners and secondly to obtain feedback from current users
of their machines to see if others have run into the same problem. I am
awaiting a written response from aqueous Technologies on what the fix will
be for this problem.
Thanks
Tom Long
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Date: Thu, 18 Oct 2001 15:55:14 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Brown <[log in to unmask]>
Organization: Xyratex
Subject: PCB depanelling
MIME-Version: 1.0
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People.
Many years ago when I worked on a manufacturing line we used to use a
small hand held "nibbler" for cutting through breakout tabs on PCB
assemblies. I've looked all through the RS and Farnell catalogues and
can't find this tool anywhere. Do any of you have recollections of such
a tool and if so where can I get one from.
Regards.
Steve Brown.
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Date: Thu, 18 Oct 2001 10:09:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: PCB depanelling
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check out FKN
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Date: Thu, 18 Oct 2001 09:13:06 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ryan Grant <[log in to unmask]>
Subject: Re: double sided BGAs
Hi Larry,
I just got through x-ray inspecting some test boards where the FBGA's where
specifically mirrored for solder joint studies. Inspection was not a
problem both because of parallax and the slight misalignment of the source
from being perfectly perpendicular to the board. This all means that if I
try really hard, the planets come into perfect alignment, and I shake the
chicken feet over the x-ray, I can get one joint (and only one joint) to be
perfectly lined up over the other. All other joints are naturally offset
from each other.
The joints will be overlap slightly, and will require some sleuthing to
determine which side a defect belongs to. Further, the overlap of the
joints might cause problems for automated x-ray inspection.
Kind Regards
Ryan Grant
Advanced Technology Engineer
MCMS
(208) 898-1145
[log in to unmask]
> -----Original Message-----
> From: Larry Koens [SMTP:[log in to unmask]]
> Sent: Wednesday, October 17, 2001 10:33 AM
> To: [log in to unmask]
> Subject: [TN] double sided BGAs
>
> Dear TechNet,
> My company has been asked to bid on assembling a board that would have
> two BGAs on the topside and two more BGAs mirrored on the bottomside.
> That is, they will be directly across from each other on both sides. I
> never done them on both sides. So far, everything that I have done has
> been on one side only. Has anyone done them on both sides before?
>
> I am figuring xray will be a problem as after the second side is
> placed, because the pads/balls will mirror each other on both sides.
> Would I be able to tell the difference between the two BGA connections?
> Suggestions?
>
> Will I need to epoxy the first side BGAs so they would not drop off
> during my second reflow? Wouldn't I need to epoxy them after first
> reflow so that the balls could collapse?
>
> Thanks,
> Larry Koens
> SMT Manufacturing Engineer
> E.I. Microcircuits
> Mankato, MN
>
> --------------------------------------------------------------------------
> -------
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Date: Thu, 18 Oct 2001 16:29:05 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: PCB depanelling
MIME-Version: 1.0
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Steve,
We use a bench mounted version of the hand held "nibbler" this gives the
operator more flexibility. They are made by CAB. This is their E mail adress
www.cabgmbh.com.
Tel:- +49/7 21/66 26-222.
-----Original Message-----
From: Stephen Brown [mailto:[log in to unmask]]
Sent: 18 October 2001 15:55
To: [log in to unmask]
Subject: [TN] PCB depanelling
People.
Many years ago when I worked on a manufacturing line we used to use a
small hand held "nibbler" for cutting through breakout tabs on PCB
assemblies. I've looked all through the RS and Farnell catalogues and
can't find this tool anywhere. Do any of you have recollections of such
a tool and if so where can I get one from.
Regards.
Steve Brown.
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Date: Thu, 18 Oct 2001 11:54:39 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Waste water treatment systems...
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boundary="part1_134.3387bda.2900553f_boundary"
--part1_134.3387bda.2900553f_boundary
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Hi all,
I'm looking into waste water treatment systems now, and wonder if any of you
could share what you are doing to treat your waste water?
One of the things that make it a little complicated for me is that we use two
diferent cleaning systems here. I've got an Electrovert H500 that uses only
DI water for our water soluble residues, and then I've got an Electrovert
MCS-1000 that uses DI water and Kyzen Aquanox XJN to clean our RMA residues.
If it wasn't for that, I would think about close-looping everything, but the
Kyzen would kill the resin beds.
I've looked at a system that uses what's called reactant powder in a
flocculation process to remove all contaminates, and was told that I could
either reuse the treated water and go back into my DI system, effectively
close-looping things, or go directly to drain. But we're talking big bucks
for this system, $ 65,000 - 80,000. Then there's also the cost of the
reactant powder...anywhere from 3 - 6 cents a gallon to treat the water.
Just asking for some other ideas of what others do with their water, and what
else I could do before going to drain with it.
As always, thanks a million!
-Steve Gregory-
--part1_134.3387bda.2900553f_boundary
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Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Hi all,
<BR>
<BR>I'm looking into waste water treatment systems now, and wonder if any of you could share what you are doing to treat your waste water?
<BR>
<BR>One of the things that make it a little complicated for me is that we use two diferent cleaning systems here. I've got an Electrovert H500 that uses only DI water for our water soluble residues, and then I've got an Electrovert MCS-1000 that uses DI water and Kyzen Aquanox XJN to clean our RMA residues. If it wasn't for that, I would think about close-looping everything, but the Kyzen would kill the resin beds.
<BR>
<BR>I've looked at a system that uses what's called reactant powder in a flocculation process to remove all contaminates, and was told that I could either reuse the treated water and go back into my DI system, effectively close-looping things, or go directly to drain. But we're talking big bucks for this system, $ 65,000 - 80,000. Then there's also the cost of the reactant powder...anywhere from 3 - 6 cents a gallon to treat the water.
<BR>
<BR>Just asking for some other ideas of what others do with their water, and what else I could do before going to drain with it.
<BR>
<BR>As always, thanks a million!
<BR>
<BR>-Steve Gregory- </FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SERIF" FACE="Times New Roman" LANG="0">
<BR>
<BR></FONT></HTML>
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Date: Thu, 18 Oct 2001 12:16:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: PCB depanelling
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I think I know what you mean. If it's what I am thinking of, I have one at
home I use for light sheet metal work. Go to the following Techni-Tool page,
search on 'nibbler' and three models will show up. You can then click on the
part numbers for pictures. Hope this helps.
https://webvia.techni-tool.com/via4/index.html
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen Brown
Sent: Thursday, October 18, 2001 10:55 AM
To: [log in to unmask]
Subject: [TN] PCB depanelling
People.
Many years ago when I worked on a manufacturing line we used to use a
small hand held "nibbler" for cutting through breakout tabs on PCB
assemblies. I've looked all through the RS and Farnell catalogues and
can't find this tool anywhere. Do any of you have recollections of such
a tool and if so where can I get one from.
Regards.
Steve Brown.
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Date: Thu, 18 Oct 2001 09:30:31 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Solder mask opening...
MIME-Version: 1.0
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All,
If we want to add openings in the solder mask for probing 50 ohm lines
to measure DC bias levels during ICT, do we need to add a test point to
the netlist to make this work? We would prefer not.
Any help will be greatly appreciated.
Re,
Ken Patel
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Date: Thu, 18 Oct 2001 12:44:41 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Reject Marking
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey Ken,
You'd think x-outs would be a no-brainer but Mr. Murphy frequently visits
the shop floor.
Relocate the stamped X to the panel boarder (seems it would only work well
on low count panels - 2-up or 4-up).
Use a permanent marker sparingly (2 X's 1 - front & 1 - back. Make sure the
ink can't wash off in any of the downstream steps and doesn't contaminate
baths (plating, developer, stripper, etc.). Photoresist pens would work but
I'm not sure they would be worth the expense. Why operators feel the need
to completely paint a board is beyond me. <it's fun - Hans>.
I've seen small holes punched out - for x-outs and cross-sections. This can
cause additional downstream process problems - photoresist chips in Imaging
(causing opens & shorts), broken drill bits.
If it is a two or four up I've also seen corners clipped.
Personally, I've hand stamped the frames (with x & y coordinates) but that
was for engineering stuff not production.
If the X-out is on the panel's boarder then the Route guys & gals have to be
on their toes - otherwise you'll pass bad boards to Test/Final Inspect.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Ken Hafften [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 9:30 AM
To: [log in to unmask]
Subject: [TN] Reject Marking
Presently we identify rejected parts on multiple up panels after lamination
by using an "X" made with a metal stamp. This stamped "X" creates other
problems during the subsequent circuit board manufacturing process steps
such as an uneven surface for imaging. Does anyone have another method for
marking rejects at lamination.
Thanks in advance for any assistance.
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Date: Thu, 18 Oct 2001 12:39:26 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Vapor Phase Soldering material
MIME-Version: 1.0
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Brian,=20
I'm getting conflicting comments from someone from 3M who is claiming =
that
Fluorinert will decompose at temperatures of 200C and above and this is =
not
a good thing in the presence of water (usually available as moisture in =
the
air). Any comments?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>=20
631-595-5879
-----Original Message-----
From: Brian Ellis [SMTP:[log in to unmask]]
Sent: Wednesday, October 17, 2001 2:38 AM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
Back in the days? Vapour-phase soldering is still done! The great
advantages of perfluorocarbons over other halocarbons are that a)
they
are chemically extremely stable because the C-F covalent bond
requires
much energy to break them; b) they are virtually non-toxic (for the
same
reason: they do not break down in the body). In fact they can be
used to
replace blood in the body for short periods as they do allow oxygen
to
be dissolved and some "sportsmen" have even injected PFCs into the
bloodstream to improve their endurance performance by a higher
oxygenation; c) they are very inert chemically; d) they withstand
high
temperatures; e) they are NOT ozone-depleting. Teflon is a solid
PFC.
The disadvantages are a) that they are very expensive; b) they are
EXTREMELY global-warming (typically 1 kg of PFC is equivalent to 10
tonnes of carbon dioxide which is roughly equivalent to half the
emissions of a medium car during its lifetime); c) their stability
(~10,000 years atmospheric residence time) is such that end-of-life
disposal is very difficult and costly.
The fluids, be they pure PFCs or PFEs, used for soldering are
sufficiently stable at 210 - 260=B0C that there is little significant
decomposition. Water hardly enters into the equation because it is
boiled off instantaneously, even if there be some condensation on
the
cooling coils. Theoretically, there may be some hydrogen fluoride
generated (no hydrofluoric acid), but I believe that the quantities
would be really negligible, in practice. With the presence of other
organics from the flux residues, I would personally be more
concerned
with trifluoroacetic acid, another nasty, but I have not heard of
any
cases. Carbonyl fluoride is also not to be excluded, also very
toxic.
There is another fluoro-compound, whose name escapes me for the
moment,
which did cause some concern in the early days, which is toxic in
the
ppb range. However, in practice, I have never heard of any of these
toxic substances being present in sufficient quantity to be of
practical
concern.
The real crunch comes when there is a secondary blanket, used in the
early days to reduce losses of the primary fluid. This was initially
always a pure CFC-113 (e.g., Freon TF, Arklone P etc.). Later,
because
of the ozone depletion potential of CFC-113 being as high as 0.8, a
lower BP PFC was also proposed. CFC-113 does decompose at the vapour
temperature of the primary fluid, so that the interface zone between
the
two vapours was always a hotbed of chemical reactions. This
certainly
produced, especially in the presence of water, whose BP was higher
than
that of the secondary fluid, a whole panoply of acids and other
toxic
substances. For this reason, these machines had both a molecular
sieve
to de-water the condensed vapours, but also a filter to remove the
acids, otherwise the stainless steel tank corroded into holes in a
matter of months. It is possibly this that you are thinking of. The
most
important decomposition product was hydrogen chloride, which becomes
hydrochloric acid in the presence of water, but there was also
phosgene,
hydrogen fluoride, trichloroacetic acid and goodness knows what
else. I
feel reasonably certain (abstraction of any environmental effects),
if
vapour phase soldering with a CFC-113 secondary blanket were
invented
for the first time today, it would never be allowed into a workshop
because of the H&S aspects.
Hope this makes it clear.
Brian
"Marsico, James" wrote:
>
> Back in the days of vapor phase soldering, I seem to recall that
> hydrofluoric acid was a bi-product of the fluorinert mixed with
water, or
> was it the Freon mixed with the fluorinert? Could anyone
elaborate?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>
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Date: Thu, 18 Oct 2001 11:25:13 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dave Pahlas <[log in to unmask]>
Subject: Hole Diameters for ENIG Press-fit
Hello All,
I am working with a customer to determine the optimal finished hole diameter
for press-fit connectors in a Gold finish PCB. The supplier's data sheet for
the connector specifies .024"+/-.002" HASL plated holes. We have learned
from experience that the connector insertion success rate is greatly
improved when using a slightly larger hole on a gold finish PCB since it is
less compliant with the connector pins then the soft HASL.
So far, the supplier has not given a recommendation on the diameter for
gold, so I am looking for other industry standards to validate our findings.
Any help would be greatly appreciated.
Dave Pahlas
Mfg Engineer
(208) 898-1072
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Date: Thu, 18 Oct 2001 13:43:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Book Review - Coombs "Printed Circuit Handbook"
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Title: Printed Circuit Handbook
Author(s): Clyde M. Coombs, Editor
Publisher: McGraw-Hill Professional Publishing
Date Published: August 2001
Edition: Fifth
Pages: 1200
ISBN: 0071350160
If the building were on fire, on the way out the door, I'd grab the picture
of my wife from my desk and from the bookshelf my copies of Coombs' "Printed
Circuit Handbook" and Kline-Wassink's "Soldering In Electronics".
The "Printed Circuits Handbook" is THE printed circuit answer book,
resolving more workaday questions than any other single source in
electronics, covering the fundamentals of printed circuit design,
fabrication, assembly, test, and quality. Top contributors from Motorola,
Cisco, Compaq, Agilent, Hewlett-Packard, and other major companies have
authored chapters.
This handbook does everything correct. Even with almost 50 chapter authors,
the book refers to material in other chapters, has minimal repetition
between chapters, is well written and edited, and contains a comprehensive
glossary and an index that is useful. AND it includes a CD-ROM with the
entire book in searchable format [although only one chapter at a time],
which is very cool, because when you need an answer, there are few things
more frustrating than being unable to find the answer that you KNOW is in
the book.
As the reader would expect by the time a book reaches this level of
refinement, improvements to the "Printed Circuits Handbook", which is an
outstanding book, are incremental. Owners of the fourth edition should
determine if the improved chapter-to-chapter flow, the rewritten and focused
chapters, and the updated and expanded content of this edition suit their
needs.
The book contains 60 chapters grouped in the following ten sections:
Section 1: "Introduction To Printed Circuits" introduces electronic
packaging and high-density interconnect, semiconductor packaging, advanced
packaging [i.e., SOP/SOC, MCM, etc.], and the types of printed wiring
boards.
Section 2: "Materials" discusses base materials and their components,
fabrication processes, and properties; issues of increasing densities;
properties of base materials that require qualification; HDI microvia
materials; and laminate qualification and testing.
Section 3: "Engineering And Design" overviews physical characteristics of
PCB; design process; electrical and mechanical design parameters; controlled
impedance; multilayer design considerations; and manufacturing issues of
planning, information requirements, and contract assembly.
Section 4: "High-Density Interconnect" covers HDI generally and the
specifics of build-up and microvia technologies.
Section 5: "Fabrication Processes" focuses on drilling, imaging, plating
[i.e., electroplating, direct plating, electroless copper], etching and
resists, machining, and testing of bare boards.
Section 6: "Assembly" concentrates on the production processes for printed
circuit assemblies.
Section 7: "Soldering" addresses design for soldering and solderability,
solder materials and processes, no-clean assembly process, lead-free
soldering, fluxes and cleaning, and press-fit connections.
Section 8: "Quality Control And Reliability" describes acceptability of
fabricated boards and assemblies, assembly inspection, design for testing,
loaded board testing, and printed circuit assembly and component-to-PWB
reliability.
Section 9: "Environmental Issues And Waste Treatment" reviews the changing
environment for process waste minimization and treatment for board
fabricators.
Section 10: "Flexible Circuits" outlines applications and materials, design,
manufacturing, termination, special constructions, and quality assurance of
flexible circuits
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Date: Thu, 18 Oct 2001 19:38:52 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: gfalconer <[log in to unmask]>
Subject: Resin recession
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Hi All,
Can anyone tell me the difference between resin recession and holewall
pull away of the copper barrel from the holewall? What can cause these
conditions to occur? What can be done to prevent them? And should boards
with either present be rejected?
Regards
Gordon
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<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Hi All,<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Can anyone tell me the difference between resin =
recession
and holewall pull away of the copper barrel from the holewall? <span
style=3D'mso-spacerun:yes'>=A0</span>What can cause these conditions to =
occur? What
can be done to prevent them? And should boards with either present be =
rejected?<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Regards<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><span style=3D'mso-spacerun:yes'>=A0</span>Gordon =
<o:p></o:p></span></font></p>
</div>
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=========================================================================
Date: Thu, 18 Oct 2001 15:01:42 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Randy Brooks <[log in to unmask]>
Subject: What Causes Dlamination
Mime-Version: 1.0
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Multilayer delamination after SMT (FR-4 material)
Can anyone give me what are the most common cause(s) for delamination of
multilayer boards.
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
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Date: Thu, 18 Oct 2001 18:48:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Seeking info on cleaning PWAs with soldered BGAs using ultrasonics
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10/18/2001
Anyone out there have any information on using ultrasonics for cleaning =
of a daughter-board PWA that has BGA soldered in place. I recall in the =
old military days, ultrasonic cleaning was a no-no because of fear of =
destroying electrical bonds within individual parts. I know times have =
changed and some folks allow use of ultrasonics. J-STD-001 allows it =
subject to the supplier proving documentation that there will be no =
mechanical damage or electrical problems. What ultrasonic cleaning =
process paramaters do we need to control? Any specific process details =
would be appreciated. Any good technical reference documents would also =
help. Please respond to Les Bogert [log in to unmask]
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<DIV><FONT face=3DArial size=3D2>10/18/2001</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Anyone out there have any information =
on using=20
ultrasonics for cleaning of a daughter-board PWA that has BGA soldered =
in=20
place. I recall in the old military days, ultrasonic cleaning was =
a no-no=20
because of fear of destroying electrical bonds within individual=20
parts. I know times have changed and some folks allow use of=20
ultrasonics. J-STD-001 allows it subject to the supplier proving=20
documentation that there will be no mechanical damage or electrical=20
problems. What ultrasonic cleaning process paramaters do we need =
to=20
control? Any specific process details would be appreciated. =
Any good=20
technical reference documents would also help. Please respond to =
Les=20
Bogert <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>.</FONT></DIV></BODY></HTML>
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=========================================================================
Date: Thu, 18 Oct 2001 19:04:42 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sherry Goodell <[log in to unmask]>
Subject: Re: HASL Plating Thickness
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The Chapter 30 is also available at www.huggroup.org and the transfer times
should be much faster. There is additional capability information there as
well.
----- Original Message -----
From: "d. terstegge" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 18, 2001 7:43 AM
Subject: Re: [TN] HASL Plating Thickness
Even better: you don't have to buy the book, as this chapter 30 is available
on-line at http://people.ne.mediaone.net/sgoodell/chapter30/ch30.html
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Frank Davies <[log in to unmask]> 10/18 2:14 pm >>>
-----Original Message-----
From: Christopher Lampron <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Thursday, October 18, 2001 11:31 AM
Subject: [TN] HASL Plating Thickness
------------------
Christopher
You may look at Chapter 30 of Printed Circuits Materials Handbook
HOT AIR LEVELING
Sherry Goodell
Teledyne Electronic Technologies, Halco
Londonderry, New Hampshire
Frank
----------------------------------
>Hello All,
>
>Is there any specification regarding the max thickness of HASL plated
>PCB's. We have recently received a lot of boards where the HASL plating on
>the fine pitch device exceeds 3.5 mils. He have an extensive amount of
>bridging on these devices now. Any help would be greatly appreciated.
>
>Thanks
>
>Christopher Lampron
>
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Date: Thu, 18 Oct 2001 18:06:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Info about IPC email forums
X-To: [log in to unmask], [log in to unmask], [log in to unmask]
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properly handle MIME multipart messages.
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This is an advisory message of just some of the current FREE peer-to-peer =
forums provided by your IPC. For information on how to sign on and for =
options, go to http://www.ipc.org/html/forum.htm If you have any =
questions please contact me personnally off-net: [log in to unmask]
Cordially,
Jack Crawford
Director of Assembly Standards and Technology
TechNet=20
This peer networking forum can be used to ask others for technical help, =
comments or questions on IPC specifications, or other technical inquiries. =
IPC will also use TechNet to announce meetings, important technical =
issues, surveys, etc. As a general networking forum, any technical =
question is fair game.=20
Discussion of pricing is not appropriate for TechNet. Requests for =
recommendations of products or suppliers are appropriate when responses =
are sent to the individual requesting the information only and not to the =
entire TechNet forum.=20
Leadfree
Lead elimination is a fast emerging topic in the PWB industry. Pressure =
from Japan and Europe is forcing US companies to react fast and prepare =
for the transition. This forum acts as a peer interaction resource for =
staying on top of lead elimination activities worldwide and within IPC, =
including updates on the IPCWorks99 conference and lead elimination =
roadmap. A separate IPC forum (NoLeadTech) is available to exchange =
research and implementation technical data derived from research experiment=
s. (See additional info on ComplianceNet)
NoLeadTech
Electronic manufacturing utilizing lead-free processes is beginning to =
mature but there are still implementation issues to be resolved. This =
forum acts as a peer interaction resource to make technical inquiries and =
to exchange research and implementation TECHNICAL DATA derived from =
research experiments. A separate IPC forum (Leadfree) is available for =
discussion of legislative, environmental and philosophical issues related =
to lead-free policies.
Halogenfree
The green monster has struck again, as materials suppliers and PWB =
fabricators are receiving OEM requirements for environmentally friendly =
base materials, soldermask and components. The OEM-targeted materials =
include bromine, halogen, halide and chlorine.
Materials suppliers are now left with the questions: What particle count =
determines halogen-free, bromine-free, etc.? Will the alternative =
materials guarantee the same reliability? Why are we doing this?=20
This email forum serves a basis for peer interaction on the issue. =
Subscribers to the forum from all over the world can discuss the issues, =
dispel the myths and help each other in making the transition to these =
green materials a smooth ride. This forum will also be the basis for =
updates on a white paper being developed by the IPC Halogen-Free Materials =
Task Group.
ComplianceNet
The ComplianceNet forum covers environmental, safety and related regulation=
s or issues. In addition to giving you a forum for exchanging information =
with your colleagues and IPC staff, and getting information you need to do =
your jobs today, IPC will provide the following information on ComplianceNe=
t:=20
Regulatory proposals, alerts and draft comments=20
Legislative updates=20
New regulatory interpretations (i.e., photoresist skins)=20
Grass roots action alerts=20
Compliance assistance
IPC_New_Releases
Provides notification to subscribers when new and revised IPC publications =
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Date: Thu, 18 Oct 2001 20:21:37 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Seeking info on cleaning PWAs with soldered BGAs using
ultrasonics
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Hi Bogert,
I would call and talk to someone at CAE Ultrasonics, I feel they have been
one of the industry leaders in developing safe ultrasonic cleaning for
electronics. Go to:
http://www.caeultrasonics.com/
Another company that has been actively producing systems to clean electronic
assemblies is Crest Ultrasonics. Go to:
http://www.crest-ultrasonics.com/home.html
I think it's like you said, back in the past, ultrasonic cleaning was
discouraged, and for good reason back then. Most ultrasonic transducers
produced the ultrasonic energy at lower frequencies and stayed at a single
frequency. Lower frequencies generate larger cavitation bubbles and excite a
part into resonance which causes the damage that everyone worried about.
Nowdays, the technology has advanced far from what it was years ago, and
transducers are made to transmit ultrasonic energy at the higher frequencies,
and with what is called non-uniform sweep rates that vary the frequencies
slightly so that resonances can't form and so that there won't be "Hot spots"
forming in certain areas of the cleaning tanks..ie: corners,etc.
Here's another link that you're probably familiar with, of the IPC-TM-650
test to determine the sensitivity of electronic assemblies to ultrasonic
cleaning, that personally, I think is a hold-over from the old days when
ultrasonics (at the time) wasn't a good thing:
http://www.ipc.org/html/2.6.9.1.pdf
I work at a contract assembly company, and have tried to feel out some of our
customers as to what their opnions are regarding ultrasonic cleaning, and
it's a tough sell...even with all the advancements that have been made with
the technology. Being able to use ultrasonics would solve a lot of issues
that I (we) face in cleaning, and I feel would provide superior results to
many methods and chemistries that are in place now...but you have to change a
lot of perceptions that were set in stone years ago.
I really think there's a lot of misplaced concern with the technology as it
stands currently...but that's only my opinion.
-Steve Gregory-
> 10/18/2001
>
> Anyone out there have any information on using ultrasonics for cleaning of
> a daughter-board PWA that has BGA soldered in place. I recall in the old
> military days, ultrasonic cleaning was a no-no because of fear of
> destroying electrical bonds within individual parts. I know times have
> changed and some folks allow use of ultrasonics. J-STD-001 allows it
> subject to the supplier proving documentation that there will be no
> mechanical damage or electrical problems. What ultrasonic cleaning process
> paramaters do we need to control? Any specific process details would be
> appreciated. Any good technical reference documents would also help.
> Please respond to Les Bogert <A HREF="mailto:[log in to unmask]">[log in to unmask]</A>.
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Bogert,
<BR>
<BR>I would call and talk to someone at CAE Ultrasonics, I feel they have been one of the industry leaders in developing safe ultrasonic cleaning for electronics. Go to:
<BR>
<BR>http://www.caeultrasonics.com/
<BR>
<BR>Another company that has been actively producing systems to clean electronic assemblies is Crest Ultrasonics. Go to:
<BR>
<BR>http://www.crest-ultrasonics.com/home.html
<BR>
<BR>I think it's like you said, back in the past, ultrasonic cleaning was discouraged, and for good reason back then. Most ultrasonic transducers produced the ultrasonic energy at lower frequencies and stayed at a single frequency. Lower frequencies generate larger cavitation bubbles and excite a part into resonance which causes the damage that everyone worried about.
<BR>
<BR>Nowdays, the technology has advanced far from what it was years ago, and transducers are made to transmit ultrasonic energy at the higher frequencies, and with what is called non-uniform sweep rates that vary the frequencies slightly so that resonances can't form and so that there won't be "Hot spots" forming in certain areas of the cleaning tanks..ie: corners,etc.
<BR>
<BR>Here's another link that you're probably familiar with, of the IPC-TM-650 test to determine the sensitivity of electronic assemblies to ultrasonic cleaning, that personally, I think is a hold-over from the old days when ultrasonics (at the time) wasn't a good thing:
<BR>
<BR>http://www.ipc.org/html/2.6.9.1.pdf
<BR>
<BR>I work at a contract assembly company, and have tried to feel out some of our customers as to what their opnions are regarding ultrasonic cleaning, and it's a tough sell...even with all the advancements that have been made with the technology. Being able to use ultrasonics would solve a lot of issues that I (we) face in cleaning, and I feel would provide superior results to many methods and chemistries that are in place now...but you have to change a lot of perceptions that were set in stone years ago.
<BR>
<BR>I really think there's a lot of misplaced concern with the technology as it stands currently...but that's only my opinion.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">10/18/2001
<BR>
<BR>Anyone out there have any information on using ultrasonics for cleaning of a daughter-board PWA that has BGA soldered in place. I recall in the old military days, ultrasonic cleaning was a no-no because of fear of destroying electrical bonds within individual parts. I know times have changed and some folks allow use of ultrasonics. J-STD-001 allows it subject to the supplier proving documentation that there will be no mechanical damage or electrical problems. What ultrasonic cleaning process paramaters do we need to control? Any specific process details would be appreciated. Any good technical reference documents would also help. Please respond to Les Bogert <A HREF="mailto:[log in to unmask]">[log in to unmask]</A>.
<BR></BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
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Date: Thu, 18 Oct 2001 21:08:43 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Internal Damage to Capacitor
X-To: [log in to unmask]
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Hi all!
Alejandro Becerra sent me an email asking to post some pictures for him, and
the following message that I've pasted below. Go to:
http://www.stevezeva.homestead.com
Read his question and check out his images...
-Steve Gregory-
In a message dated 10/18/2001 5:57:21 PM Central Daylight Time,
[log in to unmask] writes:
>
> I've read that it is possible to load pictures to your web page. Please let
> me know if you can get them to your page because I have a question to the
> forum.
>
>
> We have a failure due to a leakage in one ceramic chip capacitor. Cross
> section showed that the a damage in the capacitor. The damage has a
> elliptical shape and it is longitudinal to the length of the capacitor.
> I've seen Thermal Shock damage in this direction. Is it possible to be a
> Thermal Shock Failure or it could be a pre-existent void in the capacitor?
> Thanks,
> Alejandro Becerra
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Alejandro Becerra sent me an email asking to post some pictures for him, and the following message that I've pasted below. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>Read his question and check out his images...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>In a message dated 10/18/2001 5:57:21 PM Central Daylight Time, [log in to unmask] writes:
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Steve, </BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I've read that it is possible to load pictures to your web page. Please let me know if you can get them to your page because I have a question to the forum.
<BR>
<BR>The problem is the following:</BLOCKQUOTE> </FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">We have a failure due to a leakage in one ceramic chip capacitor. Cross section showed that the a damage in the capacitor. The damage has a elliptical shape and it is longitudinal to the length of the capacitor.</FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I've seen Thermal Shock damage in this direction. Is it possible to be a Thermal Shock Failure or it could be a pre-existent void in the capacitor?</FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Thanks,
<BR>Alejandro Becerra
<BR></BLOCKQUOTE>
<BR>
<BR></FONT></HTML>
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Date: Thu, 18 Oct 2001 20:05:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Steffen, Don E" <[log in to unmask]>
Subject: Re: What Causes Dlamination
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From my experience of Multilayer delamination of FR4 was because of over
stress because of temperature. The delamination was caused because of
moisture entrapment and then being subject to a spike in temperature.
-----Original Message-----
From: Randy Brooks [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Thursday, October 18, 2001 5:02 PM
To: [log in to unmask]
Subject: [TN] What Causes Dlamination
Multilayer delamination after SMT (FR-4 material)
Can anyone give me what are the most common cause(s) for delamination of
multilayer boards.
_________________________________________________________________
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<P><FONT SIZE=3D2>From my experience of Multilayer delamination of FR4 =
was because of over stress because of temperature. The delamination was =
caused because of moisture entrapment and then being subject to a spike =
in temperature.</FONT></P>
<BR>
<BR>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Randy Brooks [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</F=
ONT>
<BR><FONT SIZE=3D2>Sent: Thursday, October 18, 2001 5:02 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] What Causes Dlamination</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>Multilayer delamination after SMT (FR-4 =
material)</FONT>
</P>
<P><FONT SIZE=3D2>Can anyone give me what are the most common cause(s) =
for delamination of</FONT>
<BR><FONT SIZE=3D2>multilayer boards.</FONT>
</P>
<BR>
<BR>
<P><FONT =
SIZE=3D2>_______________________________________________________________=
__</FONT>
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Date: Fri, 19 Oct 2001 14:24:59 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Brass/Stainless Stencil Lifetimes????
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Hey Technetters,
I am just trying to cost replacements and establish replacement periods for
Stencils. Has anyone got any idea how many applications there are in a
brass or stainless stencil before they start to stencil poor paste
profiles??? I assume deterioration starts from day one, but in the case of
stainless stencils with apetures of 0.4mm pitch (QFP's), surely there is an
approximate number of applications before the paste application begins to
cause faults??? Is this the same for brass stencils, but at a faster
rate???
Any help would be appreciated!!
Cheers
Mike
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<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=760441601-19102001>Hey
Technetters,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=760441601-19102001>I am
just trying to cost replacements and establish replacement periods for
Stencils. Has anyone got any idea how many applications there are in a
brass or stainless stencil before they start to stencil poor paste
profiles??? I assume deterioration starts from day one, but in the
case of stainless stencils with apetures of 0.4mm pitch (QFP's), surely there is
an approximate number of applications before the paste application begins to
cause faults??? Is this the same for brass stencils, but at a faster
rate??? </SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=760441601-19102001>Any
help would be appreciated!!</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001>Cheers</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=760441601-19102001>Mike</SPAN></FONT></DIV></BODY></HTML>
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Date: Thu, 18 Oct 2001 22:02:18 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Brass/Stainless Stencil Lifetimes????
MIME-Version: 1.0
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boundary="part1_4d.12f868b3.2900e3aa_boundary"
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Hi Mike!
I was told once a while back by the owner of Screen Manufacturing
Technologies, by Bob Jillings (before Alpha Metals bought him out), that a
stainless steel stencil should last for at least 10,000 prints...but that was
before the wide use of metal squeegee blades. But brass stencils? Hmmmm...I
must say, those should be on the "Antiques Roadshow" hehehe...haven't seen a
brass stencil in at least a decade...
Realistically, it's more likely that a stencil will become unusable because
of damage due to handling or cleaning, than of pure use...then it becomes a
rather "iffy" proposition to predict its life...
It's been my experience that a stencil, if cared of properly, will last
longer than the product being built will, or at least until the board design
rolls, in which case you'll need a new stencil anyway...
-Steve Gregory-
> Hey Technetters,
>
> I am just trying to cost replacements and establish replacement periods for
> Stencils. Has anyone got any idea how many applications there are in a
> brass or stainless stencil before they start to stencil poor paste
> profiles??? I assume deterioration starts from day one, but in the case
> of stainless stencils with apetures of 0.4mm pitch (QFP's), surely there is
> an approximate number of applications before the paste application begins
> to cause faults??? Is this the same for brass stencils, but at a faster
> rate???
>
> Any help would be appreciated!!
>
> Cheers
>
> Mike
>
>
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Mike!
<BR>
<BR>I was told once a while back by the owner of Screen Manufacturing Technologies, by Bob Jillings (before Alpha Metals bought him out), that a stainless steel stencil should last for at least 10,000 prints...but that was before the wide use of metal squeegee blades. But brass stencils? Hmmmm...I must say, those should be on the "Antiques Roadshow" hehehe...haven't seen a brass stencil in at least a decade...
<BR>
<BR>Realistically, it's more likely that a stencil will become unusable because of damage due to handling or cleaning, than of pure use...then it becomes a rather "iffy" proposition to predict its life...
<BR>
<BR>It's been my experience that a stencil, if cared of properly, will last longer than the product being built will, or at least until the board design rolls, in which case you'll need a new stencil anyway...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hey Technetters,</FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">I am just trying to cost replacements and establish replacement periods for Stencils. Has anyone got any idea how many applications there are in a brass or stainless stencil before they start to stencil poor paste profiles??? I assume deterioration starts from day one, but in the case of stainless stencils with apetures of 0.4mm pitch (QFP's), surely there is an approximate number of applications before the paste application begins to cause faults??? Is this the same for brass stencils, but at a faster rate??? </FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Any help would be appreciated!!</FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Cheers</FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></FONT><FONT COLOR="#0000ff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Mike</FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT><FONT COLOR="#0f0f0f" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>
<BR></BLOCKQUOTE>
<BR></FONT></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Thu, 18 Oct 2001 20:33:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Maxwell <[log in to unmask]>
Subject: Re: Internal Damage to Capacitor
In-Reply-To: <[log in to unmask]>
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> This message is in MIME format. Since your mail reader does not understand
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--B_3086282020_415214
Content-type: text/plain; charset="US-ASCII"
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on 10/18/01 7:08 PM, Stephen R. Gregory at [log in to unmask] wrote:
> Hi all!
>
> Alejandro Becerra sent me an email asking to post some pictures for him, and
> the following message that I've pasted below. Go to:
>
> http://www.stevezeva.homestead.com
>
> Read his question and check out his images...
>
> -Steve Gregory-
>
> In a message dated 10/18/2001 5:57:21 PM Central Daylight Time,
> [log in to unmask] writes:
>
>
> Steve,
>
>
>> I've read that it is possible to load pictures to your web page. Please let
>> me know if you can get them to your page because I have a question to the
>> forum.
>>
>> The problem is the following:
>
>
> We have a failure due to a leakage in one ceramic chip capacitor. Cross
> section showed that the a damage in the capacitor. The damage has a elliptical
> shape and it is longitudinal to the length of the capacitor.
>
>
> I've seen Thermal Shock damage in this direction. Is it possible to be a
> Thermal Shock Failure or it could be a pre-existent void in the capacitor?
>
>
>> Thanks,
>> Alejandro Becerra
>>
>>
>>
Without sectioning the beast myself it appears from the two views that you
could be looking at a knit line failure or delamination. Again from the
images there appears to be three electrodes with the void at one end. The
rough edges are due to excessive polishing pressure and the brittle nature
of the ceramic.
John
--B_3086282020_415214
Content-type: text/html; charset="US-ASCII"
Content-transfer-encoding: quoted-printable
<HTML>
<HEAD>
<TITLE>Re: [TN] Internal Damage to Capacitor</TITLE>
</HEAD>
<BODY>
<FONT FACE=3D"Verdana">on 10/18/01 7:08 PM, Stephen R. Gregory at SteveZeva@A=
OL.COM wrote:<BR>
<BR>
</FONT><BLOCKQUOTE><FONT FACE=3D"Verdana"><FONT SIZE=3D"2">Hi all! <BR>
<BR>
Alejandro Becerra sent me an email asking to post some pictures for him, an=
d the following message that I've pasted below. Go to: <BR>
<BR>
http://www.stevezeva.homestead.com <BR>
<BR>
Read his question and check out his images... <BR>
<BR>
-Steve Gregory- <BR>
<BR>
In a message dated 10/18/2001 5:57:21 PM Central Daylight Time, BecerraA@tc=
e.com writes: <BR>
<BR>
<BR>
Steve, <BR>
<BR>
</FONT></FONT><FONT FACE=3D"Arial"><BR>
</FONT><BLOCKQUOTE><FONT FACE=3D"Arial"><FONT SIZE=3D"2">I've read that it is p=
ossible to load pictures to your web page. Please let me know if you can get=
them to your page because I have a question to the forum. <BR>
<BR>
The problem is the following:<BR>
</FONT></FONT></BLOCKQUOTE><FONT FACE=3D"Arial"><FONT SIZE=3D"2"> <BR>
<BR>
We have a failure due to a leakage in one ceramic chip capacitor. Cross sec=
tion showed that the a damage in the capacitor. The damage has a elliptical =
shape and it is longitudinal to the length of the capacitor.<BR>
</FONT></FONT><FONT FACE=3D"Verdana"><BR>
<BR>
</FONT><FONT SIZE=3D"2"><FONT FACE=3D"Arial">I've seen Thermal Shock damage in =
this direction. Is it possible to be a Thermal Shock Failure or it could be =
a pre-existent void in the capacitor?<BR>
</FONT></FONT><FONT FACE=3D"Verdana"><BR>
</FONT><FONT SIZE=3D"2"><FONT FACE=3D"Arial"><BR>
</FONT></FONT><BLOCKQUOTE><FONT SIZE=3D"2"><FONT FACE=3D"Arial">Thanks, <BR>
Alejandro Becerra <BR>
<BR>
<BR>
</FONT></FONT><FONT FACE=3D"Verdana"><BR>
</FONT></BLOCKQUOTE></BLOCKQUOTE><FONT FACE=3D"Verdana"><BR>
Without sectioning the beast myself it appears from the two views that you =
could be looking at a knit line failure or delamination. Again from the imag=
es there appears to be three electrodes with the void at one end. The rough =
edges are due to excessive polishing pressure and the brittle nature of the =
ceramic.<BR>
<BR>
John</FONT>
</BODY>
</HTML>
--B_3086282020_415214--
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Date: Fri, 19 Oct 2001 10:44:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Solder Joint Defects
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Hi, Cathy,
No, the acceptable percentage of missed faults is zero, but with visual
inspection, it's accepted as a fact of life that only 80% of faults are
noticed at any time - partly because "pass" and "fail" conditions are
subjective up to a point, and partly because the human mind tends to
wander, and thoughts may be elsewhere at the time the eyes are passing over
a fault, so the fault doesn't register in the inspector's mind. It's
accepted, but not acceptable. The concern is the question of how serious
the faults are that aren't found. You can reasonably assume that major
defects will be spotted, but after 20+ years in this industry, I promise
you it's not just the minor faults that escape detection.
Unfortunately, we have no means of automating this sort of inspection work,
so we have to live with the imperfect yield of fault detection. We can
improve it a bit with training and awareness sessions for inspectors, but
even so, about 20% of faults are said not to be found. This does have an
effect of product life in the field, and field defects cost - money,
hassle, time, loss of customer confidence, resources to fix, etc.
I take it you have a yield problem? Or different inspectors find/miss
different faults?
Good luck with your bug hunt - I hope you find ways to reduce their
numbers.
Regards
Peter Duncan
Cathy Killen
<ckillen@SMTE To: [log in to unmask]
K.CO.UK> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Solder Joint Defects
<[log in to unmask]
ORG>
10/18/01
07:33 PM
Please
respond to
"TechNet
E-Mail
Forum."
Could anyone help with this.
When visually inspecting PCBs to class 3, is there an acceptable percentage
of faults missed? Also is there an acceptable defect level considering PPM
with regards to soldered joints.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
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Date: Fri, 19 Oct 2001 12:24:58 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Vapor Phase Soldering material
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Jim,
This surprises me and I'd like to know more. In practice, in VP
soldering, I doubt whether there is any great significance. Firstly, the
bulk of the vapour is anaerobic, with just the top interface in contact
with the air. This air will be heated and therefore the RH, even in
humid climates, will become extremely small. Then PFCs are demonstrably
resistant to hydrolysis in the presence of free H and OH radicals (this
is why they have atmospheric residence times of thousands of years):
there is simply not enough energy available to break the F-C bonds.
Naturally, Mr Arrhenius will say that, at 200°C, the energy will be much
higher so there will be more reactivity, but it would require temps
exceeding 300°C for it to become significant. Notwithstanding, I believe
that we are talking about 1 molecule in 10^n where n is a very large
integer that will decompose at soldering temperature under practical
conditions in a given time, unless there is something new that I haven't
heard about (always possible, of course).
I just looked at Fluorinert data sheets on the 3M web site (requires
some searching!) and there is no mention of a hydrolytic reaction in
anything I could find.
Brian
"Marsico, James" wrote:
>
> Brian,
> I'm getting conflicting comments from someone from 3M who is claiming that
> Fluorinert will decompose at temperatures of 200C and above and this is not
> a good thing in the presence of water (usually available as moisture in the
> air). Any comments?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> -----Original Message-----
> From: Brian Ellis [SMTP:[log in to unmask]]
> Sent: Wednesday, October 17, 2001 2:38 AM
> To: [log in to unmask]
> Subject: Re: [TN] Vapor Phase Soldering material
>
> Back in the days? Vapour-phase soldering is still done! The great
> advantages of perfluorocarbons over other halocarbons are that a)
> they
> are chemically extremely stable because the C-F covalent bond
> requires
> much energy to break them; b) they are virtually non-toxic (for the
> same
> reason: they do not break down in the body). In fact they can be
> used to
> replace blood in the body for short periods as they do allow oxygen
> to
> be dissolved and some "sportsmen" have even injected PFCs into the
> bloodstream to improve their endurance performance by a higher
> oxygenation; c) they are very inert chemically; d) they withstand
> high
> temperatures; e) they are NOT ozone-depleting. Teflon is a solid
> PFC.
> The disadvantages are a) that they are very expensive; b) they are
> EXTREMELY global-warming (typically 1 kg of PFC is equivalent to 10
> tonnes of carbon dioxide which is roughly equivalent to half the
> emissions of a medium car during its lifetime); c) their stability
> (~10,000 years atmospheric residence time) is such that end-of-life
> disposal is very difficult and costly.
>
> The fluids, be they pure PFCs or PFEs, used for soldering are
> sufficiently stable at 210 - 260°C that there is little significant
> decomposition. Water hardly enters into the equation because it is
> boiled off instantaneously, even if there be some condensation on
> the
> cooling coils. Theoretically, there may be some hydrogen fluoride
> generated (no hydrofluoric acid), but I believe that the quantities
> would be really negligible, in practice. With the presence of other
> organics from the flux residues, I would personally be more
> concerned
> with trifluoroacetic acid, another nasty, but I have not heard of
> any
> cases. Carbonyl fluoride is also not to be excluded, also very
> toxic.
> There is another fluoro-compound, whose name escapes me for the
> moment,
> which did cause some concern in the early days, which is toxic in
> the
> ppb rnnge. However, in practice, I have never heard of any of these
> toxic substances being present in sufficient quantity to be of
> practical
> concern.
>
> The real crunch comes when there is a secondary blanket, used in the
> early days to reduce losses of the primary fluid. This was initially
> always a pure CFC-113 (e.g., Freon TF, Arklone P etc.). Later,
> because
> of the ozone depletion potential of CFC-113 being as high as 0.8, a
> lower BP PFC was also proposed. CFC-113 does decompose at the vapour
> temperature of the primary fluid, so that the interface zone between
> the
> two vapours was always a hotbed of chemical reactions. This
> certainly
> produced, especially in the presence of water, whose BP was higher
> than
> that of the secondary fluid, a whole panoply of acids and other
> toxic
> substances. For this reason, these machines had both a molecular
> sieve
> to de-water the condensed vapours, but also a filter to remove the
> acids, otherwise the stainless steel tank corroded into holes in a
> matter of months. It is possibly this that you are thinking of. The
> most
> important decomposition product was hydrogen chloride, which becomes
> hydrochloric acid in the presence of water, but there was also
> phosgene,
> hydrogen fluoride, trichloroacetic acid and goodness knows what
> else. I
> feel reasonably certain (abstraction of any environmental effects),
> if
> vapour phase soldering with a CFC-113 secondary blanket were
> invented
> for the first time today, it would never be allowed into a workshop
> because of the H&S aspects.
>
> Hope this makes it clear.
>
> Brian
>
> "Marsico, James" wrote:
> >
> > Back in the days of vapor phase soldering, I seem to recall that
> > hydrofluoric acid was a bi-product of the fluorinert mixed with
> water, or
> > was it the Freon mixed with the fluorinert? Could anyone
> elaborate?
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
> ----------------------------------------------------------------------------
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Date: Fri, 19 Oct 2001 07:34:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Creswick, Steven" <[log in to unmask]>
Subject: Re: Internal Damage to Capacitor
MIME-Version: 1.0
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Alejandro - my vote is "pre-existing"
Steve
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 9:09 PM
To: [log in to unmask]
Subject: [TN] Internal Damage to Capacitor
Hi all!
Alejandro Becerra sent me an email asking to post some pictures for him, and
the following message that I've pasted below. Go to:
http://www.stevezeva.homestead.com
Read his question and check out his images...
-Steve Gregory-
In a message dated 10/18/2001 5:57:21 PM Central Daylight Time,
[log in to unmask] writes:
Steve,
I've read that it is possible to load pictures to your web page. Please let
me know if you can get them to your page because I have a question to the
forum.
The problem is the following:
We have a failure due to a leakage in one ceramic chip capacitor. Cross
section showed that the a damage in the capacitor. The damage has a
elliptical shape and it is longitudinal to the length of the capacitor.
I've seen Thermal Shock damage in this direction. Is it possible to be a
Thermal Shock Failure or it could be a pre-existent void in the capacitor?
Thanks,
Alejandro Becerra
------_=_NextPart_001_01C15891.FED86020
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.3211.1700" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=443253511-19102001>Alejandro - my vote is
"pre-existing"</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=443253511-19102001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=443253511-19102001>Steve</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, October 18, 2001 9:09
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Internal Damage to
Capacitor<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT size=2>Hi all!
<BR><BR>Alejandro Becerra sent me an email asking to post some pictures for
him, and the following message that I've pasted below. Go to:
<BR><BR>http://www.stevezeva.homestead.com <BR><BR>Read his question and check
out his images... <BR><BR>-Steve Gregory- <BR><BR>In a message dated
10/18/2001 5:57:21 PM Central Daylight Time, [log in to unmask] writes:
<BR><BR><BR>
<BLOCKQUOTE
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"
TYPE="CITE">Steve, </BLOCKQUOTE><BR></FONT><FONT color=#000000 face=Arial
lang=0 size=3 FAMILY="SANSSERIF"><BR></FONT><FONT color=#000000 face=Arial
lang=0 size=2 FAMILY="SANSSERIF">
<BLOCKQUOTE
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"
TYPE="CITE">I've read that it is possible to load pictures to your web page.
Please let me know if you can get them to your page because I have a
question to the forum. <BR><BR>The problem is the
following:</BLOCKQUOTE></FONT><FONT color=#000000 face=Arial lang=0 size=3
FAMILY="SANSSERIF"><BR></FONT><FONT color=#000000 face=Arial lang=0 size=2
FAMILY="SANSSERIF"><BR>
<BLOCKQUOTE
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"
TYPE="CITE">We have a failure due to a leakage in one ceramic chip
capacitor. Cross section showed that the a damage in the capacitor. The
damage has a elliptical shape and it is longitudinal to the length of the
capacitor.</FONT><FONT color=#000000 face=Arial lang=0 size=3
FAMILY="SANSSERIF"></BLOCKQUOTE><BR><BR></FONT><FONT color=#000000 face=Arial
lang=0 size=2 FAMILY="SANSSERIF">
<BLOCKQUOTE
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"
TYPE="CITE">I've seen Thermal Shock damage in this direction. Is it possible
to be a Thermal Shock Failure or it could be a pre-existent void in the
capacitor?</FONT><FONT color=#000000 face=Arial lang=0 size=3
FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT color=#000000 face=Arial
lang=0 size=2 FAMILY="SANSSERIF"><BR>
<BLOCKQUOTE
style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"
TYPE="CITE">Thanks, <BR>Alejandro Becerra
<BR></BLOCKQUOTE><BR><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
------_=_NextPart_001_01C15891.FED86020--
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Date: Fri, 19 Oct 2001 07:31:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Vapor Phase Soldering material
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
BTW, the reason for my inquiry is that we are using Fluorinert as a =
medium
for a liquid burn-in chamber. We're building a multi-chip module in a =
655
BGA ceramic package. These components require 160 hrs of burn-in at =
125 C,
under power (MIL 883 requirement). The test fixture consists of BGA =
sockets
(clam-shell with gold plated copper pins) soldered to a test board. =
The
liquid is used to prevent oxidation of the solder terminations during
burn-in, since the solder balls are not attached yet. The solder
termination base material is tungsten which is nickel and gold plated. =
We
recently had a batch, or two, of components which exhibited damage to =
the
solder terminations... anywhere from flaking plating with black =
metalization
underneath to completely black, almost burnt-looking pads. Attempts at
cleaning these pads (warm HCL) were fruitless. Surface analysis of the =
pads
where metal was found showed gold, copper and molybdenum, but no =
nickel.
(Where the molybdenum came from is a mystery.) At this stage of the =
game
these components are probably worth a couple of thousand dollars, so =
you can
see the reason for trying to get to the root cause. Someone had =
mentioned
that Fluorinert breaks down and forms acid in the presence of water, so
everyone is pointing to this as the cause... I'm not so sure.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>=20
631-595-5879
-----Original Message-----
From: Brian Ellis [SMTP:[log in to unmask]]
Sent: Friday, October 19, 2001 5:25 AM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
Jim,
This surprises me and I'd like to know more. In practice, in VP
soldering, I doubt whether there is any great significance. Firstly,
the
bulk of the vapour is anaerobic, with just the top interface in
contact
with the air. This air will be heated and therefore the RH, even in
humid climates, will become extremely small. Then PFCs are
demonstrably
resistant to hydrolysis in the presence of free H and OH radicals
(this
is why they have atmospheric residence times of thousands of years):
there is simply not enough energy available to break the F-C bonds.
Naturally, Mr Arrhenius will say that, at 200=B0C, the energy will be
much
higher so there will be more reactivity, but it would require temps
exceeding 300=B0C for it to become significant. Notwithstanding, I
believe
that we are talking about 1 molecule in 10^n where n is a very large
integer that will decompose at soldering temperature under practical
conditions in a given time, unless there is something new that I
haven't
heard about (always possible, of course).
I just looked at Fluorinert data sheets on the 3M web site (requires
some searching!) and there is no mention of a hydrolytic reaction in
anything I could find.
Brian
"Marsico, James" wrote:
>
> Brian,
> I'm getting conflicting comments from someone from 3M who is
claiming that
> Fluorinert will decompose at temperatures of 200C and above and
this is not
> a good thing in the presence of water (usually available as
moisture in the
> air). Any comments?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> -----Original Message-----
> From: Brian Ellis [SMTP:[log in to unmask]]
> Sent: Wednesday, October 17, 2001 2:38 AM
> To: [log in to unmask]
> Subject: Re: [TN] Vapor Phase Soldering material
>
> Back in the days? Vapour-phase soldering is still done!
The great
> advantages of perfluorocarbons over other halocarbons are
that a)
> they
> are chemically extremely stable because the C-F covalent
bond
> requires
> much energy to break them; b) they are virtually non-toxic
(for the
> same
> reason: they do not break down in the body). In fact they
can be
> used to
> replace blood in the body for short periods as they do
allow oxygen
> to
> be dissolved and some "sportsmen" have even injected PFCs
into the
> bloodstream to improve their endurance performance by a
higher
> oxygenation; c) they are very inert chemically; d) they
withstand
> high
> temperatures; e) they are NOT ozone-depleting. Teflon is a
solid
> PFC.
> The disadvantages are a) that they are very expensive; b)
they are
> EXTREMELY global-warming (typically 1 kg of PFC is
equivalent to 10
> tonnes of carbon dioxide which is roughly equivalent to
half the
> emissions of a medium car during its lifetime); c) their
stability
> (~10,000 years atmospheric residence time) is such that
end-of-life
> disposal is very difficult and costly.
>
> The fluids, be they pure PFCs or PFEs, used for soldering
are
> sufficiently stable at 210 - 260=B0C that there is little
significant
> decomposition. Water hardly enters into the equation
because it is
> boiled off instantaneously, even if there be some
condensation on
> the
> cooling coils. Theoretically, there may be some hydrogen
fluoride
> generated (no hydrofluoric acid), but I believe that the
quantities
> would be really negligible, in practice. With the presence
of other
> organics from the flux residues, I would personally be
more
> concerned
> with trifluoroacetic acid, another nasty, but I have not
heard of
> any
> cases. Carbonyl fluoride is also not to be excluded, also
very
> toxic.
> There is another fluoro-compound, whose name escapes me
for the
> moment,
> which did cause some concern in the early days, which is
toxic in
> the
> ppb rnnge. However, in practice, I have never heard of any
of these
> toxic substances being present in sufficient quantity to
be of
> practical
> concern.
>
> The real crunch comes when there is a secondary blanket,
used in the
> early days to reduce losses of the primary fluid. This was
initially
> always a pure CFC-113 (e.g., Freon TF, Arklone P etc.).
Later,
> because
> of the ozone depletion potential of CFC-113 being as high
as 0.8, a
> lower BP PFC was also proposed. CFC-113 does decompose at
the vapour
> temperature of the primary fluid, so that the interface
zone between
> the
> two vapours was always a hotbed of chemical reactions.
This
> certainly
> produced, especially in the presence of water, whose BP
was higher
> than
> that of the secondary fluid, a whole panoply of acids and
other
> toxic
> substances. For this reason, these machines had both a
molecular
> sieve
> to de-water the condensed vapours, but also a filter to
remove the
> acids, otherwise the stainless steel tank corroded into
holes in a
> matter of months. It is possibly this that you are
thinking of. The
> most
> important decomposition product was hydrogen chloride,
which becomes
> hydrochloric acid in the presence of water, but there was
also
> phosgene,
> hydrogen fluoride, trichloroacetic acid and goodness knows
what
> else. I
> feel reasonably certain (abstraction of any environmental
effects),
> if
> vapour phase soldering with a CFC-113 secondary blanket
were
> invented
> for the first time today, it would never be allowed into a
workshop
> because of the H&S aspects.
>
> Hope this makes it clear.
>
> Brian
>
> "Marsico, James" wrote:
> >
> > Back in the days of vapor phase soldering, I seem to
recall that
> > hydrofluoric acid was a bi-product of the fluorinert
mixed with
> water, or
> > was it the Freon mixed with the fluorinert? Could
anyone
> elaborate?
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
>
------------------------------------------------------------------------=
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> -----
> > Technet Mail List provided as a free service by IPC
using LISTSERV
> 1.8d
> > To unsubscribe, send a message to [log in to unmask] with
following
> text in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send the
following
> message: SET Technet NOMAIL
> > Search previous postings at: www.ipc.org > On-Line
Resources &
> Databases > E-mail Archives
> > Please visit IPC web site
(http://www.ipc.org/html/forum.htm) for
> additional
> > information, or contact Keach Sasamori at [log in to unmask]
or
> 847-509-9700 ext.5315
> >
>
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> -----
>
>
>
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> -----
> Technet Mail List provided as a free service by IPC using
LISTSERV
> 1.8d
> To unsubscribe, send a message to [log in to unmask] with
following
> text in
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> Search previous postings at: www.ipc.org > On-Line
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> Databases > E-mail Archives
> Please visit IPC web site
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> additional
> information, or contact Keach Sasamori at [log in to unmask]
or
> 847-509-9700 ext.5315
>
>
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> -----
>
>
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-----
> Technet Mail List provided as a free service by IPC using LISTSERV
1.8d
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text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following
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Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700 ext.5315
>
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=09
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----
-----
Technet Mail List provided as a free service by IPC using LISTSERV
1.8d
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text in
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SET Technet NOMAIL
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
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847-509-9700 ext.5315
=09
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---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
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---------------------------------------------------------------------------------
=========================================================================
Date: Fri, 19 Oct 2001 08:35:28 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: Vapor Phase Soldering material
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
Content-transfer-encoding: quoted-printable
The condition of the gold pads sounds like the "Black pad" problem =
exhibited
by circuit boards. The lack of nickel is odd because I thought this
phenomenon was related to Phosphor-Nickel oxidation in the plating
process...
Just a thought,
Jeffrey A. McGlaughlin CID
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Friday, October 19, 2001 7:31 AM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
BTW, the reason for my inquiry is that we are using Fluorinert as a =
medium
for a liquid burn-in chamber. We're building a multi-chip module in a =
655
BGA ceramic package. These components require 160 hrs of burn-in at =
125 C,
under power (MIL 883 requirement). The test fixture consists of BGA =
sockets
(clam-shell with gold plated copper pins) soldered to a test board. =
The
liquid is used to prevent oxidation of the solder terminations during
burn-in, since the solder balls are not attached yet. The solder
termination base material is tungsten which is nickel and gold plated. =
We
recently had a batch, or two, of components which exhibited damage to =
the
solder terminations... anywhere from flaking plating with black =
metalization
underneath to completely black, almost burnt-looking pads. Attempts at
cleaning these pads (warm HCL) were fruitless. Surface analysis of the =
pads
where metal was found showed gold, copper and molybdenum, but no =
nickel.
(Where the molybdenum came from is a mystery.) At this stage of the =
game
these components are probably worth a couple of thousand dollars, so =
you can
see the reason for trying to get to the root cause. Someone had =
mentioned
that Fluorinert breaks down and forms acid in the presence of water, so
everyone is pointing to this as the cause... I'm not so sure.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>=20
631-595-5879
-----Original Message-----
From: Brian Ellis [SMTP:[log in to unmask]]
Sent: Friday, October 19, 2001 5:25 AM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
Jim,
This surprises me and I'd like to know more. In practice, in VP
soldering, I doubt whether there is any great significance. =
Firstly,
the
bulk of the vapour is anaerobic, with just the top interface in
contact
with the air. This air will be heated and therefore the RH, =
even in
humid climates, will become extremely small. Then PFCs are
demonstrably
resistant to hydrolysis in the presence of free H and OH =
radicals
(this
is why they have atmospheric residence times of thousands of =
years):
there is simply not enough energy available to break the F-C =
bonds.
Naturally, Mr Arrhenius will say that, at 200=B0C, the energy =
will be
much
higher so there will be more reactivity, but it would require =
temps
exceeding 300=B0C for it to become significant. =
Notwithstanding, I
believe
that we are talking about 1 molecule in 10^n where n is a very =
large
integer that will decompose at soldering temperature under =
practical
conditions in a given time, unless there is something new that =
I
haven't
heard about (always possible, of course).
I just looked at Fluorinert data sheets on the 3M web site =
(requires
some searching!) and there is no mention of a hydrolytic =
reaction in
anything I could find.
Brian
"Marsico, James" wrote:
>
> Brian,
> I'm getting conflicting comments from someone from 3M who is
claiming that
> Fluorinert will decompose at temperatures of 200C and above =
and
this is not
> a good thing in the presence of water (usually available as
moisture in the
> air). Any comments?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> -----Original Message-----
> From: Brian Ellis [SMTP:[log in to unmask]]
> Sent: Wednesday, October 17, 2001 2:38 AM
> To: [log in to unmask]
> Subject: Re: [TN] Vapor Phase Soldering =
material
>
> Back in the days? Vapour-phase soldering is still =
done!
The great
> advantages of perfluorocarbons over other halocarbons =
are
that a)
> they
> are chemically extremely stable because the C-F =
covalent
bond
> requires
> much energy to break them; b) they are virtually =
non-toxic
(for the
> same
> reason: they do not break down in the body). In fact =
they
can be
> used to
> replace blood in the body for short periods as they =
do
allow oxygen
> to
> be dissolved and some "sportsmen" have even injected =
PFCs
into the
> bloodstream to improve their endurance performance by =
a
higher
> oxygenation; c) they are very inert chemically; d) =
they
withstand
> high
> temperatures; e) they are NOT ozone-depleting. Teflon =
is a
solid
> PFC.
> The disadvantages are a) that they are very =
expensive; b)
they are
> EXTREMELY global-warming (typically 1 kg of PFC is
equivalent to 10
> tonnes of carbon dioxide which is roughly equivalent =
to
half the
> emissions of a medium car during its lifetime); c) =
their
stability
> (~10,000 years atmospheric residence time) is such =
that
end-of-life
> disposal is very difficult and costly.
>
> The fluids, be they pure PFCs or PFEs, used for =
soldering
are
> sufficiently stable at 210 - 260=B0C that there is =
little
significant
> decomposition. Water hardly enters into the equation
because it is
> boiled off instantaneously, even if there be some
condensation on
> the
> cooling coils. Theoretically, there may be some =
hydrogen
fluoride
> generated (no hydrofluoric acid), but I believe that =
the
quantities
> would be really negligible, in practice. With the =
presence
of other
> organics from the flux residues, I would personally =
be
more
> concerned
> with trifluoroacetic acid, another nasty, but I have =
not
heard of
> any
> cases. Carbonyl fluoride is also not to be excluded, =
also
very
> toxic.
> There is another fluoro-compound, whose name escapes =
me
for the
> moment,
> which did cause some concern in the early days, which =
is
toxic in
> the
> ppb rnnge. However, in practice, I have never heard =
of any
of these
> toxic substances being present in sufficient quantity =
to
be of
> practical
> concern.
>
> The real crunch comes when there is a secondary =
blanket,
used in the
> early days to reduce losses of the primary fluid. =
This was
initially
> always a pure CFC-113 (e.g., Freon TF, Arklone P =
etc.).
Later,
> because
> of the ozone depletion potential of CFC-113 being as =
high
as 0.8, a
> lower BP PFC was also proposed. CFC-113 does =
decompose at
the vapour
> temperature of the primary fluid, so that the =
interface
zone between
> the
> two vapours was always a hotbed of chemical =
reactions.
This
> certainly
> produced, especially in the presence of water, whose =
BP
was higher
> than
> that of the secondary fluid, a whole panoply of acids =
and
other
> toxic
> substances. For this reason, these machines had both =
a
molecular
> sieve
> to de-water the condensed vapours, but also a filter =
to
remove the
> acids, otherwise the stainless steel tank corroded =
into
holes in a
> matter of months. It is possibly this that you are
thinking of. The
> most
> important decomposition product was hydrogen =
chloride,
which becomes
> hydrochloric acid in the presence of water, but there =
was
also
> phosgene,
> hydrogen fluoride, trichloroacetic acid and goodness =
knows
what
> else. I
> feel reasonably certain (abstraction of any =
environmental
effects),
> if
> vapour phase soldering with a CFC-113 secondary =
blanket
were
> invented
> for the first time today, it would never be allowed =
into a
workshop
> because of the H&S aspects.
>
> Hope this makes it clear.
>
> Brian
>
> "Marsico, James" wrote:
> >
> > Back in the days of vapor phase soldering, I seem =
to
recall that
> > hydrofluoric acid was a bi-product of the =
fluorinert
mixed with
> water, or
> > was it the Freon mixed with the fluorinert? Could
anyone
> elaborate?
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] =
<mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
>
------------------------------------------------------------------------=
----
> -----
> > Technet Mail List provided as a free service by IPC
using LISTSERV
> 1.8d
> > To unsubscribe, send a message to [log in to unmask] =
with
following
> text in
> > the BODY (NOT the subject field): SIGNOFF Technet
> > To temporarily halt delivery of Technet send the
following
> message: SET Technet NOMAIL
> > Search previous postings at: www.ipc.org > On-Line
Resources &
> Databases > E-mail Archives
> > Please visit IPC web site
(http://www.ipc.org/html/forum.htm) for
> additional
> > information, or contact Keach Sasamori at =
[log in to unmask]
or
> 847-509-9700 ext.5315
> >
>
------------------------------------------------------------------------=
----
> -----
>
>
>
------------------------------------------------------------------------=
----
> -----
> Technet Mail List provided as a free service by IPC =
using
LISTSERV
> 1.8d
> To unsubscribe, send a message to [log in to unmask] =
with
following
> text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the =
following
message:
> SET Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line
Resources &
> Databases > E-mail Archives
> Please visit IPC web site
(http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at =
[log in to unmask]
or
> 847-509-9700 ext.5315
>
>
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> -----
>
>
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----
-----
> Technet Mail List provided as a free service by IPC using =
LISTSERV
1.8d
> To unsubscribe, send a message to [log in to unmask] with =
following
text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following
message: SET Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources =
&
Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) =
for
additional
> information, or contact Keach Sasamori at [log in to unmask] or
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Date: Fri, 19 Oct 2001 13:52:26 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Vapor Phase Soldering material
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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A few thoughts which may of may not be helpful:
Are you sure it's Fluorinert, sorry to ask, but in this context people could
be saying Fluorinert in the same way as Xerox for copier, Hoover for vacuum
cleaner and so on. Some of the other test/burn in liquids are not
necessarily as stable.
If you have acid in the tank then the moly could be from previous
components, moly is used as heat spreaders and so on.
Also some manufacturers put flashes of stuff between plated layers to stop
diffusion, never heard of moly being used for this but if everything else is
eliminated..?
Could there be hot spots in the tank? Are the parts going in clean? you
might have quite high heat densities if the heater design is not good,
Fluorinerts are poor solvents but you could be getting a little wash off and
accumulation of stuff around the heater elements - maybe there is a little
catalysis/breakdown or something going on down there.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Friday, October 19, 2001 12:31 PM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
BTW, the reason for my inquiry is that we are using Fluorinert as a medium
for a liquid burn-in chamber. We're building a multi-chip module in a 655
BGA ceramic package. These components require 160 hrs of burn-in at 125 C,
under power (MIL 883 requirement). The test fixture consists of BGA sockets
(clam-shell with gold plated copper pins) soldered to a test board. The
liquid is used to prevent oxidation of the solder terminations during
burn-in, since the solder balls are not attached yet. The solder
termination base material is tungsten which is nickel and gold plated. We
recently had a batch, or two, of components which exhibited damage to the
solder terminations... anywhere from flaking plating with black metalization
underneath to completely black, almost burnt-looking pads. Attempts at
cleaning these pads (warm HCL) were fruitless. Surface analysis of the pads
where metal was found showed gold, copper and molybdenum, but no nickel.
(Where the molybdenum came from is a mystery.) At this stage of the game
these components are probably worth a couple of thousand dollars, so you can
see the reason for trying to get to the root cause. Someone had mentioned
that Fluorinert breaks down and forms acid in the presence of water, so
everyone is pointing to this as the cause... I'm not so sure.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Brian Ellis [SMTP:[log in to unmask]]
Sent: Friday, October 19, 2001 5:25 AM
To: [log in to unmask]
Subject: Re: [TN] Vapor Phase Soldering material
Jim,
This surprises me and I'd like to know more. In practice, in VP
soldering, I doubt whether there is any great significance. Firstly,
the
bulk of the vapour is anaerobic, with just the top interface in
contact
with the air. This air will be heated and therefore the RH, even in
humid climates, will become extremely small. Then PFCs are
demonstrably
resistant to hydrolysis in the presence of free H and OH radicals
(this
is why they have atmospheric residence times of thousands of years):
there is simply not enough energy available to break the F-C bonds.
Naturally, Mr Arrhenius will say that, at 200°C, the energy will be
much
higher so there will be more reactivity, but it would require temps
exceeding 300°C for it to become significant. Notwithstanding, I
believe
that we are talking about 1 molecule in 10^n where n is a very large
integer that will decompose at soldering temperature under practical
conditions in a given time, unless there is something new that I
haven't
heard about (always possible, of course).
I just looked at Fluorinert data sheets on the 3M web site (requires
some searching!) and there is no mention of a hydrolytic reaction in
anything I could find.
Brian
"Marsico, James" wrote:
>
> Brian,
> I'm getting conflicting comments from someone from 3M who is
claiming that
> Fluorinert will decompose at temperatures of 200C and above and
this is not
> a good thing in the presence of water (usually available as
moisture in the
> air). Any comments?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> -----Original Message-----
> From: Brian Ellis [SMTP:[log in to unmask]]
> Sent: Wednesday, October 17, 2001 2:38 AM
> To: [log in to unmask]
> Subject: Re: [TN] Vapor Phase Soldering material
>
> Back in the days? Vapour-phase soldering is still done!
The great
> advantages of perfluorocarbons over other halocarbons are
that a)
> they
> are chemically extremely stable because the C-F covalent
bond
> requires
> much energy to break them; b) they are virtually non-toxic
(for the
> same
> reason: they do not break down in the body). In fact they
can be
> used to
> replace blood in the body for short periods as they do
allow oxygen
> to
> be dissolved and some "sportsmen" have even injected PFCs
into the
> bloodstream to improve their endurance performance by a
higher
> oxygenation; c) they are very inert chemically; d) they
withstand
> high
> temperatures; e) they are NOT ozone-depleting. Teflon is a
solid
> PFC.
> The disadvantages are a) that they are very expensive; b)
they are
> EXTREMELY global-warming (typically 1 kg of PFC is
equivalent to 10
> tonnes of carbon dioxide which is roughly equivalent to
half the
> emissions of a medium car during its lifetime); c) their
stability
> (~10,000 years atmospheric residence time) is such that
end-of-life
> disposal is very difficult and costly.
>
> The fluids, be they pure PFCs or PFEs, used for soldering
are
> sufficiently stable at 210 - 260°C that there is little
significant
> decomposition. Water hardly enters into the equation
because it is
> boiled off instantaneously, even if there be some
condensation on
> the
> cooling coils. Theoretically, there may be some hydrogen
fluoride
> generated (no hydrofluoric acid), but I believe that the
quantities
> would be really negligible, in practice. With the presence
of other
> organics from the flux residues, I would personally be
more
> concerned
> with trifluoroacetic acid, another nasty, but I have not
heard of
> any
> cases. Carbonyl fluoride is also not to be excluded, also
very
> toxic.
> There is another fluoro-compound, whose name escapes me
for the
> moment,
> which did cause some concern in the early days, which is
toxic in
> the
> ppb rnnge. However, in practice, I have never heard of any
of these
> toxic substances being present in sufficient quantity to
be of
> practical
> concern.
>
> The real crunch comes when there is a secondary blanket,
used in the
> early days to reduce losses of the primary fluid. This was
initially
> always a pure CFC-113 (e.g., Freon TF, Arklone P etc.).
Later,
> because
> of the ozone depletion potential of CFC-113 being as high
as 0.8, a
> lower BP PFC was also proposed. CFC-113 does decompose at
the vapour
> temperature of the primary fluid, so that the interface
zone between
> the
> two vapours was always a hotbed of chemical reactions.
This
> certainly
> produced, especially in the presence of water, whose BP
was higher
> than
> that of the secondary fluid, a whole panoply of acids and
other
> toxic
> substances. For this reason, these machines had both a
molecular
> sieve
> to de-water the condensed vapours, but also a filter to
remove the
> acids, otherwise the stainless steel tank corroded into
holes in a
> matter of months. It is possibly this that you are
thinking of. The
> most
> important decomposition product was hydrogen chloride,
which becomes
> hydrochloric acid in the presence of water, but there was
also
> phosgene,
> hydrogen fluoride, trichloroacetic acid and goodness knows
what
> else. I
> feel reasonably certain (abstraction of any environmental
effects),
> if
> vapour phase soldering with a CFC-113 secondary blanket
were
> invented
> for the first time today, it would never be allowed into a
workshop
> because of the H&S aspects.
>
> Hope this makes it clear.
>
> Brian
>
> "Marsico, James" wrote:
> >
> > Back in the days of vapor phase soldering, I seem to
recall that
> > hydrofluoric acid was a bi-product of the fluorinert
mixed with
> water, or
> > was it the Freon mixed with the fluorinert? Could
anyone
> elaborate?
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
> >
>
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Date: Fri, 19 Oct 2001 09:46:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: D-SUB connector (15 pin size) with 2 power contacts
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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All,
I am in a search of manufacturer of D-SUB connector (15 pin size) with 2
power contacts, 40 A rating with back shell 90 degree strain relief.
This connector has pin count of 7 (5+2 power contact).
Any help in this regards will be appreciated.
re,
Ken Patel
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Date: Fri, 19 Oct 2001 13:28:42 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Anita Sargent <[log in to unmask]>
Subject: Anita Sargent/Endicott/IBM is out of the office.
MIME-Version: 1.0
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I will be out of the office starting October 19, 2001 and will not return
until October 22, 2001.
I will respond to your message when I return.
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Date: Fri, 19 Oct 2001 12:47:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Anita Sargent/Endicott/IBM is out of the office.
X-To: [log in to unmask]
Mime-Version: 1.0
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Hey Anita,
Let us know when you're back!
>>> [log in to unmask] 10/19/01 12:28PM >>>
I will be out of the office starting October 19, 2001 and will not return
until October 22, 2001.
I will respond to your message when I return.
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Date: Fri, 19 Oct 2001 14:24:22 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: press fit pins
MIME-Version: 1.0
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In a message dated 10/17/2001 12:59:27 PM US Eastern Standard Time,
[log in to unmask] writes:
<< Where do I find information regarding hole size, plating thickness
recommedations regarding whether these should subsequently be soldered etc?
>>
The pin or connector manufacturer can give you the best data for holes sizes.
I have done testing and also seen other data from testing at other
facilities showing that press fit compliant pins are more reliable
connections when NOT soldered - even more reliable than traditional soldered
PTH connectors.
Jon Moore
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Date: Fri, 19 Oct 2001 15:36:34 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Larry Tawyea <[log in to unmask]>
Subject: Re: HASL Plating Thickness
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_fd.dd13728.2901dac2_boundary"
--part1_fd.dd13728.2901dac2_boundary
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Content-Transfer-Encoding: 7bit
In a message dated 10/18/01 5:18:09 AM Central Daylight Time,
[log in to unmask] writes:
Christopher,
A thickness of 3.5 mils seems a little high but in my experience 2.5 mils
would not be out of the question.
Larry Tawyea
> Hello All,
>
> Is there any specification regarding the max thickness of HASL plated
> PCB's. We have recently received a lot of boards where the HASL plating on
> the fine pitch device exceeds 3.5 mils. He have an extensive amount of
> bridging on these devices now. Any help would be greatly appreciated.
>
> Thanks
>
> Christopher Lampron
>
>
--part1_fd.dd13728.2901dac2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 10/18/01 5:18:09 AM Central Daylight Time, [log in to unmask] writes:
<BR>
<BR>Christopher,
<BR>
<BR>A thickness of 3.5 mils seems a little high but in my experience 2.5 mils would not be out of the question.
<BR>
<BR>Larry Tawyea
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello All,
<BR>
<BR>Is there any specification regarding the max thickness of HASL plated
<BR>PCB's. We have recently received a lot of boards where the HASL plating on
<BR>the fine pitch device exceeds 3.5 mils. He have an extensive amount of
<BR>bridging on these devices now. Any help would be greatly appreciated.
<BR>
<BR>Thanks
<BR>
<BR>Christopher Lampron
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_fd.dd13728.2901dac2_boundary--
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Date: Fri, 19 Oct 2001 15:38:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lefebvre, Scott" <[log in to unmask]>
Subject: FW: double sided BGAs Re-work
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
The question I have is how do you rework the board if one of the BGAs should fail
with out effecting the other component on the back side.
Scott
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Wednesday, October 17, 2001 10:03 AM
Subject: Re: double sided BGAs
Concerning the difficulty to analyze the solder joints by X-ray, I have seen
that the best method to improve the testability is to design the outer
layers in such a manner that the BGA pads on one side are shifted between
the pads on the other side.
If your circuits are so, it is possible to check each BGA separately.
Check the artwork.
If not, you must have at least the possibility to rotate the circuit during
inspection.
Gaby
----- Original Message -----
From: "Larry Koens" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, October 17, 2001 6:32 PM
Subject: [TN] double sided BGAs
> Dear TechNet,
> My company has been asked to bid on assembling a board that would have
> two BGAs on the topside and two more BGAs mirrored on the bottomside.
> That is, they will be directly across from each other on both sides. I
> never done them on both sides. So far, everything that I have done has
> been on one side only. Has anyone done them on both sides before?
>
> I am figuring xray will be a problem as after the second side is
> placed, because the pads/balls will mirror each other on both sides.
> Would I be able to tell the difference between the two BGA connections?
> Suggestions?
>
> Will I need to epoxy the first side BGAs so they would not drop off
> during my second reflow? Wouldn't I need to epoxy them after first
> reflow so that the balls could collapse?
>
> Thanks,
> Larry Koens
> SMT Manufacturing Engineer
> E.I. Microcircuits
> Mankato, MN
>
> --------------------------------------------------------------------------
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Date: Fri, 19 Oct 2001 16:46:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Valladares, Hector A (FL51)" <[log in to unmask]>
Subject: Re: FW: double sided BGAs Re-work
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
If your customer requires inspection of all BGA you will have to purchase
and X-ray laminography system. Very expensive about 650K for a new one.
Good luck
Hector Valladares
SMT Staff Engineer
Honeywell Space Systems
-----Original Message-----
From: Lefebvre, Scott [mailto:[log in to unmask]]
Sent: Friday, October 19, 2001 4:39 PM
To: [log in to unmask]
Subject: [TN] FW: double sided BGAs Re-work
The question I have is how do you rework the board if one of the BGAs should
fail
with out effecting the other component on the back side.
Scott
-----Original Message-----
From: Gaby Bogdan [mailto:[log in to unmask]]
Sent: Wednesday, October 17, 2001 10:03 AM
Subject: Re: double sided BGAs
Concerning the difficulty to analyze the solder joints by X-ray, I have seen
that the best method to improve the testability is to design the outer
layers in such a manner that the BGA pads on one side are shifted between
the pads on the other side.
If your circuits are so, it is possible to check each BGA separately.
Check the artwork.
If not, you must have at least the possibility to rotate the circuit during
inspection.
Gaby
----- Original Message -----
From: "Larry Koens" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, October 17, 2001 6:32 PM
Subject: [TN] double sided BGAs
> Dear TechNet,
> My company has been asked to bid on assembling a board that would have
> two BGAs on the topside and two more BGAs mirrored on the bottomside.
> That is, they will be directly across from each other on both sides. I
> never done them on both sides. So far, everything that I have done has
> been on one side only. Has anyone done them on both sides before?
>
> I am figuring xray will be a problem as after the second side is
> placed, because the pads/balls will mirror each other on both sides.
> Would I be able to tell the difference between the two BGA connections?
> Suggestions?
>
> Will I need to epoxy the first side BGAs so they would not drop off
> during my second reflow? Wouldn't I need to epoxy them after first
> reflow so that the balls could collapse?
>
> Thanks,
> Larry Koens
> SMT Manufacturing Engineer
> E.I. Microcircuits
> Mankato, MN
>
> --------------------------------------------------------------------------
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Date: Fri, 19 Oct 2001 17:00:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Fri, 19 Oct 2001 17:12:36 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_147.34fdd90.2901f144_boundary"
--part1_147.34fdd90.2901f144_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Bev!
Here's a pretty decent link about solder tip construction and plating that
Metcal has:
http://www.metcal.com/tips/tiplife1.html
-Steve Gregory-
> OK, here is a general question for all you met guys. But I am not sure I
> can explain it well enough to be understood!
>
> We all know that tin can be put on iron or we wouldn't have "tin" cans. I
> also know it is difficult to put solder on iron. So my question is this: if
> one has a tinned iron surface and it is put into molten solder the tin will
> be dissolved into the molten solder. I presume when the piece of iron is
> withdrawn from the pot, solder will be well adhered to the iron. Is this
> because there is a solderable tin/iron intermetallic? What is the main
> difference between the tin can process and putting solder directly on iron
> that makes one easy to do and the other difficult? This may be a "first
> grade" met question, but I don't know the answer. Thanks.
>
> Bev Christian
>
--part1_147.34fdd90.2901f144_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Bev!
<BR>
<BR>Here's a pretty decent link about solder tip construction and plating that Metcal has:
<BR>
<BR>http://www.metcal.com/tips/tiplife1.html
<BR>
<BR>-Steve Gregory-
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">OK, here is a general question for all you met guys. But I am not sure I
<BR>can explain it well enough to be understood!
<BR>
<BR>We all know that tin can be put on iron or we wouldn't have "tin" cans. I
<BR>also know it is difficult to put solder on iron. So my question is this: if
<BR>one has a tinned iron surface and it is put into molten solder the tin will
<BR>be dissolved into the molten solder. I presume when the piece of iron is
<BR>withdrawn from the pot, solder will be well adhered to the iron. Is this
<BR>because there is a solderable tin/iron intermetallic? What is the main
<BR>difference between the tin can process and putting solder directly on iron
<BR>that makes one easy to do and the other difficult? This may be a "first
<BR>grade" met question, but I don't know the answer. Thanks.
<BR>
<BR>Bev Christian
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_147.34fdd90.2901f144_boundary--
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Date: Fri, 19 Oct 2001 17:28:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mike Manthe <[log in to unmask]>
Subject: MIL-P-50884 PAR. A.3.4.7
What does "circuit card assembly process" , and "compliant pin technlogy"
mean as used in the particular paragraph?
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Date: Fri, 19 Oct 2001 16:19:41 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Subject: Conformal Coat Spray Systems
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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We're starting to evaluate some of the systems available for selective
conformal coating of PCBAs. Initially we'll probably dealing with silicones
and acrylics. Does anyone have any system or manufacturer recommendations,
pro or con that they'd care to share with me offline? Also any
environmental issues I need to consider?
Thanks in advance,
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Fri, 19 Oct 2001 22:22:25 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: Conformal Coat Spray Systems
MIME-Version: 1.0
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In a message dated 10/19/2001 6:28:39 PM US Eastern Standard Time,
[log in to unmask] writes:
<< Does anyone have any system or manufacturer recommendations,
pro or con that they'd care to share with me offline? >>
I have used several different systems, and I would recommend PVA hands down
over everything. I would be glad to share details with you.
Jon Moore
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Date: Sat, 20 Oct 2001 11:09:47 +0200
Reply-To: Roland Jaquet <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roland Jaquet <[log in to unmask]>
Subject: Airplane PWB
MIME-Version: 1.0
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------=_NextPart_000_0091_01C15957.BAF8F830
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Dear Technetters,
I would like to know which standards have to be followed up for the =
Design, Manufacturing and Assembly of PWB that will be used into a civil =
Aircraft engines ?
So far, I followed the lead with MIL-PFR-55110 F -> MIL-PRF-31032-X -> =
AS9100A -> IPC-6010 ..11 ...12 ...13
I could have a look to the MIL and have ordered the AS9100A.. had a look =
at IPC-6011 and IPC-6012, but couldn't have a look to IPC-6010.
I really need a statement of which stands do apply for Aircraft Engines =
or Aircraft flying equipment for approbation by the FAA
In advance, I would like to thank those of you who care to reply.
Very Best Regards
Roland
Http://www.PCBspecialist.com
Roland Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 =
Plan-Les-Ouates - Geneva - Switzerland - Tel. +41-22-880-0405 - GSM =
(cellphone) +41-79-203-3723 - Fax +41-22-880-0409 - Company Viability - =
Technical Viability - Technology Choice - Yield Improvement - Company =
Strategy - Equipment Choice - Company Acquisition
------=_NextPart_000_0091_01C15957.BAF8F830
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4616.200" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px"=20
bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Dear Technetters,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I would like to know which standards =
have to be=20
followed up for the Design, Manufacturing and Assembly of PWB that will =
be used=20
into a civil Aircraft engines ?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>So far, I followed the lead with =
MIL-PFR-55110 F=20
-> MIL-PRF-31032-X -> AS9100A -> IPC-6010 ..11 ...12 =
...13</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I could have a look to the MIL and have =
ordered the=20
AS9100A.. had a look at IPC-6011 and IPC-6012, but couldn't have a look =
to=20
IPC-6010.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I really need a statement of which =
stands do apply=20
for Aircraft Engines or Aircraft flying equipment for approbation by the =
FAA</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>In advance, I would like to thank those =
of you who=20
care to reply.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV>Very Best Regards</DIV>
<DIV> </DIV>
<DIV>Roland</DIV>
<DIV> </DIV>
<DIV><A=20
href=3D"http://www.PCBspecialist.com">Http://www.PCBspecialist.com</A><BR=
>Roland=20
Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 Plan-Les-Ouates - =
Geneva -=20
Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - =
Fax=20
+41-22-880-0409 - Company Viability - Technical Viability - Technology =
Choice -=20
Yield Improvement - Company Strategy - Equipment Choice - Company=20
Acquisition</DIV></BODY></HTML>
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Date: Sat, 20 Oct 2001 11:16:48 +0200
Reply-To: Roland Jaquet <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roland Jaquet <[log in to unmask]>
Subject: reminder : PRODUCTRONICA 2001 - 6-9 November - New Munich Trade
Fair Centre
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0098_01C15958.B5AAAC60"
C'est un message de format MIME en plusieurs parties.
------=_NextPart_000_0098_01C15958.B5AAAC60
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Just a reminder for you all, sometime far away from Munich / Germany =
that the Largest industry event in the world will happen from the 6th to =
9th November 2001.
www.global-electronics.net=20
Very Best Regards
Roland
Http://www.PCBspecialist.com
Roland Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 =
Plan-Les-Ouates - Geneva - Switzerland - Tel. +41-22-880-0405 - GSM =
(cellphone) +41-79-203-3723 - Fax +41-22-880-0409 - Company Viability - =
Technical Viability - Technology Choice - Yield Improvement - Company =
Strategy - Equipment Choice - Company Acquisition
------=_NextPart_000_0098_01C15958.B5AAAC60
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4616.200" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px"=20
bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Just a reminder for you all, sometime =
far away from=20
Munich / Germany that the Largest industry event in the world will =
happen from=20
the 6th to 9th November 2001.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.global-electronics.net">www.global-electronics.net</A>=
=20
</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV>Very Best Regards</DIV>
<DIV> </DIV>
<DIV>Roland</DIV>
<DIV> </DIV>
<DIV><A=20
href=3D"http://www.PCBspecialist.com">Http://www.PCBspecialist.com</A><BR=
>Roland=20
Jaquet - PCBspecialist - 21 Grand-Voiret - CH-1228 Plan-Les-Ouates - =
Geneva -=20
Switzerland - Tel. +41-22-880-0405 - GSM (cellphone) +41-79-203-3723 - =
Fax=20
+41-22-880-0409 - Company Viability - Technical Viability - Technology =
Choice -=20
Yield Improvement - Company Strategy - Equipment Choice - Company=20
Acquisition<BR></DIV></BODY></HTML>
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Date: Mon, 22 Oct 2001 09:04:31 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jonathan A Noquil <[log in to unmask]>
Subject: ENIG
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello Guys,
Can Electroless Ni-Au plate 40 microns diameter hole with 75 microns deep?
What is the appropriate metallization technic to this size?
thanks
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Date: Mon, 22 Oct 2001 08:31:08 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neil Atkinson <[log in to unmask]>
Subject: Re: HASL Plating Thickness
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I have been reading this thread with interest as I have a been asking this
question recently about some PCBs we have outsourced which are not as good
as our normal levelling.
Reading all of the e-mails and links I came to the conclusion that between
10 and 25 microns seems reasonable so the suggestion of 2.5 mils seems high
(if my conversions are right and 2.5mils is around 63.5 microns, back to the
old metric 'v' imperial argument!?!?!).
Does anyone out there quote a flatness spec for their HAL and if so, what do
you quote?
Neil
-----Original Message-----
From: Larry Tawyea [mailto:[log in to unmask]]
Sent: 19 October 2001 20:37
Subject: Re: HASL Plating Thickness
In a message dated 10/18/01 5:18:09 AM Central Daylight Time,
[log in to unmask] writes:
Christopher,
A thickness of 3.5 mils seems a little high but in my experience 2.5 mils
would not be out of the question.
Larry Tawyea
Hello All,
Is there any specification regarding the max thickness of HASL plated
PCB's. We have recently received a lot of boards where the HASL plating on
the fine pitch device exceeds 3.5 mils. He have an extensive amount of
bridging on these devices now. Any help would be greatly appreciated.
Thanks
Christopher Lampron
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Date: Mon, 22 Oct 2001 10:06:16 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jean-Luc Lehmann <[log in to unmask]>
Subject: Re: D-SUB connector (15 pin size) with 2 power contacts
MIME-Version: 1.0
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Heve a look at www.deltron.ch, search for the high power familly
(DT-7W2PZ).
You might find what you look for...
Jean-Luc Lehmann
All,
I am in a search of manufacturer of D-SUB connector (15 pin size) with 2
power contacts, 40 A rating with back shell 90 degree strain relief.
This connector has pin count of 7 (5+2 power contact).
Any help in this regards will be appreciated.
re,
Ken Patel
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Date: Mon, 22 Oct 2001 09:01:22 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "FOX, Ian (York Rd)" <[log in to unmask]>
Subject: Re: HASL Plating Thickness
MIME-Version: 1.0
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I have to agree with Neil, the figures quoted are well in excess of what we
find on a typical HASL board. With manufacturers trying to obtain the
flattest possible pads for fine pitch SM components, we've found it's not
uncommon to find Solderability issues arising from insufficient coverage,
particularly on the knee region of a PTH. Has anyone else seen this?
Ian Fox
Process Engineering Manager
TRW ASG
-----Original Message-----
From: Neil Atkinson [mailto:[log in to unmask]]
Sent: 22 October 2001 08:31
To: [log in to unmask]
Subject: Re: [TN] HASL Plating Thickness
I have been reading this thread with interest as I have a been asking this
question recently about some PCBs we have outsourced which are not as good
as our normal levelling.
Reading all of the e-mails and links I came to the conclusion that between
10 and 25 microns seems reasonable so the suggestion of 2.5 mils seems high
(if my conversions are right and 2.5mils is around 63.5 microns, back to the
old metric 'v' imperial argument!?!?!).
Does anyone out there quote a flatness spec for their HAL and if so, what do
you quote?
Neil
-----Original Message-----
From: Larry Tawyea [mailto:[log in to unmask]]
Sent: 19 October 2001 20:37
Subject: Re: HASL Plating Thickness
In a message dated 10/18/01 5:18:09 AM Central Daylight Time,
[log in to unmask] writes:
Christopher,
A thickness of 3.5 mils seems a little high but in my experience 2.5 mils
would not be out of the question.
Larry Tawyea
Hello All,
Is there any specification regarding the max thickness of HASL plated
PCB's. We have recently received a lot of boards where the HASL plating on
the fine pitch device exceeds 3.5 mils. He have an extensive amount of
bridging on these devices now. Any help would be greatly appreciated.
Thanks
Christopher Lampron
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Date: Mon, 22 Oct 2001 10:41:47 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: shaymaa nabil <[log in to unmask]>
Subject: Best Cooling method for LNBP10 Series
MIME-Version: 1.0
Content-Type: text/plain
> Dear All,
>
> I would like to know the best cooling techniques for the package
> "PowerSO-10"..
>
> Regards,
> Shaymaa
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Date: Mon, 22 Oct 2001 13:41:22 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] IMC'S - NO LONGER STIRRING THE POT
Mime-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
Hi Earl
Sorry I didn't reply earlier but instead of thinking about technical =
problems I was engaged in surfing and swimming in the Mediterranean for =
two weeks. However, maybe some thoughts how I see the IMC issue might be =
still be a positive contribution to the discussion. I won't be using =
1),2),... since my paragraphs do not correspond to yours.
a) The occurrence of IMC is give by the alloying process of some metals. =
In soldering these are Sn, Ni, Ag, Cu, Au.
b) The thickness of IMC's is determined by diffusion processes once an =
initial layer has been formed. Thus the thickness is time and temperature =
dependent. This means the IMC is also growing at room temperature but =
faster at solder temperature.
c) IMC's have another mechanical characteristic than solder. Solder =
creeps. It shows a continuous plastic deformation if a constant load is =
applied. Also at low load levels. Failure is do to damage accumulation =
caused by strain. IMC's are brittle with a high young's modulus. Failure =
is due to overstress. This overstress can be localised at the tip of a =
notch or crack.
d) There is no minimal thickness of IMC's to indicate a reliable solder =
joint. As soon an IMC is present we have the indication that solder and =
substrate have alloyed. That's all we need. Actually if the IMC's where =
not a part of the alloying process there would be no need for any.=20
e) Whether a solder joint with a thick IMC is reliable depends on the load =
applied. As long as the stress applied in service or in a tests is far =
below the yield strength of the IMC the solder joint will fail because of =
the strain induced during deformation. If temperature cycles with high =
temperature gradients occur stresses higher than the yield strength of the =
IMC might be induced and the IMC will fail.=20
I have the feeling that the problem occurs mainly with highly accelerated =
tests. Not only because of a catastrophic failure of the IMC but also =
because IMC needles reaching into the solder will be very likely to snap =
of. This will reduce the load bearing area in the solder joint thus =
enabling faster deformation rates. If a tests is accelerated with short =
dwell times the faster deformation will cause larger deformation resulting =
in an earlier failure.
Some new insight for you? I hope so.
Have a great day.
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Mon, 22 Oct 2001 08:27:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Louis, Edwin @ CSE" <[log in to unmask]>
Subject: Heat of Combustion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Does anyone know what the heat of combustion is for G-10 Epoxy?
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Date: Mon, 22 Oct 2001 07:16:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: Info about IPC email forums
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FYI - technical forums.
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Jack Crawford [mailto:[log in to unmask]]
Sent: Thursday, October 18, 2001 4:06 PM
To: [log in to unmask]
Subject: [TN] Info about IPC email forums
This is an advisory message of just some of the current FREE peer-to-peer
forums provided by your IPC. For information on how to sign on and for
options, go to http://www.ipc.org/html/forum.htm
<http://www.ipc.org/html/forum.htm> If you have any questions please
contact me personnally off-net: [log in to unmask] <mailto:[log in to unmask]> .
Cordially,
Jack Crawford
Director of Assembly Standards and Technology
TechNet
This peer networking forum can be used to ask others for technical help,
comments or questions on IPC specifications, or other technical inquiries.
IPC will also use TechNet to announce meetings, important technical issues,
surveys, etc. As a general networking forum, any technical question is fair
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Discussion of pricing is not appropriate for TechNet. Requests for
recommendations of products or suppliers are appropriate when responses are
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TechNet forum.
Leadfree
Lead elimination is a fast emerging topic in the PWB industry. Pressure from
Japan and Europe is forcing US companies to react fast and prepare for the
transition. This forum acts as a peer interaction resource for staying on
top of lead elimination activities worldwide and within IPC, including
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additional info on ComplianceNet)
NoLeadTech
Electronic manufacturing utilizing lead-free processes is beginning to
mature but there are still implementation issues to be resolved. This forum
acts as a peer interaction resource to make technical inquiries and to
exchange research and implementation TECHNICAL DATA derived from research
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legislative, environmental and philosophical issues related to lead-free
policies.
Halogenfree
The green monster has struck again, as materials suppliers and PWB
fabricators are receiving OEM requirements for environmentally friendly base
materials, soldermask and components. The OEM-targeted materials include
bromine, halogen, halide and chlorine.
Materials suppliers are now left with the questions: What particle count
determines halogen-free, bromine-free, etc.? Will the alternative materials
guarantee the same reliability? Why are we doing this?
This email forum serves a basis for peer interaction on the issue.
Subscribers to the forum from all over the world can discuss the issues,
dispel the myths and help each other in making the transition to these green
materials a smooth ride. This forum will also be the basis for updates on a
white paper being developed by the IPC Halogen-Free Materials Task Group.
ComplianceNet
The ComplianceNet forum covers environmental, safety and related regulations
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YI –
technical forums.<o:p></o:p></span></font></span></p>
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<p class=3DMsoAutoSig><font size=3D3 color=3Dnavy face=3D"Times New =
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<p class=3DMsoAutoSig><font size=3D3 color=3Dnavy face=3D"Times New =
Roman"><span
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color=3Dnavy><span =
style=3D'color:navy;mso-color-alt:windowtext'><o:p></o:p></span></font><=
/p>
<p class=3DMsoAutoSig><font size=3D3 color=3Dnavy face=3D"Times New =
Roman"><span
style=3D'font-size:12.0pt;color:navy'>1815 NW 169th Place, Suite =
5010</span></font><font
color=3Dnavy><span =
style=3D'color:navy;mso-color-alt:windowtext'><o:p></o:p></span></font><=
/p>
<p class=3DMsoAutoSig><font size=3D3 color=3Dnavy face=3D"Times New =
Roman"><span
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yes"> </span>97006</span></font><font color=3Dnavy><span =
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(503)-617-6550</span></font><font
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style=3D'font-size:10.0pt;font-family:Tahoma;color:black'>-----Original
Message-----<br>
<b><span style=3D'font-weight:bold'>From:</span></b> Jack Crawford
[mailto:[log in to unmask]]<br>
<b><span style=3D'font-weight:bold'>Sent:</span></b> Thursday, October =
18, 2001
4:06 PM<br>
<b><span style=3D'font-weight:bold'>To:</span></b> [log in to unmask]<br>
<b><span style=3D'font-weight:bold'>Subject:</span></b> [TN] Info about =
IPC email
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for options, go to <a =
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This peer networking forum can be used to ask others for technical =
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Lead elimination is a fast emerging topic in the PWB industry. Pressure =
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Electronic manufacturing utilizing lead-free processes is beginning to =
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<p class=3DMsoNormal style=3D'margin-left:37.5pt'><font size=3D1 =
color=3Dblack
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color=3Dblack
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The green monster has struck again, as materials suppliers and PWB =
fabricators
are receiving OEM requirements for environmentally friendly base =
materials,
soldermask and components. The OEM-targeted materials include bromine, =
halogen,
halide and chlorine.</span></font><font size=3D1 color=3Dblack =
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<p class=3DMsoNormal style=3D'margin-left:37.5pt'><font size=3D1 =
color=3Dblack
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<p class=3DMsoNormal style=3D'margin-left:37.5pt'><font size=3D1 =
color=3Dblack
face=3D"MS Sans Serif"><span style=3D'font-size:8.0pt;font-family:"MS =
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color:black'>Materials suppliers are now left with the questions: What =
particle
count determines halogen-free, bromine-free, etc.? Will the alternative
materials guarantee the same reliability? Why are we doing this? =
</span></font><font
size=3D1 color=3Dblack face=3D"MS Sans Serif"><span =
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<p class=3DMsoNormal style=3D'margin-left:37.5pt'><font size=3D1 =
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<p class=3DMsoNormal style=3D'margin-left:37.5pt'><font size=3D1 =
color=3Dblack
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Sans Serif";
color:black'>This email forum serves a basis for peer interaction on =
the issue.
Subscribers to the forum from all over the world can discuss the =
issues, dispel
the myths and help each other in making the transition to these green =
materials
a smooth ride. This forum will also be the basis for updates on a white =
paper
being developed by the IPC Halogen-Free Materials Task =
Group.</span></font><font
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The ComplianceNet forum covers environmental, safety and related =
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IPC will
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Grass roots action alerts <br>
Compliance assistance</span></font><font size=3D1 color=3Dblack =
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Provides notification to subscribers when new and revised IPC =
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Date: Mon, 22 Oct 2001 07:27:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Subject: Re: Conformal Coat Spray Systems
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Jon,
Thanks for the offer. You're the second person I've had recommend PVA...I
wasn't aware of them. I would be interested in how the compare to the
Nordson or SCS systems if you've had experience with either of them.
Regards,
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jon Moore
Sent: Friday, October 19, 2001 7:22 PM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coat Spray Systems
In a message dated 10/19/2001 6:28:39 PM US Eastern Standard Time,
[log in to unmask] writes:
<< Does anyone have any system or manufacturer recommendations,
pro or con that they'd care to share with me offline? >>
I have used several different systems, and I would recommend PVA hands down
over everything. I would be glad to share details with you.
Jon Moore
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Date: Mon, 22 Oct 2001 15:34:01 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "FOX, Ian (York Rd)" <[log in to unmask]>
Subject: Re: Heat of Combustion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
From measurements we carried out, about 1kJ/g
Ian Fox
Process Engineering Manager
TRW ASG
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: 22 October 2001 13:28
To: [log in to unmask]
Subject: [TN] Heat of Combustion
Does anyone know what the heat of combustion is for G-10 Epoxy?
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Date: Mon, 22 Oct 2001 07:38:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Darrel Therriault <[log in to unmask]>
Organization: INCEP Technologies, Inc.
Subject: Re: PWB ASSEMBLY BURN-IN TEST
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
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James,
I'd verify specs for any electrolytic caps on your board. Several have a 105C limit and at
125C I've found the outer covering starts to split.
DT
"Marsico, James" wrote:
> Good day Technet:
> We're being asked to perform a burn-in test (160 HRS @ 125ºC and 352 HRS @
> 100ºC) on a surface mount assembly. I'm sure that the parts can withstand
> this environment, but what about the PWB and solder joints?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
--
Darrel Therriault
VP, Mfg. Operations
INCEP Technologies, Inc
(858)547-9925 223
[log in to unmask]
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Date: Mon, 22 Oct 2001 07:47:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Darrel Therriault <[log in to unmask]>
Organization: INCEP Technologies, Inc.
Subject: Re: PCB layers swapped
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Genny,
I believe this is what the layer stack coupon was intended to prevent. Obviously, it was not
checked anywhere during the fabrication process. I would certainly check out your PWB
supplier for this oversite, since it is a fundamental check on FAI or QA audits for PWB
builds.
If they don't include this as part of their check process, or if they do and did not perform
it, you are "at risk" either way.
DT
Genny Gibbard wrote:
> Good morning,
> My morning has not been so good. I have a build of PCB's (over 300 boards)
> where two inner layers have been swapped. The board fabricator constructed
> the board in the wrong order. These boards are RF in nature and have
> frequencies approaching 2GHz on them. In many places we put a signal trace
> on the inner layer furthest from the component side and then a wide grounded
> trace over it on the closer inner layer as shielding. So not only is there
> no longer shielding over many traces, these signals are also about .03"
> closer to the component circuitry than they used to be. Can you contemplate
> the nightmare of spurious issues that have been created? We did not notice
> the problem until they were fully populated and almost thru our testing
> process and started failing one of the tests miserably.
> Needless to say, we will be revising our inspection techniques to try to
> catch occurrences like this much sooner.
>
> I was wondering if anyone knows of a way that layer order could be
> electrically tested for on a bare board, that we could require our
> fabricator to complete?
>
> Genny Gibbard (mailto:[log in to unmask])
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
--
Darrel Therriault
VP, Mfg. Operations
INCEP Technologies, Inc
(858)547-9925 223
[log in to unmask]
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Date: Mon, 22 Oct 2001 10:46:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Louis, Edwin @ CSE" <[log in to unmask]>
Subject: Re: Heat of Combustion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Is this a GEBA Epoxy? Was this a measured value? It seems low.
-----Original Message-----
From: FOX, Ian (York Rd) [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 10:34 AM
To: [log in to unmask]
Subject: Re: [TN] Heat of Combustion
From measurements we carried out, about 1kJ/g
Ian Fox
Process Engineering Manager
TRW ASG
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: 22 October 2001 13:28
To: [log in to unmask]
Subject: [TN] Heat of Combustion
Does anyone know what the heat of combustion is for G-10 Epoxy?
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Date: Mon, 22 Oct 2001 16:39:43 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "FOX, Ian (York Rd)" <[log in to unmask]>
Subject: Re: Heat of Combustion
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Yes it was measured by a test lab. The material was a 140degC Tg epoxy
glass. Re-reading the test report (the first quoted figure was off the top
of my head) the figure quoted for the calorific value is 1.5kJ/g.
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: 22 October 2001 15:46
To: [log in to unmask]
Subject: Re: [TN] Heat of Combustion
Is this a GEBA Epoxy? Was this a measured value? It seems low.
-----Original Message-----
From: FOX, Ian (York Rd) [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 10:34 AM
To: [log in to unmask]
Subject: Re: [TN] Heat of Combustion
From measurements we carried out, about 1kJ/g
Ian Fox
Process Engineering Manager
TRW ASG
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: 22 October 2001 13:28
To: [log in to unmask]
Subject: [TN] Heat of Combustion
Does anyone know what the heat of combustion is for G-10 Epoxy?
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Date: Tue, 23 Oct 2001 01:01:57 +0900
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gilbert Min <[log in to unmask]>
Subject: Out of office
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$)C 4Y@= 1b0# 5?>H ;g9+=G@; :q?o ?9A$@T4O4Y : 2001-10-23 - 2001-10-26.
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Date: Mon, 22 Oct 2001 10:13:14 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: gacrowell <[log in to unmask]>
Subject: Re: PCB layers swapped
MIME-Version: 1.0
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Genny,
I've never had the pleasure of a layer swap, but I've heard enough stories
to know its something I want to avoid. There have been several good
suggestions; we use the 'exposed copper edge stairstep', and it has worked
well for a quick view of the stackup, including copper and dielectric
thickness.
We are also careful to include layer id's on each gerber file, and a stackup
table on the fab drawing, and in the readme file, which includes the
filename and stackup positions.
However we don't do this, as one responder suggested:
> then follow up with a read file which creates the stackup
> order by gerber file names vs PWB
> layer.
> TOP.GBR = LAYER 1, COMPONENT SIDE
> GNDA.GBR = LAYER 2, GROUND SHIELD
> SIG1.GBR = LAYER 3, SIGNAL
> GNDB.GBR = LAYER 4, GROUND SHIELD
That is, we include the order by file names and such, but I have a different
approach to file names. When we send a zip of gerber files to a board
house, they know they're getting gerber files (and it says so in the
readme.txt file), so the extension in the example above adds no information.
Other than 'TOP' and 'BOT' the filenames offer no clue about the stackup.
So I use the filename extension in what I feel is a more useful manner.
All of our copper gerber files are of the name format: SSSSSRR.L##.
Where SSSSS is the board s/n or other identifying number, RR is the
revision, and L## is the layer: L01, L02, L03... I don't know about the
cad s/w the board house uses, but on the gerber editors I have used, (most
recently cam350, using the autoimport to load), this loads the layers in the
stackup order and they are then ordered correctly in the layer table, etc.
No need to wonder if PWRA, comes before GNDA, or whatever. The function of
the layer appears in the layer tables.
As an example, our readme layer table looks like this:
Filename Layer Cu plating prepreg est trace trace
oz oz in. width in. D-Code
============= ========= ==== ======= ======= ========= ======
20120r0.TAD top assy dwg
20120r0.FAB fab dwg
20120r0.TSP top paste
20120r0.TSK top silk
20120r0.TSM top mask
20120r0.L01 top 0.5 1.0 .006
.004
20120r0.L02 plane 1.0
.012
20120r0.L03 signal 0.5 .0055
.010
20120r0.L04 signal 0.5 .0055
.012
20120r0.L05 plane 1.0
.003
20120r0.L06 plane 2.0
.023
20120r0.L07 plane 2.0
.003
20120r0.L08 plane 1.0
.012
20120r0.L09 signal 0.5 .0055
.010
20120r0.L10 signal 0.5 .0055
.012
20120r0.L11 plane 1.0
.004
20120r0.L12 bottom 0.5 1.0 .006
20120r0.BSM bottom mask
20120r0.BSK bottom silk
20120r0.BSP bottom paste
20120r0.BAD bottom assy dwg
Now, I don't know that this layer naming is easier for the board house to
use, or less prone to layer swap error, but I haven't had any complaints,
and no swaps either.
Gary Crowell
Micron Technology
> Genny Gibbard wrote:
>
> > Good morning,
> > My morning has not been so good. I have a build of PCB's
> (over 300 boards)
> > where two inner layers have been swapped. The board
> fabricator constructed
> > the board in the wrong order. These boards are RF in
> nature and have
> > frequencies approaching 2GHz on them. In many places we
> put a signal trace
> > on the inner layer furthest from the component side and
> then a wide grounded
> > trace over it on the closer inner layer as shielding. So
> not only is there
> > no longer shielding over many traces, these signals are
> also about .03"
> > closer to the component circuitry than they used to be.
> Can you contemplate
> > the nightmare of spurious issues that have been created?
> We did not notice
> > the problem until they were fully populated and almost thru
> our testing
> > process and started failing one of the tests miserably.
> > Needless to say, we will be revising our inspection
> techniques to try to
> > catch occurrences like this much sooner.
> >
> > I was wondering if anyone knows of a way that layer order could be
> > electrically tested for on a bare board, that we could require our
> > fabricator to complete?
> >
> > Genny Gibbard (mailto:[log in to unmask])
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Date: Mon, 22 Oct 2001 11:18:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Out of office
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
huh??????
okey-dokey!!!!!!
Jason Gregory
Software Specialist - NPI Group
SCI Systems/Plant 2
13000 S. Memorial Pkwy.
Huntsville, AL. 35803
(256) 882-4107 x3728
[log in to unmask]
>>> [log in to unmask] 10/22/01 11:01AM >>>
$)C 4Y@=3D 1b0# 5?>H ;g9+=3DG@; :q?o ?9A$@T4O4Y : 2001-10-23 - =
2001-10-26.
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Date: Mon, 22 Oct 2001 10:39:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: PCB layers swapped
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
There HAVE been many really good suggestions given. I thank everyone. Some
of the suggestions are close to things we have done on other products, but
this product had evolved out of an older product and hadn't been updated
with a 'check window'. Future revisions will incorporate that. We did have
layer names printed on each layer, and the stackup clearly defined in our
readme file (but not anywhere else), and the board fab house has admitted
fault finally.
My unenviable task in the next few weeks is to try to determine if we can
salvage any of the build, by changing components, adding more filtering on
control and power lines, etc, ad nauseum, to correct the spurious. There is
too much value added to the PCB's in the build right now with components
installed and some testing already complete, to easily make a case for
writing it off completely.
Thanks again.
Genny.
-----Original Message-----
From: gacrowell [mailto:[log in to unmask]]
Sent: October 22, 2001 10:13 AM
To: [log in to unmask]
Subject: Re: [TN] PCB layers swapped
Genny,
I've never had the pleasure of a layer swap, but I've heard enough stories
to know its something I want to avoid. There have been several good
suggestions; we use the 'exposed copper edge stairstep', and it has worked
well for a quick view of the stackup, including copper and dielectric
thickness.
We are also careful to include layer id's on each gerber file, and a stackup
table on the fab drawing, and in the readme file, which includes the
filename and stackup positions.
However we don't do this, as one responder suggested:
> then follow up with a read file which creates the stackup
> order by gerber file names vs PWB
> layer.
> TOP.GBR = LAYER 1, COMPONENT SIDE
> GNDA.GBR = LAYER 2, GROUND SHIELD
> SIG1.GBR = LAYER 3, SIGNAL
> GNDB.GBR = LAYER 4, GROUND SHIELD
That is, we include the order by file names and such, but I have a different
approach to file names. When we send a zip of gerber files to a board
house, they know they're getting gerber files (and it says so in the
readme.txt file), so the extension in the example above adds no information.
Other than 'TOP' and 'BOT' the filenames offer no clue about the stackup.
So I use the filename extension in what I feel is a more useful manner.
All of our copper gerber files are of the name format: SSSSSRR.L##.
Where SSSSS is the board s/n or other identifying number, RR is the
revision, and L## is the layer: L01, L02, L03... I don't know about the
cad s/w the board house uses, but on the gerber editors I have used, (most
recently cam350, using the autoimport to load), this loads the layers in the
stackup order and they are then ordered correctly in the layer table, etc.
No need to wonder if PWRA, comes before GNDA, or whatever. The function of
the layer appears in the layer tables.
As an example, our readme layer table looks like this:
Filename Layer Cu plating prepreg est trace trace
oz oz in. width in. D-Code
============= ========= ==== ======= ======= ========= ======
20120r0.TAD top assy dwg
20120r0.FAB fab dwg
20120r0.TSP top paste
20120r0.TSK top silk
20120r0.TSM top mask
20120r0.L01 top 0.5 1.0 .006
.004
20120r0.L02 plane 1.0
.012
20120r0.L03 signal 0.5 .0055
.010
20120r0.L04 signal 0.5 .0055
.012
20120r0.L05 plane 1.0
.003
20120r0.L06 plane 2.0
.023
20120r0.L07 plane 2.0
.003
20120r0.L08 plane 1.0
.012
20120r0.L09 signal 0.5 .0055
.010
20120r0.L10 signal 0.5 .0055
.012
20120r0.L11 plane 1.0
.004
20120r0.L12 bottom 0.5 1.0 .006
20120r0.BSM bottom mask
20120r0.BSK bottom silk
20120r0.BSP bottom paste
20120r0.BAD bottom assy dwg
Now, I don't know that this layer naming is easier for the board house to
use, or less prone to layer swap error, but I haven't had any complaints,
and no swaps either.
Gary Crowell
Micron Technology
> Genny Gibbard wrote:
>
> > Good morning,
> > My morning has not been so good. I have a build of PCB's
> (over 300 boards)
> > where two inner layers have been swapped. The board
> fabricator constructed
> > the board in the wrong order. These boards are RF in
> nature and have
> > frequencies approaching 2GHz on them. In many places we
> put a signal trace
> > on the inner layer furthest from the component side and
> then a wide grounded
> > trace over it on the closer inner layer as shielding. So
> not only is there
> > no longer shielding over many traces, these signals are
> also about .03"
> > closer to the component circuitry than they used to be.
> Can you contemplate
> > the nightmare of spurious issues that have been created?
> We did not notice
> > the problem until they were fully populated and almost thru
> our testing
> > process and started failing one of the tests miserably.
> > Needless to say, we will be revising our inspection
> techniques to try to
> > catch occurrences like this much sooner.
> >
> > I was wondering if anyone knows of a way that layer order could be
> > electrically tested for on a bare board, that we could require our
> > fabricator to complete?
> >
> > Genny Gibbard (mailto:[log in to unmask])
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=========================================================================
Date: Mon, 22 Oct 2001 13:04:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Telgen <[log in to unmask]>
Subject: Re: PCB layers swapped
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Gary, to add to your comment, we use Valor's Genesis software here, and in
absence of a script specifically designed for a customer's naming
convention, Genesis loads layers of like type in alpha-numeric order. Thus,
your naming convention would work perfectly, since the names would be the
same and the extensions would be ordered by number. To everyone else's
comment, I have to agree that the layer order is the responsibility of the
fab house. I personally don't like the stair-stepping on the inner layers,
since normally inner layer copper exposure causes DFM errors. To fool-proof
it (as much as possible) the best way would be to place a daisy-chain design
into the board itself, then electrically test the board.
Steve Telgen
IGK Industries
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of gacrowell
Sent: Monday, October 22, 2001 12:13
To: [log in to unmask]
Subject: Re: [TN] PCB layers swapped
Genny,
I've never had the pleasure of a layer swap, but I've heard enough stories
to know its something I want to avoid. There have been several good
suggestions; we use the 'exposed copper edge stairstep', and it has worked
well for a quick view of the stackup, including copper and dielectric
thickness.
We are also careful to include layer id's on each gerber file, and a stackup
table on the fab drawing, and in the readme file, which includes the
filename and stackup positions.
However we don't do this, as one responder suggested:
> then follow up with a read file which creates the stackup
> order by gerber file names vs PWB
> layer.
> TOP.GBR = LAYER 1, COMPONENT SIDE
> GNDA.GBR = LAYER 2, GROUND SHIELD
> SIG1.GBR = LAYER 3, SIGNAL
> GNDB.GBR = LAYER 4, GROUND SHIELD
That is, we include the order by file names and such, but I have a different
approach to file names. When we send a zip of gerber files to a board
house, they know they're getting gerber files (and it says so in the
readme.txt file), so the extension in the example above adds no information.
Other than 'TOP' and 'BOT' the filenames offer no clue about the stackup.
So I use the filename extension in what I feel is a more useful manner.
All of our copper gerber files are of the name format: SSSSSRR.L##.
Where SSSSS is the board s/n or other identifying number, RR is the
revision, and L## is the layer: L01, L02, L03... I don't know about the
cad s/w the board house uses, but on the gerber editors I have used, (most
recently cam350, using the autoimport to load), this loads the layers in the
stackup order and they are then ordered correctly in the layer table, etc.
No need to wonder if PWRA, comes before GNDA, or whatever. The function of
the layer appears in the layer tables.
As an example, our readme layer table looks like this:
Filename Layer Cu plating prepreg est trace trace
oz oz in. width in. D-Code
============= ========= ==== ======= ======= ========= ======
20120r0.TAD top assy dwg
20120r0.FAB fab dwg
20120r0.TSP top paste
20120r0.TSK top silk
20120r0.TSM top mask
20120r0.L01 top 0.5 1.0 .006
.004
20120r0.L02 plane 1.0
.012
20120r0.L03 signal 0.5 .0055
.010
20120r0.L04 signal 0.5 .0055
.012
20120r0.L05 plane 1.0
.003
20120r0.L06 plane 2.0
.023
20120r0.L07 plane 2.0
.003
20120r0.L08 plane 1.0
.012
20120r0.L09 signal 0.5 .0055
.010
20120r0.L10 signal 0.5 .0055
.012
20120r0.L11 plane 1.0
.004
20120r0.L12 bottom 0.5 1.0 .006
20120r0.BSM bottom mask
20120r0.BSK bottom silk
20120r0.BSP bottom paste
20120r0.BAD bottom assy dwg
Now, I don't know that this layer naming is easier for the board house to
use, or less prone to layer swap error, but I haven't had any complaints,
and no swaps either.
Gary Crowell
Micron Technology
> Genny Gibbard wrote:
>
> > Good morning,
> > My morning has not been so good. I have a build of PCB's
> (over 300 boards)
> > where two inner layers have been swapped. The board
> fabricator constructed
> > the board in the wrong order. These boards are RF in
> nature and have
> > frequencies approaching 2GHz on them. In many places we
> put a signal trace
> > on the inner layer furthest from the component side and
> then a wide grounded
> > trace over it on the closer inner layer as shielding. So
> not only is there
> > no longer shielding over many traces, these signals are
> also about .03"
> > closer to the component circuitry than they used to be.
> Can you contemplate
> > the nightmare of spurious issues that have been created?
> We did not notice
> > the problem until they were fully populated and almost thru
> our testing
> > process and started failing one of the tests miserably.
> > Needless to say, we will be revising our inspection
> techniques to try to
> > catch occurrences like this much sooner.
> >
> > I was wondering if anyone knows of a way that layer order could be
> > electrically tested for on a bare board, that we could require our
> > fabricator to complete?
> >
> > Genny Gibbard (mailto:[log in to unmask])
----------------------------------------------------------------------------
-----
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
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----------------------------------------------------------------------------
-----
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Mon, 22 Oct 2001 10:29:10 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ross Winters <[log in to unmask]>
Subject: Too Much (good) Information, changing PCs, I can't keep up.
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Steve Telgen
Sent: Monday, October 22, 2001 10:05 AM
To: [log in to unmask]
Subject: Re: [TN] PCB layers swapped
Gary, to add to your comment, we use Valor's Genesis software here, and in
absence of a script specifically designed for a customer's naming
convention, Genesis loads layers of like type in alpha-numeric order. Thus,
your naming convention would work perfectly, since the names would be the
same and the extensions would be ordered by number. To everyone else's
comment, I have to agree that the layer order is the responsibility of the
fab house. I personally don't like the stair-stepping on the inner layers,
since normally inner layer copper exposure causes DFM errors. To fool-proof
it (as much as possible) the best way would be to place a daisy-chain design
into the board itself, then electrically test the board.
Steve Telgen
IGK Industries
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of gacrowell
Sent: Monday, October 22, 2001 12:13
To: [log in to unmask]
Subject: Re: [TN] PCB layers swapped
Genny,
I've never had the pleasure of a layer swap, but I've heard enough stories
to know its something I want to avoid. There have been several good
suggestions; we use the 'exposed copper edge stairstep', and it has worked
well for a quick view of the stackup, including copper and dielectric
thickness.
We are also careful to include layer id's on each gerber file, and a stackup
table on the fab drawing, and in the readme file, which includes the
filename and stackup positions.
However we don't do this, as one responder suggested:
> then follow up with a read file which creates the stackup
> order by gerber file names vs PWB
> layer.
> TOP.GBR = LAYER 1, COMPONENT SIDE
> GNDA.GBR = LAYER 2, GROUND SHIELD
> SIG1.GBR = LAYER 3, SIGNAL
> GNDB.GBR = LAYER 4, GROUND SHIELD
That is, we include the order by file names and such, but I have a different
approach to file names. When we send a zip of gerber files to a board
house, they know they're getting gerber files (and it says so in the
readme.txt file), so the extension in the example above adds no information.
Other than 'TOP' and 'BOT' the filenames offer no clue about the stackup.
So I use the filename extension in what I feel is a more useful manner.
All of our copper gerber files are of the name format: SSSSSRR.L##.
Where SSSSS is the board s/n or other identifying number, RR is the
revision, and L## is the layer: L01, L02, L03... I don't know about the
cad s/w the board house uses, but on the gerber editors I have used, (most
recently cam350, using the autoimport to load), this loads the layers in the
stackup order and they are then ordered correctly in the layer table, etc.
No need to wonder if PWRA, comes before GNDA, or whatever. The function of
the layer appears in the layer tables.
As an example, our readme layer table looks like this:
Filename Layer Cu plating prepreg est trace trace
oz oz in. width in. D-Code
============= ========= ==== ======= ======= ========= ======
20120r0.TAD top assy dwg
20120r0.FAB fab dwg
20120r0.TSP top paste
20120r0.TSK top silk
20120r0.TSM top mask
20120r0.L01 top 0.5 1.0 .006
.004
20120r0.L02 plane 1.0
.012
20120r0.L03 signal 0.5 .0055
.010
20120r0.L04 signal 0.5 .0055
.012
20120r0.L05 plane 1.0
.003
20120r0.L06 plane 2.0
.023
20120r0.L07 plane 2.0
.003
20120r0.L08 plane 1.0
.012
20120r0.L09 signal 0.5 .0055
.010
20120r0.L10 signal 0.5 .0055
.012
20120r0.L11 plane 1.0
.004
20120r0.L12 bottom 0.5 1.0 .006
20120r0.BSM bottom mask
20120r0.BSK bottom silk
20120r0.BSP bottom paste
20120r0.BAD bottom assy dwg
Now, I don't know that this layer naming is easier for the board house to
use, or less prone to layer swap error, but I haven't had any complaints,
and no swaps either.
Gary Crowell
Micron Technology
> Genny Gibbard wrote:
>
> > Good morning,
> > My morning has not been so good. I have a build of PCB's
> (over 300 boards)
> > where two inner layers have been swapped. The board
> fabricator constructed
> > the board in the wrong order. These boards are RF in
> nature and have
> > frequencies approaching 2GHz on them. In many places we
> put a signal trace
> > on the inner layer furthest from the component side and
> then a wide grounded
> > trace over it on the closer inner layer as shielding. So
> not only is there
> > no longer shielding over many traces, these signals are
> also about .03"
> > closer to the component circuitry than they used to be.
> Can you contemplate
> > the nightmare of spurious issues that have been created?
> We did not notice
> > the problem until they were fully populated and almost thru
> our testing
> > process and started failing one of the tests miserably.
> > Needless to say, we will be revising our inspection
> techniques to try to
> > catch occurrences like this much sooner.
> >
> > I was wondering if anyone knows of a way that layer order could be
> > electrically tested for on a bare board, that we could require our
> > fabricator to complete?
> >
> > Genny Gibbard (mailto:[log in to unmask])
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Date: Mon, 22 Oct 2001 13:47:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Louis, Edwin @ CSE" <[log in to unmask]>
Subject: Thermally Conducting Adhesive
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What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 12:43:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PCB layers swapped
X-To: "Gary A. Crowell" <[log in to unmask]>
Lamination and/or relamination in a board shop was/is one of my favorite
things. 90 plus % of the MLB structure is in the z axis where most folks
don't often venture.
CAD and CAM are wonderful tools reaching many parts of the shop. They do not
reach or interface with the chemical world at all. Often, they do not affect
the lamination part of the process as this, beyond progammable presses, is
not part of the layup process. Typically, layup (wherein pregs and details
come together in books) are manually driven by very conciencious process
managers who stack every layer together right or wrong. Most often they are
right.
Do as you will, the window or side tabs take priority. Etched details (inner
layers or inners) are laid up by folks paying attention to what needs doing.
Designers and CAM folks see all the Gerber or ODB++ stuff, never missing a
beat, then they send it on down the line, in most shops. via travellers or
other paper driven stuff though many other shops have this information
available for viewing on computers. Still, the operator is the key.
MoonMan
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Date: Mon, 22 Oct 2001 12:56:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Antw: [TN] IMC'S - NO LONGER STIRRING THE POT
X-To: "<Guenter Grossmann>" <[log in to unmask]>
Guenter,
Very clearly stated and appreciated that way. Still, being a stubborn not
very insightful and often ignorant sort, I get some of it but not all.
I realize "wetting" is a function of diffusion and intermetallic formation,
I think. It's the surface thing that still has me going. Werner said, as we
all should understand, that surface scientists know there are a specified
number of atomic layers, measured in Angstroms, composing an objects
surface. If it is 1000, is this the "depth" to which diffusion takes place?
Beyond this, is this fair ground as well, or does Manko's old definition
still hold up?
I know these questions have been answered, just as they have been asked,
before many times, as we all have read and studied. It still bothers me and,
I think, that is fair as soldering, solder, and the process in which metal
SURFACES are joined using, I presume, a uetectic alloy will be questioned
and answered many more times in the future. Simply, I want to get real
comfortable, not as a surface scientist, but as a manufacturing engineering
soldering guy on the floor so I can move to life without lead but,
hopefully, with some other eutectic alloy used to joing "metal" surfaces.
Earl
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Date: Mon, 22 Oct 2001 14:07:14 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Trimming Leads...
In-Reply-To: <[log in to unmask]>
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I respectfully disagree. The IPC-A-610C is a support document. It assumes a
great deal about the assembly. It is a workmanship / inspection standard
designed to qualify end items manufactured using J-STD-001C compliant
materials and processes.
Blindly using the A-610 as an acceptance standard is very dangerous.
Consider the 75% vertical fill requirement. This is acceptable because we
assume that the bare board passed J-STD-003 requirements and IPC-6012A
performance requirements. If the board has poor plating you would pass
garbage on to your customer.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Sauer, Steven T.
> Sent: Thursday, October 18, 2001 8:48 AM
> To: [log in to unmask]
> Subject: Re: [TN] Trimming Leads...
>
>
> Thomas:
> IPC-A-610 is an "acceptability standard" or "workmanship standard" not a
> process requirements standard. As you pointed out, rev B attempted to
> require a soldering touch-up operation. Rev C properly set the standard
> straight by requiring the leads to be visually inspected at 10X
> and follows
> with the words, "as an alternative to visual inspection, the solder
> connections may be reflowed." This all comes down to the process being
> employed: "solder/cut/solder/inspect" or "solder/cut/inspect" by the
> manufacturer, not by a workmanship standard trying to dictate process
> requirements. The objective of 610 is provide accept/reject
> criteria after
> processing -- which has been accomplished quite well in Rev C and the
> proposed Amendment 1.
>
> Steve Sauer
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Date: Mon, 22 Oct 2001 13:16:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
In-Reply-To: <[log in to unmask]>
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Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Mon, 22 Oct 2001 14:34:11 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
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OK, let me try saying this a different way:
it "seems" that the canning industry has an easy time putting tin on can
steel. Why do I have trouble getting solder to stick to a properly
preheated 100% iron surface? Is it just a matter of flux strength? Or
something else?
Bev Christian
Research in Motion
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: October 22, 2001 4:17 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Mon, 22 Oct 2001 14:48:23 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jerry Mosur <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
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Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 14:50:36 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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It must be flux strength. I have watched little old ladies solder wires to
nails. They were using zinc chloride. Destroyed the solder iron tips but did
what they wanted.
We also made some custom tips for Pace solder pens. They were stainless, we
solder plated them too. They did not last as long nor work as good as the
store bought ones but they were less expensive. We did not measure the tip
temperature offset . . . oh yeah you were only asking about soldering iron .
. . ramble on.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> Sent: Monday, October 22, 2001 2:34 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
>
> OK, let me try saying this a different way:
> it "seems" that the canning industry has an easy time putting tin on can
> steel. Why do I have trouble getting solder to stick to a properly
> preheated 100% iron surface? Is it just a matter of flux strength? Or
> something else?
>
> Bev Christian
> Research in Motion
>
> -----Original Message-----
> From: Mel Parrish [mailto:[log in to unmask]]
> Sent: October 22, 2001 4:17 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
>
> Dr Bev,
> Not sure what your question is but for discussion. Many of the common
> component lead frames contain significant amounts of iron which
> is plated to
> enhance solderability, limit corrosion, etc.. Seems that there should be
> some metallurgists out there that can lead us to understanding the
> solubility characteristics but my text books discuss FeSn intermetalics
> although the rate is slower that that of tin gold or tin copper.
> Also seems
> to me that the Nickel content is important to the solder interface.
>
> Mel Parrish
> Soldering Technology International
> 102 Tribble Drive
> Madison, AL 35758
> 256 705 5530
> 256 705 5538 Fax
> [log in to unmask]
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> Sent: Friday, October 19, 2001 2:01 PM
> To: [log in to unmask]
> Subject: [TN] tin on iron and solder on iron
>
>
> OK, here is a general question for all you met guys. But I am not sure I
> can explain it well enough to be understood!
>
> We all know that tin can be put on iron or we wouldn't have "tin" cans. I
> also know it is difficult to put solder on iron. So my question
> is this: if
> one has a tinned iron surface and it is put into molten solder
> the tin will
> be dissolved into the molten solder. I presume when the piece of iron is
> withdrawn from the pot, solder will be well adhered to the iron. Is this
> because there is a solderable tin/iron intermetallic? What is the main
> difference between the tin can process and putting solder directly on iron
> that makes one easy to do and the other difficult? This may be a "first
> grade" met question, but I don't know the answer. Thanks.
>
> Bev Christian
>
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Date: Mon, 22 Oct 2001 13:46:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
X-To: Bev Christian <[log in to unmask]>
Bev,
Howdy partner from the moonman in BF Montana again. Know little about tin
cans but for those housing Bud. Hell, that's aluminum and I know how those
cans are formed after having served time at Coors as an automated brewing
process engineer - whoops!
I know this doesn't answer it and I know you know this but I have too much
time on my hands. Soldering iron tims are made/formed/extruded from copper
as wire. They are properly shaped and plated with a "neutral" metal as iron
- to the soldering process when prevented from oxidizing by being properly
tinned. Properly "tinned" tips, the iron part (1 mil thick iron plating
over copper), ensure acceptable solderable surfaces provide they are cleaned
and re-tinned as often as needed.
Jeez, why am I going on with this as you are only asking about tin cans.
Could they be soldered using the same concept. When you get a "real" answer,
let me know and thanks again for all that Nortel info. It, and the contacts
you provided, really did the trick. Wish Nortel was in better health.
Respectfully,
Earl Moon
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Date: Tue, 23 Oct 2001 07:58:14 +1300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: Re: Conformal Coat Spray Systems
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Rick,
I have compared and trialled all three machines, Nordson, SCS and PVA with
silicones. I agree, the PVA is the best by far. It is the simpliest
machine in both software and hardware attributes. The only downside I have
found with the PVA is the chassis. It is simply extruded aluminium bolted
together. But overall, go for the PVA.
If you want any more details, feel free to contact me directly.
Cheers
-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Tuesday, 23 October 2001 03:27
To: [log in to unmask]
Subject: Re: [TN] Conformal Coat Spray Systems
Jon,
Thanks for the offer. You're the second person I've had recommend PVA...I
wasn't aware of them. I would be interested in how the compare to the
Nordson or SCS systems if you've had experience with either of them.
Regards,
Rick Thompson
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jon Moore
Sent: Friday, October 19, 2001 7:22 PM
To: [log in to unmask]
Subject: Re: [TN] Conformal Coat Spray Systems
In a message dated 10/19/2001 6:28:39 PM US Eastern Standard Time,
[log in to unmask] writes:
<< Does anyone have any system or manufacturer recommendations,
pro or con that they'd care to share with me offline? >>
I have used several different systems, and I would recommend PVA hands down
over everything. I would be glad to share details with you.
Jon Moore
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Date: Mon, 22 Oct 2001 15:07:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 15:15:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bev,
I thought that the tin on cans might be plated, rather than
soldered, and found a reference to that effect at:
http://www.steel.org/containers/spc/tin_production2.htm
I cannot be certain that some aren't "hot tin coated", but the reference
seems to indicate that very high speed processes are used to electroplate
the tin to the steel.
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 434-978-5181
FAX: 434-978-5898
e-mail: [log in to unmask]
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 2:34 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
OK, let me try saying this a different way:
it "seems" that the canning industry has an easy time putting tin on can
steel. Why do I have trouble getting solder to stick to a properly
preheated 100% iron surface? Is it just a matter of flux strength? Or
something else?
Bev Christian
Research in Motion
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: October 22, 2001 4:17 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Mon, 22 Oct 2001 15:27:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brewer <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
>From: "Louis, Edwin @ CSE" <[log in to unmask]>
>Subject: Thermally Conducting Adhesive
>What is a good thermally conducting adhesive for placement unter a metal
>quad flat pack device?
Edwin,
I'm not sure if they make one specifically for a QFP (though I bet
they do) but Bergquist makes a product called a SILPAD, which is a dry
thermal transfer agent. This is a MUCH easier product to keep process
control
of, than paste type thermal transfer agents.
I'd recommend you look into their stuff, or a similar dry product.
Best
John Brewer
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Date: Mon, 22 Oct 2001 15:30:51 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Greg, Guy
Ah, the lights come on! Electroplating - a totally different animal. I'm
embarrassed that I did not think of this possibility.
Yes, I guess with a strong enough flux you can "solder to wood."
For all the rest of my TechNet friends that replied: it is interesting to
note that several of your couched your replies in terms of soldering irons
or component leads (the latter which might be Alloy 42). I was not think
about soldering irons or leads, but was just wondering about a truly general
observation. Now I have my answers.
Thanks, everyone.
Bev Christian
Research in Motion
-----Original Message-----
From: Anderson, Greg (IndSys, GEFanuc, NA)
[mailto:[log in to unmask]]
Sent: October 22, 2001 3:15 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Bev,
I thought that the tin on cans might be plated, rather than
soldered, and found a reference to that effect at:
http://www.steel.org/containers/spc/tin_production2.htm
I cannot be certain that some aren't "hot tin coated", but the reference
seems to indicate that very high speed processes are used to electroplate
the tin to the steel.
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 434-978-5181
FAX: 434-978-5898
e-mail: [log in to unmask]
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 2:34 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
OK, let me try saying this a different way:
it "seems" that the canning industry has an easy time putting tin on can
steel. Why do I have trouble getting solder to stick to a properly
preheated 100% iron surface? Is it just a matter of flux strength? Or
something else?
Bev Christian
Research in Motion
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: October 22, 2001 4:17 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Mon, 22 Oct 2001 13:22:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Todd Thacker <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
I agree, if I were snding out emales taling peeple to get there speling
corect I wood shure dubble check my speling two.
-----Original Message-----
From: Steve Kelly [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:07 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 15:48:25 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jerry Mosur <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Sorry if I offended anyone.
What I meant was, of course, LOCTITE Corp. and their web site:
www.loctite.com .
Again, please accept my apologies.
-----Original Message-----
From: Steve Kelly [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 3:07 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 14:41:18 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Bev,
How come you are soldering those wires to cans anyhow. I thought those new
fangled communication devices used the strings.
P.S. I think it's the flux activity level that supports elements that have
surface oxidation issues. My handy dandy Kester flux selector slide rule
says to use Acid Core flux for iron or mild steel.
Mel Parrish
Soldering Technology International
Madison, AL
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Monday, October 22, 2001 11:34 AM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
OK, let me try saying this a different way:
it "seems" that the canning industry has an easy time putting tin on can
steel. Why do I have trouble getting solder to stick to a properly
preheated 100% iron surface? Is it just a matter of flux strength? Or
something else?
Bev Christian
Research in Motion
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: October 22, 2001 4:17 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Mon, 22 Oct 2001 10:55:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: BUS WIRE
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I'm looking for an industry (or MIL) standard for un-insulated, solid copper
bus wire, either silver plated or solder coated, no pure tin, please.
Thanks in advance...
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Mon, 22 Oct 2001 14:59:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mario Hernandez <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Gens,
All depend on which is your cure conditions (room temperature, oven, 1 o 2
components), process requirements, etc.?
Louis, you can contact to Chris Marinelli or Ed Fisher in the US at
1-800-LOCTITE (562 8483) if you are interested for more details about those
products,
Mario Hernandez
Jerry Mosur
<jmosur@SPELL Para: [log in to unmask]
MANHV.COM> cc:
Enviado por: Asunto: Re: [TN] Thermally
TechNet Conducting Adhesive
<[log in to unmask]
ORG>
22/10/01
02:48 p.m.
Por favor,
responda a
"TechNet
E-Mail
Forum."
Sorry if I offended anyone.
What I meant was, of course, LOCTITE Corp. and their web site:
www.loctite.com .
Again, please accept my apologies.
-----Original Message-----
From: Steve Kelly [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 3:07 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Mon, 22 Oct 2001 17:38:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: BUS WIRE
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Go to DODISS on Government web and look under bus wire. I believe QQ-W-343
is one spec.
----- Original Message -----
From: "Marsico, James" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, October 22, 2001 10:55 AM
Subject: [TN] BUS WIRE
> I'm looking for an industry (or MIL) standard for un-insulated, solid
copper
> bus wire, either silver plated or solder coated, no pure tin, please.
> Thanks in advance...
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date: Mon, 22 Oct 2001 19:12:19 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: BUS WIRE
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_90.1bb53a24.290601d3_boundary"
--part1_90.1bb53a24.290601d3_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Jim!
GLB was right about QQ-W-343, but it has been canceled and replaced with:
Wire, Electrical, Copper (Uninsulated)
FSC 6145
Federal Specification QQ-W-343G, dated 18 April 1997, is hereby canceled.
Future acquisition for this material should refer to commercial item
description (CID) <A HREF="http://www.dscc.dla.mil/Programs/MilSpec/listdocs.asp?BasicDoc=A-A-59551">A-A-59551</A>, Wire, Electrical, Copper (Uninsulated).
Which can be had for your downloading pleasure at:
http://www.dscc.dla.mil/Downloads/MilSpec/Docs/A-A-59551/aa59551.pdf
If you need to buy this wire, it can be had by contacting someone at:
http://www.sea-wire.com/
I know the problems with tin plated bus wire, you try and solder to it, the
tin dissolves and leaves you with bare copper, switched to silver plated wire
and the problem went away...
-Steve Gregory-
> I'm looking for an industry (or MIL) standard for un-insulated, solid copper
> bus wire, either silver plated or solder coated, no pure tin, please.
> Thanks in advance...
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
--part1_90.1bb53a24.290601d3_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Hi Jim!<BR>
<BR>
GLB was right about QQ-W-343, but it has been canceled and replaced with:<BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Verdana" LANG="0"><B>Wire, Electrical, Copper (Uninsulated)</B> <BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0"><B>FSC 6145</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Verdana" LANG="0"></B> <BR>
Federal Specification QQ-W-343G, dated 18 April 1997, is hereby canceled. Future acquisition for this material should refer to commercial item description (CID) <A HREF="http://www.dscc.dla.mil/Programs/MilSpec/listdocs.asp?BasicDoc=A-A-59551">A-A-59551</A>, Wire, Electrical, Copper (Uninsulated).<BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Verdana" LANG="0">Which can be had for your downloading pleasure at:</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Verdana" LANG="0"> <BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
http://www.dscc.dla.mil/Downloads/MilSpec/Docs/A-A-59551/aa59551.pdf<BR>
<BR>
If you need to buy this wire, it can be had by contacting someone at:<BR>
<BR>
http://www.sea-wire.com/<BR>
<BR>
I know the problems with tin plated bus wire, you try and solder to it, the tin dissolves and leaves you with bare copper, switched to silver plated wire and the problem went away...<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I'm looking for an industry (or MIL) standard for un-insulated, solid copper<BR>
bus wire, either silver plated or solder coated, no pure tin, please.<BR>
Thanks in advance...<BR>
<BR>
Jim Marsico<BR>
Senior Engineer<BR>
Production Engineering<BR>
EDO Electronics Systems Group<BR>
[log in to unmask] <mailto:[log in to unmask]><BR>
631-595-5879<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Mon, 22 Oct 2001 16:26:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: PCB layers swapped
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Genny
Another solution no one has mentioned is to put a controlled impedance
requirement and coupon on the board that will catch any reversed layers.
For instance if you had a 4-layer board, you put a ground plane on layer 2,
leave layer 3 blank, then put microstrip traces on layers 1 and referencing
layer 2. If the layers on the center core get flipped, layer 1 will read
high and layer 4 low. The coupon doesn't even have to reflect the true
impedance requirements of the board but can be designed to increase the
sensitivity to dielectric thickness changes. It sounds like you had a
0.030" core flipped and this certainly could have been caught with this type
of test.
> ----------
> From: Genny Gibbard[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Monday, October 22, 2001 9:39 AM
> To: [log in to unmask]
> Subject: Re: [TN] PCB layers swapped
>
> There HAVE been many really good suggestions given. I thank everyone.
> Some
> of the suggestions are close to things we have done on other products, but
> this product had evolved out of an older product and hadn't been updated
> with a 'check window'. Future revisions will incorporate that. We did
> have
> layer names printed on each layer, and the stackup clearly defined in our
> readme file (but not anywhere else), and the board fab house has admitted
> fault finally.
> My unenviable task in the next few weeks is to try to determine if we can
> salvage any of the build, by changing components, adding more filtering on
> control and power lines, etc, ad nauseum, to correct the spurious. There
> is
> too much value added to the PCB's in the build right now with components
> installed and some testing already complete, to easily make a case for
> writing it off completely.
>
> Thanks again.
> Genny.
>
> -----Original Message-----
> From: gacrowell [mailto:[log in to unmask]]
> Sent: October 22, 2001 10:13 AM
> To: [log in to unmask]
> Subject: Re: [TN] PCB layers swapped
>
>
> Genny,
>
> I've never had the pleasure of a layer swap, but I've heard enough stories
> to know its something I want to avoid. There have been several good
> suggestions; we use the 'exposed copper edge stairstep', and it has worked
> well for a quick view of the stackup, including copper and dielectric
> thickness.
>
> We are also careful to include layer id's on each gerber file, and a
> stackup
> table on the fab drawing, and in the readme file, which includes the
> filename and stackup positions.
>
> However we don't do this, as one responder suggested:
>
> > then follow up with a read file which creates the stackup
> > order by gerber file names vs PWB
> > layer.
> > TOP.GBR = LAYER 1, COMPONENT SIDE
> > GNDA.GBR = LAYER 2, GROUND SHIELD
> > SIG1.GBR = LAYER 3, SIGNAL
> > GNDB.GBR = LAYER 4, GROUND SHIELD
>
>
> That is, we include the order by file names and such, but I have a
> different
> approach to file names. When we send a zip of gerber files to a board
> house, they know they're getting gerber files (and it says so in the
> readme.txt file), so the extension in the example above adds no
> information.
> Other than 'TOP' and 'BOT' the filenames offer no clue about the stackup.
> So I use the filename extension in what I feel is a more useful manner.
>
> All of our copper gerber files are of the name format: SSSSSRR.L##.
>
> Where SSSSS is the board s/n or other identifying number, RR is the
> revision, and L## is the layer: L01, L02, L03... I don't know about the
> cad s/w the board house uses, but on the gerber editors I have used, (most
> recently cam350, using the autoimport to load), this loads the layers in
> the
> stackup order and they are then ordered correctly in the layer table, etc.
> No need to wonder if PWRA, comes before GNDA, or whatever. The function
> of
> the layer appears in the layer tables.
>
> As an example, our readme layer table looks like this:
>
>
> Filename Layer Cu plating prepreg est trace trace
> oz oz in. width in. D-Code
> ============= ========= ==== ======= ======= ========= ======
>
> 20120r0.TAD top assy dwg
>
> 20120r0.FAB fab dwg
> 20120r0.TSP top paste
> 20120r0.TSK top silk
> 20120r0.TSM top mask
>
> 20120r0.L01 top 0.5 1.0 .006
> .004
> 20120r0.L02 plane 1.0
> .012
> 20120r0.L03 signal 0.5 .0055
> .010
> 20120r0.L04 signal 0.5 .0055
> .012
> 20120r0.L05 plane 1.0
> .003
> 20120r0.L06 plane 2.0
> .023
> 20120r0.L07 plane 2.0
> .003
> 20120r0.L08 plane 1.0
> .012
> 20120r0.L09 signal 0.5 .0055
> .010
> 20120r0.L10 signal 0.5 .0055
> .012
> 20120r0.L11 plane 1.0
> .004
> 20120r0.L12 bottom 0.5 1.0 .006
>
>
> 20120r0.BSM bottom mask
> 20120r0.BSK bottom silk
> 20120r0.BSP bottom paste
>
> 20120r0.BAD bottom assy dwg
>
>
>
> Now, I don't know that this layer naming is easier for the board house to
> use, or less prone to layer swap error, but I haven't had any complaints,
> and no swaps either.
>
> Gary Crowell
> Micron Technology
>
>
>
>
>
>
> > Genny Gibbard wrote:
> >
> > > Good morning,
> > > My morning has not been so good. I have a build of PCB's
> > (over 300 boards)
> > > where two inner layers have been swapped. The board
> > fabricator constructed
> > > the board in the wrong order. These boards are RF in
> > nature and have
> > > frequencies approaching 2GHz on them. In many places we
> > put a signal trace
> > > on the inner layer furthest from the component side and
> > then a wide grounded
> > > trace over it on the closer inner layer as shielding. So
> > not only is there
> > > no longer shielding over many traces, these signals are
> > also about .03"
> > > closer to the component circuitry than they used to be.
> > Can you contemplate
> > > the nightmare of spurious issues that have been created?
> > We did not notice
> > > the problem until they were fully populated and almost thru
> > our testing
> > > process and started failing one of the tests miserably.
> > > Needless to say, we will be revising our inspection
> > techniques to try to
> > > catch occurrences like this much sooner.
> > >
> > > I was wondering if anyone knows of a way that layer order could be
> > > electrically tested for on a bare board, that we could require our
> > > fabricator to complete?
> > >
> > > Genny Gibbard (mailto:[log in to unmask])
>
> --------------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 10:01:04 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
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Subject: 0.8mm pitch BGA socket
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Date: Tue, 23 Oct 2001 08:14:04 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Guy,
I'm now curious. Why little old ladies? what were they making with these
wired nails? and why were you watching them?
I hope I don't regret asking these questions, we know what happened to the
curious cat!
On a more serious note, and to address the original question, intermetallics
will form between two metals when that is the stable reaction. See Hanson's
'Constitution of Binary Alloys.' This is a very good standard reference
work, though probably out of print by now. It is known that the Romans
soldered lead piping for their plumbing systems (plumbum-lead) and this
would not have formed any intermetallic even though good joints were made.
In this case the tin and lead form a solid solution which is the stable
product of the two metals involved. Therefore, it is not strictly correct to
say that an intermetallic is a requirement for a good soldered joint,
rather, that the intermetallic is a product of a good soldered joint between
copper and tin or iron and tin.
The flux is there to remove oxides and allow the solder and the base metal
to come into intimate contact and to aid heat transfer.
Regards
Eric Dawson
> -----Original Message-----
> From: Guy Ramsey [SMTP:[log in to unmask]]
> Sent: Monday, October 22, 2001 7:51 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
> It must be flux strength. I have watched little old ladies solder wires to
> nails. They were using zinc chloride. Destroyed the solder iron tips but
> did
> what they wanted.
>
> We also made some custom tips for Pace solder pens. They were stainless,
> we
> solder plated them too. They did not last as long nor work as good as the
> store bought ones but they were less expensive. We did not measure the tip
> temperature offset . . . oh yeah you were only asking about soldering iron
> .
> . . ramble on.
>
>
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > Sent: Monday, October 22, 2001 2:34 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> >
> > OK, let me try saying this a different way:
> > it "seems" that the canning industry has an easy time putting tin on can
> > steel. Why do I have trouble getting solder to stick to a properly
> > preheated 100% iron surface? Is it just a matter of flux strength? Or
> > something else?
> >
> > Bev Christian
> > Research in Motion
> >
> > -----Original Message-----
> > From: Mel Parrish [mailto:[log in to unmask]]
> > Sent: October 22, 2001 4:17 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> >
> > Dr Bev,
> > Not sure what your question is but for discussion. Many of the common
> > component lead frames contain significant amounts of iron which
> > is plated to
> > enhance solderability, limit corrosion, etc.. Seems that there should
> be
> > some metallurgists out there that can lead us to understanding the
> > solubility characteristics but my text books discuss FeSn intermetalics
> > although the rate is slower that that of tin gold or tin copper.
> > Also seems
> > to me that the Nickel content is important to the solder interface.
> >
> > Mel Parrish
> > Soldering Technology International
> > 102 Tribble Drive
> > Madison, AL 35758
> > 256 705 5530
> > 256 705 5538 Fax
> > [log in to unmask]
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > Sent: Friday, October 19, 2001 2:01 PM
> > To: [log in to unmask]
> > Subject: [TN] tin on iron and solder on iron
> >
> >
> > OK, here is a general question for all you met guys. But I am not sure
> I
> > can explain it well enough to be understood!
> >
> > We all know that tin can be put on iron or we wouldn't have "tin" cans.
> I
> > also know it is difficult to put solder on iron. So my question
> > is this: if
> > one has a tinned iron surface and it is put into molten solder
> > the tin will
> > be dissolved into the molten solder. I presume when the piece of iron
> is
> > withdrawn from the pot, solder will be well adhered to the iron. Is
> this
> > because there is a solderable tin/iron intermetallic? What is the main
> > difference between the tin can process and putting solder directly on
> iron
> > that makes one easy to do and the other difficult? This may be a "first
> > grade" met question, but I don't know the answer. Thanks.
> >
> > Bev Christian
> >
> > ------------------------------------------------------------------
> > ----------
> > -----
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
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> >
> > E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> > additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
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> > -----
> >
> > ------------------------------------------------------------------
> > ----------
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Date: Tue, 23 Oct 2001 09:08:03 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Soldering iron tips (UK: bits) are usually of made hardened copper. Copper
dissolves fairly rapidly in solder so modern tips are electroplated with
iron. Iron dissolves much more slowly in solder than copper but is harder to
wet. Thus the manufacturer will "tin" the tips with a very strong flux. In
use it is important not to remove the solder from this wetted area by over
wiping or whatever as it will be very difficult to re-tin with the low
activity assembly fluxes used in electronics. Some tip manufacturers plate
the non working areas of the tip with nickel to control the size of the
wetted area and help prevent the back end of the tip from sticking in the
soldering iron itself.
The canning industry only has to tin the steel once and doesn't keep it at
high temperatures thereafter. Similarly they can use any type of chemical
and any type of cleaning process they like - they don't have to worry about
SIR and stuff.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Monday, October 22, 2001 7:34 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
OK, let me try saying this a different way:
it "seems" that the canning industry has an easy time putting tin on can
steel. Why do I have trouble getting solder to stick to a properly
preheated 100% iron surface? Is it just a matter of flux strength? Or
something else?
Bev Christian
Research in Motion
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: October 22, 2001 4:17 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Dr Bev,
Not sure what your question is but for discussion. Many of the common
component lead frames contain significant amounts of iron which is plated to
enhance solderability, limit corrosion, etc.. Seems that there should be
some metallurgists out there that can lead us to understanding the
solubility characteristics but my text books discuss FeSn intermetalics
although the rate is slower that that of tin gold or tin copper. Also seems
to me that the Nickel content is important to the solder interface.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
Sent: Friday, October 19, 2001 2:01 PM
To: [log in to unmask]
Subject: [TN] tin on iron and solder on iron
OK, here is a general question for all you met guys. But I am not sure I
can explain it well enough to be understood!
We all know that tin can be put on iron or we wouldn't have "tin" cans. I
also know it is difficult to put solder on iron. So my question is this: if
one has a tinned iron surface and it is put into molten solder the tin will
be dissolved into the molten solder. I presume when the piece of iron is
withdrawn from the pot, solder will be well adhered to the iron. Is this
because there is a solderable tin/iron intermetallic? What is the main
difference between the tin can process and putting solder directly on iron
that makes one easy to do and the other difficult? This may be a "first
grade" met question, but I don't know the answer. Thanks.
Bev Christian
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Date: Tue, 23 Oct 2001 09:10:43 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Swanson <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Just to so we break out of this "locktight" fest, another good source is
http://www.thermoset.com.
Peter
--
=========================================================
Peter Swanson [log in to unmask]
INTERTRONICS http://www.intertronics.co.uk
INTERTRONICS is dedicated to providing quality material,
consumable and equipment solutions to the electronics
manufacturing and other technology based industries, with
the highest levels of technical support and customer
service.
-----Original Message-----
From: Mario Hernandez [mailto:[log in to unmask]]
Sent: 22 October 2001 21:00
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Gens,
All depend on which is your cure conditions (room temperature, oven, 1 o 2
components), process requirements, etc.?
Louis, you can contact to Chris Marinelli or Ed Fisher in the US at
1-800-LOCTITE (562 8483) if you are interested for more details about those
products,
Mario Hernandez
Jerry Mosur
<jmosur@SPELL Para: [log in to unmask]
MANHV.COM> cc:
Enviado por: Asunto: Re: [TN] Thermally
TechNet Conducting Adhesive
<[log in to unmask]
ORG>
22/10/01
02:48 p.m.
Por favor,
responda a
"TechNet
E-Mail
Forum."
Sorry if I offended anyone.
What I meant was, of course, LOCTITE Corp. and their web site:
www.loctite.com .
Again, please accept my apologies.
-----Original Message-----
From: Steve Kelly [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 3:07 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Tue, 23 Oct 2001 08:50:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Trimming Leads...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I can't resist Guy, with the all due respect, you struck a nerve and I could
provide a long dissertation but I will only hit the highlights. For a true
understanding of 610, read the scope and purpose, which are pretty much self
explanatory.
We all know what happens when you "asssume".
Therefore, one should require conformance to the full gambit of specs/stds
covering design, fabrication, documentation, assembly, acceptability and
rework/repair dependent on product class. Conformance to these documents
does not guarantee an acceptable product nor does it "qualify" a product.
These documents minimize the risk of attaining an acceptable, reliable,
fieldable product. ("...it sure looked good, I got the C of C and all the
other paperwork, but I don't understand how it smoked after I turned it
on...")
To "qualify" the product is another subject unrelated to this topic. But,
it all depends on how much the user is willing to pay and how well the user
defines the product requirements.
I believe you would be hard pressed in the real world to have class 1
product and some class 2 product manufacturers buy into your logic. These
mfr's rely on the end product acceptability (does it look good enough)
requirements of 610 and use best manufacturing practices to achieve that
end.
-----Original Message-----
I respectfully disagree. The IPC-A-610C is a support document. It assumes a
great deal about the assembly. It is a workmanship / inspection standard
designed to qualify end items manufactured using J-STD-001C compliant
materials and processes.
Blindly using the A-610 as an acceptance standard is very dangerous.
Consider the 75% vertical fill requirement. This is acceptable because we
assume that the bare board passed J-STD-003 requirements and IPC-6012A
performance requirements. If the board has poor plating you would pass
garbage on to your customer.
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Date: Tue, 23 Oct 2001 07:59:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Eric! Just a word of clarification - yes it is true that you do not need
to make an intermetallic to create a reliable joint provided the two
elements you are working with form a solid solution couple. However, the
action of creating a solder joint is not the joining of tin and lead but
the joining of a tin/lead alloy with copper - the formation of a copper/tin
intermetallic is critical for a reliable solder connection. Hanson's book
is a great reference - you may also want to take a look at the new edition
of the American Welding Society (AWS) handbook (3rd edition) for inclusion
in your library (ISBN 0-87171-618-6). Dr. Paul Vianco and the AWS committee
did an wonderful job of updating the handbook with new material (lots of
phase diagrams, references, etc.).
Dave Hillman
Rockwell Collins
[log in to unmask]
Eric Dawson <[log in to unmask]>@ipc.org> on 10/23/2001 02:14:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] tin on iron and solder on iron
Guy,
I'm now curious. Why little old ladies? what were they making with these
wired nails? and why were you watching them?
I hope I don't regret asking these questions, we know what happened to the
curious cat!
On a more serious note, and to address the original question,
intermetallics
will form between two metals when that is the stable reaction. See Hanson's
'Constitution of Binary Alloys.' This is a very good standard reference
work, though probably out of print by now. It is known that the Romans
soldered lead piping for their plumbing systems (plumbum-lead) and this
would not have formed any intermetallic even though good joints were made.
In this case the tin and lead form a solid solution which is the stable
product of the two metals involved. Therefore, it is not strictly correct
to
say that an intermetallic is a requirement for a good soldered joint,
rather, that the intermetallic is a product of a good soldered joint
between
copper and tin or iron and tin.
The flux is there to remove oxides and allow the solder and the base metal
to come into intimate contact and to aid heat transfer.
Regards
Eric Dawson
> -----Original Message-----
> From: Guy Ramsey [SMTP:[log in to unmask]]
> Sent: Monday, October 22, 2001 7:51 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
> It must be flux strength. I have watched little old ladies solder wires
to
> nails. They were using zinc chloride. Destroyed the solder iron tips but
> did
> what they wanted.
>
> We also made some custom tips for Pace solder pens. They were stainless,
> we
> solder plated them too. They did not last as long nor work as good as the
> store bought ones but they were less expensive. We did not measure the
tip
> temperature offset . . . oh yeah you were only asking about soldering
iron
> .
> . . ramble on.
>
>
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > Sent: Monday, October 22, 2001 2:34 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> >
> > OK, let me try saying this a different way:
> > it "seems" that the canning industry has an easy time putting tin on
can
> > steel. Why do I have trouble getting solder to stick to a properly
> > preheated 100% iron surface? Is it just a matter of flux strength? Or
> > something else?
> >
> > Bev Christian
> > Research in Motion
> >
> > -----Original Message-----
> > From: Mel Parrish [mailto:[log in to unmask]]
> > Sent: October 22, 2001 4:17 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> >
> > Dr Bev,
> > Not sure what your question is but for discussion. Many of the common
> > component lead frames contain significant amounts of iron which
> > is plated to
> > enhance solderability, limit corrosion, etc.. Seems that there should
> be
> > some metallurgists out there that can lead us to understanding the
> > solubility characteristics but my text books discuss FeSn intermetalics
> > although the rate is slower that that of tin gold or tin copper.
> > Also seems
> > to me that the Nickel content is important to the solder interface.
> >
> > Mel Parrish
> > Soldering Technology International
> > 102 Tribble Drive
> > Madison, AL 35758
> > 256 705 5530
> > 256 705 5538 Fax
> > [log in to unmask]
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > Sent: Friday, October 19, 2001 2:01 PM
> > To: [log in to unmask]
> > Subject: [TN] tin on iron and solder on iron
> >
> >
> > OK, here is a general question for all you met guys. But I am not sure
> I
> > can explain it well enough to be understood!
> >
> > We all know that tin can be put on iron or we wouldn't have "tin" cans.
> I
> > also know it is difficult to put solder on iron. So my question
> > is this: if
> > one has a tinned iron surface and it is put into molten solder
> > the tin will
> > be dissolved into the molten solder. I presume when the piece of iron
> is
> > withdrawn from the pot, solder will be well adhered to the iron. Is
> this
> > because there is a solderable tin/iron intermetallic? What is the main
> > difference between the tin can process and putting solder directly on
> iron
> > that makes one easy to do and the other difficult? This may be a
"first
> > grade" met question, but I don't know the answer. Thanks.
> >
> > Bev Christian
> >
> > ------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 08:59:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: 0.8mm pitch BGA socket
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C15BC2.83FC2F10"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------_=_NextPart_001_01C15BC2.83FC2F10
Content-Type: text/plain;
charset="iso-8859-1"
Hi Jiang,
Advanced Interconnect has .8mm BGA sockets in their catalog. They might be
able to give you the names of companies that are using them. I am using
(169) .8 mm BGA's but have not socketed them...... yet.
K
-----Original Message-----
From: Jiang Ping [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 10:01 PM
To: [log in to unmask]
Subject: [TN] 0.8mm pitch BGA socket
Hello Technetters,
Does anyone has experience using 0.8mm BGA socket that can be easily
soldered on board and give a reliable contact? We have a unsuccessful try
and are looking for recommendations.
Thanks in advance.
Jiang Ping
------_=_NextPart_001_01C15BC2.83FC2F10
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.2314.1000" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=680535912-23102001>Hi
Jiang,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=680535912-23102001>Advanced Interconnect has .8mm BGA sockets in their
catalog. They might be able to give you the names of companies that are
using them. I am using (169) .8 mm BGA's but have not socketed them......
yet.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=680535912-23102001>K</SPAN></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Jiang Ping
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, October 22, 2001 10:01
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] 0.8mm pitch BGA
socket<BR><BR></DIV></FONT>
<DIV><FONT size=2>Hello Technetters,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2>Does anyone has experience using 0.8mm BGA socket that can
be easily soldered on board and give a reliable contact? We have a
unsuccessful try and are looking for recommendations.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2>Thanks in advance.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=2>Jiang Ping</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C15BC2.83FC2F10--
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Date: Tue, 23 Oct 2001 09:31:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: exposing intermetallic on BGA pads...
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hello all,
During the process of replacing PBGA devices, we use solder wick to
remove excess solder from the board pads before stencil printing (with a
mini-stencil) solder paste and then using our Air-Vac system to place and
reflow the BGA. My question... what risk do we have in exposing the
intermetallic layer while we are cleaning off excess solder from the board
pads with solder wick? Every once in awhile, we see a solder joint that
just seems not to wet to the board pad... it's as if the solder paste that
was printed on that pad "jumped" up to increase the size of the BGA solder
ball and just didn't wet to the board pad. So now that larger looking ball
is simply resting on the pad. I am using a small mirror ( .250 inch
square) mounted on a dental pick (for a handle) and a stereo microscope...
to inspect the outer row of BGA balls.
Thanks, Bill
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Date: Tue, 23 Oct 2001 15:38:36 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Waleed Abdel-Hameed <[log in to unmask]>
Subject: modeling
MIME-Version: 1.0
Content-Type: text/plain
Dear:
Does anyone know anything about modeling ( solder joint
,traces,leads,..).
thanks
waleed
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Date: Tue, 23 Oct 2001 08:49:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: ASTM B867
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Steve! Hey, I just took a look at the ASTM B678 specification and it is
a mirror of the ANSIJ-STD-002A specification (except it is out of date in
terms of revisions). I would recommend using the 002A specification in
preference to the B678 specification.
Dave Hillman
Rockwell Collins
[log in to unmask]
"Stephen R. Gregory" <[log in to unmask]>@ipc.org> on 10/17/2001 10:12:46 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] ASTM B867
Hi Al,
What I found is that it's a go, no-go solderabilty test. Here's a summary
of the test:
Test Method B678-86(1993) Standard Test Method for Test Method for
Solderability of Metallic-Coated Products
AMERICAN SOCIETY FOR TESTING AND MATERIALS, West Conshohocken, PA. All
rights reserved.
1. Scope
1.1 This test method provides a procedure for evaluating the solderability
of metallic-coated products and test specimens to assure satisfactory
performance in manufacturing processes requiring soldering with soft
(tin-lead) solder and rosin flux. This test method is applicable only for
testing coatings that are normally readily solderable such as: tin,
tin-lead alloy, silver, and gold.
1.2 This test method is qualitative and broadly applicable. It is easy to
perform and requires only simple equipment. There are other solderability
tests not covered by this test method that are more applicable to specific
situations, yield quantitative results, or both. Several are described in
the literature. This is a "go-no-go" test and does not grade solderability
as excellent, good, fair, etc.
1.3 This standard may involve hazardous materials, operations, and
equipment. This standard does not purport to address all of the safety
problems associated with its use. It is the responsibility of whoever uses
this standard to consult and establish appropriate safety and health
practices and determine the applicability of regulatory limitations prior
to use.
You can get this standard at:
http://enterprise.astm.org/PAGES/B678.htm
It's only 3-pages long, but they charge $25.00 for it...
-Steve Gregory-
Hello Technetters,
I don't have an ASTM spec book available, but I have a print that calls out
ASTM B678, Type 2, Class 2.0, Grade 0.
What is it?
Thanks in advance,
Al
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Date: Tue, 23 Oct 2001 09:49:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Brewer <[log in to unmask]>
Subject: loc(k)tite
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
so THAT'S where Rob Halford went!
:-)
>From: Steve Kelly [mailto:[log in to unmask]]
>Sent: Monday, October 22, 2001 3:07 PM
>To: [log in to unmask]
>Subject: Re: [TN] Thermally Conducting Adhesive
>I think you should be more careful with your spelling - I do not think
>loctite would be amused where you are snding people.
>Steve Kelly
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Date: Tue, 23 Oct 2001 09:51:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Louis, Edwin @ CSE" <[log in to unmask]>
Subject: Re: Thermally Conducting Adhesive
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
What are you using to adhere 1 sq.in. flat packs to PWAs for temperature
excursions of -55-+71 Deg.C?
-----Original Message-----
From: Mario Hernandez [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 4:00 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Gens,
All depend on which is your cure conditions (room temperature, oven, 1 o 2
components), process requirements, etc.?
Louis, you can contact to Chris Marinelli or Ed Fisher in the US at
1-800-LOCTITE (562 8483) if you are interested for more details about those
products,
Mario Hernandez
Jerry Mosur
<jmosur@SPELL Para: [log in to unmask]
MANHV.COM> cc:
Enviado por: Asunto: Re: [TN] Thermally
TechNet Conducting Adhesive
<[log in to unmask]
ORG>
22/10/01
02:48 p.m.
Por favor,
responda a
"TechNet
E-Mail
Forum."
Sorry if I offended anyone.
What I meant was, of course, LOCTITE Corp. and their web site:
www.loctite.com .
Again, please accept my apologies.
-----Original Message-----
From: Steve Kelly [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 3:07 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
I think you should be more careful with your spelling - I do not think
loctite would be amused where you are snding people.
Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jerry Mosur
Sent: Monday, October 22, 2001 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Thermally Conducting Adhesive
Visit Locktite web site. They have a few to choose from.
www.locktite.com
-----Original Message-----
From: Louis, Edwin @ CSE [mailto:[log in to unmask]]
Sent: Monday, October 22, 2001 1:48 PM
To: [log in to unmask]
Subject: [TN] Thermally Conducting Adhesive
What is a good thermally conducting adhesive for placement unter a metal
quad flat pack device?
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Date: Tue, 23 Oct 2001 15:35:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Dave,
Semantics, I realise, but my dictionary does not confine itself to our
industry, so joining a lead pipe to another with tin or a tin lead alloy is
soldering, but not as we know it.
I attended a soldering and brazing conference dinner some years ago when the
outgoing president of the Institute of Metals (as was) started his speech by
noting that the Romans were known to have been soldering over 2,000 years
ago. He then leant forward, for emphasis, and said "Gentlemen, why haven't
you got it right yet?"
Well, we can only keep trying.
Regards
Eric Dawson
> -----Original Message-----
> From: David Hillman [SMTP:[log in to unmask]]
> Sent: Tuesday, October 23, 2001 1:59 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
> Hi Eric! Just a word of clarification - yes it is true that you do not
> need
> to make an intermetallic to create a reliable joint provided the two
> elements you are working with form a solid solution couple. However, the
> action of creating a solder joint is not the joining of tin and lead but
> the joining of a tin/lead alloy with copper - the formation of a
> copper/tin
> intermetallic is critical for a reliable solder connection. Hanson's book
> is a great reference - you may also want to take a look at the new edition
> of the American Welding Society (AWS) handbook (3rd edition) for
> inclusion
> in your library (ISBN 0-87171-618-6). Dr. Paul Vianco and the AWS
> committee
> did an wonderful job of updating the handbook with new material (lots of
> phase diagrams, references, etc.).
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 10/23/2001 02:14:04 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: Re: [TN] tin on iron and solder on iron
>
>
> Guy,
> I'm now curious. Why little old ladies? what were they making with these
> wired nails? and why were you watching them?
> I hope I don't regret asking these questions, we know what happened to the
> curious cat!
> On a more serious note, and to address the original question,
> intermetallics
> will form between two metals when that is the stable reaction. See
> Hanson's
> 'Constitution of Binary Alloys.' This is a very good standard reference
> work, though probably out of print by now. It is known that the Romans
> soldered lead piping for their plumbing systems (plumbum-lead) and this
> would not have formed any intermetallic even though good joints were made.
> In this case the tin and lead form a solid solution which is the stable
> product of the two metals involved. Therefore, it is not strictly correct
> to
> say that an intermetallic is a requirement for a good soldered joint,
> rather, that the intermetallic is a product of a good soldered joint
> between
> copper and tin or iron and tin.
> The flux is there to remove oxides and allow the solder and the base metal
> to come into intimate contact and to aid heat transfer.
> Regards
> Eric Dawson
>
> > -----Original Message-----
> > From: Guy Ramsey [SMTP:[log in to unmask]]
> > Sent: Monday, October 22, 2001 7:51 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> > It must be flux strength. I have watched little old ladies solder wires
> to
> > nails. They were using zinc chloride. Destroyed the solder iron tips but
> > did
> > what they wanted.
> >
> > We also made some custom tips for Pace solder pens. They were stainless,
> > we
> > solder plated them too. They did not last as long nor work as good as
> the
> > store bought ones but they were less expensive. We did not measure the
> tip
> > temperature offset . . . oh yeah you were only asking about soldering
> iron
> > .
> > . . ramble on.
> >
> >
> >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > > Sent: Monday, October 22, 2001 2:34 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, let me try saying this a different way:
> > > it "seems" that the canning industry has an easy time putting tin on
> can
> > > steel. Why do I have trouble getting solder to stick to a properly
> > > preheated 100% iron surface? Is it just a matter of flux strength?
> Or
> > > something else?
> > >
> > > Bev Christian
> > > Research in Motion
> > >
> > > -----Original Message-----
> > > From: Mel Parrish [mailto:[log in to unmask]]
> > > Sent: October 22, 2001 4:17 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > Dr Bev,
> > > Not sure what your question is but for discussion. Many of the common
> > > component lead frames contain significant amounts of iron which
> > > is plated to
> > > enhance solderability, limit corrosion, etc.. Seems that there should
> > be
> > > some metallurgists out there that can lead us to understanding the
> > > solubility characteristics but my text books discuss FeSn
> intermetalics
> > > although the rate is slower that that of tin gold or tin copper.
> > > Also seems
> > > to me that the Nickel content is important to the solder interface.
> > >
> > > Mel Parrish
> > > Soldering Technology International
> > > 102 Tribble Drive
> > > Madison, AL 35758
> > > 256 705 5530
> > > 256 705 5538 Fax
> > > [log in to unmask]
> > >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > > Sent: Friday, October 19, 2001 2:01 PM
> > > To: [log in to unmask]
> > > Subject: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, here is a general question for all you met guys. But I am not
> sure
> > I
> > > can explain it well enough to be understood!
> > >
> > > We all know that tin can be put on iron or we wouldn't have "tin"
> cans.
> > I
> > > also know it is difficult to put solder on iron. So my question
> > > is this: if
> > > one has a tinned iron surface and it is put into molten solder
> > > the tin will
> > > be dissolved into the molten solder. I presume when the piece of iron
> > is
> > > withdrawn from the pot, solder will be well adhered to the iron. Is
> > this
> > > because there is a solderable tin/iron intermetallic? What is the
> main
> > > difference between the tin can process and putting solder directly on
> > iron
> > > that makes one easy to do and the other difficult? This may be a
> "first
> > > grade" met question, but I don't know the answer. Thanks.
> > >
> > > Bev Christian
> > >
> > > ------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 10:48:47 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: modeling
MIME-Version: 1.0
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boundary="part1_4d.132eb003.2906dd4f_boundary"
--part1_4d.132eb003.2906dd4f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Waleed!
Go to:
http://www.ctcms.nist.gov/programs/solder/
There you'll find a program called "Surface Evolver" that you can use to
model various solder joints...plus there's also a few other good links from
that page.
-Steve Gregory-
> Dear:
> Does anyone know anything about modeling ( solder joint
> ,traces,leads,..).
>
> thanks
> waleed
>
--part1_4d.132eb003.2906dd4f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Waleed!
<BR>
<BR>Go to:
<BR>
<BR>http://www.ctcms.nist.gov/programs/solder/
<BR>
<BR>There you'll find a program called "Surface Evolver" that you can use to model various solder joints...plus there's also a few other good links from that page.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Dear:
<BR> Does anyone know anything about modeling ( solder joint
<BR>,traces,leads,..).
<BR>
<BR> thanks
<BR> waleed
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Tue, 23 Oct 2001 09:50:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
Thanks Guenter for an offline reply. Don't mean to drag you into this
never ending fray on line. Not trying to alienate Guenter or anyone else as
a soldering expert. Simply continuing on the theme: "Haven't you got it
right yet?" comment/statement/quote - after 2,000 years of metal joining as
soldering - not brazing or welding.
Guenter's following comments and factual analysis - together with some
relatively basic and simple physical formulae says much as did Dave, Werner,
and so many other's examples.
Hi Earl
Well well. Stubborn or not you are one of these guys I like most as students
cause they keep me working in asking on and on and on.
Let me try to explain wetting in the way I understand it. Maybe it's kind
too simplified, for mor profound explanations you might have to look into a
textbook (also good ol' Klein Wassink has a lot in it), maybe it's too long.
I don't know.
First of all wetting has nothing to do with intermetallics.
Wetting describes the spreading of one substance on another.
Formation of intermetallics is an alloying process.
Diffusion is the travelling of one substance trough another one.
Wetting:
As you see a drop of a liquid on a substrate you see that it reaches above
the level of the substrate. This height varies, depending on the combination
of liquid and substrate. To do so there must be a difference of pressure
between the inside and the outside of the drop very much like one of these
soft rubber balls kids use in the swimming pool. the more air you blow into
the ball the rounder it will lay on the surface of a table. Laplace thought
about this problem and introduced a measure called surface tension.
dP = g (1/R1 + 1/R2)
dP= Pressure difference
g = surface tension
R1; R2 = radii of curvature
In my opinion this is not a good name since I always feel that surface
tension is something with force per area. However, surface tension is not
this it is a measure for the state of energy per area the surface atoms are
in. But who am I to correct Laplace?
Where does this surface tension come from? Each atom has a certain total
internal energy. In the bulk, each atom is surrounded by other atoms mostly
of its own kind and is somehow bound to these neighbours. Now imagine the
atoms on a surface in vacuum. Those fellows have only neighbours below and
on the side. Thus some bindings are missing which brings these atoms to
another ( higher) potential energy than those in the bulk. Enlarging the
surface means enlarging the potential energy since more atoms are becoming
part of the surface.
If the substance we look at is not in a vacuum the atoms at the surface have
bonds to the atoms of the surrounding medium. This means the surface
tension at the interface of the two is a function of the combination of the
two substances.
Looking at a drop of liquid on a surface one sees several interfaces:
- Liquid- environment
- Liquid. substrate
- Substrate- environment
Each having its own interfacial energy. The total surface energy of this
system is:
E= g1x (area of free substrate surface) + g2x (area of drop surface) + g3x
(area of drop-substrate interface)
g1= surface tension substrate / environment
g2= Surface tension liquid / environment
g3= surface tension Liquid / substrate
Since every system wants to minimise its free energy all three interfaces
define the shape of the droplet with their interfacial energy. Assuming that
the drop has the shape of a spherical cap this shape can be defined with the
angle the surface of the drop forms at the point where it meets the surface
of the substrate. This wetting angle can be calculated after Young ( Yes,
the Young, seems as if them clever fellows before us did a whole lot of
things):
g3 +g2 x cos a = g1 or cos a = (g1- g3)/ g2
g1= surface tension substrate / environment
g2= Surface tension liquid / environment
g3= surface tension Liquid / substrate
cos a = cosinus of wetting angle
This means, the smaller g3 and g2 the smaller the wetting angle.
Formation of Intermetallics
The same bonds between two substances that determine the wetting angle are
also responsible for the alloying behaviour or the solubility of two
substances in each other. The better two substances are soluble in each
other the smaller is the interfacial tension between them. Generally, if two
liquid metals A and B are mixed together, one lets say A, will be solved in
the other ( B ) until saturation occurs. Again this is an energy minimum
of the system called the eutectic alloy. If the liquid metal mixture
solidifies A and B form mixtures of mixed crystals composed of A and B with
the maximum amount of A in B and the surplus B as pure B. Some metals
however do form substances that haven't got pure metallic bonds. They have
something called intermediate bonds that incorporate metallic bonds as well
as covalent bonds and ion bonds. In this manner chemical compounds are
created having complex stoechiometric composition and are called
intermetallics.
Diffusion
As diffusion one assigns the movement of atoms through some environment. In
context we are looking at this is the movement of atoms of copper atoms
through the intermetallics to the tin and movement of tin atoms to the
copper. How many atoms per area and time pass through a layer depends on
- Temperature
- Difference of concentration of copper in tin or tin in copper respectively
- Substance diffusing
- Substance of the layer
- Thickness of the layer
This is described with the 1st. law of Fick extended with a bit of
Arrhenius:
dm / dt= - D ( dc/dx ) S x e exp ( - Q / R T)
m = Amount of diffusing substance
t = Time
D = Diffusion coefficient ( Material constant )
c = Concentration
x = Diffusion way
S = Area through which the diffusion takes place
Q = Activation energy
R = Gas constant ( 8.32 J / mole K )
T = Temperature in K
All in all you might see that in soldering
1st : Wetting takes place
2nd : Solder alloys with copper ( or nickel, depending on the surface
finish)
3rd : Intermetallics are formed
4th : By diffusion of tin into copper and copper into tin through the
intermetallic layers the intermetallics keep growing
Phew I'm getting a stiff neck of writing. Sorry it got so long and sorry I
didn't get more into depth but then I would get even longer.
Have a great day
Guenter
Again, thanks to Guenter and many others, I have added to my limited
understanding of factual elements regarding soldering. In school, I always
had a hard time with LaPlace transforms as intended for use developing
electronic circuits. Went to mechanical engineering instead but he kept
showing up.
On the surface, all this wetting is simple stuff. It's the surface, and its
definition and its characteristics, I question. Still not trying to stir the
pot anymore, but trying to get this thing is perspective so - cant' we all
just get along while understanding Rodney is stuck in his ways, in jail
again, and I'm not stuck anywhere but trying after my 2,000 years, it seems,
on earth still trying understand the question - can't we all just get it
right - or at least - make it easier.
MoonMan
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Date: Tue, 23 Oct 2001 15:58:54 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Just to continue this diversion for historical completeness: there are
paintings on Egyptian tombs showing soldering of jewellery in some sort of
production line (at least the workers are sitting in rows) which go back
3,500 years.
Having said "completeness" I now half expect someone else to remind us
something about the South Americans or Chinese......
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Dawson
Sent: Tuesday, October 23, 2001 3:36 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Hi Dave,
Semantics, I realise, but my dictionary does not confine itself to our
industry, so joining a lead pipe to another with tin or a tin lead alloy is
soldering, but not as we know it.
I attended a soldering and brazing conference dinner some years ago when the
outgoing president of the Institute of Metals (as was) started his speech by
noting that the Romans were known to have been soldering over 2,000 years
ago. He then leant forward, for emphasis, and said "Gentlemen, why haven't
you got it right yet?"
Well, we can only keep trying.
Regards
Eric Dawson
> -----Original Message-----
> From: David Hillman [SMTP:[log in to unmask]]
> Sent: Tuesday, October 23, 2001 1:59 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
> Hi Eric! Just a word of clarification - yes it is true that you do not
> need
> to make an intermetallic to create a reliable joint provided the two
> elements you are working with form a solid solution couple. However, the
> action of creating a solder joint is not the joining of tin and lead but
> the joining of a tin/lead alloy with copper - the formation of a
> copper/tin
> intermetallic is critical for a reliable solder connection. Hanson's book
> is a great reference - you may also want to take a look at the new edition
> of the American Welding Society (AWS) handbook (3rd edition) for
> inclusion
> in your library (ISBN 0-87171-618-6). Dr. Paul Vianco and the AWS
> committee
> did an wonderful job of updating the handbook with new material (lots of
> phase diagrams, references, etc.).
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 10/23/2001 02:14:04 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: Re: [TN] tin on iron and solder on iron
>
>
> Guy,
> I'm now curious. Why little old ladies? what were they making with these
> wired nails? and why were you watching them?
> I hope I don't regret asking these questions, we know what happened to the
> curious cat!
> On a more serious note, and to address the original question,
> intermetallics
> will form between two metals when that is the stable reaction. See
> Hanson's
> 'Constitution of Binary Alloys.' This is a very good standard reference
> work, though probably out of print by now. It is known that the Romans
> soldered lead piping for their plumbing systems (plumbum-lead) and this
> would not have formed any intermetallic even though good joints were made.
> In this case the tin and lead form a solid solution which is the stable
> product of the two metals involved. Therefore, it is not strictly correct
> to
> say that an intermetallic is a requirement for a good soldered joint,
> rather, that the intermetallic is a product of a good soldered joint
> between
> copper and tin or iron and tin.
> The flux is there to remove oxides and allow the solder and the base metal
> to come into intimate contact and to aid heat transfer.
> Regards
> Eric Dawson
>
> > -----Original Message-----
> > From: Guy Ramsey [SMTP:[log in to unmask]]
> > Sent: Monday, October 22, 2001 7:51 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> > It must be flux strength. I have watched little old ladies solder wires
> to
> > nails. They were using zinc chloride. Destroyed the solder iron tips but
> > did
> > what they wanted.
> >
> > We also made some custom tips for Pace solder pens. They were stainless,
> > we
> > solder plated them too. They did not last as long nor work as good as
> the
> > store bought ones but they were less expensive. We did not measure the
> tip
> > temperature offset . . . oh yeah you were only asking about soldering
> iron
> > .
> > . . ramble on.
> >
> >
> >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > > Sent: Monday, October 22, 2001 2:34 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, let me try saying this a different way:
> > > it "seems" that the canning industry has an easy time putting tin on
> can
> > > steel. Why do I have trouble getting solder to stick to a properly
> > > preheated 100% iron surface? Is it just a matter of flux strength?
> Or
> > > something else?
> > >
> > > Bev Christian
> > > Research in Motion
> > >
> > > -----Original Message-----
> > > From: Mel Parrish [mailto:[log in to unmask]]
> > > Sent: October 22, 2001 4:17 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > Dr Bev,
> > > Not sure what your question is but for discussion. Many of the common
> > > component lead frames contain significant amounts of iron which
> > > is plated to
> > > enhance solderability, limit corrosion, etc.. Seems that there should
> > be
> > > some metallurgists out there that can lead us to understanding the
> > > solubility characteristics but my text books discuss FeSn
> intermetalics
> > > although the rate is slower that that of tin gold or tin copper.
> > > Also seems
> > > to me that the Nickel content is important to the solder interface.
> > >
> > > Mel Parrish
> > > Soldering Technology International
> > > 102 Tribble Drive
> > > Madison, AL 35758
> > > 256 705 5530
> > > 256 705 5538 Fax
> > > [log in to unmask]
> > >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> > > Sent: Friday, October 19, 2001 2:01 PM
> > > To: [log in to unmask]
> > > Subject: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, here is a general question for all you met guys. But I am not
> sure
> > I
> > > can explain it well enough to be understood!
> > >
> > > We all know that tin can be put on iron or we wouldn't have "tin"
> cans.
> > I
> > > also know it is difficult to put solder on iron. So my question
> > > is this: if
> > > one has a tinned iron surface and it is put into molten solder
> > > the tin will
> > > be dissolved into the molten solder. I presume when the piece of iron
> > is
> > > withdrawn from the pot, solder will be well adhered to the iron. Is
> > this
> > > because there is a solderable tin/iron intermetallic? What is the
> main
> > > difference between the tin can process and putting solder directly on
> > iron
> > > that makes one easy to do and the other difficult? This may be a
> "first
> > > grade" met question, but I don't know the answer. Thanks.
> > >
> > > Bev Christian
> > >
> > > ------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 08:26:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Land pattern for wave soldering
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi Technetters,
Is there a need to have different SMD land size/ pattern for wave soldering? Any
suggestion is appreciated.
Thanks,
Patrick
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Date: Tue, 23 Oct 2001 11:52:52 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Question regarding ENIG and solder mask
MIME-Version: 1.0
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For some reason I can't recollect (due to advancing age, dead brain cells,
etc.) whether ENIG plating is done before solder mask or after . I
remember something about the chemical baths attacking the solder mask, so
all electroless nickel and immersion gold plating would have to be done
first. Could someone check my memory for me please?
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
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Date: Tue, 23 Oct 2001 17:03:04 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: Land pattern for wave soldering
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Patrick,
If you look at say a side one footprint(reflow)for quad flat pack as opposed
to a side two (wavesolder)side. On side two you will ideally need to present
the component @ 45 deg to the wave and have solder thieves in each of the
four corners to eliminate solder bridges.
just an example.
hope its of some use.
-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: 23 October 2001 16:26
To: [log in to unmask]
Subject: [TN] Land pattern for wave soldering
Hi Technetters,
Is there a need to have different SMD land size/ pattern for wave soldering?
Any
suggestion is appreciated.
Thanks,
Patrick
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Date: Tue, 23 Oct 2001 12:13:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Acceleration (g) - Free Unit Conversion Software
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Hey Gang,
This is not an endorsement. But everybody knows that already.
I take the daring step to reopen the acceleration thread long enough to say:
Nelco's got a unit conversion calculator in their Designers Corner that
includes acceleration in g's.
http://www.parknelco.com
It takes a free username and password to get into the Designers Corner.
I now return you to your regularly scheduled e-mail.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
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Date: Tue, 23 Oct 2001 12:22:43 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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I thought I read somewhere that Adam soldered a button on his fig leaf so it
would not fall down. Sorry I can't recall the source.
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Mike Fenner [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 10:59 AM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Just to continue this diversion for historical completeness:
there are
paintings on Egyptian tombs showing soldering of jewellery
in some sort of
production line (at least the workers are sitting in rows)
which go back
3,500 years.
Having said "completeness" I now half expect someone else to
remind us
something about the South Americans or Chinese......
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric
Dawson
Sent: Tuesday, October 23, 2001 3:36 PM
To: [log in to unmask]
Subject: Re: [TN] tin on iron and solder on iron
Hi Dave,
Semantics, I realise, but my dictionary does not confine
itself to our
industry, so joining a lead pipe to another with tin or a
tin lead alloy is
soldering, but not as we know it.
I attended a soldering and brazing conference dinner some
years ago when the
outgoing president of the Institute of Metals (as was)
started his speech by
noting that the Romans were known to have been soldering
over 2,000 years
ago. He then leant forward, for emphasis, and said
"Gentlemen, why haven't
you got it right yet?"
Well, we can only keep trying.
Regards
Eric Dawson
> -----Original Message-----
> From: David Hillman [SMTP:[log in to unmask]]
> Sent: Tuesday, October 23, 2001 1:59 PM
> To: [log in to unmask]
> Subject: Re: [TN] tin on iron and solder on iron
>
> Hi Eric! Just a word of clarification - yes it is true
that you do not
> need
> to make an intermetallic to create a reliable joint
provided the two
> elements you are working with form a solid solution
couple. However, the
> action of creating a solder joint is not the joining of
tin and lead but
> the joining of a tin/lead alloy with copper - the
formation of a
> copper/tin
> intermetallic is critical for a reliable solder
connection. Hanson's book
> is a great reference - you may also want to take a look at
the new edition
> of the American Welding Society (AWS) handbook (3rd
edition) for
> inclusion
> in your library (ISBN 0-87171-618-6). Dr. Paul Vianco and
the AWS
> committee
> did an wonderful job of updating the handbook with new
material (lots of
> phase diagrams, references, etc.).
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
>
>
>
> Eric Dawson <[log in to unmask]>@ipc.org> on 10/23/2001
02:14:04 AM
>
> Please respond to "TechNet E-Mail Forum."
<[log in to unmask]>
>
> Sent by: TechNet <[log in to unmask]>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: Re: [TN] tin on iron and solder on iron
>
>
> Guy,
> I'm now curious. Why little old ladies? what were they
making with these
> wired nails? and why were you watching them?
> I hope I don't regret asking these questions, we know what
happened to the
> curious cat!
> On a more serious note, and to address the original
question,
> intermetallics
> will form between two metals when that is the stable
reaction. See
> Hanson's
> 'Constitution of Binary Alloys.' This is a very good
standard reference
> work, though probably out of print by now. It is known
that the Romans
> soldered lead piping for their plumbing systems
(plumbum-lead) and this
> would not have formed any intermetallic even though good
joints were made.
> In this case the tin and lead form a solid solution which
is the stable
> product of the two metals involved. Therefore, it is not
strictly correct
> to
> say that an intermetallic is a requirement for a good
soldered joint,
> rather, that the intermetallic is a product of a good
soldered joint
> between
> copper and tin or iron and tin.
> The flux is there to remove oxides and allow the solder
and the base metal
> to come into intimate contact and to aid heat transfer.
> Regards
> Eric Dawson
>
> > -----Original Message-----
> > From: Guy Ramsey [SMTP:[log in to unmask]]
> > Sent: Monday, October 22, 2001 7:51 PM
> > To: [log in to unmask]
> > Subject: Re: [TN] tin on iron and solder on iron
> >
> > It must be flux strength. I have watched little old
ladies solder wires
> to
> > nails. They were using zinc chloride. Destroyed the
solder iron tips but
> > did
> > what they wanted.
> >
> > We also made some custom tips for Pace solder pens. They
were stainless,
> > we
> > solder plated them too. They did not last as long nor
work as good as
> the
> > store bought ones but they were less expensive. We did
not measure the
> tip
> > temperature offset . . . oh yeah you were only asking
about soldering
> iron
> > .
> > . . ramble on.
> >
> >
> >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev
Christian
> > > Sent: Monday, October 22, 2001 2:34 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, let me try saying this a different way:
> > > it "seems" that the canning industry has an easy time
putting tin on
> can
> > > steel. Why do I have trouble getting solder to stick
to a properly
> > > preheated 100% iron surface? Is it just a matter of
flux strength?
> Or
> > > something else?
> > >
> > > Bev Christian
> > > Research in Motion
> > >
> > > -----Original Message-----
> > > From: Mel Parrish [mailto:[log in to unmask]]
> > > Sent: October 22, 2001 4:17 PM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] tin on iron and solder on iron
> > >
> > >
> > > Dr Bev,
> > > Not sure what your question is but for discussion.
Many of the common
> > > component lead frames contain significant amounts of
iron which
> > > is plated to
> > > enhance solderability, limit corrosion, etc.. Seems
that there should
> > be
> > > some metallurgists out there that can lead us to
understanding the
> > > solubility characteristics but my text books discuss
FeSn
> intermetalics
> > > although the rate is slower that that of tin gold or
tin copper.
> > > Also seems
> > > to me that the Nickel content is important to the
solder interface.
> > >
> > > Mel Parrish
> > > Soldering Technology International
> > > 102 Tribble Drive
> > > Madison, AL 35758
> > > 256 705 5530
> > > 256 705 5538 Fax
> > > [log in to unmask]
> > >
> > > -----Original Message-----
> > > From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev
Christian
> > > Sent: Friday, October 19, 2001 2:01 PM
> > > To: [log in to unmask]
> > > Subject: [TN] tin on iron and solder on iron
> > >
> > >
> > > OK, here is a general question for all you met guys.
But I am not
> sure
> > I
> > > can explain it well enough to be understood!
> > >
> > > We all know that tin can be put on iron or we wouldn't
have "tin"
> cans.
> > I
> > > also know it is difficult to put solder on iron. So
my question
> > > is this: if
> > > one has a tinned iron surface and it is put into
molten solder
> > > the tin will
> > > be dissolved into the molten solder. I presume when
the piece of iron
> > is
> > > withdrawn from the pot, solder will be well adhered to
the iron. Is
> > this
> > > because there is a solderable tin/iron intermetallic?
What is the
> main
> > > difference between the tin can process and putting
solder directly on
> > iron
> > > that makes one easy to do and the other difficult?
This may be a
> "first
> > > grade" met question, but I don't know the answer.
Thanks.
> > >
> > > Bev Christian
> > >
> > >
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Date: Tue, 23 Oct 2001 09:25:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Question regarding ENIG and solder mask
MIME-Version: 1.0
Content-Type: text/plain
Roger
The good news is you don't have to remember anymore. With the right
soldermask, you can do it before or after. We use a mask from Enthone that
is formulated to provide chemical resistance to the ENIG chemistries.
Here's a link to some more information on the issue.
http://www.enthone.com/electronics/pdf/IMUP10.pdf
> ----------
> From: Roger M. Stoops[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Tuesday, October 23, 2001 8:52 AM
> To: [log in to unmask]
> Subject: [TN] Question regarding ENIG and solder mask
>
> For some reason I can't recollect (due to advancing age, dead brain cells,
> etc.) whether ENIG plating is done before solder mask or after . I
> remember something about the chemical baths attacking the solder mask, so
> all electroless nickel and immersion gold plating would have to be done
> first. Could someone check my memory for me please?
>
> Roger M. Stoops, C.I.D., PCB Designer
> [log in to unmask]
>
>
> Trimble
> Engineering and Construction Division
> 5475 Kellenburger Rd.
> Dayton, OH 45424-1099 USA
> Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
> Fax: +01 937.233.7511
>
> --------------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 09:40:37 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Re: Land pattern for wave soldering
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi Steve,
Thanks for the prompt response.
What kind of solder thieves should I put in, say a SOIC08? Do I need to put in
leading pads and leading pads? Is there any standard published that I can find
or buy regarding wave soldering issues?
Thanks for the support.
Patrick
Steve Owen <[log in to unmask]> on 10/23/2001 09:03:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Patrick Lam/SEL)
Subject: Re: [TN] Land pattern for wave soldering
Hi Patrick,
If you look at say a side one footprint(reflow)for quad flat pack as opposed
to a side two (wavesolder)side. On side two you will ideally need to present
the component @ 45 deg to the wave and have solder thieves in each of the
four corners to eliminate solder bridges.
just an example.
hope its of some use.
-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: 23 October 2001 16:26
To: [log in to unmask]
Subject: [TN] Land pattern for wave soldering
Hi Technetters,
Is there a need to have different SMD land size/ pattern for wave soldering?
Any
suggestion is appreciated.
Thanks,
Patrick
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Date: Tue, 23 Oct 2001 09:41:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Re: Land pattern for wave soldering
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi Patrick,
If you look at say a side one footprint(reflow)for quad flat pack as opposed
to a side two (wavesolder)side. On side two you will ideally need to present
the component @ 45 deg to the wave and have solder thieves in each of the
four corners to eliminate solder bridges.
just an example.
hope its of some use.
-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: 23 October 2001 16:26
To: [log in to unmask]
Subject: [TN] Land pattern for wave soldering
Hi Technetters,
Is there a need to have different SMD land size/ pattern for wave soldering?
Any
suggestion is appreciated.
Thanks,
Patrick
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Date: Tue, 23 Oct 2001 11:35:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Question regarding ENIG and solder mask
Michael got that right. I only know this because he made me remember all I
forgot as well - brain cells or not. For sure - not many.
That Sedlak guy out in my old home town (Mt. View) has all the answers on
this as well. I bring this up because of his continuing excellent
dissertations concerning ENIG and other coating/plating stuff.
I know you can put it on before or after, with the right SM or other stuff.
Also, lot's of folks like to do the "flash" gold before SM application. This
brings up other questions, asked many times on this forum, concerning
exposed copper as a function of an electrolitic process, using gold as the
final etch resist, leaving copper exposed for obvious reasons.
I guess the answer to my obvious question has been thoroughly beat to death
with no clear evidence that exposed copper is an issue with which to be
concerned. Right? But, are there advantages to "flash" gold being
electroplated over nickel over copper vs ENIG. I've always been an
electroplated type guy. Rudy, where are you on this?
Earl Moon
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Date: Tue, 23 Oct 2001 11:33:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Fahey <[log in to unmask]>
Subject: Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side via
a solder pot system to reflow the solder, remove the component, and replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed zozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time usage
requirement.
As always, I appreciate your excellent advice.
Rgds,
John
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Date: Tue, 23 Oct 2001 11:48:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: tin on iron and solder on iron
Not offended though having gone way back over 5,000 years (sure was an
interesting relationship built on soldering technology and little else) with
a South American Chinese girl, I understand what's going on here, or not. I
know this is a poor attempt at humor but had to try in light of all the crap
going on in the world.
On a more serious note, I know we are managing soldering processes better
than ever - certainly more so than that long ago, let alone even 20 years.
It's just exciting, no more so than with my old girlfriend, seeing this
subject being debated by so many others so interested. Used to be only
interested in things like airplanes and going to the moon. Hell, I am
the MoonMan. Amazing what turns on some people.
MoonMan
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Date: Tue, 23 Oct 2001 16:10:25 +0100
Reply-To: Roger Bilham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Bilham <[log in to unmask]>
Subject: Re: modeling
In-Reply-To: <60E0961D827AD411A1ED00508B2C0595017DD5@IEPBDC>
MIME-Version: 1.0
Waleed,
In the UK, there are Rob Wallach at Cambridge University, Bill
Plumbridge at the Open University and David Whalley at Loughborough
University. In Ireland, the National Microelectronics Research Centre
(NMRC) has knowledge in this area.
Roger Bilham
In article <60E0961D827AD411A1ED00508B2C0595017DD5@IEPBDC>, Waleed
Abdel-Hameed <[log in to unmask]> writes
> Dear:
> Does anyone know anything about modeling ( solder joint
>,traces,leads,..).
>
> thanks
> waleed
>
>-------------------------------------------------------------------------------
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>-
>-
--
Roger Bilham
Roger Bilham Consultancy
Tel: +44 (0)20 8467 8819
Fax: +44 (0)8700 548 613
Mobile +44 (0)7 941 122 446
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Date: Tue, 23 Oct 2001 12:04:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Fahey <[log in to unmask]>
Subject: REPOST: Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side via
a solder pot system to reflow the solder, remove the component, and replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed Nozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time usage
requirement.
As always, I appreciate your excellent advice.
Rgds, John
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Date: Tue, 23 Oct 2001 13:48:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Through Hole Oscillator Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
John,
We have 4 Electrovert solder fountain systems, but suspect we would first
try using good old vacuum desoldering systems to remove the part, and
traditional soldering irons to replace it. The solder fountain systems may
be useful if the leads have heavy ground plane connections, but setup and
preparation for the solder fountain system may take longer that the
desolder/hand solder method.
You can see a little more about solder fountain rework on our website at:
http://www.circuittechctr.com/guides/8-1-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 12:33 PM
To: [log in to unmask]
Subject: [TN] Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side via
a solder pot system to reflow the solder, remove the component, and replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed zozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time usage
requirement.
As always, I appreciate your excellent advice.
Rgds,
John
----------------------------------------------------------------------------
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Date: Tue, 23 Oct 2001 14:18:38 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: BGA Rework - Cleaning board pads (REPOST)
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
This is a REPOST, it appears my 1st post attempt failed....
Hello all,
During the process of replacing PBGA devices, we use solder wick to
remove excess solder from the board pads before stencil printing (with a
mini-stencil) solder paste and then using our Air-Vac system to place and
reflow the BGA. My question... what risk do we have in exposing the
intermetallic layer while we are cleaning off excess solder from the board
pads with solder wick? Every once in awhile, we see a solder joint that
just seems not to wet to the board pad... it's as if the solder paste that
was printed on that pad "jumped" up to increase the size of the BGA solder
ball and just didn't wet to the board pad. So now that larger looking ball
is simply resting on the pad. I am using a small mirror ( .250 inch
square) mounted on a dental pick (for a handle) and a stereo microscope...
to inspect the outer row of BGA balls.
Thanks, Bill
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Date: Tue, 23 Oct 2001 11:24:56 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Fahey <[log in to unmask]>
Subject: Re: Through Hole Oscillator Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jerry
Thanks for the info. As you mentioned, the leads DO indeed have a heavy
ground plane connection that prevents us being able to use the traditional
soldering irons.
Are there any other options other than the Solder Fountain system. Also,
does anyone know where we could lease/rent this system as these are approx
$9K new and this is only a one time use.
Thanks
John
-----Original Message-----
From: Jeff Ferry [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 10:49 AM
To: [log in to unmask]
Subject: Re: [TN] Through Hole Oscillator Removal
John,
We have 4 Electrovert solder fountain systems, but suspect we would first
try using good old vacuum desoldering systems to remove the part, and
traditional soldering irons to replace it. The solder fountain systems may
be useful if the leads have heavy ground plane connections, but setup and
preparation for the solder fountain system may take longer that the
desolder/hand solder method.
You can see a little more about solder fountain rework on our website at:
http://www.circuittechctr.com/guides/8-1-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 12:33 PM
To: [log in to unmask]
Subject: [TN] Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side via
a solder pot system to reflow the solder, remove the component, and replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed zozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time usage
requirement.
As always, I appreciate your excellent advice.
Rgds,
John
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Date: Tue, 23 Oct 2001 11:34:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Through Hole Oscillator Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
why don't you just contract this work out?
phil
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 11:25 AM
To: [log in to unmask]
Subject: Re: [TN] Through Hole Oscillator Removal
Jerry
Thanks for the info. As you mentioned, the leads DO indeed have a heavy
ground plane connection that prevents us being able to use the traditional
soldering irons.
Are there any other options other than the Solder Fountain system. Also,
does anyone know where we could lease/rent this system as these are approx
$9K new and this is only a one time use.
Thanks
John
-----Original Message-----
From: Jeff Ferry [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 10:49 AM
To: [log in to unmask]
Subject: Re: [TN] Through Hole Oscillator Removal
John,
We have 4 Electrovert solder fountain systems, but suspect we would first
try using good old vacuum desoldering systems to remove the part, and
traditional soldering irons to replace it. The solder fountain systems may
be useful if the leads have heavy ground plane connections, but setup and
preparation for the solder fountain system may take longer that the
desolder/hand solder method.
You can see a little more about solder fountain rework on our website at:
http://www.circuittechctr.com/guides/8-1-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 12:33 PM
To: [log in to unmask]
Subject: [TN] Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side via
a solder pot system to reflow the solder, remove the component, and replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed zozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time usage
requirement.
As always, I appreciate your excellent advice.
Rgds,
John
----------------------------------------------------------------------------
-----
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=========================================================================
Date: Tue, 23 Oct 2001 14:39:59 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Question regarding ENIG and solder mask
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_90.1bb7c4b3.2907137f_boundary"
--part1_90.1bb7c4b3.2907137f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
The ENIG can go before or after solder mask.... Afterwards will be the
beloved SMOBC (Slober Mask Over Bare Copper). The SMOBC is by far the most
common in the "digital" PC board configuration although the reverse is true
in RF circuitry. That is the boards are usually ENIG prior to mask due to
exposed circuits that need a finish. This brings us around about to finishes
again, I fear. Is the ENIG the finish of the future with its nickel
controversy...
Coretec Brad
--part1_90.1bb7c4b3.2907137f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>The ENIG can go before or after solder mask.... Afterwards will be the beloved SMOBC (Slober Mask Over Bare Copper). The SMOBC is by far the most common in the "digital" PC board configuration although the reverse is true in RF circuitry. That is the boards are usually ENIG prior to mask due to exposed circuits that need a finish. This brings us around about to finishes again, I fear. Is the ENIG the finish of the future with its nickel controversy...
<BR>
<BR>Coretec Brad</FONT></HTML>
--part1_90.1bb7c4b3.2907137f_boundary--
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Date: Tue, 23 Oct 2001 13:39:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: SMT part with Backside Ground
Hi All
Hope some one can help? We have have a board from a customer which has a
PSSop-16 with a Backside Ground ( #RF2119DBP). The stencil house has made
a cutout that is slightly smaller then the ground on the device. The
ground plane area on the card is basically the size of the body of the part
with 10 via holes in it.
The customer wants evidance of solder reflow on the ends (Tinning of the
Gold Plate). Current stencil does not get enough paste to do this and we
are concerned that if we make the cut out larger then the device contact,
the part may ride on top of the extra solder and result in
opens/insufficients on the leads. Also I have been unable to find a
recomended land/paste pattern for this type of device.
Any ideas would be appreciated.
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Date: Tue, 23 Oct 2001 14:58:39 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Question regarding ENIG and solder mask & Another Subject
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Thanks everyone for your input. I'll think I'll just leave it up to the
fabricator to know what they're to do (they do, don't they?) and leave it
at that. If they plate after solder mask, it would save precious metal
use, and maybe 'save us a buck or two.'
OH, by the way, on another subject...
Anyone out in TechNet land know of tech pubs or papers dealing with solving
or decreasing susceptability problems for CE testing? We (I) have a board
design that is just barely passing the 3V/m test, and the same board in
another configuration fails the same test. (oops) Am I giving enough
information (you know, the dead brain cell thing...)?
I humbly await the collective wisdom of the scholars and gurus of
Technet...
Sincerely,
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
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=========================================================================
Date: Tue, 23 Oct 2001 14:36:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: BGA Rework - Cleaning board pads (REPOST)
X-To: William Raymond <[log in to unmask]>
Bill,
Our experience in reworking thousands of BGA components indicates that
there is a relatively high risk of exposing the intermetallic layer when
using solder wick to clear pads of old solder prior to placing new
components.
Perhaps the small size of the pads relative to the mass of the wick and
soldering iron make them venerable to the exposure of the intermetallic
during the wicking operation. Our basic instruction to technicians is not
to remove solder from the old pads so that the pads look, crusty or
granular. Leave a sheen or a slight layer of solder to protect from
intermetallic exposure.
A skilled and experienced 'prep' technician can eliminate this problem.
However, big smoking irons or ultra-light efficient irons can create
problems when wick is ground into the site in an effort to get every last
bit of solder off the pads as quickly as possible. More and more people
use a teflon tipped vacuum removal device to evacuate solder. This
prevents intermetallic exposure and limits collateral damage to solder mask
in the area.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
On Tue, 23 Oct 2001 14:18:38 -0400, Bill Raymond <[log in to unmask]>
wrote:
Hello all,
During the process of replacing PBGA devices, we use solder wick to
remove excess solder from the board pads before stencil printing (with a
mini-stencil) solder paste and then using our Air-Vac system to place and
reflow the BGA. My question... what risk do we have in exposing the
intermetallic layer while we are cleaning off excess solder from the board
pads with solder wick? Every once in awhile, we see a solder joint that
just seems not to wet to the board pad... it's as if the solder paste that
was printed on that pad "jumped" up to increase the size of the BGA solder
ball and just didn't wet to the board pad. So now that larger looking ball
is simply resting on the pad. I am using a small mirror ( .250 inch
square) mounted on a dental pick (for a handle) and a stereo microscope...
to inspect the outer row of BGA balls.
>
>Thanks, Bill
>
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=========================================================================
Date: Tue, 23 Oct 2001 17:32:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Through Hole Oscillator Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Do you need to retain the part you are removing? If not, why not just cut
the leads, remove the part then unsolder the remaining lead extensions.
----- Original Message -----
From: "John Fahey" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, October 23, 2001 12:33 PM
Subject: [TN] Through Hole Oscillator Removal
> Good Morning.
>
> I have a PCB assembly where I need to remove a 4 pin through hole
> oscillator and replace it with a different date code. (@5K units)
>
> AirVac recommends that this removal be done by heating the bottom side via
> a solder pot system to reflow the solder, remove the component, and
replace
> it with a new one.. Unfortunately, there are 3 capacitors on the bottom
> side which lie in the vicinity of the through hole leads which would
> necessitate a specially designed zozzle.
>
> Does anyone have ANY other advice/recommendations for a system to
> remove/replace through hole components from a PCBA. I am particularly
> interested ina ny systems that can be leased as this is a one time usage
> requirement.
>
> As always, I appreciate your excellent advice.
>
> Rgds,
> John
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date: Tue, 23 Oct 2001 16:34:50 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Buscomb, Scott" <[log in to unmask]>
Subject: UL ZPMV2 Listings
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Does anyone have the decoder ring to make sense of the "type" as indicated
on an Underwriters Labratories ZPMV2 PCB manufacturers sheet?
Thanks,
Scott
Scott Buscomb
PCB Design Engineer
Zight Corporation
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Date: Tue, 23 Oct 2001 15:47:08 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: UL ZPMV2 Listings
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
try this.-
http://www.ul.com/about/otm/otmv2n4/flex.html
phil
-----Original Message-----
From: Buscomb, Scott [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 3:35 PM
To: [log in to unmask]
Subject: [TN] UL ZPMV2 Listings
Does anyone have the decoder ring to make sense of the "type" as indicated
on an Underwriters Labratories ZPMV2 PCB manufacturers sheet?
Thanks,
Scott
Scott Buscomb
PCB Design Engineer
Zight Corporation
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Date: Tue, 23 Oct 2001 15:59:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: UL ZPMV2 Listings
MIME-Version: 1.0
Content-Type: text/plain
Scott
Only your fabricator knows for sure. I don't think there's any kind of
standardization from fabricator to fabricator. We have over 100 listings on
our ZPMV2 and I have know idea what they all are (or why we need so many).
Our "decoder ring" is an Excel Spreadsheet that has the details for the Top
25 or so types that we use most often. Fortunately it's not my job to out
which type to put on any given board. I think we have it in our capital
plan to upgrade to an "8-Ball" or "Ouija" board to do this in the future.
;-)
> ----------
> From: Buscomb, Scott[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Tuesday, October 23, 2001 3:34 PM
> To: [log in to unmask]
> Subject: [TN] UL ZPMV2 Listings
>
> Does anyone have the decoder ring to make sense of the "type" as indicated
> on an Underwriters Labratories ZPMV2 PCB manufacturers sheet?
> Thanks,
> Scott
> Scott Buscomb
> PCB Design Engineer
> Zight Corporation
>
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Date: Tue, 23 Oct 2001 20:37:03 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Assembling T-Lam boards...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi all!
Looks like we may be getting some business putting together assemblies that
utilize T-Lam substrates. Haven't dealt with them directly, but I did a
search and
found a link to:
http://www.thermagon.com/script/templates/pdf/T-guideII-Manufacturing.PDF
After reading it, it sounds like it shouldn't be anything that is overly
difficult, but that's coming from the *.PDF file from the manufacturer, and
as we find out sometimes, the manufacturer always says things are a "piece of
cake". But "ocassionally" we find out that things aren't quite as straight
forward as stated (I have my tongue in my cheek as I type this...)
Anyways, have any of you had the pleasure of working with T-Lam substrated
assemblies? Anything you'd be willing to share? This is a SMT assembly BTW...
Any inputs are very much 'preciated!!!
-Steve Gregory-
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Date: Tue, 23 Oct 2001 21:00:50 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: modeling
MIME-Version: 1.0
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Hi Waleed,
You are not very specific--thus the answer is a qualified yes.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Tue, 23 Oct 2001 21:06:56 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Land pattern for wave soldering
MIME-Version: 1.0
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The most cogent discussion of secondary side pads for wave soldering is in
"Manufacturing Techniques For Surface Mounted Assemblies" R. J. Klein
Wassink & M. M. F. Verguld, Electrochemical Publications, 1995, ISBN
0901150304.
We align most SMT devices with the direction of travel as we would align a
similarly leaded PTH component. The exception is devices with leads on four
sides, such as QFP and PLCC, which are aligned 45° to the wave.
Other points:
* QFP, PLCC, and SOP variants have thief [scavanger] pads trailing the last
pads to see the wave.
* Generally, wave side SMT pads are narrower and have less protrusion from
the component body than primary side pads.
Dave Fish
----- Original Message -----
From: "Patrick Lam" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, October 23, 2001 8:26 AM
Subject: [TN] Land pattern for wave soldering
> Hi Technetters,
>
> Is there a need to have different SMD land size/ pattern for wave
soldering? Any
> suggestion is appreciated.
>
> Thanks,
> Patrick
>
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Date: Wed, 24 Oct 2001 11:28:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Question regarding ENIG and solder mask
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Roger,
ENIG plating can be done either before or after solder masking. If before,
you just get more ENIG plating on the board as no areas will be masked.
This might cost a little more because of the extra chemicals consumed, but
saves the risk of the mask being attacked by the gold plating bath.
If after, the you save on the Nickel/Gold plating but have to have a solder
mask that is capable of withstanding the plating processes, particularly
the Gold one.
Peter Duncan
"Roger M. Stoops"
<rstoops@SPECTRAPRECISI To: [log in to unmask]
ONDAY.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Question regarding ENIG and
solder mask
10/23/01 11:52 PM
Please respond to
"TechNet E-Mail Forum."
For some reason I can't recollect (due to advancing age, dead brain cells,
etc.) whether ENIG plating is done before solder mask or after . I
remember something about the chemical baths attacking the solder mask, so
all electroless nickel and immersion gold plating would have to be done
first. Could someone check my memory for me please?
Roger M. Stoops, C.I.D., PCB Designer
[log in to unmask]
Trimble
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Ph: +01 937.233.8921 or +01 937.233.4574 ext 288
Fax: +01 937.233.7511
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Date: Wed, 24 Oct 2001 08:15:48 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Braime, Justin" <[log in to unmask]>
Subject: Re: Acceleration (g) - Free Unit Conversion Software
MIME-Version: 1.0
Content-Type: text/plain
For converting anything I always use 'Convert' software from
http://www.joshmadison.com/software/ it's freeware and excellent to use.
J.
> -----Original Message-----
> From: Hinners Hans M Civ WRALC/LUGE [SMTP:[log in to unmask]]
> Sent: 23 October 2001 17:13
> To: [log in to unmask]
> Subject: [TN] Acceleration (g) - Free Unit Conversion Software
>
> Hey Gang,
>
> This is not an endorsement. But everybody knows that already.
>
> I take the daring step to reopen the acceleration thread long enough to
> say:
> Nelco's got a unit conversion calculator in their Designers Corner that
> includes acceleration in g's.
> http://www.parknelco.com
>
> It takes a free username and password to get into the Designers Corner.
>
> I now return you to your regularly scheduled e-mail.
>
> Hans
>
> Integrity First - Service Before Self - Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> Special Operations Forces System Program Office (SOF - SPO)
> Gunship Team
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax: (478) 926 - 4911
> DSN Prefix: 468
>
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Date: Wed, 24 Oct 2001 08:23:04 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Braime, Justin" <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
MIME-Version: 1.0
Content-Type: text/plain
Hi Andre,
In this situation, I've found that an array of smaller square stencil
apertures, covering the entire area works well. You get the coverage but
without the excessive solder volume.
J.
> -----Original Message-----
> From: Andre Leclair [SMTP:[log in to unmask]]
> Sent: 23 October 2001 19:39
> To: [log in to unmask]
> Subject: [TN] SMT part with Backside Ground
>
> Hi All
>
> Hope some one can help? We have have a board from a customer which has a
> PSSop-16 with a Backside Ground ( #RF2119DBP). The stencil house has made
> a cutout that is slightly smaller then the ground on the device. The
> ground plane area on the card is basically the size of the body of the
> part
> with 10 via holes in it.
> The customer wants evidance of solder reflow on the ends (Tinning of the
> Gold Plate). Current stencil does not get enough paste to do this and we
> are concerned that if we make the cut out larger then the device contact,
> the part may ride on top of the extra solder and result in
> opens/insufficients on the leads. Also I have been unable to find a
> recomended land/paste pattern for this type of device.
> Any ideas would be appreciated.
>
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Date: Wed, 24 Oct 2001 09:12:01 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neil Atkinson <[log in to unmask]>
Subject: Re: Land pattern for wave soldering
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I would suggest you get a copy of the classic Klein Wassink book 'Soldering
in Electronics' (ISBN 0 901150 24X).
Wave soldering SOICs, I would add extra pads at the trailing end of the IC
connected to the last pads of the IC by fine tracks with no resist on.
Neil
-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: 23 October 2001 17:41
Subject: Re: Land pattern for wave soldering
Hi Steve,
Thanks for the prompt response.
What kind of solder thieves should I put in, say a SOIC08? Do I need to put
in
leading pads and leading pads? Is there any standard published that I can
find
or buy regarding wave soldering issues?
Thanks for the support.
Patrick
Steve Owen <[log in to unmask]> on 10/23/2001 09:03:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Patrick Lam/SEL)
Subject: Re: [TN] Land pattern for wave soldering
Hi Patrick,
If you look at say a side one footprint(reflow)for quad flat pack as opposed
to a side two (wavesolder)side. On side two you will ideally need to present
the component @ 45 deg to the wave and have solder thieves in each of the
four corners to eliminate solder bridges.
just an example.
hope its of some use.
-----Original Message-----
From: Patrick Lam [mailto:[log in to unmask]]
Sent: 23 October 2001 16:26
To: [log in to unmask]
Subject: [TN] Land pattern for wave soldering
Hi Technetters,
Is there a need to have different SMD land size/ pattern for wave soldering?
Any
suggestion is appreciated.
Thanks,
Patrick
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Date: Wed, 24 Oct 2001 11:27:49 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Antw: [TN] exposing intermetallic on BGA pads...
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Bill
Yes, it is quite possible to expose intermetallics when removing the =
excessive solder and yes it is the most normal thing in the world that =
these intermetallics won't be wetted by the solder. If you do rework you =
must either leave the solder on the pad or remove the intermetallics with =
a glass brush. Bob Willis knows a lot about that.
Best regards
Guenter
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Wed, 24 Oct 2001 12:04:45 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Through Hole Oscillator Removal
MIME-Version: 1.0
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John,
I know this problem of heavy ground plane connection. Preheating the
assembly did help a lot.=20
"Long ago" in the age of PTH-IC=B4s they used to have solder iron tips =
to heat
all leads of a chip simultaniously mainly for rework purposes.
As I recall the oscillators do fit to those measures.
You could probably mount your solder iron, use flux and new solder for =
each
assy and dip it in the "pot" you created.
Haven=B4t tried it myself but seems to a less expensive methode if it =
works.
Good luck Wolfgang=20
-----Urspr=FCngliche Nachricht-----
Von: John Fahey [mailto:[log in to unmask]]
Gesendet am: Dienstag, 23. Oktober 2001 20:25
An: [log in to unmask]
Betreff: Re: [TN] Through Hole Oscillator Removal
Jerry
Thanks for the info. As you mentioned, the leads DO indeed have a heavy
ground plane connection that prevents us being able to use the =
traditional
soldering irons.
Are there any other options other than the Solder Fountain system. =
Also,
does anyone know where we could lease/rent this system as these are =
approx
$9K new and this is only a one time use.
Thanks
John
-----Original Message-----
From: Jeff Ferry [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 10:49 AM
To: [log in to unmask]
Subject: Re: [TN] Through Hole Oscillator Removal
John,
We have 4 Electrovert solder fountain systems, but suspect we would =
first
try using good old vacuum desoldering systems to remove the part, and
traditional soldering irons to replace it. The solder fountain systems =
may
be useful if the leads have heavy ground plane connections, but setup =
and
preparation for the solder fountain system may take longer that the
desolder/hand solder method.
You can see a little more about solder fountain rework on our website =
at:
http://www.circuittechctr.com/guides/8-1-2.htm
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 12:33 PM
To: [log in to unmask]
Subject: [TN] Through Hole Oscillator Removal
Good Morning.
I have a PCB assembly where I need to remove a 4 pin through hole
oscillator and replace it with a different date code. (@5K units)
AirVac recommends that this removal be done by heating the bottom side =
via
a solder pot system to reflow the solder, remove the component, and =
replace
it with a new one.. Unfortunately, there are 3 capacitors on the bottom
side which lie in the vicinity of the through hole leads which would
necessitate a specially designed zozzle.
Does anyone have ANY other advice/recommendations for a system to
remove/replace through hole components from a PCBA. I am particularly
interested ina ny systems that can be leased as this is a one time =
usage
requirement.
As always, I appreciate your excellent advice.
Rgds,
John
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Date: Wed, 24 Oct 2001 05:21:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Antw: [TN] exposing intermetallic on BGA pads...
Guenter,
I cannot believe how much I am learning every minute about soldering and all
comprising it. Not at all being negative or contrary, I must have ruined
thousands of solder joints in my long life in this business notwithstanding
all the rework I've done and taught others.
All I've ever been taught, done, and taught others is to remove the solder,
with whatever means that works without damaging pads or board materials,
then print paste, place components, and reflow.
I've never even heard of leaving on solder or removing intermetallics -
especially with a glass brush. I finished my last contract, seemingly
successfully, two months ago. Can the world and all its "wonderful"
soldering technology all of a sudden be passing me by in such a short time?
Jeez, a glass brush. Thanks again Guenter, but I must need more help than
even you, Bob Willis, or all other experts can give.
Earl
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Date: Wed, 24 Oct 2001 13:16:34 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogdan Gabi <[log in to unmask]>
Subject: Re: Antw: [TN] exposing intermetallic on BGA pads...
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I would like to know also more about the technique, especially if it =
should
be applied for circuits with specific finishes or for all.
Gaby
> ----------
> From: Earl Moon[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: ?=E9=E5=ED =F8=E1=E9=F2=E9 24 =E0=E5=F7=E8=E5=E1=F8 2001? =
13:21
> To: [log in to unmask]
> Subject: Re: [TN] Antw: [TN] exposing intermetallic on BGA pads...
>=20
> Guenter,
>=20
> I cannot believe how much I am learning every minute about soldering =
and
> all
> comprising it. Not at all being negative or contrary, I must have =
ruined
> thousands of solder joints in my long life in this business
> notwithstanding
> all the rework I've done and taught others.
>=20
> All I've ever been taught, done, and taught others is to remove the
> solder,
> with whatever means that works without damaging pads or board =
materials,
> then print paste, place components, and reflow.
>=20
> I've never even heard of leaving on solder or removing intermetallics =
-
> especially with a glass brush. I finished my last contract, seemingly
> successfully, two months ago. Can the world and all its "wonderful"
> soldering technology all of a sudden be passing me by in such a short
> time?
>=20
> Jeez, a glass brush. Thanks again Guenter, but I must need more help =
than
> even you, Bob Willis, or all other experts can give.
>=20
> Earl
>=20
> =
------------------------------------------------------------------------=
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> -------
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> -------
>=20
------_=_NextPart_001_01C15C74.F533F7F0
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<HEAD>
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charset=3Diso-8859-8">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2652.35">
<TITLE>RE: [TN] Antw: [TN] exposing intermetallic on BGA =
pads...</TITLE>
</HEAD>
<BODY>
<P ALIGN=3DLEFT><FONT COLOR=3D"#0000FF" SIZE=3D2 FACE=3D"Arial">I would =
like to know also more about the technique, especially if it should be =
applied for circuits with specific finishes or for all.</FONT></P>
<P ALIGN=3DLEFT><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Arial">Gaby</FONT></P>
<UL>
<P ALIGN=3DLEFT><FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">----------</FONT></P>
<P ALIGN=3DLEFT><B><FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">From:</FONT></B> <FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">Earl Moon[SMTP:[log in to unmask]]</FONT></P>
<P ALIGN=3DLEFT><B><FONT SIZE=3D1 FACE=3D"MS Sans Serif">Reply =
To:</FONT></B> <FONT SIZE=3D1 FACE=3D"MS =
Sans Serif">TechNet E-Mail Forum.</FONT></P>
<P ALIGN=3DLEFT><B><FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">Sent:</FONT></B> <FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">‏=E9=E5=ED =F8=E1=E9=F2=E9 24 =E0=E5=F7=E8=E5=E1=F8 =
2001‏ 13:21</FONT></P>
<P ALIGN=3DLEFT><B><FONT SIZE=3D1 FACE=3D"MS Sans Serif">To:</FONT></B> =
<FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">[log in to unmask]</FONT></P>
<P ALIGN=3DLEFT><B><FONT SIZE=3D1 FACE=3D"MS Sans =
Serif">Subject:</FONT></B> <FONT =
SIZE=3D1 FACE=3D"MS Sans Serif">Re: [TN] Antw: [TN] exposing =
intermetallic on BGA pads...</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Guenter,</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">I cannot believe how much =
I am learning every minute about soldering and all</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">comprising it. Not at all =
being negative or contrary, I must have ruined</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">thousands of solder =
joints in my long life in this business notwithstanding</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">all the rework I've done =
and taught others.</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">All I've ever been =
taught, done, and taught others is to remove the solder,</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">with whatever means that =
works without damaging pads or board materials,</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">then print paste, place =
components, and reflow.</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">I've never even heard of =
leaving on solder or removing intermetallics -</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">especially with a glass =
brush. I finished my last contract, seemingly</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">successfully, two months =
ago. Can the world and all its "wonderful"</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">soldering technology all =
of a sudden be passing me by in such a short time?</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Jeez, a glass brush. =
Thanks again Guenter, but I must need more help than</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">even you, Bob Willis, or =
all other experts can give.</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Earl</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 =
FACE=3D"Arial">---------------------------------------------------------=
------------------------</FONT></P>
<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Technet Mail List =
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Date: Wed, 24 Oct 2001 09:09:15 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Assembling T-Lam boards...
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Hello Steve,
As PCB supplier Coretec fabricates and delivers quite a bit of this product.
T-lam is the dielectric made by Thermagon and its niche in life is its
ability to conduct heat at 10X the rate of FR4. Those who use it love it;
those that don't have a need never use it. We build standard PCB's that are
laminated to heatsinks using the T-lam prepreg. We also deliver single,
double and multilayer boards built with Thermagon dieletrics replacing FR4;
all UL approved.
In any case I have never heard one bad thing regarding assembly (or
otherwise, save the price). Pretty big statement, but true.
Boston Brad
781 858 0783
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello Steve,
<BR>
<BR>As PCB supplier Coretec fabricates and delivers quite a bit of this product. T-lam is the dielectric made by Thermagon and its niche in life is its ability to conduct heat at 10X the rate of FR4. Those who use it love it; those that don't have a need never use it. We build standard PCB's that are laminated to heatsinks using the T-lam prepreg. We also deliver single, double and multilayer boards built with Thermagon dieletrics replacing FR4; all UL approved.
<BR>In any case I have never heard one bad thing regarding assembly (or otherwise, save the price). Pretty big statement, but true.
<BR>
<BR>Boston Brad
<BR>781 858 0783</FONT></HTML>
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Date: Wed, 24 Oct 2001 09:27:57 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: BUS WIRE
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The 343 wire is very good, used it in all MIL applications.
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>The 343 wire is very good, used it in all MIL applications.</FONT></HTML>
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Date: Wed, 24 Oct 2001 15:28:57 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Adjusting the alloy composition in the solderpot
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Hi Technet,
I just received an analyses report for our solder bath composition, and my =
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at =
the edge of the J-STD-001C specification, so I'll have to add some pure =
tin to the pot.
Last time was many years ago, and unfortunately I forgot the formula for =
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.=20
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Wed, 24 Oct 2001 08:59:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kauling <[log in to unmask]>
Organization: Tri-onics, Inc.
Subject: Re: Adjusting the alloy composition in the solderpot
Daan
I do not have the formula, sorry. I would lean on your solder supplier to
help you.
Have you determined a root cause for the Sn levels to decrease? I was
wondering because, we are beginning to use white tin for a final finish.
Scott Kauling
-----Original Message-----
From: d. terstegge [SMTP:[log in to unmask]]
Sent: Wednesday, October 24, 2001 9:29 AM
To: [log in to unmask]
Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Wed, 24 Oct 2001 07:10:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Darrel Therriault <[log in to unmask]>
Organization: INCEP Technologies, Inc.
Subject: Re: Assembling T-Lam boards...
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Brad.
Out of curiosity, what is the cost factor for TLam in a PWB?
DT
Brad Saunders wrote:
> Hello Steve,
>
> As PCB supplier Coretec fabricates and delivers quite a bit of this
> product. T-lam is the dielectric made by Thermagon and its niche in
> life is its ability to conduct heat at 10X the rate of FR4. Those who
> use it love it; those that don't have a need never use it. We build
> standard PCB's that are laminated to heatsinks using the T-lam
> prepreg. We also deliver single, double and multilayer boards built
> with Thermagon dieletrics replacing FR4; all UL approved.
> In any case I have never heard one bad thing regarding assembly (or
> otherwise, save the price). Pretty big statement, but true.
>
> Boston Brad
> 781 858 0783
--
Darrel Therriault
VP, Mfg. Operations
INCEP Technologies, Inc
(858)547-9925 223
[log in to unmask]
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Brad.
<p>Out of curiosity, what is the cost factor for TLam in a PWB?
<p>DT
<br>
<br>
<br>
<p>Brad Saunders wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Hello
Steve,</font></font>
<p><font face="arial,helvetica"><font size=-1>As PCB supplier Coretec fabricates
and delivers quite a bit of this product. T-lam is the dielectric
made by Thermagon and its niche in life is its ability to conduct heat
at 10X the rate of FR4. Those who use it love it; those that don't
have a need never use it. We build standard PCB's that are laminated
to heatsinks using the T-lam prepreg. We also deliver single, double
and multilayer boards built with Thermagon dieletrics replacing FR4; all
UL approved.</font></font>
<br><font face="arial,helvetica"><font size=-1>In any case I have never
heard one bad thing regarding assembly (or otherwise, save the price).
Pretty big statement, but true.</font></font>
<p><font face="arial,helvetica"><font size=-1>Boston Brad</font></font>
<br><font face="arial,helvetica"><font size=-1>781 858 0783</font></font></blockquote>
<p>--
<br>Darrel Therriault
<br>VP, Mfg. Operations
<br>INCEP Technologies, Inc
<br>(858)547-9925 223
<br>[log in to unmask]
<br> </html>
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Date: Wed, 24 Oct 2001 16:32:04 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
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Hi Scott,
Don't know the root cause, but I think that the composition of dross is =
just a little different than the composition of the solder. This took us =
about 6 years to get to this 61.5 percent Sn level (that's the age of the =
machine)
I think there were some discussions recently about how the leadtin =
composition is affected by the boards conductor finishing, and if I =
remember it well the use of white tin shouldn't result in any problems =
with the solder pot composition.
Daan
>>> Scott Kauling <[log in to unmask]> 10/24 2:59 pm >>>
Daan
I do not have the formula, sorry. I would lean on your solder supplier to
help you.
Have you determined a root cause for the Sn levels to decrease? I was
wondering because, we are beginning to use white tin for a final finish.
Scott Kauling
-----Original Message-----
From: d. terstegge [SMTP:[log in to unmask]]=20
Sent: Wednesday, October 24, 2001 9:29 AM
To: [log in to unmask]
Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure =
tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net=20
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Date: Wed, 24 Oct 2001 10:33:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
MIME-Version: 1.0
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I not sure I understand what you're saying about your customer's
requirement, but appreciate your concern about printing too much paste and
floating the part.
We assemble with EPTSSOP [Exposed Pad Thin Shrink Small Outline Package]
parts, which sounds similar to your part. EPTSSOP increases the thermal
efficiency of power constrained standard TSSOP packages by as much as 150%
by soldering the heat sink pad on the bottom of the package to the board.
Apparently, Amkor [the part fabricator] is particularly optimistic about our
ability to assemble boards with these parts. So, they provide virtually no
information on their site, other than "use standard processes". [er, words
to that effect] We printed various paste volumes, placed, reflowed, and
sectioned dummy parts from Practical Components [probably Top Line and
others have similar parts].
If your customer is asking you to prove that there is solder coverage of the
gold pad for the heat sink after soldering,
* Why not just pop the part off the board with a beer can opener?
* Never tried this, but wont your xray machine show this?
Dave Fish
----- Original Message -----
From: "Andre Leclair" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, October 23, 2001 11:39 AM
Subject: [TN] SMT part with Backside Ground
> Hi All
>
> Hope some one can help? We have have a board from a customer which has a
> PSSop-16 with a Backside Ground ( #RF2119DBP). The stencil house has made
> a cutout that is slightly smaller then the ground on the device. The
> ground plane area on the card is basically the size of the body of the
part
> with 10 via holes in it.
> The customer wants evidance of solder reflow on the ends (Tinning of the
> Gold Plate). Current stencil does not get enough paste to do this and we
> are concerned that if we make the cut out larger then the device contact,
> the part may ride on top of the extra solder and result in
> opens/insufficients on the leads. Also I have been unable to find a
> recomended land/paste pattern for this type of device.
> Any ideas would be appreciated.
>
> --------------------------------------------------------------------------
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Date: Wed, 24 Oct 2001 09:51:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
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Hi Daan! You are right - its not that difficult but even a metallurgical
engineer (e.g. me!) can't remember the formula. However, the industry
leaders anticipated just such lapses of memory and have documented the
formula in the JSTD-001 Handbook, page 62 (paragraph 5.3.7). Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
"d. terstegge" <[log in to unmask]>@ipc.org> on 10/24/2001
09:28:57 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
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Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Wed, 24 Oct 2001 11:08:50 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Assembling T-Lam boards...
MIME-Version: 1.0
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....costing... hmmm....
case by case, it depends.... etc etc... approximates are no good....
I would say add a third to comparible FR4 build, cheap if you need it.
Boston Brad....
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>....costing... hmmm....
<BR>case by case, it depends.... etc etc... approximates are no good....
<BR>
<BR>I would say add a third to comparible FR4 build, cheap if you need it.
<BR>
<BR>Boston Brad....
<BR>
<BR></FONT></HTML>
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Date: Wed, 24 Oct 2001 10:08:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Daan! The preferential loss of tin in a wave solder pot is typically
driven by the amount of dross the solder pot produces. Tin oxidizes much
faster than lead thus the solder dross has a high tin content which results
in lower tin % in your wave solder pot.
Dave Hillman
Rockwell Collins
[log in to unmask]
"d. terstegge" <[log in to unmask]>@ipc.org> on 10/24/2001
10:32:04 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Hi Scott,
Don't know the root cause, but I think that the composition of dross is
just a little different than the composition of the solder. This took us
about 6 years to get to this 61.5 percent Sn level (that's the age of the
machine)
I think there were some discussions recently about how the leadtin
composition is affected by the boards conductor finishing, and if I
remember it well the use of white tin shouldn't result in any problems with
the solder pot composition.
Daan
>>> Scott Kauling <[log in to unmask]> 10/24 2:59 pm >>>
Daan
I do not have the formula, sorry. I would lean on your solder supplier to
help you.
Have you determined a root cause for the Sn levels to decrease? I was
wondering because, we are beginning to use white tin for a final finish.
Scott Kauling
-----Original Message-----
From: d. terstegge [SMTP:[log in to unmask]]
Sent: Wednesday, October 24, 2001 9:29 AM
To: [log in to unmask]
Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Wed, 24 Oct 2001 11:18:31 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
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Hi Daan!
I had that happen to me back in May of this year. Our analysis came back and
we were at 61.9%. On my analysis sheet, it was recommended to add 3-lbs of
pure tin for every 100-lbs of solder to bring the pot back back to a nominal
63%...
I'm no metallurgist, nor am I a good mathematician (I think everybody on the
TechNet knows that...hehehe). But we have a 1500-lb pot, and I put 45-lbs. of
pure tin in as recommended, the next sample after that we were dead-on 63%...
Maybe somebody better at math than me can decipher a formula from that...
-Steve Gregory-
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Daan!
<BR>
<BR>I had that happen to me back in May of this year. Our analysis came back and we were at 61.9%. On my analysis sheet, it was recommended to add 3-lbs of pure tin for every 100-lbs of solder to bring the pot back back to a nominal 63%...
<BR>
<BR>I'm no metallurgist, nor am I a good mathematician (I think everybody on the TechNet knows that...hehehe). But we have a 1500-lb pot, and I put 45-lbs. of pure tin in as recommended, the next sample after that we were dead-on 63%...
<BR>
<BR>Maybe somebody better at math than me can decipher a formula from that...
<BR>
<BR>-Steve Gregory-</FONT></HTML>
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Date: Wed, 24 Oct 2001 10:42:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
Only remember you making one interesting math mistake a couple of years ago.
I think it concerned the TechNet population swelling to 2,000 members from
what - meaning it needed only how many more members? What was that profound
statememt again?
Hell, hardly anyone caught it. Certainly not me as I thought you were right.
No math hero here either. Guenter and his Laplace transforms! I had a hard
time with that stuff over 30 years ago. Certainly in the same boat with you
now.
Earl
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Date: Wed, 24 Oct 2001 11:05:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Lead Free Surface finishes
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Hi Graham! Here is a pdf of one of our reports:
(See attached file: 00057.pdf)
Dave
Graham Naisbitt <[log in to unmask]>@ipc.org> on 10/16/2001
11:37:14 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Lead Free Surface finishes
For Dave Hillman
Dave thanks for that input - it is very useful.
As I may have explained, we are doing this work as part of a paper we are
to
present at a conference in Singapore. Might we be able to see a copy of
your
work and to reference it in ours?
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk <http://www.concoat.co.uk>
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Tuesday, October 16, 2001 04:58
To: [log in to unmask]
Subject: Re: [TN] Lead Free Surface finishes
Hi Graham! Let me propose a different angle to your request: spend the
money now during your testing to acquire an understanding on how the
different surface finishes influence/interact with the testing protocol
before settling on "one" finish. Rockwell Collins has spent the last 2
years testing finishes and gathering industry data on the alternative
surface finishes. We have "qualified" several finishes - some work better
in specific use applications than others. However, I also believe that we
will eventually settle on just a couple (yep, you guessed it - immersion
silver and immersion tin) as the main choices for assembly designs. One
finish doesn't fit all as HASL did - if you limit your testing now you may
end up doing additional testing in the future. Good Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Graham Naisbitt <[log in to unmask]>@ipc.org> on 10/15/2001
05:52:10 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Lead Free Surface finishes
Techies and (I guess - Leadies?)
We are about to carry out some reliability test work, examining the
influences of electro-chemical reactions using SIR techniques.
The manufacturing process that will be employed involves lead-free
soldering materials, water based fluxes and water based conformal
coatings. The methodology we shall employ shall be as drafted in a new IEC
draft spec 6-1189.
The coupon we will use is intended to model mixed technology as closely as
possible. We include through-hole connectors, J lead SOIC's, BGA 225, SMT
Capacitors and QFP 160.
We will use an LPIM resist and were going to examine 4 different surface
finishes:
NiAu (ENIG)
ImSn - Immersion Tin
ImAg - Immersion Silver
OSP
However, and to get to the question: We can't afford all these
permutations so, we shall select only one surface finish. Can you folks
advise the most popular surface finish that is likely to be used for
lead-free processing?
Please, we would REALLY like a simple answer rather than to open a huge
dialogue - 'cos we have to get the testing done by Mid November and we
have yet to have the coupons made!!
Awaiting your replies with interest.
Regards, Graham Naisbitt
[log in to unmask]
www.concoat.co.uk
For instant access to Product Data Sheets register on the Tech-Shot area
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Date: Wed, 24 Oct 2001 11:02:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
David
We have been x-raying to verify sufficient bonding of the ground terminal
to the pad, however the customer ( who is always right!!) wants solder
evident to the outer edges to ensure there is enough thermal mass for heat
dissipation.
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Date: Wed, 24 Oct 2001 12:23:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
Though MIL-STD-883E primarily is used for semiconductor and hybrid component
testing, using test method 2030 might lend more credence to your thermal
issues. This method uses acoustic microspocy (C-SAM) to determine voiding
under chips using various mounting materials - mostly eutectic alloys.
Once voiding determined, using this method or others as x-ray or?,
traditional thermal effeciency analysis can be used rather than depending on
visuals as material "oozing" out from under the devices. When thermal
efficiency and effectiveness is proven acceptable, include the customer and
you'll all be right.
MoonMan
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Date: Wed, 24 Oct 2001 10:38:50 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
X-To: Andre Leclair <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Have you considered an alteration to the aperture in a non-standard form?
For heat sinks, I customarily do not print the entire pad. I cover 75 - 90%
of the pad with paste, using small dots. The result is good adhesion and
easy application. We have used the "beer can opener" trick to confirm full
wetting. Coverage is easily adjusted, by changing the diameter of the dots.
To improve visibility, possibly add a small half circle or half of an oval
(minor axis radius = 0.015" ??) to the end of the heatsink, to expose some
of the wetted area. (assuming the end of the heat is visible) The small
addition of the paste shouldn't affect the location of the device and will
provide the visibility the customer needs.
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Andre Leclair [SMTP:[log in to unmask]]
Sent: Wednesday, October 24, 2001 9:03 AM
To: [log in to unmask]
Subject: Re: [TN] SMT part with Backside Ground
David
We have been x-raying to verify sufficient bonding of the ground
terminal
to the pad, however the customer ( who is always right!!) wants
solder
evident to the outer edges to ensure there is enough thermal mass
for heat
dissipation.
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Date: Wed, 24 Oct 2001 10:40:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Timothy Reeves <[log in to unmask]>
Subject: Re: UL ZPMV2 Listings
X-To: "Crepeau, Phil" <[log in to unmask]>,
"[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I think Scott is asking about the board manufacturer's type codes (the first
column on the listing, formerly known as a yellow card) which are not
standardized, but rather chosen by the manufacturer to classify the
different types of boards they build. There isn't anything to "decode".
You'll have to get the process/product details from the other columns in the
listing or from the board shop in question if that doesn't answer your
question.
Tim
-----Original Message-----
From: Crepeau, Phil [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 3:47 PM
Subject: Re: UL ZPMV2 Listings
hi,
try this.-
http://www.ul.com/about/otm/otmv2n4/flex.html
phil
-----Original Message-----
From: Buscomb, Scott [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 3:35 PM
To: [log in to unmask]
Subject: [TN] UL ZPMV2 Listings
Does anyone have the decoder ring to make sense of the "type" as indicated
on an Underwriters Labratories ZPMV2 PCB manufacturers sheet?
Thanks,
Scott
Scott Buscomb
PCB Design Engineer
Zight Corporation
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Date: Wed, 24 Oct 2001 11:25:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter blokhuis <[log in to unmask]>
Subject: Re: Acceleration (g) - Free Unit Conversion Software
In-Reply-To: <FDF2A7D5FB2FD411AF020001021A477102517F44@MAILHUB>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Try:
www-sci.lib.uci.edu/HSG/RefCalculators4.html
--- "Braime, Justin" <[log in to unmask]> wrote:
> For converting anything I always use 'Convert'
> software from
> http://www.joshmadison.com/software/ it's freeware
> and excellent to use.
>
> J.
>
> > -----Original Message-----
> > From: Hinners Hans M Civ WRALC/LUGE
> [SMTP:[log in to unmask]]
> > Sent: 23 October 2001 17:13
> > To: [log in to unmask]
> > Subject: [TN] Acceleration (g) - Free Unit
> Conversion Software
> >
> > Hey Gang,
> >
> > This is not an endorsement. But everybody knows
> that already.
> >
> > I take the daring step to reopen the acceleration
> thread long enough to
> > say:
> > Nelco's got a unit conversion calculator in their
> Designers Corner that
> > includes acceleration in g's.
> > http://www.parknelco.com
> >
> > It takes a free username and password to get into
> the Designers Corner.
> >
> > I now return you to your regularly scheduled
> e-mail.
> >
> > Hans
> >
> > Integrity First - Service Before Self -
> Excellence in All We Do
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > Hans M. Hinners
> > Electronics Engineer
> > Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> > Special Operations Forces System Program Office
> (SOF - SPO)
> > Gunship Team
> > 226 Cochran Street
> > Robins AFB GA 31098-1622
> >
> > mailto:[log in to unmask]
> >
> > Com: (478) 926 - 5224
> > Fax: (478) 926 - 4911
> > DSN Prefix: 468
> >
> >
>
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Date: Wed, 24 Oct 2001 15:39:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Tin/gold Intermetallic
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
OK, the last one was fun. Let's see what I can "provoke" this time!
There are standards for gold thickness for ENIG, "rules" for the amount of
gold in tin/lead solder joints (~4% for tensile, ~2% for shear), but I have
not found, looking into the TechNet archives or in J. Hwang's or Rahn's or
Manko's books I don't have the Wassink et al book ;( ), what is the range
of acceptable/expected intermetallic thickness for tin/nickel intermetallic.
I would appreciate your input - any references and results seen in your own
work. Let the discussion begin.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: October 24, 2001 6:21 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Guenter,
I cannot believe how much I am learning every minute about soldering and all
comprising it. Not at all being negative or contrary, I must have ruined
thousands of solder joints in my long life in this business notwithstanding
all the rework I've done and taught others.
All I've ever been taught, done, and taught others is to remove the solder,
with whatever means that works without damaging pads or board materials,
then print paste, place components, and reflow.
I've never even heard of leaving on solder or removing intermetallics -
especially with a glass brush. I finished my last contract, seemingly
successfully, two months ago. Can the world and all its "wonderful"
soldering technology all of a sudden be passing me by in such a short time?
Jeez, a glass brush. Thanks again Guenter, but I must need more help than
even you, Bob Willis, or all other experts can give.
Earl
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Date: Wed, 24 Oct 2001 15:29:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
I cannot believe a man of your stature asking such a question. Incredible!
MoonMan
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Date: Wed, 24 Oct 2001 14:00:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: TUV: Color coding of wires in the power supply
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Does anyone know the color code of wires inside the power supply per
TUV?
Any help in that regards will be greatly appreciated.
re,
Ken Patel
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Date: Wed, 24 Oct 2001 16:00:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Tin/gold Intermetallic
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
OK, the last one was fun. Let's see what I can "provoke" this time!
*Must be a sloooooow day up in Canada. Bev must be waiting for the new lab
equipment to come in.
Doug Pauls
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Date: Wed, 24 Oct 2001 16:52:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Bergman <[log in to unmask]>
Subject: Call for papers ECWC9
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
We are just over one month away from the close of the call for papers for =
the Electronic Circuits World Convention 9 scheduled for 7-9 October 2002 =
in Cologne Germany. ECWC9 is hosted by the European Federation of =
Interconnecting and Packaging (EFIP), and is sponsored by IPC and other =
member associations of the World Electronic Circuits Council (WECC). We =
anticipate 100 of the best technical papers in the world on electronic =
circuits will be selected for this convention.
If your company would like to present a paper at this important global =
electronics event we ask you to complete a call for papers application and =
return it to IPC to my attention. A PDF file of the call for papers can =
be found at the link below:
http://www.ipc.org/html/ECWC9%20Call%20for%20Papers.pdf=20
If you prefer a hard copy, we can mail one to you. Please reply to =
[log in to unmask] with your mailing address.
Thank you for your interest.
Regards,
Dave Bergman, IPC
***************************************************************************=
David W. Bergman, CAE
Vice President Standards, Technology & International Relations
IPC
2215 Sanders Road
Northbrook, IL 60062-6135 USA
847-790-5340 Phone 847-504-2340 Fax
Mobile 847-867-1388
[log in to unmask]
www.ipc.org
***************************************************************************=
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Date: Wed, 24 Oct 2001 15:01:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Labs in tha Bay Area,
that can test FUSE & Inductor specifications.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Guys,
I think we have a Surface Mount Fuse that is out of spec and is allowing
more current to pass through it damaging the Ferrite Bead down the road.
So, I would like to test both parts whether they are build to the spec
and for that looking for nay lab that can help me out in the Bay Area.
Any help in this direction will be highly appreciated.
re,
Ken Patel
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Date: Wed, 24 Oct 2001 18:10:07 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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From Wassink:
"At relatively low temperatures, the tin-nickel layers form about as rapidly
as the tin-copper layers do, but at higher tempertures thier growth rate is
distinctly lower. At 100°C a 2um layer is formed in 50 days, at 170°C within
two days. A 10um layer is formed at 170°C in 38 days. The appearance of the
imtermetallic layers, as well as their composition, depends on the
temperatuee at which they are formed."
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> Sent: Wednesday, October 24, 2001 3:39 PM
> To: [log in to unmask]
> Subject: [TN] Tin/gold Intermetallic
>
>
> OK, the last one was fun. Let's see what I can "provoke" this time!
>
> There are standards for gold thickness for ENIG, "rules" for the amount of
> gold in tin/lead solder joints (~4% for tensile, ~2% for shear),
> but I have
> not found, looking into the TechNet archives or in J. Hwang's or Rahn's or
> Manko's books I don't have the Wassink et al book ;( ), what is
> the range
> of acceptable/expected intermetallic thickness for tin/nickel
> intermetallic.
> I would appreciate your input - any references and results seen
> in your own
> work. Let the discussion begin.
>
> regards,
> Bev Christian
> Research in Motion
>
> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: October 24, 2001 6:21 AM
> To: [log in to unmask]
> Subject: Re: [TN] Antw: [TN] exposing intermetallic on BGA pads...
>
>
> Guenter,
>
> I cannot believe how much I am learning every minute about
> soldering and all
> comprising it. Not at all being negative or contrary, I must have ruined
> thousands of solder joints in my long life in this business
> notwithstanding
> all the rework I've done and taught others.
>
> All I've ever been taught, done, and taught others is to remove
> the solder,
> with whatever means that works without damaging pads or board materials,
> then print paste, place components, and reflow.
>
> I've never even heard of leaving on solder or removing intermetallics -
> especially with a glass brush. I finished my last contract, seemingly
> successfully, two months ago. Can the world and all its "wonderful"
> soldering technology all of a sudden be passing me by in such a
> short time?
>
> Jeez, a glass brush. Thanks again Guenter, but I must need more help than
> even you, Bob Willis, or all other experts can give.
>
> Earl
>
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Date: Wed, 24 Oct 2001 18:53:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Trimming Leads.(IPC-A-610)
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I believe I miss used the word "Qualify".
I think we agree.
"In order for the user to apply and use the content of this document
(IPC-A-610), the assembly/product should comply with other existing IPC
requirement, such as IPC-SM-782, IPC-2221, IPC-6011 and IPC-A-600. If the
assembly does not comply with these or equivalent requirement, then the
acceptance criteria needs to be defined between the customer and supplier."
(The 610 acceptance criteria may not apply).
"For a more complete understanding of this document's recommendations and
requirements, one may use this document in conjunction with IPC-HDBK-001 and
J-STD-001."
The MIL-Q-2000 paradigm is dead. Process, Process, Process. The J-STD-001
makes allowance for risk associated with Class 1 and Class 2 products.
If I was a salesman I would proclaim IPC-A-610 acceptability
If I was a buyer I would demand J-STD-001 compliance.
If I was an investor I would seek companies with knowledge of the
difference.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Sauer, Steven T.
> Sent: Tuesday, October 23, 2001 8:51 AM
> To: [log in to unmask]
> Subject: Re: [TN] Trimming Leads...
>
>
> I can't resist Guy, with the all due respect, you struck a nerve
> and I could
> provide a long dissertation but I will only hit the highlights.
> For a true
> understanding of 610, read the scope and purpose, which are
> pretty much self
> explanatory.
> We all know what happens when you "asssume".
> Therefore, one should require conformance to the full gambit of specs/stds
> covering design, fabrication, documentation, assembly, acceptability and
> rework/repair dependent on product class. Conformance to these documents
> does not guarantee an acceptable product nor does it "qualify" a product.
> These documents minimize the risk of attaining an acceptable, reliable,
> fieldable product. ("...it sure looked good, I got the C of C and all the
> other paperwork, but I don't understand how it smoked after I turned it
> on...")
> To "qualify" the product is another subject unrelated to this topic. But,
> it all depends on how much the user is willing to pay and how
> well the user
> defines the product requirements.
> I believe you would be hard pressed in the real world to have class 1
> product and some class 2 product manufacturers buy into your logic. These
> mfr's rely on the end product acceptability (does it look good enough)
> requirements of 610 and use best manufacturing practices to achieve that
> end.
>
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Date: Wed, 24 Oct 2001 19:29:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Bev! To quote Doug Paul's standard phrase "It depends"! There are quite
a number of reference books I can put my hands on which list what the
tin/nickel intermetallic phase thickness will be depending on the time and
temperature it was either i) formed (initial formation, e.g. at molten
temperatures) or ii) grown (secondary formation, e.g. at temperature
exposure such as baking). I can give you a thickness value for a specific
condition. Is that what you want? Or is your question really focused on how
thick tin/nickel intermetallic phase can be tolerated before the
reliability is impacted?
This should be a fun metallurgical discussion!
Dave Hillman
Rockwell Collins
[log in to unmask]
Bev Christian <[log in to unmask]>@ipc.org> on 10/24/2001 02:39:20 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Tin/gold Intermetallic
OK, the last one was fun. Let's see what I can "provoke" this time!
There are standards for gold thickness for ENIG, "rules" for the amount of
gold in tin/lead solder joints (~4% for tensile, ~2% for shear), but I have
not found, looking into the TechNet archives or in J. Hwang's or Rahn's or
Manko's books I don't have the Wassink et al book ;( ), what is the range
of acceptable/expected intermetallic thickness for tin/nickel
intermetallic.
I would appreciate your input - any references and results seen in your own
work. Let the discussion begin.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: October 24, 2001 6:21 AM
To: [log in to unmask]
Subject: Re: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Guenter,
I cannot believe how much I am learning every minute about soldering and
all
comprising it. Not at all being negative or contrary, I must have ruined
thousands of solder joints in my long life in this business notwithstanding
all the rework I've done and taught others.
All I've ever been taught, done, and taught others is to remove the solder,
with whatever means that works without damaging pads or board materials,
then print paste, place components, and reflow.
I've never even heard of leaving on solder or removing intermetallics -
especially with a glass brush. I finished my last contract, seemingly
successfully, two months ago. Can the world and all its "wonderful"
soldering technology all of a sudden be passing me by in such a short time?
Jeez, a glass brush. Thanks again Guenter, but I must need more help than
even you, Bob Willis, or all other experts can give.
Earl
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Date: Thu, 25 Oct 2001 00:49:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 10/24/01 1:45:52 PM Pacific Daylight Time,
[log in to unmask] writes:
> I cannot believe a man of your stature asking such a question. Incredible!
There is a VERY old joke about a very successful fighter pilot, who, after
shooting down many planes on a mission over the Pacific Ocean, and then
running out of fuel, coasts to a landing on an aircraft carrier, without
realizing that it is the wrong side's aircraft carrier....and the
announcement he hears after sliding back the plane canopy applies to your
answer above...
"You make only one small mistake Yankee flyboy".....
"bchristian" is, I suspect, very probably VERY female....
And I have made this same error when addressing a customer, where he mistake
was not merely embarrassing, BUT COSTLY...
Rudy Sedlak
RD Chemical Company
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Date: Thu, 25 Oct 2001 01:03:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
Well, dumb ass me! Having landed on decks of many wrong aircraft carriers
how could I be surprised an a mistake like this. I'm really not gender
biased but after having conversations via email with Bev a few times, I just
got this screwed up too. No wonder I've had such interesting times in my
personal life. How was I supposed to know it was a female impersonator's bar?
My appologies to Bev and to anyone else who may be offended or, for that
matter, anyTHING wrong upon which I may have landed. I just look at us all
as equals as far as gender goes on this forum. Political correctness seems
to have left me in these times as well. Plus, as I said not long ago, my
sense of humor, either concerning my first comment on this subject to Bev or
anything else lately, seems to have lost a lot recently. I'm considering
straightening up and flying right while keeping my nose down in the turns.
Earl Moon
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Date: Thu, 25 Oct 2001 07:53:00 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
Content-Type: text/plain
Hi All,
The easiest way to think of this is not the use of a complicated formula,
but the simple application of percentage.
In the example below, the total weight of tin plus lead is 1500 pounds,
61.9% of which is tin. Hence there are 928.5 pounds of tin.
Add 45 pounds of tin, the total weight is now 1545 pounds of which, 973.5
pounds is tin. Work out the new percentage of the new total weight and you
get 63%.
Ahah, I hear you ask, how do you get to 45 pounds in the first place? Well,
just plug a few numbers into the percentage calculations and see which
direction it takes you.
The main thing to remember is that you add the tin addition to the total
weight as well as the tin content when working out the new percentage.
Hope this helps
Regards
Eric Dawson
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Wednesday, October 24, 2001 4:19 PM
> To: [log in to unmask]
> Subject: Re: [TN] Adjusting the alloy composition in the solderpot
>
> Hi Daan!
>
> I had that happen to me back in May of this year. Our analysis came back
> and we were at 61.9%. On my analysis sheet, it was recommended to add
> 3-lbs of pure tin for every 100-lbs of solder to bring the pot back back
> to a nominal 63%...
>
> I'm no metallurgist, nor am I a good mathematician (I think everybody on
> the TechNet knows that...hehehe). But we have a 1500-lb pot, and I put
> 45-lbs. of pure tin in as recommended, the next sample after that we were
> dead-on 63%...
>
> Maybe somebody better at math than me can decipher a formula from that...
>
> -Steve Gregory-
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Date: Thu, 25 Oct 2001 10:36:09 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Here's an interesting thought:
If we ask all the component manufacturers (incl. bare boards) to use
pure tin for their lead coatings etc., instead of tin/lead, this would
a) satisfy the lead-free guys
b) help keep the proportions right in the solder pot
Right?
Brian
"d. terstegge" wrote:
>
> Hi Technet,
>
> I just received an analyses report for our solder bath composition, and my Sn level is at 61.5 percent instead of the nominal 63 percent. This is at the edge of the J-STD-001C specification, so I'll have to add some pure tin to the pot.
> Last time was many years ago, and unfortunately I forgot the formula for calculating the amount of tin to add.
> It can't be that difficult, but I thought it would be quicker to ask.
>
> Thanks,
>
> Daan Terstegge
> SMT Centre
> Thales Communications
> Unclassified mail
> Personal Website: http://www.smtinfo.net
>
> ---------------------------------------------------------------------------------
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Date: Thu, 25 Oct 2001 02:58:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
Ah Brian, how you do stir the pot! Nothing can be that simple, especially
coming from you.
Enjoy,
Earl
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Date: Thu, 25 Oct 2001 08:59:55 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
In-Reply-To: <[log in to unmask]>
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At 63% notional tin content there should be 63 #/kg of Sn for every 100 #/kg
of solder. A ratio of 63/37=1.7
At 61.5% actual tin content there is only 61.5 #/kg of Sn, or 38.5kg Pb.
Therefore to restore the ratio you need 38.5 x 1.7 = 65.45, less the 61.5
you already have = 4#/kg for every #/kg of pot capacity.
Tin depletes in wave soldering as it is the more active of the two
constituents and therefore tends to get used quicker and oxidise faster etc
compared to lead.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Scott Kauling
Sent: Wednesday, October 24, 2001 2:59 PM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Daan
I do not have the formula, sorry. I would lean on your solder supplier to
help you.
Have you determined a root cause for the Sn levels to decrease? I was
wondering because, we are beginning to use white tin for a final finish.
Scott Kauling
-----Original Message-----
From: d. terstegge [SMTP:[log in to unmask]]
Sent: Wednesday, October 24, 2001 9:29 AM
To: [log in to unmask]
Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Thu, 25 Oct 2001 06:44:25 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Rudy
I hate to tell you - but having met Bev at Apex last year and shaken HIS =
hand... =20
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 10/25/01 01:49AM >>>
In a message dated 10/24/01 1:45:52 PM Pacific Daylight Time,
[log in to unmask] writes:
> I cannot believe a man of your stature asking such a question. Incredible=
!
There is a VERY old joke about a very successful fighter pilot, who, after
shooting down many planes on a mission over the Pacific Ocean, and then
running out of fuel, coasts to a landing on an aircraft carrier, without
realizing that it is the wrong side's aircraft carrier....and the
announcement he hears after sliding back the plane canopy applies to your
answer above...
"You make only one small mistake Yankee flyboy".....
"bchristian" is, I suspect, very probably VERY female....
And I have made this same error when addressing a customer, where he =
mistake
was not merely embarrassing, BUT COSTLY...
Rudy Sedlak
RD Chemical Company
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Date: Thu, 25 Oct 2001 07:39:57 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
MIME-Version: 1.0
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In a message dated 10/25/01 3:46:40 AM Pacific Daylight Time,
[log in to unmask] writes:
> Rudy
> I hate to tell you - but having met Bev at Apex last year and shaken HIS
> hand...
>
Did I fall on my sword again????
Rudy
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Date: Thu, 25 Oct 2001 07:52:36 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
MIME-Version: 1.0
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:) Thank you Graham. And Rudy, it won't cost you a dime.
Anyway, I think I know a lot less than people give me credit for. In the
scientific realm I am may know a lot about vermiculite and some of the more
esoteric parts of fluorine chemistry, but I still have a whole pile to learn
in our industry.
I was referring to what people were expecting in terms of a joint reflowed
once or twice. And, yes, Dave, I would like to know if there is an upper
limit that is deemed "unreliable". I expect the answer to the latter to be
fuzzy, but not the former.
regards,
Mr. Christian
Research in Motion
-----Original Message-----
From: Graham Collins [mailto:[log in to unmask]]
Sent: October 25, 2001 6:44 AM
To: [log in to unmask]
Subject: Re: [TN] Tin/gold Intermetallic
Rudy
I hate to tell you - but having met Bev at Apex last year and shaken HIS
hand...
regards
Graham Collins
Process Engineer,
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 10/25/01 01:49AM >>>
In a message dated 10/24/01 1:45:52 PM Pacific Daylight Time,
[log in to unmask] writes:
> I cannot believe a man of your stature asking such a question. Incredible!
There is a VERY old joke about a very successful fighter pilot, who, after
shooting down many planes on a mission over the Pacific Ocean, and then
running out of fuel, coasts to a landing on an aircraft carrier, without
realizing that it is the wrong side's aircraft carrier....and the
announcement he hears after sliding back the plane canopy applies to your
answer above...
"You make only one small mistake Yankee flyboy".....
"bchristian" is, I suspect, very probably VERY female....
And I have made this same error when addressing a customer, where he mistake
was not merely embarrassing, BUT COSTLY...
Rudy Sedlak
RD Chemical Company
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Date: Thu, 25 Oct 2001 14:12:53 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
MIME-Version: 1.0
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Hi Earl,
have to second your thoughts on that one. Either I missed something =
(must
have been some power nap during the lesson) or it wasn=B4t known at =
that time
when I took ym courses.=20
Was just checking with our "solder slaves" just having attended a =
solder
course according to MIL- and ESA-standard and that wasn=B4t in there as =
well.
So, I do not doubt that you got no wetting with IMC=B4s but it seems =
that we
haven=B4t managed to get down to it with our methods or haven=B4t =
noticed it
cause the spots of IMC at the surface were that tiny that wetting =
around
those spots looked good enough for us but still lead to "weaker?" =
joints
after rework.
But I have to admit that in some rare cases when wetting wasn=B4t =
possible for
what reason ever we worked our way through the material until we met =
some
virgin copper, et viol=E1, soldered to that.=20
Who knows? , we just believed that it should be done the way they =
teached us
and we teached others. The whole "dilemma" we are in is that we can=B4t =
check
the joints after we=B4ve done our work without destroying them to see =
what
really happend so we have to trust our methods. If not we would die =
sooner
or later of "permanent doubt stress" or bad conscience regarding our =
work.
Have a good time ... and .. hmmmh ... don=B4t ge too confused about =
Bev=B4s
gender changing mentality ;-)
Wolfgang=20
-----Urspr=FCngliche Nachricht-----
Von: Earl Moon [mailto:[log in to unmask]]
Gesendet am: Mittwoch, 24. Oktober 2001 12:21
An: [log in to unmask]
Betreff: Re: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Guenter,
I cannot believe how much I am learning every minute about soldering =
and all
comprising it. Not at all being negative or contrary, I must have =
ruined
thousands of solder joints in my long life in this business =
notwithstanding
all the rework I've done and taught others.
All I've ever been taught, done, and taught others is to remove the =
solder,
with whatever means that works without damaging pads or board =
materials,
then print paste, place components, and reflow.
I've never even heard of leaving on solder or removing intermetallics -
especially with a glass brush. I finished my last contract, seemingly
successfully, two months ago. Can the world and all its "wonderful"
soldering technology all of a sudden be passing me by in such a short =
time?
Jeez, a glass brush. Thanks again Guenter, but I must need more help =
than
even you, Bob Willis, or all other experts can give.
Earl
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Date: Thu, 25 Oct 2001 09:37:20 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "S. Miller" <[log in to unmask]>
Subject: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_77.1d150e60.29096f90_boundary"
--part1_77.1d150e60.29096f90_boundary
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Content-Transfer-Encoding: 7bit
To All,
My company has been asked to tender a bid for an assembly that includes a 8
LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and any
recommendations would be truly appreciated.
--part1_77.1d150e60.29096f90_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>To All,
<BR>
<BR>My company has been asked to tender a bid for an assembly that includes a 8 LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
<BR>
<BR>I am desperately trying to find a supplier that can provide the same and any recommendations would be truly appreciated. </FONT></HTML>
--part1_77.1d150e60.29096f90_boundary--
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Date: Thu, 25 Oct 2001 08:33:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Tin/gold Intermetallic
Actually, someone set me straight about Bev being a guy several years ago,
after my having referred to him as a her several times. I liked you jab and
story so much I went along with it as I really relate to the carrier thing
but not as some heroic fighter ace. I was hoping someone would come along
and set us straignt. Really was hoping it would be Bev while please ending
my interest in what Bev is short for or not. I did learn a lesson though and
shall refer to everyone as a person from now on. Gender neutral around here
for me.
On a technical side, glad some person asked the question Bev did about gold
IMC stuff. Same question applies to all other surface finishes, right?
Earl
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Date: Thu, 25 Oct 2001 08:45:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: BGA Component Baking - Plastic Body
BGA Guru's,
We're doing a big project that requires removal/replacement of several
hundred plastic BGA components. After removal we'll be reballing the BGA's
and then reinstalling them. These are new builds, they're not coming back
from the field.
Who knows what J-STD-20, or any other reference, says about prebaking
temp/time to eliminate possible moisture problems in the components or
boards prior to initial removal? Removed parts will be stored in a
desiccant chamber before and after reballing. Do we need to bake these
parts again prior to installation? Do ya'all normally bake new build boards
in this situation?
Thanks for you recommendations.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 25 Oct 2001 08:46:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
X-To: Wolfgang Busko <[log in to unmask]>
Good to see from you again Wolfgang and thanks for the support concerning my
confusion on this subject. The whole subject certainly demands responsible,
well educated, knowledgeable scientists go forward studying and writing
about findings. It's, as you said, maybe going by just a little to fast for
a simple PERSON, like myself though that doesn't make a hill of beans to most.
Really was hoping to see more from Guenter on this subject. I know how busy
he is but he dropped this little bomb on some of us. Maybe, again as you
said, the whole process is so forgiving, we need not be so concerned, or
not. 5,000 years and not a single failure!
Can't get over the glass brush thing though. Must be someone else having an
issue or, for greater input, using them as required (as clearly indicated in
clearly defined procedures) - whatever that means. Do we use it how, when,
where, etc. and what is the acceptance criteria when finished - real thin
solder layer, some exposed copper, etc.? It must be in 001. That's where
I'll start.
Earl
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Date: Thu, 25 Oct 2001 14:53:16 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
In-Reply-To: <000d01c15d2b$097209d0$f502a8c0@ukomfenner>
MIME-Version: 1.0
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Whoops: for those that didn't spot it, answer is 4 pounds/kilos for every
100 pounds/kilos
Best regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Fenner
Sent: Thursday, October 25, 2001 9:00 AM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
At 63% notional tin content there should be 63 #/kg of Sn for every 100 #/kg
of solder. A ratio of 63/37=1.7
At 61.5% actual tin content there is only 61.5 #/kg of Sn, or 38.5kg Pb.
Therefore to restore the ratio you need 38.5 x 1.7 = 65.45, less the 61.5
you already have = 4#/kg for every #/kg of pot capacity.
Tin depletes in wave soldering as it is the more active of the two
constituents and therefore tends to get used quicker and oxidise faster etc
compared to lead.
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Scott Kauling
Sent: Wednesday, October 24, 2001 2:59 PM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Daan
I do not have the formula, sorry. I would lean on your solder supplier to
help you.
Have you determined a root cause for the Sn levels to decrease? I was
wondering because, we are beginning to use white tin for a final finish.
Scott Kauling
-----Original Message-----
From: d. terstegge [SMTP:[log in to unmask]]
Sent: Wednesday, October 24, 2001 9:29 AM
To: [log in to unmask]
Subject: [TN] Adjusting the alloy composition in the solderpot
Hi Technet,
I just received an analyses report for our solder bath composition, and my
Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
It can't be that difficult, but I thought it would be quicker to ask.
Thanks,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Thu, 25 Oct 2001 09:59:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Malewicz Wesley <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I am currently using Litton Advanced Circuitry in Springfield, Missouri for
6oz final finish and have been very satisfied. There main switchboard
number is 417-829-5200.
I hope this will help you,
Wes
SIEMENS
Wes Malewicz
Printed Circuit Development Supervisor
Siemens Medical Solutions USA, Inc.
16 Electronics Ave
Danvers, MA. 01923-1011
U.S.A.
Tele: 978.907.7776
FAX: 978.907.7713
email: [log in to unmask]
-----Original Message-----
From: S. Miller [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 9:37 AM
To: [log in to unmask]
Subject: [TN] In Search of Thick Cu PCB Manufacturer
To All,
My company has been asked to tender a bid for an assembly that includes a 8
LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and any
recommendations would be truly appreciated.
---------------------------------------------------------------------------------
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Date: Thu, 25 Oct 2001 08:55:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
X-To: "S. Miller" <[log in to unmask]>
Most any good MLB house can do the 3 oz. internals. It's just you're going
to have a lot of interesting things happening on the outers. The etch factor
and resulting trace profile (z axis view) would be very interesting even if
you could stack enough photo etch resist that high.
Used to do thousands of 8 oz outers for a MIL program for a company in Salt
Lake I can no longer remember the name but for Wendell Giles, the buyer, and
Arnie Smith, his boss. Because I said yes to the order, and they gave it to
us (I do remember this company's name), Wendell, Arnie, and I got new
offices next to the flusher.
MoonMan
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Date: Thu, 25 Oct 2001 09:13:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0004_01C15D35.5AAB2520"
This is a multi-part message in MIME format.
------=_NextPart_000_0004_01C15D35.5AAB2520
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An approximate board dimension, annual volume and fabrication specification
(IPC Class 2, Class 3 or Mil Spec) would help those making a recommendation.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of S. Miller
Sent: Thursday, October 25, 2001 8:37 AM
To: [log in to unmask]
Subject: [TN] In Search of Thick Cu PCB Manufacturer
To All,
My company has been asked to tender a bid for an assembly that includes a 8
LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and any
recommendations would be truly appreciated.
------=_NextPart_000_0004_01C15D35.5AAB2520
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<BODY>
<DIV><SPAN class=3D470201114-25102001><FONT face=3DArial color=3D#0000ff =
size=3D2>An=20
approximate board dimension, annual volume and fabrication=20
specification (IPC Class 2, Class 3 or Mil Spec) would help those making =
a=20
recommendation.</FONT></SPAN></DIV>
<DIV><SPAN class=3D470201114-25102001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D470201114-25102001><FONT face=3DArial color=3D#0000ff =
size=3D2>Don=20
Vischulis</FONT></SPAN></DIV>
<DIV><SPAN class=3D470201114-25102001></SPAN> </DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>S. Miller<BR><B>Sent:</B> =
Thursday,=20
October 25, 2001 8:37 AM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> [TN]=20
In Search of Thick Cu PCB Manufacturer<BR><BR></FONT></DIV><FONT=20
face=3Darial,helvetica><FONT size=3D2>To All, <BR><BR>My company has =
been asked to=20
tender a bid for an assembly that includes a 8 LYR PCB with 3 oz Cu =
(internal)=20
and 4 oz (external) plating. <BR><BR>I am desperately trying to =
find a=20
supplier that can provide the same and any recommendations would be =
truly=20
appreciated. </FONT> </FONT></BODY></HTML>
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Date: Thu, 25 Oct 2001 09:10:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
X-To: Jeff Ferry <[log in to unmask]>
Obviously a serious issue. Never did hundreds - only a few. Followed the
same rules taking off moisture sensitive components, for obvious reasons, as
replacing them.
Earl Moon
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Date: Thu, 25 Oct 2001 10:20:02 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
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This is a multi-part message in MIME format.
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It's been a few years, but I believe that we have used STACI (Saisha
Technology and Circuits Intenational, L.C). for a similar assy.
Phone:954-623-3100. E-MAIL: STACI [log in to unmask] . They are rep'd by "BOARDS,
INC". Hope it helps. Good Luck. --Dean
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of S. Miller
Sent: Thursday, October 25, 2001 9:37 AM
To: [log in to unmask]
Subject: [TN] In Search of Thick Cu PCB Manufacturer
To All,
My company has been asked to tender a bid for an assembly that includes
a 8 LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and
any recommendations would be truly appreciated.
------=_NextPart_000_0024_01C15D3E.9C374D30
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV><SPAN class=3D394091614-25102001><FONT color=3D#0000ff face=3DArial =
size=3D2>It's=20
been a few years, but I believe that we have used STACI (Saisha =
Technology and=20
Circuits Intenational, L.C). for a similar assy. =
Phone:954-623-3100. =20
E-MAIL: STACI <A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> . =
They are=20
rep'd by "BOARDS, INC". Hope it helps. Good=20
Luck. --Dean</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> S. =
Miller<BR><B>Sent:</B>=20
Thursday, October 25, 2001 9:37 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] In Search of Thick Cu PCB=20
Manufacturer<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>To=20
All, <BR><BR>My company has been asked to tender a bid for an =
assembly that=20
includes a 8 LYR PCB with 3 oz Cu (internal) and 4 oz (external) =
plating.=20
<BR><BR>I am desperately trying to find a supplier that can =
provide=20
the same and any recommendations would be truly appreciated. =
</FONT>=20
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 25 Oct 2001 09:25:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard W Hinebaugh <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
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I second that idea! They have done well for us.
RICH HINEBAUGH
ECAT (ELECTRONIC ASSEMBLY AND TEST) COST ENGINEER
OUTSOURCED STORAGE & COST ENGINEERING
PHONE 507-253-3470,TIE LINE 553-3470,FAX 507-253-2148
3055 41st ST NW
DEPT. 3A6,BLDG 664-1,E103
ROCHESTER,MN 55901
EMAIL: [log in to unmask]
What do you want to see when you look back on your life?
Malewicz Wesley
<[log in to unmask] To: [log in to unmask]
EMENS.COM> cc:
Sent by: TechNet Subject: Re: [TN] In Search of Thick Cu PCB Manufacturer
<[log in to unmask]>
10/25/01 08:59 AM
Please respond to "TechNet
E-Mail Forum."
Hi,
I am currently using Litton Advanced Circuitry in Springfield, Missouri for
6oz final finish and have been very satisfied. There main switchboard
number is 417-829-5200.
I hope this will help you,
Wes
SIEMENS
Wes Malewicz
Printed Circuit Development Supervisor
Siemens Medical Solutions USA, Inc.
16 Electronics Ave
Danvers, MA. 01923-1011
U.S.A.
Tele: 978.907.7776
FAX: 978.907.7713
email: [log in to unmask]
-----Original Message-----
From: S. Miller [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 9:37 AM
To: [log in to unmask]
Subject: [TN] In Search of Thick Cu PCB Manufacturer
To All,
My company has been asked to tender a bid for an assembly that includes a 8
LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and
any
recommendations would be truly appreciated.
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Date: Thu, 25 Oct 2001 17:42:59 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
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Be careful with your 3 oz internals. Unless the build-up is carefully
controlled, with adequate quantities of resin (better still, buttercoat
the internals with resin before laying up), you are going to get voids
or, at least, electrical weakness in areas where there are conductor
spacings from more than 1 internal superimposed. Been there, seen it,
boom!
Brian
"S. Miller" wrote:
>
> To All,
>
> My company has been asked to tender a bid for an assembly that
> includes a 8 LYR PCB with 3 oz Cu (internal) and 4 oz (external)
> plating.
>
> I am desperately trying to find a supplier that can provide the same
> and any recommendations would be truly appreciated.
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Date: Thu, 25 Oct 2001 10:39:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Forrester <[log in to unmask]>
Subject: Temporary Burn-In Ovens
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
We will shortly performing a major overhaul of our burn-in chamber. I
have been asked to rent temporary Burn-in oven(s) to carry us through
the overhaul period. Our units are typically 24"X36"X12" and are cycled
between 0 and 45 deg C. Does anyone know of a company that rents/leases
burn-in chambers? My plan would be to wire up a tractor trailer to house
the
required oven space during the overhaul. Thank you in advance.
Best Regards,
Michael Forrester
Sr. Manufacturing Engineer
LeCroy Corporation
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Date: Thu, 25 Oct 2001 09:37:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
X-To: "Brian E." <[log in to unmask]>
Point well taken Brian. However, I have done many 10, 5, and other oz.,
inclucing 10 mil CIC, inners with no trouble with certain provisions. As you
said, high resin to glass ratio prepregs are required to "fill" during
relamination.
I know the outers can be done when used as heat sinks or other "coarse"
features. It's the features that need attention. Obviously, fine line traces
are not part of the equation.
MoonMan
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Date: Thu, 25 Oct 2001 11:11:11 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: White Residue...
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Hi all!
Rudy, don't feel so bad, I made the same mistake a few years ago, boy was my
face red!
Anyways, I'm trying to change to a less expensive Kyzen formula to clean our
RMA residues. We use a Alpha 615-25 flux in our wave. We've been using Kyzen
Aquanox XJN, and haven't had any problems except for the price, it's gone up
to the point that we really need to consider something cheaper. We run it in
a Electrovert MCS1000 at the middle of the recommended concentration (25%),
with the wash and rinse temperatures at 150 F., the wash cycle is 6-minutes,
and the rinse is 4-minutes, with a couple of air knife passes between the
wash and rinse cycles, and then another air knife cycle at the end to dry
everything off.
We've tried some samples of LONOX 5005 because of it's price, and were told
that we can run it at much lower concentrations (10-15%). So we washed some
boards,
any got the dreaded white residues. We would have slight residues with the
XJN but they really aren't bad, we (our inspectors) could live with them. But
what we are seeing after the LONOX wash isn't something that can be
tolerated. They are non-ionic by the way, I checked. They can also be removed
by brushing them with a Q-tip. Check the pictures out:
http://stevezeva.homestead.com/index.html
Any ideas? Any of you experience this before? I'm gonna call Kyzen, but I
thought I'd get all ya'lls opinion too...
Thanks!
-Steve Gregory-
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi all!
<BR>
<BR>Rudy, don't feel so bad, I made the same mistake a few years ago, boy was my face red!
<BR>
<BR>Anyways, I'm trying to change to a less expensive Kyzen formula to clean our RMA residues. We use a Alpha 615-25 flux in our wave. We've been using Kyzen Aquanox XJN, and haven't had any problems except for the price, it's gone up to the point that we really need to consider something cheaper. We run it in a Electrovert MCS1000 at the middle of the recommended concentration (25%), with the wash and rinse temperatures at 150 F., the wash cycle is 6-minutes, and the rinse is 4-minutes, with a couple of air knife passes between the wash and rinse cycles, and then another air knife cycle at the end to dry everything off.
<BR>
<BR>We've tried some samples of LONOX 5005 because of it's price, and were told that we can run it at much lower concentrations (10-15%). So we washed some boards,
<BR>any got the dreaded white residues. We would have slight residues with the XJN but they really aren't bad, we (our inspectors) could live with them. But what we are seeing after the LONOX wash isn't something that can be tolerated. They are non-ionic by the way, I checked. They can also be removed by brushing them with a Q-tip. Check the pictures out:
<BR>
<BR>http://stevezeva.homestead.com/index.html
<BR>
<BR>Any ideas? Any of you experience this before? I'm gonna call Kyzen, but I thought I'd get all ya'lls opinion too...
<BR>
<BR>Thanks!
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_63.aa68b1.2909858f_boundary--
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Date: Thu, 25 Oct 2001 11:44:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Innerlayer shorts - predictions vs. reality
MIME-Version: 1.0
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Good Morning All!
I think I've got a case of folks comparing apples to bananas.
I'm trying to predict % defects due to inner layer shorts and compare across
part numbers. Folks are looking at one part number and saying, "12 layer
board with 7% inner layer shorts (of the ones tested) and looking at another
part number - 24 layer board has 18% inner layer shorts. You are screwing
up more on the big $$$ board - fix it!" Shouldn't inner layer shorts be a
linear or geometric relationship?
For example, take a 10 layer board, it has 5 signal layers (50-50 signal &
plane). Each signal layer will have a certain surface area where traces are
packed close enough together that a sliver of metal could cause a short. At
electrical test I fail a certain percentage of boards due to shorts - say
10%. Now take a 20 layer board and say it doubles the surface area that
could have a short. The failures due to inner layer shorts should be double
the 10 layer board or 20%. If the boards were manufactured at the same time
the process should, on average, contribute the same number of shorts/area to
each.
Inner layer short defects come from multiple sources that produces a finely
boned fish - metallic contamination, poor IL etching, poor IL
imaging/development, missed in IL AOI, equipment, material, method, people -
ad nausem. . . And for now I'm ignoring test escapes. The inner layer short
generation fluctuates over time but has some average value per area. So I
propose a simple equation:
Inner Layer Defects = (average # inner layer shorts/surface area) (total
critical surface area)
Looking at the artwork should get me the critical surface area, the inner
layer defects we know from Electrical Test so a graph of defects vs. surface
area should get me the shorts/area for the total process, no? Then I can
say when the process has changed versus merely a higher tech board being
processed.
Anybody hit this wall before? Is there a flaw in my logic?
Hans
PS. If memory serves, I remember Bev mentioning Technetters' lack of gender
identification skills at that "Stump the Chumps" session we had a few years
ago. And I can relate - every once in a while people see the middle name
(Michel) and think "must be a groovy chick".
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
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Date: Thu, 25 Oct 2001 10:37:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brad A. Smith" <[log in to unmask]>
Subject: Reflow profiling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello All,
I am with a low volume, frequent changeover contract manufacturer. We are
trying to implement a system where we profile the first assembly of every
new run through our reflow oven. We are currently using high temperature
solder for profiling. If we start to use the high temp solder for this, we
will have to scrap the assemblies. Does anyone have any suggestions for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Thu, 25 Oct 2001 11:55:23 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Laser trimming of resistors
MIME-Version: 1.0
Content-Type: text/plain
Hi Technos,
we are advancing in exploring new technologies. Some time ago I tapped your
wisdom for info on flex circuits, now I have a better one.
What is "laser trimming of resistors"? According to the small research I
did, it's related to thick films. Is that true? What should I read on this,
starting with some on-line resources?
Keeping in mind that we are assemblers, not board manufacturers, how is this
trimming related to SMT assembly, what equipment would do it (at what cost),
implementation issues, etc.
Best regards,
Ioan
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Date: Thu, 25 Oct 2001 11:01:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
X-To: Wolfgang Busko <[log in to unmask]>
Just been talking with someone also much respected in this field. The
following is my response to his answere:
Besides the glass brush talked about in other discussions, my biggest
concerns are about fine pitch and BGA device types and the solder
termination area topography required (flat)to effect placement, continued
alignment, and subsequent reflow and "acceptable" solder joint formation -
not only as first required but for rework.
As you know and have observed many times, once device removal is effected,
the solder left is very uneven, to say the least. This, again as you know,
is why we carefully wick off, or otherwise remove the solder left after the
component removal process.
This, then, is the dilemma as I see it. In your terms, we now expose an IMC
layer after the solder removal process, to whatever extent, preventing
solder "wetting" in some areas not quantifiable. I guess, this is a random
occurrence (where and how much IMC) is left. Therefore, doesn't this point
to sh luck to again effect "acceptable solder joints or is it of no
consequence - for the most part as Wolfgang said.
Earl
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Date: Thu, 25 Oct 2001 11:11:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Laser trimming of resistors
X-To: Ioan Tempea <[log in to unmask]>
In the early thick film days, resistors were designed using one mil squares
and often ended up in a variety of shapes as serpentine, or? In those days,
we used air abraiding techniques (sand blasting) to "trim" the resistors to
the correct value after the resistor ink was screened and cured on the
substrate. Much depended on the thermal coefficient of expansion of the ink
after cure and after being subjected to many tests.
Not much has changed in the process, from design through acceptance, but for
markedly improved inks that are much more stable, and the laser trimming
process. Where this applies in some PCB designs is when using resistive
inner layers as "Omega" ply types. In some instances the same concept is
used to trim the resistors to their intended value and required tolerances.
MoonMan
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Date: Thu, 25 Oct 2001 11:15:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Laser trimming of resistors
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_63398DD2.10711C65"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_63398DD2.10711C65
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Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
I know of a local manufacturer who actually does it. It is an amazing =
process. Contact me offline and I'll see if I can get you in contact with =
a process engineer over there.=20
Kathy=20
--=_63398DD2.10711C65
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I know of a local manufacturer who actually does it. It is an amazing
process. Contact me offline and I'll see if I can get you in contact with
a process engineer over there. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 25 Oct 2001 11:20:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Reflow profiling
X-To: "Bradley A. Smith" <[log in to unmask]>
I don't get all your doing or, for that matter, all anyone else is doing. At
HP, a few years ago, we averaged 15 change overs a day on 10 lines with
seldom more than 50 assemblies each lot/run. To put this in perspective, we
had 1,500 active part numbers going through the shop with requirements for
nearly 20 million placements/month with every type component imaginable at
the time. We had only three reflow profiles, with two pastes, and they did
the job but for exceptions as experiments.
Doubt this answers your question but it is a trip down memory lane for me.
Sure enjoyed the experience and the trip.
Enjoy,
MoonMan
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Date: Thu, 25 Oct 2001 12:37:42 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Brad,
Why not use a temperature datalogger, kapton tape and some long thermocouple
wire?
There are many sources but http://www.omega.com would be a great place to
start.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Brad A. Smith [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 11:37 AM
To: [log in to unmask]
Subject: [TN] Reflow profiling
Hello All,
I am with a low volume, frequent changeover contract manufacturer. We are
trying to implement a system where we profile the first assembly of every
new run through our reflow oven. We are currently using high temperature
solder for profiling. If we start to use the high temp solder for this, we
will have to scrap the assemblies. Does anyone have any suggestions for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Thu, 25 Oct 2001 12:41:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Alain Savard <[log in to unmask]>
Subject: Re: Innerlayer shorts - predictions vs. reality
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Hans,
You do not seem to account for spacing within the surface being looked at.
There is a substantial difference between boards with 10 mil spacing between
conductor traces and those with say 4 mils.
Another potential flaw is the length that traces run close to each other.
Even if 2 boards are allowed and use 5 mil spacing, if one uses it on 10% of
the layer and the other on only 2% you will get different yields.
My opinion only.
Have a nice day,
Alain Savard
QA-PCB
CAE Inc.
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 11:44 AM
To: [log in to unmask]
Subject: [TN] Innerlayer shorts - predictions vs. reality
Good Morning All!
I think I've got a case of folks comparing apples to bananas.
I'm trying to predict % defects due to inner layer shorts and compare across
part numbers. Folks are looking at one part number and saying, "12 layer
board with 7% inner layer shorts (of the ones tested) and looking at another
part number - 24 layer board has 18% inner layer shorts. You are screwing
up more on the big $$$ board - fix it!" Shouldn't inner layer shorts be a
linear or geometric relationship?
For example, take a 10 layer board, it has 5 signal layers (50-50 signal &
plane). Each signal layer will have a certain surface area where traces are
packed close enough together that a sliver of metal could cause a short. At
electrical test I fail a certain percentage of boards due to shorts - say
10%. Now take a 20 layer board and say it doubles the surface area that
could have a short. The failures due to inner layer shorts should be double
the 10 layer board or 20%. If the boards were manufactured at the same time
the process should, on average, contribute the same number of shorts/area to
each.
Inner layer short defects come from multiple sources that produces a finely
boned fish - metallic contamination, poor IL etching, poor IL
imaging/development, missed in IL AOI, equipment, material, method, people -
ad nausem. . . And for now I'm ignoring test escapes. The inner layer short
generation fluctuates over time but has some average value per area. So I
propose a simple equation:
Inner Layer Defects = (average # inner layer shorts/surface area) (total
critical surface area)
Looking at the artwork should get me the critical surface area, the inner
layer defects we know from Electrical Test so a graph of defects vs. surface
area should get me the shorts/area for the total process, no? Then I can
say when the process has changed versus merely a higher tech board being
processed.
Anybody hit this wall before? Is there a flaw in my logic?
Hans
PS. If memory serves, I remember Bev mentioning Technetters' lack of gender
identification skills at that "Stump the Chumps" session we had a few years
ago. And I can relate - every once in a while people see the middle name
(Michel) and think "must be a groovy chick".
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
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Date: Thu, 25 Oct 2001 09:44:31 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Elensky, Richard" <[log in to unmask]>
Subject: Re: Reflow profiling
X-To: "Brad A. Smith" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Unless it is a customer requirement to provide thermal profiles for each
lot, I don't understand the necessity to profile so frequently. Generally
speaking, I have always used just a few profiles for everything. These were
defined for different pastes or epoxies. As a new product came to the shop
floor, I would run a sample with the Datapaq to confirm the appropriate
thermal conditions and add that assembly to the list of assemblies used on
that profile.
Regarding the attachment issue, I would suggest the Sanders thermocouples
that clamp onto the edge of the board (Sold by ECD 1-800-323-4528 or Datapaq
508-988-9000) They are very accurate and require no attachment to the
device (solder, glue, tape). I had my set (8", 10", and 12") for several
years and used them for both reflow and wave solder applications, proving
they were quite robust.
Hope this helps,
Rich
Richard Elensky
Sr. Manufacturing Engineer
[log in to unmask] <mailto:[log in to unmask]>
Tel: 559-292-1111 x246
Fax: 559-292-9355
Dantel
2991 North Argyle Ave.
Fresno, CA, 93727
Visit our web site at:
http:// www.dantel.com <http://www.dantel.com>
----------
From: Brad A. Smith [SMTP:[log in to unmask]]
Sent: Thursday, October 25, 2001 8:37 AM
To: [log in to unmask]
Subject: [TN] Reflow profiling
Hello All,
I am with a low volume, frequent changeover contract manufacturer.
We are
trying to implement a system where we profile the first assembly of
every
new run through our reflow oven. We are currently using high
temperature
solder for profiling. If we start to use the high temp solder for
this, we
will have to scrap the assemblies. Does anyone have any suggestions
for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Thu, 25 Oct 2001 09:46:45 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Subject: Re: Reflow profiling
In-Reply-To: <DC11C7C72C2AD5119F520090279D31680E601B@NT_1>
MIME-Version: 1.0
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Brad,
Have you looked at some of the metal tapes that are available? We use an
aluminum one from KIC but I'm sure others have this as well. While it
doesn't quite emulate sticking the thermocouple in solder, the metal mass
when tape this to a solder joint does come pretty close for most profiling
purposes. In our process we do this on the first board out of the oven
which means that board sees a double reflow cycle. We haven't identified
any reliability issues with this but haven't done any long term failure
analysis.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Brad A. Smith
Sent: Thursday, October 25, 2001 8:37 AM
To: [log in to unmask]
Subject: [TN] Reflow profiling
Hello All,
I am with a low volume, frequent changeover contract manufacturer. We are
trying to implement a system where we profile the first assembly of every
new run through our reflow oven. We are currently using high temperature
solder for profiling. If we start to use the high temp solder for this, we
will have to scrap the assemblies. Does anyone have any suggestions for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Thu, 25 Oct 2001 12:50:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
Eric, Steve, et al,
I recommend going back to basic calculus and calculating the derivative of
fraction tin with respect to weight (mass) of tin.
Fraction tin = (Tin mass)/(Tin mass + Lead mass)
You will get (assuming you only want a small change in fraction tin, in the
range of, say, 0.03 or less)
Tin add = (Mass of pot) X (change desired in Fraction Tin)/(Fraction Lead)
On an unrelated matter, let me comment that a number of names like Shirley,
Beverly, and Vivian were used by men until the first half of the past
century. Over some time period, women largely took possession of them.
Lou Hart
-----Original Message-----
From: Eric Dawson [SMTP:[log in to unmask]]
Sent: Thursday, October 25, 2001 2:53 AM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Hi All,
The easiest way to think of this is not the use of a complicated formula,
but the simple application of percentage.
In the example below, the total weight of tin plus lead is 1500 pounds,
61.9% of which is tin. Hence there are 928.5 pounds of tin.
Add 45 pounds of tin, the total weight is now 1545 pounds of which, 973.5
pounds is tin. Work out the new percentage of the new total weight and you
get 63%.
Ahah, I hear you ask, how do you get to 45 pounds in the first place? Well,
just plug a few numbers into the percentage calculations and see which
direction it takes you.
The main thing to remember is that you add the tin addition to the total
weight as well as the tin content when working out the new percentage.
Hope this helps
Regards
Eric Dawson
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Date: Thu, 25 Oct 2001 09:54:26 -0700
Reply-To: Greg Jones <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Greg Jones <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Brad:
We recommend using aluminum tape to attach thermocouples. It is much easier
to use than high temp solder and completely nondestructive. There is a
paper posted on our website that discusses in depth the various means of
attaching thermocouples for profiling: A Comparison of Methods for
Attaching TCs to PCBs for Thermal Profiling,
which can be found at www.kicthermal.com /Library.
We also offer technology that can significantly reduce your changeover times
and improve your process, which I would be glad to discuss offline.
Greg Jones Ph.D.
Special Projects Manager
775.322.0158
KIC--Innovation That Works
www.kicthermal.com
----- Original Message -----
From: "Brad A. Smith" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 8:37 AM
Subject: [TN] Reflow profiling
> Hello All,
>
> I am with a low volume, frequent changeover contract manufacturer. We are
> trying to implement a system where we profile the first assembly of every
> new run through our reflow oven. We are currently using high temperature
> solder for profiling. If we start to use the high temp solder for this, we
> will have to scrap the assemblies. Does anyone have any suggestions for
> alternatives to high temp solder? Any suggestions would be greatly
> appreciated.
>
> Thank you,
> Brad Smith
> Process Technician
> Badger Electronics Co., Inc.
> (262)886-8800
> [log in to unmask]
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> the BODY (NOT the subject field): SIGNOFF Technet
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Technet NOMAIL
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
-------
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Date: Thu, 25 Oct 2001 10:03:45 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Butman <[log in to unmask]>
Subject: Re: Reflow profiling
In-Reply-To: <06CDC53D5997D411BDE9001083FDB9BC74D72D@COMSERVER>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
HI All,
I agree with Richard.
The site for the "Temprobe" is:
http://www.saunderstech.com/
Thanx
Bill Butman
--- "Elensky, Richard" <[log in to unmask]> wrote:
> Unless it is a customer requirement to provide
> thermal profiles for each
> lot, I don't understand the necessity to profile so
> frequently. Generally
> speaking, I have always used just a few profiles for
> everything. These were
> defined for different pastes or epoxies. As a new
> product came to the shop
> floor, I would run a sample with the Datapaq to
> confirm the appropriate
> thermal conditions and add that assembly to the list
> of assemblies used on
> that profile.
>
> Regarding the attachment issue, I would suggest the
> Sanders thermocouples
> that clamp onto the edge of the board (Sold by ECD
> 1-800-323-4528 or Datapaq
> 508-988-9000) They are very accurate and require no
> attachment to the
> device (solder, glue, tape). I had my set (8", 10",
> and 12") for several
> years and used them for both reflow and wave solder
> applications, proving
> they were quite robust.
>
> Hope this helps,
>
> Rich
>
> Richard Elensky
> Sr. Manufacturing Engineer
> [log in to unmask] <mailto:[log in to unmask]>
>
> Tel: 559-292-1111 x246
> Fax: 559-292-9355
>
> Dantel
> 2991 North Argyle Ave.
> Fresno, CA, 93727
> Visit our web site at:
> http:// www.dantel.com <http://www.dantel.com>
>
>
> ----------
> From: Brad A. Smith
> [SMTP:[log in to unmask]]
> Sent: Thursday, October 25, 2001 8:37 AM
> To: [log in to unmask]
> Subject: [TN] Reflow profiling
>
> Hello All,
>
> I am with a low volume, frequent changeover
> contract manufacturer.
> We are
> trying to implement a system where we
> profile the first assembly of
> every
> new run through our reflow oven. We are
> currently using high
> temperature
> solder for profiling. If we start to use the
> high temp solder for
> this, we
> will have to scrap the assemblies. Does
> anyone have any suggestions
> for
> alternatives to high temp solder? Any
> suggestions would be greatly
> appreciated.
>
> Thank you,
> Brad Smith
> Process Technician
> Badger Electronics Co., Inc.
> (262)886-8800
> [log in to unmask]
>
>
>
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Bill Butman
Circuit Technology Center
45 Research Drive
Haverhill, MA 01832
__________________________________________________
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Date: Thu, 25 Oct 2001 14:13:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles McMahon <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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VIKTRON of Stockton Cal. may be of help.
They routinely build boards with the copper wt's you seek.
If I can help please advise off line
Charlie McMahon
[log in to unmask]
"S. Miller" wrote:
>
> To All,
>
> My company has been asked to tender a bid for an assembly that
> includes a 8 LYR PCB with 3 oz Cu (internal) and 4 oz (external)
> plating.
>
> I am desperately trying to find a supplier that can provide the same
> and any recommendations would be truly appreciated.
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Date: Thu, 25 Oct 2001 14:22:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Laser trimming of resistors
In-Reply-To: <[log in to unmask]>
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Ioan:
If memory serves, Chicago Laser Systems is a manufacturer of laser trimming
equipment. When a resistor is printed, it is usually printed with a
slightly low value. When the resistor is trimmed (regardless of method),
the resistor is probed and its resistance is monitored before and after the
trimming process. In a passive trim process, the resistor's value is
adjusted by slicicng through part of the resistor with the laser to achieve
a predetermined value. In an active trim, the output of (for example) an op
amp is adjusting by trimming the bias resistors while the device is
operating to fine tune to the gain of the amplifier. The resistor initial
value must be closely controlled to maintain the width of the trimmed
resistor (read that power rating).
In the world of thick film, the resistors are in a glass matrix which is
"fired" around 800 C (I'm working from memory so don't flame me if the
temperature is off a little) which is obviously too hot for conventional
organic substrates. There are polymer thick film resistor materials, but
the downside to them historically has been a lack of temperature stability.
Another challenge to printing precision resistors on circuit boards is the
conductor height (great compared to thick film). The resistor values depend
on the length, width, thickness, and relative resistivity (ohms per square)
of the ink - printing in open areas vs. areas populated with circuitry can
affect the ink thickness.
I am aware of organic board designs utilizing polymer thick film resistor
inks but not if the resistors are laser trimmed at the assembler. One last
note: thick film types often look for .1% or .01% tolerances for their
resistors. These tolerances are ofted required in analog circuitry with
high gain amplifiers. For less demanding applications less precise
tolerances may be acceptable enabling the use of "as printed" resistors.
There are some books on thick film manufacturing, but I don't have the
titles available any more. You might try contacting ISHM (International
Society for Hybrid Manufacturing?) for more information. This got a little
long........hope it was helpful.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Tempea, Ioan
Sent: Thursday, October 25, 2001 10:55 AM
To: [log in to unmask]
Subject: [TN] Laser trimming of resistors
Hi Technos,
we are advancing in exploring new technologies. Some time ago I tapped your
wisdom for info on flex circuits, now I have a better one.
What is "laser trimming of resistors"? According to the small research I
did, it's related to thick films. Is that true? What should I read on this,
starting with some on-line resources?
Keeping in mind that we are assemblers, not board manufacturers, how is this
trimming related to SMT assembly, what equipment would do it (at what cost),
implementation issues, etc.
Best regards,
Ioan
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Date: Thu, 25 Oct 2001 15:21:07 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Innerlayer shorts - predictions vs. reality
MIME-Version: 1.0
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Another interesting variable is caused by the etch chemistry itself.
If you are etching with Cupric Chloride, you should have reasonably
consistent linear results.
If you are etching with an ammoniacal etchant, you may run into random
variables, as this type of etch chemistry is affected by board tarnish, and
if the boards are subject to tarnishing along the way, this could affect
etching, which would affect innerlayer shorts.
Rudy Sedlak
RD Chemical Company
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Date: Thu, 25 Oct 2001 15:34:13 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: White Residue...
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Well, Steve, there is the "approved" ways of doing things, which strangely
enough seems to always be the "expensive" way, and then there is the cheap
way...which seems to work, but, may not have been blessed by the gods of the
electronics world....
The "nonionic" residues you speak of are usually metallic residues, either
some kinda Lead salt, often Chloride, or a Tin oxide.
My usual approach is to use a fully aqueous cleaner, mildly alkaline, with
some kinda chelation to pick up the metal salts.
Some years ago somebody whispered that they used a machine dishwasher with a
typical machine dishwashing compound, and got real nice results.....
So we got some of this stuff, analyzed it, figured that PCB's do not need
chlorine to sanitize them, but could probably use a bit of anti-tarnish
compounds to minimize attack on the metals, and we now sell this product.
There are others, but I would warn you away from solvent containing cleaners,
and steer you towards full aqueous alkaline (to dissolve the Rosin) chelated
(to dissolve the metals) products.
This kind of product is going to be MUCH less expensive, as solvents are
costly...
Rudy Sedlak, who is still red-faced, but not so badly...
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Date: Thu, 25 Oct 2001 14:45:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Rework Procedures for electronic assemblies.
MIME-Version: 1.0
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Hello to All,
We found that our prominent contributor to scrap boards is the incorrect
rework.
Where can I find information about the recommended practices for the rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.
Any help will be greatly appreciated
Regards,
Alejandro Becerra
------_=_NextPart_001_01C15D8D.8A7EEB30
Content-Type: text/html;
charset="iso-8859-1"
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<TITLE>Rework Procedures for electronic assemblies.</TITLE>
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<BODY>
<P><FONT SIZE=2 FACE="Arial">Hello to All,</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">We found that our prominent contributor to scrap boards is the incorrect rework.</FONT>
<BR><FONT SIZE=2 FACE="Arial">Where can I find information about the recommended practices for the rework?</FONT>
<BR><FONT SIZE=2 FACE="Arial">The major problem is in components with 20 and 25 mil of pitch and with though hole connectors.</FONT>
<BR><FONT SIZE=2 FACE="Arial">Any help will be greatly appreciated</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Regards,</FONT>
</P>
<P><FONT SIZE=2 FACE="Arial">Alejandro Becerra</FONT>
</P>
</BODY>
</HTML>
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Date: Thu, 25 Oct 2001 16:13:28 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Rework Procedures for electronic assemblies.
In-Reply-To: <[log in to unmask]>
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Rework Procedures for electronic assemblies.IPC-7711 rework
IPC-7721 repair
www.circuittechctr.com click on the guidebook. Then say thank you Mr. Ferry.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Becerra Alejandro
Sent: Thursday, October 25, 2001 3:45 PM
To: [log in to unmask]
Subject: [TN] Rework Procedures for electronic assemblies.
Hello to All,
We found that our prominent contributor to scrap boards is the incorrect
rework.
Where can I find information about the recommended practices for the
rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.
Any help will be greatly appreciated
Regards,
Alejandro Becerra
------=_NextPart_000_0018_01C15D6F.FB48A680
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Rework Procedures for electronic assemblies.</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D758291120-25102001>IPC-7711 rework</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D758291120-25102001>IPC-7721 repair</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D758291120-25102001><A=20
href=3D"http://www.circuittechctr.com">www.circuittechctr.com</A> cl=
ick on=20
the guidebook. Then say thank you Mr. Ferry.</SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Becerra =
Alejandro<BR><B>Sent:</B>=20
Thursday, October 25, 2001 3:45 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Rework Procedures for =
electronic=20
assemblies.<BR><BR></DIV></FONT>
<P><FONT face=3DArial size=3D2>Hello to All,</FONT> </P>
<P><FONT face=3DArial size=3D2>We found that our prominent contributor =
to scrap=20
boards is the incorrect rework.</FONT> <BR><FONT face=3DArial =
size=3D2>Where can I=20
find information about the recommended practices for the =
rework?</FONT>=20
<BR><FONT face=3DArial size=3D2>The major problem is in components =
with 20 and 25=20
mil of pitch and with though hole connectors.</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=3DArial size=3D2>Regards,</FONT> </P>
<P><FONT face=3DArial size=3D2>Alejandro Becerra</FONT>=20
</P></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 25 Oct 2001 16:12:52 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: Rework Procedures for electronic assemblies.
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Alejandro,
You've touched on a hot spot with me. Our web site is overloaded with stuff
about rework. See our guide index at
http://www.circuittechctr.com/guides/guides.htm
<http://www.circuittechctr.com/guides/guides.htm>
Jeff Ferry
CEO
Circuit Technology Center, Inc.
www.circuittechctr.com
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
www.circuittechctr.com/general/free_email.htm
-----Original Message-----
From: Becerra Alejandro [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 3:45 PM
To: [log in to unmask]
Subject: [TN] Rework Procedures for electronic assemblies.
Hello to All,
We found that our prominent contributor to scrap boards is the incorrect
rework.
Where can I find information about the recommended practices for the rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.
Any help will be greatly appreciated
Regards,
Alejandro Becerra
------_=_NextPart_001_01C15D91.6D2D2200
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>Rework Procedures for electronic assemblies.</TITLE>
<META content="MSHTML 5.50.4807.2300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=600231020-25102001><FONT size=2>Alejandro,</FONT></SPAN></DIV>
<DIV><SPAN class=600231020-25102001><FONT size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=600231020-25102001><FONT size=2>You've touched on a hot spot
with me. Our web site is overloaded with stuff about rework. See our guide index
at <A
href="http://www.circuittechctr.com/guides/guides.htm">http://www.circuittechctr.com/guides/guides.htm</A></FONT></SPAN></DIV>
<DIV><SPAN class=600231020-25102001><FONT size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=600231020-25102001><FONT size=2>Jeff Ferry<BR>CEO<BR>Circuit
Technology Center,
Inc.<BR>www.circuittechctr.com<BR>[log in to unmask]<BR>978-374-5000<BR><BR>Sign
up for our Free E-mail Newsletter
at:<BR>www.circuittechctr.com/general/free_email.htm<BR></FONT></DIV></SPAN>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Becerra Alejandro
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, October 25, 2001 3:45
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Rework Procedures for
electronic assemblies.<BR><BR></FONT></DIV>
<P><FONT face=Arial size=2>Hello to All,</FONT> </P>
<P><FONT face=Arial size=2>We found that our prominent contributor to scrap
boards is the incorrect rework.</FONT> <BR><FONT face=Arial size=2>Where can I
find information about the recommended practices for the rework?</FONT>
<BR><FONT face=Arial size=2>The major problem is in components with 20 and 25
mil of pitch and with though hole connectors.</FONT> <BR><FONT face=Arial
size=2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=Arial size=2>Regards,</FONT> </P>
<P><FONT face=Arial size=2>Alejandro Becerra</FONT> </P></BODY></HTML>
------_=_NextPart_001_01C15D91.6D2D2200--
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Date: Thu, 25 Oct 2001 16:20:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Rework Procedures for electronic assemblies.
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Rework Procedures for electronic assemblies.=20
Two sources are:
1 Thanks to Jeff Ferry and the folk at Circuit Technology Center, Inc =
for posting outstanding on-line repair procedures =
[www.circuittechctr.com]. =20
2 IPC [www.ipc.org] publishes the following:
* 7721 - Repair & Modification of Printed Boards & Electronic Assemblies =
* 7711 - Rework of Electronic Assemblies
Dave Fish
----- Original Message -----=20
From: Becerra Alejandro=20
To: [log in to unmask]
Sent: Thursday, October 25, 2001 12:45 PM
Subject: [TN] Rework Procedures for electronic assemblies.
Hello to All,=20
We found that our prominent contributor to scrap boards is the =
incorrect rework.=20
Where can I find information about the recommended practices for the =
rework?=20
The major problem is in components with 20 and 25 mil of pitch and =
with though hole connectors.=20
Any help will be greatly appreciated=20
Regards,=20
Alejandro Becerra=20
------=_NextPart_000_000E_01C15D70.F2CE2100
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Rework Procedures for electronic assemblies.</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2919.6307" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>
<P class=3DMsoNormal>Two sources are:</P>
<P class=3DMsoNormal>1 Thanks to Jeff Ferry and the folk at Circuit =
Technology=20
Center, Inc for posting outstanding on-line repair procedures=20
[www.circuittechctr.com].<SPAN style=3D"mso-spacerun: yes"> =
</SPAN></P>
<P class=3DMsoNormal>2 IPC [www.ipc.org] publishes the following:</P>
<P class=3DMsoNormal>* 7721 - Repair & Modification of Printed =
Boards &=20
Electronic Assemblies <?xml:namespace prefix =3D o ns =3D=20
"urn:schemas-microsoft-com:office:office" /><o:p></o:p></P>
<P class=3DMsoNormal>* 7711 - Rework of Electronic Assemblies</P>
<P class=3DMsoNormal> </P>
<P class=3DMsoNormal>Dave Fish</P></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Becerra =
Alejandro</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, October 25, =
2001 12:45=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Rework Procedures =
for=20
electronic assemblies.</DIV>
<DIV><BR></DIV>
<P><FONT face=3DArial size=3D2>Hello to All,</FONT> </P>
<P><FONT face=3DArial size=3D2>We found that our prominent contributor =
to scrap=20
boards is the incorrect rework.</FONT> <BR><FONT face=3DArial =
size=3D2>Where can I=20
find information about the recommended practices for the =
rework?</FONT>=20
<BR><FONT face=3DArial size=3D2>The major problem is in components =
with 20 and 25=20
mil of pitch and with though hole connectors.</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=3DArial size=3D2>Regards,</FONT> </P>
<P><FONT face=3DArial size=3D2>Alejandro Becerra</FONT>=20
</P></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_000E_01C15D70.F2CE2100--
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Date: Thu, 25 Oct 2001 16:25:22 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Rework Procedures for electronic assemblies.
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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boundary="----=_NextPart_000_0016_01C15D71.A51096E0"
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Rework Procedures for electronic assemblies.Go to
http://www.circuittechctr.com/guides/guides.htm
There is a wealth of information here. Also, you should have IPC documents
7711 and 7721.
Bob
Robert Barr
Manufacturing Engineering
Formation, Inc.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Becerra Alejandro
Sent: Thursday, October 25, 2001 3:45 PM
To: [log in to unmask]
Subject: [TN] Rework Procedures for electronic assemblies.
Hello to All,
We found that our prominent contributor to scrap boards is the incorrect
rework.
Where can I find information about the recommended practices for the
rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.
Any help will be greatly appreciated
Regards,
Alejandro Becerra
------=_NextPart_000_0016_01C15D71.A51096E0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Rework Procedures for electronic assemblies.</TITLE>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D350272220-25102001><FONT face=3DArial size=3D2>Go =
to <A=20
href=3D"http://www.circuittechctr.com/guides/guides.htm">http://www.circu=
ittechctr.com/guides/guides.htm</A></FONT></SPAN></DIV>
<DIV><SPAN class=3D350272220-25102001><FONT face=3DArial=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D350272220-25102001><FONT face=3DArial size=3D2>There =
is a wealth of=20
information here. Also, you should have IPC documents 7711 and=20
7721.</FONT></SPAN></DIV>
<DIV> </DIV><BR>
<P><FONT size=3D2>Bob<BR><BR><BR>Robert Barr<BR>Manufacturing=20
Engineering<BR>Formation, Inc.<BR></FONT></P>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Becerra =
Alejandro<BR><B>Sent:</B>=20
Thursday, October 25, 2001 3:45 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Rework Procedures for =
electronic=20
assemblies.<BR><BR></FONT></DIV>
<P><FONT face=3DArial size=3D2>Hello to All,</FONT> </P>
<P><FONT face=3DArial size=3D2>We found that our prominent contributor =
to scrap=20
boards is the incorrect rework.</FONT> <BR><FONT face=3DArial =
size=3D2>Where can I=20
find information about the recommended practices for the =
rework?</FONT>=20
<BR><FONT face=3DArial size=3D2>The major problem is in components =
with 20 and 25=20
mil of pitch and with though hole connectors.</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=3DArial size=3D2>Regards,</FONT> </P>
<P><FONT face=3DArial size=3D2>Alejandro Becerra</FONT>=20
</P></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0016_01C15D71.A51096E0--
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Date: Thu, 25 Oct 2001 16:27:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
We would not bake the parts again, after reballing, sounds like you will be
meeting the requirments of the standard. I think it is a free download. If
you need the link let me know and I will try to find it. Might have been on
the ANSI page or JEDEC.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jeff Ferry
> Sent: Thursday, October 25, 2001 9:45 AM
> To: [log in to unmask]
> Subject: [TN] BGA Component Baking - Plastic Body
>
>
> BGA Guru's,
>
> We're doing a big project that requires removal/replacement of several
> hundred plastic BGA components. After removal we'll be reballing the BGA's
> and then reinstalling them. These are new builds, they're not coming back
> from the field.
>
> Who knows what J-STD-20, or any other reference, says about prebaking
> temp/time to eliminate possible moisture problems in the components or
> boards prior to initial removal? Removed parts will be stored in a
> desiccant chamber before and after reballing. Do we need to bake these
> parts again prior to installation? Do ya'all normally bake new
> build boards
> in this situation?
>
> Thanks for you recommendations.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
>
> ------------------------------------------------------------------
> ---------------
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> Databases > E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>
---------------------------------------------------------------------------------
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Date: Thu, 25 Oct 2001 15:27:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Re: THE ANSWER!! Rework Procedures for electronic assemblies.
Mime-Version: 1.0
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7711 - Rework of Electronic Assemblies
Covers procedures for reworking electronic assemblies, either as part of =
the manufacturing process or after the assemblies have been in the field. =
Describes the procedural requirements, tools, materials and methods to be =
used in removing and replacing conformal coatings, surface mount and =
through-hole components. Supersedes IPC-R-700C. 184 pages. Released =
February 1998.=20
7721 - Repair and Modification of Printed Boards and Electronic Assemblies
Covers procedures for modifying, reworking and repairing printed boards =
and printed board assemblies. Prescribes the procedural requirements as =
well as tools, materials and methods to be used in removing and replacing =
conformal coatings and solder resist material. Also covers repair and =
modification of printed board conductors, laminates and plated-through =
holes. Supersedes IPC-R-700C. 156 pages. Released February 1998.=20
Purchase the IPC-7711/7721 series and save 20% over individual document =
prices.
www.ipc.org/bookstore
Jack
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
APEX - the industry's premier trade show in Electronics
Manufacturing, January 22-24, 2002, San Diego, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
>>> [log in to unmask] 10/25/01 02:45PM >>>
Hello to All,=20
We found that our prominent contributor to scrap boards is the incorrect =
rework.=20
Where can I find information about the recommended practices for the =
rework?=20
The major problem is in components with 20 and 25 mil of pitch and with =
though hole connectors.=20
Any help will be greatly appreciated=20
Regards,=20
Alejandro Becerra=20
--=_2872C6D6.6C0D69E5
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV>7711 - Rework of Electronic Assemblies<BR>Covers procedures for =
reworking=20
electronic assemblies, either as part of the manufacturing process or =
after the=20
assemblies have been in the field. Describes the procedural requirements, =
tools,=20
materials and methods to be used in removing and replacing conformal =
coatings,=20
surface mount and through-hole components. Supersedes IPC-R-700C. 184 =
pages.=20
Released February 1998. </DIV>
<DIV> </DIV>
<DIV>7721 - Repair and Modification of Printed Boards and Electronic=20
Assemblies<BR>Covers procedures for modifying, reworking and repairing =
printed=20
boards and printed board assemblies. Prescribes the procedural requirements=
as=20
well as tools, materials and methods to be used in removing and =
replacing=20
conformal coatings and solder resist material. Also covers repair and=20
modification of printed board conductors, laminates and plated-through =
holes.=20
Supersedes IPC-R-700C. 156 pages. Released February 1998. </DIV>
<DIV> </DIV>
<DIV>Purchase the IPC-7711/7721 series and save 20% over individual =
document=20
prices.</DIV>
<DIV> </DIV>
<DIV><A href=3D"http://www.ipc.org/bookstore">www.ipc.org/bookstore</A></DI=
V>
<DIV> </DIV>
<DIV>Jack<BR></DIV>
<DIV> </DIV>
<DIV>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<BR>APEX - the =
industry's premier=20
trade show in Electronics<BR>Manufacturing, January 22-24, 2002, San =
Diego,=20
California.<BR>More information on website <A=20
href=3D"http://www.goapex.org">www.goapex.org</A><BR>--------<BR>Jack =
Crawford,=20
IPC Director of Assembly Standards and Technology<BR>2215 Sanders Road,=20
Northbrook IL 60062-6135<BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <BR>847-790-5393<BR>fax=
=20
847-504-2393<BR><BR>>>> [log in to unmask] 10/25/01 02:45PM=20
>>><BR></DIV>
<P><FONT face=3DArial size=3D2>Hello to All,</FONT> </P>
<P><FONT face=3DArial size=3D2>We found that our prominent contributor to =
scrap=20
boards is the incorrect rework.</FONT> <BR><FONT face=3DArial size=3D2>Wher=
e can I=20
find information about the recommended practices for the rework?</FONT>=20
<BR><FONT face=3DArial size=3D2>The major problem is in components with 20 =
and 25=20
mil of pitch and with though hole connectors.</FONT> <BR><FONT face=3DArial=
=20
size=3D2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=3DArial size=3D2>Regards,</FONT> </P>
<P><FONT face=3DArial size=3D2>Alejandro Becerra</FONT> </P></BODY></HTML>
--=_2872C6D6.6C0D69E5--
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Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
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---------------------------------------------------------------------------------
=========================================================================
Date: Thu, 25 Oct 2001 16:36:42 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cheryl White <[log in to unmask]>
Subject: Chloride levels
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Is there a standard for acceptable levels of chloride on assembled PCBs and
on bare boards? What sources of chlorides exist in a board fabrication
process, and in an assembly process?
We are using a no-clean low-solid flux.
Thanks,
Cheryl White
Manufacturing Engineering
DSC Ltd.
[log in to unmask]
(905) 760-3000 ext. 7228
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=========================================================================
Date: Thu, 25 Oct 2001 15:59:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Re: THE ANSWER!! Rework Procedures for electronic assemblie s.
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Thanks for all your answers.
I found very usefull information.
-----Original Message-----
From: Jack Crawford [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 1:28 PM
To: [log in to unmask]
Subject: Re: [TN] THE ANSWER!! Rework Procedures for electronic assemblies.
7711 - Rework of Electronic Assemblies
Covers procedures for reworking electronic assemblies, either as part of the
manufacturing process or after the assemblies have been in the field.
Describes the procedural requirements, tools, materials and methods to be
used in removing and replacing conformal coatings, surface mount and
through-hole components. Supersedes IPC-R-700C. 184 pages. Released February
1998.
7721 - Repair and Modification of Printed Boards and Electronic Assemblies
Covers procedures for modifying, reworking and repairing printed boards and
printed board assemblies. Prescribes the procedural requirements as well as
tools, materials and methods to be used in removing and replacing conformal
coatings and solder resist material. Also covers repair and modification of
printed board conductors, laminates and plated-through holes. Supersedes
IPC-R-700C. 156 pages. Released February 1998.
Purchase the IPC-7711/7721 series and save 20% over individual document
prices.
www.ipc.org/bookstore <http://www.ipc.org/bookstore>
Jack
==========================================
APEX - the industry's premier trade show in Electronics
Manufacturing, January 22-24, 2002, San Diego, California.
More information on website www.goapex.org <http://www.goapex.org>
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask] <mailto:[log in to unmask]>
847-790-5393
fax 847-504-2393
>>> [log in to unmask] 10/25/01 02:45PM >>>
Hello to All,
We found that our prominent contributor to scrap boards is the incorrect
rework.
Where can I find information about the recommended practices for the rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.
Any help will be greatly appreciated
Regards,
Alejandro Becerra
------_=_NextPart_001_01C15D97.DF48CE60
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4522.1800" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV><SPAN class=690145820-25102001><FONT size=1>Thanks for all your
answers.</FONT></SPAN></DIV>
<DIV><SPAN class=690145820-25102001><FONT size=1>I found very usefull
information.</FONT></SPAN></DIV>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Jack Crawford
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, October 25, 2001 1:28
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] THE ANSWER!! Rework
Procedures for electronic assemblies.<BR><BR></FONT></DIV>
<DIV>7711 - Rework of Electronic Assemblies<BR>Covers procedures for reworking
electronic assemblies, either as part of the manufacturing process or after the
assemblies have been in the field. Describes the procedural requirements, tools,
materials and methods to be used in removing and replacing conformal coatings,
surface mount and through-hole components. Supersedes IPC-R-700C. 184 pages.
Released February 1998. </DIV>
<DIV> </DIV>
<DIV>7721 - Repair and Modification of Printed Boards and Electronic
Assemblies<BR>Covers procedures for modifying, reworking and repairing printed
boards and printed board assemblies. Prescribes the procedural requirements as
well as tools, materials and methods to be used in removing and replacing
conformal coatings and solder resist material. Also covers repair and
modification of printed board conductors, laminates and plated-through holes.
Supersedes IPC-R-700C. 156 pages. Released February 1998. </DIV>
<DIV> </DIV>
<DIV>Purchase the IPC-7711/7721 series and save 20% over individual document
prices.</DIV>
<DIV> </DIV>
<DIV><A href="http://www.ipc.org/bookstore">www.ipc.org/bookstore</A></DIV>
<DIV> </DIV>
<DIV>Jack<BR></DIV>
<DIV> </DIV>
<DIV>==========================================<BR>APEX - the industry's premier
trade show in Electronics<BR>Manufacturing, January 22-24, 2002, San Diego,
California.<BR>More information on website <A
href="http://www.goapex.org">www.goapex.org</A><BR>--------<BR>Jack Crawford,
IPC Director of Assembly Standards and Technology<BR>2215 Sanders Road,
Northbrook IL 60062-6135<BR><A
href="mailto:[log in to unmask]">[log in to unmask]</A> <BR>847-790-5393<BR>fax
847-504-2393<BR><BR>>>> [log in to unmask] 10/25/01 02:45PM
>>><BR></DIV>
<P><FONT face=Arial size=2>Hello to All,</FONT> </P>
<P><FONT face=Arial size=2>We found that our prominent contributor to scrap
boards is the incorrect rework.</FONT> <BR><FONT face=Arial size=2>Where can I
find information about the recommended practices for the rework?</FONT>
<BR><FONT face=Arial size=2>The major problem is in components with 20 and 25
mil of pitch and with though hole connectors.</FONT> <BR><FONT face=Arial
size=2>Any help will be greatly appreciated</FONT> </P>
<P><FONT face=Arial size=2>Regards,</FONT> </P>
<P><FONT face=Arial size=2>Alejandro Becerra</FONT> </P></BODY></HTML>
------_=_NextPart_001_01C15D97.DF48CE60--
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Date: Thu, 25 Oct 2001 13:56:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sean Clinton <[log in to unmask]>
Subject: Racks plating up
Mime-Version: 1.0
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Hi All,
I have a slight problem that I want to avoid turning into a major costly
issue. I have a few plating racks that are starting to be overrun with
wild plating ( copper and tin) up the rack away from the contacts in areas
that are not supposed to be plating. There are even areas of isolated
plated metal surrounded by plastic. Upon inspection, I was able to peel
off the plated tin and copper and noticed several layers. I think this is
most likely due to multiple plating cycles.
The racks are solid copper core with a plastic shrouding. The manufacturer
claims that "no rack stripping" is needed. In the universe where I am
from, most plastics aren't conductive and don't plate. I understand that
once initiated, the plating will propagate in the path of least resistance,
but what is causing it?
My suspicions include poor rinsing of the racks (conductive salts
remaining?) after a plating cycle or conductive carbon (from our Shadow
process) getting into scratches in the plastic shrouds and eventually
arcing causing this plating, but I haven't been able to confirm or disprove
either theory yet. It's not affecting quality, but I don't want to wait
until it does. Is there some preventative measure to eliminate the problem
that anyone has tried?
Thanks,
Sean Clinton
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Date: Thu, 25 Oct 2001 17:25:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ilknur Baylakoglu <[log in to unmask]>
Organization: CALCE EPRC
Subject: Re: Chloride levels
In-Reply-To: <D886DC8708ACD3118A0500606DD5DA63035F930C@DSC_MAIL>
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Hi Cheryl,
There are some recommended maximum chloride levels at csl`s
web page(www.residue.com)
4.5 micrograms per square inch for final assemblies processed
with rosen fluxes
2.5 micrograms per square inch for final assemblies processed
with low solids (no-clean) fluxes
4.5 -5.0 micrograms per square inch for final assemblies
processed with water soluble fluxes
<2.0 micrograms per square inch for a bare board(tin-lead coated)
Rinsing water is one of the source in PWB manufacturing.
Ilknur baylakoglu
On 25 Oct 01, at 16:36, Cheryl White wrote:
> Is there a standard for acceptable levels of chloride on assembled PCBs and
> on bare boards? What sources of chlorides exist in a board fabrication
> process, and in an assembly process?
>
> We are using a no-clean low-solid flux.
>
> Thanks,
> Cheryl White
> Manufacturing Engineering
> DSC Ltd.
> [log in to unmask]
> (905) 760-3000 ext. 7228
>
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Date: Thu, 25 Oct 2001 16:24:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary McCauley <[log in to unmask]>
Subject: Re: Chloride levels
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Many fluxes used in board fabrication contain chlorides or bromides.
gary mccauley
-----Original Message-----
From: Cheryl White [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 3:37 PM
To: [log in to unmask]
Subject: [TN] Chloride levels
Is there a standard for acceptable levels of chloride on assembled PCBs and
on bare boards? What sources of chlorides exist in a board fabrication
process, and in an assembly process?
We are using a no-clean low-solid flux.
Thanks,
Cheryl White
Manufacturing Engineering
DSC Ltd.
[log in to unmask]
(905) 760-3000 ext. 7228
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Date: Thu, 25 Oct 2001 18:12:48 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bogert <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
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Wrong. Pure tin will grow tin whiskers.
----- Original Message -----
From: "Brian Ellis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 3:36 AM
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
> Here's an interesting thought:
>
> If we ask all the component manufacturers (incl. bare boards) to use
> pure tin for their lead coatings etc., instead of tin/lead, this would
> a) satisfy the lead-free guys
> b) help keep the proportions right in the solder pot
>
> Right?
>
> Brian
>
> "d. terstegge" wrote:
> >
> > Hi Technet,
> >
> > I just received an analyses report for our solder bath composition, and
my Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
> > Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
> > It can't be that difficult, but I thought it would be quicker to ask.
> >
> > Thanks,
> >
> > Daan Terstegge
> > SMT Centre
> > Thales Communications
> > Unclassified mail
> > Personal Website: http://www.smtinfo.net
> >
>
> --------------------------------------------------------------------------
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> E-mail Archives
> > Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
>
> --------------------------------------------------------------------------
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>
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Date: Thu, 25 Oct 2001 15:41:55 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: BGA Profiling
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Hello,
I encounter a board with various BGAs and one with
pads as small as 0.014" dia. but my thermalcouple is
at least 0.024".
Any suggestion on profiling the board with regard to
method of attaching the TC on these pads?
Rgds,
Peter
__________________________________________________
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Date: Thu, 25 Oct 2001 19:05:20 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
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Hellooooo S. Miller,
We at Coretec LOVE heavy copper and will have much fun delivering product to
you. Check out the www.coretec-inc.com web site, it will have a lot of heavy
copper info. 3 ounce per layer is easy (currently doing 6 ounce inners, 4 oz
outers; UL approved).
Feel free to call me if you need info.
Sincerely,
Brad Saunders
Coretec Field Applications Eng
781-858-0783
--part1_1e.1d454c06.2909f4b0_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hellooooo S. Miller,
<BR>
<BR>We at Coretec LOVE heavy copper and will have much fun delivering product to you. Check out the www.coretec-inc.com web site, it will have a lot of heavy copper info. 3 ounce per layer is easy (currently doing 6 ounce inners, 4 oz outers; UL approved).
<BR>
<BR>Feel free to call me if you need info.
<BR>
<BR>Sincerely,
<BR>
<BR>Brad Saunders
<BR>Coretec Field Applications Eng
<BR>781-858-0783</FONT></HTML>
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Date: Thu, 25 Oct 2001 16:25:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
does reflowed tin grow whiskers? i thought whiskers grew from plated tin that's under stress. i also thought that one way to correct this was to reflow the plated tin.
phil
-----Original Message-----
From: Bogert [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 3:13 PM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Wrong. Pure tin will grow tin whiskers.
----- Original Message -----
From: "Brian Ellis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 3:36 AM
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
> Here's an interesting thought:
>
> If we ask all the component manufacturers (incl. bare boards) to use
> pure tin for their lead coatings etc., instead of tin/lead, this would
> a) satisfy the lead-free guys
> b) help keep the proportions right in the solder pot
>
> Right?
>
> Brian
>
> "d. terstegge" wrote:
> >
> > Hi Technet,
> >
> > I just received an analyses report for our solder bath composition, and
my Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
the edge of the J-STD-001C specification, so I'll have to add some pure tin
to the pot.
> > Last time was many years ago, and unfortunately I forgot the formula for
calculating the amount of tin to add.
> > It can't be that difficult, but I thought it would be quicker to ask.
> >
> > Thanks,
> >
> > Daan Terstegge
> > SMT Centre
> > Thales Communications
> > Unclassified mail
> > Personal Website: http://www.smtinfo.net
> >
>
> --------------------------------------------------------------------------
-------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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in
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> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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>
> --------------------------------------------------------------------------
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>
> --------------------------------------------------------------------------
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Date: Fri, 26 Oct 2001 09:14:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: In Search of Thick Cu PCB Manufacturer
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
You can try Fineline Circuits & Technology , Brea, CA. They do almost
anything and everything and are very good in my experience. Talk to Ken
Pansuria 714-529-2942.
Peter Duncan
"S. Miller"
<CircuitekAsi To: [log in to unmask]
[log in to unmask]> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] In Search of Thick Cu PCB
<[log in to unmask] Manufacturer
ORG>
10/25/01
09:37 PM
Please
respond to
"TechNet
E-Mail
Forum."
To All,
My company has been asked to tender a bid for an assembly that includes a 8
LYR PCB with 3 oz Cu (internal) and 4 oz (external) plating.
I am desperately trying to find a supplier that can provide the same and
any recommendations would be truly appreciated.
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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Date: Fri, 26 Oct 2001 09:19:46 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Most, if not all PBGA's I've met are MSD Cat 3's, but that's a little
beside the point. The bake-out recommendation from the latest J-STD info is
125 deg C for 48 hours if the components have exceeded their 16 hours
"shop" life humidity exposure.
Peter Duncan
Jeff Ferry
<jferry@CIRCUITTE To: [log in to unmask]
CHCTR.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] BGA Component Baking - Plastic
Body
10/25/01 09:45 PM
Please respond to
"TechNet E-Mail
Forum."
BGA Guru's,
We're doing a big project that requires removal/replacement of several
hundred plastic BGA components. After removal we'll be reballing the BGA's
and then reinstalling them. These are new builds, they're not coming back
from the field.
Who knows what J-STD-20, or any other reference, says about prebaking
temp/time to eliminate possible moisture problems in the components or
boards prior to initial removal? Removed parts will be stored in a
desiccant chamber before and after reballing. Do we need to bake these
parts again prior to installation? Do ya'all normally bake new build boards
in this situation?
Thanks for you recommendations.
Jeff Ferry
CEO
Circuit Technology Center, Inc.
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Date: Thu, 25 Oct 2001 21:32:46 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dennis Fritz <[log in to unmask]>
Subject: Re: Laser trimming of resistors
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In a message dated 10/25/01 10:55:24 AM US Eastern Standard Time,
[log in to unmask] writes:
> What is "laser trimming of resistors"? According to the small research I
> did, it's related to thick films. Is that true? What should I read on this,
> starting with some on-line resources?
>
> Keeping in mind that we are assemblers, not board manufacturers, how is this
> trimming related to SMT assembly, what equipment would do it (at what cost),
> implementation issues, etc.
>
All discrete surface mount resistors are trimmed to value by lasers. It is
just that you can't see the cuts because the trimmed surface is overcoated
with some passivation protection. Thick film hybrid circuits are trimmed "in
the open" and you can see the trim to value. Interestingly, there is a move
to embed resistors in circuit boards - in the middle of a multilayer. There
is a proposal to laser trim these, too if high accuracy is required. Electro
Scientific Industries (ESI) showed a concept machine for this at IPC Expo
last April in Anaheim.
Both ESI and Lumonics make laser trim machines for the discrete component
industry. With discretes, it is assumed the resistor is trimmed to the
correct value before passivation coating (and sale) - do you have a need to
change resistor values once the board is assembled? Can that be done by a
variable resistor component?
Dennis Fritz
MacDermid
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 10/25/01 10:55:24 AM US Eastern Standard Time, [log in to unmask] writes:
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><I>What is "laser trimming of resistors"? According to the small research I
<BR>did, it's related to thick films. Is that true? What should I read on this,
<BR>starting with some on-line resources?
<BR>
<BR>Keeping in mind that we are assemblers, not board manufacturers, how is this
<BR>trimming related to SMT assembly, what equipment would do it (at what cost),
<BR>implementation issues, etc.</I>
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">All discrete surface mount resistors are trimmed to value by lasers. It is just that you can't see the cuts because the trimmed surface is overcoated with some passivation protection. Thick film hybrid circuits are trimmed "in the open" and you can see the trim to value. Interestingly, there is a move to embed resistors in circuit boards - in the middle of a multilayer. There is a proposal to laser trim these, too if high accuracy is required. Electro Scientific Industries (ESI) showed a concept machine for this at IPC Expo last April in Anaheim.
<BR>
<BR>Both ESI and Lumonics make laser trim machines for the discrete component industry. With discretes, it is assumed the resistor is trimmed to the correct value before passivation coating (and sale) - do you have a need to change resistor values once the board is assembled? Can that be done by a variable resistor component?
<BR>
<BR>Dennis Fritz
<BR>MacDermid
<BR></FONT></HTML>
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Date: Fri, 26 Oct 2001 09:59:41 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
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Brad,
Are you using real, fully-populated boards for thermal profiling?
Extravagant fellow is you are when the volume is low, and I'm not sure
either why you have to scrap the assemblies afterwards - the major
components willbe recoverable.
I also am involved with high mix, low volume builds, and I try to get one
board of each type from the fab house that has failed electrical with
internal shorts or whatever (cheaper than sacrificing a good board). I then
buy in a stack of dummy components from Practical Components or Topline and
populate the profile board with those. I don't bother with discrete
passives, as they contribute precious little to the thermal mass. The
thermal profile board is them reflowed using the standard profile supplied
by the solder manufacturer.
For BGA's and so forth, I then drill a hole up through the board into one
of the central contacts to take a thermocouple wire, which is bonded in
place, and add other thermocouples around the board. plug them all into a
high-temp data logger
"Brad A. Smith"
<BAS@BADGERELECTR To: [log in to unmask]
ONICS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Reflow profiling
10/25/01 11:37 PM
Please respond to
"TechNet E-Mail
Forum."
Hello All,
I am with a low volume, frequent changeover contract manufacturer. We are
trying to implement a system where we profile the first assembly of every
new run through our reflow oven. We are currently using high temperature
solder for profiling. If we start to use the high temp solder for this, we
will have to scrap the assemblies. Does anyone have any suggestions for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Thu, 25 Oct 2001 22:00:18 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Chloride levels
MIME-Version: 1.0
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Cheryl:
Be aware that most "chloride" measuring devices/systems simply measure
conductivity, and express it as equivalent amounts of Sodium Chloride, so
they really do not actually determine chloride, they determine conductivity.
And anything ionic can contribute to conductivity, and that can come from
either flux or tap water.
Rudy Sedlak
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Date: Fri, 26 Oct 2001 00:22:14 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Zarrow <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_171.2ef1992.290a3ef6_boundary"
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Peter and all -
Actually, the IPC/Jedec spec scratches the surface - MSD is more involved
than most practitioners know about.
I highly recommend some excellent papers, including one by Dr. Schook of ATT
who seems to be the MSD whiz at the Cogiscan website. The Cogiscan people
are MSD gurus. They are at www.cogiscan.com
Phil Zarrow
ITM Consulting
Durham, NH USA
www.ITM-SMT.com
--part1_171.2ef1992.290a3ef6_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Peter and all -
<BR>Actually, the IPC/Jedec spec scratches the surface - MSD is more involved than most practitioners know about.
<BR>I highly recommend some excellent papers, including one by Dr. Schook of ATT who seems to be the MSD whiz at the Cogiscan website. The Cogiscan people are MSD gurus. They are at www.cogiscan.com
<BR>Phil Zarrow
<BR>ITM Consulting
<BR>Durham, NH USA
<BR>www.ITM-SMT.com</FONT></HTML>
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Date: Fri, 26 Oct 2001 13:45:01 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
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Actually, you don't need very long thermocouple wire. Just bond your
t/couples to the desired board positions and plug them into a data logger
that travels through the reflow oven with the board. At the other end, you
unplug the data logger from the t/couples and plug it into a printer with a
special docking port and it just prints out the profile of the temperatures
achieved by each couple on its journey through the oven. Then if you need
to tweak the temperature settings of the zones, you can do so and run the
profile baord through the oven again to verify that everything is OK and
get another print-out straight away - very simple and convenient.
Peter Duncan
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: Re: [TN] Reflow profiling
<[log in to unmask]>
10/26/01 12:37 AM
Please respond to
"TechNet E-Mail
Forum."
Hi Brad,
Why not use a temperature datalogger, kapton tape and some long
thermocouple
wire?
There are many sources but http://www.omega.com would be a great place to
start.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Brad A. Smith [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 11:37 AM
To: [log in to unmask]
Subject: [TN] Reflow profiling
Hello All,
I am with a low volume, frequent changeover contract manufacturer. We are
trying to implement a system where we profile the first assembly of every
new run through our reflow oven. We are currently using high temperature
solder for profiling. If we start to use the high temp solder for this, we
will have to scrap the assemblies. Does anyone have any suggestions for
alternatives to high temp solder? Any suggestions would be greatly
appreciated.
Thank you,
Brad Smith
Process Technician
Badger Electronics Co., Inc.
(262)886-8800
[log in to unmask]
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Date: Fri, 26 Oct 2001 09:17:50 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
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Wrong. There will be no whiskers after it has gone through the wave.
Bogert wrote:
>
> Wrong. Pure tin will grow tin whiskers.
> ----- Original Message -----
> From: "Brian Ellis" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Thursday, October 25, 2001 3:36 AM
> Subject: Re: [TN] Adjusting the alloy composition in the solderpot
>
> > Here's an interesting thought:
> >
> > If we ask all the component manufacturers (incl. bare boards) to use
> > pure tin for their lead coatings etc., instead of tin/lead, this would
> > a) satisfy the lead-free guys
> > b) help keep the proportions right in the solder pot
> >
> > Right?
> >
> > Brian
> >
> > "d. terstegge" wrote:
> > >
> > > Hi Technet,
> > >
> > > I just received an analyses report for our solder bath composition, and
> my Sn level is at 61.5 percent instead of the nominal 63 percent. This is at
> the edge of the J-STD-001C specification, so I'll have to add some pure tin
> to the pot.
> > > Last time was many years ago, and unfortunately I forgot the formula for
> calculating the amount of tin to add.
> > > It can't be that difficult, but I thought it would be quicker to ask.
> > >
> > > Thanks,
> > >
> > > Daan Terstegge
> > > SMT Centre
> > > Thales Communications
> > > Unclassified mail
> > > Personal Website: http://www.smtinfo.net
> > >
> >
> > --------------------------------------------------------------------------
> -------
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Date: Fri, 26 Oct 2001 08:32:40 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
In-Reply-To: <[log in to unmask]>
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So using your formula that makes Bev about 150 years old percent then, or
did I miss something.
Happy Friday.
Best regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Lou Hart
Sent: Thursday, October 25, 2001 5:51 PM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Eric, Steve, et al,
I recommend going back to basic calculus and calculating the derivative of
fraction tin with respect to weight (mass) of tin.
Fraction tin = (Tin mass)/(Tin mass + Lead mass)
You will get (assuming you only want a small change in fraction tin, in the
range of, say, 0.03 or less)
Tin add = (Mass of pot) X (change desired in Fraction Tin)/(Fraction Lead)
On an unrelated matter, let me comment that a number of names like Shirley,
Beverly, and Vivian were used by men until the first half of the past
century. Over some time period, women largely took possession of them.
Lou Hart
-----Original Message-----
From: Eric Dawson [SMTP:[log in to unmask]]
Sent: Thursday, October 25, 2001 2:53 AM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Hi All,
The easiest way to think of this is not the use of a complicated formula,
but the simple application of percentage.
In the example below, the total weight of tin plus lead is 1500 pounds,
61.9% of which is tin. Hence there are 928.5 pounds of tin.
Add 45 pounds of tin, the total weight is now 1545 pounds of which, 973.5
pounds is tin. Work out the new percentage of the new total weight and you
get 63%.
Ahah, I hear you ask, how do you get to 45 pounds in the first place? Well,
just plug a few numbers into the percentage calculations and see which
direction it takes you.
The main thing to remember is that you add the tin addition to the total
weight as well as the tin content when working out the new percentage.
Hope this helps
Regards
Eric Dawson
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Date: Fri, 26 Oct 2001 16:08:10 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Guy,
I am a bit concerned about your suggestion about not baking the BGA's
without knowing what their exposure time is. If they haven't been
monitored, or have been out of a dry cabinet for 16 hours or more in total
since previous bake or since removal from their original barrier bags, it's
safer to bake them after re-balling them. This is to minimise the risk of
delamination or popcorning when they placed back on the boards and
subjected to reflow.
I think you're right that both J-STD-20 and J-STD-33 are free downloads
from the IPC site.
Peter Duncan
Guy Ramsey
<gramsey@ACIU To: [log in to unmask]
SA.ORG> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] BGA Component Baking -
<[log in to unmask] Plastic Body
ORG>
10/26/01
04:27 AM
Please
respond to
"TechNet
E-Mail
Forum."
We would not bake the parts again, after reballing, sounds like you will be
meeting the requirments of the standard. I think it is a free download. If
you need the link let me know and I will try to find it. Might have been on
the ANSI page or JEDEC.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jeff Ferry
> Sent: Thursday, October 25, 2001 9:45 AM
> To: [log in to unmask]
> Subject: [TN] BGA Component Baking - Plastic Body
>
>
> BGA Guru's,
>
> We're doing a big project that requires removal/replacement of several
> hundred plastic BGA components. After removal we'll be reballing the
BGA's
> and then reinstalling them. These are new builds, they're not coming back
> from the field.
>
> Who knows what J-STD-20, or any other reference, says about prebaking
> temp/time to eliminate possible moisture problems in the components or
> boards prior to initial removal? Removed parts will be stored in a
> desiccant chamber before and after reballing. Do we need to bake these
> parts again prior to installation? Do ya'all normally bake new
> build boards
> in this situation?
>
> Thanks for you recommendations.
>
> Jeff Ferry
> CEO
> Circuit Technology Center, Inc.
>
> ------------------------------------------------------------------
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Date: Fri, 26 Oct 2001 10:32:02 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sasha Miladinovic <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
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Hello Andre,
How big are those 10 via holes? Is the PCB double sided?
My experience with the SMT parts with backside ground is that you must =
wave
solder after reflow. Usually, when reviewing the design of the PCB, I m=
ake
remark on those things by asking the designer to implement plated holes=
in
to the soldering area. The size of the holes is depending of the
components/soldering area geometry. Than it's relatively easy to solder=
those kinds of components. First by screening the soldering paste on th=
e
area, having reasonable distance between the hole and screened solderin=
g
paste avoiding that the holes are draining the solder during reflow.
Secondly, by taking the advantage of the capillary effect, remelt
(hopefully) the previously soldered backside ground area during the wav=
e
soldering process. The soldered part is still positioned by solder on t=
he
outline. Do not forget that the result is depending of the compatibilit=
y of
those two processes (reflow and wave soldering). I have verified the re=
sult
on the four different PCB and the only thing that I have done was to ch=
ange
wave-soldering profile slightly to increase the contact lenght over the=
tin
bath.
I don't know if this solution is applicable in your manufacturing proce=
ss
but I'm hoping that you are going to solve the problem soon. :)
Good luck,
Sasha
***********************************************************************=
**
Sasha Miladinovic - Production Engineering
Amersham Biosciences, PCB Production, Ume=E5
Tel: +46 (0) 90 150 232
Fax: +46 (0) 90 138 372
E-mail: [log in to unmask]
***********************************************************************=
**
=
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Date: Fri, 26 Oct 2001 10:40:55 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: AW: [TN] Rework Procedures for electronic assemblies.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi Alejandro,
=20
besides those literature covering all the different methods for =
different
rework tasks it=B4s absolutely necessary that you have the right tools =
and the
operators the knowledge and skill to use them the right way.
Although everything was "well" known in some companies the results of =
their
rework were really disastrous. A good training and a lot of practice as =
well
as the willingness to do a good job are also necessary.
Say goodby to "quick=B4n=B4dirty", allow for the time that=B4s really =
needed for a
rework action. Have only the best do the job and not just everybody.
=20
This is a painful everyday experience and I think it=B4s not limited to =
just
my part of the world.
=20
Good luck=20
Wolfgang
=20
-----Urspr=FCngliche Nachricht-----
Von: Becerra Alejandro [mailto:[log in to unmask]]
Gesendet am: Donnerstag, 25. Oktober 2001 21:45
An: [log in to unmask]
Betreff: [TN] Rework Procedures for electronic assemblies.
Hello to All,=20
We found that our prominent contributor to scrap boards is the =
incorrect
rework.=20
Where can I find information about the recommended practices for the =
rework?
The major problem is in components with 20 and 25 mil of pitch and with
though hole connectors.=20
Any help will be greatly appreciated=20
Regards,=20
Alejandro Becerra=20
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Date: Fri, 26 Oct 2001 09:45:09 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
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Mike,
In such cases I apply a variable constant.
Happy POETS Day
Regards
Eric Dawson
> -----Original Message-----
> From: Mike Fenner [SMTP:[log in to unmask]]
> Sent: Friday, October 26, 2001 8:33 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adjusting the alloy composition in the solderpot
>
> So using your formula that makes Bev about 150 years old percent then, or
> did I miss something.
>
> Happy Friday.
>
> Best regards
>
> Mike
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Lou Hart
> Sent: Thursday, October 25, 2001 5:51 PM
> To: [log in to unmask]
> Subject: Re: [TN] Adjusting the alloy composition in the solderpot
>
>
> Eric, Steve, et al,
>
> I recommend going back to basic calculus and calculating the derivative of
> fraction tin with respect to weight (mass) of tin.
>
> Fraction tin = (Tin mass)/(Tin mass + Lead mass)
>
> You will get (assuming you only want a small change in fraction tin, in
> the
> range of, say, 0.03 or less)
>
> Tin add = (Mass of pot) X (change desired in Fraction Tin)/(Fraction Lead)
>
> On an unrelated matter, let me comment that a number of names like
> Shirley,
> Beverly, and Vivian were used by men until the first half of the past
> century. Over some time period, women largely took possession of them.
> Lou Hart
>
>
>
> -----Original Message-----
> From: Eric Dawson [SMTP:[log in to unmask]]
> Sent: Thursday, October 25, 2001 2:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Adjusting the alloy composition in the solderpot
>
> Hi All,
> The easiest way to think of this is not the use of a complicated formula,
> but the simple application of percentage.
>
> In the example below, the total weight of tin plus lead is 1500 pounds,
> 61.9% of which is tin. Hence there are 928.5 pounds of tin.
> Add 45 pounds of tin, the total weight is now 1545 pounds of which, 973.5
> pounds is tin. Work out the new percentage of the new total weight and you
> get 63%.
> Ahah, I hear you ask, how do you get to 45 pounds in the first place?
> Well,
> just plug a few numbers into the percentage calculations and see which
> direction it takes you.
> The main thing to remember is that you add the tin addition to the total
> weight as well as the tin content when working out the new percentage.
> Hope this helps
> Regards
> Eric Dawson
>
> --------------------------------------------------------------------------
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Date: Fri, 26 Oct 2001 11:21:20 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Reid, Lorraine" <[log in to unmask]>
Subject: Land Patterns
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Fri, 26 Oct 2001 13:42:54 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Land Patterns
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Hi Lorraine,
Usually the supplier of the part can recommend a good footprint for the =
device. Or you can use IPC's land pattern calculator at http://search.ipc.o=
rg/sm782/default.asp (be sure to have "cookies" on).
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> "Reid, Lorraine" <[log in to unmask]> 10/26 11:21 am >>>
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Fri, 26 Oct 2001 07:59:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Land Patterns
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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The correct IPC document number is IPC-SM-782. But you can verify patterns
that are not in the book by using the Land pattern calculator. It is on the
IPC web site. Click on the tab On-Line Resources & Databases. That page has
a link to the calculator. If you have any trouble with the variables in the
calculation give me a call.
Other than that you can use the land patterns suggested by the Manufacturer
of the component. They can get you in trouble. IMHO, the manufacturers
optimize for density. The IPC patterns are optimized for process yield . . .
did I just start something?
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Reid, Lorraine
> Sent: Friday, October 26, 2001 6:21 AM
> To: [log in to unmask]
> Subject: [TN] Land Patterns
>
>
> Can anyone point me to a good reliable resource for land patterns for
> devices which are not in IPC-SM-762?
>
> I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
> none of which seem to be covered in the standards!
>
> thanks in advance,
>
> Lorraine Reid
>
> ------------------------------------------------------------------
> ---------------
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> additional
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> 847-509-9700 ext.5315
> ------------------------------------------------------------------
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>
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Date: Fri, 26 Oct 2001 07:59:14 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: BGA Component Baking - Plastic Body
In-Reply-To: <[log in to unmask]>
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Jeff said in his message that they baked the part, reballed the part and
directly placed it in a dry box. IMHO they will be safe. You are correct. If
they let the material set on the shop floor for two man days before they
complete rework they may have trouble . . . they know better than that.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
> Sent: Friday, October 26, 2001 4:08 AM
> To: [log in to unmask]
> Subject: Re: [TN] BGA Component Baking - Plastic Body
>
>
> Guy,
>
> I am a bit concerned about your suggestion about not baking the BGA's
> without knowing what their exposure time is. If they haven't been
> monitored, or have been out of a dry cabinet for 16 hours or more in total
> since previous bake or since removal from their original barrier
> bags, it's
> safer to bake them after re-balling them. This is to minimise the risk of
> delamination or popcorning when they placed back on the boards and
> subjected to reflow.
>
> I think you're right that both J-STD-20 and J-STD-33 are free downloads
> from the IPC site.
>
> Peter Duncan
>
>
>
>
>
> Guy Ramsey
> <gramsey@ACIU To: [log in to unmask]
> SA.ORG> cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> Sent by: Aero/ST Group)
> TechNet Subject: Re: [TN]
> BGA Component Baking -
> <[log in to unmask] Plastic Body
> ORG>
>
>
> 10/26/01
> 04:27 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum."
>
>
>
>
>
>
> We would not bake the parts again, after reballing, sounds like
> you will be
> meeting the requirments of the standard. I think it is a free download. If
> you need the link let me know and I will try to find it. Might
> have been on
> the ANSI page or JEDEC.
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Jeff Ferry
> > Sent: Thursday, October 25, 2001 9:45 AM
> > To: [log in to unmask]
> > Subject: [TN] BGA Component Baking - Plastic Body
> >
> >
> > BGA Guru's,
> >
> > We're doing a big project that requires removal/replacement of several
> > hundred plastic BGA components. After removal we'll be reballing the
> BGA's
> > and then reinstalling them. These are new builds, they're not
> coming back
> > from the field.
> >
> > Who knows what J-STD-20, or any other reference, says about prebaking
> > temp/time to eliminate possible moisture problems in the components or
> > boards prior to initial removal? Removed parts will be stored in a
> > desiccant chamber before and after reballing. Do we need to bake these
> > parts again prior to installation? Do ya'all normally bake new
> > build boards
> > in this situation?
> >
> > Thanks for you recommendations.
> >
> > Jeff Ferry
> > CEO
> > Circuit Technology Center, Inc.
> >
> > ------------------------------------------------------------------
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>
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Date: Fri, 26 Oct 2001 08:33:58 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Reflow profiling
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Good plan. I would add a reminder. Some packages have internal structures to
conduct heat away from active device(s) in the package. These may not be
represented in the dummy component, and can result in an oven profile that
is too cool.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
> Sent: Thursday, October 25, 2001 10:00 PM
> To: [log in to unmask]
> Subject: Re: [TN] Reflow profiling
>
>
>
> I also am involved with high mix, low volume builds, and I try to get one
> board of each type from the fab house that has failed electrical with
> internal shorts or whatever (cheaper than sacrificing a good
> board). I then
> buy in a stack of dummy components from Practical Components or
> Topline and
> populate the profile board with those. I don't bother with discrete
> passives, as they contribute precious little to the thermal mass. The
> thermal profile board is them reflowed using the standard profile supplied
> by the solder manufacturer.
>
> For BGA's and so forth, I then drill a hole up through the board into one
> of the central contacts to take a thermocouple wire, which is bonded in
> place, and add other thermocouples around the board. plug them all into a
> high-temp data logger
>
>
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Date: Fri, 26 Oct 2001 07:34:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hillman <[log in to unmask]>
Subject: Re: Adjusting the alloy composition in the solderpot
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Phil! The latest and greatest information on tin whiskering phenomena
was given by Mike Toben and Rob Schetty at the IPC Fall meeting in Orlando.
Their presentations are contained in the Conference proceedings. Also check
out this paper:
http://download.lead-free.org/downloads/Baudry_STMicro_FIB_LeadFree_Plating_Analysis.pdf
The researchers used Focused Ion Beam (FIB) microscopy to get a view of the "root" of a whisker (after seeing
the pictures I now know what I want for Xmas!). The FIB paper correlates very well with the Toben/Schetty presentations - we
might be finally getting close to understanding the cause of tin whiskering.
Dave Hillman
Rockwell Collins
[log in to unmask]
"Crepeau, Phil" <[log in to unmask]>@ipc.org> on 10/25/2001 06:25:52 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
hi,
does reflowed tin grow whiskers? i thought whiskers grew from plated tin
that's under stress. i also thought that one way to correct this was to
reflow the plated tin.
phil
-----Original Message-----
From: Bogert [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 3:13 PM
To: [log in to unmask]
Subject: Re: [TN] Adjusting the alloy composition in the solderpot
Wrong. Pure tin will grow tin whiskers.
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Date: Fri, 26 Oct 2001 09:02:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Land Patterns
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Not finding the patterns in IPC, I would consult the "suggested land
patterns" of the manufacturer's of those devices. Technical support, or
engineering support of the companies that manufacture the component spec'd
in should be able to provide you with suggested land patterns and
recommended soldering profiles.
--Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Reid, Lorraine
Sent: Friday, October 26, 2001 6:21 AM
To: [log in to unmask]
Subject: [TN] Land Patterns
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Fri, 26 Oct 2001 09:14:38 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Encapsulation Voids
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Good morning everyone.
Today we have a situation where we have our "Lore and Legend" of
business (or "that's the way we've always done it") versus what a vendor
will supply. Now let my unscramble this for you. We make systems that
use high voltage coils encapsulated in epoxy. Our practice for many
years is to not accept any voids (that we could see on the surface) in
the finished encapsulated item. Generally we can achieve this by
pouring the epoxy into the mold while it is at roughing pressure or
under low vacuum. If there was a void we never accepted the unit even
if it was patched because of a concern about punch through because of a
poor bond, dirt or other "conductive" gunk possible trapped under the
patch. We won't go into the waste generated or process control here,
that's a separate discussion.
We now have a unit that is being potted by an outside vendor. One unit
came in with a visibly patched void. We rejected it because of our
undocumented culture of "no voids". The outside vendor says they will
not guarantee void free potting. So now we can either eat the cost of
this unit or use it.
What is a generally accepted practice for encapsulation or potting
regarding visible voids and patching?
Do you flat out reject it or do you consider the application and the
location of the void/patch?
I'd appreciate your views as we will be meeting on this subject and I'd
like to have some external opinions as reference when discussing the
merits of accepting repaired voids.
Thanks in advance,
Phil Nutting
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Date: Fri, 26 Oct 2001 08:09:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: SMT part with Backside Ground
Sasha
I like your idea about the wave solder but unfortunatly it wont work with
this application. The are MICRO BGAs on both sides of the board. The
backside ground part is on the top side ( with MINi leds) and there are
unsealed mini pots on the bottom.
What we did find was a discrepancy in the customers gerbers. The paste
layer was too small for the amount of pad. We are going to attempt a
modification of the stencil by opening up 2 narrow slots radiating out from
the existing appature.
Thanks for all the ideas
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Date: Fri, 26 Oct 2001 08:16:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Chloride levels
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Is there a standard for acceptable levels of chloride on assembled PCBs and
on bare boards? What sources of chlorides exist in a board fabrication
process, and in an assembly process?
We are using a no-clean low-solid flux.
*Cheryl, the short answer to your first question is NO. There are no
standards yet for "acceptable" levels of chloride (or other anions) in
printed wiring assemblies, and I doubt there ever will be. The main reason
is that most of us realize that there are no more golden numbers, no one
value that can be blindly applied across the board without considering the
function of the assembly or the end use environment. Most of us can
remember back to the "good old days" of rosin flux and Freon cleaning,
where we could use the military specs and the single pass-fail value for
ROSE testers, regardless of whether it was a garage door opener or a
controller board for the radar on an Aegis warship. Them days is gone and
so is a single pass-fail value. I think the best you will get is
standardized protocols on how to determine how clean you need to be for
YOUR product. It is harder work for you, but better for your product in
the long run.
What sources of chloride exist? Consider chloride in the workplace to be
as prevalent as nitrogen in the air, as corruption in Washington, as empty
Diet Mt. Dew containers in Doug Pauls' cubicle..... but I digress.
Chloride is in your finger salts, metal plating salts, fluxes, cleaning
solutions, and as constituent elements of most resins. It is everywhere.
What YOU need to do is determine how much chloride is bad for YOUR hardware
in YOUR end use environment.
The recommended chloride levels used by CSL are a good starting point, and
I emphasize starting point. You need to do correlation studies between ion
chromatography and environmental stress tests in humid environments on
actual product to determine the amount of acceptable chloride. If you have
an in-house ROSE/SEC tester (or as I call them, artificial reef materials),
then you can expand the correlation study to determine what ROSE values you
should be using for process control for your hardware.
People have asked where the CSL numbers come from. As I was technical
director there for 8 years, I'll tell you. Over half of the work done at
CSL was failure analysis. Products coming back from the field with
electrochemical failures (corrosion, metal migration, leakage). Ion
chromatography was done on the failures to determine "bad" levels of
anions. Then we would work with the client to examine the process and
determine where the big contributors to the bad anions were. Cleaning them
up to a "good" level solved the problem. Over time, you build up a
histogram of "bad" and "good" levels. The recommended CSL levels are the
general dividing lines between "good" and "bad".
I will correct Mr. Sedlak on his response. Ion chromatography is ion
specific and can give you accurate chloride levels. A ROSE or SEC tester
(e.g. Omegameter) gives outputs in micrograms of sodium chloride
EQUIVALENCE per unit area, and has nothing to do with the actual amount of
chloride or sodium on the board. It is merely a reference to an easily
ionizable salt. So you can't use an Omegameter (or others) to determine
how much chloride is present.
I would suggest that you take a look at J-HDBK-001, the companion handbook
to J-STD-001. Section 8 goes into more detail on cleaning and cleanliness.
The IPC Ionic Conductivity / Ion Chromatography Task Group, chaired by
Terry Munson, CSL, is working on a tutorial or state of the art paper on
ionic measurement, which just kicked off a few weeks ago.
Doug Pauls
Rockwell Collins
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Date: Fri, 26 Oct 2001 09:54:17 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jon Moore <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
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In a message dated 10/25/2001 10:47:54 AM US Eastern Standard Time,
[log in to unmask] writes:
<< Does anyone have any suggestions for
alternatives to high temp solder? >>
I have found that holding the T/C in place with a piece of aluminum tape will
get almost exactly the same results as a soldered T/C.
Jon Moore
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Date: Fri, 26 Oct 2001 09:55:50 -0400
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ed Tordahl <[log in to unmask]>
Subject: LIDC October 23rd Kickoff Meeting.
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Hello All,
The following are minutes from the Long Island IPC Designers Council October
23rd Kickoff Meeting.
Thanks to Bill Gillespie for providing the minutes!
On October 23 the Long Island Designers Council held its first meeting. The
meeting was held at Miteq Corporation in Hauppauge, thank you to James
Klepper, Manager of Engineering Services at Miteq.
The initial meeting focused on the Designers Council, its purpose and what
it can do for you, and what the plans are for the near future. Gary Ferrari
of the IPC gave a presentation outlining this. Among the topics he talked
about was the IPC hierarchy structure, how to set up a successful chapter,
the advantages of being a member versus a non-member, discounts for members
and the chapter in purchasing materials such as IPC standards, video's and
video workshops. Also the chance to represent Long Island at yearly IPC
meetings, and to be a part of standardization committees that are currently
working on the standards that we all use in our every day Design
environment. In short giving Long Island a voice to address issues local to
our region.
Next up was Ed Tordahl who has taken on the responsibly of President of the
chapter. Ed presented a sideshow outlining the chapter goals, he also
stressed some points that Gary had addressed, mainly what the Chapter had to
offer you, and the advantages of being a member. Ed also talked about a two
2 trends that seemed local to this region, 1.) Most companies do not think
of Designers as value assets. In fact most companies balk at the idea a
paying Designers to go to workshops or seminars. 2.) That Designers seem to
have a false comfort level, thinking that they will be at their company
forever, or that they know enough already. Ed also talked about that the
only one responsible for your career is yourself, you cannot wait for
someone to hand you something, this will probably never happen. If you want
to prepare yourself for the future then you will have to take matters into
your hands yourself. Most of the current core members feel exactly this way,
having paid for training, workshops and seminars out of their own pocket. (A
small price to pay for your future) However the core group will be working
to provide these services to our members at little to no cost. This includes
Designer Certification (CID) John Bohenek of Brookhaven Labs will be heading
up this effort. Also in the works are guest speakers, these speakers are
well known on the IPC seminars/workshop circuit, this effort is being lead
by Bill Gillespie of L3-Satellite Networks.
The current core members are;
President Ed Tordahl
Vice President Bill Gillespie
Education John Bohenek
Communications Ron Ryan
The turnout for this meeting was good; all who attended were serious about
their careers, and how to improve themselves. From the first meeting we were
able to attract additional core members who along with the current core
members will work (on their own time) towards providing Long Island
Designers with the training, information, services and networking required
for career advancement in any economic environment.
Anyone in the PCB Industry on Long Island wishing to be a part of this group
contact
Ed Tordahl [log in to unmask]
Bill Gillespie [log in to unmask]
Ron Ryan [log in to unmask]
Thank You all......
AYS,
Edward S. Tordahl, MCSE
Engineering Services Supervisor/MIS
CEM ltd. (formerly 4DI inc.)
700 Blue Point Rd.
Holtsville, NY 11742
V:(631)758-8100 F:(631)758-8101
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Date: Fri, 26 Oct 2001 15:30:18 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Cleaning paste when mis-aligned.
MIME-Version: 1.0
Content-Type: text/plain
Hello All & the mountain dew man.
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
particles?
Is there any danger of damaging innerlayers of PCB?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
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The views expressed in this E-mail are those of the author, and do not
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otherwise expressly indicated.
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Date: Fri, 26 Oct 2001 10:38:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Looking for Industrial X-ray machine
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As a follow on topic to the encapsulating voids, we periodically have
the need for a system to x-ray failed potted assemblies to determine the
cause of failure. Sometimes this can be accomplished by sawing the unit
in half, but sometimes we need to look inside without destroying the
item. We could build a system, but a recent sanity check suggested that
by buying an industrial unit it would come with all the necessary
guards, precautions and certifications that a home made unit might not.
Our sample size is usually no larger than a 6 inch cube. Naturally
tomorrow someone will need to x-ray something larger than a six inch
cube so a little flexibility would be nice.
I'm interested in knowing what is out there, what is good and bad and
relative cost.
I can be contacted offline at [log in to unmask] or
978-922-9300.
Thanks in advance,
Phil Nutting
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Date: Fri, 26 Oct 2001 10:32:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Linda Langley <[log in to unmask]>
Subject: Tinning Solder Tips
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We are currently doing rework with Alpha Pure Cure Wire Solder which is very
corrosive to our solder tips. I want to use Alpha Energized-Plus RA Wire
Solder to tin the tips. Does anyone have any information if this practice
would be harmful for the solder joints or if a small amount was used and
wiped off with a clean sponge would be acceptable.
Linda Langley
Training Specialist
(248) 292-6176
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Date: Fri, 26 Oct 2001 09:45:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Tontis <[log in to unmask]>
Subject: Re: Land Patterns
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I would give http://www.pcbstandards.com/index1.html A look over.
Ted
-----Original Message-----
From: Dean Lillibridge [mailto:[log in to unmask]]
Sent: Friday, October 26, 2001 8:02 AM
To: [log in to unmask]
Subject: Re: [TN] Land Patterns
Not finding the patterns in IPC, I would consult the "suggested land
patterns" of the manufacturer's of those devices. Technical support, or
engineering support of the companies that manufacture the component spec'd
in should be able to provide you with suggested land patterns and
recommended soldering profiles.
--Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Reid, Lorraine
Sent: Friday, October 26, 2001 6:21 AM
To: [log in to unmask]
Subject: [TN] Land Patterns
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Fri, 26 Oct 2001 17:53:40 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Cleaning paste when mis-aligned.
MIME-Version: 1.0
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Yes, but use the right solvent
No
Brian
Cathy Killen wrote:
>
> Hello All & the mountain dew man.
> Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
> particles?
> Is there any danger of damaging innerlayers of PCB?
>
> Thanks in advance.
>
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
> The information contained in the E-mail is confidential. It is intended only
> for the stated addressee(s) and access to it by any other person is
> unauthorised.
> The views expressed in this E-mail are those of the author, and do not
> represent the views of Smtek Europe, its associates or subsidiaries, unless
> otherwise expressly indicated.
> Please note: It is your responsibility to scan this E-mail for viruses.
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> the BODY (NOT the subject field): SIGNOFF Technet
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Fri, 26 Oct 2001 10:52:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Cleaning paste when mis-aligned.
In-Reply-To: <A1630D6F27C0D21198AF00805F613595465F31@DDLSBS>
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Probably not. The mechanisms by which ultrasonic cleaning damages electronic
components should not damage the internal layers of a PWB. No embedded
components?
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Cathy Killen
> Sent: Friday, October 26, 2001 10:30 AM
> To: [log in to unmask]
> Subject: [TN] Cleaning paste when mis-aligned.
> Importance: High
>
>
> Hello All & the mountain dew man.
> Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
> particles?
> Is there any danger of damaging innerlayers of PCB?
>
> Thanks in advance.
>
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
>
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Date: Fri, 26 Oct 2001 10:56:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Tinning Solder Tips
In-Reply-To: <[log in to unmask]>
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In a former life we used Alpha Engergized Plus RA wire without ill effects
on the tips.
Presently, we use Reliacore 11, also with no ill effects Reliacore is less
active.
I am not familiar with Pure Cure Wire, your Alpha rep should be able to help
you identify any potentials for chemistry conflicts.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Linda Langley
> Sent: Friday, October 26, 2001 10:33 AM
> To: [log in to unmask]
> Subject: [TN] Tinning Solder Tips
>
>
> We are currently doing rework with Alpha Pure Cure Wire Solder
> which is very
> corrosive to our solder tips. I want to use Alpha Energized-Plus RA Wire
> Solder to tin the tips. Does anyone have any information if this practice
> would be harmful for the solder joints or if a small amount was used and
> wiped off with a clean sponge would be acceptable.
>
> Linda Langley
> Training Specialist
> (248) 292-6176
>
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Date: Fri, 26 Oct 2001 08:02:37 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Cleaning paste when mis-aligned.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Cathy: This should not be a problem for the bare (unloaded) PCB. However if
you are doing a double sided reflow and misprint the second side you need
to verify that the first side components are compatible with the ultrasonics
you are using.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Cathy Killen [mailto:[log in to unmask]]
Sent: Friday, October 26, 2001 7:30 AM
To: [log in to unmask]
Subject: [TN] Cleaning paste when mis-aligned.
Importance: High
Hello All & the mountain dew man.
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
particles?
Is there any danger of damaging innerlayers of PCB?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
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Date: Fri, 26 Oct 2001 11:17:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Racks plating up
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey Sean,
Do these racks have a cover that seals the contacts off from the bath? I've
seen impressive rack plating when the contact's cover got stuck open.
Electroless plating is designed to put copper on non-conductive surfaces.
If you are talking electrolytic plating (panel & pattern) then the racks are
completing the circuit somehow.
I'd hazard a guess that you'll eventually have to either replace, recoat or
just stop using these racks. Once the plated metal is there it'll continue
to build up everytime you use them. In the short term, you might try
peeling the plated metal off with a non-scratching scrapper or using a
strong etch bath between runs (well ventilated area a must). And since that
metal isn't getting plated onto the boards it adds to your costs. If this
just started happening you might notice your chemistry adds getting bigger.
When I first started in this biz ('98) we were still using ancient racks
with uncoated wing nuts. Talk about extra plating - up, down and all
around. After a week or so the nodules could cut through your gloves easy.
It can be a real pain if your hand slips when your scrapping it off.
Hans
Integrity First - Service Before Self - Excellence in All We Do
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
Special Operations Forces System Program Office (SOF - SPO)
Gunship Team
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Sean Clinton [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 4:57 PM
To: [log in to unmask]
Subject: [TN] Racks plating up
Hi All,
I have a slight problem that I want to avoid turning into a major costly
issue. I have a few plating racks that are starting to be overrun with
wild plating ( copper and tin) up the rack away from the contacts in areas
that are not supposed to be plating. There are even areas of isolated
plated metal surrounded by plastic. Upon inspection, I was able to peel
off the plated tin and copper and noticed several layers. I think this is
most likely due to multiple plating cycles.
The racks are solid copper core with a plastic shrouding. The manufacturer
claims that "no rack stripping" is needed. In the universe where I am
from, most plastics aren't conductive and don't plate. I understand that
once initiated, the plating will propagate in the path of least resistance,
but what is causing it?
My suspicions include poor rinsing of the racks (conductive salts
remaining?) after a plating cycle or conductive carbon (from our Shadow
process) getting into scratches in the plastic shrouds and eventually
arcing causing this plating, but I haven't been able to confirm or disprove
either theory yet. It's not affecting quality, but I don't want to wait
until it does. Is there some preventative measure to eliminate the problem
that anyone has tried?
Thanks,
Sean Clinton
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Date: Fri, 26 Oct 2001 08:31:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Racks plating up
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Sean: It is not unusual for plating deposits to start building on older
plastic coated racks. After X number of cycles thru cleaners, microetches
etc the plastic surface becomes porous and absorbs conductive chemistries.
Any type of conductive material such as palladium or carbon will only make
it worse but are not necessary to make this happen. Small electroplated
sites begin to form that continue to build with each additional cycle.
These plated up areas can either be chemically or as you have done manually
stripped. Chemical stripping is typically much faster if you have a lot of
racks and it also strips out most of the material seated down into the
plastic coated surface. However you need to make sure your stripping
chemistry is compatible with the plating you are stripping, the type of
plastic coating you are using and the rack contact areas. There are both
proprietary and generic(nitric acid)products available. Don't forget you
will now generate an additional waste by-product.
Typically after a few years, depending on your usage and application, the
coated racks are stripped and recoated.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Sean Clinton [mailto:[log in to unmask]]
Sent: Thursday, October 25, 2001 1:57 PM
To: [log in to unmask]
Subject: [TN] Racks plating up
Hi All,
I have a slight problem that I want to avoid turning into a major costly
issue. I have a few plating racks that are starting to be overrun with
wild plating ( copper and tin) up the rack away from the contacts in areas
that are not supposed to be plating. There are even areas of isolated
plated metal surrounded by plastic. Upon inspection, I was able to peel
off the plated tin and copper and noticed several layers. I think this is
most likely due to multiple plating cycles.
The racks are solid copper core with a plastic shrouding. The manufacturer
claims that "no rack stripping" is needed. In the universe where I am
from, most plastics aren't conductive and don't plate. I understand that
once initiated, the plating will propagate in the path of least resistance,
but what is causing it?
My suspicions include poor rinsing of the racks (conductive salts
remaining?) after a plating cycle or conductive carbon (from our Shadow
process) getting into scratches in the plastic shrouds and eventually
arcing causing this plating, but I haven't been able to confirm or disprove
either theory yet. It's not affecting quality, but I don't want to wait
until it does. Is there some preventative measure to eliminate the problem
that anyone has tried?
Thanks,
Sean Clinton
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Date: Fri, 26 Oct 2001 08:41:21 -0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Maxwell <[log in to unmask]>
Subject: Re: Encapsulation Voids
In-Reply-To: <[log in to unmask]
sys.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Phil,
You raise an interesting point. The real issue has to do with voids between
high voltage points within the structure. Interesting things happen at high
voltage and one is partial discharge arcing. Spacing, void size and voltage
between points where a void resides are all critical but if there is
partial discharge present internally then you can run into reliability
problems. It gets interesting when one starts this testing because there
are two distinct PD mechanisms present, Townsend discharges characterized
by fast duration (<10nS) and low charge transfer (<100pC) at corona
inception voltage (CIV). Townsend type discharges are normal and usually do
not lead to long term problems. The other and what you need to avoid is
streamer type discharges characterized by longer duration (>100nS) and high
charge transfer (>120pC) at CIV. These types of discharges are detrimental
to long term reliability and must be avoided. This requires PD test
equipment typically made by Biddle and a few others and using these tools
will allow you to have an objective acceptance criteria. Clearly you will
need to characterize what is good and bad and then perform a lot of cross
sectioning to verify your results.
I enjoyed working in this arena and found it fascinating finding and
correlating these types of defects in the past. Have fun.
John Maxwell
>Good morning everyone.
>
>Today we have a situation where we have our "Lore and Legend" of
>business (or "that's the way we've always done it") versus what a vendor
>will supply. Now let my unscramble this for you. We make systems that
>use high voltage coils encapsulated in epoxy. Our practice for many
>years is to not accept any voids (that we could see on the surface) in
>the finished encapsulated item. Generally we can achieve this by
>pouring the epoxy into the mold while it is at roughing pressure or
>under low vacuum. If there was a void we never accepted the unit even
>if it was patched because of a concern about punch through because of a
>poor bond, dirt or other "conductive" gunk possible trapped under the
>patch. We won't go into the waste generated or process control here,
>that's a separate discussion.
>
>We now have a unit that is being potted by an outside vendor. One unit
>came in with a visibly patched void. We rejected it because of our
>undocumented culture of "no voids". The outside vendor says they will
>not guarantee void free potting. So now we can either eat the cost of
>this unit or use it.
>
>What is a generally accepted practice for encapsulation or potting
>regarding visible voids and patching?
>Do you flat out reject it or do you consider the application and the
>location of the void/patch?
>
>I'd appreciate your views as we will be meeting on this subject and I'd
>like to have some external opinions as reference when discussing the
>merits of accepting repaired voids.
>
>Thanks in advance,
>
>Phil Nutting
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=========================================================================
Date: Fri, 26 Oct 2001 10:34:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: J Larson <[log in to unmask]>
Subject: Re: Chloride levels
I think that it is really important to remember that using IC testing will
measure your process capability and is a tool to verify that your process
is in control. IE that you are not adding any contaminants to your board.
I disagree that the numbers CSL or IPC 610 has come up with mean anything
though - if you tested a complete assembly and the chloride levels per cm
squared were grossly higher than a published number this doesn't really
mean that you suddenly have a problem. It means you have alot work left to
do in order to determine if there is a problem. Three months down the road
if the number is the same you can feel comfortable that your process hasn't
changed.
The biggest thing I feel about IC testing is that it is like a computer, it
will only tell you what you tell it to.
It is not a miracle test and will not solve your problems for you, apply
common sense and engineering practice with a grain of salt ; )
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Date: Fri, 26 Oct 2001 11:46:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
MIME-Version: 1.0
Content-Type: multipart/alternative; boundary="=_alternative 005688CA87256AF1_="
This is a multipart message in MIME format.
--=_alternative 005688CA87256AF1_=
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Mike and Guy,
We routinely clean the second side of misprint solder paste, but from what
you are saying perhaps there could be a problem with damaging some
components. The components that we clean in the ultrasonic cleaner are
mostly flat chip package, C lead diodes, and some SOT-23 and SOIC. How do
I verify which components can or cannot go in the cleaner? Is there any
test data out there to support this issue? Though we clean very few
misprints, I am a little concerned. Thanks for your help!
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
"Barmuta, Mike" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
10/26/01 09:02 AM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: Re: [TN] Cleaning paste when mis-aligned.
Cathy: This should not be a problem for the bare (unloaded) PCB. However
if
you are doing a double sided reflow and misprint the second side you
need
to verify that the first side components are compatible with the
ultrasonics
you are using.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Cathy Killen [mailto:[log in to unmask]]
Sent: Friday, October 26, 2001 7:30 AM
To: [log in to unmask]
Subject: [TN] Cleaning paste when mis-aligned.
Importance: High
Hello All & the mountain dew man.
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
particles?
Is there any danger of damaging innerlayers of PCB?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended
only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries,
unless
otherwise expressly indicated.
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--=_alternative 005688CA87256AF1_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Mike and Guy,</font>
<br>
<br><font size=2 face="sans-serif">We routinely clean the second side of misprint solder paste, but from what you are saying perhaps there could be a problem with damaging some components. The components that we clean in the ultrasonic cleaner are mostly flat chip package, C lead diodes, and some SOT-23 and SOIC. How do I verify which components can or cannot go in the cleaner? Is there any test data out there to support this issue? Though we clean very few misprints, I am a little concerned. Thanks for your help!</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>"Barmuta, Mike" <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">10/26/01 09:02 AM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: Re: [TN] Cleaning paste when mis-aligned.</font></table>
<br>
<br>
<br><font size=2 face="Courier New">Cathy: This should not be a problem for the bare (unloaded) PCB. However if<br>
you are doing a double sided reflow and misprint the second side you need<br>
to verify that the first side components are compatible with the ultrasonics<br>
you are using.<br>
<br>
<br>
Regards<br>
<br>
Michael Barmuta<br>
<br>
Staff Engineer<br>
<br>
Fluke Corp.<br>
<br>
Everett WA<br>
<br>
425-446-6076<br>
<br>
-----Original Message-----<br>
From: Cathy Killen [mailto:[log in to unmask]]<br>
Sent: Friday, October 26, 2001 7:30 AM<br>
To: [log in to unmask]<br>
Subject: [TN] Cleaning paste when mis-aligned.<br>
Importance: High<br>
<br>
<br>
Hello All & the mountain dew man.<br>
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste<br>
particles?<br>
Is there any danger of damaging innerlayers of PCB?<br>
<br>
Thanks in advance.<br>
<br>
Cathy Killen<br>
Training Instructor<br>
Smtek Europe Ltd.<br>
The information contained in the E-mail is confidential. It is intended only<br>
for the stated addressee(s) and access to it by any other person is<br>
unauthorised.<br>
The views expressed in this E-mail are those of the author, and do not<br>
represent the views of Smtek Europe, its associates or subsidiaries, unless<br>
otherwise expressly indicated.<br>
Please note: It is your responsibility to scan this E-mail for viruses.<br>
<br>
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Date: Fri, 26 Oct 2001 17:46:06 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Mime-Version: 1.0
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Earl
Well, I think some acceptance criteria is necessary since if there isn't =
even no solder is accepted. However, I agree that in many cases I feel =
that the acceptance criteria mare more designed in a manner that they can =
be controlled rather than in respect to reliability.
Regarding your comment of IMC and the discussion we had offline I thought =
abut the thing at home:
- Suppose you do a good job in designing your solder profile. This means, =
in my understanding, that just enough heat is brought into a PCB that all =
joints are formed and as little heat as possible stresses the components. =
As an effect the IMC will be very thin.
- Suppose again that you rework. Again you do a good job in removing the =
remaining tin thoroughly. To do so you need to keep the pad to be cleaned =
at elevated temperature for quite a while.
The result will be, that=20
- Because of thoroughly removing the solder you expose IMC or
- Because the IMC is thin and the pad is warm for some time the remaining =
little amount of tin that covers the IMC is transformed into IMC.
Hence, one can say that a job too well done leads to a poor solder joint. =
And thus ( just to steer the pot a bit as you like it) if you instruct =
people for repairing solder joints and it works, your instruction wasn't =
too accurate? ( HeHe)
Have a great weekend
Ps: What do you mean by : you spoke with someone who is also much =
respected in this field?
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Fri, 26 Oct 2001 08:59:08 -0700
Reply-To: Leo Roos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Leo Roos <[log in to unmask]>
Subject: Re: Chloride levels
MIME-Version: 1.0
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See IPC spec. SM-840 C
Leo Roos
----- Original Message -----
From: "Cheryl White" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 1:36 PM
Subject: [TN] Chloride levels
> Is there a standard for acceptable levels of chloride on assembled PCBs
and
> on bare boards? What sources of chlorides exist in a board fabrication
> process, and in an assembly process?
>
> We are using a no-clean low-solid flux.
>
> Thanks,
> Cheryl White
> Manufacturing Engineering
> DSC Ltd.
> [log in to unmask]
> (905) 760-3000 ext. 7228
>
> --------------------------------------------------------------------------
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E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
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Date: Fri, 26 Oct 2001 11:21:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Land Patterns
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Check out the Manufacturer of the device. Most all publish suggested land =
patterns. =20
Kathy=20
--=_87DD6880.F594F981
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<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Check out the Manufacturer of the device. Most all publish suggested
land patterns. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Fri, 26 Oct 2001 10:30:11 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
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Guenter,
As you replied to me personally, I respected your not posting on the
TechNet. So, I said it was someone else but everyone knows it must be you.
Simply, I didn't/don't want to betray your confidence as I respect your
privacy.
Earl
ps. I am enjoying this and learning much from this conversation. Still, I am
stirring the pot for everyone to benefit. I'm too old to add much but if I
can elicit responses from real experts, like you, we will all learn more
Earl
----- Original Message -----
From: "Guenter Grossmann" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, October 26, 2001 8:46 AM
Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Earl
Well, I think some acceptance criteria is necessary since if there isn't
even no solder is accepted. However, I agree that in many cases I feel that
the acceptance criteria mare more designed in a manner that they can be
controlled rather than in respect to reliability.
Regarding your comment of IMC and the discussion we had offline I thought
abut the thing at home:
- Suppose you do a good job in designing your solder profile. This means, in
my understanding, that just enough heat is brought into a PCB that all
joints are formed and as little heat as possible stresses the components. As
an effect the IMC will be very thin.
- Suppose again that you rework. Again you do a good job in removing the
remaining tin thoroughly. To do so you need to keep the pad to be cleaned at
elevated temperature for quite a while.
The result will be, that
- Because of thoroughly removing the solder you expose IMC or
- Because the IMC is thin and the pad is warm for some time the remaining
little amount of tin that covers the IMC is transformed into IMC.
Hence, one can say that a job too well done leads to a poor solder joint.
And thus ( just to steer the pot a bit as you like it) if you instruct
people for repairing solder joints and it works, your instruction wasn't too
accurate? ( HeHe)
Have a great weekend
Ps: What do you mean by : you spoke with someone who is also much respected
in this field?
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Fri, 26 Oct 2001 11:26:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Encapsulation Voids
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I dealt with this issue about two years ago. Some of the voids we had =
found were quite large and exposed the internal circuitry but others were =
very small and didn't expose the internals. We ended up making a size =
maximum which at that application was .020". If the part had a void that =
was larger than that it was unacceptable but if it was smaller than that =
we allowed a small patch. The application wasn't affected by patches. We =
were more worried about entrappment through wave and wash. =20
Kathy=20
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<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I dealt with this issue about two years ago. Some of the voids we had
found were quite large and exposed the internal circuitry but others were very
small and didn't expose the internals. We ended up making a size maximum
which at that application was .020". If the part had a void that was
larger than that it was unacceptable but if it was smaller than that we allowed
a small patch. The application wasn't affected by patches. We were
more worried about entrappment through wave and wash. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Fri, 26 Oct 2001 11:31:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
As in some past messages, I thought I was replying to Guenter personally. I
don't know how this got posted and regret any inconvenience to Guenter.
Earl Moon
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Date: Fri, 26 Oct 2001 12:45:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads.. .
MIME-Version: 1.0
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TechNetters,
Questions of my sex aside.. got your attention now, right?
I will ask again what do people expect for the average thickness of the
tin/nickel intermetallic. The closest answer I got was the rate of growth,
but not what one expects it to start at after a single reflow. I bring it
up here as it is related to the current discussion.
regards,
Bev Christian
Resaerch in Motion
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: October 26, 2001 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA
pads...
Guenter,
As you replied to me personally, I respected your not posting on the
TechNet. So, I said it was someone else but everyone knows it must be you.
Simply, I didn't/don't want to betray your confidence as I respect your
privacy.
Earl
ps. I am enjoying this and learning much from this conversation. Still, I am
stirring the pot for everyone to benefit. I'm too old to add much but if I
can elicit responses from real experts, like you, we will all learn more
Earl
----- Original Message -----
From: "Guenter Grossmann" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, October 26, 2001 8:46 AM
Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
Earl
Well, I think some acceptance criteria is necessary since if there isn't
even no solder is accepted. However, I agree that in many cases I feel that
the acceptance criteria mare more designed in a manner that they can be
controlled rather than in respect to reliability.
Regarding your comment of IMC and the discussion we had offline I thought
abut the thing at home:
- Suppose you do a good job in designing your solder profile. This means, in
my understanding, that just enough heat is brought into a PCB that all
joints are formed and as little heat as possible stresses the components. As
an effect the IMC will be very thin.
- Suppose again that you rework. Again you do a good job in removing the
remaining tin thoroughly. To do so you need to keep the pad to be cleaned at
elevated temperature for quite a while.
The result will be, that
- Because of thoroughly removing the solder you expose IMC or
- Because the IMC is thin and the pad is warm for some time the remaining
little amount of tin that covers the IMC is transformed into IMC.
Hence, one can say that a job too well done leads to a poor solder joint.
And thus ( just to steer the pot a bit as you like it) if you instruct
people for repairing solder joints and it works, your instruction wasn't too
accurate? ( HeHe)
Have a great weekend
Ps: What do you mean by : you spoke with someone who is also much respected
in this field?
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Fri, 26 Oct 2001 11:52:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads.. .
Whatever and to whomever interested, whohaw is supposed to be wohaw to get
away from the film in which what's her name got naked and starred. Demi?
Anyway, the following is what ended up this way - partly.
Whohaw Guenter,
Your're fine and your messages are all received well. I just never knew you
had to remove the intermetallics, and with a glass brush. That's all I
meant.
I'm the one who's been on holiday. Even though only a few weeks, I must have
missed something during that time. You're helping me see more things than
ever before.
Thanks a million times over. And you know I like stirring the pot. Hell, I
just can't help it.
Please enjoy and thanks again,
MoonMan
----- Original Message -----
From: "Guenter Grossmann" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 8:14 AM
Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGApads...
Hey Moon Man
What bomb? Do you mean my comment about intermetallics? Well, gotta rub my
eyes, I never meant doing something wrong and I even didn't get the irony in
your comment. Seems as if I am still in a holiday mood.
You hoped to see something more from me. Hmmmm. What should I say?
- Every soldering process produces an intermetallic layer
- Intermetallics don't wet to my knowledge and I mean to know that this is
due to the formation of very stable oxides that won't solder either.
If you desolder and remove the remaining solder there is a real chance that
you expose intermetallics. More likely if you remove the solder thoroughly.
I had a case this summer that had nothing to do with rework but with
repeated reflow solder operations. The solder joints didn't look bad, but on
the pads that where not printed dewetting of the HASL could be seen. When we
made microsections we saw that the solder joints had areas where the solder
was touching the IMC but we observed a thin dark line. I wasn't sure
whether I see a preparation artefact or a real thing. However, 2 joints we
looked at had a clear separation between the IMC and the solder some um long
and I believe this was due to exposed intermetallics before the printing
took place. In the dewetted regions no solder was present on the copper only
intermetallics.
Sorry, that I upset you, I didn't mean to but I stand to my point: If you
repair and remove the remaining solder there is a good chance to expose
intermetallics, maybe only partially, and no soldering takes place in the
spots where the IMC was exposed.
Best regards
Guenter
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
Never a bother. Love the joke and say hi to the kids.
Besides the glass brush, my biggest concerns are about fine pitch and BGA
device types and the solder termination area topography they require (flat)
to effect placement, continued alignment, and subsequent reflow and
"acceptable" solder joint formation.
As you know and have observed many times, once device removal is effected,
the solder left is very uneven, to say the least. This, again as you know,
is why we wick off the solder left after the removal process.
This, then, is the dilemma as I see it. In your terms, we now expose an IMC
layer, to whatever extent, preventing solder "wetting" in some areas. I
guess, this is a random occurrence (where and how much IMC) is left.
Therefore, doesn't this point to sh luck to again effect "acceptable solder
joints?
Enjoy your kiddy romp,
Earl
----- Original Message -----
From: "Guenter Grossmann" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 25, 2001 8:37 AM
Subject: Rework
Sorry for bothering you again but I just had a thought:
1) Someone doing a job thoroughly an clean does his / her job good
2) Doing a job only partially is bad workmanship
3) Thoroughly removing solder exposes IMC and produces bad solder joints
4) Partially removing the remaining solder protects the IMC and leads to
acceptable solder joints according to MIL and ESA standards
ERGO: MIL and ESA standards support bad workmanship
( just a joke that came to my mind before I go of to play with my kids)
Have a great day
Guenter
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Date: Fri, 26 Oct 2001 12:11:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Chloride levels
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
I think that it is really important to remember that using IC testing will
measure your process capability and is a tool to verify that your process
is in control. IE that you are not adding any contaminants to your board.
*One valid use for IC, yes, but I would say more of process consistency
rather than process capability.
I disagree that the numbers CSL or IPC 610 has come up with mean anything
though - if you tested a complete assembly and the chloride levels per cm
squared were grossly higher than a published number this doesn't really
mean that you suddenly have a problem. It means you have alot work left to
do in order to determine if there is a problem. Three months down the road
if the number is the same you can feel comfortable that your process hasn't
changed.
*I agree with most of this, but argue that the numbers DO mean something.
In my original message, I indicated that the CSL numbers are a good
STARTING point. I should have expanded on that to say that if you don't
have a clue as to what your residue picture is now, then that might be a
good place to start. On the other hand, if you have a process that is in
control and you are not seeing failures in burn-in or from the field, IC
testing can tell you what levels of residues may correlate to that
acceptable performance. You then have a good idea of what is good for YOUR
hardware and YOUR end use environment.
The biggest thing I feel about IC testing is that it is like a computer, it
will only tell you what you tell it to.
It is not a miracle test and will not solve your problems for you, apply
common sense and engineering practice with a grain of salt ; )
*I respectfully disagree. Your statement implies that you can make IC say
whatever you want it to say. IC data, when properly generated and properly
interpreted, can be a very powerful tool for characterizing, optimizing,
and troubleshooting a process. IC is a tool. It has valid and invalid
uses. It has valid and invalid applications. It has valid and invalid
interpretations. I agree with yoru last statement that you have to use the
data wisely and not try to blindly apply numbers.
Doug Pauls
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Date: Fri, 26 Oct 2001 12:53:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Warren crow <[log in to unmask]>
Subject: Re: Land Patterns
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Date: Fri, 26 Oct 2001 11:08:50 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jana L. Carraway" <[log in to unmask]>
Subject: Looking for Joseph Fjelstad
In-Reply-To: <[log in to unmask]>
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Would anyone have an email address or phone number for Joe Fjelstad?
Thank you,
Jana Carraway
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Date: Fri, 26 Oct 2001 11:09:18 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject: Re: Land Patterns
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Another online site to try is http://www.pcdmag.com/
Under RESOURCES > SMT FOOTPRINTS
They have additional standard packages that IPC is missing.
Greg Scott
Cray Inc.
"Reid, Lorraine" wrote:
> Can anyone point me to a good reliable resource for land patterns for
> devices which are not in IPC-SM-762?
>
> I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
> none of which seem to be covered in the standards!
>
> thanks in advance,
>
> Lorraine Reid
>
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Date: Fri, 26 Oct 2001 14:14:34 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
In-Reply-To: <[log in to unmask]>
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I don't mean to cause any undue concern. The issue is fairly simple . . .
You can break glass and ceramic with sound but it is not likely if you are
careful. But ultrasonic cleaning can break wire bonds, and wires, this is
especially true in controls, ceramic ICs and the like were the wires are not
encapsulated and subject to vibration. There are technologies that are
effective in reducing this type of damage. Hope this relieves your fear. If
you are still concerned then you have some homework to do. What frequency
and power does you cleaner work at. What is a construction of the packages
in question . . . stuff like that.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: Friday, October 26, 2001 11:46 AM
To: [log in to unmask]
Subject: Re: [TN] Cleaning paste when misaligned.
Mike and Guy,
We routinely clean the second side of misprint solder paste, but from what
you are saying perhaps there could be a problem with damaging some
components. The components that we clean in the ultrasonic cleaner are
mostly flat chip package, C lead diodes, and some SOT-23 and SOIC. How do I
verify which components can or cannot go in the cleaner? Is there any test
data out there to support this issue? Though we clean very few misprints, I
am a little concerned. Thanks for your help!
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
"Barmuta, Mike" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
10/26/01 09:02 AM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: Re: [TN] Cleaning paste when mis-aligned.
Cathy: This should not be a problem for the bare (unloaded) PCB. However
if
you are doing a double sided reflow and misprint the second side you
need
to verify that the first side components are compatible with the
ultrasonics
you are using.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Cathy Killen [mailto:[log in to unmask]]
Sent: Friday, October 26, 2001 7:30 AM
To: [log in to unmask]
Subject: [TN] Cleaning paste when mis-aligned.
Importance: High
Hello All & the mountain dew man.
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
particles?
Is there any danger of damaging innerlayers of PCB?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended
only
for the stated addressee(s) and access to it by any other person is
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The views expressed in this E-mail are those of the author, and do not
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unless
otherwise expressly indicated.
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<HTML><HEAD>
<META content=3D"text/html; charset=3Dwindows-1252" =
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<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D446215617-26102001>I=20
don't mean to cause any undue concern. The issue is fairly simple . . . =
You can=20
break glass and ceramic with sound but it is not likely if you are =
careful. But=20
ultrasonic cleaning can break wire bonds, and wires, this is especially =
true in=20
controls, ceramic ICs and the like were the wires are not encapsulated =
and=20
subject to vibration. There are technologies that are effective in =
reducing this=20
type of damage. Hope this relieves your fear. If you are still concerned =
then=20
you have some homework to do. What frequency and power does you cleaner =
work at.=20
What is a construction of the packages in question . . . stuff like=20
that.</SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Howard =
Watson<BR><B>Sent:</B>=20
Friday, October 26, 2001 11:46 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Cleaning paste when=20
misaligned.<BR><BR></DIV></FONT><BR><FONT face=3Dsans-serif =
size=3D2>Mike and=20
Guy,</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>We routinely =
clean the second=20
side of misprint solder paste, but from what you are saying perhaps =
there=20
could be a problem with damaging some components. The components =
that we=20
clean in the ultrasonic cleaner are mostly flat chip package, C lead =
diodes,=20
and some SOT-23 and SOIC. How do I verify which components can =
or cannot=20
go in the cleaner? Is there any test data out there to support =
this=20
issue? Though we clean very few misprints, I am a little =
concerned.=20
Thanks for your help!</FONT> <BR><BR><FONT face=3Dsans-serif =
size=3D2>Howard=20
Watson<BR>Manufacturing Engineer<BR>AMETEK/Dixson</FONT> <BR><BR><BR>
<TABLE width=3D"100%">
<TBODY>
<TR vAlign=3Dtop>
<TD>
<TD><FONT face=3Dsans-serif size=3D1><B>"Barmuta, Mike"=20
<[log in to unmask]></B></FONT> <BR><FONT =
face=3Dsans-serif=20
size=3D1>Sent by: TechNet <[log in to unmask]></FONT>=20
<P><FONT face=3Dsans-serif size=3D1>10/26/01 09:02 AM</FONT> =
<BR><FONT=20
face=3Dsans-serif size=3D1>Please respond to "TechNet E-Mail =
Forum."</FONT>=20
<BR></P>
<TD><FONT face=3DArial size=3D1> =
</FONT><BR><FONT=20
face=3Dsans-serif size=3D1> To: =
=20
[log in to unmask]</FONT> <BR><FONT face=3Dsans-serif=20
size=3D1> cc: =20
</FONT> <BR><FONT face=3Dsans-serif size=3D1> =
=20
Subject: Re: [TN] Cleaning =
paste when=20
mis-aligned.</FONT></TR></TBODY></TABLE><BR><BR><BR><FONT =
face=3D"Courier New"=20
size=3D2>Cathy: This should not be a problem for the bare (unloaded) =
PCB.=20
However if<BR>you are doing a double sided reflow and misprint =
the=20
second side you need<BR>to verify that the first side components are=20
compatible with the ultrasonics<BR>you are=20
using.<BR><BR><BR>Regards<BR><BR>Michael Barmuta<BR><BR>Staff=20
Engineer<BR><BR>Fluke Corp.<BR><BR>Everett=20
WA<BR><BR>425-446-6076<BR><BR>-----Original Message-----<BR>From: =
Cathy Killen=20
[mailto:[log in to unmask]]<BR>Sent: Friday, October 26, 2001 7:30 =
AM<BR>To:=20
[log in to unmask]<BR>Subject: [TN] Cleaning paste when=20
mis-aligned.<BR>Importance: High<BR><BR><BR>Hello All & the =
mountain dew=20
man.<BR>Can a mis-printed PCB be washed in a ultrasonic bath to remove =
all=20
paste<BR>particles?<BR>Is there any danger of damaging innerlayers of=20
PCB?<BR><BR>Thanks in advance.<BR><BR>Cathy Killen<BR>Training=20
Instructor<BR>Smtek Europe Ltd.<BR>The information contained in the =
E-mail is=20
confidential. It is intended only<BR>for the stated addressee(s) and =
access to=20
it by any other person is<BR>unauthorised.<BR>The views expressed in =
this=20
E-mail are those of the author, and do not<BR>represent the views of =
Smtek=20
Europe, its associates or subsidiaries, unless<BR>otherwise expressly=20
indicated.<BR>Please note: It is your responsibility to scan this =
E-mail for=20
=
viruses.<BR><BR>---------------------------------------------------------=
-------------------<BR>-----<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to [log in to unmask] with following text =
in<BR>the=20
BODY (NOT the subject field): SIGNOFF Technet<BR>To temporarily halt =
delivery=20
of Technet send the following message: SET<BR>Technet NOMAIL<BR>Search =
previous postings at: www.ipc.org > On-Line Resources & =
Databases=20
><BR>E-mail Archives<BR>Please visit IPC web site=20
(http://www.ipc.org/html/forum.htm) for additional<BR>information, or =
contact=20
Keach Sasamori at [log in to unmask] or=20
=
847-509-9700<BR>ext.5315<BR>---------------------------------------------=
-------------------------------<BR>-----<BR><BR>-------------------------=
--------------------------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to [log in to unmask] with following text =
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of Technet send the following message: SET Technet NOMAIL<BR>Search =
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postings at: www.ipc.org > On-Line Resources & Databases > =
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Date: Fri, 26 Oct 2001 14:36:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: Looking for Joseph Fjelstad
MIME-Version: 1.0
Content-Type: text/plain
Hi Jana,
according to his book on flex, his coordinates were in 1998 as follows
1030 East El Camino Real #262
Sunnyvale, CA, 94087
(408) 383-3611
(650) 691-6780 x 41
Ioan
> -----Original Message-----
> From: Jana L. Carraway [SMTP:[log in to unmask]]
> Sent: Friday, October 26, 2001 2:09 PM
> To: [log in to unmask]
> Subject: [TN] Looking for Joseph Fjelstad
>
> Would anyone have an email address or phone number for Joe Fjelstad?
> Thank you,
> Jana Carraway
>
> --------------------------------------------------------------------------
> -------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
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> --------------------------------------------------------------------------
> -------
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Date: Fri, 26 Oct 2001 14:46:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: William Brown <[log in to unmask]>
Subject: Re: Laser trimming of resistors
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> =20
Just so you know, ISHM is now IMAPS (International
Microelectronics and Packaging Society). Their website is
http://www.imaps.org/ and there is a link for their publications.
Bill
There are some books on thick film manufacturing, but I don't
have the
titles available any more. You might try contacting ISHM
(International
Society for Hybrid Manufacturing?) for more information. This
got a little
long........hope it was helpful.
William G. Brown - Senior Electrical Engineer
TeraConnect, Inc. (http://www.teraconnect.com)
(P) 603-888-0288 x127 (F) 603-888-6564
98 Spit Brook Road, Nashua, NH 03062
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Date: Fri, 26 Oct 2001 13:47:56 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Long, Thomas" <[log in to unmask]>
Subject: Aqueous Heater Update
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
As a follow up to an earlier e-mail regarding a corrosion issue on
two Aqueous Technologies DI cleaners, it appears it was an isolated vendor
issue supplying the heaters. Most likely the heater fins were not cleaned
prior to coating application. Aqueous has taken steps to ensure proper
coating adhesion in the future, and has promised to replace anyone's heater
coils that is experiencing heater coil issues with the new improved
product. I am glad this was brought to closure quickly as the machines have
performed well for us in general.
Tom Long
************************************
If this email is not intended for you, or you are not responsible for the
delivery of this message to the addressee, please note that this message may
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************************************
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Date: Fri, 26 Oct 2001 16:15:53 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Abrahamson <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
Gents,
If you are using a SmartSonic Ultrasonic cleaner, their technical people say
that because they alternate their ultrasonic frequency, damage to die bonds
should not occur.
You might want to give your Ultrasonic cleaner representitive a call to find
out more specifics.
Steve A
> -----Original Message-----
> From: Guy Ramsey [SMTP:[log in to unmask]]
> Sent: Friday,October 26,2001 12:15 PM
> To: [log in to unmask]
> Subject: Re: [TN] Cleaning paste when misaligned.
>
> I don't mean to cause any undue concern. The issue is fairly simple . . .
> You can break glass and ceramic with sound but it is not likely if you are
> careful. But ultrasonic cleaning can break wire bonds, and wires, this is
> especially true in controls, ceramic ICs and the like were the wires are
> not encapsulated and subject to vibration. There are technologies that are
> effective in reducing this type of damage. Hope this relieves your fear.
> If you are still concerned then you have some homework to do. What
> frequency and power does you cleaner work at. What is a construction of
> the packages in question . . . stuff like that.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
> Sent: Friday, October 26, 2001 11:46 AM
> To: [log in to unmask]
> Subject: Re: [TN] Cleaning paste when misaligned.
>
>
>
> Mike and Guy,
>
> We routinely clean the second side of misprint solder paste, but
> from what you are saying perhaps there could be a problem with damaging
> some components. The components that we clean in the ultrasonic cleaner
> are mostly flat chip package, C lead diodes, and some SOT-23 and SOIC.
> How do I verify which components can or cannot go in the cleaner? Is
> there any test data out there to support this issue? Though we clean very
> few misprints, I am a little concerned. Thanks for your help!
>
> Howard Watson
> Manufacturing Engineer
> AMETEK/Dixson
>
>
>
> "Barmuta, Mike" <[log in to unmask]>
> Sent by: TechNet <[log in to unmask]>
>
> 10/26/01 09:02 AM
> Please respond to "TechNet E-Mail Forum."
>
>
>
> To: [log in to unmask]
> cc:
> Subject: Re: [TN] Cleaning paste when mis-aligned.
>
>
>
> Cathy: This should not be a problem for the bare (unloaded) PCB.
> However if
> you are doing a double sided reflow and misprint the second side
> you need
> to verify that the first side components are compatible with the
> ultrasonics
> you are using.
>
>
> Regards
>
> Michael Barmuta
>
> Staff Engineer
>
> Fluke Corp.
>
> Everett WA
>
> 425-446-6076
>
> -----Original Message-----
> From: Cathy Killen [mailto:[log in to unmask]]
> Sent: Friday, October 26, 2001 7:30 AM
> To: [log in to unmask]
> Subject: [TN] Cleaning paste when mis-aligned.
> Importance: High
>
>
> Hello All & the mountain dew man.
> Can a mis-printed PCB be washed in a ultrasonic bath to remove all
> paste
> particles?
> Is there any danger of damaging innerlayers of PCB?
>
> Thanks in advance.
>
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
> The information contained in the E-mail is confidential. It is
> intended only
> for the stated addressee(s) and access to it by any other person is
> unauthorised.
> The views expressed in this E-mail are those of the author, and do
> not
> represent the views of Smtek Europe, its associates or subsidiaries,
> unless
> otherwise expressly indicated.
> Please note: It is your responsibility to scan this E-mail for
> viruses.
>
>
> --------------------------------------------------------------------------
> --
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV
> 1.8d
> To unsubscribe, send a message to [log in to unmask] with following
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> SET
> Technet NOMAIL
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> Databases >
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> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700
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Date: Fri, 26 Oct 2001 15:31:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jana L. Carraway" <[log in to unmask]>
Subject: Re: Looking for Joseph Fjelstad
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Thank you to all who responded. He contacted me.
Thanks for taking the time to help,
Jana Carraway
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Tempea, Ioan
Sent: Friday, October 26, 2001 11:37 AM
To: [log in to unmask]
Subject: Re: [TN] Looking for Joseph Fjelstad
Hi Jana,
according to his book on flex, his coordinates were in 1998 as follows
1030 East El Camino Real #262
Sunnyvale, CA, 94087
(408) 383-3611
(650) 691-6780 x 41
Ioan
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Date: Fri, 26 Oct 2001 17:30:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mike Manwell <[log in to unmask]>
Subject: Masking For Conformal Coating
Hello,
Im just getting into coating a UV curable material and was wondering what
others use to mask parts that you dont want coating on, such as LED's and
odd shaped connectors.
Any suggestions would be appriciated.
Mike Manwell
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Date: Fri, 26 Oct 2001 16:12:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Innerlayer shorts - predictions vs. reality
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I've approached this problem in the past by looking at a yield per layer.
Obviously a lot of assumptions have to be made in terms of density of
layers, complexity of circuits, size of board, number of holes, which layers
to include, etc. But if you're trying to get an idea of what role the
number of layers plays on yields, I still think it's effective.
I usually make a little spreadsheet that keeps raising the yield per layer
to the appropriate power. For instance if you're yield per layer is 99%,
the yield for 2 layers is 98%, for 3 it is 97%. The equation looks linear
here but that's just because 0.99 is so close to 1 and you're looking at
only a few layers. If you increase the number of layers and drop the yield,
you'll see the curve is actually asymptotic.
So let's look at your scenario. For a 12-layer board, let's assume 6 signal
layers with a 93% yield. Working backwards, I get a yield of 98.8% per
layer. Applying this to a 24 layer board with 12 signal layers, the yield
should be 86.5% versus the 82% you are reporting. Looks to me like you are
sandbagging it on the 24-layer board! ;-)
Just kidding of course. As I said the assumptions are critical, but I still
think this is a good way to show how the number of layers impacts yields.
> ----------
> From: Hinners Hans M Civ
> WRALC/LUGE[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Thursday, October 25, 2001 8:44 AM
> To: [log in to unmask]
> Subject: [TN] Innerlayer shorts - predictions vs. reality
>
> Good Morning All!
>
> I think I've got a case of folks comparing apples to bananas.
>
> I'm trying to predict % defects due to inner layer shorts and compare
> across
> part numbers. Folks are looking at one part number and saying, "12 layer
> board with 7% inner layer shorts (of the ones tested) and looking at
> another
> part number - 24 layer board has 18% inner layer shorts. You are screwing
> up more on the big $$$ board - fix it!" Shouldn't inner layer shorts be a
> linear or geometric relationship?
>
> For example, take a 10 layer board, it has 5 signal layers (50-50 signal &
> plane). Each signal layer will have a certain surface area where traces
> are
> packed close enough together that a sliver of metal could cause a short.
> At
> electrical test I fail a certain percentage of boards due to shorts - say
> 10%. Now take a 20 layer board and say it doubles the surface area that
> could have a short. The failures due to inner layer shorts should be
> double
> the 10 layer board or 20%. If the boards were manufactured at the same
> time
> the process should, on average, contribute the same number of shorts/area
> to
> each.
>
> Inner layer short defects come from multiple sources that produces a
> finely
> boned fish - metallic contamination, poor IL etching, poor IL
> imaging/development, missed in IL AOI, equipment, material, method, people
> -
> ad nausem. . . And for now I'm ignoring test escapes. The inner layer
> short
> generation fluctuates over time but has some average value per area. So I
> propose a simple equation:
>
> Inner Layer Defects = (average # inner layer shorts/surface area) (total
> critical surface area)
>
> Looking at the artwork should get me the critical surface area, the inner
> layer defects we know from Electrical Test so a graph of defects vs.
> surface
> area should get me the shorts/area for the total process, no? Then I can
> say when the process has changed versus merely a higher tech board being
> processed.
>
> Anybody hit this wall before? Is there a flaw in my logic?
>
> Hans
>
> PS. If memory serves, I remember Bev mentioning Technetters' lack of
> gender
> identification skills at that "Stump the Chumps" session we had a few
> years
> ago. And I can relate - every once in a while people see the middle name
> (Michel) and think "must be a groovy chick".
>
> Integrity First - Service Before Self - Excellence in All We Do
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> Special Operations Forces System Program Office (SOF - SPO)
> Gunship Team
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax: (478) 926 - 4911
> DSN Prefix: 468
>
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Date: Fri, 26 Oct 2001 16:15:26 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Miller <[log in to unmask]>
Subject: Re: Masking For Conformal Coating
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Hi Mike,
Try Kinnarney Rubber Co. Ph: 609-464-1320. There out of New Jersey.
Eric Miller
Sales Manager
Ascentec Engineering
13565 SW. Tualatin-Sherwood Rd.
Suite 400
Sherwood, Oregon. 97140
PHONE: 503-925-1942
Fax: 503-925-1191
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Mike Manwell
Sent: Friday, October 26, 2001 3:30 PM
To: [log in to unmask]
Subject: [TN] Masking For Conformal Coating
Hello,
Im just getting into coating a UV curable material and was wondering
what
others use to mask parts that you dont want coating on, such as LED's
and
odd shaped connectors.
Any suggestions would be appriciated.
Mike Manwell
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Date: Sun, 28 Oct 2001 10:40:19 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
To Everyone,
As I get more involved with high density, Rf products and as the worldwide
directive ahs us leaning more to lead-free processes is bearing down on us
all we will be experiencing the need/joy/requirement to be profiling more
often. This is because there are key components being made and designed into
circuits that will require extraordinary temperature control. For example
some are saying that the top of the part must be within 10 degrees celsius
of the bottom (the plane that meets the PCB) of the component AND the reflow
temperature is for high temperature solder irrespective of the fact there
are (many) other components on the assembly that are at the very least
"sensitive" to high temperature solder.
Earl I too feel that most assemblies can be accomodated by a few profiles
but we really can't say what is going on at specific locations and that is
what we will be needing to do to accomodate one "special" part. I need
profiling but I hate it because the equipment cannot do what I need with the
accuracy, dependability and flexability the new design/assemblies require.
Regards,
Dorothy Lush
> ----------
> From: Earl Moon[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Thursday, October 25, 2001 8:20 AM
> To: [log in to unmask]
> Subject: Re: Reflow profiling
>
> I don't get all your doing or, for that matter, all anyone else is doing.
> At
> HP, a few years ago, we averaged 15 change overs a day on 10 lines with
> seldom more than 50 assemblies each lot/run. To put this in perspective,
> we
> had 1,500 active part numbers going through the shop with requirements for
> nearly 20 million placements/month with every type component imaginable at
> the time. We had only three reflow profiles, with two pastes, and they did
> the job but for exceptions as experiments.
>
> Doubt this answers your question but it is a trip down memory lane for me.
> Sure enjoyed the experience and the trip.
>
> Enjoy,
>
> MoonMan
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
> -------
> Hello All,
>
> I am with a low volume, frequent changeover contract manufacturer. We are
> trying to implement a system where we profile the first assembly of every
> new run through our reflow oven. We are currently using high temperature
> solder for profiling. If we start to use the high temp solder for this, we
> will have to scrap the assemblies. Does anyone have any suggestions for
> alternatives to high temp solder? Any suggestions would be greatly
> appreciated.
>
> Thank you,
> Brad Smith
> Process Technician
> Badger Electronics Co., Inc.
> (262)886-8800
> [log in to unmask]
>
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>
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Date: Sun, 28 Oct 2001 10:41:49 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: REPOST: Through Hole Oscillator Removal
MIME-Version: 1.0
Content-Type: text/plain
Take the capacitors off, do your thing, then put them back.
Dorothy Lush
> ----------
> From: John Fahey[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Tuesday, October 23, 2001 9:04 AM
> To: [log in to unmask]
> Subject: REPOST: Through Hole Oscillator Removal
>
> Good Morning.
>
> I have a PCB assembly where I need to remove a 4 pin through hole
> oscillator and replace it with a different date code. (@5K units)
>
> AirVac recommends that this removal be done by heating the bottom side via
> a solder pot system to reflow the solder, remove the component, and
> replace
> it with a new one.. Unfortunately, there are 3 capacitors on the bottom
> side which lie in the vicinity of the through hole leads which would
> necessitate a specially designed Nozzle.
>
> Does anyone have ANY other advice/recommendations for a system to
> remove/replace through hole components from a PCBA. I am particularly
> interested ina ny systems that can be leased as this is a one time usage
> requirement.
>
> As always, I appreciate your excellent advice.
>
> Rgds, John
>
> --------------------------------------------------------------------------
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Date: Mon, 29 Oct 2001 08:11:38 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Land Patterns
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I just went through the same pain, adn the answer for now is that you have
to use either the 3 formulae in SM-782 or IPC's on-line calculator for
packages with no defined land pattern. The trouble is that where you can
correlate results, SM-782 and the calculator usually give different
results, so which one is right. Also, if you use any other soldering method
than convection reflow, there is even less certain guidance.
Jack Crawford has stated that IPC "were working on these issues" (how's it
coming along, Jack?), but it's a Pandora's box. There area so many
variables like substrate material, component package varieties (even within
the same species - every manufacturer has its own version of the "standard"
package), assembly process, etc., that it will be quite difficult to turn
this trial and error art into a science. Sorry not to be more encouraging.
I determined the following heirarchy of rules for our guys:
1. If you have a land pattern in a data sheet, use it.
2. If the dtata sheet doesn't have a land pattern, but does have an RPL
(registered land pattern) number or JEDEC number, try SM-782 and use the
land pattern there, if there is one.
3. If 1 and 2 fail, use the IPC calculator and take the heel and toe solder
joint figures required from table 3.4 in SM-782. If in practice later, the
resultant pattern doesn't work, well, you're largely on your own to sort
out a better solution.
There's a chance here for someone to make a name for themselves here by
determining a reliable formula and save everyone re-inventing the wheel .
Maybe Daan can start a database on his site for successful land patterns
people have worked out for particular substrate materials/OEM component
packages/soldering process/operating conditions/.../... that other mortals
could use as a library. What d'ya reckon, Daan? People can add to it
themselves if the want to share their findings.
Peter Duncan
"Reid, Lorraine"
<Lorraine.Reid@TRI To: [log in to unmask]
VIRIX.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] Land Patterns
10/26/01 06:21 PM
Please respond to
"TechNet E-Mail
Forum."
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Mon, 29 Oct 2001 08:19:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Reflow profiling
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Good point, Guy, and these heat sinking components often are not available
as dummy parts, so one is them faced with using a genuine part if it's felt
to be critical in terms of thermal mass on the board. There may well be a
case of dwell time being insufficient or inadequate peak temp spike.
Peter Duncan
Guy Ramsey
<gramsey@ACIU To: [log in to unmask]
SA.ORG> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Reflow profiling
<[log in to unmask]
ORG>
10/26/01
08:33 PM
Please
respond to
"TechNet
E-Mail
Forum."
Good plan. I would add a reminder. Some packages have internal structures
to
conduct heat away from active device(s) in the package. These may not be
represented in the dummy component, and can result in an oven profile that
is too cool.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
> Sent: Thursday, October 25, 2001 10:00 PM
> To: [log in to unmask]
> Subject: Re: [TN] Reflow profiling
>
>
>
> I also am involved with high mix, low volume builds, and I try to get one
> board of each type from the fab house that has failed electrical with
> internal shorts or whatever (cheaper than sacrificing a good
> board). I then
> buy in a stack of dummy components from Practical Components or
> Topline and
> populate the profile board with those. I don't bother with discrete
> passives, as they contribute precious little to the thermal mass. The
> thermal profile board is them reflowed using the standard profile
supplied
> by the solder manufacturer.
>
> For BGA's and so forth, I then drill a hole up through the board into one
> of the central contacts to take a thermocouple wire, which is bonded in
> place, and add other thermocouples around the board. plug them all into
a
> high-temp data logger
>
>
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=========================================================================
Date: Mon, 29 Oct 2001 08:26:45 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Land Patterns
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
If this information is so readily available, why don't manufacturers just
quote land patterns in their data sheets as a standard part of the format?
Very few do, and it's a real pain to ring up every one of them every time
to get this information. Yet everyone seems to accept this as the way it
is!
Can't IPC bring any pressure to bear on manufacturers to provide this
information as standard? Jack?
Peter Duncan
Dean
Lillibridge To: [log in to unmask]
<lillibrd@NTC cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
1.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] Land Patterns
TechNet
<[log in to unmask]
ORG>
10/26/01
09:02 PM
Please
respond to
"TechNet
E-Mail
Forum."
Not finding the patterns in IPC, I would consult the "suggested land
patterns" of the manufacturer's of those devices. Technical support, or
engineering support of the companies that manufacture the component spec'd
in should be able to provide you with suggested land patterns and
recommended soldering profiles.
--Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Reid, Lorraine
Sent: Friday, October 26, 2001 6:21 AM
To: [log in to unmask]
Subject: [TN] Land Patterns
Can anyone point me to a good reliable resource for land patterns for
devices which are not in IPC-SM-762?
I need to verify patterns for devices such as TSSOPs, QSOPs, and SSOPs,
none of which seem to be covered in the standards!
thanks in advance,
Lorraine Reid
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Date: Sun, 28 Oct 2001 20:34:35 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Fjelstad <[log in to unmask]>
Subject: Solving the 0.25% problem
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_3a.1cd86ae9.290e0c2b_boundary"
--part1_3a.1cd86ae9.290e0c2b_boundary
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
Hello friends,=20
I continue to be amazed at how much energy is being leveled at the lead-free=
=20
issue. Which is a shame because there are so many truly important issues tha=
t=20
are not being looked into. Especially given that lead in electronics has=20
never been shown to be a hazard or a problem to humans. (Lead in human blood=
=20
plasma has actually gone down significantly in the past 20 years) CRTs are a=
=20
possible exception as the leaded glass to stop x-rays may be an issue but=20
that lead is at least bound in glass. (Alas, such the power of fear based=20
marketing)=20
In my limited research, lead in electronics appears to account for less than=
=20
0.5% of all lead used globally on an annual basis. It may be less than 0.25%=
=20
as one soon to be released research report I just read has the number at 0.2=
%=20
or a factor of 10 times less.
(I know the IPC web site says less than 2% and it is true but not accurate=20
because 0.5% is in fact less than 2%. It appears to have come from a US EPA=20
study that was done in the 1980s and relates primarily to the US. I think=20
they will get around to changing it someday when they have the time. I=20
mentioned this to David some time back and he was going to have Chris look=20
into it but Chris moved on before that happened, I am guessing)=20
Remember that different profiles will be required for all of the different=20
solders you use as military, medical, automotive and high reliability=20
electronics are exempted you will likely have two or more solder lines=20
running several different profiles. Also be reminded that the lines will=20
likely have to be slowed down to get good wetting in reflow soldering and=20
NEMI is recommending a wave soldering temperature of 275=BAC. You may wish t=
o=20
read the NCMS and NEMI reports.=20
Remember also that there is no "world wide" directive yet. The US is,=20
however, going to be taking a science based look at the issue. The IPC, EIA=20
and EPA are going to do a co-sponsored risk analysis of lead-free. If a smal=
l=20
part of what I have read and learned is true lead-free is going not going to=
=20
get any green stickers due to the excessive energy requirements for prebakes=
=20
and long assembly cycles.=20
I have nothing to sell or gain from all of this, no matter what happens over=
=20
the long haul I do, however, have a strong interest in truth. ( For the=20
record, I also favored lead-free on principle when it first came about, but=20
my deeper look into the matter has caused me to question the intelligence an=
d=20
rational of the movement)=20
Best wishes and kind regard to all,=20
Joe=20
=20
--part1_3a.1cd86ae9.290e0c2b_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2>Hello friends,=20
<BR>
<BR>I continue to be amazed at how much energy is being leveled at the lead-=
free issue. Which is a shame because there are so many truly important issue=
s that are not being looked into. Especially given that lead in electronics=20=
has never been shown to be a hazard or a problem to humans. (Lead in human b=
lood plasma has actually gone down significantly in the past 20 years) CRTs=20=
are a possible exception as the leaded glass to stop x-rays may be an issue=20=
but that lead is at least bound in glass. (Alas, such the power of fea=
r based marketing)=20
<BR>
<BR>In my limited research, lead in electronics appears to account for less=20=
than 0.5% of all lead used globally on an annual basis. It may be less than=20=
0.25% as one soon to be released research report I just read has the number=20=
at 0.2% or a factor of 10 times less.
<BR>
<BR>(I know the IPC web site says less than 2% and it is true but not accura=
te because 0.5% is in fact less than 2%. It appears to have come from a US E=
PA study that was done in the 1980s and relates primarily to the US. I think=
they will get around to changing it someday when they have the time. I ment=
ioned this to David some time back and he was going to have Chris look into=20=
it but Chris moved on before that happened, I am guessing)=20
<BR>
<BR>Remember that different profiles will be required for all of the differe=
nt solders you use as military, medical, automotive and high reliability ele=
ctronics are exempted you will likely have two or more solder lines running=20=
several different profiles. Also be reminded that the lines will likely have=
to be slowed down to get good wetting in reflow soldering and NEMI is recom=
mending a wave soldering temperature of 275=BAC. You may wish to read the NC=
MS and NEMI reports.=20
<BR>
<BR>Remember also that there is no "world wide" directive yet. The US is, ho=
wever, going to be taking a science based look at the issue. The IPC, EIA an=
d EPA are going to do a co-sponsored risk analysis of lead-free. If a small=20=
part of what I have read and learned is true lead-free is going not going to=
get any green stickers due to the excessive energy requirements for prebake=
s and long assembly cycles.=20
<BR>
<BR>I have nothing to sell or gain from all of this, no matter what happens=20=
over the long haul I do, however, have a strong interest in truth. ( For the=
record, I also favored lead-free on principle when it first came about, but=
my deeper look into the matter has caused me to question the intelligence a=
nd rational of the movement)=20
<BR>
<BR>Best wishes and kind regard to all,=20
<BR>Joe=20
<BR>
<BR> </FONT></HTML>
--part1_3a.1cd86ae9.290e0c2b_boundary--
---------------------------------------------------------------------------------
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=========================================================================
Date: Sun, 28 Oct 2001 20:55:35 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Solving the 0.25% problem
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_8d.e8520dd.290e1117_boundary"
--part1_8d.e8520dd.290e1117_boundary
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
Hello Joe...
Speaking for myself, you are singing to the choir (so to speak), I agree wit=
h=20
you 100%!!!
What's even more irritating is this new TRI reporting legislation. By what=20
has been detailed out, some of my hunting buddies could be legally bound to=20
submit because they use more than 100-lbs. of lead shot when reloading. The=20
same thing could apply to commercial fishermen who make their own sinkers...
It's a bunch of bull@$%t!!!
-Steve Gregory-
> Hello friends,=20
>=20
> I continue to be amazed at how much energy is being leveled at the=20
> lead-free issue. Which is a shame because there are so many truly importan=
t=20
> issues that are not being looked into. Especially given that lead in=20
> electronics has never been shown to be a hazard or a problem to humans.=20
> (Lead in human blood plasma has actually gone down significantly in the=20
> past 20 years) CRTs are a possible exception as the leaded glass to stop=20
> x-rays may be an issue but that lead is at least bound in glass. (Alas,=20
> such the power of fear based marketing)=20
>=20
> In my limited research, lead in electronics appears to account for less=20
> than 0.5% of all lead used globally on an annual basis. It may be less tha=
n=20
> 0.25% as one soon to be released research report I just read has the numbe=
r=20
> at 0.2% or a factor of 10 times less.=20
>=20
> (I know the IPC web site says less than 2% and it is true but not accurate=
=20
> because 0.5% is in fact less than 2%. It appears to have come from a US EP=
A=20
> study that was done in the 1980s and relates primarily to the US. I think=20
> they will get around to changing it someday when they have the time. I=20
> mentioned this to David some time back and he was going to have Chris look=
=20
> into it but Chris moved on before that happened, I am guessing)=20
>=20
> Remember that different profiles will be required for all of the different=
=20
> solders you use as military, medical, automotive and high reliability=20
> electronics are exempted you will likely have two or more solder lines=20
> running several different profiles. Also be reminded that the lines will=20
> likely have to be slowed down to get good wetting in reflow soldering and=20
> NEMI is recommending a wave soldering temperature of 275=BAC. You may wish=
to=20
> read the NCMS and NEMI reports.=20
>=20
> Remember also that there is no "world wide" directive yet. The US is,=20
> however, going to be taking a science based look at the issue. The IPC, EI=
A=20
> and EPA are going to do a co-sponsored risk analysis of lead-free. If a=20
> small part of what I have read and learned is true lead-free is going not=20
> going to get any green stickers due to the excessive energy requirements=20
> for prebakes and long assembly cycles.=20
>=20
> I have nothing to sell or gain from all of this, no matter what happens=20
> over the long haul I do, however, have a strong interest in truth. ( For=20
> the record, I also favored lead-free on principle when it first came about=
,=20
> but my deeper look into the matter has caused me to question the=20
> intelligence and rational of the movement)=20
>=20
> Best wishes and kind regard to all,=20
> Joe=20
>=20
--part1_8d.e8520dd.290e1117_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
<FONT SIZE=3D2>Hello Joe...<BR>
<BR>
Speaking for myself, you are singing to the choir (so to speak), I agree wit=
h you 100%!!!<BR>
<BR>
What's even more irritating is this new TRI reporting legislation. By what h=
as been detailed out, some of my hunting buddies could be legally bound to s=
ubmit because they use more than 100-lbs. of lead shot when reloading. The s=
ame thing could apply to commercial fishermen who make their own sinkers...<=
BR>
<BR>
It's a bunch of bull@$%t!!!<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT=
: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello friends, <BR>
<BR>
I continue to be amazed at how much energy is being leveled at the lead-free=
issue. Which is a shame because there are so many truly important issues th=
at are not being looked into. Especially given that lead in electronics has=20=
never been shown to be a hazard or a problem to humans. (Lead in human blood=
plasma has actually gone down significantly in the past 20 years) CRTs are=20=
a possible exception as the leaded glass to stop x-rays may be an issue but=20=
that lead is at least bound in glass. (Alas, such the power of fear ba=
sed marketing) <BR>
<BR>
In my limited research, lead in electronics appears to account for less than=
0.5% of all lead used globally on an annual basis. It may be less than 0.25=
% as one soon to be released research report I just read has the number at 0=
.2% or a factor of 10 times less. <BR>
<BR>
(I know the IPC web site says less than 2% and it is true but not accurate b=
ecause 0.5% is in fact less than 2%. It appears to have come from a US EPA s=
tudy that was done in the 1980s and relates primarily to the US. I think the=
y will get around to changing it someday when they have the time. I mentione=
d this to David some time back and he was going to have Chris look into it b=
ut Chris moved on before that happened, I am guessing) <BR>
<BR>
Remember that different profiles will be required for all of the different s=
olders you use as military, medical, automotive and high reliability electro=
nics are exempted you will likely have two or more solder lines running seve=
ral different profiles. Also be reminded that the lines will likely have to=20=
be slowed down to get good wetting in reflow soldering and NEMI is recommend=
ing a wave soldering temperature of 275=BAC. You may wish to read the NCMS a=
nd NEMI reports. <BR>
<BR>
Remember also that there is no "world wide" directive yet. The US is, howeve=
r, going to be taking a science based look at the issue. The IPC, EIA and EP=
A are going to do a co-sponsored risk analysis of lead-free. If a small part=
of what I have read and learned is true lead-free is going not going to get=
any green stickers due to the excessive energy requirements for prebakes an=
d long assembly cycles. <BR>
<BR>
I have nothing to sell or gain from all of this, no matter what happens over=
the long haul I do, however, have a strong interest in truth. ( For the rec=
ord, I also favored lead-free on principle when it first came about, but my=20=
deeper look into the matter has caused me to question the intelligence and r=
ational of the movement) <BR>
<BR>
Best wishes and kind regard to all, <BR>
Joe <BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_8d.e8520dd.290e1117_boundary--
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Sun, 28 Oct 2001 21:47:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solving the 0.25% problem
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 8bit
Your sentiments have been expressed many times over on the LeadFree forum as
well. And your point is well taken. Remember, there are two forces working
here, the forces of Law and the forces of the Marketplace.
With respect to the law, put your thoughts on paper and send them to
legislators.
With respect to the marketplace, I am at a loss. I hope that the green
consumers will listen, learn and choose wisely.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Joseph Fjelstad
Sent: Sunday, October 28, 2001 8:35 PM
To: [log in to unmask]
Subject: [TN] Solving the 0.25% problem
Hello friends,
I continue to be amazed at how much energy is being leveled at the
lead-free issue. Which is a shame because there are so many truly important
issues that are not being looked into. Especially given that lead in
electronics has never been shown to be a hazard or a problem to humans.
(Lead in human blood plasma has actually gone down significantly in the past
20 years) CRTs are a possible exception as the leaded glass to stop x-rays
may be an issue but that lead is at least bound in glass. (Alas, such the
power of fear based marketing)
In my limited research, lead in electronics appears to account for less
than 0.5% of all lead used globally on an annual basis. It may be less than
0.25% as one soon to be released research report I just read has the number
at 0.2% or a factor of 10 times less.
(I know the IPC web site says less than 2% and it is true but not accurate
because 0.5% is in fact less than 2%. It appears to have come from a US EPA
study that was done in the 1980s and relates primarily to the US. I think
they will get around to changing it someday when they have the time. I
mentioned this to David some time back and he was going to have Chris look
into it but Chris moved on before that happened, I am guessing)
Remember that different profiles will be required for all of the different
solders you use as military, medical, automotive and high reliability
electronics are exempted you will likely have two or more solder lines
running several different profiles. Also be reminded that the lines will
likely have to be slowed down to get good wetting in reflow soldering and
NEMI is recommending a wave soldering temperature of 275ºC. You may wish to
read the NCMS and NEMI reports.
Remember also that there is no "world wide" directive yet. The US is,
however, going to be taking a science based look at the issue. The IPC, EIA
and EPA are going to do a co-sponsored risk analysis of lead-free. If a
small part of what I have read and learned is true lead-free is going not
going to get any green stickers due to the excessive energy requirements for
prebakes and long assembly cycles.
I have nothing to sell or gain from all of this, no matter what happens
over the long haul I do, however, have a strong interest in truth. ( For the
record, I also favored lead-free on principle when it first came about, but
my deeper look into the matter has caused me to question the intelligence
and rational of the movement)
Best wishes and kind regard to all,
Joe
------=_NextPart_000_000E_01C15FFA.13E87A30
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D36324202-29102001>Your=20
sentiments have been expressed many times over on the LeadFree forum as =
well.=20
And your point is well taken. Remember, there are two forces working =
here, the=20
forces of Law and the forces of the Marketplace.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D36324202-29102001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D36324202-29102001>With=20
respect to the law, put your thoughts on paper and send them to =
legislators.=20
</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D36324202-29102001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D36324202-29102001>With=20
respect to the marketplace, I am at a loss. I hope that the green =
consumers will=20
listen, learn and choose wisely. </SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Joseph =
Fjelstad<BR><B>Sent:</B>=20
Sunday, October 28, 2001 8:35 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Solving the 0.25%=20
problem<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>Hello=20
friends, <BR><BR>I continue to be amazed at how much energy is being =
leveled=20
at the lead-free issue. Which is a shame because there are so many =
truly=20
important issues that are not being looked into. Especially given that =
lead in=20
electronics has never been shown to be a hazard or a problem to =
humans. (Lead=20
in human blood plasma has actually gone down significantly in the past =
20=20
years) CRTs are a possible exception as the leaded glass to stop =
x-rays may be=20
an issue but that lead is at least bound in glass. (Alas, such =
the power=20
of fear based marketing) <BR><BR>In my limited research, lead in =
electronics=20
appears to account for less than 0.5% of all lead used globally on an =
annual=20
basis. It may be less than 0.25% as one soon to be released research =
report I=20
just read has the number at 0.2% or a factor of 10 times less.=20
<BR><BR>(I know the IPC web site says less than 2% and it is true but =
not=20
accurate because 0.5% is in fact less than 2%. It appears to have come =
from a=20
US EPA study that was done in the 1980s and relates primarily to the =
US. I=20
think they will get around to changing it someday when they have the =
time. I=20
mentioned this to David some time back and he was going to have Chris =
look=20
into it but Chris moved on before that happened, I am guessing)=20
<BR><BR>Remember that different profiles will be required for all of =
the=20
different solders you use as military, medical, automotive and high=20
reliability electronics are exempted you will likely have two or more =
solder=20
lines running several different profiles. Also be reminded that the =
lines will=20
likely have to be slowed down to get good wetting in reflow soldering =
and NEMI=20
is recommending a wave soldering temperature of 275=BAC. You may wish =
to read=20
the NCMS and NEMI reports. <BR><BR>Remember also that there is no =
"world wide"=20
directive yet. The US is, however, going to be taking a science based =
look at=20
the issue. The IPC, EIA and EPA are going to do a co-sponsored risk =
analysis=20
of lead-free. If a small part of what I have read and learned is true=20
lead-free is going not going to get any green stickers due to the =
excessive=20
energy requirements for prebakes and long assembly cycles. <BR><BR>I =
have=20
nothing to sell or gain from all of this, no matter what happens over =
the long=20
haul I do, however, have a strong interest in truth. ( For the record, =
I also=20
favored lead-free on principle when it first came about, but my deeper =
look=20
into the matter has caused me to question the intelligence and =
rational of the=20
movement) <BR><BR>Best wishes and kind regard to all, <BR>Joe=20
<BR><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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Date: Mon, 29 Oct 2001 08:30:02 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
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Earl
OK Earl, that's one of the answers I wanted to hear. Hehe. It's the first =
time someone tells me that I am much respected in my field. Kind of balm =
on my wounded soul.=20
I have no problem at all with a discussion on TechNet. Maybe I should try =
to refrain of teasing though . But on the other side science is no fun if =
you have to be serious all the time.
Have good Monday and a terrific week
Guenter
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Mon, 29 Oct 2001 08:48:25 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guenter Grossmann <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
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Bev
I couldn't give you a number. From the metallurgical side some nm are =
enough because then the solder and the substrate have alloyed. The problem =
is the maximum. From my feelings I would say that a thick IMC is not =
optimal for reliability. However, I have no facts and Werner pointed out =
that a thick IMC doesn't do any bad to reliability. On these inputs I =
would say that it is important to have an IMC because it is the indicator =
for a successful alloying of solder and substrate. The thickness seems to =
be not so important.
If I find some founds left over in LEADFREE by mid 2002 I will make some =
trials on that.
Best regards
Guenter
Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland
Phone: xx41 1 823 4279
Fax : xx41 1823 4054
mail: [log in to unmask]
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Date: Mon, 29 Oct 2001 10:26:06 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
In-Reply-To: <[log in to unmask]>
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Back in the days when F113 was the best thing since sliced bread there were
several studies on bond wire integrity in ultrasonic cleaning. In this
country by ICI (then supplying F113 cleaners under brand name Arklone,
equivalent to Dupont Freon) and Marconi Stanmore in UK. Possibly also the UK
National Physical Laboratory, although it might be that Marconi and NPL
collaborated.
Basically they concluded that there was possibly a problem with the then
frequency used [40kHz], but this would really only affect poor quality wire
bonds that would fail anyway. Modern units run at 70kHz and/or sweep the
frequencies so eliminating the problem. This was all ages ago and my memory
may be a little poor on the details, but the essentials are correct.
Are we now saying that component sizes are now so reduced that there is a
problem again?
Best regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: http://Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
Sent: Friday, October 26, 2001 7:15 PM
To: [log in to unmask]
Subject: Re: [TN] Cleaning paste when misaligned.
I don't mean to cause any undue concern. The issue is fairly simple . . .
You can break glass and ceramic with sound but it is not likely if you are
careful. But ultrasonic cleaning can break wire bonds, and wires, this is
especially true in controls, ceramic ICs and the like were the wires are not
encapsulated and subject to vibration. There are technologies that are
effective in reducing this type of damage. Hope this relieves your fear. If
you are still concerned then you have some homework to do. What frequency
and power does you cleaner work at. What is a construction of the packages
in question . . . stuff like that.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: Friday, October 26, 2001 11:46 AM
To: [log in to unmask]
Subject: Re: [TN] Cleaning paste when misaligned.
Mike and Guy,
We routinely clean the second side of misprint solder paste, but from
what you are saying perhaps there could be a problem with damaging some
components. The components that we clean in the ultrasonic cleaner are
mostly flat chip package, C lead diodes, and some SOT-23 and SOIC. How do I
verify which components can or cannot go in the cleaner? Is there any test
data out there to support this issue? Though we clean very few misprints, I
am a little concerned. Thanks for your help!
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
"Barmuta, Mike" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
10/26/01 09:02 AM
Please respond to "TechNet E-Mail Forum."
To: [log in to unmask]
cc:
Subject: Re: [TN] Cleaning paste when mis-aligned.
Cathy: This should not be a problem for the bare (unloaded) PCB. However
if
you are doing a double sided reflow and misprint the second side you
need
to verify that the first side components are compatible with the
ultrasonics
you are using.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Cathy Killen [mailto:[log in to unmask]]
Sent: Friday, October 26, 2001 7:30 AM
To: [log in to unmask]
Subject: [TN] Cleaning paste when mis-aligned.
Importance: High
Hello All & the mountain dew man.
Can a mis-printed PCB be washed in a ultrasonic bath to remove all paste
particles?
Is there any danger of damaging innerlayers of PCB?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended
only
for the stated addressee(s) and access to it by any other person is
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The views expressed in this E-mail are those of the author, and do not
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unless
otherwise expressly indicated.
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR></HEAD>
<BODY>
<DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN =
class=3D937500215-07062001><SPAN=20
class=3D984131810-29102001>Back in the days when F113 was the best thing =
since=20
sliced bread there</SPAN> <SPAN class=3D984131810-29102001> =
were</SPAN>=20
several studies on <SPAN class=3D984131810-29102001>bond=20
wire </SPAN><SPAN class=3D984131810-29102001>integrity in =
ultrasonic=20
cleaning.</SPAN> I<SPAN class=3D984131810-29102001>n this =
country </SPAN>by=20
ICI (then supplying F113 cleaners<SPAN class=3D984131810-29102001> =
under=20
brand name </SPAN>Arklone<SPAN class=3D984131810-29102001>, equivalent =
to Dupont=20
Freon</SPAN>) and Marconi Stanmore in UK. Possibly also <SPAN=20
class=3D984131810-29102001>the UK </SPAN> National Physical Laboratory, =
although=20
it might be that M<SPAN class=3D984131810-29102001>a</SPAN>rconi and NPL =
collaborated.</SPAN></FONT></FONT></DIV>
<DIV><SPAN class=3D937500215-07062001></SPAN><FONT color=3D#0000ff=20
face=3DArial> </FONT></DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN=20
class=3D937500215-07062001>Basically they concluded that there was =
possibly a=20
problem with the then frequency used [40kHz], but this would really only =
affect=20
poor quality wire bonds that would fail anyway. Modern units run at=20
70kHz <SPAN class=3D984131810-29102001>and/</SPAN>or sweep the =
frequencies so=20
eliminating the problem. <SPAN class=3D984131810-29102001>=20
</SPAN></SPAN><SPAN class=3D937500215-07062001>This was all ages ago and =
my memory=20
may be a little poor on the details, but the essentials are=20
correct.</SPAN></FONT></FONT><FONT color=3D#0000ff =
face=3DArial></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial><SPAN =
class=3D984131810-29102001>Are we now=20
saying that component sizes are now so reduced that there is a problem=20
again?</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial><SPAN=20
class=3D984131810-29102001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial>Best regards</FONT> </DIV></DIV>
<P><FONT color=3D#0000ff face=3DArial>Mike Fenner</FONT> <BR><FONT =
color=3D#0000ff=20
face=3DArial>Applications Engineer, European Operations</FONT> =
<BR><B><FONT=20
color=3D#0000ff face=3DArial>Indium Corporation</FONT></B> <BR><FONT =
color=3D#0000ff=20
face=3DArial> T: + 44 1908 580 400</FONT> <BR><FONT color=3D#0000ff =
face=3DArial>M: + 44 7810 526 317</FONT> <BR><FONT color=3D#0000ff=20
face=3DArial> F: + 44 1908 580 411</FONT> <BR><FONT color=3D#0000ff =
face=3DArial> E: [log in to unmask]</FONT> <BR><FONT =
color=3D#0000ff=20
face=3DArial>W: www.indium.com<BR>Leadfree:<U> <A =
href=3D"http://pb-free.com/"=20
target=3D_blank>http://Pb-Free.com</A></U> </FONT></P>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Guy Ramsey<BR><B>Sent:</B> =
Friday,=20
October 26, 2001 7:15 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> Re:=20
[TN] Cleaning paste when misaligned.<BR><BR></DIV></FONT>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D446215617-26102001>I=20
don't mean to cause any undue concern. The issue is fairly simple . . =
. You=20
can break glass and ceramic with sound but it is not likely if you are =
careful. But ultrasonic cleaning can break wire bonds, and wires, this =
is=20
especially true in controls, ceramic ICs and the like were the wires =
are not=20
encapsulated and subject to vibration. There are technologies that are =
effective in reducing this type of damage. Hope this relieves your =
fear. If=20
you are still concerned then you have some homework to do. What =
frequency and=20
power does you cleaner work at. What is a construction of the packages =
in=20
question . . . stuff like that.</SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; =
PADDING-LEFT: 5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Howard =
Watson<BR><B>Sent:</B>=20
Friday, October 26, 2001 11:46 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Cleaning paste when=20
misaligned.<BR><BR></DIV></FONT><BR><FONT face=3Dsans-serif =
size=3D2>Mike and=20
Guy,</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>We routinely =
clean the=20
second side of misprint solder paste, but from what you are saying =
perhaps=20
there could be a problem with damaging some components. The =
components=20
that we clean in the ultrasonic cleaner are mostly flat chip =
package, C lead=20
diodes, and some SOT-23 and SOIC. How do I verify which =
components can=20
or cannot go in the cleaner? Is there any test data out there =
to=20
support this issue? Though we clean very few misprints, I am a =
little=20
concerned. Thanks for your help!</FONT> <BR><BR><FONT =
face=3Dsans-serif=20
size=3D2>Howard Watson<BR>Manufacturing =
Engineer<BR>AMETEK/Dixson</FONT>=20
<BR><BR><BR>
<TABLE width=3D"100%">
<TBODY>
<TR vAlign=3Dtop>
<TD>
<TD><FONT face=3Dsans-serif size=3D1><B>"Barmuta, Mike"=20
<[log in to unmask]></B></FONT> <BR><FONT =
face=3Dsans-serif=20
size=3D1>Sent by: TechNet <[log in to unmask]></FONT>=20
<P><FONT face=3Dsans-serif size=3D1>10/26/01 09:02 AM</FONT> =
<BR><FONT=20
face=3Dsans-serif size=3D1>Please respond to "TechNet E-Mail=20
Forum."</FONT> <BR></P>
<TD><FONT face=3DArial size=3D1> =20
</FONT><BR><FONT face=3Dsans-serif size=3D1> =
=20
To: [log in to unmask]</FONT> =
<BR><FONT=20
face=3Dsans-serif size=3D1> cc: =
=20
</FONT> <BR><FONT face=3Dsans-serif =
size=3D1> =20
Subject: Re: [TN] =
Cleaning=20
paste when =
mis-aligned.</FONT></TD></TR></TBODY></TABLE><BR><BR><BR><FONT=20
face=3D"Courier New" size=3D2>Cathy: This should not be a problem =
for the bare=20
(unloaded) PCB. However if<BR>you are doing a double sided reflow =
and =20
misprint the second side you need<BR>to verify that the first side=20
components are compatible with the ultrasonics<BR>you are=20
using.<BR><BR><BR>Regards<BR><BR>Michael Barmuta<BR><BR>Staff=20
Engineer<BR><BR>Fluke Corp.<BR><BR>Everett=20
WA<BR><BR>425-446-6076<BR><BR>-----Original Message-----<BR>From: =
Cathy=20
Killen [mailto:[log in to unmask]]<BR>Sent: Friday, October 26, =
2001 7:30=20
AM<BR>To: [log in to unmask]<BR>Subject: [TN] Cleaning paste when=20
mis-aligned.<BR>Importance: High<BR><BR><BR>Hello All & the =
mountain dew=20
man.<BR>Can a mis-printed PCB be washed in a ultrasonic bath to =
remove all=20
paste<BR>particles?<BR>Is there any danger of damaging innerlayers =
of=20
PCB?<BR><BR>Thanks in advance.<BR><BR>Cathy Killen<BR>Training=20
Instructor<BR>Smtek Europe Ltd.<BR>The information contained in the =
E-mail=20
is confidential. It is intended only<BR>for the stated addressee(s) =
and=20
access to it by any other person is<BR>unauthorised.<BR>The views =
expressed=20
in this E-mail are those of the author, and do not<BR>represent the =
views of=20
Smtek Europe, its associates or subsidiaries, unless<BR>otherwise =
expressly=20
indicated.<BR>Please note: It is your responsibility to scan this =
E-mail for=20
=
viruses.<BR><BR>---------------------------------------------------------=
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Mail List provided as a free service by IPC using LISTSERV =
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NOMAIL<BR>Search previous postings at: www.ipc.org > On-Line =
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or=20
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--------------------------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV =
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Date: Mon, 29 Oct 2001 12:51:47 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Vacuum Packaging
MIME-Version: 1.0
Content-Type: text/plain
Hi all,
How long can you keep bare PCBs after they have been removed from their
original vacuum sealed packaging?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries, unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for viruses.
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Date: Mon, 29 Oct 2001 08:30:37 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Vacuum Packaging
In-Reply-To: <A1630D6F27C0D21198AF00805F613595465FED@DDLSBS>
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Boards are not always shipped in vacuum packs. Shelf life depends on many
variables, not the least of which are temperature and humidity. Surface
finish, flux activity level, substrate material, layer count, process method
(hand solder vrs mass reflow) . . .
A short answer is 6 months to a year for solderabitliy, bakeout maybe
advisable under some conditions to prevent failure in the board laminate.
A shorter answer is we need more information.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Cathy Killen
> Sent: Monday, October 29, 2001 7:52 AM
> To: [log in to unmask]
> Subject: [TN] Vacuum Packaging
>
>
> Hi all,
> How long can you keep bare PCBs after they have been removed from their
> original vacuum sealed packaging?
>
> Thanks in advance.
>
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
>
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Date: Mon, 29 Oct 2001 13:34:59 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
MIME-Version: 1.0
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Trials were also conducted in Plessey in the late 80s using an ICI u/s tank
and Arklone. The engineer concerned found that the standard packages used
were all OK after a total of 24 hours exposure. No functional degradation at
all, but, boy!, were they clean!
Unfortunately, the study was never published and the engineer himself passed
away a few years ago so I was never able to obtain confirmation in writing.
I am surprised that one of the larger suppliers of u/s cleaning equipment
has not undertaken a definitive study and published the results. Or have
they and I just missed it?
Regards
Eric Dawson
> -----Original Message-----
> From: Mike Fenner [SMTP:[log in to unmask]]
> Sent: Monday, October 29, 2001 10:26 AM
> To: [log in to unmask]
> Subject: Re: [TN] Cleaning paste when misaligned.
>
> Back in the days when F113 was the best thing since sliced bread there
> were several studies on bond wire integrity in ultrasonic cleaning. In
> this country by ICI (then supplying F113 cleaners under brand name
> Arklone, equivalent to Dupont Freon) and Marconi Stanmore in UK. Possibly
> also the UK National Physical Laboratory, although it might be that
> Marconi and NPL collaborated.
>
> Basically they concluded that there was possibly a problem with the then
> frequency used [40kHz], but this would really only affect poor quality
> wire bonds that would fail anyway. Modern units run at 70kHz and/or sweep
> the frequencies so eliminating the problem. This was all ages ago and my
> memory may be a little poor on the details, but the essentials are
> correct.
>
> Are we now saying that component sizes are now so reduced that there is a
> problem again?
>
> Best regards
>
> Mike Fenner
> Applications Engineer, European Operations
> Indium Corporation
> T: + 44 1908 580 400
> M: + 44 7810 526 317
> F: + 44 1908 580 411
> E: [log in to unmask]
> W: www.indium.com
> Leadfree: http://Pb-Free.com <http://pb-free.com/>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
> Sent: Friday, October 26, 2001 7:15 PM
> To: [log in to unmask]
> Subject: Re: [TN] Cleaning paste when misaligned.
>
>
> I don't mean to cause any undue concern. The issue is fairly simple
> . . . You can break glass and ceramic with sound but it is not likely if
> you are careful. But ultrasonic cleaning can break wire bonds, and wires,
> this is especially true in controls, ceramic ICs and the like were the
> wires are not encapsulated and subject to vibration. There are
> technologies that are effective in reducing this type of damage. Hope this
> relieves your fear. If you are still concerned then you have some homework
> to do. What frequency and power does you cleaner work at. What is a
> construction of the packages in question . . . stuff like that.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard
> Watson
> Sent: Friday, October 26, 2001 11:46 AM
> To: [log in to unmask]
> Subject: Re: [TN] Cleaning paste when misaligned.
>
>
>
> Mike and Guy,
>
> We routinely clean the second side of misprint solder paste,
> but from what you are saying perhaps there could be a problem with
> damaging some components. The components that we clean in the ultrasonic
> cleaner are mostly flat chip package, C lead diodes, and some SOT-23 and
> SOIC. How do I verify which components can or cannot go in the cleaner?
> Is there any test data out there to support this issue? Though we clean
> very few misprints, I am a little concerned. Thanks for your help!
>
> Howard Watson
> Manufacturing Engineer
> AMETEK/Dixson
>
>
>
> "Barmuta, Mike" <[log in to unmask]>
> Sent by: TechNet <[log in to unmask]>
>
> 10/26/01 09:02 AM
> Please respond to "TechNet E-Mail Forum."
>
>
>
> To: [log in to unmask]
> cc:
> Subject: Re: [TN] Cleaning paste when mis-aligned.
>
>
>
> Cathy: This should not be a problem for the bare (unloaded)
> PCB. However if
> you are doing a double sided reflow and misprint the
> second side you need
> to verify that the first side components are compatible with
> the ultrasonics
> you are using.
>
>
> Regards
>
> Michael Barmuta
>
> Staff Engineer
>
> Fluke Corp.
>
> Everett WA
>
> 425-446-6076
>
> -----Original Message-----
> From: Cathy Killen [mailto:[log in to unmask]]
> Sent: Friday, October 26, 2001 7:30 AM
> To: [log in to unmask]
> Subject: [TN] Cleaning paste when mis-aligned.
> Importance: High
>
>
> Hello All & the mountain dew man.
> Can a mis-printed PCB be washed in a ultrasonic bath to
> remove all paste
> particles?
> Is there any danger of damaging innerlayers of PCB?
>
> Thanks in advance.
>
> Cathy Killen
> Training Instructor
> Smtek Europe Ltd.
> The information contained in the E-mail is confidential. It
> is intended only
> for the stated addressee(s) and access to it by any other
> person is
> unauthorised.
> The views expressed in this E-mail are those of the author,
> and do not
> represent the views of Smtek Europe, its associates or
> subsidiaries, unless
> otherwise expressly indicated.
> Please note: It is your responsibility to scan this E-mail
> for viruses.
>
>
> --------------------------------------------------------------------------
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Date: Mon, 29 Oct 2001 13:43:04 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Brown <[log in to unmask]>
Organization: Xyratex
Subject: Re: Vacuum Packaging
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; format=flowed
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This very much depend upon the surface finish of the PCB's in question.
I've managed to solder Hot Air Solder Levelled PCBs which are twelve
month old and have not been in any vacuum packing. Some Organic Solder
Preservatives only have a shelf life of six months. Can you provide any
more information?
Steve Brown.
Xyratex Ltd.
Cathy Killen wrote:
>Hi all,
>How long can you keep bare PCBs after they have been removed from their
>original vacuum sealed packaging?
>
>Thanks in advance.
>
>Cathy Killen
>Training Instructor
>Smtek Europe Ltd.
>The information contained in the E-mail is confidential. It is intended only
>for the stated addressee(s) and access to it by any other person is
>unauthorised.
>The views expressed in this E-mail are those of the author, and do not
>represent the views of Smtek Europe, its associates or subsidiaries, unless
>otherwise expressly indicated.
>Please note: It is your responsibility to scan this E-mail for viruses.
>
>---------------------------------------------------------------------------------
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>---------------------------------------------------------------------------------
>
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Date: Mon, 29 Oct 2001 08:48:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Land Patterns
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I'd also love to see polarity, component markings, and wash/and wave
information in the specs that tell you if the component has to be hand
soldered at a final step or if you can install it prior to any wave
soldering and aqueous cleaning steps. Some manufacturer's do include this
information, but many out there do not.
--Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of <Peter George Duncan>
Sent: Sunday, October 28, 2001 7:27 PM
To: [log in to unmask]
Subject: Re: [TN] Land Patterns
If this information is so readily available, why don't manufacturers just
quote land patterns in their data sheets as a standard part of the format?
Very few do, and it's a real pain to ring up every one of them every time
to get this information. Yet everyone seems to accept this as the way it
is!
Can't IPC bring any pressure to bear on manufacturers to provide this
information as standard? Jack?
Peter Duncan
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Date: Mon, 29 Oct 2001 08:56:32 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Cleaning paste when misaligned.
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_ac.1cf641b8.290eba10_boundary"
--part1_ac.1cf641b8.290eba10_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Go to:
http://www.caeultrasonics.com/index.php3
Then click on any one of the technical papers. They're very detailed and talk
about what causes damage and how using multiple sweep frequencies eliminates
it.
Some pretty good stuff...
-Steve Gregory-
> Trials were also conducted in Plessey in the late 80s using an ICI u/s tank
> and Arklone. The engineer concerned found that the standard packages used
> were all OK after a total of 24 hours exposure. No functional degradation at
> all, but, boy!, were they clean!
> Unfortunately, the study was never published and the engineer himself passed
> away a few years ago so I was never able to obtain confirmation in writing.
> I am surprised that one of the larger suppliers of u/s cleaning equipment
> has not undertaken a definitive study and published the results. Or have
> they and I just missed it?
> Regards
> Eric Dawson
--part1_ac.1cf641b8.290eba10_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Go to:
<BR>
<BR>http://www.caeultrasonics.com/index.php3
<BR>
<BR>Then click on any one of the technical papers. They're very detailed and talk about what causes damage and how using multiple sweep frequencies eliminates it.
<BR>
<BR>Some pretty good stuff...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Trials were also conducted in Plessey in the late 80s using an ICI u/s tank
<BR>and Arklone. The engineer concerned found that the standard packages used
<BR>were all OK after a total of 24 hours exposure. No functional degradation at
<BR>all, but, boy!, were they clean!
<BR>Unfortunately, the study was never published and the engineer himself passed
<BR>away a few years ago so I was never able to obtain confirmation in writing.
<BR>I am surprised that one of the larger suppliers of u/s cleaning equipment
<BR>has not undertaken a definitive study and published the results. Or have
<BR>they and I just missed it?
<BR>Regards
<BR>Eric Dawson</FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_ac.1cf641b8.290eba10_boundary--
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Date: Mon, 29 Oct 2001 07:53:07 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ryan Grant <[log in to unmask]>
Subject: Re: Solving the 0.25% problem
Wow Steve! I never though of that. So if a small business has a couple of
automobiles (like construction contractors), would they fall under the TRI
reporting legislation when they buy replacement car batteries or another car
that has a battery in it? Come to think of it, the batteries in my diesel
pickup truck weigh at least 50-lbs., and it uses two batteries!
Ryan Grant
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Sunday, October 28, 2001 6:56 PM
> To: [log in to unmask]
> Subject: Re: [TN] Solving the 0.25% problem
>
> Hello Joe...
>
> Speaking for myself, you are singing to the choir (so to speak), I agree
> with you 100%!!!
>
> What's even more irritating is this new TRI reporting legislation. By what
> has been detailed out, some of my hunting buddies could be legally bound
> to submit because they use more than 100-lbs. of lead shot when reloading.
> The same thing could apply to commercial fishermen who make their own
> sinkers...
>
> It's a bunch of bull@$%t!!!
>
> -Steve Gregory-
>
>
>
>
> Hello friends,
>
> I continue to be amazed at how much energy is being leveled at the
> lead-free issue. Which is a shame because there are so many truly
> important issues that are not being looked into. Especially given that
> lead in electronics has never been shown to be a hazard or a problem to
> humans. (Lead in human blood plasma has actually gone down significantly
> in the past 20 years) CRTs are a possible exception as the leaded glass to
> stop x-rays may be an issue but that lead is at least bound in glass.
> (Alas, such the power of fear based marketing)
>
> In my limited research, lead in electronics appears to account for
> less than 0.5% of all lead used globally on an annual basis. It may be
> less than 0.25% as one soon to be released research report I just read has
> the number at 0.2% or a factor of 10 times less.
>
> (I know the IPC web site says less than 2% and it is true but not
> accurate because 0.5% is in fact less than 2%. It appears to have come
> from a US EPA study that was done in the 1980s and relates primarily to
> the US. I think they will get around to changing it someday when they have
> the time. I mentioned this to David some time back and he was going to
> have Chris look into it but Chris moved on before that happened, I am
> guessing)
>
> Remember that different profiles will be required for all of the
> different solders you use as military, medical, automotive and high
> reliability electronics are exempted you will likely have two or more
> solder lines running several different profiles. Also be reminded that the
> lines will likely have to be slowed down to get good wetting in reflow
> soldering and NEMI is recommending a wave soldering temperature of 275oC.
> You may wish to read the NCMS and NEMI reports.
>
> Remember also that there is no "world wide" directive yet. The US
> is, however, going to be taking a science based look at the issue. The
> IPC, EIA and EPA are going to do a co-sponsored risk analysis of
> lead-free. If a small part of what I have read and learned is true
> lead-free is going not going to get any green stickers due to the
> excessive energy requirements for prebakes and long assembly cycles.
>
> I have nothing to sell or gain from all of this, no matter what
> happens over the long haul I do, however, have a strong interest in truth.
> ( For the record, I also favored lead-free on principle when it first came
> about, but my deeper look into the matter has caused me to question the
> intelligence and rational of the movement)
>
> Best wishes and kind regard to all,
> Joe
>
>
>
>
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Date: Mon, 29 Oct 2001 08:52:44 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Reflow profiling
X-To: "Dorothy M. Lush" <[log in to unmask]>
I certainly do respect what you say, but doesn't this go back to electronic
assembly beginnings? I mean, we've always faced compromises from design
through customer acceptance.
I guess it's getting harder now, or is it just getting less DFM/CE
conscious. Engineers always cook up new needs based on market/customer
demand or what is perceived the market needs. They don't always see all the
way through all the processes required when effecting a design maybe based
on a single component. They certainly do not always consult with those who
know these effects and what is required to produce high quality assemblies
on time at the lowest cost and highest quality.
I keep going back, in my mind, to the early SMT days in the early '80's when
50 mil pitch stuff was the norm. At that time, I knew of many GOOD board fab
houses saying it would never be possible to get to 25 mils. Look at us now
and beyond. I also remember the days when RF engineers and designers
insisted on placing through holes in SMT pads and wondering why
solderability and chip component cracking were serious issues. Here too we
have come a long way in a short period.
Where I'm going with this is, as you know, there must be something amiss
when we have to profile a board around one or two components. Dorothy, as
you replied to another, remove the caps and replace them as you need. In
many cases, second ops are needed to handle unique devices. You know the
processes required as well - selective wave, etc.
As these compromises exist in every design we attempt. We must work together
more closely so one component doesn't hold up the show - either with better
device selections or better manufacturing capabilities. Having said that, it
is just too tough to profile a board focusing on such a wide temperature
range - between a few devices and so many others. It's better to effect a
better design or facilitate ways to add unique devices in a separate operation.
Earl Moon
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Date: Mon, 29 Oct 2001 08:57:58 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads...
X-To: "<Guenter Grossmann>" <[log in to unmask]>
Guenter,
As I probably will never visit your area of the world again, I have no
reason to "suck up." No matter, you serve us well so the compliment stands.
However, I still need to know how we can get around this issue of having to
either leave solder during rework, after device removal, and, if we do, how
we are expected to remove the IMC layer underneath to effect acceptable
solder joints.
Earl
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Date: Mon, 29 Oct 2001 15:10:29 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Kinner <[log in to unmask]>
Subject: Re: Masking For Conformal Coating
In-Reply-To: <[log in to unmask]>
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Mike,
Most people use a combination of liquid latex masks, tapes and moulded
rubber boots to mask their assemblies.
The methods used depend to a certain extent on the method of application
and the susceptibility of the coating to capillary action due to the
components in question.
Try HumiSeal www.humiseal.com - they should be able to point you in the
right direction for masking materials.
Hope this helps,
Best Regards,
Phil Kinner
Chief Chemist
Concoat Ltd
2C Albany Park, Frimley Road,
Camberley, Surrey, GU16 7PH
Tel: +44 (0) 1276 691100
Fax: +44 (0) 1276 691227
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subsidiaries each reserve the right to monitor all e-mail communications
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Any views expressed in this message are those of the individual sender,
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Thank You - Concoat Ltd
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Mike Manwell
Sent: 26 October 2001 23:30
To: [log in to unmask]
Subject: [TN] Masking For Conformal Coating
Hello,
Im just getting into coating a UV curable material and was wondering
what others use to mask parts that you dont want coating on, such as
LED's and odd shaped connectors. Any suggestions would be appriciated.
Mike Manwell
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<body lang=3DEN-GB link=3Dblue vlink=3Dpurple =
style=3D'tab-interval:36.0pt'>
<div class=3DSection1>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>Mike,<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>Most people use a combination of =
liquid
latex masks, tapes and moulded rubber boots to mask their =
assemblies.<span
style=3D'mso-spacerun:yes'> </span><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>The methods used depend to a =
certain extent
on the method of application and the susceptibility of the coating to =
capillary
action due to the components in question. <o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>Try <span =
class=3DSpellE>HumiSeal</span>
www.humiseal.com - they should be able to point you in the right =
direction for
masking materials.<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>Hope this =
helps,<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'>Best =
Regards,<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><o:p> </o:p></span></font></p>=
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Phil =
Kinner<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Chief =
Chemist<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Concoat =
Ltd<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>2C =
</span></font><st1:place><st1:PlaceName><font
size=3D2 color=3Dblue><span =
style=3D'font-size:10.0pt;color:blue'>Albany</span></font></st1:PlaceName=
><font
size=3D2 color=3Dblue><span style=3D'font-size:10.0pt;color:blue'> =
</span></font><st1:PlaceType><font
size=3D2 color=3Dblue><span =
style=3D'font-size:10.0pt;color:blue'>Park</span></font></st1:PlaceType><=
/st1:place><font
size=3D2 color=3Dblue><span style=3D'font-size:10.0pt;color:blue'>, =
</span></font><st1:Street><st1:address><span
class=3DSpellE><font size=3D2 color=3Dblue><span =
style=3D'font-size:10.0pt;
color:blue'>Frimley</span></font></span><font size=3D2 =
color=3Dblue><span
style=3D'font-size:10.0pt;color:blue'> =
Road</span></font></st1:address></st1:Street><font
size=3D2 color=3Dblue><span style=3D'font-size:10.0pt;color:blue'>, =
<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Camberley, =
</span></font><st1:place><st1:City><font
size=3D2 color=3Dblue><span =
style=3D'font-size:10.0pt;color:blue'>Surrey</span></font></st1:City><fon=
t
size=3D2 color=3Dblue><span style=3D'font-size:10.0pt;color:blue'>, =
</span></font><st1:PostalCode><font
size=3D2 color=3Dblue><span style=3D'font-size:10.0pt;color:blue'>GU16 =
7PH</span></font></st1:PostalCode></st1:place><font
size=3D2 color=3Dblue><span =
style=3D'font-size:10.0pt;color:blue'><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'><span
style=3D'mso-spacerun:yes'> </span><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Tel: +44 (0) 1276 =
691100<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D2 color=3Dblue face=3DArial><span
style=3D'font-size:10.0pt;color:blue'>Fax: +44 (0) 1276 =
691227<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 color=3Dblue face=3DArial><span
style=3D'font-size:12.0pt;color:blue'><span
style=3D'mso-spacerun:yes'> </span><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D1 color=3Dblue face=3DArial><span
style=3D'font-size:8.0pt;color:blue'><span
style=3D'mso-spacerun:yes'> </span>Attention: This message is for =
the named
person's use only. It may contain confidential, proprietary or legally
privileged information. No confidentiality or privilege is waived or =
lost by
any <span class=3DSpellE>mistransmission</span>. If you receive this =
message in
error, please immediately delete it and all copies of it from your =
system,
destroy any hard copies of it securely and notify the sender. You must =
not,
directly or indirectly, use, disclose, distribute, print, or copy any =
part of
this message if you are not the intended recipient. Concoat Ltd and any =
of its
subsidiaries each reserve the right to monitor all e-mail communications
through its networks.<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D1 color=3Dblue face=3DArial><span
style=3D'font-size:8.0pt;color:blue'>Any views expressed in this message =
are those
of the individual sender, except where the message states otherwise and =
the
sender is authorised to state them to be the views of Concoat Ltd or one =
of its
subsidiaries.<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D1 color=3Dblue face=3DArial><span
style=3D'font-size:8.0pt;color:blue'>Although this message has been =
scanned for
known viruses and inappropriate content, we recommend that recipients =
employ
appropriate measures on their systems to intercept any such =
material.<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D1 color=3Dblue face=3DArial><span
style=3D'font-size:8.0pt;color:blue'>Thank You - Concoat Ltd =
<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>-----Original
Message-----<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>From:
TechNet [mailto:[log in to unmask]] On Behalf <span class=3DGramE>Of</span> =
Mike <span
class=3DSpellE>Manwell</span><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>Sent:
26 October 2001 23:30<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>To:
[log in to unmask]<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>Subject:
[TN] Masking <span class=3DGramE>For</span> Conformal =
Coating<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>Hello,<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><span class=3DSpellE><font size=3D3 =
face=3DArial><span
style=3D'font-size:12.0pt'>Im</span></font></span> just getting into =
coating a UV
curable material and was wondering what others use to mask parts that =
you <span
class=3DSpellE>dont</span> want coating on, such as LED's and odd shaped
connectors. Any suggestions would be <span =
class=3DSpellE>appriciated</span>.<o:p></o:p></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>Mike
<span class=3DSpellE>Manwell</span><o:p></o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'><o:p> </o:p></span></font></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>----------------------------------------------=
-----------------------------------<o:p></o:p></span></font></p>
<p class=3DMsoPlainText><span class=3DSpellE><font size=3D3 =
face=3DArial><span
style=3D'font-size:12.0pt'>Technet</span></font></span> Mail List =
provided as a
free service by IPC using LISTSERV 1.8d To unsubscribe, send a message =
to
[log in to unmask] with following text in the BODY (NOT the subject =
field):
SIGNOFF <span class=3DSpellE>Technet</span> To temporarily halt delivery =
of <span
class=3DSpellE>Technet</span> send the following message: SET <span =
class=3DSpellE>Technet</span>
NOMAIL Search previous postings at: www.ipc.org > On-Line Resources =
&
Databases > E-mail Archives Please visit IPC web site
(http://www.ipc.org/html/forum.htm) for additional information, or =
contact <span
class=3DSpellE>Keach</span> <span class=3DSpellE>Sasamori</span> at =
[log in to unmask]
or 847-509-9700 ext.5315<o:p></o:p></p>
<p class=3DMsoPlainText><font size=3D3 face=3DArial><span =
style=3D'font-size:12.0pt'>----------------------------------------------=
-----------------------------------<o:p></o:p></span></font></p>
</div>
</body>
</html>
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=========================================================================
Date: Mon, 29 Oct 2001 10:27:31 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Give up on Solving the 0.25% problem
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Look, trying to hold the gummint to a responisible and reasonable, even
vaguely logical position is totally fruitless, and wastes everybody's
time....a classic example.....
It is illegal for every business in the US to clean their toilets.
You see, all toilet cleaners are strong acids, usually they are Hydrochloric
(Muriatic) Acid, and when you flush them away the pH is WAY below allowable
minimums....
Everyone of us ought to turn ourselves in, and admit to polluting for all of
our business lives...wouldn't that make the EPA crazy?
Rudy Sedlak
RD Chemical Company---We refuse to discuss even IF we clean our toilets!
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=========================================================================
Date: Mon, 29 Oct 2001 10:57:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Text Comparing Editor
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi All,
Does anyone know about a software or utility that allows you to compare
two or more text files? I need to edit a DXF file and is necessary to
compare it with
an original file.
I thank you in advance,
Shahed
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=========================================================================
Date: Sun, 15 Jul 2001 12:23:08 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Applying HAL on Electroles Nickel Gold
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_e4.17cbea3c.28831d6c_boundary"
--part1_e4.17cbea3c.28831d6c_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Tamir,
What is the thickness of the gold deposit.
If it is a thin immersion caoting, embrittlement will not be an issue, if it
is a thick coating then you need to calculate if the gold will be more tha 3%
of the solder.
George Milad
Shipley Co.
--part1_e4.17cbea3c.28831d6c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Tamir,
<BR>What is the thickness of the gold deposit.
<BR>If it is a thin immersion caoting, embrittlement will not be an issue, if it
<BR>is a thick coating then you need to calculate if the gold will be more tha 3%
<BR>of the solder.
<BR>George Milad
<BR>Shipley Co.</FONT></HTML>
--part1_e4.17cbea3c.28831d6c_boundary--
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=========================================================================
Date: Mon, 16 Jul 2001 09:36:06 -0400
Reply-To: Mark Charlton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Charlton <[log in to unmask]>
Organization: MSI of Central Florida, Inc.
Subject: Re: ICT Test Points
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I remember reading a report or apps notefrom HP or GenRad that addressed
this very issue. I'm sure either sales force would be willing to help. I
got such information from our fixture vendors as well.
Mark
----- Original Message -----
From: "Michael Forrester" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, July 16, 2001 9:14 AM
Subject: ICT Test Points
> Does anyone have any statistics on ICT reliability based on test point
size?
> What I am looking for
> is information on what am I giving up, other than cost, by going from a
.035
> test pad to a .025 test pad.
> Is there a reliability curve based on test point size? Any help would be
> appreciated. Thank you.
>
> Best Regards,
>
> Michael Forrester
> LeCroy Corp.
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date: Sun, 15 Jul 2001 16:09:36 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: FLEX CIRCUIT FAILURE
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Joe,
>1) IS THIS 30 DEGREE ANGLE A REAL PROBLEM ?
Without actually seeing your design and the failures, one cannot say for
sure. However, the angle is not likely to be the or evan a part of the
problem.
>2)IS THERE POSSIBLY MORE THAT I SHOULD BE LOOKING AT?
Yes. What is the failure mode--through the solder or interfacial? How long is
the hot bar tool? Where along the tool contact length are the failures? Are
they typically at the same location? When are the failures occurring? How are
the SJs loaded--CTE-mismatch, vibrationn, mechanical shock, cyclic or
steady-state?
>3)IS THERE A WAY OF SOLVING THIS PROBLEM WITHOUT MOVING THE COMPONENTS?
Possibly, but without having any of the details i cannot be sure.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Mon, 16 Jul 2001 09:20:55 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Lead protrusion
MIME-Version: 1.0
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A long time ago, we once had a cutter for cropping leads after wave solder,
but it was peculiarly unreliable in its consistency. The blades would go
blunt very quickly and make a dreadful job of cutting leads cleanly. When
the lead is cut almost through, the weight of the lead and the pressure of
the cutter tended to break rather than cut the final part leaving rather a
rag or a smear. We gave up using the machine eventually and took to hand
cropping, but the shock of the 'snap' as the cutters through each lead
cannot have been very good for the joints.
The kindest way to treat the solder joints is to preform and trim the leads
so that they are soldered only once and require no cropping at all. We
found that many components habitually rode up in the solder wave to the
extent that minimum protrusion wasn't always achieved and rework had to be
performed. The test jig we had then couldn't handle clinched leads, though
that is the best way to go - preform, insert, clinch (half or full), trim,
solder.
Be careful cutting the leads of any components with a glass-to-metal seal -
they really don't like too much shock, so hand-cutting should be avoided.
Pete Duncan
"Pelchat,
Janice" To: [log in to unmask]
<JANICE.PELCHAT@ cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
BENCH.COM> Subject: Re: [TN] Lead protrusion
Sent by: TechNet
<[log in to unmask]
>
07/13/01 06:53
PM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to "Pelchat,
Janice"
Where I worked before, the wave solder machine had an inline cutter that
worked with the machine.
Solder, inline cut (Circular saw on its side basically), resolder, out the
other end. No manual cutting allowed.
Jan Pelchat
Benchmark Electronics
> -----Original Message-----
> From: Dorothy M. Lush [SMTP:[log in to unmask]]
> Sent: Thursday, July 12, 2001 7:32 PM
> To: [log in to unmask]
> Subject: Re: [TN] Lead protrusion
>
> Peter,
> Bill is right about the need to avoid trimming leads after solderwave.
The
> thicker the lead and/or cheaper the cutter the more likely there will be
a
> cracked solder joint. IPC class-2 says that this cracked solder joint
does
> not need to be remelted and class-3 says it does. Class-2 recommends
> 60-100
> mils lead length unless otherwise specified by the customer. If you are
> building to Class-2 and you don't want a possible lab or field failure
> because of a cracked solder joint then think and plan ahead to avoid
> having
> to trim. The thinking and planning includes the final assembly the PCA
> will
> be in. For instance, clearance for slot cards to slid in and out.
> Connector
> leads under a front panel even with an insulation strip can cut through
> the
> insulation eventually fail. I had a customer who wanted me to trim 70
mil
> plus diameter pins to 30 mils on the off the shelf power supply instead
of
> ordering the right length leads. They would have to be machined to do
that
> which can lead to other defects.
> Dorothy Lush
>
> > ----------
> > From: Kasprzak, Bill (sys) USX[SMTP:[log in to unmask]]
> > Reply To: TechNet E-Mail Forum.;Kasprzak, Bill (sys) USX
> > Sent: Thursday, July 12, 2001 12:58 PM
> > To: [log in to unmask]
> > Subject: Re: Lead protrusion
> >
> > Peter:
> >
> > Personally, I like .090", but typically I have to hold between .040 and
> > .060. In my mind, I think you would like to install parts with the
> correct
> > lead length prior to wavesoldering. Avoid having to trim after
soldering
> > is
> > always a good idea.
> >
> > Bill Kasprzak
> > Moog Inc., Electronic Assembly Engineering
> >
> >
> > > -----Original Message-----
> > > From: PL [SMTP:[log in to unmask]]
> > > Sent: Thursday, July 12, 2001 2:26 AM
> > > To: [log in to unmask]
> > > Subject: [TN] Lead protrusion
> > >
> > > Hello,
> > >
> > > Does anyone know what is the standard used for prepping
> > > the leads for through-hole boards?
> > >
> > > What are the critical parameters one should consider
> > > when determining the amount of trimming on the leads?
> > >
> > > Rgds,
> > > Peter
> > >
> > >
> > > _________________________________________________________
> > > Do You Yahoo!?
> > > Get your free @yahoo.com address at http://mail.yahoo.com
> > >
> > >
> >
>
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> > >
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Date: Wed, 18 Jul 2001 09:23:35 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Just a question...
In-Reply-To: <[log in to unmask]>
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Steve: I would put it like this:
you probably get better value for your membership fees than most....but
give good value too.!
Mike Fenner
Indium Corporation of Europe
T: + 44 1908 580 400
F: + 44 1908 580 411
M: + 44 7810 526 317
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Wednesday, July 18, 2001 4:38 AM
To: [log in to unmask]
Subject: [TN] Just a question...
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I
see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case,
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go
with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
------=_NextPart_000_0017_01C10F6B.526F55B0
Content-Type: text/html;
charset="us-ascii"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial><SPAN =
class=3D640252008-18072001>Steve: I=20
would put it like this:</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial><SPAN =
class=3D640252008-18072001> you=20
probably get better value for your membership fees than=20
most....</SPAN></FONT><FONT color=3D#0000ff face=3DArial><SPAN=20
class=3D640252008-18072001>but give good value =
too.!</SPAN></FONT></DIV>
<P><FONT face=3DArial size=3D2>Mike Fenner</FONT> <BR><FONT face=3DArial =
size=3D2>Indium=20
Corporation of Europe</FONT> <BR><FONT face=3DArial size=3D2> T: + =
44 1908 580=20
400</FONT> <BR><FONT face=3DArial size=3D2> F: + 44 1908 580 =
411</FONT>=20
<BR><FONT face=3DArial size=3D2>M: + 44 7810 526 317</FONT> </P>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. =
Gregory<BR><B>Sent:</B>=20
Wednesday, July 18, 2001 4:38 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Just a=20
question...<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>I've=20
gotta off-the-wall question...am I the only one that faces the stuff =
<BR>that=20
I post about, or am I the only one that posts about the problems I =
see?=20
<BR>Just curious... <BR><BR>It seems like I have a "black-cloud" =
following=20
me...if that's the case, maybe <BR>I should persue a different=20
profession....hehehe. <BR><BR>Anyways, do any of you see the same =
stuff that I=20
do? Does this stuff go with <BR>the territory? Kinda think it does, =
but nobody=20
whines like I do...hehehe. <BR><BR>Thanks.... <BR><BR>-Steve =
Gregory-</FONT>=20
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 18 Jul 2001 13:40:51 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: Just a question...
In-Reply-To: <[log in to unmask]>
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Steve, maybe you just need a new Suzuki Katana (although I prefer my
Corvette) to outrace that "black cloud".
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Tuesday, July 17, 2001 8:38 PM
To: [log in to unmask]
Subject: [TN] Just a question...
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case,
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
------=_NextPart_000_0032_01C10F8F.42C2FEE0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D950433720-18072001>Steve, maybe you just need a new =
Suzuki=20
<SPAN class=3D950433720-18072001>K</SPAN>atana (although I prefer =
my=20
Corvette)<SPAN class=3D950433720-18072001> to outrace that "black =
cloud".=20
</SPAN></SPAN></DIV>
<DIV> </DIV>
<DIV>David Ricketts<BR><BR>Pertek Engineering<BR>Voice:=20
949-475-4485<BR>Fax: 949-475-4493 </DIV>
<P><FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. =
Gregory<BR><B>Sent:</B>=20
Tuesday, July 17, 2001 8:38 PM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B>=20
[TN] Just a question...<BR><BR></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>I've gotta off-the-wall question...am I the only one that faces =
the stuff=20
<BR>that I post about, or am I the only one that posts about the =
problems I see?=20
<BR>Just curious... <BR><BR>It seems like I have a "black-cloud" =
following=20
me...if that's the case, maybe <BR>I should persue a different=20
profession....hehehe. <BR><BR>Anyways, do any of you see the same stuff =
that I=20
do? Does this stuff go with <BR>the territory? Kinda think it does, but =
nobody=20
whines like I do...hehehe. <BR><BR>Thanks.... <BR><BR>-Steve =
Gregory-</FONT>=20
</FONT></P></BODY></HTML>
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Date: Mon, 16 Jul 2001 09:40:12 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: FLEX CIRCUIT FAILURE
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
The 30 degree angle shouldn't in itself be a problem. Are the leaads
pre-formed to this angle? If they're not, then there could be a leverage
effect from the flex being forced up over the components. How much
unsupported flex is there? i.e. do you have a long run of flex after the
solder joints before it either terminates again or passes through a
securing tie/clip.
Pre-formed flexis perform pretty well in my experience, while flexis that
are forced into a shape they're not pre-fomed for can have numerous
problems. Talk to your flex manufacturer about the problems you're having
and the design that the flexi is part of see what they suggest. An
alternative (though I'm reluctant to suggest it, as it seems like a
backward step) is to have the terminations made as through-hole and wave
solder the thing.
Pete Duncan
Joseph Keary
<jkeary@SYSTR To: [log in to unmask]
ON.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: Subject: [TN] FLEX CIRCUIT FAILURE
TechNet
<[log in to unmask]
ORG>
07/14/01
02:55 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Joseph Keary
HELLO TECHNETERS
GOOD FRIDAY TO YOU ALL
I HAVE A PROBLEM THAT I AM HOPING SOMEBODY CAN HELP WITH. I HAVE A FLEX
CIRCUIT BEING HOTBAR SOLDERED TO A PCB. THERE ARE COMPONENTS UNDER THE FLEX
CIRCUIT. THIS CAUSES THE FLEX TO EXIT THE SOLDER JOINT AT ABOUT A 30 DEGREE
ANGLE. WE ARE PRESENTLY HAVING FAILURES IN THE SOLDER JOINTS OF THE FLEX TO
PCB. THE COMPONENTS UNDER THE FLEX STRIP ARE WELL PLACED (FILTER CAPS).
MOVING THESE PARTS COULD CAUSE THE PCB NOT TO PASS EMC TEST. THESE
ASSEMBLIES GO INTO AN ENVIROMENT THAT HAS A LOT OF VIBRATION INVOLVED.
1) IS THIS 30 DEGREE ANGLE A REAL PROBLEM ?
2)IS THERE POSSIBLY MORE THAT I SHOULD BE LOOKING AT?
3)IS THERE A WAY OF SOLVING THIS PROBLEM WITHOUT MOVING THE COMPONENTS
ALL COMMENTS GREATLY APPRECIATED
THANKYOU
JOE KEARY
SR. PCB DESIGNER
SYSTRON AND DONNER
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Date: Mon, 16 Jul 2001 01:00:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mark Orlowski <[log in to unmask]>
Subject: Mark Orlowski/PEMSTAR Inc is out of the office.
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I will be out of the office starting 07/14/2001 and will not return until
07/19/2001.
I will respond to your message when I return.
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Date: Mon, 16 Jul 2001 09:27:15 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Plugged vias
MIME-Version: 1.0
Content-Type: text/plain
Hi,
This subject is being discussed form time to time by forum.
During production of PCB we are facing more and problems with accuracy of
plugging , especially on dence SMD and BGA boards.
The plugging is done by screen printing and the main problem is
registration. At this stage of production we are facing most problems of
tolerances between drilling and circuitry pattern image and in dence boards
this lead us to plugging problems.
I do believe,that they are lot of people in the industry with the same
problem and I am just wondering what methods are used by other.
regards
Edward
Edward Szpruch
Eltek , Manager of Process Engineering
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
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Date: Mon, 16 Jul 2001 09:41:41 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bartkowaik Christine <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bartkowaik Christine <[log in to unmask]>
Subject: Re: ICT Test Points
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Michael:
The fixture company in which we use is allowing us to use .025" test pads on
our up and coming PCB. Approx. 675 test pads. There is an additional
fixture cost for their custom "guided probe plate". This will be our first
fixture with .025" test pads. They tell me there will be no problems
probing these test pads.
Regards, Chris Bartkowiak
Acu-Rite Inc
-----Original Message-----
From: Michael Forrester [SMTP:[log in to unmask]]
Sent: Monday, July 16, 2001 9:14 AM
To: [log in to unmask]
Subject: [TN] ICT Test Points
Does anyone have any statistics on ICT reliability based on test
point size?
What I am looking for
is information on what am I giving up, other than cost, by going
from a .035
test pad to a .025 test pad.
Is there a reliability curve based on test point size? Any help
would be
appreciated. Thank you.
Best Regards,
Michael Forrester
LeCroy Corp.
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Date: Mon, 16 Jul 2001 09:05:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Neda Thrash <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Neda Thrash <[log in to unmask]>
Subject: Re: Lead protrusion
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
I beg your pardon for my jumping in the middle here but this is of =
interest to me since I am currently looking for the best tool for =
clinching/cutting. Any suggestions? I need hand tools for approximately =
200 operators.
TIA.
>>> [log in to unmask] 07/15/01 08:20PM >>>
A long time ago, we once had a cutter for cropping leads after wave =
solder,
but it was peculiarly unreliable in its consistency. The blades would go
blunt very quickly and make a dreadful job of cutting leads cleanly. When
the lead is cut almost through, the weight of the lead and the pressure of
the cutter tended to break rather than cut the final part leaving rather a
rag or a smear. We gave up using the machine eventually and took to hand
cropping, but the shock of the 'snap' as the cutters through each lead
cannot have been very good for the joints.
The kindest way to treat the solder joints is to preform and trim the =
leads
so that they are soldered only once and require no cropping at all. We
found that many components habitually rode up in the solder wave to the
extent that minimum protrusion wasn't always achieved and rework had to be
performed. The test jig we had then couldn't handle clinched leads, though
that is the best way to go - preform, insert, clinch (half or full), trim,
solder.
Be careful cutting the leads of any components with a glass-to-metal seal =
-
they really don't like too much shock, so hand-cutting should be avoided.
Pete Duncan
"Pelchat,
Janice" To: [log in to unmask]
<JANICE.PELCHAT@ cc: (bcc: DUNCAN Peter/Asst=
Prin Engr/ST Aero/ST Group)
BENCH.COM> Subject: Re: [TN] Lead =
protrusion
Sent by: TechNet
<[log in to unmask]
>
07/13/01 06:53
PM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to "Pelchat,
Janice"
Where I worked before, the wave solder machine had an inline cutter that
worked with the machine.
Solder, inline cut (Circular saw on its side basically), resolder, out the
other end. No manual cutting allowed.
Jan Pelchat
Benchmark Electronics
> -----Original Message-----
> From: Dorothy M. Lush [SMTP:[log in to unmask]]=20
> Sent: Thursday, July 12, 2001 7:32 PM
> To: [log in to unmask]
> Subject: Re: [TN] Lead protrusion
>
> Peter,
> Bill is right about the need to avoid trimming leads after solderwave.
The
> thicker the lead and/or cheaper the cutter the more likely there will be
a
> cracked solder joint. IPC class-2 says that this cracked solder joint
does
> not need to be remelted and class-3 says it does. Class-2 recommends
> 60-100
> mils lead length unless otherwise specified by the customer. If you are
> building to Class-2 and you don't want a possible lab or field failure
> because of a cracked solder joint then think and plan ahead to avoid
> having
> to trim. The thinking and planning includes the final assembly the PCA
> will
> be in. For instance, clearance for slot cards to slid in and out.
> Connector
> leads under a front panel even with an insulation strip can cut through
> the
> insulation eventually fail. I had a customer who wanted me to trim 70
mil
> plus diameter pins to 30 mils on the off the shelf power supply instead
of
> ordering the right length leads. They would have to be machined to do
that
> which can lead to other defects.
> Dorothy Lush
>
> > ----------
> > From: Kasprzak, Bill (sys) USX[SMTP:[log in to unmask]]=20
> > Reply To: TechNet E-Mail Forum.;Kasprzak, Bill (sys) USX
> > Sent: Thursday, July 12, 2001 12:58 PM
> > To: [log in to unmask]
> > Subject: Re: Lead protrusion
> >
> > Peter:
> >
> > Personally, I like .090", but typically I have to hold between .040 =
and
> > .060. In my mind, I think you would like to install parts with the
> correct
> > lead length prior to wavesoldering. Avoid having to trim after
soldering
> > is
> > always a good idea.
> >
> > Bill Kasprzak
> > Moog Inc., Electronic Assembly Engineering
> >
> >
> > > -----Original Message-----
> > > From: PL [SMTP:[log in to unmask]]
> > > Sent: Thursday, July 12, 2001 2:26 AM
> > > To: [log in to unmask]
> > > Subject: [TN] Lead protrusion
> > >
> > > Hello,
> > >
> > > Does anyone know what is the standard used for prepping
> > > the leads for through-hole boards?
> > >
> > > What are the critical parameters one should consider
> > > when determining the amount of trimming on the leads?
> > >
> > > Rgds,
> > > Peter
> > >
> > >
> > > _________________________________________________________
> > > Do You Yahoo!?
> > > Get your free @yahoo.com address at http://mail.yahoo.com=20
> > >
> > >
> >
>
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> > >
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Date: Thu, 19 Jul 2001 10:50:43 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: White residue from conformal coating
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Kathy
I suggest that your problem will be related to high humidity during
application. What you describe we would refer to as "blushing" or
"milk-effect". It is caused by excessive moisture either in the room during
application - usually spraying, but might originate from the air-line to the
gun.
In our coating facility - where they complained about the recent heat-wave
so now enjoy a "work naked bonus" - we maintain humidity using
de-humidifiers to between 40% and 60% RH. Too dry = ESD issues - Too humid =
Your problem.
Will it go away Yes! Dry / oven cure them as suggested, it wont leave any
cracks or holes! Then get your humidity under control.
Regards, Graham Naisbitt
[log in to unmask]
http:// www.concoat.co.uk <http://www.concoat.co.uk>
For instant access to Product Data Sheets register on the Tech-Shot area of
http:// www.concoat.co.uk <http://www.concoat.co.uk>
Concoat Limited
Alasan House, Albany Park
CAMBERLEY GU16 7PH UK
Phone: +44 (0)1276 691100
Fax: +44 (0)1276 691227
Mobile: +44 (0)79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kathy Kuhlow
Sent: Wednesday, July 18, 2001 10:11
To: [log in to unmask]
Subject: Re: [TN] White residue from conformal coating
Hans,
It appears to be in the coating. On the uncoated boards there are no
visible residues, fingerprints, etc. And it is very hot and humid today
and yesterday (dew point low to mid 70's).
Kathy
>>> [log in to unmask] 07/18/01 12:53PM >>>
Kathy,
Is the white residue in the coating or on the assemblies surface?
It's probably moisture related as has been discussed recently.
Do you dry the assemblies prior to coating?
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Process Engineer
Toppan Electronics, Inc.
770 Miramar Road
San Diego, CA 92126
(858) 695 - 2222 ext. 241
(858) 695 - 6823 fax
[log in to unmask]
-----Original Message-----
From: Kathy Kuhlow [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 10:24 AM
To: [log in to unmask]
Subject: [TN] White residue from conformal coating
What causes white residues after conformal coating? The coating is an
acrylic and after the first coat there appears to be a white residue and
after the 24 hour cure the coating appears very dull and still has some of
the white residues. The residues almost look like water flux residue but it
isn't. The supplier that the coating was purchased from says it is strictly
humidity related and only a cosmetic issue. There is no visible loss of
adhesion. The solder mask is a LPI matte finish. Can this be part of the
problem?
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Date: Thu, 19 Jul 2001 21:10:43 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: Gerber specification
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Hi Dee,
Have a look at this document: http://194.7.253.113/ets//data/rs274xc.pdf
Daan Terstegge
www.smtinfo.net
----- Original Message -----
From: "Dee Stover" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, July 19, 2001 7:37 PM
Subject: [TN] Gerber specification
> I need to find the specifications of gerber language, would any of you
know
> where I can get that information.
>
> TIA
>
>
> Dee Stover [log in to unmask]
> Associate Technician Design
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520-318-8489
> FAX 520-318-8303
>
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Date: Mon, 16 Jul 2001 09:11:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Brooks,Bill" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Brooks,Bill" <[log in to unmask]>
Subject: Re: Recommendations for developing a mold
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Bill,
I don't claim to be an expert in the field of over molding or potting
electronics... but the first guy I would talk with in researching the
molding of plastics in any form would be Bill Sandford at Hi-Rel Corp in
Riverside Calif. He has done some work for me in the past and I recommend
him highly. A very knowledgeable guy.
Also, the potting of transformers and chokes would be cleaner if they were
molded similar to the way axial leaded capacitors are over molded. I was
involved with a leaded chip capacitor application where we used pelletized
thermoplastic resin and injection over molded the capacitors into a DIP
pattern for the '2 pin dip' style caps that have been replaced with surface
mounted caps today, (lead-less). I know that Pico over molds their
transformers for current sense applications.. A similar process should work
for you. Figure to spend 10K on Tooling, and have a high volume application
so you can amortize the cost of the tooling over the life of the product...
If you have a low volume product, you may be stuck with the messy potting
compounds for cost reasons...
Hope that helps a little... ;)
Bill Brooks
PCB Design Engineer
DATRON WORLD COMMUNICATIONS INC.
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm
-----Original Message-----
From: Kasprzak, Bill (sys) USX [mailto:[log in to unmask]]
Sent: Monday, July 16, 2001 8:51 AM
To: [log in to unmask]
Subject: [TN] Recommendations for developing a mold
Hello all,
I am involved with a project that requires that I encapsulate a pc board in
mold so that when completed, it will be a ring with an ID of 1.37" and an OD
of 1.64". The ring will be .13" thick and .35" tall. There will be six, 28
AWG wires exiting the finished potted assembly. The potting compound will be
Emerson & Cumings 2651-40 with Catalyst 11.
I have a basic 3 piece mold that works OK, but the pieces only
reflect what the final product should look like. It takes a little work to
get the mold apart even though mold release is used. The cure for the
potting is 8 - 16 hours at 180 deg F
What I'm looking for is any tricks and hints that should be incorporated
into the mold design that would facilitate easy processing. What I mean is
to make it easier to pour the material, easy to assemble into the mold, easy
to take apart, etc. etc. Right now the whole process just seems to be crude
and messy. Maybe, that's just the nature of the beast.
Any and all responses appreciated. Thanks.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
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Date: Mon, 29 Oct 2001 11:30:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Text Comparing Editor
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Shahed,
I have used and like Araxis Merge 2000 for comparing 2 or 3 documents
for changes. Go to www.araxis.com for details.
Phil Nutting
-----Original Message-----
From: Safavi-Bayat Shahed [mailto:[log in to unmask]]
Sent: Monday, October 29, 2001 10:57 AM
To: [log in to unmask]
Subject: [TN] Text Comparing Editor
Hi All,
Does anyone know about a software or utility that allows you to compare
two or more text files? I need to edit a DXF file and is necessary to
compare it with
an original file.
I thank you in advance,
Shahed
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Date: Mon, 29 Oct 2001 11:36:51 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Blasts from the past?!??
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_79.1d400295.290edfa3_boundary"
--part1_79.1d400295.290edfa3_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Did any of you just get some replys to some postings that were from back in
July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
--part1_79.1d400295.290edfa3_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Did any of you just get some replys to some postings that were from back in July?
<BR>
<BR>I did...got about 3 or 4 of them.....strange....
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_79.1d400295.290edfa3_boundary--
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Date: Mon, 29 Oct 2001 10:43:03 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: Blasts from the past?!??
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C16098.C73A5970"
This message is in MIME format. Since your mail reader does not understand
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Yup, I was just sending the same question out to the forum, so you are not
alone.
I assume there's a glitch in the server??
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: October 29, 2001 10:37 AM
To: [log in to unmask]
Subject: [TN] Blasts from the past?!??
Did any of you just get some replys to some postings that were from back in
July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
------_=_NextPart_001_01C16098.C73A5970
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.3314.2100" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=060134316-29102001>Yup, I
was just sending the same question out to the forum, so you are not
alone.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=060134316-29102001>I
assume there's a glitch in the server??</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> October 29, 2001 10:37
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Blasts from the
past?!??<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT size=2>Did any
of you just get some replys to some postings that were from back in July?
<BR><BR>I did...got about 3 or 4 of them.....strange.... <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C16098.C73A5970--
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Date: Mon, 29 Oct 2001 16:45:43 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Blasts from the past?!??
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_001E_01C16099.271E6250"
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------=_NextPart_000_001E_01C16099.271E6250
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Yep me to, for a moment I thought it was late night TV..
Best regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Monday, October 29, 2001 4:37 PM
To: [log in to unmask]
Subject: [TN] Blasts from the past?!??
Did any of you just get some replys to some postings that were from back
in July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
------=_NextPart_000_001E_01C16099.271E6250
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial><SPAN =
class=3D018374416-29102001>Yep me to, =20
for a moment I thought it was late night TV..</SPAN></FONT></DIV>
<DIV> </DIV>
<P><FONT color=3D#0000ff face=3DArial>Best regards</FONT> </P>
<P><FONT color=3D#0000ff face=3DArial>Mike</FONT></P>
<P><FONT color=3D#0000ff face=3DArial></FONT> </P>
<P> <FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B>=20
TechNet [mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R.=20
Gregory<BR><B>Sent:</B> Monday, October 29, 2001 4:37 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Blasts from the =
past?!??<BR><BR></P>
<BLOCKQUOTE></FONT><FONT face=3Darial,helvetica><FONT size=3D2>Did any =
of you just=20
get some replys to some postings that were from back in July? =
<BR><BR>I=20
did...got about 3 or 4 of them.....strange.... <BR><BR>-Steve =
Gregory-</FONT>=20
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 29 Oct 2001 11:53:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: Blasts from the past?!??
MIME-version: 1.0
Content-type: multipart/mixed; boundary="------------InterScan_NT_MIME_Boundary"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
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Yeah, but the system says it is working correctly!?!
Jeffrey
[log in to unmask]
4-7582
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Monday, October 29, 2001 11:37 AM
To: [log in to unmask]
Subject: [TN] Blasts from the past?!??
Did any of you just get some replys to some postings that were from back in
July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
------_=_NextPart_001_01C1609A.3B87CC30
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2600.0" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=265585216-29102001><FONT color=#0000ff>Yeah, but the system
says it is working correctly!?!</FONT></SPAN></DIV>
<DIV> </DIV>
<P><I><FONT face="Comic Sans MS" color=#008080 size=5>Jeffrey</FONT></I>
<BR><FONT face=Arial>[log in to unmask]</FONT> <BR><FONT
face=Arial>4-7582</FONT> </P>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, October 29, 2001 11:37
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Blasts from the
past?!??<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Did any
of you just get some replys to some postings that were from back in July?
<BR><BR>I did...got about 3 or 4 of them.....strange.... <BR><BR>-Steve
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C1609A.3B87CC30--
--------------InterScan_NT_MIME_Boundary--
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Date: Mon, 16 Jul 2001 10:08:56 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Recommendations for developing a mold
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
i think the suggestions for adding a draft angle to the walls of the mold are what you need. i'd also suggest that stay with an aluminum mold and get the inside of the mold teflon coated. your parts will come out without any release on them. also you might think about cutting slots at the seam of the mold so that you can get something like a screwdriver in there to help pry the pieces of the mold apart.
phil
-----Original Message-----
From: Kasprzak, Bill (sys) USX [mailto:[log in to unmask]]
Sent: Monday, July 16, 2001 8:51 AM
To: [log in to unmask]
Subject: [TN] Recommendations for developing a mold
Hello all,
I am involved with a project that requires that I encapsulate a pc board in
mold so that when completed, it will be a ring with an ID of 1.37" and an OD
of 1.64". The ring will be .13" thick and .35" tall. There will be six, 28
AWG wires exiting the finished potted assembly. The potting compound will be
Emerson & Cumings 2651-40 with Catalyst 11.
I have a basic 3 piece mold that works OK, but the pieces only
reflect what the final product should look like. It takes a little work to
get the mold apart even though mold release is used. The cure for the
potting is 8 - 16 hours at 180 deg F
What I'm looking for is any tricks and hints that should be incorporated
into the mold design that would facilitate easy processing. What I mean is
to make it easier to pour the material, easy to assemble into the mold, easy
to take apart, etc. etc. Right now the whole process just seems to be crude
and messy. Maybe, that's just the nature of the beast.
Any and all responses appreciated. Thanks.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
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Date: Mon, 29 Oct 2001 17:56:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Text Comparing Editor
X-To: [log in to unmask]
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Shahed,
I don't get the idea of editing graphical files with a text-editor, but =
anyway, I suggest you visit http://www.nisnevich.com/examdiff/examdiff.htm =
and download the freeware version of ExamDiff. It does an excellent job =
comparing text-files.
There's also a shareware version available, with some extra features, in =
case you need them.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Safavi-Bayat Shahed <[log in to unmask]> 10/29 4:57 pm >>>
Hi All,
Does anyone know about a software or utility that allows you to compare
two or more text files? I need to edit a DXF file and is necessary to
compare it with
an original file.
I thank you in advance,
Shahed
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Date: Mon, 16 Jul 2001 17:00:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Cleaning No-Clean
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Alan,
Alpha 205R is what we used to use before we switched to Alpha Lonco 373 (an
OA flux). We also got the white residue. Our solutions was to change the
entire supply of flux in the machine. Essentially this was a complete
cleaning if the fluxing system. We also used small dams on the front of the
boards. These would build up a layer of white guck that was like soap stone
in feel. Cleaning this white residue off the boards was almost impossible.
Alcohol didn't want to touch it. Scrubbing and buffing only made the
assemblers tired and frustrated.
Any chance of changing some of the flux or washing system or better yet
both?
Phil Nutting
Manufacturing Engineer
Kaiser Systems, Inc.
-----Original Message-----
From: Alan Kreplick [mailto:[log in to unmask]]
Sent: Monday, July 16, 2001 4:41 PM
To: [log in to unmask]
Subject: [TN] Cleaning No-Clean
Hello Technet,
Looking for recommendations on how to remove the white residue left from a
no-clean (Alpha 205R) rework process (mini-wave rework station) on a bunch
of boards, both in-house and out in the field.
The boards - single-sided pth - were wave soldered using Cobar no-clean
flux. The boards have several aqueous incompatible components on them, so
cleaning the already built boards in an in-line or batch di-water system
with or without a saponifier is not an option (maybe a consideration for
new boards if the aqueous compatible parts are put on after wave).
Thanks in advance for the responses,
Al Kreplick
Sr. Mfg. Eng.
Teraydne, Inc.
500 Riverpark Drive
North Reading, MA 01864
Tel: 978-370-1726
Fax: 734-661-5352
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Date: Thu, 9 Aug 2001 14:15:06 -0400
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Sender: TechNet <[log in to unmask]>
From: Tim Jensen <[log in to unmask]>
Subject: Re: VIAS in pads...
In-Reply-To: <F50E145240DBD311A2FC00D0B72CE8BC011E5273@SALEXSMBX1>
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Gary brings up a very good point regarding various via-in-pad technologies.
The microvia technology has proven to be much more difficult than the vias
that pass completely through the board. My experience is related to
soldering and have worked with various customers using both technologies, I
can provide the following insight on each:
Through hole via-in-pad: The biggest problem that I have run into with this
technology has been related to solder paste volume. Since the solder will
wet down into the via, it is necessary to print a large deposit of paste.
In addition, solder paste is half flux(by volume) and the resultant solder
joint volume will be half of the paste deposit (another reason to print more
paste). I have had a number of situations where people have taped off or
masked the bottom side of the via to keep the paste from flowing out the
bottom side. This typically creates some of the same problems seen with the
microvia technology(see below), so I would avoid sealing the bottom side of
the via. The opening at the bottom of the via provides an addition path for
the volatile components of the solder paste to escape the molten solder.
Microvia-in-pad: Voiding is the primary problem that I have seen here and
typically people are seeing a very large void right in the middle of the
solder joint. In the process, you print solder paste over a small opening.
Air becomes entrapped underneath the solder paste printed and many people
theorize that it is this entrapped air that is causing the void. However,
our work has shown that this is probably not the case. It is more likely
the entrapped volatiles from the solder paste(although I often say that "the
paste is never the problem," in this case it seems that the paste could be
the problem). As the flux is cleaning the surface to promote wetting, it
produces volatiles through this fluxing reaction. The more difficult a
surface is to wet to, the more volatiles that are produced from the flux.
Since the microvia openings are quite small, it is possible that the plating
of the via walls isn't that great. In addition, as the constituents of the
flux go from a liquid to a vapor, their volume can increase up to 100x.
I am no chemist, so I hope that my comments are clear. Again, this is just
what we have seen from a solder paste supplier's perspective. This is a
very interesting topic to me and any additional comments would be great!
As this is my first posting to TechNet, I would like to add one comment to a
particular member of the Ontario, Canada contingent(Since I don't want to
mention names, we will call him Bev). You thought it would never happen,
but the central NY engineer is finally among your ranks!!!
Regards,
Tim Jensen
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Erickson, Gary
Sent: Thursday, August 09, 2001 9:34 AM
To: [log in to unmask]
Subject: Re: [TN] VIAS in pads...
Ken:
Are you talking about Microvia ( single or multi-tier ) or Thru hole "via in
pad" ??
GaryE
-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Wednesday, August 08, 2001 2:53 PM
To: [log in to unmask]
Subject: [TN] VIAS in pads...
Assemblers,
How robust is the VIA in the pad technology now? Can someone share the
process of handling board that has vias in pads?
Most of our boards have VIAS in the pads and there is no way out.
re,
Ken Patel
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Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type><TITLE>RE: [TN] VIAS in pads...</TITLE>
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>Gary=20
brings up a very good point regarding various via-in-pad=20
technologies.</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>The=20
microvia technology has proven to be much more difficult than the vias =
that pass=20
completely through the board. My experience is related to =
soldering and=20
have worked with various customers using both technologies, I can =
provide the=20
following insight on each:</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>Through hole via-in-pad: The biggest problem that I have run =
into with=20
this technology has been related to solder paste volume. Since the =
solder=20
will wet down into the via, it is necessary to print a large deposit of=20
paste. In addition, solder paste is half flux(by volume) and the =
resultant=20
solder joint volume will be half of the paste deposit (another reason to =
print=20
more paste). I have had a number of situations where people have =
taped off=20
or masked the bottom side of the via to keep the paste from flowing out =
the=20
bottom side. This typically creates some of the same problems seen =
with=20
the microvia technology(see below), so I would avoid sealing the bottom =
side of=20
the via. The opening at the bottom of the via provides an addition =
path=20
for the volatile components of the solder paste to escape the molten=20
solder.</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>Microvia-in-pad: Voiding is the primary problem that I have =
seen here and=20
typically people are seeing a very large void right in the middle of the =
solder=20
joint. In the process, you print solder paste over a small =
opening. =20
Air becomes entrapped underneath the solder paste printed and many =
people=20
theorize that it is this entrapped air that is causing the void. =
However,=20
our work has shown that this is probably not the case. It is more =
likely=20
the entrapped volatiles from the solder paste(although I often say that=20
"the paste is never the problem," in this case it seems that =
the paste=20
could be the problem). As the flux is cleaning the surface to =
promote=20
wetting, it produces volatiles through this fluxing reaction. The =
more=20
difficult a surface is to wet to, the more volatiles that are produced =
from the=20
flux. Since the microvia openings are quite small, it is possible =
that the=20
plating of the via walls isn't that great. In addition, as the=20
constituents of the flux go from a liquid to a vapor, their volume can =
increase=20
up to 100x. </FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>I am=20
no chemist, so I hope that my comments are clear. Again, this is =
just what=20
we have seen from a solder paste supplier's perspective. This is a =
very=20
interesting topic to me and any additional comments would be=20
great!</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>As=20
this is my first posting to TechNet, I would like to add one comment to =
a=20
particular member of the Ontario, Canada contingent(Since I don't want =
to=20
mention names, we will call him Bev). You thought it would never =
happen,=20
but the central NY engineer is finally among your =
ranks!!!</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>Regards,</FONT></SPAN></DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D750301214-09082001><FONT color=3D#0000ff face=3DArial =
size=3D2>Tim=20
Jensen</FONT></SPAN></DIV>
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Erickson, =
Gary<BR><B>Sent:</B>=20
Thursday, August 09, 2001 9:34 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] VIAS in =
pads...<BR><BR></FONT></DIV>
<P><FONT size=3D2>Ken: </FONT><BR><FONT size=3D2>Are you =
talking about=20
Microvia ( single or multi-tier ) or Thru hole "via in pad" =
??</FONT>=20
</P>
<P><FONT size=3D2>GaryE</FONT> </P>
<P><FONT size=3D2>-----Original Message-----</FONT> <BR><FONT =
size=3D2>From: Ken=20
Patel [<A =
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>=20
<BR><FONT size=3D2>Sent: Wednesday, August 08, 2001 2:53 PM</FONT> =
<BR><FONT=20
size=3D2>To: [log in to unmask]</FONT> <BR><FONT size=3D2>Subject: [TN] =
VIAS in=20
pads...</FONT> </P><BR>
<P><FONT size=3D2>Assemblers,</FONT> <BR><FONT size=3D2>How robust is =
the VIA in the=20
pad technology now? Can someone share the</FONT> <BR><FONT =
size=3D2>process of=20
handling board that has vias in pads?</FONT> </P>
<P><FONT size=3D2>Most of our boards have VIAS in the pads and there is =
no way=20
out.</FONT> </P>
<P><FONT size=3D2>re,</FONT> <BR><FONT size=3D2>Ken Patel</FONT> </P>
<P><FONT=20
size=3D2>----------------------------------------------------------------=
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Date: Mon, 16 Jul 2001 17:10:50 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Recommendations for developing a mold
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Slots are a great idea, just be sure your slots are not around the cavity
area.
With aluminum one slip prying apart and the mold is damaged.
KW
Advantage Tool & Microweld
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Slots are a great idea, just be sure your slots are not around the cavity
<BR>area.
<BR>With aluminum one slip prying apart and the mold is damaged.
<BR>
<BR>KW
<BR>Advantage Tool & Microweld</FONT></HTML>
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Date: Mon, 16 Jul 2001 16:40:34 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Kreplick <[log in to unmask]>
Subject: Cleaning No-Clean
MIME-Version: 1.0
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Hello Technet,
Looking for recommendations on how to remove the white residue left from a
no-clean (Alpha 205R) rework process (mini-wave rework station) on a bunch
of boards, both in-house and out in the field.
The boards - single-sided pth - were wave soldered using Cobar no-clean
flux. The boards have several aqueous incompatible components on them, so
cleaning the already built boards in an in-line or batch di-water system
with or without a saponifier is not an option (maybe a consideration for
new boards if the aqueous compatible parts are put on after wave).
Thanks in advance for the responses,
Al Kreplick
Sr. Mfg. Eng.
Teraydne, Inc.
500 Riverpark Drive
North Reading, MA 01864
Tel: 978-370-1726
Fax: 734-661-5352
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Date: Thu, 9 Aug 2001 12:31:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Susana Anaya <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Susana Anaya <[log in to unmask]>
Subject: Re: Capacitor 0603 vs 0402...why not networks and arrays?
In-Reply-To: <[log in to unmask]>
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Hi, the lurker comes out of the shadows here to ask all you wise ones
what's up with availablity for lower volumes. I ask because the reps that
have been suggesting them to me and haven't said a word about this (and I
am one of those not looking for thousands monthly)....sanaya.
At 08:45 AM 8/9/01 -0700, Greg Scott wrote:
>Steve,
>
>Our materials and component Engineers encourage us NOT to use chip
>resistor networks
>but we do use alot of capacitor arrays. The reason Is availability unless
>you buy by the thousands monthly.
>
>Greg Scott
>Cray Inc.
>
>"Stephen R. Gregory" wrote:
>>Hi Glenn!
>>
>>I've read the responses you've received to your question (they've all been
>>good), and want to ask another question...
>>
>>I assume the reason to use smaller passive components, is to reduce the real
>>estate needed by these components. My question is; why isn't there more use
>>of chip resistor networks and capacitor arrays?
>>
>>To me, it seems obvious that the use of these components will reduce real
>>estate, but I don't see them being used as often as they could be...maybe
>>I'm
>>not aware of the electrical characteristics or something else, but I wonder
>>why they aren't used more often in designs that are tight for space than
>>what
>>I've seen so far...
>>
>>Can anybody shed some light on this?
>>
>>-Steve Gregory-
>>
>>
>>>Hi all,
>>> I'm brainstorming on risks and benefits of 0603 caps vs 0402 caps.
>>>If the cap value, voltage rating, dielectric material, terminations, and
>>>use conditions are the same, would one be better than the other? My
>>>thoughts are it would be a wash or at least not significant. Here's what I
>>>have so far:
>>>Benefits of 0402 vs 0603:
>>>Smaller size reduces thermal stress/strain on solder joints from CTE or
>>>board flexing.
>>>Smaller size uses less real estate on board
>>>Risks of 0402 vs 0603:
>>>Equipment may have difficulty placing
>>>Thinner dielectric spacing to achieve same capacitance, cap higher failure
>>>rate
>>>Smaller size, cracks easier to develop
>>>Higher risk of tombstoning
>>> What do you all think? I'm sure I missed something, maybe even
>>>wrong on some of the above.
>>>Thanks,
>>>Glenn
>>
>>
--=====================_220019651==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
Hi, the lurker comes out of the shadows here to ask all you wise ones
what's up with availablity for lower volumes. I ask because the reps that
have been suggesting them to me and haven't said a word about this (and I
am one of those not looking for thousands monthly)....sanaya.<br>
<br>
<br>
At 08:45 AM 8/9/01 -0700, Greg Scott wrote:<br>
<blockquote type=cite cite>Steve, <br>
<br>
Our materials and component Engineers encourage us NOT to use
<font face="arial" size=2>chip resistor networks</font> <br>
<font face="arial" size=2>but we do use alot of capacitor arrays.
The reason Is availability unless you buy by the thousands
monthly.</font> <br>
<br>
<font face="arial" size=2>Greg Scott</font> <br>
<font face="arial" size=2>Cray Inc.</font> <br>
<br>
"Stephen R. Gregory" wrote: <br>
<blockquote type=cite cite><font face="arial" size=2>Hi Glenn!</font>
<br>
<br>
<font face="arial" size=2>I've read the responses you've received to your question (they've all been</font> <br>
<font face="arial" size=2>good), and want to ask another question...</font> <br>
<br>
<font face="arial" size=2>I assume the reason to use smaller passive components, is to reduce the real</font> <br>
<font face="arial" size=2>estate needed by these components. My question is; why isn't there more use</font> <br>
<font face="arial" size=2>of chip resistor networks and capacitor arrays?</font> <br>
<br>
<font face="arial" size=2>To me, it seems obvious that the use of these components will reduce real</font> <br>
<font face="arial" size=2>estate, but I don't see them being used as often as they could be...maybe I'm</font> <br>
<font face="arial" size=2>not aware of the electrical characteristics or something else, but I wonder</font> <br>
<font face="arial" size=2>why they aren't used more often in designs that are tight for space than what</font> <br>
<font face="arial" size=2>I've seen so far...</font> <br>
<br>
<font face="arial" size=2>Can anybody shed some light on this?</font> <br>
<br>
<font face="arial" size=2>-Steve Gregory-</font> <br>
<br>
<br>
<blockquote type=cite cite><font face="arial" size=2>Hi all,</font> <br>
<font face="arial" size=2> I'm brainstorming on risks and benefits of 0603 caps vs 0402 caps.</font> <br>
<font face="arial" size=2>If the cap value, voltage rating, dielectric material, terminations, and</font> <br>
<font face="arial" size=2>use conditions are the same, would one be better than the other? My</font> <br>
<font face="arial" size=2>thoughts are it would be a wash or at least not significant. Here's what I</font> <br>
<font face="arial" size=2>have so far:</font> <br>
<font face="arial" size=2><b>Benefits of 0402 vs 0603:</b></font> <br>
<font face="arial" size=2>Smaller size reduces thermal stress/strain on solder joints from CTE or</font> <br>
<font face="arial" size=2>board flexing.</font> <br>
<font face="arial" size=2>Smaller size uses less real estate on board</font> <br>
<font face="arial" size=2><b>Risks of 0402 vs 0603:</b></font> <br>
<font face="arial" size=2>Equipment may have difficulty placing</font> <br>
<font face="arial" size=2>Thinner dielectric spacing to achieve same capacitance, cap higher failure</font> <br>
<font face="arial" size=2>rate</font> <br>
<font face="arial" size=2>Smaller size, cracks easier to develop</font> <br>
<font face="arial" size=2>Higher risk of tombstoning</font> <br>
<font face="arial" size=2> What do you all think? I'm sure I missed something, maybe even</font> <br>
<font face="arial" size=2>wrong on some of the above.</font> <br>
<font face="arial" size=2>Thanks,</font> <br>
<font face="arial" size=2>Glenn</font></blockquote><br>
</blockquote></blockquote></html>
--=====================_220019651==_.ALT--
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Date: Thu, 9 Aug 2001 17:17:16 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Subject: Re: Gold/Paste
In-Reply-To: <71417DD0BB76D311B68300104B8FDEE820E9C6@SUPERVISOR>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Rick,
If it's really gold plating, our experience has been that you will
definitely get a 'grayish' dull finish due to dissolution of the gold into
the solder. The bigger concern should probably be the brittleness of the
joint due to the tin/gold intermetallics that are formed. While immersion
gold may exhibit some of this behavior, the fact that it's an extremely thin
layer should minimize the 'dulling' visual effects you see. If you really
have immersion gold boards it might be wise to check the thickness of the
gold if you're seeing significant dulling.
Regards,
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
Sent: Thursday, August 09, 2001 1:53 PM
To: [log in to unmask]
Subject: [TN] Gold/Paste
We are seeing cloudy/grayish smt solder joints on boards with immersion gold
or soft body gold plating. Is this common???
Thanks,
Rick
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Date: Mon, 16 Jul 2001 18:44:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Header pin (single pin/post)
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi all,
Looking for a single pin header to solder between two boards which are
.400 mils apart and .062" thick. Any suggestion?
re,
Ken patel
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Date: Mon, 16 Jul 2001 15:45:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Ellsworth D. Berkowitz" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Ellsworth D. Berkowitz" <[log in to unmask]>
Subject: Re: ICT Test Points
Factors to consider are the number of test points required by this design,
size of the card, probe types, etc.
We had a design with close to 2000 test points on a 9"X11" card. Our
standard test point is 40 mils; for this product test signed-up for 30 mil
pads due to "lack of space". We had significant contact-related problems;
i.e., probe not hitting the pad, on virtually every ICT cycle. The fixture
was reworked to ensure tooling pin accuracy, in addition, a "funnel plate"
was added for increased probe precision. While much improved,
contact-related false failures were still evident. Our resident statistics
expert calculated that, with 2000 30 mil test points, the probability for a
false contact failure was one out of two ICT cycles, taking into
consideration tolerances on board fab, ICT fixture, etc. With 40 mil pads,
the probability for success is virtually 100% (in this particular case).
New designs since use 40 mil pads; JTAG is used on dense boards to eliminate
test points.
I'm not a test engineer, but learned alot about ICT probing dynamics from
this episode. Your board size, style and quantity of test points will
significantly influence success with 25 mil pads. A small board with few
25 mil test points is likely to succeed when coupled with a quality ICT
fixture.
I like to see the TE's shooting at the biggest target, it keeps the first
pass yields high!
Ellsworth D. Berkowitz, P.E.
NPI/Production Engineering
Paradyne Networks Inc.
"The opinions expressed above are solely those of the writer and do not
necessarily reflect the views of Paradyne Networks Inc."
On Mon, 16 Jul 2001 09:14:27 -0400, Michael Forrester
<[log in to unmask]> wrote:
>Does anyone have any statistics on ICT reliability based on test point
size?
>What I am looking for
>is information on what am I giving up, other than cost, by going from a
.035
>test pad to a .025 test pad.
>Is there a reliability curve based on test point size? Any help would be
>appreciated. Thank you.
>
>Best Regards,
>
>Michael Forrester
>LeCroy Corp.
>
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Date: Mon, 30 Jul 2001 15:35:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mar DeJoya <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mar DeJoya <[log in to unmask]>
Subject: Re: Line width and space
In-Reply-To: <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
Hello,
Try to get a hold of IPC-2221 specs (Generic Standards on Printed Board
Design). Page 38 gives you 3 graphs showing conductor thicknesses, widths
for internal & external layers and their current carrying capacity. Page 39
will show you minimum spacing requirements between conductors at various
voltages.
Hope this helps.
Mar de Joya, C.I.D.
Bustronic Corp.
Fremont, CA 94538
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ruby Hazen
Sent: Monday, July 30, 2001 10:32 AM
To: [log in to unmask]
Subject: [TN] Line width and space
Hello:
Could someone tell me the guidelines and/or standards about trace line width
and space in PCB? Thanks.
R.H.
_________________________________________________________________
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Date: Mon, 16 Jul 2001 21:56:10 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Header pin (single pin/post)
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_a6.16c0f542.2884f53a_boundary"
--part1_a6.16c0f542.2884f53a_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
In a message dated 7/16/2001 8:46:43 PM Central Daylight Time, [log in to unmask]
writes:
> Hi all,
> Looking for a single pin header to solder between two boards which are
> .400 mils apart and .062" thick. Any suggestion?
>
> re,
> Ken patel
>
SMT on one side, PTH on the other? Might have a solution...lemme get back to
work tomorrow....
-Steve Gregory-
--part1_a6.16c0f542.2884f53a_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 7/16/2001 8:46:43 PM Central Daylight Time, [log in to unmask]
<BR>writes:
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi all,
<BR>Looking for a single pin header to solder between two boards which are
<BR>.400 mils apart and .062" thick. Any suggestion?
<BR>
<BR>re,
<BR>Ken patel
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR>SMT on one side, PTH on the other? Might have a solution...lemme get back to
<BR>work tomorrow....
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_a6.16c0f542.2884f53a_boundary--
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Date: Fri, 10 Aug 2001 11:52:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Telgen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Telgen <[log in to unmask]>
Subject: Material specification
MIME-Version: 1.0
Content-Type: text/plain; charset="Windows-1252"
Content-Transfer-Encoding: 7bit
Hi, everyone,
Does anyone know what 7781 E glass is? It's supposed to be a type of
fiberglass material for PCBs.
TIA
Steve Telgen
IGK Industries
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Date: Tue, 17 Jul 2001 15:00:42 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Lead protrusion
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Neda,
We only ever had a batch production unit and leads were hand clinched. All
you need is a pair of flat nosed pliers, sometimes called "duck-billed"
pliers. They have flat faces and a rounded nose and are ideal for most
component leads except those on connectors. We still used them for
connectors, but a bit more force was required to clinch the leads, and we
only half clinched the corner pins just to hold them. They are pretty cheap
and normally a standard electronic workshop tool. Then a small pair of wire
cutters were used to trim the leads to length prior to soldering.
Pete Duncan
Neda Thrash
<nthrash@PEAV To: [log in to unmask]
EY.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: Subject: Re: [TN] Lead protrusion
TechNet
<[log in to unmask]
ORG>
07/16/01
10:05 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Neda Thrash
I beg your pardon for my jumping in the middle here but this is of interest
to me since I am currently looking for the best tool for clinching/cutting.
Any suggestions? I need hand tools for approximately 200 operators.
TIA.
>>> [log in to unmask] 07/15/01 08:20PM >>>
A long time ago, we once had a cutter for cropping leads after wave solder,
but it was peculiarly unreliable in its consistency. The blades would go
blunt very quickly and make a dreadful job of cutting leads cleanly. When
the lead is cut almost through, the weight of the lead and the pressure of
the cutter tended to break rather than cut the final part leaving rather a
rag or a smear. We gave up using the machine eventually and took to hand
cropping, but the shock of the 'snap' as the cutters through each lead
cannot have been very good for the joints.
The kindest way to treat the solder joints is to preform and trim the leads
so that they are soldered only once and require no cropping at all. We
found that many components habitually rode up in the solder wave to the
extent that minimum protrusion wasn't always achieved and rework had to be
performed. The test jig we had then couldn't handle clinched leads, though
that is the best way to go - preform, insert, clinch (half or full), trim,
solder.
Be careful cutting the leads of any components with a glass-to-metal seal -
they really don't like too much shock, so hand-cutting should be avoided.
Pete Duncan
"Pelchat,
Janice" To: [log in to unmask]
<JANICE.PELCHAT@ cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST Aero/ST Group)
BENCH.COM> Subject: Re: [TN] Lead
protrusion
Sent by: TechNet
<[log in to unmask]
>
07/13/01 06:53
PM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to "Pelchat,
Janice"
Where I worked before, the wave solder machine had an inline cutter that
worked with the machine.
Solder, inline cut (Circular saw on its side basically), resolder, out the
other end. No manual cutting allowed.
Jan Pelchat
Benchmark Electronics
> -----Original Message-----
> From: Dorothy M. Lush [SMTP:[log in to unmask]]
> Sent: Thursday, July 12, 2001 7:32 PM
> To: [log in to unmask]
> Subject: Re: [TN] Lead protrusion
>
> Peter,
> Bill is right about the need to avoid trimming leads after solderwave.
The
> thicker the lead and/or cheaper the cutter the more likely there will be
a
> cracked solder joint. IPC class-2 says that this cracked solder joint
does
> not need to be remelted and class-3 says it does. Class-2 recommends
> 60-100
> mils lead length unless otherwise specified by the customer. If you are
> building to Class-2 and you don't want a possible lab or field failure
> because of a cracked solder joint then think and plan ahead to avoid
> having
> to trim. The thinking and planning includes the final assembly the PCA
> will
> be in. For instance, clearance for slot cards to slid in and out.
> Connector
> leads under a front panel even with an insulation strip can cut through
> the
> insulation eventually fail. I had a customer who wanted me to trim 70
mil
> plus diameter pins to 30 mils on the off the shelf power supply instead
of
> ordering the right length leads. They would have to be machined to do
that
> which can lead to other defects.
> Dorothy Lush
>
> > ----------
> > From: Kasprzak, Bill (sys) USX[SMTP:[log in to unmask]]
> > Reply To: TechNet E-Mail Forum.;Kasprzak, Bill (sys) USX
> > Sent: Thursday, July 12, 2001 12:58 PM
> > To: [log in to unmask]
> > Subject: Re: Lead protrusion
> >
> > Peter:
> >
> > Personally, I like .090", but typically I have to hold between .040 and
> > .060. In my mind, I think you would like to install parts with the
> correct
> > lead length prior to wavesoldering. Avoid having to trim after
soldering
> > is
> > always a good idea.
> >
> > Bill Kasprzak
> > Moog Inc., Electronic Assembly Engineering
> >
> >
> > > -----Original Message-----
> > > From: PL [SMTP:[log in to unmask]]
> > > Sent: Thursday, July 12, 2001 2:26 AM
> > > To: [log in to unmask]
> > > Subject: [TN] Lead protrusion
> > >
> > > Hello,
> > >
> > > Does anyone know what is the standard used for prepping
> > > the leads for through-hole boards?
> > >
> > > What are the critical parameters one should consider
> > > when determining the amount of trimming on the leads?
> > >
> > > Rgds,
> > > Peter
> > >
> > >
> > > _________________________________________________________
> > > Do You Yahoo!?
> > > Get your free @yahoo.com address at http://mail.yahoo.com
> > >
> > >
> >
>
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Date: Mon, 30 Jul 2001 14:20:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jana L. Carraway" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jana L. Carraway" <[log in to unmask]>
Subject: Graphics products
In-Reply-To: <2C3A3BE59D91D411AF3B00508BE3FBDC8B1204@EMSS09M10>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Greetings TechNetters,
Would you guys have phone numbers for a few graphic arts products companies
like Bishop Graphics, etc.
Thank you for your help,
Jana Carraway
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Date: Mon, 29 Oct 2001 17:13:58 -0000
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Blasts from the past?!??
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_002E_01C1609D.19740390"
This is a multi-part message in MIME format.
------=_NextPart_000_002E_01C1609D.19740390
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
As in "Good morning, I'm completely operational and all my circuits are
functioning perfectly" ??
[HAL in 2001, just before it topped the crew]
Best regards
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of McGlaughlin, Jeffrey A
Sent: Monday, October 29, 2001 4:53 PM
To: [log in to unmask]
Subject: Re: [TN] Blasts from the past?!??
Yeah, but the system says it is working correctly!?!
Jeffrey
[log in to unmask]
4-7582
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Monday, October 29, 2001 11:37 AM
To: [log in to unmask]
Subject: [TN] Blasts from the past?!??
Did any of you just get some replys to some postings that were from back
in July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
------=_NextPart_000_002E_01C1609D.19740390
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN =
class=3D781410517-29102001>As in=20
"Good morning, I'm completely operational and all my circuits are =
functioning=20
perfectly</SPAN><SPAN class=3D781410517-29102001>" =20
??</SPAN></FONT></FONT></DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN=20
class=3D781410517-29102001></SPAN></FONT></FONT> </DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN =
class=3D781410517-29102001>[HAL in=20
2</SPAN><SPAN class=3D781410517-29102001>001, just before it =
topped the=20
crew]</SPAN></FONT></FONT></DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN=20
class=3D781410517-29102001></SPAN></FONT></FONT> </DIV>
<DIV><FONT color=3D#0000ff><FONT face=3DArial><SPAN=20
class=3D781410517-29102001></SPAN>Best regards</FONT></FONT> </DIV>
<P><FONT color=3D#0000ff face=3DArial>Mike </FONT></P>
<P><FONT face=3DTahoma size=3D2>-----Original =
Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>McGlaughlin, Jeffrey=20
A<BR><B>Sent:</B> Monday, October 29, 2001 4:53 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Blasts from the =
past?!??<BR><BR></P>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px"></FONT>
<DIV><SPAN class=3D265585216-29102001><FONT color=3D#0000ff>Yeah, but =
the system=20
says it is working correctly!?!</FONT></SPAN></DIV>
<DIV> </DIV>
<P><I><FONT color=3D#008080 face=3D"Comic Sans MS" =
size=3D5>Jeffrey</FONT></I>=20
<BR><FONT face=3DArial>[log in to unmask]</FONT> <BR><FONT=20
face=3DArial>4-7582</FONT> </P>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Stephen R. =
Gregory=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, October 29, 2001 =
11:37=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Blasts from =
the=20
past?!??<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>Did any=20
of you just get some replys to some postings that were from back in =
July?=20
<BR><BR>I did...got about 3 or 4 of them.....strange.... =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 10 Aug 2001 17:09:24 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Solder conditions
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I'm seeing this the same way as Kathy Kuhlow. But, if this board has heavy
internal layers and is preheated enough to get good top side solder fillets,
the solder may still be molten when it comes out of the end of the machine.
Are we looking at disturbed joints here?
Guy Ramsey
Senior Lab Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kathy Bergman
Sent: Friday, August 10, 2001 2:00 PM
To: [log in to unmask]
Subject: [TN] Solder conditions
I am looking to get some help in identifying the causes of certain post wave
solder conditions. In particular, a "cracked ice" effect in which the very
surface of the solder looks like a thin layer of it has been cracked in the
way that ice would crack. Another one is lumpy solder, as if the solder had
dirt in it. (I know it doesn't). I am a board manufacturer with just a
minimum of assembly knowledge.
I am unable to post a good picture of the conditions at this time. I
am wondering if there are some on line resources I can tap into, to see some
visual examples of these and other conditions.
Also, what would be a normal wave profile for a board such as this: .093
thick FR4, through hole technology, approx. 6x11, .025 to .195 sized holes,
HASL finish. Please include any prebake information.
I apprectiate in advance any help I can get.
Kathy Bergman
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Date: Tue, 17 Jul 2001 11:16:03 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Cleaning No-Clean
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Al,
In my opinion, prevention is the ONLY cure! I believe that any
palliative removal of your residues will only cause much more harm than
good. If you have components that will not withstand water, there is
every chance they won't like any cleaning solvent, either. Even if you
find a compatible solvent, the best you can hope for, judging from your
description, is to spread your gudge in a thinner layer over a wider
surface area, so that it is less visible. However, no guarantee can be
offered about the reliability of the result. It will probably be better
to leave the boards, as is, warts and all.
It is never a very good idea to use one type of "no-clean" flux on top
of the residues of another: you have no control whatsoever of the
chemistry. At least, try the same flux for both operations.
Brian
Alan Kreplick wrote:
>
> Hello Technet,
>
> Looking for recommendations on how to remove the white residue left from a
> no-clean (Alpha 205R) rework process (mini-wave rework station) on a bunch
> of boards, both in-house and out in the field.
>
> The boards - single-sided pth - were wave soldered using Cobar no-clean
> flux. The boards have several aqueous incompatible components on them, so
> cleaning the already built boards in an in-line or batch di-water system
> with or without a saponifier is not an option (maybe a consideration for
> new boards if the aqueous compatible parts are put on after wave).
>
> Thanks in advance for the responses,
>
> Al Kreplick
> Sr. Mfg. Eng.
> Teraydne, Inc.
> 500 Riverpark Drive
> North Reading, MA 01864
> Tel: 978-370-1726
> Fax: 734-661-5352
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Tue, 17 Jul 2001 14:52:36 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: ICT Test Points
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
It rather depends on which ICT machine you are using. We are going to use
an HP machine whose preferred pad size is 0.050" with 0.075" spacing and a
clearance area around that for access by the test probes. We argued the pad
size down to 0.035" to maximise board real estate, but the main danger of
going any lower than that size is false error readings.
If the pads are too small or too close together, or both, there is a risk
of the probes not contacting properly and returning open or even short
circuit failures where none actually exist. Check with your ICT test
machine manufacturer and/or your test jig vendor and make sure from them
that you understand why the smaller pad sizes could be a problem and what
it would mean to you in terms of false readings.
It may be that you can go to smaller pads, but the downside could be
greatly increased jig costs owing to the greater precision required of the
jig and of the probes. You will also find that tight tolerence probes have
to be replaced more often as they can tolerate less wear before replacement
than a less stringent requirement.
Hope this helps.
Pete Duncan
Michael Forrester
<michael.forrester@L To: [log in to unmask]
ECROY.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: TechNet Subject: [TN] ICT Test Points
<[log in to unmask]>
07/16/01 09:14 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Michael
Forrester
Does anyone have any statistics on ICT reliability based on test point
size?
What I am looking for
is information on what am I giving up, other than cost, by going from a
.035
test pad to a .025 test pad.
Is there a reliability curve based on test point size? Any help would be
appreciated. Thank you.
Best Regards,
Michael Forrester
LeCroy Corp.
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Date: Fri, 10 Aug 2001 22:21:15 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Bryant <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Bryant <[log in to unmask]>
Subject: Assembly Inspection/verification.
MIME-Version: 1.0
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TechNet,
Has anyone tried to use templates or overlays at the end of a machine =
process or the end of a progressive line as a quick check for polarity =
or component orientations? If so what type of materials did you make =
your overlays from? Were they conductive for ESD? Where did you have =
your templates made? Can a board house make these from Gerber data? =
Stencil shop? I would appreciate your comments. Thanks.
J. Bryant
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charset="iso-8859-1"
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<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>TechNet,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Has anyone tried to use templates or =
overlays at=20
the end of a machine process or the end of a progressive line as a =
quick=20
check for polarity or component orientations? If so what type of =
materials did=20
you make your overlays from? Were they conductive for ESD? Where did you =
have=20
your templates made? Can a board house make these from Gerber data? =
Stencil=20
shop? I would appreciate your comments. Thanks.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>J. Bryant</FONT></DIV></BODY></HTML>
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Date: Tue, 17 Jul 2001 18:07:17 +0900
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gilbert Min <[log in to unmask]>
Subject: Vent Hole
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello Every Technetters.
I was informed by our customer which is about vent hole at the BGA
substrates?
What is the vent hole's function?
Why make some vent hole at the BGA substrates?
Please give me more idea.
Thanks
Best regards
SIMMTECH.CO.,Ltd.
Quality & Reliability Assurance Team / Gilbert Min.
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Date: Mon, 29 Oct 2001 11:26:05 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tostevin, Bruce" <[log in to unmask]>
Subject: Re: Looking for Industrial X-ray machine
MIME-Version: 1.0
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Phil,
If you're checking out machines with a joystick or similarly controlled
movable table (X - Y axis), make sure that the motion control features
permit accurate scanning under the highest magnification. Under low mag
conditions, a stage with too much acceleration, jerkiness or too coarse an
increment can still look OK. When the image is highly magnified, those
faults become incredibly frustrating because you do not have precise enough
control over the table to pass smoothly from one point to another along your
specimen. Even though a system may have a "FAST / SLOW" feature, try it
out!
Bruce Tostevin
Benchmark Electronics
Hudson,NH
> ----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Friday, October 26, 2001 10:38 AM
> To: [log in to unmask]
> Subject: [TN] Looking for Industrial X-ray machine
>
> As a follow on topic to the encapsulating voids, we periodically have
> the need for a system to x-ray failed potted assemblies to determine the
> cause of failure. Sometimes this can be accomplished by sawing the unit
> in half, but sometimes we need to look inside without destroying the
> item. We could build a system, but a recent sanity check suggested that
> by buying an industrial unit it would come with all the necessary
> guards, precautions and certifications that a home made unit might not.
>
> Our sample size is usually no larger than a 6 inch cube. Naturally
> tomorrow someone will need to x-ray something larger than a six inch
> cube so a little flexibility would be nice.
>
> I'm interested in knowing what is out there, what is good and bad and
> relative cost.
>
> I can be contacted offline at [log in to unmask] or
> 978-922-9300.
>
> Thanks in advance,
>
> Phil Nutting
>
> --------------------------------------------------------------------------
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Date: Thu, 9 Aug 2001 16:11:25 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Erickson, Gary" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Erickson, Gary" <[log in to unmask]>
Subject: Re: VIAS in pads...
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All:
Just to push this a little further (I'm interested in this
response), does a finish of HASL present less issues with wetting
and outgassing of the solder paste volatiles to the uVias, say
versus a finish of OSP or ENIG ??
If what you say is true, then will the wetting of the uVia walls
during HASL eliminate or reduce the tendency of
entrapment of gases (or air) during BGA assembly ??
Regards,
Gary Erickson
-----Original Message-----
From: Tim Jensen [mailto:[log in to unmask]]
Sent: Thursday, August 09, 2001 2:15 PM
To: [log in to unmask]
Subject: Re: [TN] VIAS in pads...
Gary brings up a very good point regarding various via-in-pad technologies.
The microvia technology has proven to be much more difficult than the vias
that pass completely through the board. My experience is related to
soldering and have worked with various customers using both technologies, I
can provide the following insight on each:
Through hole via-in-pad: The biggest problem that I have run into with this
technology has been related to solder paste volume. Since the solder will
wet down into the via, it is necessary to print a large deposit of paste.
In addition, solder paste is half flux(by volume) and the resultant solder
joint volume will be half of the paste deposit (another reason to print more
paste). I have had a number of situations where people have taped off or
masked the bottom side of the via to keep the paste from flowing out the
bottom side. This typically creates some of the same problems seen with the
microvia technology(see below), so I would avoid sealing the bottom side of
the via. The opening at the bottom of the via provides an addition path for
the volatile components of the solder paste to escape the molten solder.
Microvia-in-pad: Voiding is the primary problem that I have seen here and
typically people are seeing a very large void right in the middle of the
solder joint. In the process, you print solder paste over a small opening.
Air becomes entrapped underneath the solder paste printed and many people
theorize that it is this entrapped air that is causing the void. However,
our work has shown that this is probably not the case. It is more likely
the entrapped volatiles from the solder paste(although I often say that "the
paste is never the problem," in this case it seems that the paste could be
the problem). As the flux is cleaning the surface to promote wetting, it
produces volatiles through this fluxing reaction. The more difficult a
surface is to wet to, the more volatiles that are produced from the flux.
Since the microvia openings are quite small, it is possible that the plating
of the via walls isn't that great. In addition, as the constituents of the
flux go from a liquid to a vapor, their volume can increase up to 100x.
I am no chemist, so I hope that my comments are clear. Again, this is just
what we have seen from a solder paste supplier's perspective. This is a
very interesting topic to me and any additional comments would be great!
As this is my first posting to TechNet, I would like to add one comment to a
particular member of the Ontario, Canada contingent(Since I don't want to
mention names, we will call him Bev). You thought it would never happen,
but the central NY engineer is finally among your ranks!!!
Regards,
Tim Jensen
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Erickson, Gary
Sent: Thursday, August 09, 2001 9:34 AM
To: [log in to unmask]
Subject: Re: [TN] VIAS in pads...
Ken:
Are you talking about Microvia ( single or multi-tier ) or Thru hole "via in
pad" ??
GaryE
-----Original Message-----
From: Ken Patel [ mailto:[log in to unmask] <mailto:[log in to unmask]> ]
Sent: Wednesday, August 08, 2001 2:53 PM
To: [log in to unmask]
Subject: [TN] VIAS in pads...
Assemblers,
How robust is the VIA in the pad technology now? Can someone share the
process of handling board that has vias in pads?
Most of our boards have VIAS in the pads and there is no way out.
re,
Ken Patel
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Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>RE: [TN] VIAS in pads...</TITLE>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
All:</SPAN></FONT></DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001></SPAN></FONT> </DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
Just to push this a little further (I'm interested in this response), does a
finish of HASL present less issues with wetting</SPAN></FONT></DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
and outgassing of the solder paste volatiles to the uVias, say versus a finish
of OSP or ENIG ?? </SPAN></FONT></DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001></SPAN></FONT> </DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
If what you say is true, </SPAN></FONT><FONT color=#008080
face="Calisto MT" size=2><SPAN class=220574919-09082001>then will the wetting of
the uVia walls during HASL eliminate or reduce the tendency of
</SPAN></FONT></DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
entrapment of gases (or air) </SPAN></FONT><FONT color=#008080
face="Calisto MT" size=2><SPAN class=220574919-09082001>during BGA assembly
??</SPAN></FONT></DIV>
<DIV> </DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
Regards,</SPAN></FONT></DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001></SPAN></FONT> </DIV>
<DIV><FONT color=#008080 face="Calisto MT" size=2><SPAN
class=220574919-09082001>
Gary Erickson</SPAN></FONT></DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Tim Jensen
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, August 09, 2001 2:15
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] VIAS in
pads...<BR><BR></DIV></FONT>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial size=2>Gary
brings up a very good point regarding various via-in-pad
technologies.</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial size=2>The
microvia technology has proven to be much more difficult than the vias that
pass completely through the board. My experience is related to soldering
and have worked with various customers using both technologies, I can provide
the following insight on each:</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2>Through hole via-in-pad: The biggest problem that I have run into with
this technology has been related to solder paste volume. Since the
solder will wet down into the via, it is necessary to print a large deposit of
paste. In addition, solder paste is half flux(by volume) and the
resultant solder joint volume will be half of the paste deposit (another
reason to print more paste). I have had a number of situations where
people have taped off or masked the bottom side of the via to keep the paste
from flowing out the bottom side. This typically creates some of the
same problems seen with the microvia technology(see below), so I would avoid
sealing the bottom side of the via. The opening at the bottom of the via
provides an addition path for the volatile components of the solder paste to
escape the molten solder.</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2>Microvia-in-pad: Voiding is the primary problem that I have seen here
and typically people are seeing a very large void right in the middle of the
solder joint. In the process, you print solder paste over a small
opening. Air becomes entrapped underneath the solder paste printed and
many people theorize that it is this entrapped air that is causing the
void. However, our work has shown that this is probably not the
case. It is more likely the entrapped volatiles from the solder
paste(although I often say that "the paste is never the problem," in this case
it seems that the paste could be the problem). As the flux is cleaning
the surface to promote wetting, it produces volatiles through this fluxing
reaction. The more difficult a surface is to wet to, the more volatiles
that are produced from the flux. Since the microvia openings are quite
small, it is possible that the plating of the via walls isn't that
great. In addition, as the constituents of the flux go from a liquid to
a vapor, their volume can increase up to 100x. </FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial size=2>I am
no chemist, so I hope that my comments are clear. Again, this is just
what we have seen from a solder paste supplier's perspective. This is a
very interesting topic to me and any additional comments would be
great!</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial size=2>As
this is my first posting to TechNet, I would like to add one comment to a
particular member of the Ontario, Canada contingent(Since I don't want to
mention names, we will call him Bev). You thought it would never happen,
but the central NY engineer is finally among your ranks!!!</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2>Regards,</FONT></SPAN></DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=750301214-09082001><FONT color=#0000ff face=Arial size=2>Tim
Jensen</FONT></SPAN></DIV>
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> TechNet
[mailto:[log in to unmask]]<B>On Behalf Of</B> Erickson, Gary<BR><B>Sent:</B>
Thursday, August 09, 2001 9:34 AM<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [TN] VIAS in
pads...<BR><BR></FONT></DIV>
<P><FONT size=2>Ken: </FONT><BR><FONT size=2>Are you talking about
Microvia ( single or multi-tier ) or Thru hole "via in pad" ??</FONT> </P>
<P><FONT size=2>GaryE</FONT> </P>
<P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From: Ken
Patel [<A href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Wednesday, August 08, 2001 2:53 PM</FONT> <BR><FONT
size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject: [TN] VIAS in
pads...</FONT> </P><BR>
<P><FONT size=2>Assemblers,</FONT> <BR><FONT size=2>How robust is the VIA in
the pad technology now? Can someone share the</FONT> <BR><FONT size=2>process
of handling board that has vias in pads?</FONT> </P>
<P><FONT size=2>Most of our boards have VIAS in the pads and there is no way
out.</FONT> </P>
<P><FONT size=2>re,</FONT> <BR><FONT size=2>Ken Patel</FONT> </P>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Technet Mail List provided as a free service by IPC using
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Date: Mon, 29 Oct 2001 12:25:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Collins <[log in to unmask]>
Subject: Re: Blasts from the past?!??
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Maybe it's Jack running a "best of TechNet" retrospective... there was =
frost on the car this morning so it's too cold here to contemplate Graham =
Naisbitt's "work naked" bonus, but it was good for a second laugh.
regards
Graham Collins
Process Engineer,=20
Northrop Grumman
Atlantic Facility of Litton Systems Canada
(902) 873-2000 ext 6215
>>> [log in to unmask] 10/29/01 12:36PM >>>
Did any of you just get some replys to some postings that were from back =
in
July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
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Date: Thu, 9 Aug 2001 16:05:24 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: ESD smocks in high temperature and humidity level
MIME-Version: 1.0
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Our policy is that ESD smocks are optional during the summer months. =
Keep
in mind that some companies don't use smocks at all!
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>=20
631-595-5879
-----Original Message-----
From: Bissonnette, Jean-Francois [SMTP:[log in to unmask]]
Sent: Thursday, August 09, 2001 11:29 AM
To: [log in to unmask]
Subject: [TN] ESD smocks in high temperature and humidity
level
Hi techneters
=20
Would it be considered risky to permit shop floor employees to work
without
ESD smocks if the humidity level is around 50%?
=20
Problem is that the temperature is very high (35 dec celcius) and
working with
the smock is a real torture.
=20
I hesitate before giving the my opinion on this. I know that the
higher the humidity=20
the lower the risk of having ESD problems. But is 50% enough???
=20
Jean-Fran=E7ois Bissonnette
Contr=F4le de la Qualit=E9, =C9lectronique
Quality Control, Electronics
Vapor Canada Inc.
10655 Henri-Bourassa O.
St-Laurent, Qc
H4S 1A1
(514) 335-4200 Ext: 2021
=20
WABTEC CORPORATION CONFIDENTIALITY NOTE
The content contained in this e-mail transmission is legally
privileged and confidential information intended only for the use of =
the
individual or entity named herein. If the reader of this transmission =
is not
the intended recipient, you are hereby notified that any dissemination,
distribution, or copying of this transmission is strictly prohibited.
=09
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Date: Sat, 11 Aug 2001 17:14:54 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Colin W.T. McVean" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
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Omissions, ambiguities, or conflicts are resolved with the customer before contract acceptance and performance. 4.4.7 Design Output Design output is documented and expressed in terms that are verified and validated against design input requirements. Design Process Management is responsible for the correct translation of all design requirements into specifications and drawings so the designs may be verified and validated (proven to meet input or intended requirements).
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Date: Tue, 17 Jul 2001 07:47:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
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From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Re: Recommendations for developing a mold
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Thanks go out to Phil N., Mike, Bill, Hans and Phil C for the tips on mold
development. I will certainly incorporate draft angles and slots in the mold
to facilitate extraction of the part. I will also look into a flexible
material for the actual mold itself.
I must say that it is really neat to have over 1200 consultants at your
fingertips willing to help out with any assembly problem. The technet
network is to be commended for its rapid response and expert advice. Thanks
again to all who responded to my post.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
> -----Original Message-----
> From: Crepeau, Phil [SMTP:[log in to unmask]]
> Sent: Monday, July 16, 2001 1:09 PM
> To: [log in to unmask]
> Subject: Re: [TN] Recommendations for developing a mold
>
> hi,
>
> i think the suggestions for adding a draft angle to the walls of the mold
> are what you need. i'd also suggest that stay with an aluminum mold and
> get the inside of the mold teflon coated. your parts will come out
> without any release on them. also you might think about cutting slots at
> the seam of the mold so that you can get something like a screwdriver in
> there to help pry the pieces of the mold apart.
>
> phil
>
>
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Date: Tue, 31 Jul 2001 05:56:36 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
cmcmahon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: cmcmahon <[log in to unmask]>
Subject: Company, Inc.
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Company Client PO# Part Number Rev Release# Description Contact Quantity Tooling Plotting Size/Layers Layers Unit Cost Testing Turnaround Special Features Shipping Method Total Cost Delivery Date Notes: Boards Tested? Yes / No Reorder? Yes / No Rev? Old / New / / / / / / FedX UPS Ground Other .
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Date: Mon, 29 Oct 2001 12:51:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Telgen <[log in to unmask]>
Subject: Re: Blasts from the past?!??
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0017_01C16078.7702D1A0"
This is a multi-part message in MIME format.
------=_NextPart_000_0017_01C16078.7702D1A0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I got them too. (Of course, now I'm generating this, which I'll get back
next February). :-{)
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Monday, October 29, 2001 11:37
To: [log in to unmask]
Subject: [TN] Blasts from the past?!??
Did any of you just get some replys to some postings that were from back
in July?
I did...got about 3 or 4 of them.....strange....
-Steve Gregory-
------=_NextPart_000_0017_01C16078.7702D1A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D230215017-29102001>I got=20
them too. (Of course, now I'm generating this, which I'll get back =
next=20
February). :-{)</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Stephen R. =
Gregory<BR><B>Sent:</B>=20
Monday, October 29, 2001 11:37<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Blasts from the=20
past?!??<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>Did any=20
of you just get some replys to some postings that were from back in =
July?=20
<BR><BR>I did...got about 3 or 4 of them.....strange.... =
<BR><BR>-Steve=20
Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 9 Aug 2001 16:18:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Roger M. Stoops" <[log in to unmask]>
Subject: Re: Capacitor 0603 vs 0402...why not networks and arrays?
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
It seems only a few values are readily available in networks and arrays;
you have to do your homework in advance and make sure stock is available
someplace. Stock for these parts is hard to come by in domestic U.S
market.
We are using networks and arrays on medium/high volume products, and where
we use many of a few values on low volume products.
Ex: One product, estimated yearly build of 500, uses 38 cap arrays and 57
resistor ntwks, and we try to use these same values on other products. We
use un-imaginative values, too, in order to get parts (such as 1K, 10K,
100K, 0.1uF, 0.001uF) and find as many good vendors as possible.
Stock is getting better as time goes by.
My 2 cents worth.
Roger M. Stoops, C.I.D., PCB Designer
Trimble
Engineering and Construction Division
Susana Anaya
<sanaya@QUALC To: [log in to unmask]
OMM.COM> cc:
Sent by: Subject: Re: [TN] Capacitor 0603 vs 0402...why not networks and
TechNet arrays?
<[log in to unmask]
ORG>
08/09/01
03:31 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Susana Anaya
Hi, the lurker comes out of the shadows here to ask all you wise ones
what's up with availablity for lower volumes. I ask because the reps that
have been suggesting them to me and haven't said a word about this (and I
am one of those not looking for thousands monthly)....sanaya.
At 08:45 AM 8/9/01 -0700, Greg Scott wrote:
Steve,
Our materials and component Engineers encourage us NOT to use chip
resistor networks
but we do use alot of capacitor arrays. The reason Is availability
unless you buy by the thousands monthly.
Greg Scott
Cray Inc.
"Stephen R. Gregory" wrote:
Hi Glenn!
I've read the responses you've received to your question (they've
all been
good), and want to ask another question...
I assume the reason to use smaller passive components, is to
reduce the real
estate needed by these components. My question is; why isn't
there more use
of chip resistor networks and capacitor arrays?
To me, it seems obvious that the use of these components will
reduce real
estate, but I don't see them being used as often as they could
be...maybe I'm
not aware of the electrical characteristics or something else,
but I wonder
why they aren't used more often in designs that are tight for
space than what
I've seen so far...
Can anybody shed some light on this?
-Steve Gregory-
Hi all,
I'm brainstorming on risks and benefits of 0603 caps
vs 0402 caps.
If the cap value, voltage rating, dielectric material,
terminations, and
use conditions are the same, would one be better than the
other? My
thoughts are it would be a wash or at least not significant.
Here's what I
have so far:
Benefits of 0402 vs 0603:
Smaller size reduces thermal stress/strain on solder joints
from CTE or
board flexing.
Smaller size uses less real estate on board
Risks of 0402 vs 0603:
Equipment may have difficulty placing
Thinner dielectric spacing to achieve same capacitance, cap
higher failure
rate
Smaller size, cracks easier to develop
Higher risk of tombstoning
What do you all think? I'm sure I missed something,
maybe even
wrong on some of the above.
Thanks,
Glenn
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Date: Tue, 31 Jul 2001 07:44:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
cmcmahon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: cmcmahon <[log in to unmask]>
Subject: !"#$
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Date: Mon, 29 Oct 2001 12:59:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Re: Blasts from the past?!??
MIME-Version: 1.0
Content-Type: text/plain
This is wierd. I just received notification that a post that I wrote in July
was sucessfully distributed. I did not resend this post. I'll assume that
the system has gone nuts. Somebody will figure it out.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
> -----Original Message-----
> From: McGlaughlin, Jeffrey A [SMTP:[log in to unmask]]
> Sent: Monday, October 29, 2001 11:53 AM
> To: [log in to unmask]
> Subject: Re: [TN] Blasts from the past?!??
>
> Yeah, but the system says it is working correctly!?!
>
>
> Jeffrey
> [log in to unmask]
> 4-7582
>
> -----Original Message-----
> From: Stephen R. Gregory [mailto:[log in to unmask]]
> Sent: Monday, October 29, 2001 11:37 AM
> To: [log in to unmask]
> Subject: [TN] Blasts from the past?!??
>
>
> Did any of you just get some replys to some postings that were from
> back in July?
>
> I did...got about 3 or 4 of them.....strange....
>
> -Steve Gregory-
>
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Date: Mon, 30 Jul 2001 08:50:14 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Clearance area around holes
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Daan,
The sizes you quote are not especially small, nor is the difference between
them. I'm not totally clear from your description what you are meaning,
but, (converting to my old-fashioned language), do you have 12 mil diameter
holes going through 24 mils diameter exclusion zones in the copper planes?
Unless your Fab House's registration accuracy is very bad, you will have a
nominal 6 mils all-round clearance and in practice, shouldn't have less
than 3 to 4 mils clearance. Is this OK electrically if your small
clearances are, for example, at layers with high power? It should not be a
difficult job for a decent Fab House to make this board for you, though.
Pete Duncan
"d. terstegge"
<[log in to unmask] To: [log in to unmask]
GROUP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: TechNet Subject: [TN] Clearance area around holes
<[log in to unmask]>
07/27/01 04:37 PM
Please respond to
"TechNet E-Mail Forum.";
Please respond to "d.
terstegge"
Hi Technet,
Here's a question for the bare board experts out there:
One of our pcb-suppliers had rejects on a complete batch of our boards
because the clearance between the via's and the surrounding copperplane was
so small that it resulted in short circuits.
The holes were designed 0.3 mm (finished hole size) and the openings in the
copperplane were 0.6 mm, leaving only a small clearance area. The board
measures about 20*15 cm.
What do you think, is a board like this manufacturable for a decent board
shop, or is it really that difficult? Could you give me a typical value
for the minimum clearance around the finished-hole that board vendors need
?
Best regards,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Tue, 31 Jul 2001 11:10:34 -0400
Reply-To: Mark Charlton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Charlton <[log in to unmask]>
Organization: MSI of Central Florida, Inc.
Subject: Vibratory base feeders
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_001A_01C119B1.6B37A840"
This is a multi-part message in MIME format.
------=_NextPart_000_001A_01C119B1.6B37A840
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Fellow Technetters,
=20
I am looking for suggestions how to present "stick" parts to my pick =
and
place machines. These vibratory-base feeders have been troublesome for
years and was wondering what other solutions are available. I know I'm
not the only user struggling with this technology so any assistance or
alternatives will be welcome.
=20
Mark
=20
------=_NextPart_000_001A_01C119B1.6B37A840
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"MSHTML 5.50.4207.2601" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Fellow Technetters,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I am looking =
for suggestions how=20
to present "stick" parts to my pick and place machines. =
These=20
vibratory-base feeders have been troublesome for years and was =
wondering what=20
other solutions are available. I know I'm not the only user=20
struggling with this technology so any assistance or alternatives will =
be=20
welcome.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Mark</FONT></DIV>
<DIV> </DIV></BODY></HTML>
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Date: Mon, 30 Jul 2001 10:31:58 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Rejected posting to [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Steve,
Yeah, I got one of these ListServer messages the other day and didn't
understand it either. I corrected a typo and resent it, and it was accepted
OK. Hasn't happened again since, so maybe just a visiting gremlin in the
works.
What a fantastic iceberg picture! I'm using it as my PC wallpaper -
symbolic of how much we don't know compared with how much we do, and it's
only the clear days that show this.
Pete Duncan
"Stephen R.
Gregory" To: [log in to unmask]
<SteveZeva@AO cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
L.COM> Subject: [TN] Rejected posting to [log in to unmask]
Sent by:
TechNet
<[log in to unmask]
ORG>
07/28/01
12:12 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
I just got this email from the Listserver:
Your message is being returned to you unprocessed because it appears to
have
already been distributed to the TechNet list. That is, a message with
identical
text (but possibly with different mail headers) has been posted to the
list
recently, either by you or by someone else.
Has anyone else gotten this? What's really weird, is that the message was
referring to a reply I made 4-days ago to the list...strange.
Anyways, it's Friday...YAY! I gotta neat picture up on my web page that is
pretty cool...literally. It's of an iceberg. You'll see why the Titanic
sank!
You'll also be able really understand the saying; "It's just the tip of the
iceburg".
The photo came from a Rig Manager for Global Marine Drilling in St. Johns,
Newfoundland. They actually have to divert the path of these things away
from
the rig by towing them with ships.
In this particular case the water was calm & the sun was almost directly
overhead so that the diver was able to get into the water and click this
pic.
Clear water huh? They estimated the weight of this behemoth at over
300,000,000 tons!
http://stevezeva.homestead.com/index.html
-Steve Gregory-
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Date: Tue, 31 Jul 2001 21:14:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Graphics products
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Bishop Graphics Westlake Village, CA is no longer in business. They
sold-out to ChartPak 800-628-1910
----- Original Message -----
From: "Jana L. Carraway" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, July 30, 2001 2:20 PM
Subject: [TN] Graphics products
> Greetings TechNetters,
>
> Would you guys have phone numbers for a few graphic arts products
companies
> like Bishop Graphics, etc.
> Thank you for your help,
> Jana Carraway
>
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Date: Mon, 29 Oct 2001 13:13:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Company, Inc.
X-To: cmcmahon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Serious delay in the y2k bug.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of cmcmahon
> Sent: Tuesday, July 31, 2001 8:57 AM
> To: [log in to unmask]
> Subject: [TN] Company, Inc.
>
>
> Company Client
> PO# Part Number Rev
> Release# Description
> Contact Quantity
> Tooling Plotting Size/Layers
> Layers Unit Cost Testing
> Turnaround Special Features
> Shipping Method Total Cost
> Delivery Date Notes: Boards Tested?
> Yes / No Reorder? Yes / No
> Rev?
> Old / New / / / / /
> / FedX UPS Ground Other .
>
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Date: Mon, 29 Oct 2001 13:17:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Assembly Inspection/verification.
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Jack,
=20
We are running in the dark ages and have created inspection overlays by
hand using either Nomex or Acetate film.
=20
Phil Nutting
-----Original Message-----
From: Jack Bryant [mailto:[log in to unmask]]
Sent: Friday, August 10, 2001 10:21 PM
To: [log in to unmask]
Subject: [TN] Assembly Inspection/verification.
TechNet,
=20
Has anyone tried to use templates or overlays at the end of a machine
process or the end of a progressive line as a quick check for polarity
or component orientations? If so what type of materials did you make
your overlays from? Were they conductive for ESD? Where did you have
your templates made? Can a board house make these from Gerber data?
Stencil shop? I would appreciate your comments. Thanks.
=20
J. Bryant
------_=_NextPart_001_01C160A5.F7CB4A10
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D317151618-29102001><FONT face=3DArial color=3D#0000ff =
size=3D2>Jack,</FONT></SPAN></DIV>
<DIV><SPAN class=3D317151618-29102001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D317151618-29102001><FONT face=3DArial color=3D#0000ff =
size=3D2>We are=20
running in the dark ages and have created inspection overlays by hand =
using=20
either Nomex or Acetate film.</FONT></SPAN></DIV>
<DIV><SPAN class=3D317151618-29102001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D317151618-29102001><FONT face=3DArial color=3D#0000ff =
size=3D2>Phil=20
Nutting</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Jack Bryant=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, August 10, 2001 =
10:21=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Assembly=20
Inspection/verification.<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>TechNet,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Has anyone tried to use templates or =
overlays at=20
the end of a machine process or the end of a progressive line as =
a quick=20
check for polarity or component orientations? If so what type of =
materials did=20
you make your overlays from? Were they conductive for ESD? Where did =
you have=20
your templates made? Can a board house make these from Gerber data? =
Stencil=20
shop? I would appreciate your comments. Thanks.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>J. =
Bryant</FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 9 Aug 2001 13:55:26 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Re: VIAS in pads...
MIME-Version: 1.0
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Through hole vias. I am looking for problem resolution at assembly level
and not fab level.
re,
Ken Patel
"Erickson, Gary" wrote:
> Part 1.1Type: Plain Text (text/plain)
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Date: Thu, 9 Aug 2001 14:53:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Howieson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: Gold/Paste
MIME-Version: 1.0
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We are seeing cloudy/grayish smt solder joints on boards with immersion gold
or soft body gold plating. Is this common???
Thanks,
Rick
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Date: Thu, 9 Aug 2001 16:12:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mason Hu <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mason Hu <[log in to unmask]>
Subject: Re: Microvia in BGA pad
Have you looked into IPC-6016?
Mason
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Date: Tue, 17 Jul 2001 14:15:10 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Geoff Layhe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Geoff Layhe <[log in to unmask]>
Subject: Re: Impedance Discrepency
MIME-Version: 1.0
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Paul,
I don't think 5 plies of 7628 in 0.35" is the reason for the difference. 5 x
7628 calculates to a dielectric constant of 4.84. I just ran a quick manual
calculation using Er 4.84 and got the almost the same results as your Polar
(65.2 ohms.
Assuming track width and dielectric spacings are OK the only way to get an
impedance of 72 is by using an Er of 3.9. You aren't using BT Epoxy are you.
Is the 72 Ohms measured on a test coupon or on a track in the board. Could
there be an something in the circuit affecting the results?
Geoff Layhe
www.Lamar-uk.co.uk
-----Original Message-----
From: tech [mailto:[log in to unmask]]
Sent: 17 July 2001 13:33
To: [log in to unmask]
Subject: [TN] Impedance Discrepency
I have a 6 layer design with layers 2 and 5 being planes and 3 and 4
signals. In this particular case , due to overall thickness and outer
layer impedance requirements we have .010 from the planes to the signals
and .035 between the signals. 1 Oz. copper and finished lines at .006.
My impedance software ( Polar CITS25) is giving a number of 65.02 ohms
but the actual results we're getting are all at the 72+ ohm range.We do
many impedance designs and have not seen a discrepency like this. The
.035 dielectric between the signals is 5 pieces of 7628 which is an
unusually high amount of prepreg for us and the .010 from planes to
signals are cores. All 140Tg FR4. Can the high thickness (resin content)
of prepreg be creating the problem ? Sections on the coupons are very
close to design so we don't appear to have a process issue.
Any input appreciated.
Paul Greene
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Date: Mon, 30 Jul 2001 07:42:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mary Jane Chism <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mary Jane Chism <[log in to unmask]>
Subject: Re: ESD mat material...
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Steve,
Here is the company name, location, phone number, and contact of where we
order our matting. Hope this helps.
Bennett & Bennett
Contact: John Denny
Phone number: 937-879-3144
Springfield, OH
Mary Jane Chism/Technical Trainer
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Friday, July 27, 2001 1:10 PM
To: [log in to unmask]
Subject: [TN] ESD mat material...
Hi everyone!
Does anybody know a vendor that sells ESD mat material by the roll? I used
to
have
one, but I've misplaced the business card I had, and I can't remember who it
was (senility creeping in...hehehe).
Oh by the way, I just found out that iceburg picture is a fake...go to:
http://www.snopes2.com/spoons/photos/iceberg.htm
Sure looked cool though...I need something cool here. It's been over
100-degrees here for more than a week...
-Steve Gregory-
------_=_NextPart_001_01C118F5.0ADD3D50
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<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001>Steve,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=200183912-30072001>Here
is the company name, location, phone number, and contact of where we order our
matting. Hope this helps.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001>Bennett & Bennett</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001>Contact: John Denny</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=200183912-30072001>Phone
number: 937-879-3144</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001>Springfield, OH</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=200183912-30072001></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=200183912-30072001>Mary
Jane Chism/Technical Trainer</SPAN></FONT></DIV>
<DIV> </DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, July 27, 2001 1:10
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] ESD mat
material...<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT size=2>Hi
everyone! <BR><BR>Does anybody know a vendor that sells ESD mat material by
the roll? I used to <BR>have <BR>one, but I've misplaced the business card I
had, and I can't remember who it <BR>was (senility creeping in...hehehe).
<BR><BR>Oh by the way, I just found out that iceburg picture is a fake...go
to: <BR><BR>http://www.snopes2.com/spoons/photos/iceberg.htm <BR><BR>Sure
looked cool though...I need something cool here. It's been over
<BR>100-degrees here for more than a week... <BR><BR>-Steve Gregory-</FONT>
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Tue, 17 Jul 2001 10:22:24 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McGlaughlin, Jeffrey A" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject: Re: Impedance Discrepency
MIME-version: 1.0
Content-type: text/plain; charset="iso-8859-1"
The problem may be the assumed dielectric constant of the FR4 prepreg
material. FR4 has a dielectric constant that changes with respect to
frequency, making it necessary to find the effective Er for impedance
calculations, not the base Er. These calculations appear in several of
Richard Hartley's presentations on high speed design. These presentations
should be in the proceedings for either PCB Design conference from last year
if you have them (if not let me know and I will try to find my copy). I have
found that based on these calculations the Er of FR4 *can* vary from around
4.2-5.0 when using "garden variety" material. When doing boards where the
controlled impedance is critical I have found it to be a good idea to
include not only a stack-up but a list of assumed values and the calculator
used. This allows fabricator to make the necessary adjustments to my data to
meet the critical values, based on their processes.
Good Luck,
Jeffrey A. McGlaughlin, C.I.D.
Sr. PCB Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]
-----Original Message-----
From: tech [mailto:[log in to unmask]]
Sent: Tuesday, July 17, 2001 8:33 AM
To: [log in to unmask]
Subject: [TN] Impedance Discrepency
I have a 6 layer design with layers 2 and 5 being planes and 3 and 4
signals. In this particular case , due to overall thickness and outer
layer impedance requirements we have .010 from the planes to the signals
and .035 between the signals. 1 Oz. copper and finished lines at .006.
My impedance software ( Polar CITS25) is giving a number of 65.02 ohms
but the actual results we're getting are all at the 72+ ohm range.We do
many impedance designs and have not seen a discrepency like this. The
.035 dielectric between the signals is 5 pieces of 7628 which is an
unusually high amount of prepreg for us and the .010 from planes to
signals are cores. All 140Tg FR4. Can the high thickness (resin content)
of prepreg be creating the problem ? Sections on the coupons are very
close to design so we don't appear to have a process issue.
Any input appreciated.
Paul Greene
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Date: Tue, 17 Jul 2001 11:55:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Anderson, Greg (IndSys, GEFanuc, NA)" <[log in to unmask]>
Subject: Re: Weave Exposure...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
I've seen images like this long ago. . . caused then by rework of solder
mask. Most things that strip solder mask also do a number on the "butter
coat". Shows up first at the thinner "knuckle" of the glass weave.
Greg Anderson
Senior Advanced Manufacturing Engineer
GE Fanuc Automation
Charlottesville, VA 22911
Phone: 804-978-5181
FAX: 804-978-5898
e-mail: [log in to unmask]
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, July 17, 2001 9:56 AM
To: [log in to unmask]
Subject: [TN] Weave Exposure...
Hi Everyone!
I've got some boards in here that has what I believe to be weave exposure,
and I think it's bad enough to reject the boards. Go to:
http://stevezeva.homestead.com/index.html
and tell me what you think. What causes something like that?
-Steve Gregory-
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Date: Tue, 17 Jul 2001 08:59:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chuck Brummer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: Weave Exposure...
MIME-Version: 1.0
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Steve,
Wow, great shot of the glass fibers. What did you do with the resin?
The resin must have been there before but not very much maybe. Looks
like fairly heavy glass too, which usually has a lower resin content,
here you have the glass exposed over the knuckles. Might have removed
the epoxy mechanically or chemically.
Chuck Brummer
"Stephen R. Gregory" wrote:
> Hi Everyone!
>
> I've got some boards in here that has what I believe to be weave
> exposure,
> and I think it's bad enough to reject the boards. Go to:
>
> http://stevezeva.homestead.com/index.html
>
> and tell me what you think. What causes something like that?
>
> -Steve Gregory-
--------------70333D477D0298624D186420
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Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Steve,
<br>Wow, great shot of the glass fibers. What did you do with the
resin? The resin must have been there before but not very much maybe.
Looks like fairly heavy glass too, which usually has a lower resin content,
here you have the glass exposed over the knuckles. Might have removed
the epoxy mechanically or chemically.
<br>Chuck Brummer
<p>"Stephen R. Gregory" wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>Hi Everyone!</font></font>
<p><font face="arial,helvetica"><font size=-1>I've got some boards in here
that has what I believe to be weave exposure,</font></font>
<br><font face="arial,helvetica"><font size=-1>and I think it's bad enough
to reject the boards. Go to:</font></font>
<p><font face="arial,helvetica"><font size=-1><A HREF="http://stevezeva.homestead.com/index.html">http://stevezeva.homestead.com/index.html</A></font></font>
<p><font face="arial,helvetica"><font size=-1>and tell me what you think.
What causes something like that?</font></font>
<p><font face="arial,helvetica"><font size=-1>-Steve Gregory-</font></font></blockquote>
</html>
--------------70333D477D0298624D186420--
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Date: Tue, 17 Jul 2001 12:08:32 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Francey <[log in to unmask]>
Subject: Re: Weave Exposure...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_1e.18a3273b.2885bd00_boundary"
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"excessive brushing before solder mask application" and or rework? I'd ask
the question.
What's the base material? (looks like bt-epoxy or polyimide - or cooked
epoxy!)............Jim
In a message dated 17/07/2001 4:26:10 PM GMT Daylight Time,
[log in to unmask] writes:
> Very impressive picture indeed.As Susan suggests,we will use your picture
> for training.
> My first guess will be excessive brushing before solder mask application
> Edward
>
>
--part1_1e.18a3273b.2885bd00_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>"excessive brushing before solder mask application" and or <U>rework</U>? I'd ask
<BR>the question.
<BR>
<BR>What's the base material? (looks like bt-epoxy or polyimide - or cooked
<BR>epoxy!)............Jim
<BR>
<BR>In a message dated 17/07/2001 4:26:10 PM GMT Daylight Time,
<BR>[log in to unmask] writes:
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Very impressive picture indeed.As Susan suggests,we will use your picture
<BR>for training.
<BR>My first guess will be excessive brushing before solder mask application
<BR>Edward
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Mon, 30 Jul 2001 13:49:36 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Cathy Killen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Just a few Questions
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hope someone can help.
Why is an 'iconic' wash required and is it required in a no-clean process?
Can a no-clean process achieve the desired standards, if not what is the
best way to achieve the standards?
Cathy Killen
Training Instructor
[log in to unmask] <mailto:[log in to unmask]>
An Oasis of Training Excellence
* 028 38314305
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Date: Mon, 30 Jul 2001 09:32:21 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Flex delamination?
MIME-Version: 1.0
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Hi Everyone!
Still hot as Hades, here...looks like we're looking at +100-degree days all
this week!
They did an interesting thing on one of the local news station here to
illustrate how hot it gets inside a car, and why it's really crazy to leave
kids or pets inside cars when it gets this hot...they actually baked cookies
inside a car!!! Enough of that...
Daan's asked me to post a picture for him up on our web site. Go to:
http://stevezeva.homestead.com/index.html
I've got a picture of a flex-rigid board with a greenish spot on the
copperplane, under the coverlayer. I would like to know what this is, and if
it we should reject it or not.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
--part1_d2.a0aee16.2896bbe5_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Everyone!
<BR>
<BR>Still hot as Hades, here...looks like we're looking at +100-degree days all
<BR>this week!
<BR>They did an interesting thing on one of the local news station here to
<BR>illustrate how hot it gets inside a car, and why it's really crazy to leave
<BR>kids or pets inside cars when it gets this hot...they actually baked cookies
<BR>inside a car!!! Enough of that...
<BR>
<BR>Daan's asked me to post a picture for him up on our web site. Go to:
<BR>
<BR>http://stevezeva.homestead.com/index.html
<BR>
<BR>I've got a picture of a flex-rigid board with a greenish spot on the
<BR>copperplane, under the coverlayer. I would like to know what this is, and if
<BR>it we should reject it or not.
<BR>
<BR>Daan Terstegge
<BR>SMT Centre
<BR>Thales Communications
<BR>Unclassified mail
<BR>Personal Website: http://www.smtinfo.net
<BR></FONT></HTML>
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Date: Mon, 30 Jul 2001 15:47:00 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Flex delamination?
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Thanks Steve,
Here's some extra info about the picture:
Before my destructive experiments with removing the coverlayer (always a =
pleasure! ) this discoloration showed through as dark spots, some about 1 =
cm diameter. The material still looked flat, unlike most delaminations =
that I've seen, and that's why I'm not sure if this really is a delaminatio=
n. After cutting the flex with scissors I found out that at these spots =
there is very bad adhesion between copperplane and coverlayer.=20
Although the copper has a greenish color, it looks smooth and shiny. This =
was already somewhat visible before assembly, but it became worse during =
reflow soldering.
Daan
>>> <[log in to unmask]> 07/30 3:32 pm >>>
Hi Everyone!
Still hot as Hades, here...looks like we're looking at +100-degree days =
all=20
this week!
They did an interesting thing on one of the local news station here to=20
illustrate how hot it gets inside a car, and why it's really crazy to =
leave=20
kids or pets inside cars when it gets this hot...they actually baked =
cookies=20
inside a car!!! Enough of that...
Daan's asked me to post a picture for him up on our web site. Go to:
http://stevezeva.homestead.com/index.html=20
I've got a picture of a flex-rigid board with a greenish spot on the=20
copperplane, under the coverlayer. I would like to know what this is, and =
if=20
it we should reject it or not.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net=20
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Date: Thu, 9 Aug 2001 15:59:05 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Gold/Paste
MIME-Version: 1.0
Content-Type: text/plain
Also is this a double-sided board and are the solder joints in question on
the first pass side only or both sides (if a double-sided board)? The first
pass side can look great after 1st reflow but if it goes through a slow cool
on the 2nd reflow can get some extraordinary crystal growth depending on the
solder paste and it looks dull. What solder paste are you using and is the
questionable solder appearance random or at certain components?
Dorothy Lush
Manufacturing Engineer
> ----------
> From: Andrew Hoggan[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Andrew Hoggan
> Sent: Thursday, August 09, 2001 3:21 PM
> To: [log in to unmask]
> Subject: Re: Gold/Paste
>
> Hi Rick,
>
> could be;
>
> a) oxide on the joint
>
> b) change in the composition of the original solder through elemental
> contamination from your plating (pad/component) during reflow giving
> differential freezing, resulting in a change in the surface appearance
>
> c) the solder you've been supplied with is 'out of spec' (do you have a
> spec?) and is freezing differentially
>
> d) all of the above
>
> e) none of the above
>
> Best regards,
>
> Andrew Hoggan
> BBA Associates Ltd
> www.bba-associates.com
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Howieson
> Sent: 09 August 2001 21:53
> To: [log in to unmask]
> Subject: [TN] Gold/Paste
>
>
> We are seeing cloudy/grayish smt solder joints on boards with immersion
> gold
> or soft body gold plating. Is this common???
> Thanks,
> Rick
>
> --------------------------------------------------------------------------
> --
> -----
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> --------------------------------------------------------------------------
> --
> -----
>
> --------------------------------------------------------------------------
> -------
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Date: Thu, 9 Aug 2001 16:27:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Re: VIAS in pads...
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Greg,
Can you clarify the following...
(1) What do you mean by 170 mils area - Are you referring as a length or area? I think you are
saying square mils here.
(2) Do you mean via towards the heel and not toe on chip parts?
(3) No solder mask on via pad on other side, the non-SMT pad side.
re,
Ken Patel
Greg Scott wrote:
> We have had great success with vias in pads, by establishing some rules.
> NO vias in following component's pads.
> 0603 and smaller, components of any style where the pad has an area of less than 170
> mils.
> No gull wing pin style ICs.
> Also we tend to place via on chip parts off center of pad towards center of part.
> Also we capture the bottom side (none solder side) of via with solder mask, solder mask
> opening should be only large enough to clear drill (with some tolerance)
>
> hope this helps.
> Greg Scott
> Cray Inc.
>
> "Sklenar Vit (RBAU-BK/MGE4)" wrote:
>
> > We had this design and did not like it despite of fact it saved a lot of PBB
> > space. Problem was , especially for small chip packages ( 0603) that volume
> > of vias barrel is comparable to volume of solder joint and this vias was
> > "steeling" solder from solder joint accidentally ( during wave soldering).
> > Result - insufficient or even missing solder joint.
> >
> > We do not have this layout design anymore ..
> >
> > Regards
> >
> > Vit Sklenar MGE4VS
> > T: (61 3)9541 7734 F: (61 3) 9541 3909
> > e-mail work: [log in to unmask]
> > e-mail home: [log in to unmask]
> > > Robert Bosch (Aust) ,
> > 1555 cnr.Centre and McNaugton Road,
> > > Clayton , VIC 3169, Australia
> > >
> > >
> > > -----Original Message-----
> > > From: Ken Patel [SMTP:[log in to unmask]]
> > > Sent: Thursday, August 09, 2001 4:53 AM
> > > To: [log in to unmask]
> > > Subject: [TN] VIAS in pads...
> > >
> > > Assemblers,
> > > How robust is the VIA in the pad technology now? Can someone share the
> > > process of handling board that has vias in pads?
> > >
> > > Most of our boards have VIAS in the pads and there is no way out.
> > >
> > > re,
> > > Ken Patel
> > >
> > > --------------------------------------------------------------------------
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Date: Thu, 9 Aug 2001 22:02:21 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: [LF] Eutectic alloys?????
MIME-Version: 1.0
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Hi Lee,
In a message dated 08/09/2001 14:53:17, [log in to unmask] writes:
>Werner Engelmaier,
>I'm not familiar with the work of Roger Wild concerning SnPb Solders.
>What did he do? Are there any technical publications available?
>I'm curious. Any help you can provide would be greatly appreciated.
>Thanks
>Lee Whiteman
Roger Wild's now classical work characterized the temperature- and
time-dependency of the creep-fatigue of Sn/Pb solders. The characterization
was enough to allow the development of the Engelmaier-Wild solder
creep-fatigue model that is widely used in the industry, which enables one
to relate the results of proper accelerated testing (as per IPC-SM-785) to
product reliability (IPC-D-279).
You can his work at: R. N. Wild, "1974 IRAD Study - Fatigue Properties of
Solder Joints," IBM Report No. M45-74-002, Contract No. IBM 4A69, 5 January
1975, among others.
Werner Engelmaier
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Date: Mon, 30 Jul 2001 09:23:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Pelchat, Janice" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Pelchat, Janice" <[log in to unmask]>
Subject: Re:
MIME-Version: 1.0
Content-Type: text/plain
We use an Ersascope for peripheral inspection and Hewlett Packard 5DX
laminography for soldered BGA inspection (takes X-rays in slices so to
speak).
Both are quite costly as routine inspection tools (time consumption,
programming, etc) but are invaluable for referee decisions.
Janice Pelchat
Benchmark Electronics
> -----Original Message-----
> From: Mark Ross [SMTP:[log in to unmask]]
> Sent: Monday, July 30, 2001 9:56 AM
> To: [log in to unmask]
> Subject: [TN]
>
> We have a BGA we need to inspect. However, the kicker is that
> directly below the BGA there is a socket adapter and we have tried
> XRAY and it fails miserably.
>
> Does anyone out there inspect UNDER a BGA once it is soldered in place
> with a boroscope or fiber optic camera? Thanks.
>
> Mark Ross
> PCB Designer
> Accurate Technologies
>
> --------------------------------------------------------------------------
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Date: Fri, 10 Aug 2001 12:01:09 +0900
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Young Hwan Ju <[log in to unmask]>
Subject: Expiration date for soft gold surface plating
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
HI, technetters
I am writing again to ask you for getting information about expiration date
for soft Ni/Au finished BGA.
As you know, there are several surface plating methods such as HASL,
preflux. moreover each method has different expiration date.
I wonder the expiration date of soft Ni/Au finished BGA. ( thickness is
5/0.5um).
Pls let me have any kind of information or instruction.
Regards
Jay Ju
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Date: Mon, 30 Jul 2001 18:08:39 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Flex delamination?
MIME-Version: 1.0
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Daan,
Only after your second mail I took a look on the right spot...
You wrote,that adhesion on those spots is bad and going worst after
soldering, so this is clear delamination.The point is,if the problem is =
only
on those spots,or after reflow is expanding.
You should ask a lot of questions the manufacturer of those =
boards,since a
lot depends how the board is build.Those spots might be results of
drops,that attacked oxide treatment ( it seems,that copperplane is =
treated
in this way. If coverlay is based on acrylic adhesive,this might be =
epoxy
dust,that was not cured during coverlay lamination stage,which is done =
in
lower temp. compared to epoxy cycle.This can be also the original
antioxidation layer applied on the raw flexible material . Another =
point to
discuss with the manufacturer of the rigid-flex - what are the chances =
to
have it in rigid area ( it might be inside,but you can not see it due =
to
stack of rigid layers with big land areas inside) etc...
Good luck=20
Edward
Edward Szpruch
Eltek , Manager of Process Engineering
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: d. terstegge [SMTP:[log in to unmask]]
> Sent: =E1 =E9=E5=EC=E9 30 2001 15:47
> To: [log in to unmask]
> Subject: Re: [TN] Flex delamination?
>=20
> Thanks Steve,
>=20
> Here's some extra info about the picture:
>=20
> Before my destructive experiments with removing the coverlayer =
(always a
> pleasure! ) this discoloration showed through as dark spots, some =
about 1
> cm diameter. The material still looked flat, unlike most =
delaminations
> that I've seen, and that's why I'm not sure if this really is a
> delamination. After cutting the flex with scissors I found out that =
at
> these spots there is very bad adhesion between copperplane and =
coverlayer.
>=20
> Although the copper has a greenish color, it looks smooth and shiny. =
This
> was already somewhat visible before assembly, but it became worse =
during
> reflow soldering.
>=20
> Daan
>=20
> >>> <[log in to unmask]> 07/30 3:32 pm >>>
> Hi Everyone!
>=20
> Still hot as Hades, here...looks like we're looking at +100-degree =
days
> all=20
> this week!
> They did an interesting thing on one of the local news station here =
to=20
> illustrate how hot it gets inside a car, and why it's really crazy to
> leave=20
> kids or pets inside cars when it gets this hot...they actually baked
> cookies=20
> inside a car!!! Enough of that...
>=20
> Daan's asked me to post a picture for him up on our web site. Go to:
>=20
> http://stevezeva.homestead.com/index.html=20
>=20
> I've got a picture of a flex-rigid board with a greenish spot on the=20
> copperplane, under the coverlayer. I would like to know what this is, =
and
> if=20
> it we should reject it or not.
>=20
> Daan Terstegge
> SMT Centre
> Thales Communications
> Unclassified mail
> Personal Website: http://www.smtinfo.net=20
>=20
> =
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> =
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Date: Mon, 30 Jul 2001 08:33:16 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Whittaker, Dewey E. (AZ75)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Whittaker, Dewey E. (AZ75)" <[log in to unmask]>
Subject: Re: Just a few Questions
MIME-Version: 1.0
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Cathy,
Because a few of the "icons" of the industry(Doug Pauls,etc.) tell you to.
Unless you have a Freudian sense of humor,which can be attributed to
drinking too much Mountain Dew(Doug Pauls,etc.),I believe you meant to say
ionic wash.
There are many reasons to clean an assembly,besides just removing flux or
it's postreflow by-products.Knowing the end use enviroment,whether it is to
be conformally coated,as well as many other factors will determine whether
you need to clean after a no-clean process.If you would to talk to me
off-line give me a call.
Doug Pauls is also an excellent source of information.
Dewey (602-436-2766)
> -----Original Message-----
> From: Cathy Killen [SMTP:[log in to unmask]]
> Sent: Monday, July 30, 2001 5:50 AM
> To: [log in to unmask]
> Subject: [TN] Just a few Questions
>
> Hope someone can help.
> Why is an 'iconic' wash required and is it required in a no-clean process?
> Can a no-clean process achieve the desired standards, if not what is the
> best way to achieve the standards?
> Cathy Killen
> Training Instructor
> [log in to unmask] <mailto:[log in to unmask]>
> An Oasis of Training Excellence
> * 028 38314305
>
>
>
> DISCLAIMER
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Date: Mon, 30 Jul 2001 23:55:38 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Ceramic BGA's on FR4,any thermal coefficient problems
MIME-Version: 1.0
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In a message dated 07/26/2001 14:14:26, [log in to unmask] writes:
>Has there been any studies completed to prove or disprove thermal
>coefficient problems between ceramic BGA's mounted on FR4 causing long term
>reliability problems of the BGA balls (solder ball separating from PWB) over
>commercial and industrial temperature ranges?
>Commercial temp range: 0O C to +70 O C.
>Industrial temp range: -40 O C to + 80 O C.
Of course!
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Mon, 30 Jul 2001 10:32:04 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ruby Hazen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ruby Hazen <[log in to unmask]>
Subject: Line width and space
Mime-Version: 1.0
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Hello:
Could someone tell me the guidelines and/or standards about trace line width
and space in PCB? Thanks.
R.H.
_________________________________________________________________
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Date: Fri, 10 Aug 2001 14:59:59 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: SMT Pads
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Hi,
I have used both same size pads and different size pads for reflow/wave
soldering and have come to the conclusion that slightly longer pads (0.5 mm)
show advantages on wave soldering compared to reflow.
This is because taller components tend to shield the footprint from the chip
wave which can lead to skipped or open joints. The longer pads help to
capture the solder and lead it into the joint.
If you are wave soldering in-line gull wing devices, then orientate them so
that each footprint/lead goes through the solder wave one after the other.
This will prevent shielding one side of the device. Extra pads at the output
end, known as 'solder thieves' will aid drainage of the molten solder and
help prevent shorts. Orientation of these devices on the reflow side is not
an issue.
My experience also says that reflow soldering inherently gives lower defect
levels so I try to design wave soldering out of the equation. Double sided
reflow and pin in hole reflow help here.
Regards
Eric Dawson
> -----Original Message-----
> From: Cathy Killen [SMTP:[log in to unmask]]
> Sent: 10 August 2001 13:48
> To: [log in to unmask]
> Subject: [TN] SMT Pads
>
> Hi,
> Is there a difference in SMT pad/land size at the design stage if the PCB
> is
> to be reflowed or wave soldered?
> Cathy Killen
> Training Instructor
> [log in to unmask] <mailto:[log in to unmask]>
> An Oasis of Training Excellence
> * 028 38314305
>
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Date: Mon, 30 Jul 2001 11:41:14 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: DIN connector & Hardware & Labor cost...
MIME-Version: 1.0
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Guys,
Question related to cost savings..
We are currently using DIN connectors which require screws, nuts and
washers for protection against the solder joints cracking due
insertions BUT how about using the connectors with metal twist that hold
down connectors to the board that way we can eliminate the hardware
cost?
Anyone suggestions? Has anyone seen a problem with connectors with
twists?
re,
Ken Patel
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Date: Mon, 30 Jul 2001 13:37:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Just a few Questions
MIME-Version: 1.0
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Because a few of the "icons" of the industry(Doug Pauls,etc.) tell you to.
Unless you have a Freudian sense of humor,which can be attributed to
drinking too much Mountain Dew(Doug Pauls,etc.),I believe you meant to say
ionic wash.
There are many reasons to clean an assembly,besides just removing flux or
it's postreflow by-products.Knowing the end use enviroment,whether it is to
be conformally coated,as well as many other factors will determine whether
you need to clean after a no-clean process.If you would to talk to me
off-line give me a call.
Doug Pauls is also an excellent source of information.
**Oh, hell. Now I have to buy Dewey another beer at IPC. "Industry
Icon?". That means when you click on me, I crash and give you the blank
look of the Blue Screen of Death. Any time someone mentions my name three
times in an e-mail, I turn into a large Norwegian rat for 1 day. Thanks a
lot, Dewey.
The way I read the original question, I don't know if Cathy was referring
to the final rinsing, a general cleaning, or to the ROSE/SEC cleanliness
test.
I don't disagree with any of the former commenters, but the issue of
cleaning and cleanliness can be a complex one. If you have an assembly
process which incorporates cleaning, then you have the opportunity to
remove residues. If you have a no-clean assembly process, you must
determine, in advance, if the constituent parts (boards and components) are
clean enough to avoid electrochemical failures. How clean is clean enough?
A very difficult question to answer and can only be done on a case by case
basis in my opinion.
I would recommend that you get the following documents to assist in your
education on the matter:
IPC-TP-1115: SELECTION AND IMPLEMENTATION STRATEGY FOR A LOW-RESIDUE
NO-CLEAN PROCESS. This document discusses all the factors that an
assembler has to consider, cleanliness being a big one, when switching to
no-clean assembly methods.
IPC-HDBK-001: This document is a companion to J-STD-001. I was the editor
or writer for sections 4 (Fluxes) and 8 (Cleaning and Cleanliness). It
goes into the various cleanliness tests and cleaning in general. I
understand that a similar document is being initiated as a companion to
IPC-A-610.
EMPF Report RR0013: An In-Depth Look at Ionic Cleanliness Testers. This
may also be available as an IPC technical paper. If not, the paper is
available from www.empf.org. The paper discusses ROSE/SEC testers and why
they should be used ONLY for process control and not product acceptance.
I authored a column for Circuits Assembly Magazine
(www.circuitsassembly.com) called Process Rx for a number of years, with
topics including cleaning and cleanliness testing. You can check their
archives or the Library section of CSL (www.residues.com) for copies.
I wrote two articles for the October and November 2000 IPC Review on bare
board cleanliness specifications and assembly cleanliness specifications in
general.
Jack Brous, often considered the father of the Omegameter, wrote a paper
that outlined the origins of the ROSE test and how it can and can't be
used. IPC should have it as a technical paper. If not, I have it around
here somewhere.
If that is not enough to put you to sleep, I wrote another few documents
called the Layman's Guide to MIL-STD-2000A and the Layman's Guide to
J-STD-001B. They cover the aspects of cleaning and qualifying the process.
Well, that should be enough for a start. Let me know if I can help some
more.
Doug Pauls
Rockwell Collins
Industry Court Jester
(Now where did I put that Mountain Dew.....)
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Date: Mon, 30 Jul 2001 14:14:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Orlowski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Orlowski <[log in to unmask]>
Subject: German Inspection Jig/Support
Has anybody located a U.S. distributor of Wolfgang's "Kugeltisch"
inspection jig? It sounds like an elegant solution to a common problem. I
must have one! Thanks in advance.
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Date: Tue, 17 Jul 2001 23:37:55 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Just a question...
MIME-Version: 1.0
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boundary="part1_da.92def0f.28865e93_boundary"
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I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case, maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I've gotta off-the-wall question...am I the only one that faces the stuff
<BR>that I post about, or am I the only one that posts about the problems I see?
<BR>Just curious...
<BR>
<BR>It seems like I have a "black-cloud" following me...if that's the case, maybe
<BR>I should persue a different profession....hehehe.
<BR>
<BR>Anyways, do any of you see the same stuff that I do? Does this stuff go with
<BR>the territory? Kinda think it does, but nobody whines like I do...hehehe.
<BR>
<BR>Thanks....
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_da.92def0f.28865e93_boundary--
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Date: Mon, 30 Jul 2001 12:39:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Thorup, John" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Thorup, John" <[log in to unmask]>
Subject: Re: German Inspection Jig/Support
MIME-Version: 1.0
Content-Type: text/plain
I'll bet most of us have one of these lurking in some dusty corner already.
A little ingenuity and one of those ball and socket pan/tilt assemblies that
used to come with computer monitors could be the ticket. I know I have one
here somewhere...where did I last see that thing?
John Thorup
> -----Original Message-----
> From: Mark Orlowski [SMTP:[log in to unmask]]
> Sent: Monday, July 30, 2001 12:14 PM
> To: [log in to unmask]
> Subject: [TN] German Inspection Jig/Support
>
> Has anybody located a U.S. distributor of Wolfgang's "Kugeltisch"
> inspection jig? It sounds like an elegant solution to a common problem.
> I
> must have one! Thanks in advance.
>
> --------------------------------------------------------------------------
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Date: Fri, 10 Aug 2001 10:24:05 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject: Re: VIAS in pads...
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Hi Ken,
1. Yes, square area. Basically no IC pins, no sot23s, but most discrete components are OK.
2. Yes via towards heel.
3. Soldermask defined pad (donut) leaving plated hole clear of soldermask for venting during
solder reflow.
If you had .010 mil plated via hole with .030 mil pad (non-smt side) then the soldermask
opening would be .016 dia. (non-smt side)
I just notify assembly house that there is vias in solder pads so they can compensate on
solder stencil.
I stay very consistent on which components get the vias in pads so they can count on a
certain aperture Dcode for the
solder paste stencil. This way they can compensate by dcode and not search for XY
locations.
Greg Scott
Cray Inc.
----------------------------------------------------
Ken Patel wrote:
> Greg,
> Can you clarify the following...
> (1) What do you mean by 170 mils area - Are you referring as a length or area? I think you are
> saying square mils here.
> (2) Do you mean via towards the heel and not toe on chip parts?
> (3) No solder mask on via pad on other side, the non-SMT pad side.
>
> re,
> Ken Patellast pick:
>
> Greg Scott wrote:
>
> > We have had great success with vias in pads, by establishing some rules.
> > NO vias in following component's pads.
> > 0603 and smaller, components of any style where the pad has an area of less than 170
> > mils.
> > No gull wing pin style ICs.
> > Also we tend to place via on chip parts off center of pad towards center of part.
> > Also we capture the bottom side (none solder side) of via with solder mask, solder mask
> > opening should be only large enough to clear drill (with some tolerance)
> >
> > hope this helps.
> > Greg Scott
> > Cray Inc.
> >
> > "Sklenar Vit (RBAU-BK/MGE4)" wrote:
> >
> > > We had this design and did not like it despite of fact it saved a lot of PBB
> > > space. Problem was , especially for small chip packages ( 0603) that volume
> > > of vias barrel is comparable to volume of solder joint and this vias was
> > > "steeling" solder from solder joint accidentally ( during wave soldering).
> > > Result - insufficient or even missing solder joint.
> > >
> > > We do not have this layout design anymore ..
> > >
> > > Regards
> > >
> > > Vit Sklenar MGE4VS
> > > T: (61 3)9541 7734 F: (61 3) 9541 3909
> > > e-mail work: [log in to unmask]
> > > e-mail home: [log in to unmask]
> > > > Robert Bosch (Aust) ,
> > > 1555 cnr.Centre and McNaugton Road,
> > > > Clayton , VIC 3169, Australia
> > > >
> > > >
> > > > -----Original Message-----
> > > > From: Ken Patel [SMTP:[log in to unmask]]
> > > > Sent: Thursday, August 09, 2001 4:53 AM
> > > > To: [log in to unmask]
> > > > Subject: [TN] VIAS in pads...
> > > >
> > > > Assemblers,
> > > > How robust is the VIA in the pad technology now? Can someone share the
> > > > process of handling board that has vias in pads?
> > > >
> > > > Most of our boards have VIAS in the pads and there is no way out.
> > > >
> > > > re,
> > > > Ken Patel
> > > >
> > > > --------------------------------------------------------------------------
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Date: Fri, 10 Aug 2001 11:12:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Solder conditions
MIME-Version: 1.0
Content-Type: text/plain
Sounds like amoung other things you have a solder fluxer problem, I.E you
aren't getting any because the nozzle is clogged, not moving and/or maybe
the the fluxer was not purged when the solderwave process changed from
aqueous to no-clean or vice versa and you have mixed fluxes.
Dorothy
> ----------
> From: Kathy Bergman[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Kathy Bergman
> Sent: Friday, August 10, 2001 10:59 AM
> To: [log in to unmask]
> Subject: Solder conditions
>
> I am looking to get some help in identifying the causes of certain post
> wave
> solder conditions. In particular, a "cracked ice" effect in which the very
> surface of the solder looks like a thin layer of it has been cracked in
> the
> way that ice would crack. Another one is lumpy solder, as if the solder
> had
> dirt in it. (I know it doesn't). I am a board manufacturer with just a
> minimum of assembly knowledge.
> I am unable to post a good picture of the conditions at this time. I
> am wondering if there are some on line resources I can tap into, to see
> some
> visual examples of these and other conditions.
> Also, what would be a normal wave profile for a board such as this: .093
> thick FR4, through hole technology, approx. 6x11, .025 to .195 sized
> holes,
> HASL finish. Please include any prebake information.
> I apprectiate in advance any help I can get.
> Kathy Bergman
>
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Date: Mon, 30 Jul 2001 13:44:37 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
What are you inspecting for. Normally XRAY inspection is for bridging and
not much else. HP's 5DX machine will XRAY your BGA on any side of the PCA.
Dorothy
> ----------
> From: Mark Ross[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Monday, July 30, 2001 6:56 AM
> To: [log in to unmask]
>
> We have a BGA we need to inspect. However, the kicker is that
> directly below the BGA there is a socket adapter and we have tried
> XRAY and it fails miserably.
>
> Does anyone out there inspect UNDER a BGA once it is soldered in place
> with a boroscope or fiber optic camera? Thanks.
>
> Mark Ross
> PCB Designer
> Accurate Technologies
>
> --------------------------------------------------------------------------
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Date: Mon, 30 Jul 2001 17:02:35 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Hiteshew, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Hiteshew, Michael" <[log in to unmask]>
Subject: Re: Clearance area around holes
MIME-version: 1.0
Content-type: text/plain
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Pete,
I'd have to disagree. I think Daan's board barely meets Level C
(reduced producibility) standards according to IPC-2221, Section 9.0.
Daan requires a 0.3mm (12 mil) diameter finished hole. Add to that
** at least ** 0.2mm (8 mils) of fabrication allowance. That leaves
0.1mm (4 mils) left - that's 0.05mm (2 mils) of clearance between
the barrel and the surrounding copper that needs to be etched in a
production environment. That would be very tough to do under highly
controlled experimental conditions!
In my humble opinion, that board was bound from the start to be a
problem once it got to production.
Michael Hiteshew
Lockheed Martin NE&SS Marine Systems
410-682-1259
-----Original Message-----
From: <Peter George Duncan> [mailto:[log in to unmask]]
Sent: Sunday, July 29, 2001 8:50 PM
To: [log in to unmask]
Subject: Re: [TN] Clearance area around holes
Daan,
The sizes you quote are not especially small, nor is the difference between
them. I'm not totally clear from your description what you are meaning,
but, (converting to my old-fashioned language), do you have 12 mil diameter
holes going through 24 mils diameter exclusion zones in the copper planes?
Unless your Fab House's registration accuracy is very bad, you will have a
nominal 6 mils all-round clearance and in practice, shouldn't have less
than 3 to 4 mils clearance. Is this OK electrically if your small
clearances are, for example, at layers with high power? It should not be a
difficult job for a decent Fab House to make this board for you, though.
Pete Duncan
----------------------------------------------------------------------------
---
Hi Technet,
Here's a question for the bare board experts out there:
One of our pcb-suppliers had rejects on a complete batch of our boards
because the clearance between the via's and the surrounding copperplane was
so small that it resulted in short circuits.
The holes were designed 0.3 mm (finished hole size) and the openings in the
copperplane were 0.6 mm, leaving only a small clearance area. The board
measures about 20*15 cm.
What do you think, is a board like this manufacturable for a decent board
shop, or is it really that difficult? Could you give me a typical value
for the minimum clearance around the finished-hole that board vendors need
?
Best regards,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
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Date: Wed, 18 Jul 2001 07:42:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Re: Just a question...
MIME-Version: 1.0
Content-Type: text/plain
Steve:
Speaking for myself, I only consult the 'net when either I'm at ground zero,
such as my recent post on developing a mold for potting, or when I've
exhausted all of my own possible solutions to problems. I also will not post
because you really hate to abuse the system by posting every little thing
that comes up.
However, you Steve, are legendary on this 'net, therefore you can post
whatever and whenever you need to. Besides, you have a way of turning
problems into sources of entertainment. All of my problems pale in
comparison.
Seriously, from a manufacturing standpoint, what we do here is not really
cutting edge stuff. Very conservative designs with approved suppliers with
rather long lead times and long cycle times. SOS if you know what I mean.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Tuesday, July 17, 2001 11:38 PM
> To: [log in to unmask]
> Subject: [TN] Just a question...
>
> I've gotta off-the-wall question...am I the only one that faces the stuff
> that I post about, or am I the only one that posts about the problems I
> see?
> Just curious...
>
> It seems like I have a "black-cloud" following me...if that's the case,
> maybe
> I should persue a different profession....hehehe.
>
> Anyways, do any of you see the same stuff that I do? Does this stuff go
> with
> the territory? Kinda think it does, but nobody whines like I do...hehehe.
>
> Thanks....
>
> -Steve Gregory-
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Date: Fri, 10 Aug 2001 13:31:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: NTC: Just a thanks about BGA/ X-ray question posted earlier
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_6A302865.15741895"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_6A302865.15741895
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
You guys are the greatest resource. I appreciate all of the response from =
a post I had made earlier this week. I received a lot of good responses. =
Surprisingly we also posted the same question to smta and only received 3 =
responses. I had that many in 1 hour from technet. =20
Have a great weekend, finally some heat relief......
Kathy=20
--=_6A302865.15741895
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY style="FONT: 10pt Haettenschweiler; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>You guys are the greatest resource. I appreciate all of the response
from a post I had made earlier this week. I received a lot of good
responses. Surprisingly we also posted the same question to smta and only
received 3 responses. I had that many in 1 hour from technet. </DIV>
<DIV> </DIV>
<DIV>Have a great weekend, finally some heat relief......</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_6A302865.15741895--
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Date: Wed, 18 Jul 2001 07:36:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Just a question...
Mime-Version: 1.0
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Steve, I concur.....
You ARE the greatest thing since sliced bread.=20
Jason Gregory
Software Specialist - NPI Group
SCI Systems/Plant 2
13000 S. Memorial Pkwy.
Huntsville, AL. 35803
(256) 882-4107 x3728
[log in to unmask]
>>> [log in to unmask] 07/17/01 10:37PM >>>
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I =
see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case, =
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go =
with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
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Date: Wed, 18 Jul 2001 10:54:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mark Hargreaves <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Hargreaves <[log in to unmask]>
Subject: HASL thickness spec
MIME-Version: 1.0
Content-Type: text/plain
Is there an IPC spec regarding the thickness (or flatness) of HASL solder
coating? I don't see it referenced in IPC 6012 or IPC-A-600.
Thanks,
Mark Hargreaves
EMDS, Inc
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Date: Wed, 18 Jul 2001 17:30:58 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: HASL thickness spec
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
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Hi Mark,
As far as I know this is not specified in IPC-specs, but some very usefull =
documentation about the HASL-proces and thickness-specifications for a =
"capable process" can be found at http://people.ne.mediaone.net/sgoodell/ch=
apter30/ch30.html
It's a complete chapter of the "Printed Circuits Materials Handbook".=20
Best regards,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Mark Hargreaves <[log in to unmask]> 07/18 4:54 pm >>>
Is there an IPC spec regarding the thickness (or flatness) of HASL solder
coating? I don't see it referenced in IPC 6012 or IPC-A-600.
Thanks,
Mark Hargreaves
EMDS, Inc
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Date: Wed, 18 Jul 2001 08:36:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Rework of 0201 components
MIME-Version: 1.0
Content-Type: text/plain
Julien,
I heard from someone that a solder iron tweezer was good. Two separate
solder tips will not work. The part is and the land pads are too small.
Exactly what process a person would use I do not know. For instance, would
it work to be putting solder down, placing the part and remelting, or
putting solder on one pad then heating and placing the part and filling in
the other pad. It is tough to rework 0402's and 0201's because both the part
size and the layout that is recommended now adays. If you are working on a
RF circuit there is evidence, though acceptable per IPC specs, that flux
residue and the reworked solder joint will "detune" the assembly.
I have been trying to figure out how to remove/wick/suck solder off these
tiny land pads that are so closely spaced and not take the pad too. Is there
equipment that can doo this delicate process or will boards have to be
tossed each time?
Dorothy Lush
> ----------
> From: Julien Bouchard[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Julien Bouchard
> Sent: Wednesday, July 18, 2001 7:31 AM
> To: [log in to unmask]
> Subject: Rework of 0201 components
>
> Hi everybody,
> We will soon start to use 0201 component for some tests. The
> placement and
> the print seem to be ok, but we still have some interogation about the
> rework of theses components. They are really difficult to handle and to
> solder. Anybody have some advice for the reworks of these so much littles
> components ??? Thank you.
>
> Julien Bouchard
>
> --------------------------------------------------------------------------
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>
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Date: Wed, 18 Jul 2001 11:39:07 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Vandendolder, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Vandendolder, Ron" <[log in to unmask]>
Subject: Re: diamond impregnated hard gold
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Richter Precision in East Petersburg PA does a Chemical Vapor Deposited
(CVD) hard carbon treatment. It may not meet your specs, but calling them
may give you a lead to someone who might.
Good Luck,
Ron VandenDolder
Telaxis Communications
SouthDeerfield, MA
413-665-8551
-----Original Message-----
From: Paul Linehan [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 10:26 AM
To: [log in to unmask]
Subject: [TN] diamond impregnated hard gold
Hi,
We have a customer requirement for diamond impregnated hard gold plating.
Is this an available technology?
Paul Linehan
Nashua Circuits
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Date: Wed, 18 Jul 2001 12:24:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: White residue from conformal coating
Mime-Version: 1.0
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What causes white residues after conformal coating? The coating is an =
acrylic and after the first coat there appears to be a white residue and =
after the 24 hour cure the coating appears very dull and still has some of =
the white residues. The residues almost look like water flux residue but =
it isn't. The supplier that the coating was purchased from says it is =
strictly humidity related and only a cosmetic issue. There is no visible =
loss of adhesion. The solder mask is a LPI matte finish. Can this be =
part of the problem? =20
--=_98C2FB58.E382EE56
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Haettenschweiler; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">What
causes white residues after conformal coating? The coating is an acrylic
and after the first coat there appears to be a white residue and after the 24
hour cure the coating appears very dull and still has some of the white
residues. The residues almost look like water flux residue but it
isn't. The supplier that the coating was purchased from says it is
strictly humidity related and only a cosmetic issue. There is no visible
loss of adhesion. The solder mask is a LPI matte finish. Can this be
part of the problem? </BODY></HTML>
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Date: Wed, 18 Jul 2001 14:32:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Fahey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Fahey <[log in to unmask]>
Subject: EIA 481-2
Folks,
I do not have a copy of this EIA 481-2 standard, but can anyone tell me if
this spec contains information in relation to STANDARD quantities per reel.
i.e: If I order a reel of 44 pin QFP's from a supplier who adheres to EIA
481-2, does this require them to put a particular amount of components on
the reel, or is this up to the individual supplier/customer?
Thanks for your help,
John
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Date: Fri, 10 Aug 2001 15:25:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Susana Anaya <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Susana Anaya <[log in to unmask]>
Subject: Re: Material specification (7781 E-glass)
In-Reply-To: <000001c121b4$7e34bd60$4200a8c0@stelgen>
Mime-Version: 1.0
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Ok, my turn to try and give back here...(thanks to all who replied to my
question about availablity of cap arrays). 7781 E-glass means E=
Electrical. E-glass is an aluminosilicate glass. 7781 = the yarn style
(yarn, warp x fill and weight). "7781" just refers to the yarn style, not
the finished material and sizes available or application. In your
comparison shopping for "7781 E-glass" for PCB use you want to look for
resin-compatibility as this varies from mfgr. to mfgr. depending on how the
material is processed. Before weaving the yarn is sized with a binder or
coating to maintain strand integrity and protect the fibers during the
weaving process. After weaving the fabric is "desized" to permit adhesion
between the glass fiber and chrome or silane finishing agents. Finally, the
fabric is finished to give desired resin compatibility. There are
conventional processed E-glass PCB yarns (usually with an oily starch) and
there are some with newer coatings available now that are supposed to help
eliminate heat cleaning ( a problem with the oil starch used for "sizing"),
improve hydrolytic stability and increase overall laminate strength and
stiffness among other things. Take a look at websites for Owens Corning,
PPG Industries, Nippon among others for more info.
-eom-
At 11:52 AM 8/10/01 -0400, Steve Telgen wrote:
>Hi, everyone,
>Does anyone know what 7781 E glass is? It's supposed to be a type of
>fiberglass material for PCBs.
>TIA
>Steve Telgen
>IGK Industries
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Date: Wed, 18 Jul 2001 13:02:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: White residue from conformal coating
MIME-Version: 1.0
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Kathy,
I would argue against the "only a cosmetic issue" statement. The moisute (if this is the cause) takes up space in the polymer coating and will be a path for more moisture and contaminants to permiate to the surface.
Because you are spending time and money to coat the boards it is obvious you are expecting them to be exposed to harsh conditions. These residues/gaps in the coating material will reduce the protective ability of the coating.
What is the RH in the coating room?
David A. Douthit
Manager
LoCan LLC
Kathy Kuhlow wrote:
> What causes white residues after conformal coating? The coating is an acrylic and after the first coat there appears to be a white residue and after the 24 hour cure the coating appears very dull and still has some of the white residues. The residues almost look like water flux residue but it isn't. The supplier that the coating was purchased from says it is strictly humidity related and only a cosmetic issue. There is no visible loss of adhesion. The solder mask is a LPI matte finish. Can this be part of the problem?
>
> ------------------------------------------------------------------------
>
> TEXT.htmName: TEXT.htm
> Type: Plain Text (text/plain)
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Date: Mon, 30 Jul 2001 18:33:56 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Brad Saunders <[log in to unmask]>
Subject: Re: Clearance area around holes
MIME-Version: 1.0
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boundary="part1_bb.119cdc30.28973ad4_boundary"
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Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
Hello All;
Relative to plane clearance diameter, fine pitch and micro BGA pad sizes of=20
.019 inch and below narrowly allow for .004 spacing and .004 inch trace=20
width. =A0The plated through hole is tangent to edge of pad and potentially=20
"break-out". =A0In the .8mm BGA exercise we need to maximize the copper plan=
e=20
web and also have producibilty. =A0Based on the ,019 pad is a challenging=20
diameter; the clearance is moreso. =A0Tangency and or break out in the=20
clearance is a short and scrap. =A0One must calculate, in a true positional=20
format, worst case location of drilled hole and add minimum dielectric=20
spacing requirement. =A0This is also a good time to add "cheap insurance" to=
=20
obtain a solid producible board. =A0Keep in mind that it is not unusual to s=
ee=20
upwards of 40% plane layers. To date the pressing question is: what is the=20
drilled hole diameter. =A0It will hover in the 10/1 aspect ratio (drill to n=
on=20
plated nominal thickness). =A0Realistic applications are 16 layer .059 thick=
,=20
18-22 layer .093, 24+ layer in over .200 thick. =A0I say "to date" due to=20
registration of layers being as or more critical to success rather than=20
"just" the aspect ratio. =A0This explains Laser Direct Imaging, wet resist,=20=
and=20
the like. =A0
I recomend .004 min web; leading to .0275 clearance, direct hit in place of=20
thermals, and a non defined finished hole diameter (naturally within reason)=
.=20
=A0The hole diameter needs to be a function of .001 inch min wall thickness=20
verses a pin gauge or crossectional exam for diameter.
Well, Daan =A0"what I think" is .3mm(.0118) PTH within .6mm(.0236) clearance=
is=20
.1mm(.004) to small of a clearance. =A0In today's "micropackaging" mils coun=
t.=20
Boston's Coretec Brad
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Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=
=3D"Arial" LANG=3D"0">Hello All;
<BR>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ce=
ntury Gothic" LANG=3D"0">Relative to plane clearance diameter, fine pitch an=
d micro BGA pad sizes of=20
<BR>.019 inch and below narrowly allow for .004 spacing and .004 inch trace=20
<BR>width. =A0The plated through hole is tangent to edge of pad and potentia=
lly=20
<BR>"break-out". =A0In the .8mm BGA exercise we need to maximize the copper=20=
plane=20
<BR>web and also have producibilty. =A0Based on the ,019 pad is a challengin=
g=20
<BR>diameter; the clearance is moreso. =A0Tangency and or break out in the=20
<BR>clearance is a short and scrap. =A0One must calculate, in a true positio=
nal=20
<BR>format, worst case location of drilled hole and add minimum dielectric=20
<BR>spacing requirement. =A0This is also a good time to add "cheap insurance=
" to=20
<BR>obtain a solid producible board. =A0Keep in mind that it is not unusual=20=
to see=20
<BR>upwards of 40% plane layers. To date the pressing question is: what is t=
he=20
<BR>drilled hole diameter. =A0It will hover in the 10/1 aspect ratio (drill=20=
to non=20
<BR>plated nominal thickness). =A0Realistic applications are 16 layer .059 t=
hick,=20
<BR>18-22 layer .093, 24+ layer in over .200 thick. =A0I say "to date" due t=
o=20
<BR>registration of layers being as or more critical to success rather than=20
<BR>"just" the aspect ratio. =A0This explains Laser Direct Imaging, wet resi=
st, and=20
<BR>the like. =A0
<BR>I recomend .004 min web; leading to .0275 clearance, direct hit in place=
of=20
<BR>thermals, and a non defined finished hole diameter (naturally within rea=
son).=20
<BR>=A0The hole diameter needs to be a function of .001 inch min wall thickn=
ess=20
<BR>verses a pin gauge or crossectional exam for diameter.
<BR>Well, Daan =A0"<I>what I think</I>" is .3mm(.0118) PTH within .6mm(.0236=
) clearance is=20
<BR>.1mm(.004) to small of a clearance. =A0In today's "micropackaging" mils=20=
count.</FONT><FONT COLOR=3D"#ff0000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"=
Century Gothic" LANG=3D"0">=20
<BR>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ce=
ntury Gothic" LANG=3D"0">Boston's Coretec Brad</FONT></HTML>
--part1_bb.119cdc30.28973ad4_boundary--
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Date: Mon, 30 Jul 2001 15:21:47 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ruby Hazen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ruby Hazen <[log in to unmask]>
Subject: RE: Line width and space
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Hi, Dorothy:
These are power lines. The voltage between them is about 180V. Please let me
know if you have any other questions. Thanks.
R.H.
>From: [log in to unmask]
>To: [log in to unmask]
>Subject: RE: Line width and space
>Date: Mon, 30 Jul 2001 14:22:35 -0700
>
>Ruby could you tell everyone what your application is? Power? RF? Digital?
>PTH? Industrial? Medical? It all makes a difference.
>
>Dorothy
>
> > ----------
> > From: Ruby Hazen[SMTP:[log in to unmask]]
> > Reply To: TechNet E-Mail Forum.;Ruby Hazen
> > Sent: Monday, July 30, 2001 10:32 AM
> > To: [log in to unmask]
> > Subject: Line width and space
> >
> > Hello:
> >
> > Could someone tell me the guidelines and/or standards about trace line
> > width
> > and space in PCB? Thanks.
> >
> > R.H.
> >
> > _________________________________________________________________
> > Get your FREE download of MSN Explorer at
>http://explorer.msn.com/intl.asp
> >
> >
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Date: Tue, 31 Jul 2001 09:17:27 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Cathy Killen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: Encapsulated Ions
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Apologies for 'Iconic' instead of ionic. I wish it was because of the
mountain dew.
I have another question:
How do you carry out a non-destructive test in a no-clean process. Ions are
encapsulated as part of the process, surely methods used in the standards
will release the ions and then fail the test?
Cathy Killen
Training Instructor
[log in to unmask] <mailto:[log in to unmask]>
An Oasis of Training Excellence
* 028 38314305
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Date: Wed, 18 Jul 2001 16:09:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Just a question...
Mime-Version: 1.0
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Steve,
No Katana.....NO NO NO. Go for the gusto....maybe a Huyabusa 1300 or a =
ZX-12 Ninja.
Jason Gregory
Software Specialist - NPI Group
SCI Systems/Plant 2
13000 S. Memorial Pkwy.
Huntsville, AL. 35803
(256) 882-4107 x3728
[log in to unmask]
>>> David Ricketts <[log in to unmask]> 07/18/01 03:40PM =
>>>
Steve, maybe you just need a new Suzuki Katana (although I prefer my
Corvette) to outrace that "black cloud".
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Tuesday, July 17, 2001 8:38 PM
To: [log in to unmask]
Subject: [TN] Just a question...
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I =
see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case,
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go =
with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
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Date: Wed, 18 Jul 2001 16:10:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: White residue from conformal coating
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Hans,=20
It appears to be in the coating. On the uncoated boards there are no =
visible residues, fingerprints, etc. And it is very hot and humid today =
and yesterday (dew point low to mid 70's).=20
Kathy=20
>>> [log in to unmask] 07/18/01 12:53PM >>>
Kathy,
Is the white residue in the coating or on the assemblies surface?
It's probably moisture related as has been discussed recently.
Do you dry the assemblies prior to coating?
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Process Engineer
Toppan Electronics, Inc.
770 Miramar Road
San Diego, CA 92126
(858) 695 - 2222 ext. 241
(858) 695 - 6823 fax
[log in to unmask]
-----Original Message-----
From: Kathy Kuhlow [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 10:24 AM
To: [log in to unmask]
Subject: [TN] White residue from conformal coating
What causes white residues after conformal coating? The coating is an
acrylic and after the first coat there appears to be a white residue and
after the 24 hour cure the coating appears very dull and still has some of
the white residues. The residues almost look like water flux residue but =
it
isn't. The supplier that the coating was purchased from says it is =
strictly
humidity related and only a cosmetic issue. There is no visible loss of
adhesion. The solder mask is a LPI matte finish. Can this be part of the
problem?
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Date: Tue, 31 Jul 2001 10:27:54 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Just a few Questions
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Dang it, Doug, you filled your Omega Meter with it.
Brian
[log in to unmask] wrote:
>
> Because a few of the "icons" of the industry(Doug Pauls,etc.) tell you to.
> Unless you have a Freudian sense of humor,which can be attributed to
> drinking too much Mountain Dew(Doug Pauls,etc.),I believe you meant to say
> ionic wash.
> There are many reasons to clean an assembly,besides just removing flux or
> it's postreflow by-products.Knowing the end use enviroment,whether it is to
> be conformally coated,as well as many other factors will determine whether
> you need to clean after a no-clean process.If you would to talk to me
> off-line give me a call.
> Doug Pauls is also an excellent source of information.
>
> **Oh, hell. Now I have to buy Dewey another beer at IPC. "Industry
> Icon?". That means when you click on me, I crash and give you the blank
> look of the Blue Screen of Death. Any time someone mentions my name three
> times in an e-mail, I turn into a large Norwegian rat for 1 day. Thanks a
> lot, Dewey.
>
> The way I read the original question, I don't know if Cathy was referring
> to the final rinsing, a general cleaning, or to the ROSE/SEC cleanliness
> test.
>
> I don't disagree with any of the former commenters, but the issue of
> cleaning and cleanliness can be a complex one. If you have an assembly
> process which incorporates cleaning, then you have the opportunity to
> remove residues. If you have a no-clean assembly process, you must
> determine, in advance, if the constituent parts (boards and components) are
> clean enough to avoid electrochemical failures. How clean is clean enough?
> A very difficult question to answer and can only be done on a case by case
> basis in my opinion.
>
> I would recommend that you get the following documents to assist in your
> education on the matter:
>
> IPC-TP-1115: SELECTION AND IMPLEMENTATION STRATEGY FOR A LOW-RESIDUE
> NO-CLEAN PROCESS. This document discusses all the factors that an
> assembler has to consider, cleanliness being a big one, when switching to
> no-clean assembly methods.
>
> IPC-HDBK-001: This document is a companion to J-STD-001. I was the editor
> or writer for sections 4 (Fluxes) and 8 (Cleaning and Cleanliness). It
> goes into the various cleanliness tests and cleaning in general. I
> understand that a similar document is being initiated as a companion to
> IPC-A-610.
>
> EMPF Report RR0013: An In-Depth Look at Ionic Cleanliness Testers. This
> may also be available as an IPC technical paper. If not, the paper is
> available from www.empf.org. The paper discusses ROSE/SEC testers and why
> they should be used ONLY for process control and not product acceptance.
>
> I authored a column for Circuits Assembly Magazine
> (www.circuitsassembly.com) called Process Rx for a number of years, with
> topics including cleaning and cleanliness testing. You can check their
> archives or the Library section of CSL (www.residues.com) for copies.
>
> I wrote two articles for the October and November 2000 IPC Review on bare
> board cleanliness specifications and assembly cleanliness specifications in
> general.
>
> Jack Brous, often considered the father of the Omegameter, wrote a paper
> that outlined the origins of the ROSE test and how it can and can't be
> used. IPC should have it as a technical paper. If not, I have it around
> here somewhere.
>
> If that is not enough to put you to sleep, I wrote another few documents
> called the Layman's Guide to MIL-STD-2000A and the Layman's Guide to
> J-STD-001B. They cover the aspects of cleaning and qualifying the process.
>
> Well, that should be enough for a start. Let me know if I can help some
> more.
>
> Doug Pauls
> Rockwell Collins
> Industry Court Jester
>
> (Now where did I put that Mountain Dew.....)
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Wed, 18 Jul 2001 17:40:39 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jim Francey <[log in to unmask]>
Subject: Re: diamond impregnated hard gold
MIME-Version: 1.0
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Diamond grit can be co-deposited with electroplating - normally with Nickel
to make specialist cutting tools (e.g for glass). If it's for some kind of
wiper application (e.g slip-rings) then there's other solutions.
JF
In a message dated 18/07/2001 3:42:11 PM GMT Daylight Time, [log in to unmask]
writes:
> Hi,
>
> We have a customer requirement for diamond impregnated hard gold plating.
> Is this an available technology?
>
> Paul Linehan
> Nashua Circuits
>
>
--part1_73.10343d94.28875c57_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Diamond grit can be co-deposited with electroplating - normally with Nickel
<BR>to make specialist cutting tools (e.g for glass). If it's for some kind of
<BR>wiper application (e.g slip-rings) then there's other solutions.
<BR>
<BR>JF
<BR>
<BR>
<BR>
<BR>In a message dated 18/07/2001 3:42:11 PM GMT Daylight Time, [log in to unmask]
<BR>writes:
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi,
<BR>
<BR>We have a customer requirement for diamond impregnated hard gold plating.
<BR>Is this an available technology?
<BR>
<BR>Paul Linehan
<BR>Nashua Circuits
<BR>
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Wed, 18 Jul 2001 18:10:54 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Sewell <[log in to unmask]>
Subject: Re: Just a question...
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Black cloud? I think you've been having so much fun here you'd go insane at a
more mundane job...hehehe
Mike Sewell
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Black cloud? I think you've been having so much fun here you'd go insane at a
<BR>more mundane job...hehehe
<BR>
<BR>
<BR>Mike Sewell
<BR></FONT></HTML>
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Date: Tue, 31 Jul 2001 07:55:55 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Re: Fluxes
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Ray:
One key factor in selecting an OA (water soluble) flux is whether the
material is alcohol based or water based. During a qualification test that I
ran years ago to qualify us for J-Std-001A, we selected a material which was
a water based material. We ran some initial test runs using our typical
solder profiles. When the circuit boards reached the wave, there was still
enough moisture left on the boards from the flux. This resulted in a
splattering effect similar to water in a hot frying pan except in this case,
solder balls were evrywhere from the splattering effect! Making a long story
short, I was finally able to correct for the situation but it took a while
for me to accept and break the solder process paradigms.
So if selecting an OA flux, and you want the make the process transition
virtually seamless from RMA, select an alcohol based OA flux.
By the way, you can never eliminate RMA. Do not solder stranded wires using
OA flux!! Corrosive residues will be trapped under wire insulation resulting
in broken wires at the wrong time.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
> -----Original Message-----
> From: Golembiewski, Ray [SMTP:[log in to unmask]]
> Sent: Friday, July 27, 2001 9:13 AM
> To: [log in to unmask]
> Subject: [TN] Fluxes
>
> I am looking for data analysis between a water soluble flux, and
> an RMA. What are the major effects each has on a PCB. What do I have to
> know before I make a switch from RMA to water soluble. If you might be
> able to direct me to a link, or send me some information it would be
> greatly appreciated. Thanks again,
>
> Ray Golembiewski C.I.D.
> IPC Certified Interconnect Designer
> Manufacturing Test Engineer
> Projects Unlimited, Inc.
> (937) 918-2200
>
> --------------------------------------------------------------------------
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Date: Tue, 31 Jul 2001 07:26:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: High aspect ratio via qualification
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Steve,
The problem that you describe sounds vaguely familiar. Whilst at CSL, we
examined a problem with open circuits in high aspect ration vias, under
BGAs, on about the thickness of board you describe. The client had solder
mask that plugged the vias on the wave solder side of the board. The mask
went on before gold plating. Consequently, the sulfuric acid from the gold
plating remained in the vias and cause circumferential cracking in the
barrels of the holes. The client had not had a problem with the vias until
they dropped under 13 mil diameter. With vias larger than 13 mil, there
was enough opening for water rinsing to get down in the vias. With vias
smaller than 13 mils, the surface tension of the water prevented it from
getting down into the via. Imagine trying to clean out a capillary tube
and you get the general idea. I wrote about this in Circuits Assembly
magazine. The articles were in the Process Rx columns titled "It Cracks Me
Up" and "Sulfates in Vias: The Rest Of The Story". I can furnish them if
you desire, or you can probably get them from the CSL web site
www.residues.com.
I would say that you have to microsection to find out what is really going
on with the vias.
Doug Pauls
Rockwell Collins
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Date: Wed, 18 Jul 2001 17:59:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Taheri, Kamran" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Taheri, Kamran" <[log in to unmask]>
Subject: Re: Just a question...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Katana? Ninja? Come on people. Are you trying to help this guy out or what?
Steve, what you need is a Yamaha R1 to take care of that black cloud.
-----Original Message-----
From: Jason Gregory [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 4:09 PM
To: [log in to unmask]
Subject: Re: [TN] Just a question...
Steve,
No Katana.....NO NO NO. Go for the gusto....maybe a Huyabusa 1300 or a ZX-12
Ninja.
Jason Gregory
Software Specialist - NPI Group
SCI Systems/Plant 2
13000 S. Memorial Pkwy.
Huntsville, AL. 35803
(256) 882-4107 x3728
[log in to unmask]
>>> David Ricketts <[log in to unmask]> 07/18/01 03:40PM
>>>
Steve, maybe you just need a new Suzuki Katana (although I prefer my
Corvette) to outrace that "black cloud".
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Tuesday, July 17, 2001 8:38 PM
To: [log in to unmask]
Subject: [TN] Just a question...
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case,
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
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Date: Wed, 18 Jul 2001 16:24:18 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Galang, Jerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Galang, Jerry" <[log in to unmask]>
Subject: Re: Just a question...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
mellow out folks,
get the karma going
(read HARLEY) cruise thru life
no clouds around you then!
ok, back to the technical stuff.
RF is magic
I need a wand ;)
Jerry Galang
PCB Designer
Xircom Inc. an Intel company
805.376.6684
-----Original Message-----
From: Taheri, Kamran [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 3:59 PM
To: [log in to unmask]
Subject: Re: [TN] Just a question...
Katana? Ninja? Come on people. Are you trying to help this guy out or what?
Steve, what you need is a Yamaha R1 to take care of that black cloud.
-----Original Message-----
From: Jason Gregory [mailto:[log in to unmask]]
Sent: Wednesday, July 18, 2001 4:09 PM
To: [log in to unmask]
Subject: Re: [TN] Just a question...
Steve,
No Katana.....NO NO NO. Go for the gusto....maybe a Huyabusa 1300 or a ZX-12
Ninja.
Jason Gregory
Software Specialist - NPI Group
SCI Systems/Plant 2
13000 S. Memorial Pkwy.
Huntsville, AL. 35803
(256) 882-4107 x3728
[log in to unmask]
>>> David Ricketts <[log in to unmask]> 07/18/01 03:40PM
>>>
Steve, maybe you just need a new Suzuki Katana (although I prefer my
Corvette) to outrace that "black cloud".
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Tuesday, July 17, 2001 8:38 PM
To: [log in to unmask]
Subject: [TN] Just a question...
I've gotta off-the-wall question...am I the only one that faces the stuff
that I post about, or am I the only one that posts about the problems I see?
Just curious...
It seems like I have a "black-cloud" following me...if that's the case,
maybe
I should persue a different profession....hehehe.
Anyways, do any of you see the same stuff that I do? Does this stuff go with
the territory? Kinda think it does, but nobody whines like I do...hehehe.
Thanks....
-Steve Gregory-
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Date: Sat, 11 Aug 2001 09:05:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard Hamilton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard Hamilton <[log in to unmask]>
Subject: Re: Assembly Inspection/verification.
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: multipart/alternative;
boundary="=====================_1982497==_.ALT"
--=====================_1982497==_.ALT
Content-Type: text/plain; charset="us-ascii"; format=flowed
J,
Yes that was done in a past llife.
We used a black rubber type overlay which was cut out in house for the
parts in the last immediate process. I can't say for sure they were or were
not ESD sensitive. Pretty useful and simple.
Hope this helps.
Richard
At 10:21 PM 8/10/01 -0400, you wrote:
>TechNet,
>
>Has anyone tried to use templates or overlays at the end of a machine
>process or the end of a progressive line as a quick check for polarity or
>component orientations? If so what type of materials did you make your
>overlays from? Were they conductive for ESD? Where did you have your
>templates made? Can a board house make these from Gerber data? Stencil
>shop? I would appreciate your comments. Thanks.
>
>J. Bryant
--=====================_1982497==_.ALT
Content-Type: text/html; charset="us-ascii"
<html>
J,<br>
<br>
Yes that was done in a past llife.<br>
<br>
We used a black rubber type overlay which was cut out in house for the
parts in the last immediate process. I can't say for sure they were or
were not ESD sensitive. Pretty useful and simple.<br>
<br>
Hope this helps.<br>
<br>
Richard<br>
<br>
At 10:21 PM 8/10/01 -0400, you wrote:<br>
<font face="arial" size=2><blockquote type=cite cite>TechNet,</font><br>
<br>
<font face="arial" size=2>Has anyone tried to use templates or overlays
at the end of a machine process or the end of a progressive line as a
quick check for polarity or component orientations? If so what type of
materials did you make your overlays from? Were they conductive for ESD?
Where did you have your templates made? Can a board house make these from
Gerber data? Stencil shop? I would appreciate your comments.
Thanks.</font><br>
<br>
<font face="arial" size=2>J. Bryant</font></blockquote></html>
--=====================_1982497==_.ALT--
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Date: Tue, 31 Jul 2001 07:56:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Encapsulated Ions
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
How do you carry out a non-destructive test in a no-clean process. Ions are
encapsulated as part of the process, surely methods used in the standards
will release the ions and then fail the test?
*Cathy, Andrew Hoggan had some good answers and I will add to what he said.
If you do a suitable extraction-based test, and by suitable I mean the
right composition of solvents, time, and temperature, then you WILL get
ions. Either from the surface residues from the assembly process, or ions
leached out the base materials. Examples are chloride (present in all
epoxies), bromide (present in most flame retardant laminates), carbonate
(from many solder masks), etc. I don't consider the existing ROSE/SEC
tests to be suitable, since the times are short (10 minutes), the
temperatures relatively benign (45C max) and it is not ion specific.
The key to evaluating ROSE/SEC or any extraction-based test is to
understand what your signal means. For far too long, people have looked at
the value of 10 (suitably modified per machine) as the divider between
"good" and "bad" and never understood what the response was telling them.
When manufacturers started shifting to no-clean assembly processes, they
did not understand that the low solids flux residues dissolve in
isopropanol/water and become electrically conductive when they do so.
People used to seeing 4-5 now saw 40-50 and, to put it Biblically, there
was much wailing and gnashing of teeth. They did not understand what the
signal was telling them. That is why I prefer ion chromatography as a tool
for analyzing ions. People have been using it now for over 10 years to
help determine if the ions they see are good ions or bad ions. (Every time
I say that I think of Glinda, the Good Witch of the North in the Wizard of
Oz asking if Dorothy was a good witch or a bad witch. Where was I?)
Any time that you have a cleanliness test, whether ROSE or ion
chromatography, you have to determine several things: (1) is the test
repeatable, (2) am I seeing good residues or bad residues, and (3) how
clean is clean enough for my product in my end use application. As my
friend John Sohn puts it "the company has to do the hard work".
You can use an Omegameter type instrument on a process, provided you throw
out any preconcieved notions of what is good and bad and form your own
process control limits. You can analyze by ion chromatography, but you
have to do correlations with either field failures or accelerated life
testing in humid conditions to determine what ions are present and how
robust your assembly is to various ions.
Overall, do not look to IPC specifications to tell you what "clean" or
"dirty" is; you won't really find it. There are no more golden numbers.
No one size fits all figure. We could do that when we all manufactured
with RMAs and Freon cleaning, but there is far too much diversity in
products and materials to do that now. The best that you can hope for is
guidance from IPC on how a company should do the "hard work" to determine
their own limits. What limits are good for Rockwell Collins may not be
good for you. Clean enough for RF work might not be clean enough for
biomedical.
This is an issue that one of my task groups is working on (Bare Board
Cleanliness). I think we have good tools for measuring bare board
cleanliness, but now we have to define a protocol for how a manufacturer
might determine how clean their boards need to be for their product. A
tough task.
Well, now that my fingers are warmed up.....
Doug Pauls
Rockwell Collins
Court Jester to Jack Crawford
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Date: Wed, 18 Jul 2001 19:52:52 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Just a question...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2b.185e4e63.28877b54_boundary"
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Content-Transfer-Encoding: 7bit
Hehehe...have to agree with you Kamran, the R1 is one hellava bike. But while
I'm dreaming, I think I'd go for a Ducati 996S...IF I had a spare $22,000
laying around.
Mmmmmmmm...996cc "L" twin, 112 hp engine...trestle-style chrome moly tube
frame...carbon fiber fairing...upside down Ohlin forks...4-piston, 4-pad
Brembo brakes...titanium exhaust, aluminum mufflers...436 lbs
wet...mmmmmmm...(oh geeze, I drooled all over myself!) hehehe
-Steve Gregory-
> Katana? Ninja? Come on people. Are you trying to help this guy out or what?
> Steve, what you need is a Yamaha R1 to take care of that black cloud.
>
--part1_2b.185e4e63.28877b54_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hehehe...have to agree with you Kamran, the R1 is one hellava bike. But while
<BR>I'm dreaming, I think I'd go for a Ducati 996S...IF I had a spare $22,000
<BR>laying around.
<BR>
<BR>Mmmmmmmm...996cc "L" twin, 112 hp engine...trestle-style chrome moly tube
<BR>frame...carbon fiber fairing...upside down Ohlin forks...4-piston, 4-pad
<BR>Brembo brakes...titanium exhaust, aluminum mufflers...436 lbs
<BR>wet...mmmmmmm...(oh geeze, I drooled all over myself!) hehehe
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Katana? Ninja? Come on people. Are you trying to help this guy out or what?
<BR>Steve, what you need is a Yamaha R1 to take care of that black cloud.
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Tue, 31 Jul 2001 08:52:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Scott Kauling <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kauling <[log in to unmask]>
Organization: Tri-onics, Inc.
Subject: Re: End-of-Line SMT inspection ... need 10x magnification ...
We are using the Super Vision from Vision Technology. It ranges from 7X to
140X using a camera to display on a monitor. Their website is
www.govti.com.
Scott Kauling
Tri-onics Inc.
Highland, IL
-----Original Message-----
From: Chris Murphy [SMTP:[log in to unmask]]
Sent: Monday, July 30, 2001 6:09 PM
To: [log in to unmask]
Subject: Re: [TN] End-of-Line SMT inspection ... need 10x magnification ...
Hi Tony,
just a comment on the Mantis which may or may not be useful to you. They
are great tools - easy to use, easy on the eyes, and with a good field
of view at lower magnifications. However we find that at 10X
magnification the lack of rigidity of the arm can become a problem, as
the image doesnt tend to stay still. So if the majority of your
inspection has to be done at this magnification, you might have to
consider going to the next level of equipment - I think that they call
it the Cobra or something.
The Mantis can also double up as a radar scope / photon torpedo tracker
thingy. I have seen them in use on the bridge of the Starship
Enterprise on Star Trek - The Next Generation. The cheapskates couldnt
be bothered making their own props.
Regards,
Chris Murphy
"PERALTA, Kevin (BREA)" wrote:
>
>
> In California, WASSCO is one place that distributes MANTIS from Vision
> Eng. (1-800-492-7726) But, ye being in Ireland may be a reach.
>
> Kevin L. Peralta
> Senior Quality Systems Analyst
> TRW Aeronautical / Lucas Aerospace
>
> -----Original Message-----
> From: Tony Conlon [mailto:[log in to unmask]]
> Sent: Friday, July 27, 2001 4:54 AM
> To: [log in to unmask]
> Subject: [TN] End-of-Line SMT inspection ... need 10x magnification
> ...
>
> Folks,
> A question for ye ...
>
> At end-of-line inspection of SMT assemblies ... what equipment are ye
> using?
>
> Our spec. requires that we inspect to 10x magnification for 100%
> product
> ... to do this we 'have' to use a stereo microscope with adjustable
>
> magnification 8x to 40x.
> Problems: Tiresome for operator; impractical to do 100% because of
> conflicts with thru-put.
> What we need is more or less an 'eye-piece' (similar to a bench-top
>
> magnifier) with 10x. We can have our microscopes for back-up if and
> when
> necessary. We have seen some equipment from 'Vision Engineering'
> ... the
> Mantis product is similar to what we are looking for.
> Who supplied this product to you?
>
> For the guys whom I've bcc:'d ... this is an unusual mail for ye to
> receive
> from me ... none the less, suggestions welcome.
> Many thanks,
>
> **************************************
> Tony Conlon
>
> SMT Process Engineer
> PNY Technologies Ireland Ltd.,
> Ballivor,
> Co. Meath.
> Fax: +353 (0)405 67301
> **************************************
>
>
>
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Date: Wed, 18 Jul 2001 21:26:39 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Thanks for the replies!
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2f.1806d21f.2887914f_boundary"
--part1_2f.1806d21f.2887914f_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Everyone!
I just want to say thanks for all the kind replies! I do want to let everyone
know that I post things that are pretty generic with all of us. There's
things I can't talk about due to it being proprietary, but I am pretty aware
of what I can talk about, and what I can't.
I think there's more than a few of us that are in that category...especially
if you're a contract manufacturer. You build partnerships with your customers
that you must establish a trust with, and must follow through with, that goes
without saying.
I will ask a question of a situation that I'm faced with sometimes even when
I can find stuff in the archives, only because what was in the archives is
past knowledge, not saying that past knowledge isn't still valid, but maybe,
just maybe, something new has been learned...
I haven't been doing this stuff very long, I've only been in the industry
since I got out of the Navy in 1987 (there's those out there that consider me
a kid)...and it's changed so much since then. Every year there are new
revelations. Maybe that's why I stay in this profession (like Mike Sewell
says, I would probably get bored doing anything else...) things change so
rapidly, and all of us are challenged to do things better and faster, all the
while, the whole scope of things are evolving...
I'm just glad that I've been lucky enough to be a part of a group such as
this. Maybe next Apex, I won't fall asleep in my hotel room, and can meet
some of you face-to-face, and shake some hands...
Thanks!
-Steve Gregory-
--part1_2f.1806d21f.2887914f_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Everyone!
<BR>
<BR>I just want to say thanks for all the kind replies! I do want to let everyone
<BR>know that I post things that are pretty generic with all of us. There's
<BR>things I can't talk about due to it being proprietary, but I am pretty aware
<BR>of what I can talk about, and what I can't.
<BR>
<BR>I think there's more than a few of us that are in that category...especially
<BR>if you're a contract manufacturer. You build partnerships with your customers
<BR>that you must establish a trust with, and must follow through with, that goes
<BR>without saying.
<BR>
<BR>I will ask a question of a situation that I'm faced with sometimes even when
<BR>I can find stuff in the archives, only because what was in the archives is
<BR>past knowledge, not saying that past knowledge isn't still valid, but maybe,
<BR>just maybe, something new has been learned...
<BR>
<BR>I haven't been doing this stuff very long, I've only been in the industry
<BR>since I got out of the Navy in 1987 (there's those out there that consider me
<BR>a kid)...and it's changed so much since then. Every year there are new
<BR>revelations. Maybe that's why I stay in this profession (like Mike Sewell
<BR>says, I would probably get bored doing anything else...) things change so
<BR>rapidly, and all of us are challenged to do things better and faster, all the
<BR>while, the whole scope of things are evolving...
<BR>
<BR>I'm just glad that I've been lucky enough to be a part of a group such as
<BR>this. Maybe next Apex, I won't fall asleep in my hotel room, and can meet
<BR>some of you face-to-face, and shake some hands...
<BR>
<BR>Thanks!
<BR>
<BR>-Steve Gregory-
<BR>
<BR></FONT></HTML>
--part1_2f.1806d21f.2887914f_boundary--
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Date: Thu, 19 Jul 2001 14:18:33 +1000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Colin Weber <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Colin Weber <[log in to unmask]>
Subject: Bow & Twist
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Folks,
Is there a method of determining the maximum permissible size of two board
types?
a) A SMT PCB containing Fine pitch QFP devices
b) A SMT PCB containing PBGA 388pin 1.27mm pitch & Fine pitch QFPs
with respect to Bow and Twist.
I am interested in how the thickness of the board relates to maximum bow
and twist.
I'd like to determine this before I design the layout, rather than find out
it is wrong
after performing the tests of IPC-6012A, IPC-TM-650 2.4.22.
Regards,
Colin Weber
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Date: Thu, 19 Jul 2001 07:23:07 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: HASL thickness spec
MIME-Version: 1.0
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Hi Jack,
We have very bitter experience with specs related to HASL.=20
Especially, since soldering problems are nightmare of assemby people =
and the
easiest way is to blame the supplier of PCB.
Contrary to other para. in IPC specs,this critria is very subjective. =
In the
past we invested a lot of money and time in our trials to satisfy some =
of
our customers : we installed XRF equipment for thickness and =
composition
measurements and SERA equipment for soldereability measurements.
The problem was and stayed the same: QC of the customer put a mark on
corner of SMD pad with remark :"I do not like this appearance". All our
attempts to find objective and measureable criteria end up with =
nothing.
The methods for evaluation of solderability are based of specimens and =
we
never had been able to perform non-desctrictive test of one of such =
"SMD pad
corners" without destroying the whole PCB.
Edward
Edward Szpruch
Eltek , Manager of Process Engineering
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Jack Crawford [SMTP:[log in to unmask]]
> Sent: =E3 =E9=E5=EC=E9 18 2001 20:29
> To: [log in to unmask]
> Subject: Re: [TN] HASL thickness spec
>=20
> Mark, yes, there is a spec and it's in IPC-6012 Table 3-2. The =
applicable
> line is "Fused tin-lead or solder coat - Coverage and Solderable". =
The
> lack of any specific dimension criteria doesn't make this any less a
> requirement. There has to be complete coverage of solder on the =
land, and
> it must be wettable.
> =20
> Many physics elements involved that affect thickness and shape =
(flatness)
> of the coverage. Not counting the experience-based opinions published =
in
> some private guidelines or technical conference papers, it has not =
been
> possible for your industry peers to establish any consensus standards =
for
> HASL coverage.
> Cordially,
> Jack
> =20
> =
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> APEX - the industry's premier trade show in Electronics
> Manufacturing, January 22-24, 2002, San Diego, California.
> More information on website www.goapex.org <http://www.goapex.org>
> --------
> Jack Crawford, IPC Director of Assembly Standards and Technology
> 2215 Sanders Road, Northbrook IL 60062-6135
> [log in to unmask] <mailto:[log in to unmask]>=20
> 847-790-5393
> fax 847-509-9798
>=20
> >>> [log in to unmask] 07/18/01 09:54AM >>>
> Is there an IPC spec regarding the thickness (or flatness) of HASL =
solder
> coating? I don't see it referenced in IPC 6012 or IPC-A-600.
>=20
> Thanks,
> Mark Hargreaves
> EMDS, Inc
>=20
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Date: Thu, 19 Jul 2001 08:26:00 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
mech_eng <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: mech_eng <[log in to unmask]>
Subject: Re: EIA 481-2
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"
John,
This spec does not have specific information on standard quantities.
It covers issues like how loose components can be in the Carrier Tape
cavity, specifies standard Carrier Tape widths, the dimensions for the
sprocket holes, defines standard Reel sizes, tape leader and trailer
lengths, etc.
Since there is practically an infinite number of different surface mount
electronic package styles, and the quantity of parts that can fit on a
Standard Reel size depends on the component's length or width, and height,
it is probably outside the scope of any organization to define a Standard
quantity of parts per Reel for all packages.
The number of components is up to the individual supplier/customer.
Haim Halpert
-----Original Message-----
From: John Fahey [mailto:[log in to unmask]]
Sent: 18 July, 2001 9:32 PM
Subject: EIA 481-2
Folks,
I do not have a copy of this EIA 481-2 standard, but can anyone tell me if
this spec contains information in relation to STANDARD quantities per reel.
i.e: If I order a reel of 44 pin QFP's from a supplier who adheres to EIA
481-2, does this require them to put a particular amount of components on
the reel, or is this up to the individual supplier/customer?
Thanks for your help,
John
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Date: Thu, 19 Jul 2001 01:11:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mary Jane Chism <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mary Jane Chism <[log in to unmask]>
Subject: Just a question
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Steve,
I have not been subscribing very long to "TechNet"; but in the time that I
have, I have seen more informative and interesting material in your postings
than I have encountered in the 17 years I have been in the field of
electronics. This goes without saying that your "humor" is also a relief to
the sometime stressful aspects of this field. Keep up the good work on your
"website" postings. (I love the music also.)
------_=_NextPart_001_01C11019.A9B8C550
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
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<BODY>
<P><FONT SIZE=3D2 FACE=3D"Arial">Steve,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">I have not been subscribing very long =
to "TechNet"; but in the time that I have, I have seen =
more informative and interesting material in your postings than I have =
encountered in the 17 years I have been in the field of electronics. =
This goes without saying that your "humor" is also a relief =
to the sometime stressful aspects of this field. Keep up the good work =
on your "website" postings. (I love the music =
also.)</FONT></P>
</BODY>
</HTML>
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Date: Thu, 19 Jul 2001 14:44:00 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Bow & Twist
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Much of the bow and twist these days is down to the choice of material used
for the substrate coupled with 'balance' in the board design and ultimately
on the capability of the fabrication process.
If you have heavy planes in the board, make sure they're distributed evenly
throughout the layers, otherwise any good PCB Fab worth his salt will keep
any bow and twist within the bounds of the usual specs. It used ot be that
the thicker the board was, the more rigid it was and the less inclined it
was to warping. These days, more than 20 mils bow or twist on a 63 mil
thick board measuring 9 x 6 inches is unusual.
Are you designing boards to be made to MIL-PRF-55110, to an IPC spec or to
something more commercial?
Pete Duncan
Colin Weber
<colin.weber@VARI To: [log in to unmask]
ANINC.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: TechNet Subject: [TN] Bow & Twist
<[log in to unmask]>
07/19/01 12:18 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Colin
Weber
Folks,
Is there a method of determining the maximum permissible size of two board
types?
a) A SMT PCB containing Fine pitch QFP devices
b) A SMT PCB containing PBGA 388pin 1.27mm pitch & Fine pitch QFPs
with respect to Bow and Twist.
I am interested in how the thickness of the board relates to maximum bow
and twist.
I'd like to determine this before I design the layout, rather than find out
it is wrong
after performing the tests of IPC-6012A, IPC-TM-650 2.4.22.
Regards,
Colin Weber
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Date: Thu, 19 Jul 2001 07:38:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: White residue from conformal coating
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Graham,
Thanks for the insights on the "blush" phenomena. How interesting that it
comes up in the same discussion as your "work naked bonus".
Is there any link between the type of solvent in the coating and blush, or
is it exclusively humidity related? One project that has been suggested
for me is to replace the toluene and xylene we use as acrylic thinners with
methyl propyl ketone. If such a switch were made, would you expect a
greater or lesser susceptibility to blush, or is it immaterial (no pun
intended).
Doug Pauls
Rockwell Collins
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Date: Thu, 19 Jul 2001 10:37:05 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dee Stover <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dee Stover <[log in to unmask]>
Subject: Gerber specification
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
I need to find the specifications of gerber language, would any of you know
where I can get that information.
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
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Date: Thu, 19 Jul 2001 14:43:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Hybiske, Tom" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Hybiske, Tom" <[log in to unmask]>
Subject: Re: Gerber specification
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Gerber Scientific has a publication explaining the RS274X language. Contact
them directly.
Tom Hybiske
Bose Corporation
Framingham, MA
>
> I need to find the specifications of gerber language, would
> any of you know
> where I can get that information.
>
> TIA
>
>
> Dee Stover [log in to unmask]
> Associate Technician Design
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520-318-8489
> FAX 520-318-8303
>
>
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Date: Tue, 31 Jul 2001 21:30:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason Gregory <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason Gregory <[log in to unmask]>
Subject: Re: Solder Paste Measurements
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Howard, in the past, I was forced to use to use and invest in smaller, =
less expensive systems (I've since been lucky to have nice EXPENSIVE =
toys-teehee). One of my favorite tools has always been the benchtop =
Cyberoptics unit. I don't remember the model name, I'm sure it's on their =
website, or a price figure. But I do know it was cheaper than most =
systems.=20
The beauty of it is it shoots a laser at an angle, laser is viewable on =
monitor and is deflected by paste height. You line up the reference lines =
on the screen and get pretty true paste height. If your using 1:1 =
apertures or if you're doing aperaure reductions, you can calculate your =
volume.=20
Hope I've helped.
Jason Gregory
SCI Systems, Inc.
Software Specialist - NPI Group
(256)882-4107 x3728
[log in to unmask]
>>> [log in to unmask] 07/31/01 11:49 AM >>>
Hi Howard,
I've always found measuring solder paste volume to be very difficult. Yes,
numbers can be generated, but even taking large amounts of data doesn't
guarantee the correct impression. Generally, regardless of equipment used,
the best results one can hope for are for trends, which at best could be
described to be of the order of -1 or +1 from true. It's not a bad thing =
to
try but don't expect absolute results.
Best regards,
Andrew Hoggan
BBA Associates Ltd
www.bba-associates.ltd
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: 31 July 2001 14:47
To: [log in to unmask]
Subject: [TN] Solder Paste Measurements
Dear Technetters,
My question is: how do you measure solder paste height and volume
accurately? My situation is with using the VisionMaster Model 150A, I am
having trouble obtaining reasonably accurate measurements. The VisionMaste=
r
is a small bench topsystem that uses a template consisting of a "region of
interest" (the solder paste), and reference regions (the areas on each =
side
of the pad). Because there are inconsistencies in the PCB (HASL finish),
like raised areas from traces, valleys surrounding the pad, and
irregularities in the solder mask, the readings I get cannot possibly be
true. Many times the measured readings for weighted average height are =
over
7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The
process specifics are Multicore NC-40 paste, shore 94-97 polyurethane
blades, DEK 265 Infinity, and correct squeegee pressures, print gap, etc..
I believe the bricks are good, I just ca! n't use the measurements for SPC
as it shows the process to be out of control.
In theory, polyurethane blades should "scoop" if anything, leaving a
shorter brick than the stencil thickness. It seems logical to me that the
best way to obtain accurate measurements would be to use the pad as a
reference region and measure the height from the pad, but the VisionMaster
system does not allow me to do this. Does anyone have knowledge or
recommendations on what I can do here? How do the more expensive systems
measure solder paste? Oh yea, spending $$ on new equipment is not a real
good option at this point!
Thanks in advance for the assistance,
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 31 Jul 2001 23:19:02 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Solder Paste Measurements
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_17.194f45fc.2898cf26_boundary"
--part1_17.194f45fc.2898cf26_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi All!
Just want to "muddy the waters" a bit...
How many of you that use metal squeegees, and pretty much have your stencil
thickness down (as far as specifying thickness for a given pitch) have found
that it is really "crucial" to measure your paste thickness?
I for one, have found that when I spend the time and the money on equipment
to measure paste thickness, when using metal squeegee blades, and having a
solid set-up procedure, that I'm spending a bunch of time and money measuring
things that are always good...meaning that time could be spent better
elsewhere as long as you use metal squeegee blades, and have a good procedure
in place ensures that the printer is set-up correctly..which is not rocket
science...
Am I over simplifying things? It's always worked for me since the advent of
metal squeegees...I don't know how you can go wrong with a metal blade. Look
at the gerbers you're given, see if they match the pad geometries, and then
get the stencil made. Things are pretty straight forward after that...
-Steve Gregory-
> Howard, in the past, I was forced to use to use and invest in smaller, less
> expensive systems (I've since been lucky to have nice EXPENSIVE
> toys-teehee). One of my favorite tools has always been the benchtop
> Cyberoptics unit. I don't remember the model name, I'm sure it's on their
> website, or a price figure. But I do know it was cheaper than most systems.
> The beauty of it is it shoots a laser at an angle, laser is viewable on
> monitor and is deflected by paste height. You line up the reference lines
> on the screen and get pretty true paste height. If your using 1:1 apertures
> or if you're doing aperaure reductions, you can calculate your volume.
> Hope I've helped.
>
> Jason Gregory
> SCI Systems, Inc.
> Software Specialist - NPI Group
> (256)882-4107 x3728
> [log in to unmask]
>
>
> >>> [log in to unmask] 07/31/01 11:49 AM >>>
> Hi Howard,
>
> I've always found measuring solder paste volume to be very difficult. Yes,
> numbers can be generated, but even taking large amounts of data doesn't
> guarantee the correct impression. Generally, regardless of equipment used,
> the best results one can hope for are for trends, which at best could be
> described to be of the order of -1 or +1 from true. It's not a bad thing to
> try but don't expect absolute results.
>
> Best regards,
>
> Andrew Hoggan
> BBA Associates Ltd
> www.bba-associates.ltd
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
> Sent: 31 July 2001 14:47
> To: [log in to unmask]
> Subject: [TN] Solder Paste Measurements
>
>
>
> Dear Technetters,
>
> My question is: how do you measure solder paste height and volume
> accurately? My situation is with using the VisionMaster Model 150A, I am
> having trouble obtaining reasonably accurate measurements. The VisionMaster
> is a small bench topsystem that uses a template consisting of a "region of
> interest" (the solder paste), and reference regions (the areas on each side
> of the pad). Because there are inconsistencies in the PCB (HASL finish),
> like raised areas from traces, valleys surrounding the pad, and
> irregularities in the solder mask, the readings I get cannot possibly be
> true. Many times the measured readings for weighted average height are over
> 7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The
> process specifics are Multicore NC-40 paste, shore 94-97 polyurethane
> blades, DEK 265 Infinity, and correct squeegee pressures, print gap, etc..
> I believe the bricks are good, I just ca! n't use the measurements for SPC
> as it shows the process to be out of control.
>
> In theory, polyurethane blades should "scoop" if anything, leaving a
> shorter brick than the stencil thickness. It seems logical to me that the
> best way to obtain accurate measurements would be to use the pad as a
> reference region and measure the height from the pad, but the VisionMaster
> system does not allow me to do this. Does anyone have knowledge or
> recommendations on what I can do here? How do the more expensive systems
> measure solder paste? Oh yea, spending $$ on new equipment is not a real
> good option at this point!
>
> Thanks in advance for the assistance,
>
> Howard Watson
> Manufacturing Engineer
> AMETEK/Dixson
--part1_17.194f45fc.2898cf26_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi All!
<BR>
<BR>Just want to "muddy the waters" a bit...
<BR>
<BR>How many of you that use metal squeegees, and pretty much have your stencil
<BR>thickness down (as far as specifying thickness for a given pitch) have found
<BR>that it is really "crucial" to measure your paste thickness?
<BR>
<BR>I for one, have found that when I spend the time and the money on equipment
<BR>to measure paste thickness, when using metal squeegee blades, and having a
<BR>solid set-up procedure, that I'm spending a bunch of time and money measuring
<BR>things that are always good...meaning that time could be spent better
<BR>elsewhere as long as you use metal squeegee blades, and have a good procedure
<BR>in place ensures that the printer is set-up correctly..which is not rocket
<BR>science...
<BR>
<BR>Am I over simplifying things? It's always worked for me since the advent of
<BR>metal squeegees...I don't know how you can go wrong with a metal blade. Look
<BR>at the gerbers you're given, see if they match the pad geometries, and then
<BR>get the stencil made. Things are pretty straight forward after that...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Howard, in the past, I was forced to use to use and invest in smaller, less
<BR>expensive systems (I've since been lucky to have nice EXPENSIVE
<BR>toys-teehee). One of my favorite tools has always been the benchtop
<BR>Cyberoptics unit. I don't remember the model name, I'm sure it's on their
<BR>website, or a price figure. But I do know it was cheaper than most systems.
<BR>The beauty of it is it shoots a laser at an angle, laser is viewable on
<BR>monitor and is deflected by paste height. You line up the reference lines
<BR>on the screen and get pretty true paste height. If your using 1:1 apertures
<BR>or if you're doing aperaure reductions, you can calculate your volume.
<BR>Hope I've helped.
<BR>
<BR>Jason Gregory
<BR>SCI Systems, Inc.
<BR>Software Specialist - NPI Group
<BR>(256)882-4107 x3728
<BR>[log in to unmask]
<BR>
<BR>
<BR>>>> [log in to unmask] 07/31/01 11:49 AM >>>
<BR>Hi Howard,
<BR>
<BR>I've always found measuring solder paste volume to be very difficult. Yes,
<BR>numbers can be generated, but even taking large amounts of data doesn't
<BR>guarantee the correct impression. Generally, regardless of equipment used,
<BR>the best results one can hope for are for trends, which at best could be
<BR>described to be of the order of -1 or +1 from true. It's not a bad thing to
<BR>try but don't expect absolute results.
<BR>
<BR>Best regards,
<BR>
<BR>Andrew Hoggan
<BR>BBA Associates Ltd
<BR>www.bba-associates.ltd
<BR> -----Original Message-----
<BR> From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
<BR> Sent: 31 July 2001 14:47
<BR> To: [log in to unmask]
<BR> Subject: [TN] Solder Paste Measurements
<BR>
<BR>
<BR>
<BR> Dear Technetters,
<BR>
<BR> My question is: how do you measure solder paste height and volume
<BR>accurately? My situation is with using the VisionMaster Model 150A, I am
<BR>having trouble obtaining reasonably accurate measurements. The VisionMaster
<BR>is a small bench topsystem that uses a template consisting of a "region of
<BR>interest" (the solder paste), and reference regions (the areas on each side
<BR>of the pad). Because there are inconsistencies in the PCB (HASL finish),
<BR>like raised areas from traces, valleys surrounding the pad, and
<BR>irregularities in the solder mask, the readings I get cannot possibly be
<BR>true. Many times the measured readings for weighted average height are over
<BR>7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The
<BR>process specifics are Multicore NC-40 paste, shore 94-97 polyurethane
<BR>blades, DEK 265 Infinity, and correct squeegee pressures, print gap, etc..
<BR>I believe the bricks are good, I just ca! n't use the measurements for SPC
<BR>as it shows the process to be out of control.
<BR>
<BR> In theory, polyurethane blades should "scoop" if anything, leaving a
<BR>shorter brick than the stencil thickness. It seems logical to me that the
<BR>best way to obtain accurate measurements would be to use the pad as a
<BR>reference region and measure the height from the pad, but the VisionMaster
<BR>system does not allow me to do this. Does anyone have knowledge or
<BR>recommendations on what I can do here? How do the more expensive systems
<BR>measure solder paste? Oh yea, spending $$ on new equipment is not a real
<BR>good option at this point!
<BR>
<BR> Thanks in advance for the assistance,
<BR>
<BR> Howard Watson
<BR> Manufacturing Engineer
<BR> AMETEK/Dixson</FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_17.194f45fc.2898cf26_boundary--
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=========================================================================
Date: Thu, 19 Jul 2001 15:05:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Shiny vs. Dull
Mime-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
I have found that this is more dependent on method of reflow and flux. =20
Kathy=20
>>> [log in to unmask] 07/19/01 02:19PM >>>
Hello TechNetters,
Looking for confirmation that solder joints over gold platings will tend =
to
be duller than solder joints over HASL platings.
Thanks,
Craig
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bmZvcm1hdGlvbiwgb3IgY29udGFjdCBLZWFjaCBTYXNhbW9yaSBhdCBzYXNha29AaXBjLm9yZyBv
ciANCjg0Ny01MDktOTcwMCANCmV4dC41MzE1PEJSPi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLTxC
Uj48L0RJVj48L0JPRFk+PC9IVE1MPg0K
--=_A7FDC69E.4A2B47FF--
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Date: Thu, 19 Jul 2001 15:32:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: White residue from conformal coating
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Does MPK have the same health concerns as MEK?
*Dunno. The man in charge of our coating specification wants me to look
into MPK because it supposedly has a lower health risk than the
toluene/xylene that we currently use (by the carload). I have not looked
at MPK vs. MEK, but the chemistries are very similar. Whats a carbon atom
between friends?
Doug
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Date: Wed, 1 Aug 2001 11:50:07 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Solder Paste Measurements
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Technetters,
Having a solid set-up procedure (like Steve mentions) is the key issue =
here. But how about making proto's all the time, some of them hardly =
manufacturable, like flex-rigid boards without a carrier or boards with =
solderpads within 0.5 mm of the board-edges ? Setting up the machine =
means some improvisation then.....
For an engineer it's quite easy to see if set-up is incorrect, but for the =
average operator a height- measurement helps in identifying such a =
problem.=20
For average, flat and rigid boards I agree with Steve (as long as metal =
blades are used).
Howard: measuring a value a little higher then the stencil thickness is =
normal. Maybe someone else can give an explanation for this is, because I =
don't remember :-{
Kind regards,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> "Stephen R. Gregory" <[log in to unmask]> 08/01 5:19 am >>>
Hi All!
Just want to "muddy the waters" a bit...
How many of you that use metal squeegees, and pretty much have your =
stencil
thickness down (as far as specifying thickness for a given pitch) have =
found
that it is really "crucial" to measure your paste thickness?
I for one, have found that when I spend the time and the money on =
equipment
to measure paste thickness, when using metal squeegee blades, and having a
solid set-up procedure, that I'm spending a bunch of time and money =
measuring
things that are always good...meaning that time could be spent better
elsewhere as long as you use metal squeegee blades, and have a good =
procedure
in place ensures that the printer is set-up correctly..which is not rocket
science...
Am I over simplifying things? It's always worked for me since the advent =
of
metal squeegees...I don't know how you can go wrong with a metal blade. =
Look
at the gerbers you're given, see if they match the pad geometries, and =
then
get the stencil made. Things are pretty straight forward after that...
-Steve Gregory-
> Howard, in the past, I was forced to use to use and invest in smaller, =
less
> expensive systems (I've since been lucky to have nice EXPENSIVE
> toys-teehee). One of my favorite tools has always been the benchtop
> Cyberoptics unit. I don't remember the model name, I'm sure it's on =
their
> website, or a price figure. But I do know it was cheaper than most =
systems.
> The beauty of it is it shoots a laser at an angle, laser is viewable on
> monitor and is deflected by paste height. You line up the reference =
lines
> on the screen and get pretty true paste height. If your using 1:1 =
apertures
> or if you're doing aperaure reductions, you can calculate your volume.
> Hope I've helped.
>
> Jason Gregory
> SCI Systems, Inc.
> Software Specialist - NPI Group
> (256)882-4107 x3728
> [log in to unmask]
>
>
> >>> [log in to unmask] 07/31/01 11:49 AM >>>
> Hi Howard,
>
> I've always found measuring solder paste volume to be very difficult. =
Yes,
> numbers can be generated, but even taking large amounts of data doesn't
> guarantee the correct impression. Generally, regardless of equipment =
used,
> the best results one can hope for are for trends, which at best could be
> described to be of the order of -1 or +1 from true. It's not a bad =
thing to
> try but don't expect absolute results.
>
> Best regards,
>
> Andrew Hoggan
> BBA Associates Ltd
> www.bba-associates.ltd=20
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
> Sent: 31 July 2001 14:47
> To: [log in to unmask]
> Subject: [TN] Solder Paste Measurements
>
>
>
> Dear Technetters,
>
> My question is: how do you measure solder paste height and volume
> accurately? My situation is with using the VisionMaster Model 150A, I =
am
> having trouble obtaining reasonably accurate measurements. The =
VisionMaster
> is a small bench topsystem that uses a template consisting of a "region =
of
> interest" (the solder paste), and reference regions (the areas on each =
side
> of the pad). Because there are inconsistencies in the PCB (HASL =
finish),
> like raised areas from traces, valleys surrounding the pad, and
> irregularities in the solder mask, the readings I get cannot possibly be
> true. Many times the measured readings for weighted average height are =
over
> 7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The
> process specifics are Multicore NC-40 paste, shore 94-97 polyurethane
> blades, DEK 265 Infinity, and correct squeegee pressures, print gap, =
etc..
> I believe the bricks are good, I just ca! n't use the measurements for =
SPC
> as it shows the process to be out of control.
>
> In theory, polyurethane blades should "scoop" if anything, leaving a
> shorter brick than the stencil thickness. It seems logical to me that =
the
> best way to obtain accurate measurements would be to use the pad as a
> reference region and measure the height from the pad, but the VisionMaste=
r
> system does not allow me to do this. Does anyone have knowledge or
> recommendations on what I can do here? How do the more expensive =
systems
> measure solder paste? Oh yea, spending $$ on new equipment is not a =
real
> good option at this point!
>
> Thanks in advance for the assistance,
>
> Howard Watson
> Manufacturing Engineer
> AMETEK/Dixson
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=========================================================================
Date: Thu, 19 Jul 2001 15:50:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Keach Sasamori <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: OT- Virus Warning
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
We've had some mail today that contains a virus. It is known as W32/SirCam@=
mm or Backdoor.SirCam. Not from Technet (because no attachments are =
allowed), but just wanted to pass it on.
The subject will be random, but matches the attachment subject.
The body of the message is very simple. Just 3 or 4 lines. Something to =
the effect of:
Hi How are you
I send you this file in order to have your advice
----- OR--------
I hope you can help me with this file that I send
----- OR--------
I hope you like the file that I sendo you
----- OR--------
This is the file with the information that you ask for
The attachment has a familiar extension (xls, doc, etc) followed by any of =
the following (.vbs, .pif, .com, .bat) and is generated from a recently =
used file on the infected person's system.
The virus sends out the message and attachment to addresses from the =
e-mail client. The damage done varies from case to case.=20
You may get more info from: http://www.symantec.com/avcenter/venc/data/w32.=
[log in to unmask] which also has a fix for infected systems.
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=========================================================================
Date: Thu, 19 Jul 2001 14:18:47 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hans Shin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hans Shin <[log in to unmask]>
Subject: Re: White residue from conformal coating
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Overexposure to both MEK and MPK will give headaches too...and eye and nose irritation...
Hans Shin
PTL
-----Original Message-----
From: Hans Hinners [SMTP:[log in to unmask]]
Sent: Thursday, July 19, 2001 1:47 PM
To: [log in to unmask]
Subject: Re: [TN] White residue from conformal coating
Only reason I ask is because, I had to get extra special permission to use
some MEK (100%) to thin out a potting compound when I was at Robins.
Reducing toluene & xylene exposure is very commendable - nothing like that
solvent headache killing brain cells.
H
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, July 19, 2001 1:32 PM
To: TechNet E-Mail Forum.; Hans Hinners
Subject: Re: [TN] White residue from conformal coating
Does MPK have the same health concerns as MEK?
*Dunno. The man in charge of our coating specification wants me to look
into MPK because it supposedly has a lower health risk than the
toluene/xylene that we currently use (by the carload). I have not looked
at MPK vs. MEK, but the chemistries are very similar. Whats a carbon atom
between friends?
Doug
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=========================================================================
Date: Thu, 19 Jul 2001 16:30:50 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: So long & thanks for all the fish
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_DD87BC88.A2C3AF14"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_DD87BC88.A2C3AF14
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
Sorry for the inconvenience......(Hitchhikers guide reference, for those =
wondering)
Kathy
--=_DD87BC88.A2C3AF14
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY style="FONT: 10pt Haettenschweiler; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Sorry for the inconvenience......(Hitchhikers guide reference, for those
wondering)</DIV>
<DIV> </DIV>
<DIV>Kathy</DIV></BODY></HTML>
--=_DD87BC88.A2C3AF14--
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Date: Thu, 19 Jul 2001 16:35:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barbara Burcham <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barbara Burcham <[log in to unmask]>
Subject: Re: So long & thanks for all the fish
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hans...sounds like you are headed into the Deep South. Where will you =
be
living?
Barbara
-----Original Message-----
From: Hans Hinners [mailto:[log in to unmask]]
Sent: Thursday, July 19, 2001 3:55 PM
To: [log in to unmask]
Subject: [TN] So long & thanks for all the fish
Hey Doug & all,
Boy, do I have news for everybody.
Today is my last day in the board business and the private world at =
least
for now. <sigh - I hate good byes> I intend to sign up for Tech Net =
once I
get settled in the new digs. Who knows? I might end up on the other =
side
of the board industry.
My fianc=E9e couldn't find a job out in San Diego before the economy =
tanked .
. . so I'm heading back to the military world (civilian Air Force). =
Only
this time I'll be an Electronics Engineer working on either the HH 60
Helicopter or the C-130 gunship.
It's back to deep fried everything (catfish, sweet potatoes, pickles, =
ice
cream) & sweet tea. Oh and really cheap gas!
If there are any Engineers out there who want to live in sunny San =
Diego
give me a shout!
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Process Engineer
Toppan Electronics, Inc.
770 Miramar Road
San Diego, CA 92126
(858) 695 - 2222 ext. 241
(858) 695 - 6823 fax
[log in to unmask]
------------------------------------------------------------------------=
----
-----
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in
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E-mail Archives
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additional
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847-509-9700
ext.5315
------------------------------------------------------------------------=
----
-----
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Date: Fri, 20 Jul 2001 07:43:55 +1000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Colin Weber <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Colin Weber <[log in to unmask]>
Subject: Re: Bow & Twist
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Peter,
We are designing the board to IPC specifications for scientific
instrumentation.
There is no special case for these designs. I don't have a problem with bow
and twist
as I haven't designed the boards yet. My question is more directed to how
to avoid
the issue if I want to design a large PCB.
Apart from stiffeners and the like I am specifically wondering how thick I
need to make
a PCB if I am going to be placing fine pitch devices and/or PBGAs on them.
If I were
to go with 2.4mm I have EMI stackup and aspect ratio concerns, but feel
comfortable
the board will be more rigid. I could and would prefer to step down in
thickness but do
not have a feel for how the board would fair during handling and assembly.
I am talking about 14 to 15 x 9 to 10 inch board sizes for processor
designs. An
obvious solution is to split the PCB up into two boards, but I do not have
that luxury.
I was just curios if there are any guidelines or figures fro bow & twist
with respect to
size versus thickness?
At 02:44 PM 19/07/2001 +0800, you wrote:
>Much of the bow and twist these days is down to the choice of material used
>for the substrate coupled with 'balance' in the board design and ultimately
>on the capability of the fabrication process.
>
>If you have heavy planes in the board, make sure they're distributed evenly
>throughout the layers, otherwise any good PCB Fab worth his salt will keep
>any bow and twist within the bounds of the usual specs. It used ot be that
>the thicker the board was, the more rigid it was and the less inclined it
>was to warping. These days, more than 20 mils bow or twist on a 63 mil
>thick board measuring 9 x 6 inches is unusual.
>
>Are you designing boards to be made to MIL-PRF-55110, to an IPC spec or to
>something more commercial?
>
>Pete Duncan
>
>
>
>
> <colin.weber@VARI To: [log in to unmask]
>
> 07/19/01 12:18 PM
>
>Folks,
>
>Is there a method of determining the maximum permissible size of two board
>types?
>a) A SMT PCB containing Fine pitch QFP devices
>b) A SMT PCB containing PBGA 388pin 1.27mm pitch & Fine pitch QFPs
>
>with respect to Bow and Twist.
>
>I am interested in how the thickness of the board relates to maximum bow
>and twist.
>I'd like to determine this before I design the layout, rather than find out
>it is wrong
>after performing the tests of IPC-6012A, IPC-TM-650 2.4.22.
>
>Regards,
>
>Colin Weber
Regards,
Colin Weber
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Date: Thu, 19 Jul 2001 14:52:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: X-Ray Laminography Test
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I am looking for a lab that provides X-Ray Laminography services. I need to
evaluate the solder joints on some BGAs and I was wondering what would give
a complete 3D analysis of the solder joint. Is there any lab that provides
Laminography services? My company is located in Phoenix, Arizona.
Any information would be appreciated.
Jorge Rodriguez
Process Engineer
Varian, Inc.
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Date: Mon, 13 Aug 2001 08:57:51 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: PCB Moisture Absorption
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Karen,
In my former salt mine, where we used organic boards, it was standard
practice to bake the bare boards for 2 hours at 90 deg C to drive off
absorbed moisture prior to assembly. Thereafter, the boards were kept in
low humidity or nitrogen cabinets between assembly operations until after
conformal coating.
How are your boards packed when they arrive with you from the
manufacturer? I would expect them to be in sealed bags with desiccant, and
they should be left that way (or resealed immediately after inspection in
vacuum bags with desiccant) until you're ready to assemble them,
preferrably in the low humidity cabinet. How long are you leaving the
boards on the shop floor after baking? You should try and arrange matters
so that they're not baked until they're required, and thereafter used
immediately.
Regards
Pete Duncan
Karen Walters
<KWalters@BTU To: [log in to unmask]
.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: Subject: [TN] PCB Moisture Absorption
TechNet
<[log in to unmask]
ORG>
08/09/01
02:39 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Karen Walters
I am trying to solve the problem of cracking inside a printed
circuit board due to moisture absorption, temperature in the oven and the
thermal gradient observed on the board. After the drying process, the
boards are left outside
in the manufacturing area, but due to the environment they are absorbing
moisture again. I would like to know which products would fit
better(sealed
bags,vacuum bag,with/without desiccant,low humidity or nitrogen filled
storage cabinets...). Also has anyone done a study on moisture absorption
in a PCB under different environment conditions, and baking requirements
for
different environmental conditions?
If you have any data, please advise.
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Date: Thu, 19 Jul 2001 15:19:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Chuck Brummer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Chuck Brummer <[log in to unmask]>
Subject: Re: ICD
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------C41DBD1EAB03DCA8B0C75832"
--------------C41DBD1EAB03DCA8B0C75832
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Wayne,
My past recalls that for that test copper elongation was much more
important than copper plate thickness. I think you want to be greater
than 12% elongation when you plate, then one mil to one ounce is
probably enough.
Chuck Brummer
Acuson
Wayne Martin wrote:
> Need some help!We are trying to pass the IPC TM-650 2.4.36 Rework
> simulation test. We are having ICD in trying to pass the test. We pass
> the solder float test.We run a direct plate (palladium) line. We have
> platted anywhere from 1 mil. of copper in the through holes all the
> way to 2.5 mil. of copper in the holes and still fail the test.Looking
> for any help that anyone can give me.Wayne MartinElectronic Service
> and Design
--------------C41DBD1EAB03DCA8B0C75832
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<body bgcolor="#FFFFFF">
Wayne,
<p>My past recalls that for that test copper elongation was much more important
than copper plate thickness. I think you want to be greater than
12% elongation when you plate, then one mil to one ounce is probably enough.
<p>Chuck Brummer
<br>Acuson
<p>Wayne Martin wrote:
<blockquote TYPE=CITE><style></style>
<font face="Arial"><font size=-1>Need
some help!</font></font><font face="Arial"><font size=-1>We are trying
to pass the IPC TM-650 2.4.36 Rework simulation test. We are having ICD
in trying to pass the test. We pass the solder float test.</font></font><font face="Arial"><font size=-1>We
run a direct plate (palladium) line. We have platted anywhere from 1 mil.
of copper in the through holes all the way to 2.5 mil. of copper in the
holes and still fail the test.</font></font><font face="Arial"><font size=-1>Looking
for any help that anyone can give me.</font></font><font face="Arial"><font size=-1>Wayne
Martin</font></font><font face="Arial"><font size=-1>Electronic Service
and Design</font></font></blockquote>
</body>
</html>
--------------C41DBD1EAB03DCA8B0C75832--
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Date: Wed, 1 Aug 2001 08:34:47 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Kasprzak, Bill (sys) USX" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Kasprzak, Bill (sys) USX" <[log in to unmask]>
Subject: Process Problem vs Board Problem
MIME-Version: 1.0
Content-Type: text/plain
Technetters'
I've recently run into a problem with Wavesoldering some circuit boards
where I am having problems getting topside solder joints. The process that
I'm running has the topside of the board at 195-200 F just prior to the
solder wave. My conveyor speed is 4.0 fpm. My fluxer is a spray fluxer. The
board is a .062 - 6 layer board that has an aluminum heat sink on it. I feel
that my process is set correctly.
The original process that previously used on these boards was very
successful when we used an OA water soluble flux. This process was on that I
qualified many years ago to J-Std-001A for Class 3 assemblies.
On these circuit boards, I'm trying to use a No Clean Lo Activity level flux
that is water washable. Because I have new equipment for wavesoldering, I
was hoping to not have to do a re-qualification process for our level 3
assemblies. Because our new equipment has much better controls than our old
equipment I thought that it would be easy to solder these boards with an LO
active flux. Well, my initial pass has been a disaster so far. There are
three pictures that I'm looking for comments on. They are located on Steve's
Webpage at http://stevezeva.homestead.com. (A thousand thanks go out to
Steve Gregory for providing a site for posting the pictures.) Two of the
pictures, called Bare Pad and Bare Pad2 show a condition that I can describe
but I don't know if this condition has a name. In those pictures, there is a
heavier coat of solder on the pad, but it seems to form a concentric ring on
the pad.The extremities of the pads, both toward the outside and the inside,
show a tinned surface but it appears to be much thinner. To me, it seems
like these thin areas do not readily solder. It seems like this thin area is
barrier that can only be overcome with a very strong OA flux. This may
explain why I did not have a problem before. The other picture shows another
condition that I see in various places on the bare board where there are
protrusions on the inside of the PTH's. This appears to be trapped volitiles
that were being expulsed during the HASL process.
I'm trying to determine if I have a board problem or a process problem.
Is it unreasonable for me to think that this board can be soldered with a
no-clean (but water washable) LO activity level flux?
Any help or comments would be greatly appreciated.
Bill Kasprzak
Moog Inc., Electronic Assembly Engineering
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Date: Mon, 13 Aug 2001 08:05:18 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Edward Szpruch <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: horizontal lines for flex innerlayers- oxide substitution
MIME-Version: 1.0
Content-Type: text/plain
Hi Technetters,
I need opinion from people that installed such lines about their experience.
We specified the capability of the line to process flexible innerlayers and
polyimide thin innerlayers ( 50 microns dielectric,17/17 micron copper) with
signal circuitry without leaders as well as thicker rigid innerlayers ( up
to 1 mm ) with ground areas with uniform color of treated copper.
I am very interested in actual results.
I will very appreciate also private mails if there is negative experience
and someone hestitate to send on the net the names of suppliers.
Edward Szpruch
Eltek , Manager of Process Engineering
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
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Date: Fri, 20 Jul 2001 08:42:02 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: So long & thanks for all the fish
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=========================================================================
Date: Wed, 1 Aug 2001 09:40:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Woelfel, Tim" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Woelfel, Tim" <[log in to unmask]>
Subject: Re: Board layout service
MIME-Version: 1.0
Content-Type: text/plain
Try Plexus in Neenah, WI.
> -----Original Message-----
> From: West, Jim [SMTP:[log in to unmask]]
> Sent: Wednesday, August 01, 2001 9:31 AM
> To: [log in to unmask]
> Subject: [TN] Board layout service
>
> Hi,
>
> I'm in need of someone that can layout a new PCB's. I'm located in the
> Columbus Ohio area, and would like someone close to this area if possible.
> Please e-mail me offline if you know of someone that can help.
>
> Thanks,
>
> Jim
>
> --------------------------------------------------------------------------
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Date: Fri, 20 Jul 2001 09:16:44 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Bow & Twist
MIME-Version: 1.0
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Colin,
I haven't come across any such figures, and I doubt that they would have
been very meaningful if I had, as there are too many variables in terms of
material choice and choice of fab house to pin numbers to. I suggest you
determine what flatness you need and the materials you want to use and then
go talk to fab houses for advice on how possible your requirements are.
My view is that, if you're using BGA's, I would prefer a thinner board to a
thicker one from a manufacturing point of view. It takes a much longer time
to get BGA contacts up to soldering temperature compared with most other
components where the leads stick out the sides. A thicker board means an
even longer dwell time at high temperature, which to me is a risky time for
a board. Peak soldering temperatures, especially where BGA's are involved,
are pretty close to the max case temperatures of a lot of components, and
if you increase the length of time components cases are exposed to high
temps just to heat up a thick board, you may induce internal damage.
You can put the boards in support jigs during processing until the
stiffeners are fitted.
Pete Duncan
Colin Weber
<colin.weber@vari To: "TechNet E-Mail Forum." <[log in to unmask]>, DUNCAN
aninc.com> Peter/Asst Prin Engr/ST Aero/ST Group@ST Domain
cc:
07/20/01 05:43 AM Subject: Re: [TN] Bow & Twist
Peter,
We are designing the board to IPC specifications for scientific
instrumentation.
There is no special case for these designs. I don't have a problem with bow
and twist
as I haven't designed the boards yet. My question is more directed to how
to avoid
the issue if I want to design a large PCB.
Apart from stiffeners and the like I am specifically wondering how thick I
need to make
a PCB if I am going to be placing fine pitch devices and/or PBGAs on them.
If I were
to go with 2.4mm I have EMI stackup and aspect ratio concerns, but feel
comfortable
the board will be more rigid. I could and would prefer to step down in
thickness but do
not have a feel for how the board would fair during handling and assembly.
I am talking about 14 to 15 x 9 to 10 inch board sizes for processor
designs. An
obvious solution is to split the PCB up into two boards, but I do not have
that luxury.
I was just curios if there are any guidelines or figures fro bow & twist
with respect to
size versus thickness?
At 02:44 PM 19/07/2001 +0800, you wrote:
>Much of the bow and twist these days is down to the choice of material
used
>for the substrate coupled with 'balance' in the board design and
ultimately
>on the capability of the fabrication process.
>
>If you have heavy planes in the board, make sure they're distributed
evenly
>throughout the layers, otherwise any good PCB Fab worth his salt will keep
>any bow and twist within the bounds of the usual specs. It used ot be that
>the thicker the board was, the more rigid it was and the less inclined it
>was to warping. These days, more than 20 mils bow or twist on a 63 mil
>thick board measuring 9 x 6 inches is unusual.
>
>Are you designing boards to be made to MIL-PRF-55110, to an IPC spec or to
>something more commercial?
>
>Pete Duncan
>
>
>
>
> <colin.weber@VARI To: [log in to unmask]
>
> 07/19/01 12:18 PM
>
>Folks,
>
>Is there a method of determining the maximum permissible size of two board
>types?
>a) A SMT PCB containing Fine pitch QFP devices
>b) A SMT PCB containing PBGA 388pin 1.27mm pitch & Fine pitch QFPs
>
>with respect to Bow and Twist.
>
>I am interested in how the thickness of the board relates to maximum bow
>and twist.
>I'd like to determine this before I design the layout, rather than find
out
>it is wrong
>after performing the tests of IPC-6012A, IPC-TM-650 2.4.22.
>
>Regards,
>
>Colin Weber
Regards,
Colin Weber
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=========================================================================
Date: Fri, 20 Jul 2001 09:26:23 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Gerber specification
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dee,
Try looking up IPC-D-350. I don't have a copy myself, but was given this
number recently as the spec for the Gerber format. It might help some.
Pete Duncan
"Hybiske,
Tom" To: [log in to unmask]
<Tom_Hybiske@ cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
BOSE.COM> Subject: Re: [TN] Gerber specification
Sent by:
TechNet
<[log in to unmask]
ORG>
07/20/01
02:43 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Hybiske,
Tom"
Gerber Scientific has a publication explaining the RS274X language.
Contact
them directly.
Tom Hybiske
Bose Corporation
Framingham, MA
>
> I need to find the specifications of gerber language, would
> any of you know
> where I can get that information.
>
> TIA
>
>
> Dee Stover [log in to unmask]
> Associate Technician Design
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520-318-8489
> FAX 520-318-8303
>
>
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=========================================================================
Date: Thu, 19 Jul 2001 21:33:56 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Shiny vs. Dull
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_f5.cb170d2.2888e484_boundary"
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Content-Transfer-Encoding: 7bit
Hi Craig!
This is true from my experience when using a standard 63/37 solder. I do know
one way to make them look better, I'm not a metallurgist, and I can't explain
why, but if you use a 2% silver solder the joints are noticably smoother and
shinier...this was told to me a long, long time ago. Ever since then when I'm
soldering to flash gold, I'll use a SN62/ PB36/ AG2 solder paste..
Maybe somebody like Werner can tell us why using a 2% silver solder makes the
joints look smoother and shinier...
-Steve Gregory-
> Hello TechNetters,
>
> Looking for confirmation that solder joints over gold platings will tend to
> be duller than solder joints over HASL platings.
>
> Thanks,
> Craig
>
--part1_f5.cb170d2.2888e484_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Craig!
<BR>
<BR>This is true from my experience when using a standard 63/37 solder. I do know
<BR>one way to make them look better, I'm not a metallurgist, and I can't explain
<BR>why, but if you use a 2% silver solder the joints are noticably smoother and
<BR>shinier...this was told to me a long, long time ago. Ever since then when I'm
<BR>soldering to flash gold, I'll use a SN62/ PB36/ AG2 solder paste..
<BR>
<BR>Maybe somebody like Werner can tell us why using a 2% silver solder makes the
<BR>joints look smoother and shinier...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello TechNetters,
<BR>
<BR>Looking for confirmation that solder joints over gold platings will tend to
<BR>be duller than solder joints over HASL platings.
<BR>
<BR>Thanks,
<BR>Craig
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_f5.cb170d2.2888e484_boundary--
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Date: Thu, 19 Jul 2001 22:10:01 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: So long & thanks for all the fish
MIME-Version: 1.0
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boundary="part1_d6.970871d.2888ecf9_boundary"
--part1_d6.970871d.2888ecf9_boundary
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Hey Hans!!
You forgot about a couple of other things too...affordable housing, no=20
rolling blackouts, and no 12-lane freeways that turn into parking lots twice=
=20
a day!!
But you'll have to get back dealing with the humidity...here in Oklahoma it'=
s=20
been like a 'friggen sauna...getting over a 100-degrees, 75% humidity, heat=20
index is like 115-degrees, and that's in the shade!! They're saying this=20
gonna go on for at least another week or so!! (pant, pant, pant...)
We'll see you...have a good trip!!
-Steve Gregory-
> Hey Doug & all,
>=20
> Boy, do I have news for everybody.
>=20
> Today is my last day in the board business and the private world at least
> for now. <sigh - I hate good byes> I intend to sign up for Tech Net once=20=
I
> get settled in the new digs. Who knows? I might end up on the other side
> of the board industry.
>=20
> My fianc=E9e couldn't find a job out in San Diego before the economy tanke=
d .
> . . so I'm heading back to the military world (civilian Air Force). Only
> this time I'll be an Electronics Engineer working on either the HH 60
> Helicopter or the C-130 gunship.
>=20
> It's back to deep fried everything (catfish, sweet potatoes, pickles, ice
> cream) & sweet tea. Oh and really cheap gas!
>=20
> If there are any Engineers out there who want to live in sunny San Diego
> give me a shout!
>=20
> Hans
>=20
--part1_d6.970871d.2888ecf9_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2>Hey Hans!!
<BR>
<BR>You forgot about a couple of other things too...affordable housing, no=20
<BR>rolling blackouts, and no 12-lane freeways that turn into parking lots t=
wice=20
<BR>a day!!
<BR>
<BR>But you'll have to get back dealing with the humidity...here in Oklahoma=
it's=20
<BR>been like a 'friggen sauna...getting over a 100-degrees, 75% humidity, h=
eat=20
<BR>index is like 115-degrees, and that's in the shade!! They're saying this=
=20
<BR>gonna go on for at least another week or so!! (pant, pant, pant...)
<BR>
<BR>We'll see you...have a good trip!!
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hey Doug & all,
<BR>
<BR>Boy, do I have news for everybody.
<BR>
<BR>Today is my last day in the board business and the private world at leas=
t
<BR>for now. <sigh - I hate good byes> I intend to sign up for T=
ech Net once I
<BR>get settled in the new digs. Who knows? I might end up on th=
e other side
<BR>of the board industry.
<BR>
<BR>My fianc=E9e couldn't find a job out in San Diego before the economy tan=
ked .
<BR>. . so I'm heading back to the military world (civilian Air Force)=
. Only
<BR>this time I'll be an Electronics Engineer working on either the HH 60
<BR>Helicopter or the C-130 gunship.
<BR>
<BR>It's back to deep fried everything (catfish, sweet potatoes, pickles, ic=
e
<BR>cream) & sweet tea. Oh and really cheap gas!
<BR>
<BR>If there are any Engineers out there who want to live in sunny San Diego
<BR>give me a shout!
<BR>
<BR>Hans
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR></FONT></HTML>
--part1_d6.970871d.2888ecf9_boundary--
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=========================================================================
Date: Thu, 19 Jul 2001 21:20:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
=?US-ASCII?Q?cscholbe?= <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: =?US-ASCII?Q?cscholbe?= <[log in to unmask]>
Subject: =?US-ASCII?Q?ERROR?=
Content-Type: text/plain; charset="US-ASCII"
I'm out from 7/20 to 7/24. Back on 7/25. Please contact Bob Corbey or Wendi Boger in my absence. Thanks!
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Date: Fri, 20 Jul 2001 14:55:09 +1000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Van Hoang Dinh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Van Hoang Dinh <[log in to unmask]>
Subject: In-line process
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0005_01C1112B.F8E97580"
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------=_NextPart_000_0005_01C1112B.F8E97580
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Hi TechNet,
We are going to implement IN-LINE process. Any recommends or ideas would =
help for me.
Thanks In Advance
Van
------=_NextPart_000_0005_01C1112B.F8E97580
Content-Type: text/html;
charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2314.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hi TechNet,</FONT></DIV>
<DIV><FONT size=3D2>We are going to implement IN-LINE process. Any =
recommends or=20
ideas would help for me.</FONT></DIV>
<DIV><FONT size=3D2>Thanks In Advance</FONT></DIV>
<DIV><FONT size=3D2>Van</FONT></DIV></BODY></HTML>
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Date: Mon, 13 Aug 2001 13:41:42 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Searching for reflow oven manufacturer or user
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Hi Jim!
ABW ovens are now sold by Manix. Go to:
http://www.manixmfg.com/reflow.htm
The latest TT-5 has windows software and looks like it has a neat flat-panel
display...
-Steve Gregory-
> Hi,
>
> Anybody know if ABW Systems Corporation is still in business? They produced
> a reflow oven ABW model TT-5 for Zevatech back in 1994. Or, does anybody
> use the TT-5 oven currently? I'm in need of assistance on getting the one
> we recently purchased up an running.
>
> Thanks,
>
> Jim West
> Manufacturing Engineer
>
> Nexergy Inc.
> 1909 Arlingate Lane
> Columbus, Ohio 43228
> Ph. 614-351-6216
> Fax. 614-324-1979
>
> http://www.nexergy.com
>
--part1_85.e7d189c.28a96b56_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jim!
<BR>
<BR>ABW ovens are now sold by Manix. Go to:
<BR>
<BR>http://www.manixmfg.com/reflow.htm
<BR>
<BR>The latest TT-5 has windows software and looks like it has a neat flat-panel
<BR>display...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi,
<BR>
<BR>Anybody know if ABW Systems Corporation is still in business? They produced
<BR>a reflow oven ABW model TT-5 for Zevatech back in 1994. Or, does anybody
<BR>use the TT-5 oven currently? I'm in need of assistance on getting the one
<BR>we recently purchased up an running.
<BR>
<BR>Thanks,
<BR>
<BR>Jim West
<BR>Manufacturing Engineer
<BR>
<BR>Nexergy Inc.
<BR>1909 Arlingate Lane
<BR>Columbus, Ohio 43228
<BR>Ph. 614-351-6216
<BR>Fax. 614-324-1979
<BR>
<BR>http://www.nexergy.com
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_85.e7d189c.28a96b56_boundary--
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Date: Mon, 13 Aug 2001 12:26:47 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Roger Hammond <[log in to unmask]>
Subject: FDA approval
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Dear Techneters,
I work for a Printed Circuit Fabricator in the U.K.and one of our
customers, a Printed Circuit Assembler has been approached by an OEM
that produces medical equipment. This OEM has FDA approval for his
product. The question is, is it the equipment that is FDA approved or
does it transfer down the line to the assembler and printed circuit
manufacturer in similar fashion to UL recognition. If it transfers down
the line how does one go about obtaining the approval.
Thank you in advance
Roger Hammond
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Date: Wed, 1 Aug 2001 15:51:44 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Re: Solder Paste Measurements
MIME-Version: 1.0
Content-Type: multipart/alternative; boundary="=_alternative 006CE2A087256A9B_="
This is a multipart message in MIME format.
--=_alternative 006CE2A087256A9B_=
Content-Type: text/plain; charset="us-ascii"
Steve,
Thanks for the sound advice. I agree that a bullet-proof process and
set-up procedure will produce the results necessary for high yield and
that metal blades will help reduce variation. The situation I have seen
here is that metal blades can, and will, get damaged in our facility (I've
even seen poly blades get nicked!). In addition, I have seen several
stencils get damaged, through careless handling or otherwise. The result
is inconsistent print volume, leading to solder defects. The one area
where I can't completely reduce variation is with operator skill, or
diligence in following common sense practices. For example, soon after I
got here I was troubled by the fact that boards were allowed to slide down
a ramp at the end of reflow, sliding into each other and piling up.
Unbelievably, I was questioned by some as to "why" I requested an
operator at the end of reflow at all times. Some glued on components were
actually being sheared off.
The main problem we face here in arid western Colorado is the huge swing
in RH and temperatures (swamp cooling in summer & gas heat in winter), and
the very narrow process window of our current paste (Multicore NC-40). In
the winter, RH can be around 8% at 70 - 76 deg F, and in the summer RH is
up to 70% with temps up to 83 F. We have a significant problem with paste
dry out on the boards and in the stencil apertures - sometimes a delay of
less than 20 minutes can cause a problem. Many of the current solder
pastes may eliminate this problem, and I am working on changing the paste
- once I can get through the customer approvals and all that non-technical
stuff. Until we can get the process in control, we must monitor the
prints and reduce every variation that we can. Any feedback out there on
enclosed printheads, ie ProFlow to help with our indoor climate problem?
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
"Stephen R. Gregory" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
07/31/01 09:19 PM
Please respond to "TechNet E-Mail Forum."; Please respond to SteveZeva
To: [log in to unmask]
cc:
Subject: Re: [TN] Solder Paste Measurements
Hi All!
Just want to "muddy the waters" a bit...
How many of you that use metal squeegees, and pretty much have your
stencil
thickness down (as far as specifying thickness for a given pitch) have
found
that it is really "crucial" to measure your paste thickness?
I for one, have found that when I spend the time and the money on
equipment
to measure paste thickness, when using metal squeegee blades, and having a
solid set-up procedure, that I'm spending a bunch of time and money
measuring
things that are always good...meaning that time could be spent better
elsewhere as long as you use metal squeegee blades, and have a good
procedure
in place ensures that the printer is set-up correctly..which is not rocket
science...
Am I over simplifying things? It's always worked for me since the advent
of
metal squeegees...I don't know how you can go wrong with a metal blade.
Look
at the gerbers you're given, see if they match the pad geometries, and
then
get the stencil made. Things are pretty straight forward after that...
-Steve Gregory-
Howard, in the past, I was forced to use to use and invest in smaller,
less
expensive systems (I've since been lucky to have nice EXPENSIVE
toys-teehee). One of my favorite tools has always been the benchtop
Cyberoptics unit. I don't remember the model name, I'm sure it's on their
website, or a price figure. But I do know it was cheaper than most
systems.
The beauty of it is it shoots a laser at an angle, laser is viewable on
monitor and is deflected by paste height. You line up the reference lines
on the screen and get pretty true paste height. If your using 1:1
apertures
or if you're doing aperaure reductions, you can calculate your volume.
Hope I've helped.
Jason Gregory
SCI Systems, Inc.
Software Specialist - NPI Group
(256)882-4107 x3728
[log in to unmask]
>>> [log in to unmask] 07/31/01 11:49 AM >>>
Hi Howard,
I've always found measuring solder paste volume to be very difficult. Yes,
numbers can be generated, but even taking large amounts of data doesn't
guarantee the correct impression. Generally, regardless of equipment used,
the best results one can hope for are for trends, which at best could be
described to be of the order of -1 or +1 from true. It's not a bad thing
to
try but don't expect absolute results.
Best regards,
Andrew Hoggan
BBA Associates Ltd
www.bba-associates.ltd
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson
Sent: 31 July 2001 14:47
To: [log in to unmask]
Subject: [TN] Solder Paste Measurements
Dear Technetters,
My question is: how do you measure solder paste height and volume
accurately? My situation is with using the VisionMaster Model 150A, I am
having trouble obtaining reasonably accurate measurements. The
VisionMaster
is a small bench topsystem that uses a template consisting of a "region of
interest" (the solder paste), and reference regions (the areas on each
side
of the pad). Because there are inconsistencies in the PCB (HASL finish),
like raised areas from traces, valleys surrounding the pad, and
irregularities in the solder mask, the readings I get cannot possibly be
true. Many times the measured readings for weighted average height are
over
7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The
process specifics are Multicore NC-40 paste, shore 94-97 polyurethane
blades, DEK 265 Infinity, and correct squeegee pressures, print gap, etc..
I believe the bricks are good, I just ca! n't use the measurements for SPC
as it shows the process to be out of control.
In theory, polyurethane blades should "scoop" if anything, leaving a
shorter brick than the stencil thickness. It seems logical to me that the
best way to obtain accurate measurements would be to use the pad as a
reference region and measure the height from the pad, but the VisionMaster
system does not allow me to do this. Does anyone have knowledge or
recommendations on what I can do here? How do the more expensive systems
measure solder paste? Oh yea, spending $$ on new equipment is not a real
good option at this point!
Thanks in advance for the assistance,
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
--=_alternative 006CE2A087256A9B_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Steve,</font>
<br>
<br><font size=2 face="sans-serif">Thanks for the sound advice. I agree that a bullet-proof process and set-up procedure will produce the results necessary for high yield and that metal blades will help reduce variation. The situation I have seen here is that metal blades can, and will, get damaged in our facility (I've even seen poly blades get nicked!). In addition, I have seen several stencils get damaged, through careless handling or otherwise. The result is inconsistent print volume, leading to solder defects. The one area where I can't completely reduce variation is with operator skill, or diligence in following common sense practices. For example, soon after I got here I was troubled by the fact that boards were allowed to slide down a ramp at the end of reflow, sliding into each other and piling up. Unbelievably, I was questioned by some as to "why" I requested an operator at the end of reflow at all times. So!
me glued on components were actually being sheared off.</font>
<br>
<br><font size=2 face="sans-serif">The main problem we face here in arid western Colorado is the huge swing in RH and temperatures (swamp cooling in summer & gas heat in winter), and the very narrow process window of our current paste (Multicore NC-40). In the winter, RH can be around 8% at 70 - 76 deg F, and in the summer RH is up to 70% with temps up to 83 F. We have a significant problem with paste dry out on the boards and in the stencil apertures - sometimes a delay of less than 20 minutes can cause a problem. Many of the current solder pastes may eliminate this problem, and I am working on changing the paste - once I can get through the customer approvals and all that non-technical stuff. Until we can get the process in control, we must monitor the prints and reduce every variation that we can. Any feedback out there on enclosed printheads, ie ProFlow to help with our indoor climate problem?</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>"Stephen R. Gregory" <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">07/31/01 09:19 PM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."; Please respond to SteveZeva</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: Re: [TN] Solder Paste Measurements</font></table>
<br>
<br>
<br><font size=2 face="Arial">Hi All! <br>
<br>
Just want to "muddy the waters" a bit... <br>
<br>
How many of you that use metal squeegees, and pretty much have your stencil <br>
thickness down (as far as specifying thickness for a given pitch) have found <br>
that it is really "crucial" to measure your paste thickness? <br>
<br>
I for one, have found that when I spend the time and the money on equipment <br>
to measure paste thickness, when using metal squeegee blades, and having a <br>
solid set-up procedure, that I'm spending a bunch of time and money measuring <br>
things that are always good...meaning that time could be spent better <br>
elsewhere as long as you use metal squeegee blades, and have a good procedure <br>
in place ensures that the printer is set-up correctly..which is not rocket <br>
science... <br>
<br>
Am I over simplifying things? It's always worked for me since the advent of <br>
metal squeegees...I don't know how you can go wrong with a metal blade. Look <br>
at the gerbers you're given, see if they match the pad geometries, and then <br>
get the stencil made. Things are pretty straight forward after that... <br>
<br>
-Steve Gregory- <br>
<br>
</font>
<br><font size=2 face="Arial">Howard, in the past, I was forced to use to use and invest in smaller, less <br>
expensive systems (I've since been lucky to have nice EXPENSIVE <br>
toys-teehee). One of my favorite tools has always been the benchtop <br>
Cyberoptics unit. I don't remember the model name, I'm sure it's on their <br>
website, or a price figure. But I do know it was cheaper than most systems. <br>
The beauty of it is it shoots a laser at an angle, laser is viewable on <br>
monitor and is deflected by paste height. You line up the reference lines <br>
on the screen and get pretty true paste height. If your using 1:1 apertures <br>
or if you're doing aperaure reductions, you can calculate your volume. <br>
Hope I've helped. <br>
<br>
Jason Gregory <br>
SCI Systems, Inc. <br>
Software Specialist - NPI Group <br>
(256)882-4107 x3728 <br>
[log in to unmask] <br>
<br>
<br>
>>> [log in to unmask] 07/31/01 11:49 AM >>> <br>
Hi Howard, <br>
<br>
I've always found measuring solder paste volume to be very difficult. Yes, <br>
numbers can be generated, but even taking large amounts of data doesn't <br>
guarantee the correct impression. Generally, regardless of equipment used, <br>
the best results one can hope for are for trends, which at best could be <br>
described to be of the order of -1 or +1 from true. It's not a bad thing to <br>
try but don't expect absolute results. <br>
<br>
Best regards, <br>
<br>
Andrew Hoggan <br>
BBA Associates Ltd <br>
www.bba-associates.ltd <br>
-----Original Message----- <br>
From: TechNet [mailto:[log in to unmask]]On Behalf Of Howard Watson <br>
Sent: 31 July 2001 14:47 <br>
To: [log in to unmask] <br>
Subject: [TN] Solder Paste Measurements <br>
<br>
<br>
<br>
Dear Technetters, <br>
<br>
My question is: how do you measure solder paste height and volume <br>
accurately? My situation is with using the VisionMaster Model 150A, I am <br>
having trouble obtaining reasonably accurate measurements. The VisionMaster <br>
is a small bench topsystem that uses a template consisting of a "region of <br>
interest" (the solder paste), and reference regions (the areas on each side <br>
of the pad). Because there are inconsistencies in the PCB (HASL finish), <br>
like raised areas from traces, valleys surrounding the pad, and <br>
irregularities in the solder mask, the readings I get cannot possibly be <br>
true. Many times the measured readings for weighted average height are over <br>
7.5 mils using a 6 mil screen and 9.5 mils using an 8 mil screen. The <br>
process specifics are Multicore NC-40 paste, shore 94-97 polyurethane <br>
blades, DEK 265 Infinity, and correct squeegee pressures, print gap, etc.. <br>
I believe the bricks are good, I just ca! n't use the measurements for SPC <br>
as it shows the process to be out of control. <br>
<br>
In theory, polyurethane blades should "scoop" if anything, leaving a <br>
shorter brick than the stencil thickness. It seems logical to me that the <br>
best way to obtain accurate measurements would be to use the pad as a <br>
reference region and measure the height from the pad, but the VisionMaster <br>
system does not allow me to do this. Does anyone have knowledge or <br>
recommendations on what I can do here? How do the more expensive systems <br>
measure solder paste? Oh yea, spending $$ on new equipment is not a real <br>
good option at this point! </font>
<br><font size=2 face="Arial"><br>
Thanks in advance for the assistance, <br>
<br>
Howard Watson <br>
Manufacturing Engineer <br>
AMETEK/Dixson</font>
<br><font size=2 face="Arial"><br>
</font>
<br>
<br>
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=========================================================================
Date: Mon, 13 Aug 2001 14:21:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Brian L. Guidi" <[log in to unmask]>
Subject: Uralite
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Uralite.
Does anyone have any information on the above brand of conformal coat?
Technical details, history, and/or vendor information would be greatly
appreciated.
Thanks.
Brian Guidi
Product Engineer
Teledyne Electronic Technologies
Tel: (603) 889-6191 X:310
Fax: (603) 886-2977
E-mail: [log in to unmask]
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=========================================================================
Date: Mon, 13 Aug 2001 14:40:14 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: 6-pin DIP Optocoupler problem...
MIME-Version: 1.0
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boundary="part1_90.18a43b6e.28a9790e_boundary"
--part1_90.18a43b6e.28a9790e_boundary
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Content-Transfer-Encoding: 7bit
Hope you all are having a joyous Monday like I am...
Got pulled over by one of the inspectors this morning because we have this
little 6-pin DIP optocoupler that only goes about 65-per board. On some of
the parts we're seeing exposed copper up on the shoulder of the leads as it
comes out of the body.
Go to: http://www.stevezeva.homestead.com/index.html and take a peek...
What's kinda' strange is that this only happens on the pin-1 side of the
part. I've determined that we're getting the parts in like this...I found
some of the problem parts in tubes that we haven't done anything to yet...
In looking really close at the parts, there seems to be some sort of film
coming out of the body that covers the shoulders and prevents the leads from
plating fully (the picture is on the page as well)...it's almost like some
sort of thin plastic sheet...or could it be an adhesive preform that bond the
two halves of the part together? (I don't have a clue how these parts are
made).
Anyways, should I worry about these parts? There's some people here that's
worried about the exposed copper (here we go again...) and want to touch it
up. I feel that there really isn't a problem because it's so high up the lead
that it shouldn't hurt anything....if I were concerned about anything, it
would be about that stuff that is coming out the body of the part...
The part seems to work fine, we ICT the boards, and do a ambient power-on
burn in for 24-hrs...everything is okie-dokie. This is a class-2 board by the
way.
Thanks again, and have a lovely Monday...hehehe
-Steve Gregory-
--part1_90.18a43b6e.28a9790e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hope you all are having a joyous Monday like I am...
<BR>
<BR>Got pulled over by one of the inspectors this morning because we have this
<BR>little 6-pin DIP optocoupler that only goes about 65-per board. On some of
<BR>the parts we're seeing exposed copper up on the shoulder of the leads as it
<BR>comes out of the body.
<BR>
<BR>Go to: http://www.stevezeva.homestead.com/index.html and take a peek...
<BR>
<BR>What's kinda' strange is that this only happens on the pin-1 side of the
<BR>part. I've determined that we're getting the parts in like this...I found
<BR>some of the problem parts in tubes that we haven't done anything to yet...
<BR>
<BR>In looking really close at the parts, there seems to be some sort of film
<BR>coming out of the body that covers the shoulders and prevents the leads from
<BR>plating fully (the picture is on the page as well)...it's almost like some
<BR>sort of thin plastic sheet...or could it be an adhesive preform that bond the
<BR>two halves of the part together? (I don't have a clue how these parts are
<BR>made).
<BR>
<BR>Anyways, should I worry about these parts? There's some people here that's
<BR>worried about the exposed copper (here we go again...) and want to touch it
<BR>up. I feel that there really isn't a problem because it's so high up the lead
<BR>that it shouldn't hurt anything....if I were concerned about anything, it
<BR>would be about that stuff that is coming out the body of the part...
<BR>
<BR>The part seems to work fine, we ICT the boards, and do a ambient power-on
<BR>burn in for 24-hrs...everything is okie-dokie. This is a class-2 board by the
<BR>way.
<BR>
<BR>Thanks again, and have a lovely Monday...hehehe
<BR>
<BR>-Steve Gregory- </FONT></HTML>
--part1_90.18a43b6e.28a9790e_boundary--
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Date: Wed, 1 Aug 2001 16:17:42 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: [LF] Eutectic alloys?????
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Hi,
I am not so sure that the automotive industry is at the forefront of
soldering technology--only 2 years ago one of the Detroit Big 3 had to recall
2 years worth of SUVs because 60/40 SJs on CEM-1 [!?] PCBs for the windshield
wiper controls under-the-hood failed well within the warranty period. CEM-1
not only grossly thermally expands, but swells on H2O-absorption, and the bad
housing design caused the PCBs to warp.
Werner Engelmaier
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Date: Wed, 1 Aug 2001 16:43:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Erickson, Gary" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Erickson, Gary" <[log in to unmask]>
Subject: Re: 0.5 mm pitch components and soldermask relief
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I wouldn't think that a 3 mil web of Taiyo mask would survive ENIG
processing either.
Must be HASL Finish that Tony is talking about.
Gary
-----Original Message-----
From: Thomas Bauer [mailto:[log in to unmask]]
Sent: Wednesday, August 01, 2001 4:30 PM
To: [log in to unmask]
Subject: Re: [TN] 0.5 mm pitch components and soldermask relief
Tony,
What type of finish are you using on the pcb? Gold? Silver? not HASL???
THOMAS
-----Original Message-----
From: Tony Steinke [mailto:[log in to unmask]]
Sent: Wednesday, August 01, 2001 12:49 PM
To: [log in to unmask]
Subject: Re: [TN] 0.5 mm pitch components and soldermask relief
Phil,
As far as holding small dams-we have just recently qualified an LPI from
Taiyo
that we were repeatedly capable of holding .003in. solder dam.
Tony Steinke
Circuit Technologies Inc.
----- Original Message -----
From: phil bavaro <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, August 01, 2001 12:15 PM
Subject: [TN] 0.5 mm pitch components and soldermask relief
> We are just starting our development of 0.5 mm pitch BGAs and I am hearing
> conflicting reports as to the approach we should take with respect to the
> soldermask relief around the solderball pads.
>
> First of all, the 0.5mm BGA is made up of pairs of pads in a perimeter
> layout, along with a larger perimeter also made up of pairs of pads.
There
> is also a ground block in the center. Basically it looks like two
> concentric windowframes with a large gap between the frames for routing.
>
> Historically we have always made our soldermask 1:1 with the pad size and
> then the pwb fabricators would swell the opening so that the soldermask
did
> not encroach upon the pad and make it a mask defined pad. That works fine
> for 1.0 and 1.27 mm pitch devices because there is still enough soldermask
> left to actually stick to the board.
>
> When we reduce the pitch down to 0.5 mm, the gap between and the
> registrations swelling, basically eliminates the thicker stripe of
> soldermask down to a very thin (and poor yielding) line which may or may
> not stick.
>
> This is the exact same problem we have always had with 0.5 mm QFPs and the
> solution was always to permit the pwb fabricator to window out the whole
> area between the fine pitch pads.
>
> So here is the question:
>
> If we open up the soldermask aperture so that it is something like .065mm
> away from the actual etched pad, doesn't that just reduce the
producibility
> of the board at the pwb house. The reason for specifying this tight
> requirement is speculated to be related to reliability but I'm not
> convinced yet.
>
> In reality very few of the pads are strictly etch defined round pads
> because many have surface conductors coming off of them which makes the
> pads a hybrid of etch and mask defined. The greater the relief of the
> soldermask, the more non-uniform the exposed metal pad will become.
>
> Because there is more surface to wet to, this has the effect of reducing
> solderball volume and we expect to see the diameter not the height change
> accordingly.
>
> My suggestion is to eliminate the soldermask wherever the tight pad to pad
> areas are so that for two round pads, the aperture would be a very wide
> oval shape. This also means that the routing away from the pads has to go
> to the outside away from the open soldermasked area.
>
> The intention here is minimize the enlargement of the pads with respect to
> wettable area and at the same time make the soldermask application process
> easier.
>
> Ironically it seems that 0201 pads can also follow this logic.
> Hopefully I've explained this in detail enough for everyone to understand.
>
> What does your land patterns guidelines when it comes to soldermask for
> fine pitch QFPs, BGAs, and 0201s?
>
> All inputs are appreciated.
>
> Phillip A. Bavaro
> QUALCO/\/\/\/\ Incorporated
> Engineer, Staff
> [log in to unmask]
> Pager (858) 271-3640
> Tel (858) 658-2542 Voice mail
> Cell (858) 845-9968 (workday)
> Cell (619) 602-8644 (offsite, after hours)
> Fax (858) 658-1584
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
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> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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<TITLE>RE: [TN] 0.5 mm pitch components and soldermask relief</TITLE>
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<P><FONT SIZE=2>I wouldn't think that a 3 mil web of Taiyo mask would survive ENIG processing either.</FONT>
<BR><FONT SIZE=2>Must be HASL Finish that Tony is talking about.</FONT>
</P>
<P><FONT SIZE=2>Gary</FONT>
</P>
<P><FONT SIZE=2>-----Original Message-----</FONT>
<BR><FONT SIZE=2>From: Thomas Bauer [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=2>Sent: Wednesday, August 01, 2001 4:30 PM</FONT>
<BR><FONT SIZE=2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=2>Subject: Re: [TN] 0.5 mm pitch components and soldermask relief</FONT>
</P>
<BR>
<P><FONT SIZE=2>Tony,</FONT>
<BR><FONT SIZE=2>What type of finish are you using on the pcb? Gold? Silver? not HASL???</FONT>
</P>
<P><FONT SIZE=2>THOMAS</FONT>
</P>
<BR>
<P><FONT SIZE=2>-----Original Message-----</FONT>
<BR><FONT SIZE=2>From: Tony Steinke [<A HREF="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=2>Sent: Wednesday, August 01, 2001 12:49 PM</FONT>
<BR><FONT SIZE=2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=2>Subject: Re: [TN] 0.5 mm pitch components and soldermask relief</FONT>
</P>
<BR>
<P><FONT SIZE=2>Phil,</FONT>
<BR><FONT SIZE=2>As far as holding small dams-we have just recently qualified an LPI from</FONT>
<BR><FONT SIZE=2>Taiyo</FONT>
<BR><FONT SIZE=2>that we were repeatedly capable of holding .003in. solder dam.</FONT>
<BR><FONT SIZE=2>Tony Steinke</FONT>
<BR><FONT SIZE=2>Circuit Technologies Inc.</FONT>
<BR><FONT SIZE=2>----- Original Message -----</FONT>
<BR><FONT SIZE=2>From: phil bavaro <[log in to unmask]></FONT>
<BR><FONT SIZE=2>To: <[log in to unmask]></FONT>
<BR><FONT SIZE=2>Sent: Wednesday, August 01, 2001 12:15 PM</FONT>
<BR><FONT SIZE=2>Subject: [TN] 0.5 mm pitch components and soldermask relief</FONT>
</P>
<BR>
<P><FONT SIZE=2>> We are just starting our development of 0.5 mm pitch BGAs and I am hearing</FONT>
<BR><FONT SIZE=2>> conflicting reports as to the approach we should take with respect to the</FONT>
<BR><FONT SIZE=2>> soldermask relief around the solderball pads.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> First of all, the 0.5mm BGA is made up of pairs of pads in a perimeter</FONT>
<BR><FONT SIZE=2>> layout, along with a larger perimeter also made up of pairs of pads.</FONT>
<BR><FONT SIZE=2>There</FONT>
<BR><FONT SIZE=2>> is also a ground block in the center. Basically it looks like two</FONT>
<BR><FONT SIZE=2>> concentric windowframes with a large gap between the frames for routing.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> Historically we have always made our soldermask 1:1 with the pad size and</FONT>
<BR><FONT SIZE=2>> then the pwb fabricators would swell the opening so that the soldermask</FONT>
<BR><FONT SIZE=2>did</FONT>
<BR><FONT SIZE=2>> not encroach upon the pad and make it a mask defined pad. That works fine</FONT>
<BR><FONT SIZE=2>> for 1.0 and 1.27 mm pitch devices because there is still enough soldermask</FONT>
<BR><FONT SIZE=2>> left to actually stick to the board.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> When we reduce the pitch down to 0.5 mm, the gap between and the</FONT>
<BR><FONT SIZE=2>> registrations swelling, basically eliminates the thicker stripe of</FONT>
<BR><FONT SIZE=2>> soldermask down to a very thin (and poor yielding) line which may or may</FONT>
<BR><FONT SIZE=2>> not stick.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> This is the exact same problem we have always had with 0.5 mm QFPs and the</FONT>
<BR><FONT SIZE=2>> solution was always to permit the pwb fabricator to window out the whole</FONT>
<BR><FONT SIZE=2>> area between the fine pitch pads.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> So here is the question:</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> If we open up the soldermask aperture so that it is something like .065mm</FONT>
<BR><FONT SIZE=2>> away from the actual etched pad, doesn't that just reduce the</FONT>
<BR><FONT SIZE=2>producibility</FONT>
<BR><FONT SIZE=2>> of the board at the pwb house. The reason for specifying this tight</FONT>
<BR><FONT SIZE=2>> requirement is speculated to be related to reliability but I'm not</FONT>
<BR><FONT SIZE=2>> convinced yet.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> In reality very few of the pads are strictly etch defined round pads</FONT>
<BR><FONT SIZE=2>> because many have surface conductors coming off of them which makes the</FONT>
<BR><FONT SIZE=2>> pads a hybrid of etch and mask defined. The greater the relief of the</FONT>
<BR><FONT SIZE=2>> soldermask, the more non-uniform the exposed metal pad will become.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> Because there is more surface to wet to, this has the effect of reducing</FONT>
<BR><FONT SIZE=2>> solderball volume and we expect to see the diameter not the height change</FONT>
<BR><FONT SIZE=2>> accordingly.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> My suggestion is to eliminate the soldermask wherever the tight pad to pad</FONT>
<BR><FONT SIZE=2>> areas are so that for two round pads, the aperture would be a very wide</FONT>
<BR><FONT SIZE=2>> oval shape. This also means that the routing away from the pads has to go</FONT>
<BR><FONT SIZE=2>> to the outside away from the open soldermasked area.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> The intention here is minimize the enlargement of the pads with respect to</FONT>
<BR><FONT SIZE=2>> wettable area and at the same time make the soldermask application process</FONT>
<BR><FONT SIZE=2>> easier.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> Ironically it seems that 0201 pads can also follow this logic.</FONT>
<BR><FONT SIZE=2>> Hopefully I've explained this in detail enough for everyone to understand.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> What does your land patterns guidelines when it comes to soldermask for</FONT>
<BR><FONT SIZE=2>> fine pitch QFPs, BGAs, and 0201s?</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> All inputs are appreciated.</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> Phillip A. Bavaro</FONT>
<BR><FONT SIZE=2>> QUALCO/\/\/\/\ Incorporated</FONT>
<BR><FONT SIZE=2>> Engineer, Staff</FONT>
<BR><FONT SIZE=2>> [log in to unmask]</FONT>
<BR><FONT SIZE=2>> Pager (858) 271-3640</FONT>
<BR><FONT SIZE=2>> Tel (858) 658-2542 Voice mail</FONT>
<BR><FONT SIZE=2>> Cell (858) 845-9968 (workday)</FONT>
<BR><FONT SIZE=2>> Cell (619) 602-8644 (offsite, after hours)</FONT>
<BR><FONT SIZE=2>> Fax (858) 658-1584</FONT>
<BR><FONT SIZE=2>></FONT>
<BR><FONT SIZE=2>> --------------------------------------------------------------------------</FONT>
<BR><FONT SIZE=2>-------</FONT>
<BR><FONT SIZE=2>> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d</FONT>
<BR><FONT SIZE=2>> To unsubscribe, send a message to [log in to unmask] with following text in</FONT>
<BR><FONT SIZE=2>> the BODY (NOT the subject field): SIGNOFF Technet</FONT>
<BR><FONT SIZE=2>> To temporarily halt delivery of Technet send the following message: SET</FONT>
<BR><FONT SIZE=2>Technet NOMAIL</FONT>
<BR><FONT SIZE=2>> Search previous postings at: www.ipc.org > On-Line Resources & Databases ></FONT>
<BR><FONT SIZE=2>E-mail Archives</FONT>
<BR><FONT SIZE=2>> Please visit IPC web site (<A HREF="http://www.ipc.org/html/forum.htm" TARGET="_blank">http://www.ipc.org/html/forum.htm</A>) for</FONT>
<BR><FONT SIZE=2>additional</FONT>
<BR><FONT SIZE=2>> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700</FONT>
<BR><FONT SIZE=2>ext.5315</FONT>
<BR><FONT SIZE=2>> --------------------------------------------------------------------------</FONT>
<BR><FONT SIZE=2>-------</FONT>
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Date: Wed, 1 Aug 2001 15:49:24 -0400
Reply-To: Tony Steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tony Steinke <[log in to unmask]>
Subject: Re: 0.5 mm pitch components and soldermask relief
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Phil,
As far as holding small dams-we have just recently qualified an LPI from
Taiyo
that we were repeatedly capable of holding .003in. solder dam.
Tony Steinke
Circuit Technologies Inc.
----- Original Message -----
From: phil bavaro <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, August 01, 2001 12:15 PM
Subject: [TN] 0.5 mm pitch components and soldermask relief
> We are just starting our development of 0.5 mm pitch BGAs and I am hearing
> conflicting reports as to the approach we should take with respect to the
> soldermask relief around the solderball pads.
>
> First of all, the 0.5mm BGA is made up of pairs of pads in a perimeter
> layout, along with a larger perimeter also made up of pairs of pads.
There
> is also a ground block in the center. Basically it looks like two
> concentric windowframes with a large gap between the frames for routing.
>
> Historically we have always made our soldermask 1:1 with the pad size and
> then the pwb fabricators would swell the opening so that the soldermask
did
> not encroach upon the pad and make it a mask defined pad. That works fine
> for 1.0 and 1.27 mm pitch devices because there is still enough soldermask
> left to actually stick to the board.
>
> When we reduce the pitch down to 0.5 mm, the gap between and the
> registrations swelling, basically eliminates the thicker stripe of
> soldermask down to a very thin (and poor yielding) line which may or may
> not stick.
>
> This is the exact same problem we have always had with 0.5 mm QFPs and the
> solution was always to permit the pwb fabricator to window out the whole
> area between the fine pitch pads.
>
> So here is the question:
>
> If we open up the soldermask aperture so that it is something like .065mm
> away from the actual etched pad, doesn't that just reduce the
producibility
> of the board at the pwb house. The reason for specifying this tight
> requirement is speculated to be related to reliability but I'm not
> convinced yet.
>
> In reality very few of the pads are strictly etch defined round pads
> because many have surface conductors coming off of them which makes the
> pads a hybrid of etch and mask defined. The greater the relief of the
> soldermask, the more non-uniform the exposed metal pad will become.
>
> Because there is more surface to wet to, this has the effect of reducing
> solderball volume and we expect to see the diameter not the height change
> accordingly.
>
> My suggestion is to eliminate the soldermask wherever the tight pad to pad
> areas are so that for two round pads, the aperture would be a very wide
> oval shape. This also means that the routing away from the pads has to go
> to the outside away from the open soldermasked area.
>
> The intention here is minimize the enlargement of the pads with respect to
> wettable area and at the same time make the soldermask application process
> easier.
>
> Ironically it seems that 0201 pads can also follow this logic.
> Hopefully I've explained this in detail enough for everyone to understand.
>
> What does your land patterns guidelines when it comes to soldermask for
> fine pitch QFPs, BGAs, and 0201s?
>
> All inputs are appreciated.
>
> Phillip A. Bavaro
> QUALCO/\/\/\/\ Incorporated
> Engineer, Staff
> [log in to unmask]
> Pager (858) 271-3640
> Tel (858) 658-2542 Voice mail
> Cell (858) 845-9968 (workday)
> Cell (619) 602-8644 (offsite, after hours)
> Fax (858) 658-1584
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send the following message: SET
Technet NOMAIL
> Search previous postings at: www.ipc.org > On-Line Resources & Databases >
E-mail Archives
> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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Date: Fri, 20 Jul 2001 14:52:44 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Larry Tawyea <[log in to unmask]>
Subject: Re: Cooling Rates
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_23.ea704a0.2889d7fc_boundary"
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In a message dated 6/28/01 6:39:56 AM Central Daylight Time,
[log in to unmask] writes:
I not sure about the cooling rate for Silicon but I will bet you that if you
have any plastic IC's on the PCB they are sure to not like that profile.
Larry Tawyea
> Hello Guys,
>
> What is the best cooling down rate in a reflow oven?
> Does anybody have experience on what maximum cooling down rate
> that will not result in Silicon cracking?
> We have some silicon cracking (Chips) and we are still evaluating
> if fast cool down can cause this problem.
> My Profile is:
> Pre-heat: 150 C
> Soak: 250 C
> Reflow 1: 290 C
> Reflow 2: 290 C
> Time of Reflow: 180 secs
>
> Thank you very much in advance for your ideas tomorrow
>
--part1_23.ea704a0.2889d7fc_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated 6/28/01 6:39:56 AM Central Daylight Time,
<BR>[log in to unmask] writes:
<BR>
<BR>I not sure about the cooling rate for Silicon but I will bet you that if you
<BR>have any plastic IC's on the PCB they are sure to not like that profile.
<BR>
<BR>Larry Tawyea
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello Guys,
<BR>
<BR>What is the best cooling down rate in a reflow oven?
<BR>Does anybody have experience on what maximum cooling down rate
<BR>that will not result in Silicon cracking?
<BR>We have some silicon cracking (Chips) and we are still evaluating
<BR>if fast cool down can cause this problem.
<BR>My Profile is:
<BR>Pre-heat: 150 C
<BR>Soak: 250 C
<BR>Reflow 1: 290 C
<BR>Reflow 2: 290 C
<BR>Time of Reflow: 180 secs
<BR>
<BR>Thank you very much in advance for your ideas tomorrow
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_23.ea704a0.2889d7fc_boundary--
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Date: Fri, 20 Jul 2001 10:19:07 -0400
Reply-To: Ed Valentine <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Valentine <[log in to unmask]>
Organization: Electronics Manufacturing Solutions
Subject: Re: In-line process
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0018_01C11105.68C16CE0"
This is a multi-part message in MIME format.
------=_NextPart_000_0018_01C11105.68C16CE0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
You may want to consider options other than a straight line.
Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask]
Website: http://www.ems-consulting.com
----- Original Message -----=20
From: Van Hoang Dinh=20
To: [log in to unmask]
Sent: Friday, July 20, 2001 12:55 AM
Subject: [TN] In-line process
Hi TechNet,
We are going to implement IN-LINE process. Any recommends or ideas =
would help for me.
Thanks In Advance
Van
------=_NextPart_000_0018_01C11105.68C16CE0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4611.1300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>You may want to consider options other =
than a=20
straight line.</FONT></DIV>
<DIV><BR>Ed Valentine<BR>Electronics Manufacturing Solutions<BR>8612 =
Mourning=20
Dove Road, Raleigh, NC 27615<BR>Phone: (919) 270-5145, Fax: (919)=20
847-9971<BR>Email: <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]
om</A><BR>Website:=20
<A=20
href=3D"http://www.ems-consulting.com">http://www.ems-consulting.com</A><=
BR></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Van =
Hoang Dinh</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, July 20, 2001 =
12:55=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] In-line =
process</DIV>
<DIV><BR></DIV>
<DIV><FONT size=3D2>Hi TechNet,</FONT></DIV>
<DIV><FONT size=3D2>We are going to implement IN-LINE process. Any =
recommends or=20
ideas would help for me.</FONT></DIV>
<DIV><FONT size=3D2>Thanks In Advance</FONT></DIV>
<DIV><FONT size=3D2>Van</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0018_01C11105.68C16CE0--
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Date: Mon, 13 Aug 2001 15:32:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Off-Topic - coatings for airplane-home
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
i've seen articles about you weird people in wobeoregon doing this. why not ask somebody up there that has already done this? kapton makes a pretty good tape, but not much as a coating.
why not use a catlyzed polyurethane coating which is what the military uses to paint their non-stealthy aircraft? you should know, however, that this will cause an unacceptable number of trees and wildlife (including humans)to expire.
why not ditch the 727 and build a sod hut?
phil
-----Original Message-----
From: Carl VanWormer [mailto:[log in to unmask]]
Sent: Monday, August 13, 2001 2:59 PM
To: [log in to unmask]
Subject: [TN] Off-Topic - coatings for airplane-home
Definitely off-topic, but interesting . . .
I have a friend who is making his new home out of a 727 airplane (see
www.AirplaneHome.com <http://www.AirplaneHome.com> for details). He is
investigating coatings he might use to "paint the house", and has rejected
his first choice (Kapton) when he found that it deteriorates when exposed to
UV and Oxygen (I think that was what it was). Since I've seen some amazing
insights shared on this group, I thought I'd dangle this challenge in front
of the group to see what happens . . . Any (and all) suggestions will be
appreciated and investigated. Please let me know of your suggestions and
I'll forward them to him.
Thanks
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
p.s. here's a snippet from my last contact with the airplane/home owner:
Hot dog, thanks very much. I've always been very fond of RTVs - they seem
more stable than any conventional paint, or any other coating short of
Teflon. I've never in my life seen any evidence of any form of
deterioration
of RTVs, and they've been around since I was a kid. I've always thought
they'd make a great roof coating for my mobile home (back when maintenance
of
the structure would've been justified) or the freight vans.
The timing is quite good too in that I've been thinking about coatings
again.
I've been pressure washing again in the last few days, and I've noted that,
while the color coats often flake off, the chromates don't, although they
can
bleed off. That is, the chromates seem to form a chemical bond with the
aluminum, whereas the paint just forms an adhesive bond, which, like all
adhesive bonds, is unreliable. When the pressurized water is forced onto
the
chromate at its most aggressive (with the wand within a cm or two of the
surface), the chromate sometimes get fainter and fainter as if they're being
abraded off. But they never peel. That's impressive.
And that's what I'd like in a coating - a true chemical bond, so that it's
literally part of the metal, not just a layer over the metal. Well, that,
plus absolute immunity to UV, chemical weathering, and every other factor
that makes a coating just plain perfect.
Teflon's been on my mind too. It's extremely stable of course. But I'm not
sure what the nature of it's bond is, or what the economics are - I need to
look into it.
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Date: Fri, 20 Jul 2001 07:35:18 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Gerber specification
In-Reply-To: <3.0.3.32.20010719103705.01e28b08@orion>
MIME-Version: 1.0
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The Gerber specification is now owned by:
Barco ETS
30 South Satellite Road, South Windsor, CT 06074
Tel. ++ 1 860 291 7000 Fax ++ 1 860 291 7021
They have (had??) a printed document (The Gerber Format Guide) which was
available under part number 414-100-002 when this was part of Gerber Systems
Corp.
The now also have published a new version of this document on the web:
http://www.barco.be/ets/data/rs274xc.pdf
(and that is still there).
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dee Stover
Sent: Thursday, July 19, 2001 10:37
To: [log in to unmask]
Subject: [TN] Gerber specification
I need to find the specifications of gerber language, would any of you know
where I can get that information.
TIA
Dee Stover [log in to unmask]
Associate Technician Design
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
520-318-8489
FAX 520-318-8303
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Date: Mon, 13 Aug 2001 16:20:40 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Creswick, Steven" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Creswick, Steven" <[log in to unmask]>
Subject: Back-side Device Metallization
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Technetters,
I ran into an interesting item the other day that I would appreciate a
sanity check on. I realize that this is a rather oblique question for this
forum, but there are other (silent) hybrid types out there (I believe).
Most of the bare silicon die that I have used in the past have either been
grey-backed (bare silicon), gold-silicon (eutectic), or chrome-nickel-silver
(power mosfets).
I have recently encountered a supplier that uses aluminum (alloyed) for
back-side contact of generic, none speciallized, silicon devices. Has
anyone else encountered this as well? If so, have you observed any contact
resistance problems when used with normal silver-filled conductive
adhesives?
It makes sense that it would form an ohmic contact to the back-side of the
wafer - just never ran into an aluminum metallized back-side before....
.. Just wanted to know if my head has been .... in the sand. (Will post on
ChipNet as well)
Thanks
Steve Creswick - Gentex
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Date: Wed, 15 Aug 2001 09:21:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Subject: Re: Solder analysis results
Any comment on Steve's stratification theory? A few years back I had SPC
charts at a HASL pot at a PC fab, with analysis every two weeks. Cu
content stayed 0.21% to 0.24% over a period of 1+ years, even though all we
were doing was skimming stuff off the top. Lou Hart
-----Original Message-----
From: Stephen R. Gregory [SMTP:[log in to unmask]]
Sent: Tuesday, August 14, 2001 10:04 PM
To: [log in to unmask]
Subject: Re: [TN] Solder analysis results
Dave,
Surely, not ALL 1700-lbs.? Wooo-doggies! I can only imagine what a task
that
would be!!! I've read some stuff that if you keep the pot static, and keep
it
at a stable temperature for a period (what this really is, I don't
know...there's varying opinions), the metals will seek their own level
(according to the different opinions, the copper will be towards the top),
then you scoop out out the top layer, and replenish what you've removed
with
fresh bars.
The question that I have though, how did the pot get so out of balance with
copper? I've never had a problem with copper content, even when waving OSP
boards...tin levels dropping, yes. But not excessive copper...somebody
throw
some pennies in the pot?
-Steve Gregory-
> RJ Klien Wassink suggests [bible p 169] pouring contaminated solder at
about
> 190°C through a 20 mesh stainless steel stariner to reduce copper content
to
> 0.25%.
>
> Dave Fish
>
<< File: ATT00002.htm >>
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Date: Wed, 15 Aug 2001 08:35:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Cleanliness evaluation!
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Whilst I wholeheartedly concur with what Doug stated, I do not agree for
the
need for Ion Chromatography (IC) testing.
*WHAT?!!!! LIGHT THE TORCHES, BURN THE HERETIC....... (he turned me into
a newt....I got better...)
I must disagree with your disagreement.
Iain, if you run a correct SIR test regime on your proper proposed
production process, and you have acceptable results, then you can feel
comfortable that you will have a reliable end product. If you have failures
in this test, then you need IC to find out precisely what is present on the
surface that may be causing your problem. Yes you should then use ionic
extract testing (SEC/ROSE) to keep an eye on your process conditions - but
make no attempt to correlate SIR with SEC/ROSE results.
*Graham brings up a valid point that there is more than one tool for
assessing cleanliness or quality, but I don't know that SIR would be any
better than IC at this point. For both tests, you need someone to help you
interpret the numbers. Having the information that your assemblies have
2.7 ppm of chloride doesn't do much good unless you know if that is a good
or bad number. Having the information that your process yields a mean SIR
level of 283 megohms on a B-24 doesn't mean much unless you can relate to
product. The advantage of SIR is that of these two tests, it is better at
showing if residues have a propensity for electrochemical failures
(leakage, corrosion, metal migration), but you still have to do more
extensive correlation studies on actual product to know whether the values
from that lab test relate to product life in the field. Then you have to
also do a correlation study with ROSE/SEC to see what levels to use as a
target and upper control limit. An additional disadvantage of SIR is that
it is a long test. Brian Ellis wrote a paper a few years ago that long
term SIR testing could be cut down to an 8 hour test, but that is still
much longer than a 2 hour IC test. Difficult to do as a process control
measure. I have found it easier to correlate IC results with SEC/ROSE than
with SIR.
*You know, I find it really weird that after being and SIR champion for so
long, I argue against it here. I guess the point being that if you are
going to use ROSE/SEC as a process monitoring tool, which several companies
do successfully, you have to do extensive correlation studies between
product life testing (dozens of ways to do it) and any quality control
measures you implement. You have to know what your monitoring signal means
in order to properly set the target and upper control limits. Most
existing ROSE/SEC levels in specifications are both antiquated and bogus.
I would suggest that you retain the use of SIR equipment as a
process/quality monitor. Taking sample coupons at each stage of the
production process and running short tests will (probably) give you the
necessary indicators if the process or process materials are changing.
*This is possible, but I would say that you need a more focused test coupon
than the B-24 and one that is fabricated with your set of materials.
Additional cost in doing this, but the data is more relevant. Maybe use
the **fanfare** CONCOAT TEST COUPON!!!! (Look, up in the sky, its a bird,
its a plane...)
To ensure that you have used the correct test protocol, I assume that you
took on board the recommendations as published by the EU project partners
NPL, Siemens, NMRC and Lares Cozzi. If anyone wants a copy of this work,
let
me know.
*What a clever way to do some academic spamming <grin>. Sayyyyyyy, wasn't
that the work where the particpants used **fanfare** THE CONCOAT AUTOSIR?
(Notice how I very slyly slip in some gratuitous advertising for my friend
across the pond. Ain't I clever?).
*Graham refers to a consortia activity going on for the last three years or
so looking at continous monitoring SIR vs. various flux and processing
conditions. I wasn't aware that this was a published report yet. I have
invited Dr. Chris Hunt of NPL in the UK to give a presentation on this work
at the SIR task group meeting at the Fall IPC meeting.
By the way, running IPC-TM-650 did they test to Appendix D of J-STD001 (or
is it now B? Doug??) or did they run to 6.2.3. or 6.2.3.3? What was the
coupon they used? What was the pitch/width they used? What was the test
voltage used?
*I'm sure Graham means methods 2.6.3 (cyclical environment) and 2.6.3.3
(static environment). The SIR protocol that Graham refers to was found in
Appendix D of J-STD-001, Revisions A and B. Revision C is now the current
version and the protocol is now Appendix B (lost two appendices somewhere).
*Graham, in his last two sentences brings up another good point - there are
so many possible choices in an SIR test (or IC test for that matter), that
you really need a guide in selecting the best factors for any particular
situation. And where would you FIND such experts? Why, at the upcoming
Fall IPC meeting in Orlando, Florida. (notice the sly advertising for the
IPC...) Usually you can get a few of them to guide you along if ya buy the
beer (well, at least ONE such expert I know of...).
Doug Pauls
Rockwell Collins
(Well into his third Mountain Dew of the day)
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Date: Thu, 16 Aug 2001 17:16:14 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: To wave or not to wave, that is the question...
In-Reply-To: <[log in to unmask]>
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We've done several different assys (board sizes and complexities) using
0805's on side 2. We have used a 2nd side adhesive step and cure prior to
hand assembly insertion and Dover Soltec Wave soldering. I will contact our
process engineer to dig up solder wave profiles, adhesive spec, and cure
times tomorrow and I will send them your way. --Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kevin Stokes
Sent: Thursday, August 16, 2001 4:26 PM
To: [log in to unmask]
Subject: [TN] To wave or not to wave, that is the question...
Old problem: mounting ceramic capacitors to the bottom side of an
assembly and your customer wants you to wave them on.
We are having problems with 0805 0.22 uF and 0.1 uF caps going through
wave and cracking during the process. We are following all of the standard
protocols (preheat, etc.). My understanding is that 0805s are typically
capable of handling this process.
Anyone got any ideas short of moving the cap to the top or doing a
double sided reflow?
Kevin
Kevin Stokes
Reliability Manager
Kimball Electronics Group
(812) 634-4207
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<TITLE>To wave or not to wave, that is the question...</TITLE>
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV><SPAN class=3D865081121-16082001><FONT color=3D#0000ff face=3DArial =
size=3D2>We've=20
done several different assys (board sizes and complexities) using 0805's =
on side=20
2. We have used a 2nd side adhesive step and cure prior to hand =
assembly=20
insertion and Dover Soltec Wave soldering. I will contact our =
process=20
engineer to dig up solder wave profiles, adhesive spec, and cure times =
tomorrow=20
and I will send them your way. --Dean =
Lillibridge</FONT></SPAN></DIV>
<DIV><SPAN class=3D865081121-16082001><FONT color=3D#0000ff face=3DArial =
size=3D2> &nbs=
p;  =
; =
&=
nbsp; &n=
bsp; &nb=
sp; &nbs=
p;  =
; =
&=
nbsp; =20
NEWvENTURE TECHNOLOGIES</FONT></SPAN></DIV>
<DIV><SPAN class=3D865081121-16082001><FONT color=3D#0000ff face=3DArial =
size=3D2> </FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet [<A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]<B>On =
Behalf Of</B>=20
Kevin Stokes<BR><B>Sent:</B> Thursday, August 16, 2001 4:26 =
PM<BR><B>To:</B>=20
<A =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR><B>Subject:</B> =
[TN]=20
To wave or not to wave, that is the question...<BR><BR></FONT></DIV>
<P><FONT face=3DArial size=3D2>Old problem: mounting ceramic =
capacitors to the=20
bottom side of an assembly and your customer wants you to wave them=20
on.</FONT> </P>
<P><FONT face=3DArial size=3D2>We are having problems with 0805 0.22 =
uF and 0.1=20
uF caps going through wave and cracking during the process. We =
are=20
following all of the standard protocols (preheat, etc.). My=20
understanding is that 0805s are typically capable of handling this=20
process.</FONT></P>
<P><FONT face=3DArial size=3D2>Anyone got any ideas short of moving =
the cap to=20
the top or doing a double sided reflow?</FONT> <BR><BR><FONT =
face=3DArial=20
size=3D2>Kevin</FONT> </P>
<P><I><FONT color=3D#000080 face=3D"News Gothic MT">Kevin =
Stokes</FONT></I>=20
<BR><FONT face=3DArial size=3D2>Reliability Manager</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Kimball Electronics Group</FONT> <BR><FONT face=3DArial =
size=3D2>(812)=20
634-4207</FONT> </P></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 15 Aug 2001 11:45:39 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "James W. High" <[log in to unmask]>
Subject: photoplotting service
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Technetters,
I am in search of a photoplotting service that can plot larger than 36",
with good service and reasonable pricing. Geographical location is not
important.
Thanks
James W. High
NASA Langley Research Center
Mail Stop 390
Hampton, VA 23681-2199
757-864-5416 (Phone)
757-864-8092 (Fax)
Email: [log in to unmask]
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Date: Wed, 15 Aug 2001 18:59:44 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Dewetting
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Grant
This is controversial. Dewetting is caused by myriad non-wettable areas,
most commonly because abrasive particles are implanted in the metal.
IMHO, this means that intermetallic formation is discontinuous and the
joint will be weaker. Whether the loss of strength is important or not
is more academic than real life, but my view is that everything should
be done to maximise strength. Also, if you permit it, where do you start
to draw the line?
Brian
Grant Emandien wrote:
>
> Hi all,
>
> Brian, thanks for your earlier comments.
>
> If a portion of a pad shows evidence of dewetting (some dewetted pad areas
> appear to show base metal) and the solder joint looks good (nice shiny
> fillets), is there reason for concern that these joints may fail at
> temperature excursions (-40°C to +60°C)?
>
> Thanks in advance for responses.
> Grant
>
> **********************************************************************
> Notice:
>
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Date: Fri, 20 Jul 2001 13:18:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: Re: X-Ray Laminography Test
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Technetters,
> I am looking for a lab that provides X-Ray Laminography services. I need
> to evaluate the solder joints on some BGAs and I was wondering what would
> give a complete 3D analysis of the solder joint. Is there any lab that
> provides Laminography services? My company is located in Phoenix, Arizona.
> Any information would be appreciated.
>
> Jorge Rodriguez
> Process Engineer
> Varian, Inc.
>
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Date: Tue, 14 Aug 2001 08:55:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: JinSee Goh <[log in to unmask]>
Subject: Additive Trace Repair
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Hi Technetters,
Instead of using Jumper wires, I'm looking into the additive trace method
(including etch deletes). Is anyone out there in this business or knows of
anyone who is in this business?
I am not looking for manual repair service providers but am looking for
automated repairs with high turnaround. I would also prefer if the service
provider is in Asia. Thanks.
Rgds,
JS
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<BODY>
<P><FONT SIZE=3D2>Hi Technetters,</FONT>
<BR><FONT SIZE=3D2>Instead of using Jumper wires, I'm looking into the =
additive trace method (including etch deletes). Is anyone out there in =
this business or knows of anyone who is in this business? </FONT></P>
<P><FONT SIZE=3D2>I am not looking for manual repair service providers =
but am looking for automated repairs with high turnaround. I would also =
prefer if the service provider is in Asia. Thanks.</FONT></P>
<P><FONT SIZE=3D2>Rgds,</FONT>
<BR><FONT SIZE=3D2>JS</FONT>
</P>
</BODY>
</HTML>
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Date: Mon, 13 Aug 2001 20:57:38 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Off-Topic - coatings for airplane-home
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Hi Carl!
I will agree that this is off-topic, and I must say is interesting!
I'm trying to imagine what effort it is taking for your freind to convert a
727 into a home, it really is something...I've read through a lot of his
progress reports, but not all, but I found the FAQ at his page most
informative as to why he is doing something like this...I must say, he does
point out some good reasons for this.
Although there may be some snickers at his efforts, there are have been, and
are, unusual homes built by others. One such is the "Beer Can House" check it
out at:
http://www.hgtv.com/HGTV/project/0,1158,BDRE_project_1113,FF.html
Sounds like you would need to get a bunch of buddies together for one
MARATHON party for that...hehehe.
Another is the Missile Silo Houses, go to: http://www.missilebases.com/
Here you can have 18,000 sq. ft. of space to model to your desires. Just hope
that any country that has ICBM's have updated the targeting data for their
missiles to these sites as being residential areas...and NOT functional ICBM
sites...
As to the dilemma of what to "paint" the aircraft with...the best thing to do
with aluminum (which is undoubtably what the skin is made of) anodizing
provides the best finish. But we can't very well make a tank big enough to
anodize the whole bloody aircraft, and I'm sure we don't want to take the
plane apart piece-by-piece to do that.
Another consideration to think about is how any finish is going to be
applied. This I assume is going to be done on the site, out in the open,
without the benefit of a Hanger that will sheild the aircraft from the
elements.
>From my Navy days as a aircraft structural mechanic, we used to do our
corrosion inspections on T-28's in South Texas humidity, on the flight lines
sometimes, and use a Zinc Chromate primer, with a polyurethane final
coat...not the most enviromentally freindly finishes. But that's what we
used...
This isn't gonna be a easy one for your freind...and from what I know, there
is always going to be some maintenance of the finish down the line...
Cheers,
-Steve Gregory-
> Definitely off-topic, but interesting . . .
>
> I have a friend who is making his new home out of a 727 airplane (see
> www.AirplaneHome.com <http://www.AirplaneHome.com> for details). He is
> investigating coatings he might use to "paint the house", and has rejected
> his first choice (Kapton) when he found that it deteriorates when exposed to
> UV and Oxygen (I think that was what it was). Since I've seen some amazing
> insights shared on this group, I thought I'd dangle this challenge in front
> of the group to see what happens . . . Any (and all) suggestions will be
> appreciated and investigated. Please let me know of your suggestions and
> I'll forward them to him.
>
> Thanks
>
--part1_64.11b283ba.28a9d182_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Carl!
<BR>
<BR>I will agree that this is off-topic, and I must say is interesting!
<BR>
<BR>I'm trying to imagine what effort it is taking for your freind to convert a
<BR>727 into a home, it really is something...I've read through a lot of his
<BR>progress reports, but not all, but I found the FAQ at his page most
<BR>informative as to why he is doing something like this...I must say, he does
<BR>point out some good reasons for this.
<BR>
<BR>Although there may be some snickers at his efforts, there are have been, and
<BR>are, unusual homes built by others. One such is the "Beer Can House" check it
<BR>out at:
<BR>
<BR>http://www.hgtv.com/HGTV/project/0,1158,BDRE_project_1113,FF.html
<BR>
<BR>Sounds like you would need to get a bunch of buddies together for one
<BR>MARATHON party for that...hehehe.
<BR>
<BR>Another is the Missile Silo Houses, go to: http://www.missilebases.com/
<BR>
<BR>Here you can have 18,000 sq. ft. of space to model to your desires. Just hope
<BR>that any country that has ICBM's have updated the targeting data for their
<BR>missiles to these sites as being residential areas...and NOT functional ICBM
<BR>sites...
<BR>
<BR>As to the dilemma of what to "paint" the aircraft with...the best thing to do
<BR>with aluminum (which is undoubtably what the skin is made of) anodizing
<BR>provides the best finish. But we can't very well make a tank big enough to
<BR>anodize the whole bloody aircraft, and I'm sure we don't want to take the
<BR>plane apart piece-by-piece to do that.
<BR>
<BR>Another consideration to think about is how any finish is going to be
<BR>applied. This I assume is going to be done on the site, out in the open,
<BR>without the benefit of a Hanger that will sheild the aircraft from the
<BR>elements.
<BR>
<BR>From my Navy days as a aircraft structural mechanic, we used to do our
<BR>corrosion inspections on T-28's in South Texas humidity, on the flight lines
<BR>sometimes, and use a Zinc Chromate primer, with a polyurethane final
<BR>coat...not the most enviromentally freindly finishes. But that's what we
<BR>used...
<BR>
<BR>This isn't gonna be a easy one for your freind...and from what I know, there
<BR>is always going to be some maintenance of the finish down the line...
<BR>
<BR>Cheers,
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Definitely off-topic, but interesting . . .
<BR>
<BR>I have a friend who is making his new home out of a 727 airplane (see
<BR>www.AirplaneHome.com <http://www.AirplaneHome.com> for details). He is
<BR>investigating coatings he might use to "paint the house", and has rejected
<BR>his first choice (Kapton) when he found that it deteriorates when exposed to
<BR>UV and Oxygen (I think that was what it was). Since I've seen some amazing
<BR>insights shared on this group, I thought I'd dangle this challenge in front
<BR>of the group to see what happens . . . Any (and all) suggestions will be
<BR>appreciated and investigated. Please let me know of your suggestions and
<BR>I'll forward them to him.
<BR>
<BR>Thanks
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Mon, 13 Aug 2001 21:16:51 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Rudy Sedlak>" <[log in to unmask]>
Subject: Re: Flip Chip flex circuit
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>From what I have heard, putting Electroless Ni/Imm Gold on flex can be an
interesting challenge in getting it to plate where you want ONLY...
Has anyone else heard this?
Rudy Sedlak
RD Chemical Company
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Date: Thu, 2 Aug 2001 01:01:11 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Heinz Mader <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Heinz Mader <[log in to unmask]>
Subject: Heinz Mader/NMADEH/CH/Ascom ist außer Haus.
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Ich werde ab 30.07.2001 nicht im Büro sein. Ich kehre zurück am
10.08.2001.
Ich werde Ihre Nachricht nach meiner Rückkehr beantworten.
Bei Problemen Hugo Piller oder Bernhard Schaeren
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Date: Tue, 14 Aug 2001 21:31:59 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Solder analysis results
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RJ Klien Wassink suggests [bible p 169] pouring contaminated solder at about
190°C through a 20 mesh stainless steel stariner to reduce copper content to
0.25%.
Dave Fish
----- Original Message -----
From: "Phil Nutting" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, August 14, 2001 5:48 AM
Subject: [TN] Solder analysis results
> Ok folks, here is today's question.
>
> I just received a Certificate of Analysis (our first one) for the solder
> in our Soltec Waver Solder machine. All parameters are "within
> specification" except the percentage of copper which is at 1.6859. (Tin
> is at 61.3% and Lead is at 36.99% and other stuff is at 0.0199%) We run
> 63/37 in the wave. We only solder our own product, none of which goes
> into "mission critical" applications. We normally build our product to
> IPC-A-610C, Class 2.
>
> My question is two-fold. Should I worry about this? If so, how do I
> fix it with 1700 pounds of solder in the solder pot?
>
> Thanks is advance for sharing your knowledge.
>
> Phil Nutting
> Manufacturing Engineer
> Kaiser Systems, Inc.
>
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Date: Wed, 1 Aug 2001 16:05:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Rework
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What do the manufacturer's specifications say? In my experience some are 0
and some are more.
Dorothy Lush
> ----------
> From: Craig Hillman[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Craig Hillman
> Sent: Wednesday, August 01, 2001 3:48 PM
> To: [log in to unmask]
> Subject: Rework
>
> Technetters,
>
> Any recommendations on maximum number of rework cycles for a Plastic BGA?
>
> TIA,
> Craig
>
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Date: Thu, 2 Aug 2001 11:25:38 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Process Problem vs Board Problem
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Bill:
I've run into boards with this appearance before. You should see it on the
'as received' boards. What you're seeing is dewetting at the knee of the
hole. If my memory is correct, you will not get good hole fill after
soldering and the top side filets on holes with leaded components will not
wet out onto the pads completely. It's been several years but the cause may
arise from copper contamination prior to HASL. Possibly from a poorly
vented or contaminated curing oven for LPI final cure.
My memory is fuzy about the root cause, so don't take it as a certaintity.
Hope this helps.
Don Vischulis
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Date: Tue, 14 Aug 2001 08:22:33 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Off-Topic - coatings for airplane-home
MIME-Version: 1.0
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Good Morning,
We chaps here in foggy England are always being told that everything in the
States is bigger and better, so why not find a plating shop with a large
tank and anodise the fuselage? Lots of jolly colours to choose from as well!
Regards
Eric the Cad
> -----Original Message-----
> From: Crepeau, Phil [SMTP:[log in to unmask]]
> Sent: 13 August 2001 23:33
> To: [log in to unmask]
> Subject: Re: [TN] Off-Topic - coatings for airplane-home
>
> hi,
>
> i've seen articles about you weird people in wobeoregon doing this. why
> not ask somebody up there that has already done this? kapton makes a
> pretty good tape, but not much as a coating.
>
> why not use a catlyzed polyurethane coating which is what the military
> uses to paint their non-stealthy aircraft? you should know, however, that
> this will cause an unacceptable number of trees and wildlife (including
> humans)to expire.
>
> why not ditch the 727 and build a sod hut?
>
> phil
>
> -----Original Message-----
> From: Carl VanWormer [mailto:[log in to unmask]]
> Sent: Monday, August 13, 2001 2:59 PM
> To: [log in to unmask]
> Subject: [TN] Off-Topic - coatings for airplane-home
>
>
> Definitely off-topic, but interesting . . .
>
> I have a friend who is making his new home out of a 727 airplane (see
> www.AirplaneHome.com <http://www.AirplaneHome.com> for details). He is
> investigating coatings he might use to "paint the house", and has rejected
> his first choice (Kapton) when he found that it deteriorates when exposed
> to
> UV and Oxygen (I think that was what it was). Since I've seen some
> amazing
> insights shared on this group, I thought I'd dangle this challenge in
> front
> of the group to see what happens . . . Any (and all) suggestions will be
> appreciated and investigated. Please let me know of your suggestions and
> I'll forward them to him.
>
> Thanks
>
> Carl Van Wormer
> Cipher Systems
> 1815 NW 169th Place, Suite 5010
> Beaverton, OR 97006
> Phone (503)-617-7447 Fax (503)-617-6550
>
>
>
> p.s. here's a snippet from my last contact with the airplane/home owner:
> Hot dog, thanks very much. I've always been very fond of RTVs - they seem
> more stable than any conventional paint, or any other coating short of
> Teflon. I've never in my life seen any evidence of any form of
> deterioration
> of RTVs, and they've been around since I was a kid. I've always thought
> they'd make a great roof coating for my mobile home (back when maintenance
> of
> the structure would've been justified) or the freight vans.
>
> The timing is quite good too in that I've been thinking about coatings
> again.
> I've been pressure washing again in the last few days, and I've noted
> that,
>
> while the color coats often flake off, the chromates don't, although they
> can
> bleed off. That is, the chromates seem to form a chemical bond with the
> aluminum, whereas the paint just forms an adhesive bond, which, like all
> adhesive bonds, is unreliable. When the pressurized water is forced onto
> the
> chromate at its most aggressive (with the wand within a cm or two of the
> surface), the chromate sometimes get fainter and fainter as if they're
> being
>
> abraded off. But they never peel. That's impressive.
>
> And that's what I'd like in a coating - a true chemical bond, so that it's
> literally part of the metal, not just a layer over the metal. Well, that,
> plus absolute immunity to UV, chemical weathering, and every other factor
> that makes a coating just plain perfect.
>
> Teflon's been on my mind too. It's extremely stable of course. But I'm
> not
>
> sure what the nature of it's bond is, or what the economics are - I need
> to
> look into it.
>
> --------------------------------------------------------------------------
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>
> --------------------------------------------------------------------------
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Date: Fri, 20 Jul 2001 18:49:58 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Inspection Criteria
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Hi John!!
Like Kathy said, magnification for inspection is spelled out in the 610, and
the J-STD too...I would quote them, but I don't have them in front of me...I
do know 30X is pushing things a whole lot!
This issue is a never ending debate. Are your inspectors finding REAL
defects? I go through this stuff quite a bit too...so I understand your
frustrations.
An ol' crusty QA manager told me a while back, is that there are two kinds of
inspectors, those that inspect to accept, and those that inspect to reject.
He also said that if it takes more than just a couple of seconds to decide if
something is good or bad, it's probably good...leave it alone.
I go through this stuff all the time...especially with class-II stuff here.
The latest battle has been with barrel-fill. You're allowed a 75% barrel fill
with class-II stuff...
The inspectors complain that they can't tell if it's 74% or 76%, so they
reject everything that doesn't have a full barrel fill...(where's my
Excedrin?). In turn, this just conditions all our operators to touch-up
things that they don't need to touch-up...and it goes on and on, and on, and
on...
Have tried to talk to them about the issues when re-heating solder joints,
(intermetallics, and that it's NOT increasing the functionality or
reliability of the joints).
But it's like like I'm talking to a wall. Inspectors, as you have learned,
need to feel that they must find something...I've only met a few inspectors
that I can hand a board to, and get it back without red-arrows on it
somewhere...whether there is defects on it or not. That's their job (in their
mind), to find something wrong...if they can't find something wrong, then
they've missed something, and not done their job...
If it sounds like I'm getting down on inspectors, I'm really not. There's
been more than just a few times in my career that I was really glad that
there was a very detailed, picky, inspector, that caught a mistake from
production that was pretty serious before we shipped to the customer...stuff
happens. But on the other hand, there has been times that they've been so
focused on solder joints, that they've totally missed that there were
components installed, that were wrong values, wrong polarity, etc...
I'm not saying that you need a QA inspector to tell you when you load
something wrong, that responsibilty should fall squarely on the set-up and
first article inspection from the people that are running the line, but you
know what I'm driving at...
-Steve Gregory-
--part1_a6.16f537ff.288a0f96_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi John!!
<BR>
<BR>Like Kathy said, magnification for inspection is spelled out in the 610, and
<BR>the J-STD too...I would quote them, but I don't have them in front of me...I
<BR>do know 30X is pushing things a whole lot!
<BR>
<BR>This issue is a never ending debate. Are your inspectors finding REAL
<BR>defects? I go through this stuff quite a bit too...so I understand your
<BR>frustrations.
<BR>
<BR>An ol' crusty QA manager told me a while back, is that there are two kinds of
<BR>inspectors, those that inspect to accept, and those that inspect to reject.
<BR>He also said that if it takes more than just a couple of seconds to decide if
<BR>something is good or bad, it's probably good...leave it alone.
<BR>
<BR>I go through this stuff all the time...especially with class-II stuff here.
<BR>The latest battle has been with barrel-fill. You're allowed a 75% barrel fill
<BR>with class-II stuff...
<BR>
<BR>The inspectors complain that they can't tell if it's 74% or 76%, so they
<BR>reject everything that doesn't have a full barrel fill...(where's my
<BR>Excedrin?). In turn, this just conditions all our operators to touch-up
<BR>things that they don't need to touch-up...and it goes on and on, and on, and
<BR>on...
<BR>
<BR>Have tried to talk to them about the issues when re-heating solder joints,
<BR>(intermetallics, and that it's NOT increasing the functionality or
<BR>reliability of the joints).
<BR>
<BR>But it's like like I'm talking to a wall. Inspectors, as you have learned,
<BR>need to feel that they must find something...I've only met a few inspectors
<BR>that I can hand a board to, and get it back without red-arrows on it
<BR>somewhere...whether there is defects on it or not. That's their job (in their
<BR>mind), to find something wrong...if they can't find something wrong, then
<BR>they've missed something, and not done their job...
<BR>
<BR>If it sounds like I'm getting down on inspectors, I'm really not. There's
<BR>been more than just a few times in my career that I was really glad that
<BR>there was a very detailed, picky, inspector, that caught a mistake from
<BR>production that was pretty serious before we shipped to the customer...stuff
<BR>happens. But on the other hand, there has been times that they've been so
<BR>focused on solder joints, that they've totally missed that there were
<BR>components installed, that were wrong values, wrong polarity, etc...
<BR>
<BR>I'm not saying that you need a QA inspector to tell you when you load
<BR>something wrong, that responsibilty should fall squarely on the set-up and
<BR>first article inspection from the people that are running the line, but you
<BR>know what I'm driving at...
<BR>
<BR>-Steve Gregory-
<BR>
<BR></FONT></HTML>
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Date: Wed, 15 Aug 2001 11:52:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dave Roesler <[log in to unmask]>
Subject: Re: photoplotting service
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James,
Try Reyhan in Minnesota. They can plot up to 6 foot x 8 foot. I have had
excellent quality and service from them.
Contact Pat Beadles at (651) 256-0050.
Dave Roesler
TRI-C Design, Inc.
----- Original Message -----
From: "James W. High" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, August 15, 2001 10:45 AM
Subject: [TN] photoplotting service
> Technetters,
>
> I am in search of a photoplotting service that can plot larger than 36",
> with good service and reasonable pricing. Geographical location is not
> important.
>
> Thanks
>
>
> James W. High
> NASA Langley Research Center
> Mail Stop 390
> Hampton, VA 23681-2199
>
> 757-864-5416 (Phone)
> 757-864-8092 (Fax)
> Email: [log in to unmask]
>
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Date: Fri, 20 Jul 2001 19:23:26 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Air filtration units...
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_10.fd06985.288a176e_boundary"
--part1_10.fd06985.288a176e_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi everyone!
Well, I'm just about to melt into a puddle here...it's hella hot here!! Check
out the National Weather Service message for us after my question...they're
saying this weather is gonna be with us all next week on the news...
ANYWAYS, do any of you you use any of the filtration units on the market to
exhaust your wave solder machines, reflow ovens, etc.?
When I worked with Zevatech, and did NEPCON shows etc., there was a unit that
was always used for exhaust when things were being run "live" at the shows
(TAC line for example, plus other vendors that actually wanted to run their
machines)...I was pretty impressed with them...they were units from
Impell...just trying to find out if anybody actually uses this method to
exhaust mass reflow machines (wave, reflow ovens).
Thanks!
(he says as he's getting a cool iced-tea..be glad you're not here!)
-Steve Gregory-
Non Precipitation Advisory: HEAT ADVISORY THROUGH SATURDAY
Urgent - Weather Message National Weather Service Tulsa OK 405 PM CDT Thu
Jul 19 2001 Creek OK - Nowata OK - Okfuskee OK - Okmulgee OK - Osage OK -
Pawnee OK - Rogers OK - Tulsa OK - Washington OK - Including The Cities Of...
Nowata... Claremore... Okemah... Okmulgee... Pawhuska... Tulsa... Sand
Springs... Broken Arrow... Bartlesville... Pawnee And Bristow 405 PM CDT Thu
Jul 19 2001
Heat Advisory Through Saturday...
The Combination Of Very Hot Temperatures And High Relative Humidity Will
Continue To Create Dangerous Conditions Through Saturday Across Much Of
Northeast Oklahoma. Afternoon High Temperatures Will Reach Between 98 And 101
Degrees With Heat Index Values Between 110 And 115. Overnight Temperatures
Will Only Briefly Drop To Around Or Slightly Below 80 Degrees Providing
Little Relief From The Heat. The Upper Level High Pressure System Responsible
For The Heat Is Forecast By Computer Models To Remain Nearly Stationary
Across Oklahoma... Thus The Hot And Humid Weather Is Expected To Continue
Through The Rest Of Week And Into The Weekend. Strenuous Activities Should Be
Reduced... Eliminated Or Rescheduled To The Coolest Time Of The Day. If You
Must Be Outside... Drink Plenty Of Fluids To Avoid Dehydration. Your Body Can
Lose Up To A Gallon Of Water An Hour Through Perspiration. Alcoholic And
Caffeinated Beverages Can Increase The Rate Of Water Loss In Your Body...
Increasing The Risk Of Heat Exhaustion Or Stroke. Wear Lightweight... Light -
Colored... Loose - Fitting Clothing. Wear A Hat To Shield Yourself From The
Sun... And Use A Sunscreen To Reduce Possible Sunburn. Pets Can Also Succumb
To The Affects Of Excessive Heat. Ensure Pets Have Adequate Drinking Water
And A Shady Place To Rest. Do Not Leave Pets In Cars... Temperatures Inside
An Enclosed Car Can Reach Over 150 Degrees Quickly... Resulting In Heat
Stroke And Death.
Children... The Elderly... And People With Chronic Ailments Are Usually The
First To Suffer From The Heat. Heat Exhaustion... Heat Cramps... Or In
Extreme Cases... Heat Stroke May Result From Prolonged Exposure To These
Conditions. Friends... Relatives... Or Neighbors Should Check On People At
Risk.
Stay Tuned To Noaa Weather Radio... Commercial Radio Or Television For The
Latest Information Concerning This Excessive Heat Event. Additional Weather
Information Can Also Be Obtained On Our Web Site At: Www.Srh.Noaa.Gov/Tulsa
--part1_10.fd06985.288a176e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi everyone!
<BR>
<BR>Well, I'm just about to melt into a puddle here...it's hella hot here!! Check
<BR>out the National Weather Service message for us after my question...they're
<BR>saying this weather is gonna be with us all next week on the news...
<BR>
<BR>ANYWAYS, do any of you you use any of the filtration units on the market to
<BR>exhaust your wave solder machines, reflow ovens, etc.?
<BR>
<BR>When I worked with Zevatech, and did NEPCON shows etc., there was a unit that
<BR>was always used for exhaust when things were being run "live" at the shows
<BR>(TAC line for example, plus other vendors that actually wanted to run their
<BR>machines)...I was pretty impressed with them...they were units from
<BR>Impell...just trying to find out if anybody actually uses this method to
<BR>exhaust mass reflow machines (wave, reflow ovens).
<BR>
<BR>Thanks!
<BR>(he says as he's getting a cool iced-tea..be glad you're not here!)
<BR>
<BR>-Steve Gregory-
<BR>
<BR>Non Precipitation Advisory: HEAT ADVISORY THROUGH SATURDAY
<BR> Urgent - Weather Message National Weather Service Tulsa OK 405 PM CDT Thu
<BR>Jul 19 2001 Creek OK - Nowata OK - Okfuskee OK - Okmulgee OK - Osage OK -
<BR>Pawnee OK - Rogers OK - Tulsa OK - Washington OK - Including The Cities Of...
<BR>Nowata... Claremore... Okemah... Okmulgee... Pawhuska... Tulsa... Sand
<BR>Springs... Broken Arrow... Bartlesville... Pawnee And Bristow 405 PM CDT Thu
<BR>Jul 19 2001
<BR>
<BR>Heat Advisory Through Saturday...
<BR>
<BR>The Combination Of Very Hot Temperatures And High Relative Humidity Will
<BR>Continue To Create Dangerous Conditions Through Saturday Across Much Of
<BR>Northeast Oklahoma. Afternoon High Temperatures Will Reach Between 98 And 101
<BR>Degrees With Heat Index Values Between 110 And 115. Overnight Temperatures
<BR>Will Only Briefly Drop To Around Or Slightly Below 80 Degrees Providing
<BR>Little Relief From The Heat. The Upper Level High Pressure System Responsible
<BR>For The Heat Is Forecast By Computer Models To Remain Nearly Stationary
<BR>Across Oklahoma... Thus The Hot And Humid Weather Is Expected To Continue
<BR>Through The Rest Of Week And Into The Weekend. Strenuous Activities Should Be
<BR>Reduced... Eliminated Or Rescheduled To The Coolest Time Of The Day. If You
<BR>Must Be Outside... Drink Plenty Of Fluids To Avoid Dehydration. Your Body Can
<BR>Lose Up To A Gallon Of Water An Hour Through Perspiration. Alcoholic And
<BR>Caffeinated Beverages Can Increase The Rate Of Water Loss In Your Body...
<BR>Increasing The Risk Of Heat Exhaustion Or Stroke. Wear Lightweight... Light -
<BR>Colored... Loose - Fitting Clothing. Wear A Hat To Shield Yourself From The
<BR>Sun... And Use A Sunscreen To Reduce Possible Sunburn. Pets Can Also Succumb
<BR>To The Affects Of Excessive Heat. Ensure Pets Have Adequate Drinking Water
<BR>And A Shady Place To Rest. Do Not Leave Pets In Cars... Temperatures Inside
<BR>An Enclosed Car Can Reach Over 150 Degrees Quickly... Resulting In Heat
<BR>Stroke And Death.
<BR>
<BR>Children... The Elderly... And People With Chronic Ailments Are Usually The
<BR>First To Suffer From The Heat. Heat Exhaustion... Heat Cramps... Or In
<BR>Extreme Cases... Heat Stroke May Result From Prolonged Exposure To These
<BR>Conditions. Friends... Relatives... Or Neighbors Should Check On People At
<BR>Risk.
<BR>
<BR>Stay Tuned To Noaa Weather Radio... Commercial Radio Or Television For The
<BR>Latest Information Concerning This Excessive Heat Event. Additional Weather
<BR>Information Can Also Be Obtained On Our Web Site At: Www.Srh.Noaa.Gov/Tulsa</FONT></HTML>
--part1_10.fd06985.288a176e_boundary--
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Date: Fri, 20 Jul 2001 16:24:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Inspection Criteria
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_0F5561A5.F091FD46"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_0F5561A5.F091FD46
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Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
The magnification guidelines are in section 1. It is determined by the =
conductor width and if the magnification is being a referee judgement or =
inspection judgement.=20
Kathy=20
--=_0F5561A5.F091FD46
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY style="FONT: 10pt Haettenschweiler; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>The magnification guidelines are in section 1. It is determined by
the conductor width and if the magnification is being a referee judgement or
inspection judgement. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 15 Aug 2001 13:46:28 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Panelized Boards
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I have a 3.5" x 5.5", .063" thick board we will be building in somewhat high
quantities (3,000+/month). This size board is just on the edge as far as
having to put it into a basket to run through our in-line aqueous cleaner to
keep it from moving around. I do not want the operators to have to put this
many boards in baskets during production runs. So, my thoughts have turned
to panelizing these boards, perhaps in a 2x2 arrangement. This would go
through the cleaner with no problem. I do not have a lot of experience in
the best designs for panels. What are the advantages/disadvantages between
v-score and tabs? If using tabs, how many are required to maintain the
rigidity of the panel during reflow? Does there have to be a border around
the boards? Are fiducials required on the panel in addition to the fiducials
already on the individual boards? Any other issues I may have missed?
Thanks.
Bob
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Date: Wed, 1 Aug 2001 22:30:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Rework
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Craig,
For what Class product (1,2, or 3)?
David A. Douthit
Manager
LoCan LLC
Craig Hillman wrote:
> Technetters,
>
> Any recommendations on maximum number of rework cycles for a Plastic BGA?
>
> TIA,
> Craig
>
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> ---------------------------------------------------------------------------------
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Date: Tue, 14 Aug 2001 14:06:02 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Connector tilt, acceptable or not?
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Wolfgang,
After looking at the pictures I have a question. Are these connectors mounted to the PCB with
90 degree leads? If so the only way to get the sort of "tilt" showing is if the leads have
been bent.
In any case the fact that the connectors may "fit" does not alter the fact that they will
still transfer stress and strains not designed for. These additional stresses could shorten
the lije of the solder joints plus the change internally between the male/female interface
can cause unusual wear on the gold plating.
If this is a class 3 product fix it and argue about whose fault it is later.
David A. Douthit
Manager
LoCan LLC
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Date: Tue, 14 Aug 2001 14:05:38 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Lush, Dorothy" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lush, Dorothy" <[log in to unmask]>
Subject: Re: solder balls
MIME-Version: 1.0
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I like Loan's answer because solderballs normally form in the middle along
the side of the chip component and not underneath. The normal solderball is
formed when solder follows the flux under the component during reflow then
is "squeezed" out to the side when the molten solder solidifies, shrinks and
pulls the chip flush to the board surface. I could see the pulling down
action stopped by, say, epoxy or soldermask non-existence or over presence.
Are these balls being formed during SMD or solderwave do you think? An
aqueous SMT paste process usually will wash this ball away. No-clean paste
requires not forming them in the first place (and only allowing them to stay
if they are imbedded in flux and less than a certain size, etc.) by
controlling stencil aperature, solder printing(x-y and z(volume)), solder
choice and oven profile. Is this an aqueous or no-clean solder paste/process
we are talking about?
Dorothy Lush
Manufacturing Engineer
> ----------
> From: Marsico, James[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Marsico, James
> Sent: Tuesday, August 14, 2001 12:34 PM
> To: [log in to unmask]
> Subject: soldr balls
>
> Here's a relatively basic SMT question, but we've haven't experienced this
> before. We're seeing solder balls under (way under, in the center) chip
> components. Any recommendations?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> --------------------------------------------------------------------------
> -------
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> E-mail Archives
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> additional
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> --------------------------------------------------------------------------
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>
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Date: Wed, 15 Aug 2001 14:45:18 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Panelized Boards
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
if you don't mind supplying me with your fax number, I can fax over some
considerations that we have used for panelizing boards.
--Dean Lillibridge
NEWvENTURE TECHNOLOGIES
(860) 253-7057
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
Sent: Wednesday, August 15, 2001 1:46 PM
To: [log in to unmask]
Subject: [TN] Panelized Boards
I have a 3.5" x 5.5", .063" thick board we will be building in somewhat high
quantities (3,000+/month). This size board is just on the edge as far as
having to put it into a basket to run through our in-line aqueous cleaner to
keep it from moving around. I do not want the operators to have to put this
many boards in baskets during production runs. So, my thoughts have turned
to panelizing these boards, perhaps in a 2x2 arrangement. This would go
through the cleaner with no problem. I do not have a lot of experience in
the best designs for panels. What are the advantages/disadvantages between
v-score and tabs? If using tabs, how many are required to maintain the
rigidity of the panel during reflow? Does there have to be a border around
the boards? Are fiducials required on the panel in addition to the fiducials
already on the individual boards? Any other issues I may have missed?
Thanks.
Bob
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=========================================================================
Date: Mon, 23 Jul 2001 19:39:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jiang Ping <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jiang Ping <[log in to unmask]>
Subject: Re: Inspection Criteria
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Date: Tue, 14 Aug 2001 14:04:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Keel, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Keel, Mike" <[log in to unmask]>
Subject: Re: Off-Topic - coatings for airplane-home
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Tile it . . .
Just like the space shuttle
-----Original Message-----
From: Albin, David [mailto:[log in to unmask]]
Sent: Tuesday, August 14, 2001 11:43 AM
To: [log in to unmask]
Subject: Re: [TN] Off-Topic - coatings for
airplane-home
Aha!
and the eggshells could make a nice mosaic
motif......
David Albin
Coates Circuit Products
-----Original Message-----
From: Mike Fenner [mailto:[log in to unmask]]
Sent: 14 August 2001 09:11
To: [log in to unmask]
Subject: Re: [TN] Off-Topic - coatings for airplane-home
A slightly more environmentally friendly way of doing this
might be to paint
the thing with raw egg yolks and leave out to bake in the
Sunshine which I
understand you fellows also have in the USA. The sulphides
in the egg should
give a nice matt black finish. The whites should contribute
to a nice
meringue which in accordance with Eric's observations will
be the biggest in
the World. [However please dispose of the eggshells
considerately]
Mike
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric
Dawson
Sent: Tuesday, August 14, 2001 8:23 AM
To: [log in to unmask]
Subject: Re: [TN] Off-Topic - coatings for airplane-home
Good Morning,
We chaps here in foggy England are always being told that
everything in the
States is bigger and better, so why not find a plating shop
with a large
tank and anodise the fuselage? Lots of jolly colours to
choose from as well!
Regards
Eric the Cad
> -----Original Message-----
> From: Crepeau, Phil [SMTP:[log in to unmask]]
> Sent: 13 August 2001 23:33
> To: [log in to unmask]
> Subject: Re: [TN] Off-Topic - coatings for
airplane-home
>
> hi,
>
> i've seen articles about you weird people in wobeoregon
doing this. why
> not ask somebody up there that has already done this?
kapton makes a
> pretty good tape, but not much as a coating.
>
> why not use a catlyzed polyurethane coating which is what
the military
> uses to paint their non-stealthy aircraft? you should
know, however, that
> this will cause an unacceptable number of trees and
wildlife (including
> humans)to expire.
>
> why not ditch the 727 and build a sod hut?
>
> phil
>
> -----Original Message-----
> From: Carl VanWormer [mailto:[log in to unmask]]
> Sent: Monday, August 13, 2001 2:59 PM
> To: [log in to unmask]
> Subject: [TN] Off-Topic - coatings for airplane-home
>
>
> Definitely off-topic, but interesting . . .
>
> I have a friend who is making his new home out of a 727
airplane (see
> www.AirplaneHome.com <http://www.AirplaneHome.com> for
details). He is
> investigating coatings he might use to "paint the house",
and has rejected
> his first choice (Kapton) when he found that it
deteriorates when exposed
> to
> UV and Oxygen (I think that was what it was). Since I've
seen some
> amazing
> insights shared on this group, I thought I'd dangle this
challenge in
> front
> of the group to see what happens . . . Any (and all)
suggestions will be
> appreciated and investigated. Please let me know of your
suggestions and
> I'll forward them to him.
>
> Thanks
>
> Carl Van Wormer
> Cipher Systems
> 1815 NW 169th Place, Suite 5010
> Beaverton, OR 97006
> Phone (503)-617-7447 Fax (503)-617-6550
>
>
>
> p.s. here's a snippet from my last contact with the
airplane/home owner:
> Hot dog, thanks very much. I've always been very fond of
RTVs - they seem
> more stable than any conventional paint, or any other
coating short of
> Teflon. I've never in my life seen any evidence of any
form of
> deterioration
> of RTVs, and they've been around since I was a kid. I've
always thought
> they'd make a great roof coating for my mobile home (back
when maintenance
> of
> the structure would've been justified) or the freight
vans.
>
> The timing is quite good too in that I've been thinking
about coatings
> again.
> I've been pressure washing again in the last few days,
and I've noted
> that,
>
> while the color coats often flake off, the chromates
don't, although they
> can
> bleed off. That is, the chromates seem to form a chemical
bond with the
> aluminum, whereas the paint just forms an adhesive bond,
which, like all
> adhesive bonds, is unreliable. When the pressurized water
is forced onto
> the
> chromate at its most aggressive (with the wand within a cm
or two of the
> surface), the chromate sometimes get fainter and fainter
as if they're
> being
>
> abraded off. But they never peel. That's impressive.
>
> And that's what I'd like in a coating - a true chemical
bond, so that it's
> literally part of the metal, not just a layer over the
metal. Well, that,
> plus absolute immunity to UV, chemical weathering, and
every other factor
> that makes a coating just plain perfect.
>
> Teflon's been on my mind too. It's extremely stable of
course. But I'm
> not
>
> sure what the nature of it's bond is, or what the
economics are - I need
> to
> look into it.
>
>
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Date: Tue, 14 Aug 2001 22:34:14 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Roger Hammond <[log in to unmask]>
Subject: FAB. Cleaning stainless steel multilayer bonding shims.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Dear all,
My thanks to those good peple who answered my query on FDA approval, it
was all very useful.My customer was most Pleased.
Here is another Question. What is the best way to clean epoxy and
polyimide resin spew from the surface and from the pin location holes of
stainless steel shims?
Years ago we used to use Chlorinated solvent but that is now banned. We
currently brush the shims in a Schmid deburring machine after use but
have to manually clear the holes. Concentrated sulpuric acid has been
suggested. This is not an option I would willingly take. Are there any
other alternatives?
Thank you
Roger Hammond
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Date: Mon, 23 Jul 2001 13:32:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Component Mass / Pad Geometries
In-Reply-To: <[log in to unmask]@eric>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I have a very cool ruler, made of FR4. One side is inches and tenths. The
other side is centimeters and halves, quarters and eighths.
Guy Ramsey
Senior Lab Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Christison
Sent: Monday, July 23, 2001 11:44 AM
To: [log in to unmask]
Subject: Re: [TN] Component Mass / Pad Geometries
Nice to see some consistent units - g/in^2 here. Haven't seen this mix since
I came across a stress quoted in N/in^2 ;-).....
> Hi Steve!
>
> The formula that has been floating around for a while is that you get
> 30-grams of surface tension for every square inch of pad surface....
>
> -Steve Gregory-
>
>
> > Question?
> >
> > There is a formula somewhere which I can use to calculate the maximum
> > allowable mass of a component in relation to the pad lands. Basically
> I
> > want to make sure our designers do not put components on the underside
> > of the PCB which are going to fall off during doublesided reflow.
> >
> > I would like to point out that this is a design for manufacturability
> > question, not an attack on the tentative grasp on reality some card
> > designers have.
> >
> > Steve.
> >
>
>
>
Eric Christison
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Date: Thu, 2 Aug 2001 09:18:18 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Rework
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hi Craig,
One rework cycle for a BGA means desoldering, cleaning excessive solder =
from the BGA-pads, reballing and resoldering, all this in addition to the =
original soldering cycle.
I don't think there's any manufacturer that will guarantee that their =
BGA's will survive this.
In practice I've had some good results (meaning: the board still worked) =
with BGA's that were subjected to all these cycles for 4 or 5 times.
Kind regards,
Daan Terstegge
Unclassified mail
Personal Website: http://www.smtinfo.net=20
>>> Craig Hillman <[log in to unmask]> 08/02 12:48 am >>>
Technetters,
Any recommendations on maximum number of rework cycles for a Plastic BGA?
TIA,
Craig
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Date: Tue, 14 Aug 2001 16:37:11 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: LI YUAN <[log in to unmask]>
Subject: Interesting Coplanarity ?
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
I had a customer asking this question:
The customer has the devices already soldered on the board and want to know
what is the coplanarity. Is is a valid question? If so, how?
Thanks,
YL
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Date: Thu, 16 Aug 2001 12:47:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Moisture Sensitive Component Handling & Identification
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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A quick review of moisture/time sensitive packages in our stockroom shows
that:
moisture sensitivity related material (shelf life/ prebake/sealed
date/etc) is included on the outside bag as well as mfr/mfr part number/
p.o.#/ etc on material that comes from distributors or has not been
repackaged by consigned suppliers.
I also have examples in which a moisture-sensitive programmable supplied
on tape and reel would also include the moisture sensitve information on the
reel itself as well as the outside bag or box. I have a gut feeling that
this is strictly up to the packaging specs of the mfr or distributor who has
done the final blasting of the programmable. If your distributor offers
programming of components, they may be able to mark both the reel and
outside packaging. A good question to ask when you are quoting availability
of material or sourceing a new distributor.
If a device is distributed as a blank and then programmed or tape and
reeled by an outside source, you may not have this information carried over
from the outside packaging to the new reel. Customer part numbers and p.o.
information are usually carried over to the new reel.
As far as moisture/time sensitive components supplied in stick or matrix
tray form, I do not show evidence that there is any indication of moisture
sensitivity data or customer part number or purchase order information on
the sticks or trays. This information is supplied only on the outside bag
or box the sticks and trays were sealed in.
Hope it helps. --Dean Lillibridge
component engineer
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Tom Parkinson -
Quality System Manager
Sent: Thursday, August 16, 2001 11:39 AM
To: [log in to unmask]
Subject: Re: [TN] Moisture Sensitive Component Handling & Identification
Nancy
Our experience shows all the information is on the outside of the sealed
bag. Customer supplied parts are usually pre-marked (by the customer)
with their part number, reference designator, etc. on the outside only
and the bag is still sealed. For parts that we purchase, our receiving
inspection writes the info on the outside of the sealed bag. The sealed
bags are not opened until ready for use.
Tom
Nancy Reynolds/MKT/HQ/KEMET/US wrote:
>
> Please forgive the idiotic sounding questions below, but I am losing a
> battle and need some new ammunition.... If all you folks who work in
board
> assembly could give me a few quick yes or no answers, I would be quite
> grateful. Any of my fellow component manufacturers' comments are also
> welcome. Just 2 multiple choice questions...
>
> Regarding Moisture Sensitive components that are shipped to you in
dry-pack
> bags....
>
> 1. Is the moisture sensitivity-related labeling info (MSL, Bag Seal Date,
> Floor Life) found on...
> a) Moisture Barrier Bag only?
> b) Unit container (reel, tube, etc...) only?
> c) Both bag and reel?
>
> 2. Is the component/customer specific labeling info (Customer part number,
> PO number, etc...) found on...
> a) Moisture Barrier Bag only?
> b) Unit container (reel, tube, etc...) only?
> c) Both bag and reel?
>
> Thanks in advance for any answers you might have.
> Nancy Reynolds
>
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Date: Tue, 14 Aug 2001 19:33:59 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Mcanall <[log in to unmask]>
Subject: Re: Solder analysis results
MIME-Version: 1.0
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There is a method of 'cleaning the solder' by cooling it down in a specific
manner and the intermetalics will freeze out before the actual solder will
turn.
Contact Jess Baker of RPS, he can help you.
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Date: Tue, 14 Aug 2001 16:52:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Connector tilt, acceptable or not?
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hi,
looking at the leads in the plated through holes makes me believe that =
these holes are too big for the leads. if the holes weren't this big, =
i doubt that you'd need special tooling to prevent a misalignment =
problem.
phil
-----Original Message-----
From: Busko, Wolfgang [mailto:[log in to unmask]]
Sent: Tuesday, August 14, 2001 8:48 AM
To: [log in to unmask]
Subject: [TN] Connector tilt, acceptable or not?
Thanks Steve for your picture service !!!
To all,
I have some pictures on Steve=B4s page
http://stevezeva.homestead.com/index.html
<http://stevezeva.homestead.com/index.html>=20
The issue is that these connectors (Teradyne 2mm pitch) adapt our =
boards to
a backplane and the problem is that due to this obvious shift/tilt the
danger of damaging some of the male connector pins at the backplane if =
not
mounting these boards with the greatest possible caution is quite =
probable.
The CM in this case states that according to IPC A610 chapter 5.2.9 =
this is
within tolerance of 0.5mm as shown and refuses any rework or refund.
The question is, does 5.2.9 apply in this case? The "not acceptable"
criteria is what the discussion is all about. With, let=B4s say, =
caution and
some extra force the insertion is possible but I see the danger of =
breaking
backplane connector pins especially when customer service teams try to
change boards --( it happens from time to time and asks for a new =
backplane
or, if in the field, the change of the complete 19" rack)
To do the mounting of the connector properly is absolutely no problem =
and
has never been one until now that they changed their workflow and team =
for
this task.
The rework would be: Loosen the srew - attach mating connector module -
resolder over rework wave and the connector adjust automatically
We ourselves do have the "accept or not accept"-debate "now and here" =
and I
would like to hear what others have to say about the risks of rework
compared to the risk of damaging a more costly device.
Me no like this borderline cases,=20
Wolfgang
=20
=20
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Date: Thu, 16 Aug 2001 12:52:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Fallout
In-Reply-To: <OFBF20C89C.4260E679-ON85256AAA.0056BCD5@LocalDomain>
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Proper training of operators to identify polarity of parts plus good
assembly documentation solves this problem. We also have in-process
inspectors, post-reflow and post-wave inspectors, and final auditors that
look for this sort of thing along with solderability inspection of
components.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Nancy
Reynolds/MKT/HQ/KEMET/US
Sent: Thursday, August 16, 2001 11:49 AM
To: [log in to unmask]
Subject: Re: [TN] Fallout
I wince at the thought of operators picking up (POLAR) tantalum caps off
the floor and placing them by hand. Too much potential for placing in the
wrong polarity. Tantalum caps don't like that much...
Nancy Reynolds
Dean Lillibridge <[log in to unmask]>@IPC.ORG> on 08/15/2001 02:57:32 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Fallout
I agree with not using fallout if you can help it and certainly if it's
dropped to the floor, don't even chance it. I would, however, have little
reservation to a part that you can see and identify in the machine
(resistor
networks, marked I.C.'s, tantalum caps) when your assembly has to ship on
Friday and the customer has only sent you the exact amount required for the
build. This is especially common with vibratory feeder-fed parts. I've
had
several customers supply material in stick form and provide just what was
required by the build. I'm not going to hold off revenue for a fallen
tantalum cap. --Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of John Brewer
Sent: Wednesday, August 15, 2001 2:05 PM
To: [log in to unmask]
Subject: Re: [TN] Fallout
>>"are your operators consciencious about picking up/saving and
>>hand placing dropped parts?"
Oh man....with all due respect, I'd surely not advise doing this. With
the size
of most SMT parts, the lack of marking, and the relatively cheap cost of
most of them
compared with the cost of diagnose> test> rework> retest, etc, I'd
generally
advise not ever doing this!
If things are falling off in such quantities so as to make it
economically
feasible to reuse the parts, then the SMT process engineer should
investigate
the root cause and fix it, rather than try and reuse fallout....
Rgds and good luck!
John
-=-=-=-=-=-=-=-=-=-=--=--=-=-=-=-=
John Brewer
Square D Component Engineering
Raleigh NC
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Date: Tue, 14 Aug 2001 20:40:15 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Connector tilt, acceptable or not?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_ae.193b8980.28ab1eef_boundary"
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Hi Wolfgang,
...had the same observation that Phil did. Looking at where the leads coming
are through the board on the bottom, on the left side of the connector, the
leads are at the top of the holes, whereas on the rightside, they are towards
the bottom...so it does seem like there is some slop in the holes...
But as you state, things were okay before...what really changed? Sometimes,
when teams change, there may be some "tribal knowledge" that disappears along
with certain team members...
I work at a CM, and I can state that we do build things per our customers
needs that haven't been documented on their end...we try to put these
"special" things in our work instructions so that the product meets "Form,
fit, and function"...it can be a very daunting task sometimes...and sometimes
we get bloodied and bruised through it all.
In situations like this, it's really easy to point fingers at each other and
turn the whole situation in to a very negative deal...hard feelings on both
sides. I think that everything should be laid-out objectivley on the table,
understand what really happened, fix it, and then move on...
My guess is that your CM truely wants your business, and wants to do a good
job for you...but maybe made some changes in the team that once did the work,
and wasn't aware that things weren't documented as well as they should have
been...be it on their part or yours...
-Steve Gregory-
> hi,
>
> looking at the leads in the plated through holes makes me believe that
> these holes are too big for the leads. if the holes weren't this big, i
> doubt that you'd need special tooling to prevent a misalignment problem.
>
> phil
>
--part1_ae.193b8980.28ab1eef_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Wolfgang,
<BR>
<BR>...had the same observation that Phil did. Looking at where the leads coming
<BR>are through the board on the bottom, on the left side of the connector, the
<BR>leads are at the top of the holes, whereas on the rightside, they are towards
<BR>the bottom...so it does seem like there is some slop in the holes...
<BR>
<BR>But as you state, things were okay before...what really changed? Sometimes,
<BR>when teams change, there may be some "tribal knowledge" that disappears along
<BR>with certain team members...
<BR>
<BR>I work at a CM, and I can state that we do build things per our customers
<BR>needs that haven't been documented on their end...we try to put these
<BR>"special" things in our work instructions so that the product meets "Form,
<BR>fit, and function"...it can be a very daunting task sometimes...and sometimes
<BR>we get bloodied and bruised through it all.
<BR>
<BR>In situations like this, it's really easy to point fingers at each other and
<BR>turn the whole situation in to a very negative deal...hard feelings on both
<BR>sides. I think that everything should be laid-out objectivley on the table,
<BR>understand what really happened, fix it, and then move on...
<BR>
<BR>My guess is that your CM truely wants your business, and wants to do a good
<BR>job for you...but maybe made some changes in the team that once did the work,
<BR>and wasn't aware that things weren't documented as well as they should have
<BR>been...be it on their part or yours...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">hi,
<BR>
<BR>looking at the leads in the plated through holes makes me believe that
<BR>these holes are too big for the leads. if the holes weren't this big, i
<BR>doubt that you'd need special tooling to prevent a misalignment problem.
<BR>
<BR>phil
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_ae.193b8980.28ab1eef_boundary--
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Date: Wed, 15 Aug 2001 08:33:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Leonel Jay J. Manuel>" <[log in to unmask]>
Subject: Misplace component
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello Technetters,
We currently have misplace component at a level of 0.2%. Component placement, solder land proportionality, solderabilty of component terminal and amount of solder was verified to be within specs. Reflow profile was also based in standard settings.
Can you give us some other possible root causes of the above mention problem We are using 0402 SMD and SnPbAg no-clean solder paste.
Leonel Jay J. Manuel
Process Engineer
RF PCC Engineering
Philips Semiconductors Phils. Inc.
Office Tel: (6349) 5430001 to 25
: (632) 8445139 ext. 288
Fax No. : (632) 8445248 / (6349) 5430027
E-mail :[log in to unmask]
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Date: Tue, 14 Aug 2001 22:04:15 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Solder analysis results
MIME-Version: 1.0
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boundary="part1_8b.ae4b41e.28ab329f_boundary"
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Dave,
Surely, not ALL 1700-lbs.? Wooo-doggies! I can only imagine what a task that=
=20
would be!!! I've read some stuff that if you keep the pot static, and keep i=
t=20
at a stable temperature for a period (what this really is, I don't=20
know...there's varying opinions), the metals will seek their own level=20
(according to the different opinions, the copper will be towards the top),=20
then you scoop out out the top layer, and replenish what you've removed with=
=20
fresh bars.
The question that I have though, how did the pot get so out of balance with=20
copper? I've never had a problem with copper content, even when waving OSP=20
boards...tin levels dropping, yes. But not excessive copper...somebody throw=
=20
some pennies in the pot?
-Steve Gregory-
> RJ Klien Wassink suggests [bible p 169] pouring contaminated solder at abo=
ut
> 190=B0C through a 20 mesh stainless steel stariner to reduce copper conten=
t to
> 0.25%.
>=20
> Dave Fish
>=20
--part1_8b.ae4b41e.28ab329f_boundary
Content-Type: text/html; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable
<HTML><FONT FACE=3Darial,helvetica><FONT SIZE=3D2>Dave,
<BR>
<BR>Surely, not ALL 1700-lbs.? Wooo-doggies! I can only imagine what a task=20=
that=20
<BR>would be!!! I've read some stuff that if you keep the pot static, and ke=
ep it=20
<BR>at a stable temperature for a period (what this really is, I don't=20
<BR>know...there's varying opinions), the metals will seek their own level=20
<BR>(according to the different opinions, the copper will be towards the top=
),=20
<BR>then you scoop out out the top layer, and replenish what you've removed=20=
with=20
<BR>fresh bars.
<BR>
<BR>The question that I have though, how did the pot get so out of balance w=
ith=20
<BR>copper? I've never had a problem with copper content, even when waving O=
SP=20
<BR>boards...tin levels dropping, yes. But not excessive copper...somebody t=
hrow=20
<BR>some pennies in the pot?
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=3DCITE style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-=
LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">RJ Klien Wassink suggests [=
bible p 169] pouring contaminated solder at about
<BR>190=B0C through a 20 mesh stainless steel stariner to reduce copper cont=
ent to
<BR>0.25%.
<BR>
<BR>Dave Fish
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D3 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR=3D"#000000" SIZE=3D2 FAMILY=3D"SANSSERIF" FACE=3D"Ar=
ial" LANG=3D"0">
<BR></FONT></HTML>
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Date: Wed, 15 Aug 2001 09:24:43 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Edward Szpruch <[log in to unmask]>
Subject: Re: Solder analysis results
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Stephen,
In our HALS equipment this is daily routine.This daily treatment takes =
3
hours.
We are running also solder analysis 3 times a month with very =
consistent
results.Apart of daily treatment solder composition corrections are =
very
rare.As you mentioned,from time to time we have to add some pure tin.
Edward
Edward Szpruch
Eltek , Manager of Process Engineering
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Stephen S. Schiera [SMTP:[log in to unmask]]
> Sent: =E2 =E0=E5=E2=E5=F1=E8 14 2001 18:46
> To: [log in to unmask]
> Subject: Re: [TN] Solder analysis results
>=20
> You will want to take another sample after doing this. As you cool =
the
> pot
> the heavier metals (i.e. lead) will drop. When you remove the dross =
you
> will be removing tin also and could change the Sn/Pb ratio. You can =
buy
> pure tin to add back in to correct this.
>=20
> -----Original Message-----
> From: Edward Szpruch [mailto:[log in to unmask]]
> Sent: Tuesday, August 14, 2001 11:35 AM
> Subject: Re: Solder analysis results
>=20
>=20
> Phil,
> Copper content is 5.5 times higher that should be.
> Try to remove the excess copper by veeery slow cooling of your solder =
pot
> in
> static conditions.Around 190 centigrade you should get the first =
dross on
> the surface ,which is very rich in copper.Take it out.
> Good luck
> Edward
>=20
> Edward Szpruch
> Eltek , Manager of Process Engineering
> P.O.Box 159 ; 49101 Petah Tikva Israel
> Tel ++972 3 9395050 , Fax ++972 3 9309581
> e-mail [log in to unmask]
>=20
> > -----Original Message-----
> > From: Phil Nutting [SMTP:[log in to unmask]]
> > Sent: =E2 =E0=E5=E2=E5=F1=E8 14 2001 14:48
> > To: [log in to unmask]
> > Subject: [TN] Solder analysis results
> >
> > Ok folks, here is today's question.
> >
> > I just received a Certificate of Analysis (our first one) for the =
solder
> > in our Soltec Waver Solder machine. All parameters are "within
> > specification" except the percentage of copper which is at 1.6859. =
(Tin
> > is at 61.3% and Lead is at 36.99% and other stuff is at 0.0199%) =
We run
> > 63/37 in the wave. We only solder our own product, none of which =
goes
> > into "mission critical" applications. We normally build our =
product to
> > IPC-A-610C, Class 2.
> >
> > My question is two-fold. Should I worry about this? If so, how do =
I
> > fix it with 1700 pounds of solder in the solder pot?
> >
> > Thanks is advance for sharing your knowledge.
> >
> > Phil Nutting
> > Manufacturing Engineer
> > Kaiser Systems, Inc.
> >
> >
> =
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Date: Wed, 15 Aug 2001 06:52:39 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: solder balls
MIME-Version: 1.0
Content-Type: text/plain
The process is standard SMT with convection reflow using water soluble flux
and a very aggressive in-line aqueous cleaner. The solder balls seem to be
stuck under the chip components. They are very difficult to see, you have
to actually tilt the board sideways and look under the components.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Lush, Dorothy [SMTP:[log in to unmask]]
<mailto:[SMTP:[log in to unmask]]>
Sent: Tuesday, August 14, 2001 5:06 PM
To: 'TechNet E-Mail Forum.'; 'Marsico, James'
Subject: RE: solder balls
I like Loan's answer because solderballs normally form in the middle
along
the side of the chip component and not underneath. The normal
solderball is
formed when solder follows the flux under the component during
reflow then
is "squeezed" out to the side when the molten solder solidifies,
shrinks and
pulls the chip flush to the board surface. I could see the pulling
down
action stopped by, say, epoxy or soldermask non-existence or over
presence.
Are these balls being formed during SMD or solderwave do you think?
An
aqueous SMT paste process usually will wash this ball away. No-clean
paste
requires not forming them in the first place (and only allowing them
to stay
if they are imbedded in flux and less than a certain size, etc.) by
controlling stencil aperature, solder printing(x-y and z(volume)),
solder
choice and oven profile. Is this an aqueous or no-clean solder
paste/process
we are talking about?
Dorothy Lush
Manufacturing Engineer
> ----------
> From: Marsico, James[SMTP:[log in to unmask]]
<mailto:[SMTP:[log in to unmask]]>
> Reply To: TechNet E-Mail Forum.;Marsico, James
> Sent: Tuesday, August 14, 2001 12:34 PM
> To: [log in to unmask] <mailto:[log in to unmask]>
> Subject: soldr balls
>
> Here's a relatively basic SMT question, but we've haven't
experienced this
> before. We're seeing solder balls under (way under, in the
center) chip
> components. Any recommendations?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
<mailto:[log in to unmask] <mailto:[log in to unmask]> >
> 631-595-5879
>
>
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Date: Thu, 2 Aug 2001 08:59:54 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: BGA PCB mounting material thickness
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_84.19917137.289aa8ca_boundary"
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Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Wes!
All the boards that I've built with BGA devices on them have been .062"...had
one board with MicroBGA on it and it was down around .056". There was someone
on the TechNet a few weeks back talking about BGA on flex (with a stiffener
beneath)...
So no, there really isn't any minimum material thickness requirement that I
know of, it all depends on what your application is going to be.
-Steve Gregory-
> Hi,
>
> Is their a minimum required material thickness for PCB's with BGA components
> mounted on them? Our PCB supplier has said that they have not seen PCB's
> with BGA's on them with a material thickness of .062.
>
> Wes
> Siemens
>
--part1_84.19917137.289aa8ca_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Wes!
<BR>
<BR>All the boards that I've built with BGA devices on them have been .062"...had
<BR>one board with MicroBGA on it and it was down around .056". There was someone
<BR>on the TechNet a few weeks back talking about BGA on flex (with a stiffener
<BR>beneath)...
<BR>
<BR>So no, there really isn't any minimum material thickness requirement that I
<BR>know of, it all depends on what your application is going to be.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi,
<BR>
<BR>Is their a minimum required material thickness for PCB's with BGA components
<BR>mounted on them? Our PCB supplier has said that they have not seen PCB's
<BR>with BGA's on them with a material thickness of .062.
<BR>
<BR>Wes
<BR>Siemens
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Fri, 27 Jul 2001 09:16:13 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Thompson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Thompson <[log in to unmask]>
Subject: Assembleon PPS Pro Offline Programming?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I'm looking for feedback on from anyone using Assembleon (Philips) placement
equipment who is using their PPS Pro Offline Programming software. How do
you like it? How does it compare to the older PPS system on OS/2? Please
reply offline so we don't get into vendor specifics in the forum.
Thanks in advance.
Rick Thompson
Ventura Electronics Assembly
2655 Park Center Dr.
Simi Valley, CA 93065
+1 (805) 584-9858 x-304 voice
+1 (805) 584-1529 fax
[log in to unmask]
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Date: Mon, 23 Jul 2001 14:37:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Thorup, John" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Thorup, John" <[log in to unmask]>
Subject: Re: X-Ray Laminography Services
MIME-Version: 1.0
Content-Type: text/plain
Try SMT Unlimited in Freemont Ca. www.smtu.com
> -----Original Message-----
> From: Jorge Rodriguez [SMTP:[log in to unmask]]
> Sent: Monday, July 23, 2001 2:05 PM
> To: [log in to unmask]
> Subject: [TN] X-Ray Laminography Services
>
> Fellow Technetters
>
> I am looking for an X-Ray laminography Lab to inspect solder joints on
> some
> BGAs. Do you know of any lab that provides these type of service?
>
> Any information would be appreciated.
>
> Jorge Rodriguez
>
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Date: Thu, 2 Aug 2001 17:29:14 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: IPC 600
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One of my favorite topics - not!!!
The 6010 specification (6012 is to be "spec'd") NOT 600.
600 says IF you do an inspection or test this is what it should look like and
here
are examples of various defects and what is acceptable for each class of
product.
But it DOES NOT REQUIRE ANY INSPECTIONS OR TESTS.
6012 has a sampling plan and details how many and how often various tests and
inspections are to be performed.
Too many people certify their boards to 600 because they know they are good,
but
do no inspections or tests to confirm that fact.
OK, by now you probably get the picture that I think there is a
misunderstanding of the use of 600 vs 6012. People like to cert to 600
because it doesn't tie them to a specific number of tests.
Susan Mansilla
Robisan Lab
--part1_114.29c6593.289b202a_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>One of my favorite topics - not!!!
<BR>
<BR>The 6010 specification (6012 is to be "spec'd") NOT 600.
<BR>
<BR>600 says IF you do an inspection or test this is what it should look like and
<BR>here
<BR>are examples of various defects and what is acceptable for each class of
<BR>product.
<BR>But it DOES NOT REQUIRE ANY INSPECTIONS OR TESTS.
<BR>
<BR>6012 has a sampling plan and details how many and how often various tests and
<BR>inspections are to be performed.
<BR>
<BR>Too many people certify their boards to 600 because they know they are good,
<BR>but
<BR>do no inspections or tests to confirm that fact.
<BR>
<BR>OK, by now you probably get the picture that I think there is a
<BR>misunderstanding of the use of 600 vs 6012. People like to cert to 600
<BR>because it doesn't tie them to a specific number of tests.
<BR>
<BR>Susan Mansilla
<BR>Robisan Lab</FONT></HTML>
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Date: Wed, 8 Aug 2001 15:19:56 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Ionics again.
In-Reply-To: <A1630D6F27C0D21198AF00805F6135953E81AA@DDLSBS>
MIME-Version: 1.0
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Yes.
We should talk off line.
Mike Fenner
Indium Corporation of Europe
T: + 44 1908 580 400
F: + 44 1908 580 411
M: + 44 7810 526 317
W: www.indium.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Cathy Killen
Sent: Wednesday, August 08, 2001 2:51 PM
To: [log in to unmask]
Subject: [TN] Ionics again.
Hi everyone,
Can a no-clean process achieve ionic contamination <1.5ug cmsq according to
IPC TM-650 2.3.25 and a surface resistance > 5 X 10 (power of 8) according
to IPC TM-650.2.6.3.3?
If you believe it can be achieved, how?
How could you confirm it as an ongoing process control?
Cathy Killen
Training Instructor
[log in to unmask] <mailto:[log in to unmask]>
An Oasis of Training Excellence
* 028 38314305
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Date: Fri, 27 Jul 2001 13:47:50 -0400
Reply-To: Mark Charlton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mark Charlton <[log in to unmask]>
Organization: MSI of Central Florida, Inc.
Subject: Re: NHB 5300.4 (1C)
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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----- Original Message -----
From: "Rick Howieson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, July 27, 2001 10:24 AM
Subject: NHB 5300.4 (1C)
> Is there a place on the net where I can get a copy of NHB 5300.4 (1C) or
do
> I have to purchase this?
> Thanks,
> Rick Howieson
> www.deltagroupinc.com
>
> --------------------------------------------------------------------------
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Date: Thu, 2 Aug 2001 15:37:19 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Howieson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: Re: IPC 600
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Thanks Susan, but...IPC 600 clearly states "Printed boards should be of
uniform quality and shall conform to the IPC 6010 series". So, to conform to
this the tests and inspections outlined in 6010 must be performed.
Correct??? Maybe Jack can help us out a little?
Rick
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Thursday, August 02, 2001 2:29 PM
To: [log in to unmask]; [log in to unmask]
Subject: Re: [TN] IPC 600
One of my favorite topics - not!!!
The 6010 specification (6012 is to be "spec'd") NOT 600.
600 says IF you do an inspection or test this is what it should look like
and
here
are examples of various defects and what is acceptable for each class of
product.
But it DOES NOT REQUIRE ANY INSPECTIONS OR TESTS.
6012 has a sampling plan and details how many and how often various tests
and
inspections are to be performed.
Too many people certify their boards to 600 because they know they are good,
but
do no inspections or tests to confirm that fact.
OK, by now you probably get the picture that I think there is a
misunderstanding of the use of 600 vs 6012. People like to cert to 600
because it doesn't tie them to a specific number of tests.
Susan Mansilla
Robisan Lab
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<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=340501921-02082001>Thanks
Susan, but...IPC 600 clearly states "Printed boards should be of uniform quality
and shall conform to the IPC 6010 series". So, to conform to this the tests and
inspections outlined in 6010 must be performed. Correct??? Maybe Jack can help
us out a little?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=340501921-02082001>Rick</SPAN></FONT></DIV>
<BLOCKQUOTE>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, August 02, 2001 2:29
PM<BR><B>To:</B> [log in to unmask];
[log in to unmask]<BR><B>Subject:</B> Re: [TN] IPC
600<BR><BR></DIV></FONT><FONT face=arial,helvetica><FONT size=2>One of my
favorite topics - not!!! <BR><BR>The 6010 specification (6012 is to be
"spec'd") NOT 600. <BR><BR>600 says IF you do an inspection or test this
is what it should look like and <BR>here <BR>are examples of various defects
and what is acceptable for each class of <BR>product. <BR>But it DOES NOT
REQUIRE ANY INSPECTIONS OR TESTS. <BR><BR>6012 has a sampling plan and details
how many and how often various tests and <BR>inspections are to be performed.
<BR><BR>Too many people certify their boards to 600 because they know they are
good, <BR>but <BR>do no inspections or tests to confirm that fact. <BR><BR>OK,
by now you probably get the picture that I think there is a
<BR>misunderstanding of the use of 600 vs 6012. People like to cert to
600 <BR>because it doesn't tie them to a specific number of tests.
<BR><BR>Susan Mansilla <BR>Robisan Lab</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 2 Aug 2001 16:40:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: IPC 600
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a lot of the same can be said for IPC-610 to the J-STD-001.
Kat
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<DIV>a lot of the same can be said for IPC-610 to the J-STD-001.</DIV>
<DIV> </DIV>
<DIV>Kat</DIV></BODY></HTML>
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Date: Wed, 8 Aug 2001 16:34:14 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dean Lillibridge <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: Capacitor 0603 vs 0402
In-Reply-To: <48359946794DD511BA3A00508BA5563F0BF227@MERCURY>
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I'm also thinking of 0402 resistors in regards to this issue: thinking of
concerns of visual inspection (values not usually marked on 0402 resistors,
but 5% (E-24) Decades for resistors could be marked on 0603), lead
times/availability of parts (suppliers stocking 0402's????), and special
nozzle requirements for side 2 placement. We were unable to use our typical
adhesive displacement process for 0603's and smaller and had to resort to
stencil paste screening of side two. I believe different nozzle sizes for
pick and place units would also be required.
Dean
Lillibridge
NEWvENTURE
TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Pelkey, Glenn
Sent: Wednesday, August 08, 2001 3:56 PM
To: [log in to unmask]
Subject: [TN] Capacitor 0603 vs 0402
Hi all,
I'm brainstorming on risks and benefits of 0603 caps vs 0402
caps. If the cap value, voltage rating, dielectric material, terminations,
and use conditions are the same, would one be better than the other? My
thoughts are it would be a wash or at least not significant. Here's what I
have so far:
Benefits of 0402 vs 0603:
Smaller size reduces thermal stress/strain on solder joints from CTE or
board flexing.
Smaller size uses less real estate on board
Risks of 0402 vs 0603:
Equipment may have difficulty placing
Thinner dielectric spacing to achieve same capacitance, cap higher
failure rate
Smaller size, cracks easier to develop
Higher risk of tombstoning
What do you all think? I'm sure I missed something, maybe even
wrong on some of the above.
Thanks,
Glenn
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<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE>Capacitor 0603 vs 0402</TITLE>
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV><SPAN class=3D455001820-08082001><FONT color=3D#0000ff face=3DArial =
size=3D2>I'm=20
also thinking of 0402 resistors in regards to this issue: thinking =
of=20
concerns of visual inspection (values not usually marked on 0402 =
resistors, but=20
5% (E-24) Decades for resistors could be marked on 0603), lead=20
times/availability of parts (suppliers stocking 0402's????), and special =
nozzle=20
requirements for side 2 placement. We were unable to use our =
typical=20
adhesive displacement process for 0603's and smaller and had to resort =
to=20
stencil paste screening of side two. I believe different nozzle =
sizes for=20
pick and place units would also be required.</FONT></SPAN></DIV>
<DIV><SPAN class=3D455001820-08082001><FONT color=3D#0000ff face=3DArial =
size=3D2> &nbs=
p;  =
; =
&=
nbsp; &n=
bsp; =20
Dean Lillibridge</FONT></SPAN></DIV>
<DIV><SPAN class=3D455001820-08082001><FONT color=3D#0000ff face=3DArial =
size=3D2> &nbs=
p;  =
; =
&=
nbsp; =20
NEWvENTURE TECHNOLOGIES </FONT></SPAN></DIV>
<DIV><SPAN class=3D455001820-08082001><FONT color=3D#0000ff face=3DArial =
size=3D2> </FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Pelkey, =
Glenn<BR><B>Sent:</B>=20
Wednesday, August 08, 2001 3:56 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Capacitor 0603 vs=20
0402<BR><BR></FONT></DIV>
<P><FONT face=3DArial size=3D2>Hi all,</FONT> </P>
<P> <FONT face=3DArial =
size=3D2>I'm=20
brainstorming on risks and benefits of 0603 caps vs 0402 caps. =
If the=20
cap value, voltage rating, dielectric material, terminations, and =
use=20
conditions are the same, would one be better than the other? =
My=20
thoughts are it would be a wash or at least not significant. =
Here's=20
what I have so far:</FONT></P>
<P><B><FONT face=3DArial size=3D2>Benefits of 0402 vs =
0603:</FONT></B> <BR><FONT=20
face=3DArial size=3D2>Smaller size reduces thermal stress/strain on =
solder=20
joints from CTE or board flexing.</FONT> <BR><FONT face=3DArial =
size=3D2>Smaller=20
size uses less real estate on board</FONT> </P>
<P><B><FONT face=3DArial size=3D2>Risks of 0402 vs 0603:</FONT></B> =
<BR><FONT=20
face=3DArial size=3D2>Equipment may have difficulty placing</FONT> =
<BR><FONT=20
face=3DArial size=3D2>Thinner dielectric spacing to achieve same =
capacitance,=20
cap higher failure rate</FONT> <BR><FONT face=3DArial =
size=3D2>Smaller size,=20
cracks easier to develop</FONT> <BR><FONT face=3DArial =
size=3D2>Higher risk of=20
tombstoning</FONT> </P>
<P> <FONT face=3DArial =
size=3D2>What=20
do you all think? I'm sure I missed something, maybe even =
wrong on=20
some of the above.</FONT> </P>
<P><FONT face=3DArial size=3D2>Thanks,</FONT> </P>
<P><FONT face=3DArial size=3D2>Glenn</FONT> =
</P></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 2 Aug 2001 15:13:02 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard Hamilton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard Hamilton <[log in to unmask]>
Subject: Re: IPC 600
In-Reply-To: <71417DD0BB76D311B68300104B8FDEE820E9A2@SUPERVISOR>
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Rick,
Initally I would have thought that there was not a direct tie between them,
but according to what you quote, '...and shall conform...' I would take it
that it then does count and is a requirement.
Hey, if that is what the black and white says, that is what it says!
In the meantime, hope your having fun!
Richard
At 01:44 PM 8/2/01 -0600, you wrote:
>IPC-A-600 states "Printed boards should be of uniform quality and shall
>conform to the IPC-6010 series." and that "IPC-A-600 is a complementary
>document,..."
>Can one interpret this as IPC-6010 series being a requirement if IPC-A-600
>is being quoted?
>Thanks,
>Rick Howieson
>www.deltagroupinc.com
>
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Date: Tue, 24 Jul 2001 14:31:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Circuit boards in oil
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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We have made numerous circuits which have to operate continuously in oil.
The best designs use an all polyimide system including the base material as
well as the covercoats. Regards Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of John Fischbach
Sent: Tuesday, July 24, 2001 1:58 PM
To: [log in to unmask]
Subject: [TN] Circuit boards in oil
This is my first time on this message board.
I am looking for information on circuit boards operating in oil. The
application would be a flex/rigid board with SMT components on it operating
in a hydraulic pump. I am wondering if there is any experience on the
affects of the oil on the components, solder and the board.
Any information would be greatly appreciated!!!
Thank you,
John
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Date: Wed, 15 Aug 2001 19:02:31 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re:
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Phil
In his country, isn't it aquavit?
Brian
"Crepeau, Phil" wrote:
>
> hi,
>
> how many ounces of schnaps do you need before you start hearing mr. arrhenius?
>
> phil
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: Wednesday, August 15, 2001 3:29 AM
> To: [log in to unmask]
> Subject: Re: [TN]
>
> Grant
>
> You have a few problems, but nothing very severe. I agree that at 5 GHz,
> "no-clean" is a no-no. However, I'd be concerned with FR-4 at those
> frequencies as the Zo of your tracks can vary considerably with
> humidity. What is unclear is whether the product operates at ONLY -40°C
> or whether at higher temps, as well. If only there, then my guess is
> that you have no specific W/S flux-related problem. A Mr. Arrhenius told
> me that you should have much reduced corrosion risks and that cleaning
> and excellent drying with adequate equipment (i.e., 10% of what is
> available on the market) will give you the required results. Ionic
> contamination testing would be adequate for process control, once you
> have established your qualification conditions.
>
> Brian
>
> Grant Emandien wrote:
> >
> > Hi all out there,
> >
> > One of our customers is concerned with the level of flux residue (no clean)
> > present on RF boards - concern that the flux characteristics negatively
> > affects circuit perfomance (FR4 material, HASL finished is being used for
> > circuitry operating at 5GHz). He has thus requested to rather assemble using
> > water-soluble flux. With water-soluble flux of course comes cleanliness
> > issues which may result in latent defects due to entrapped corrosive flux
> > residue. The product is spec'd to operate, uncoated at -40deg.C. Any
> > insights into this dilemma?
> >
> > Thanks in anticipation.
> > Grant
> >
> > **********************************************************************
> > Notice:
> >
> > The information contained in this e-mail (including any attachments) may contain commercially sensitive or confidential information which may be legally privileged and is for the sole use of the intended recipient(s). If you are not, or believe you may not be, the intended recipient, you are hereby notified that any use, dissemination, copying, review, disclosure or action taken in reliance of this e-mail is prohibited and may be unlawful. If you have received this message in error, please notify the sender immediately by reply e-mail and delete all copies of the message.
> >
> > Any views expressed in this message are those of the individual sender unless expressly stated by the sender to be given on behalf of Tellumat (Pty) Ltd. Tellumat (Pty) Ltd disclaims liability for any unauthorised opinion or representation made by the sender on behalf of Tellumat (Pty) Ltd.
> >
> > No warranty is given by Tellumat (Pty) Ltd that the integrity or security of this e-mail (including any attachments) has been maintained through transmission, nor that the communication is free of virus, interception or interference.
> >
> > **********************************************************************
> >
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Date: Wed, 15 Aug 2001 09:09:58 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re:
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Grant,
Is the unit hermetically sealed? If so is he board baked prior to sealing and are you using dry nitrogen or something simular?
If not then moisture/contamination issues can cause problems.
David A. Douthit
Manager
LoCan LLC
Grant Emandien wrote:
> Brian,
>
> Thanks for the response - the unit operates between -40deg.C to 60deg.C
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: Wednesday, August 15, 2001 12:29 PM
> To: [log in to unmask]
> Subject: Re: [TN]
>
> Grant
>
> You have a few problems, but nothing very severe. I agree that at 5 GHz,
> "no-clean" is a no-no. However, I'd be concerned with FR-4 at those
> frequencies as the Zo of your tracks can vary considerably with
> humidity. What is unclear is whether the product operates at ONLY -40°C
> or whether at higher temps, as well. If only there, then my guess is
> that you have no specific W/S flux-related problem. A Mr. Arrhenius told
> me that you should have much reduced corrosion risks and that cleaning
> and excellent drying with adequate equipment (i.e., 10% of what is
> available on the market) will give you the required results. Ionic
> contamination testing would be adequate for process control, once you
> have established your qualification conditions.
>
> Brian
>
> Grant Emandien wrote:
> >
> > Hi all out there,
> >
> > One of our customers is concerned with the level of flux residue (no
> clean)
> > present on RF boards - concern that the flux characteristics negatively
> > affects circuit perfomance (FR4 material, HASL finished is being used for
> > circuitry operating at 5GHz). He has thus requested to rather assemble
> using
> > water-soluble flux. With water-soluble flux of course comes cleanliness
> > issues which may result in latent defects due to entrapped corrosive flux
> > residue. The product is spec'd to operate, uncoated at -40deg.C. Any
> > insights into this dilemma?
> >
> > Thanks in anticipation.
> > Grant
> >
> > **********************************************************************
> > Notice:
> >
> > The information contained in this e-mail (including any attachments) may
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> unless expressly stated by the sender to be given on behalf of Tellumat
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> >
> > No warranty is given by Tellumat (Pty) Ltd that the integrity or security
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Date: Thu, 16 Aug 2001 14:22:28 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jana L. Carraway" <[log in to unmask]>
Subject: Re: Easy Thursday Question!
In-Reply-To: <[log in to unmask]>
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Thank you for the responses, they have been quite helpful.
Best Regards,
Jana Carraway
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Wenger, George M
(George)
Sent: Thursday, August 16, 2001 11:45 AM
To: [log in to unmask]
Subject: Re: [TN] Easy Thursday Question!
The Lucent Specification for ENi/IAu is 0.075 microns (3 microinch) minimum
and 0.4 microns (16 microinches) for IAu and 3.75 +/-2.5 microns (150 +/-100
microinches) of ENi. In many cases it doesn't matter what your spec is
you're going to get 100 to 400 microinches of ENi depending on how they
control their plating bath.
Regards,
George
George M. Wenger, DMTS, (609)-639-2769 fax(2343), [log in to unmask]
Celiant Corporation
Box 900 Route 569 Carter Road
Princeton NJ 08542-0900 Hopewell, NJ 08525
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Date: Wed, 15 Aug 2001 10:46:15 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dorothy M. Lush" <[log in to unmask]>
Subject: Re: Misplace component
MIME-Version: 1.0
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Wolfgang,
What do you mean by "misplaced"?=20
Do you mean it is missing?
Do you mean it is tombstoning?
Do you mean it is misaligned?
Do you mean it is in the wrong location?
Dorothy Lush
> ----------
> From: Busko, Wolfgang[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Wednesday, August 15, 2001 4:22 AM
> To: [log in to unmask]
> Subject: AW: [TN] Misplace component
>=20
> Hi Leonel,
>=20
> if the processes are checked already and there seems to be no cause =
you
> might check your checks and focus on the results, if they clearly =
show
> that
> the particular process is definetly not the cause.
>=20
> For the solderability of bare boards and parts, there=B4s always a =
good
> portion of trust in solderability of a whole batch after checking =
some
> samples.
>=20
> Cleanliness is another major factor in this game, how is the handling
> done,
> is the dust removed prior to paste print (there=B4s always some of it =
right
> out of the sealed package), for how long do the printed boards wait =
until
> beeing reflowed, and what about temperature and humidity at these hot
> summer
> days, does your paste like it as it is now?
>=20
> Just a couple of things which I think can contribute to that what =
you=B4re
> seeing.
> If it happened suddenly, can you find out what has changed?
>=20
> Good luck
> Wolfgang
>=20
> =
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Databases >
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847-509-9700
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> =
------------------------------------------------------------------------=
--
> -------
>=20
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Date: Thu, 2 Aug 2001 13:22:51 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Bill Davis <[log in to unmask]>
Subject: BGA Inspection
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Hello all,
Could any one point me in the right direction to find quality BGA inspection equipment? Also, we are looking into doing assemblies with BGA's and I have never had any experience with them. Does any one have any good ideas where I can go to study up on problems, ideas, the equipment needed, the process, ect.... of placing BGA's. Any help you could give me would be greatly appreciated.
Thanks.
Bill Davis
Thermo Assembly & Test
970-242-5593
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Date: Thu, 16 Aug 2001 16:32:12 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: To wave or not to wave, that is the question...
In-Reply-To: <[log in to unmask]>
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To wave or not to wave, that is the question...Kevin:
Double check the preheat profile. Your cap manufacturer should have the
profile recommendations. Typically, there are two criteria: rate of rise
during preheat and maximum temperature change when the caps hit the wave.
Assuming that the caps are'nt damaged going in, it sounds like the
temperature change between the preheat and the wave may be excessive.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kevin Stokes
Sent: Thursday, August 16, 2001 2:26 PM
To: [log in to unmask]
Subject: [TN] To wave or not to wave, that is the question...
Old problem: mounting ceramic capacitors to the bottom side of an assembly
and your customer wants you to wave them on.
We are having problems with 0805 0.22 uF and 0.1 uF caps going through
wave and cracking during the process. We are following all of the standard
protocols (preheat, etc.). My understanding is that 0805s are typically
capable of handling this process.
Anyone got any ideas short of moving the cap to the top or doing a double
sided reflow?
Kevin
Kevin Stokes
Reliability Manager
Kimball Electronics Group
(812) 634-4207
------=_NextPart_000_000D_01C12671.03E0AB20
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE>To wave or not to wave, that is the question...</TITLE>
<META content=3D"MSHTML 5.00.2722.2800" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D220182822-16082001>Kevin:</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D220182822-16082001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D220182822-16082001>Double=20
check the preheat profile. Your cap manufacturer should have the =
profile=20
recommendations. Typically, there are two criteria: rate of rise =
during=20
preheat and maximum temperature change when the caps hit the wave. =
Assuming that the caps are'nt damaged going in, it sounds like the =
temperature=20
change between the preheat and the wave may be =
excessive.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D220182822-16082001></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D220182822-16082001>Don=20
Vischulis</SPAN></FONT></DIV>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Kevin =
Stokes<BR><B>Sent:</B>=20
Thursday, August 16, 2001 2:26 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] To wave or not to wave, that =
is the=20
question...<BR><BR></DIV></FONT>
<P><FONT face=3DArial size=3D2>Old problem: mounting ceramic =
capacitors to the=20
bottom side of an assembly and your customer wants you to wave them =
on.</FONT>=20
</P>
<P><FONT face=3DArial size=3D2>We are having problems with 0805 0.22 =
uF and 0.1 uF=20
caps going through wave and cracking during the process. We are=20
following all of the standard protocols (preheat, etc.). My=20
understanding is that 0805s are typically capable of handling this=20
process.</FONT></P>
<P><FONT face=3DArial size=3D2>Anyone got any ideas short of moving =
the cap to the=20
top or doing a double sided reflow?</FONT> <BR><BR><FONT face=3DArial=20
size=3D2>Kevin</FONT> </P>
<P><I><FONT color=3D#000080 face=3D"News Gothic MT">Kevin =
Stokes</FONT></I>=20
<BR><FONT face=3DArial size=3D2>Reliability Manager</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Kimball Electronics Group</FONT> <BR><FONT face=3DArial =
size=3D2>(812)=20
634-4207</FONT> </P></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 15 Aug 2001 14:31:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: FMA Labs in Northeast US
MIME-Version: 1.0
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Hi All,
With the drastic reduction occurring here at Lucent, I am going to be
without the services of our Evaluation / FMA Lab in Princeton for (at the
very least) the period it takes to relocate it. At the worst, it could be
shut down altogether. I am looking for another source to do the testing of
PWB's and Backplanes for conformance to our specifications and reliability
needs. This testing includes cross-sectioning with analysis, XRF, thermal
shock, pull tests, solderability evaluation, SIR/EM, SEM/EDX, and also FMA
of assembled boards. Ideally, I am looking for someone within driving
distance so that I can easily foster the relationship. However, I am open to
any viable suggestions. If this is a testimonial from users please respond
via the TechNet. If this is a lab promoting its capabilities, please contact
me directly at [log in to unmask] Thanks in advance for everyone's input.
P.S. I am also looking for a lab to provide me the direction, insight,
foresight, enthusiasm, and overall experience that George Wenger at our
Princeton Lab has provided me.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
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Date: Wed, 15 Aug 2001 14:32:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Panelized Boards
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Bob,
We have panelized several boards for ease of processing. We first added
a 1/2 inch v-score border around each individual board that contains the
necessary alignment holes for our semi-automatic through hole pick and
place machine. This added three benefits. 1) the alignment holes are
never filled with a component lead.
2) we can hold the board by the edges and stuff parts right out to the
edge.
3) we can hold the board in the wave solder without fixtures and still
have components right out to the edges of the board.
An added side benefit was that with multiple boards (up to 10 per panel,
assuming the total number of boards did not exceed our machine holding
and processing capability) in a panel we could reduce our machine build
time.
Depending on how deep the v-score was made will be a factor in how
flimsy the panel will be during processing.
For v-scoring info check out http://www.accusystemscorp.com/ and click
on "V-Scoring Service" and look for their FAQ page. It gives all the
gory details for v-scoring.
Phil Nutting
Manufacturing Engineer
Kaiser Systems, Inc.
-----Original Message-----
From: bbarr [mailto:[log in to unmask]]
Sent: Wednesday, August 15, 2001 1:46 PM
To: [log in to unmask]
Subject: [TN] Panelized Boards
I have a 3.5" x 5.5", .063" thick board we will be building in somewhat
high
quantities (3,000+/month). This size board is just on the edge as far as
having to put it into a basket to run through our in-line aqueous
cleaner to
keep it from moving around. I do not want the operators to have to put
this
many boards in baskets during production runs. So, my thoughts have
turned
to panelizing these boards, perhaps in a 2x2 arrangement. This would go
through the cleaner with no problem. I do not have a lot of experience
in
the best designs for panels. What are the advantages/disadvantages
between
v-score and tabs? If using tabs, how many are required to maintain the
rigidity of the panel during reflow? Does there have to be a border
around
the boards? Are fiducials required on the panel in addition to the
fiducials
already on the individual boards? Any other issues I may have missed?
Thanks.
Bob
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Date: Fri, 3 Aug 2001 11:03:23 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: UV and Flex
In-Reply-To: <FE89B36841C1D411AB9D0002555830D739D835@BARRY>
MIME-Version: 1.0
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Ted:
Suggest you check with DuPont regarding the effects of UV on Kapton. Their
web site http://www.dupont.com/kapton/general/sumofprop.html would be a good
place to start. Keep in mind that your clear cover might act as an UV
fiter.
Don Vischulis
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Date: Mon, 23 Jul 2001 09:12:28 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Inspection Criteria
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
John,
I have never seen any recommendations as to how long people should stare at
a solder joint, nor, think I, that giving a time is possible - the time
required to inspect a joint is entirely in the eye of the beholder (or
Inspector) and depends on things like the eyesight of your inspector, how
quick he/she is at assimilating and interpreting what he/she is seeing, how
critical it is to have a completely defect-free joint and how difficult it
is to detect a particular defect visually. Such human variables and other
things in visual inspection are beyond the scope of most specs. They just
tell you what to do and how to do it - how long it takes is up to the
individual.
Having said that, it sounds like your inspectors are desparate to justify
their existence. If you have your suppliers well house-trained, it should
be possible to do away with further inspection operations and accept their
certification. Remember, you can't inspect quality into a job - it merely
catches some (note some, not all) defects and costs a lot of extra money
besides. If you're only getting one minor failure in 1000 units, I'ld
either move to batch sampling at in-coming inspection, or remove in-coming
inspection altogether until such time as you have problems with the product
again. Have you asked your inspectors why they feel they have to take so
long to inspect these boards so closely?
Pete Duncan
John Fahey
<jfahey@ECHEL To: [log in to unmask]
ON.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Sent by: Subject: [TN] Inspection Criteria
TechNet
<[log in to unmask]
ORG>
07/21/01
04:32 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
John Fahey
Do any IPC standards (particularly IPC-610-C)recommend standard
magnification, distance, and time for inspecting surface mount solder
joints?
Some of our internal inspectors can spend up to 5 mins per small PCB assy
under 30x magnification to investigate and find minor fracture in solder
joint(say 1/1000 units)supplied by our CM's. These units have already gone
through 3 rounds on 100% visual inspection at the CM. These units pass
Functional test.
My worry is that our inspectors feel that they NEED to find visual defects
in order to show that they are doing their job effectively! Unfortunately,
finding 1 defect in a batch of 1000 assemblies under high magnification
with ample time to twist and turn the board under inspection, results in us
having to do 100% inspection on every unit from our CMs!
Does anyone have any input at all on this issue?
Thanks.
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Date: Sat, 21 Jul 2001 02:08:53 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Scott Mcanall <[log in to unmask]>
Subject: Re: Solderability tests
MIME-Version: 1.0
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www.rpstest.com or www.rpsautomation.com. we make all types of solderability
testers
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Date: Fri, 3 Aug 2001 14:23:39 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Encoder with contamination.Soldering or Supplier process.
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Yes, years ago. Our supplier used a type of lubricant that broke down with
age. We special ordered the encoder without lubricant there after. They
worked fine without for many years. Some, I am sure, are still in use.
Guy Ramsey
Senior Lab Technician / Instructor
E-Mail: [log in to unmask] <mailto:[log in to unmask]>
Ph: (610) 362-1200 x107
Fax: (610) 362-1290
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Valdez, Raul (R.)
Sent: Friday, August 03, 2001 1:30 PM
To: [log in to unmask]
Subject: [TN] Encoder with contamination.Soldering or Supplier process.
Hello,
We are using rotary switch encoders on our application and they are failing,
after some were opened, certain kind of yellow grease was found, we are not
sure if that's flux since the encoder is being soldered to the board thru
wave soldering.
After cleaning the "defective" encoder with alcohol the encoder works fine.
Anyone has had a similar experience?? soldering process or encoder supplier
fault??
Please help.
Thanks.
Raúl Valdéz.
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Date: Wed, 1 Aug 2001 22:36:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Malewicz Wesley <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Malewicz Wesley <[log in to unmask]>
Subject: BGA PCB mounting material thickness
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi,
Is their a minimum required material thickness for PCB's with BGA components
mounted on them? Our PCB supplier has said that they have not seen PCB's
with BGA's on them with a material thickness of .062.
Wes
Siemens
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Date: Mon, 23 Jul 2001 08:40:36 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Inspection Criteria
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
Content-Type: text/plain; charset=US-ASCII
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Hi John,
Required magnification depends on minimum land-width for the inspected =
device:
>1. mm 1.75X
>0.5 to 1.0 mm 4X
0.25 to 0.5 mm 10X
<0.25 mm 20X
(data from IPC-A-610C)
Maybe you have some data about field returns ? It would be interesting =
to see how many of the defects that occur at the end-users are related to =
those so-called defective solder joints that your inspectors see. Probably =
none. Than better work on real issues !
Kind regards,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> John Fahey <[log in to unmask]> 07/20 10:32 pm >>>
Do any IPC standards (particularly IPC-610-C)recommend standard
magnification, distance, and time for inspecting surface mount solder
joints?
Some of our internal inspectors can spend up to 5 mins per small PCB assy
under 30x magnification to investigate and find minor fracture in solder
joint(say 1/1000 units)supplied by our CM's. These units have already gone
through 3 rounds on 100% visual inspection at the CM. These units pass
Functional test.
My worry is that our inspectors feel that they NEED to find visual defects
in order to show that they are doing their job effectively! Unfortunately,
finding 1 defect in a batch of 1000 assemblies under high magnification
with ample time to twist and turn the board under inspection, results in =
us
having to do 100% inspection on every unit from our CMs!
Does anyone have any input at all on this issue?
Thanks.
---------------------------------------------------------------------------=
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Date: Tue, 24 Jul 2001 16:47:21 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
gleason <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: gleason <[log in to unmask]>
Subject: Re: Inspection Jig/Support
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0014_01C11460.4EB0A560"
This is a multi-part message in MIME format.
------=_NextPart_000_0014_01C11460.4EB0A560
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Mike,
We have experience in a few different methods to accomplish that. Give me a
call offline and we can see what applies to your situation.
Chuck Smith
GSC
972-494-1911
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Sewell
Sent: Tuesday, July 24, 2001 2:30 PM
To: [log in to unmask]
Subject: [TN] Inspection Jig/Support
I'm looking for a moveable/articulating jig to hold a PWB during visual
inspection with a microscope. The issue is the board's weight over 9 -
10hr
shift wearing down the inspector(s). Dunno if this is would be a
counterbalanced arm/swivel ... curious to see if anyone has any thoughts
or
similar experiences.
Thanks in advance,
Mike Sewell
------=_NextPart_000_0014_01C11460.4EB0A560
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 5.50.4207.2601" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2>Mike,</FONT></SPAN></DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2>We=20
have experience in a few different methods to accomplish that. Give me a =
call=20
offline and we can see what applies to your =
situation.</FONT></SPAN></DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2>Chuck=20
Smith</FONT></SPAN></DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2>GSC</FONT></SPAN></DIV>
<DIV><SPAN class=3D620284523-24072001><FONT face=3DArial color=3D#0000ff =
size=3D2>972-494-1911</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Mike =
Sewell<BR><B>Sent:</B>=20
Tuesday, July 24, 2001 2:30 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Inspection=20
Jig/Support<BR><BR></FONT></DIV><FONT face=3Darial,helvetica><FONT =
size=3D2>I'm=20
looking for a moveable/articulating jig to hold a PWB during visual=20
<BR>inspection with a microscope. The issue is the board's =
weight over 9=20
- 10hr <BR>shift wearing down the inspector(s). Dunno if this is =
would=20
be a <BR>counterbalanced arm/swivel ... curious to see if anyone has =
any=20
thoughts or <BR>similar experiences. <BR><BR>Thanks in advance, =
<BR>Mike=20
Sewell </FONT></FONT></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 15 Aug 2001 15:02:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: FMA Labs in Northeast US
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Robert,
Here are two "close" choices I know of:
Trace Labs East,
5 North Park Drive
Hunt Valley Maryland 21030
303-683-4806
EMPF/ACI
One International Plaza, Suite 150,
Philadelphia, Penn 19113
610-362-1200
regards,
Bev Christian
Research in Motion
Waterloo, Ontario
Canada
519-888-7465
-----Original Message-----
From: Furrow, Robert Gordon (Bob) [mailto:[log in to unmask]]
Sent: August 15, 2001 2:31 PM
To: [log in to unmask]
Subject: [TN] FMA Labs in Northeast US
Hi All,
With the drastic reduction occurring here at Lucent, I am going to be
without the services of our Evaluation / FMA Lab in Princeton for (at the
very least) the period it takes to relocate it. At the worst, it could be
shut down altogether. I am looking for another source to do the testing of
PWB's and Backplanes for conformance to our specifications and reliability
needs. This testing includes cross-sectioning with analysis, XRF, thermal
shock, pull tests, solderability evaluation, SIR/EM, SEM/EDX, and also FMA
of assembled boards. Ideally, I am looking for someone within driving
distance so that I can easily foster the relationship. However, I am open to
any viable suggestions. If this is a testimonial from users please respond
via the TechNet. If this is a lab promoting its capabilities, please contact
me directly at [log in to unmask] Thanks in advance for everyone's input.
P.S. I am also looking for a lab to provide me the direction, insight,
foresight, enthusiasm, and overall experience that George Wenger at our
Princeton Lab has provided me.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Strategic Supply Global Account Manager
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
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Date: Wed, 15 Aug 2001 12:04:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Lush, Dorothy" <[log in to unmask]>
Subject: Re: Fallout
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If the components are small chip parts they are making little mosaic pendant
jewelry.
But seriously, fallout takes a number of forms and part of this is because
of people who are not paid to think (PNPTT). Every reel has a leader at the
beginning and the end of the reel of empty pockets that usually wraps around
the reel at least once. Some PNPTT's count the empty and loaded pockets
which makes their count wrong in many cases. PNPTT's can be located at the
OEM and/or the CM. Of course, suppliers/manufacturers never miscount.
SMD feeders have at least one inch of strip/carrier where the top tape is
pulled back exposing the parts to a high chance of loss especially when they
are small components. Loading/setting-up the feeder is done at setup which
is some distance in time and space from production.
If a strip of parts is cut sometimes the cutting tool cuts into a pocket
leaving the back door wide open and the part is lost on some floor somewhere
along the way.
Everytime the placement machine stops and a particular feeder is pulled out
and checked is another opportunity to lose parts. I have found this occurs
more frequently with plastic carriers than with paper carriers on the
smaller chip parts. It seems the tape on top has a glue that is either
weaker and breaks 10 times more often or the glue is stronger or stickier
(so it sticks to the feeder when pulled back) and the tape breaks therefore
cannot be pulled back to expose the next part and the machine stops.
Placement machines will reject parts and lose parts for various good and bad
reasons.
Bill of materials (BOM's) are sometimes off in their quantities (this
happens much more in prototype and the transistion to full production than
in full production).
Rework needs extra parts. The smaller the part and the less reworkable the
part the more extra parts you need.
IC type parts with leads tend to get damaged at the beginning of a strip
with no empty leader pockets.
Bad layout will result in many more defects: lost part, tombstone,
misaligned, bridging. If you couple this with nonreworkable part you will
need extra parts.
I was an engineer on an account that had some RF boards. After the first
disaster I ordered my own attrition that was based on the part cost,
qty/assembly and likelyhood of the part to get lost or come in damaged.
Frankly, the time lost ordering parts and the line down time (somewhere
between 2K and 6K/hour, depending) waiting for parts pays for most
attrition.
The most difficult thing here is that most component buyers can only order
for a build qty with no attrition and this all goes back to software
programs and their inflexability.
Dorothy Lush
> ----------
> From: Rick Howieson[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.
> Sent: Wednesday, August 15, 2001 6:20 AM
> To: [log in to unmask]
> Subject: Fallout
>
> Our purchasing department believes people are taking components home and
> making necklaces...hehehe. So my question, what is the typical
> loss/fallout
> of smt components, on reel, does one see?
> Thanks,
> Rick Howieson
> Delta Group Electronics, Inc.
>
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=========================================================================
Date: Wed, 25 Jul 2001 08:58:37 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, Ivy <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ivy <[log in to unmask]>
Subject: Sorry~~ I got a Virus
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Sorry, I got a Virus~~=20
If you received a File about 677-001P or CAR or ETC.... Pls do not open =
it..... =20
Sorry ~~~~~ > <=20
Regards,
Ivy
------=_NextPart_000_00AD_01C114E7.FE633540
Content-Type: text/html;
charset="big5"
Content-Transfer-Encoding: quoted-printable
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial>Sorry, I got a Virus~~ </FONT></DIV>
<DIV><FONT face=3DArial>If you received a File about 677-001P or CAR or=20
ETC.... Pls do not open it..... </FONT></DIV>
<DIV><FONT face=3DArial>Sorry ~~~~~ > < </FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial>Regards,</FONT></DIV>
<DIV><FONT face=3DArial>Ivy</FONT></DIV></BODY></HTML>
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Date: Mon, 23 Jul 2001 08:47:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Inspection Criteria
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I prefer to have the inspectors refresh train on the minimum requirements =
annually. I also am always looking for good photo's that I can put out to =
the inspection group of minimum acceptable. The IPC-610 Rev C has some =
really good photo's and I back up this with actual photo's. I make a lot =
of the minimum acceptable photo's and get lots of copies. I have been =
doing this since I first became an IPC-610 C instructor. I also include =
these in my outside training that I do for the local tech colleges. =20
A couple of things that are in place here are:=20
1. I double check defects noted by performing secondary inspections =
periodically and on all first builds. =20
2. If a defect is questioned the person making the rejection has to prove =
in the IPC-610 why it is a defect exactly by clause. =20
I have an inspector that is always looking for the mole hill. I appreciate=
her toughness because the processes before her know that she will be =
looking at everything with a fine tooth comb and they do perform better =
knowing that. I also like the fact that she is so thorough in her =
inspections and everything gets questioned. Luckily she also really =
understands the minimum requirements and applies the criteria correctly. =
She provides a tremendous amount of feedback for borderline processes. =
This allows us to really utilize minimum acceptable as a process improvemen=
t opportunity. =20
Kathy=20
--=_22784806.0B6A06BD
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY style="FONT: 10pt Haettenschweiler; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>I prefer to have the inspectors refresh train on the minimum requirements
annually. I also am always looking for good photo's that I can put out to
the inspection group of minimum acceptable. The IPC-610 Rev C has some
really good photo's and I back up this with actual photo's. I make a lot
of the minimum acceptable photo's and get lots of copies. I have been
doing this since I first became an IPC-610 C instructor. I also include
these in my outside training that I do for the local tech colleges. </DIV>
<DIV> </DIV>
<DIV>A couple of things that are in place here are: </DIV>
<DIV>1. I double check defects noted by performing secondary inspections
periodically and on all first builds. </DIV>
<DIV>2. If a defect is questioned the person making the rejection has to prove
in the IPC-610 why it is a defect exactly by clause. </DIV>
<DIV> </DIV>
<DIV>I have an inspector that is always looking for the mole hill. I
appreciate her toughness because the processes before her know that she will be
looking at everything with a fine tooth comb and they do perform better knowing
that. I also like the fact that she is so thorough in her inspections and
everything gets questioned. Luckily she also really understands the
minimum requirements and applies the criteria correctly. She provides a
tremendous amount of feedback for borderline processes. This allows us to
really utilize minimum acceptable as a process improvement opportunity.
</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Fri, 17 Aug 2001 10:40:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dean Lillibridge <[log in to unmask]>
Subject: Re: To wave or not to wave, that is the question...
In-Reply-To: <[log in to unmask]>
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came across some technical reference articles on behalf of AVX CORPORATION.:
1) "Factors responsible for Thermal Shock Behavior of Chip Capacitors"
from the 37th Electronic Components Conference 1987, pp 145-156.
by B. Rawal, R. Ladew, and R. Garcia.
2) "Surface Mount Soldering Tchniques and Thermal Shock in Mulitlayer
Ceramic Capacitors" AVX Technical Information Series 1987 4pp.
by J. Maxwell.
Hope it helps. --Dean Lillibridge
NEWvENTURE TECHNOLOGIES
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kevin Stokes
Sent: Thursday, August 16, 2001 4:26 PM
To: [log in to unmask]
Subject: [TN] To wave or not to wave, that is the question...
Old problem: mounting ceramic capacitors to the bottom side of an
assembly and your customer wants you to wave them on.
We are having problems with 0805 0.22 uF and 0.1 uF caps going through
wave and cracking during the process. We are following all of the standard
protocols (preheat, etc.). My understanding is that 0805s are typically
capable of handling this process.
Anyone got any ideas short of moving the cap to the top or doing a
double sided reflow?
Kevin
Kevin Stokes
Reliability Manager
Kimball Electronics Group
(812) 634-4207
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<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<TITLE>To wave or not to wave, that is the question...</TITLE>
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial =
size=3D2>came=20
across some technical reference articles on behalf of AVX=20
CORPORATION.:</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial size=3D2> 1) "Factors =
responsible for=20
Thermal Shock Behavior of Chip Capacitors" from the 37th Electronic =
Components Conference 1987, pp 145-156.</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial size=3D2> by B. Rawal, R. Ladew, and R.=20
Garcia.</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial size=3D2> 2) "Surface =
Mount=20
Soldering Tchniques and Thermal Shock in Mulitlayer Ceramic =
Capacitors" AVX=20
Technical Information Series 1987 4pp.</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial size=3D2> by J. Maxwell.</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial=20
size=3D2> &nbs=
p;  =
; =20
Hope it helps. --Dean=20
Lillibridge</FONT></SPAN></DIV>
<DIV><SPAN class=3D83293514-17082001><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT></SPAN><SPAN class=3D83293514-17082001><FONT =
color=3D#0000ff=20
face=3DArial=20
size=3D2> &nbs=
p;  =
; =
&=
nbsp;=20
NEWvENTURE TECHNOLOGIES</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Kevin =
Stokes<BR><B>Sent:</B>=20
Thursday, August 16, 2001 4:26 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] To wave or not to wave, that =
is the=20
question...<BR><BR></FONT></DIV>
<P><FONT face=3DArial size=3D2>Old problem: mounting ceramic =
capacitors to the=20
bottom side of an assembly and your customer wants you to wave them=20
on.</FONT> </P>
<P><FONT face=3DArial size=3D2>We are having problems with 0805 0.22 =
uF and 0.1=20
uF caps going through wave and cracking during the process. We =
are=20
following all of the standard protocols (preheat, etc.). My=20
understanding is that 0805s are typically capable of handling this=20
process.</FONT></P>
<P><FONT face=3DArial size=3D2>Anyone got any ideas short of moving =
the cap to=20
the top or doing a double sided reflow?</FONT> <BR><BR><FONT =
face=3DArial=20
size=3D2>Kevin</FONT> </P>
<P><I><FONT color=3D#000080 face=3D"News Gothic MT">Kevin =
Stokes</FONT></I>=20
<BR><FONT face=3DArial size=3D2>Reliability Manager</FONT> <BR><FONT =
face=3DArial=20
size=3D2>Kimball Electronics Group</FONT> <BR><FONT face=3DArial =
size=3D2>(812)=20
634-4207</FONT> </P></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Mon, 23 Jul 2001 09:12:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Pelchat, Janice" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Pelchat, Janice" <[log in to unmask]>
Subject: Re: Inspection Criteria
MIME-Version: 1.0
Content-Type: text/plain
AbsoLUTELY declined! I hate rework, I hate the rework process flow, I hate
REinspection, I hate double & triple handling of boards.
Janice Pelchat
Benchmark Electronics
> -----Original Message-----
> From: Werner Engelmaier [SMTP:[log in to unmask]]
> Sent: Monday, July 23, 2001 8:43 AM
> To: [log in to unmask]
> Subject: Re: [TN] Inspection Criteria
>
> Hi Pete,
> You correctly state, that: "you can't inspect quality into a job - it
> merely
> catches some (note some, not all) defects." This is certainly true, but
> manual inspections also 'catch' a lot of deviations of workmanship
> standards
> (or other things that the inspector for some reason does not like) that
> are
> nor really defects and have no real impact on quality or reliability. Now,
> after repair or rework of these 'defects'--has the quality/reliability
> improved or declined?
>
> Werner Engelmaier
>
> --------------------------------------------------------------------------
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Date: Mon, 23 Jul 2001 16:01:37 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Stephen Brown <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephen Brown <[log in to unmask]>
Organization: Xyratex
Subject: Component Mass / Pad Geometries
MIME-Version: 1.0
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Question?
There is a formula somewhere which I can use to calculate the maximum
allowable mass of a component in relation to the pad lands. Basically I
want to make sure our designers do not put components on the underside
of the PCB which are going to fall off during doublesided reflow.
I would like to point out that this is a design for manufacturability
question, not an attack on the tentative grasp on reality some card
designers have.
Steve.
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Date: Thu, 26 Jul 2001 08:06:12 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Hare <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Hare <[log in to unmask]>
Subject: Re: solder paste with 2% silver
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I did my PhD thesis on the creep behavior of SN62 versus SN63 (UW - 1995).
SN62 (62Sn-36Pb-2Ag) was significantly more creep resistant and had a higher
elastic modulus than SN63. This might make it more resistant to creep
rupture failure and thermal fatigue (due to creep-fatigue interactions).
Much of this research is published as cited below.
Best regards,
Ed Hare
1995 "Stress Relaxation Behavior of Eutectic Tin-Lead Solder", Journal of
Electronic Materials, October 1995.
1994 "Stress Relaxation Behavior of Eutectic Tin-Lead Solder with Silver and
Copper Additions", Ph.D. Dissertation, University of Washington, 1994.
1993 "The Effect of Ag Additions on the Stress Relaxation Behavior of
Eutectic Tin-Lead Solder", TMS Annual Meeting, Denver, CO.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Barton
Sent: Thursday, July 26, 2001 7:35 AM
To: [log in to unmask]
Subject: Re: [TN] solder paste with 2% silver
One other reason given for preference of 62Sn/36Pb/2Ag is that it is a
ternary alloy with a 'pasty' range between 177deg C and 189 deg. C as
opposed to 63Sn/37Pb which is a eutectic. This slower transition from
solidus to liquidous is helpful when soldering low mass parts that are prone
to tombstoning such as 0402 and 0201.
Also according to the data published by the International Tin Research
Institute the 2% silver version gives a stronger soldered joint.
Pete Barton
ACW Technology Ltd
===== Original Message from "TechNet E-Mail Forum." <[log in to unmask]> at
26/07/01 14:31
>>From "Soldering in Electronics" by Klein Wassink:
>
>"Note on solder alloy composition:
>Solder paste in hybrid circuit technology (for thick-film circuits) usually
has a metal
composition of tin62-lead36-silver2. It should be realised that the addition
of silver is not at all necessary for the silver (-palladium) metallisation
of the
>components, but for the much thinner silver-palladium conductors on the
tick-film substrates.
The use of the more expensive silver containing alloy, instead of the common
tin60-lead40 alloy, for (relow) soldering on printed boards with copper
>solder lands is not based on technological necessity, but sometimes on
>better availability of this alloy (in the form of paste) and in most cases
merely on habit.
For the rest: with silver loaded alloy no harm is done !"
>
>Kind regards,
>
>Daan Terstegge
>SMT Centre
>Thales Communications
>Unclassified mail
>Personal Website: http://www.smtinfo.net
>
>
>
>
>>>> "Kasprzak, Bill (sys) USX" <[log in to unmask]> 07/26 1:54 pm >>>
>To all:
>
>I've been reading, with great interest, the responses so far to the use of
>2% silver paste. I am not being critical of the folks who responded so far
>but, each one cites a "reported" or "understood" advantage to using 2%
>paste.
>
>I have also heard some of same reasons for considering a switch to a 2%
>silver paste. Can any of the metallurgists on this forum confirm some of
>these reported advantages and perhaps recommend that given x,y, and z, one
>should consider using 2% silver solder alloys?
>
>Good topic.
>
>Bill Kasprzak
>Moog Inc., Electronic Assembly Engineering
>
>
>> -----Original Message-----
>> From: Eric Christison [SMTP:[log in to unmask]]
>> Sent: Thursday, July 26, 2001 4:20 AM
>> To: [log in to unmask]
>> Subject: Re: [TN] solder paste with 2% silver
>>
>> > I always understood that you had to use a paste with 2% silver if you
>> > were using components
>> > with terminations containing Palladium. The 2% silver is also supposed
>> to
>> > five you a shinier
>> > finished solder joint.
>> >
>> > Steve.
>> >
>> > Larry Koens wrote:
>> >
>> > > Got a question for everyone,
>> > >
>> > > I just switched companies and the new company that I'm with now uses
a
>> > > 62/36/2 solder paste. I've always used the 63/37 formula. The guys
who
>> > > decided to use the 2% silver are no longer with the company. My
>> > question
>> > > to you is, why would they want the 2% silver in the paste? They know
>> > > something I don't?!
>> > >
>>
>> The silver should give the alloy higher strength, better creep resistance
>> and a higher melting point. Perhaps your application benefits from one of
>> these differences?
>>
>> Regards,
>>
>>
>>
>> Eric Christison
>>
>> -------------------------------------------------------------------------
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>
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Date: Thu, 26 Jul 2001 10:50:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Hare <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Hare <[log in to unmask]>
Subject: Re: solder paste with 2% silver
In-Reply-To: <[log in to unmask]@eric>
MIME-Version: 1.0
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Eric,
I don't know for sure, but I believe it is a combination of solid solution
strengthening of the tin phase and a more macro mechanism involving pinning
of grain boundaries by the Ag3Sn intermetallic phase. I did not resolve the
deformation mechanisms as part of my research. I was more interested in
empirical constitutive relationships of Ag (& Cu) concentration versus creep
rate because that data was not available at the time to support finite
element modeling of solder joints.
Best regards.
Ed
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Eric Christison
Sent: Thursday, July 26, 2001 10:02 AM
To: [log in to unmask]
Subject: Re: [TN] solder paste with 2% silver
Ed,
As a matter of interest. Are the improved mechanical properties a result of
the silver atoms limiting dislocations in the Xtal structure?
Regards,
>
> I did my PhD thesis on the creep behavior of SN62 versus SN63 (UW -
> 1995).
> SN62 (62Sn-36Pb-2Ag) was significantly more creep resistant and had a
> higher
> elastic modulus than SN63. This might make it more resistant to creep
> rupture failure and thermal fatigue (due to creep-fatigue interactions).
> Much of this research is published as cited below.
>
> Best regards,
> Ed Hare
>
> 1995 "Stress Relaxation Behavior of Eutectic Tin-Lead Solder", Journal
> of
> Electronic Materials, October 1995.
>
> 1994 "Stress Relaxation Behavior of Eutectic Tin-Lead Solder with
> Silver
> and
> Copper Additions", Ph.D. Dissertation, University of Washington, 1994.
>
> 1993 "The Effect of Ag Additions on the Stress Relaxation Behavior of
> Eutectic Tin-Lead Solder", TMS Annual Meeting, Denver, CO.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Barton
> Sent: Thursday, July 26, 2001 7:35 AM
> To: [log in to unmask]
> Subject: Re: [TN] solder paste with 2% silver
>
>
> One other reason given for preference of 62Sn/36Pb/2Ag is that it is a
> ternary alloy with a 'pasty' range between 177deg C and 189 deg. C as
> opposed to 63Sn/37Pb which is a eutectic. This slower transition from
> solidus to liquidous is helpful when soldering low mass parts that are
> prone
> to tombstoning such as 0402 and 0201.
>
> Also according to the data published by the International Tin Research
> Institute the 2% silver version gives a stronger soldered joint.
>
> Pete Barton
> ACW Technology Ltd
>
> ===== Original Message from "TechNet E-Mail Forum." <[log in to unmask]> at
> 26/07/01 14:31
> >From "Soldering in Electronics" by Klein Wassink:
> >
> >"Note on solder alloy composition:
> >Solder paste in hybrid circuit technology (for thick-film circuits)
> usually
> has a metal
> composition of tin62-lead36-silver2. It should be realised that the
> addition
> of silver is not at all necessary for the silver (-palladium) metallisatio
> n
> of the
> >components, but for the much thinner silver-palladium conductors on the
> tick-film substrates.
> The use of the more expensive silver containing alloy, instead of the
> common
> tin60-lead40 alloy, for (relow) soldering on printed boards with copper
> >solder lands is not based on technological necessity, but sometimes on
> >better availability of this alloy (in the form of paste) and in most
> cases
> merely on habit.
> For the rest: with silver loaded alloy no harm is done !"
> >
> >Kind regards,
> >
> >Daan Terstegge
> >SMT Centre
> >Thales Communications
> >Unclassified mail
> >Personal Website: http://www.smtinfo.net
> >
> >
> >
> >
> >>>> "Kasprzak, Bill (sys) USX" <[log in to unmask]> 07/26 1:54 pm >>>
> >To all:
> >
> >I've been reading, with great interest, the responses so far to the use
> of
> >2% silver paste. I am not being critical of the folks who responded so
> far
> >but, each one cites a "reported" or "understood" advantage to using 2%
> >paste.
> >
> >I have also heard some of same reasons for considering a switch to a 2%
> >silver paste. Can any of the metallurgists on this forum confirm some
> of
> >these reported advantages and perhaps recommend that given x,y, and z,
> one
> >should consider using 2% silver solder alloys?
> >
> >Good topic.
> >
> >Bill Kasprzak
> >Moog Inc., Electronic Assembly Engineering
> >
> >
> >> -----Original Message-----
> >> From: Eric Christison [SMTP:[log in to unmask]]
> >> Sent: Thursday, July 26, 2001 4:20 AM
> >> To: [log in to unmask]
> >> Subject: Re: [TN] solder paste with 2% silver
> >>
> >> > I always understood that you had to use a paste with 2% silver if
> you
> >> > were using components
> >> > with terminations containing Palladium. The 2% silver is also
> supposed
> >> to
> >> > five you a shinier
> >> > finished solder joint.
> >> >
> >> > Steve.
> >> >
> >> > Larry Koens wrote:
> >> >
> >> > > Got a question for everyone,
> >> > >
> >> > > I just switched companies and the new company that I'm with now
> uses
> a
> >> > > 62/36/2 solder paste. I've always used the 63/37 formula. The
> guys
> who
> >> > > decided to use the 2% silver are no longer with the company. My
> >> > question
> >> > > to you is, why would they want the 2% silver in the paste? They
> know
> >> > > something I don't?!
> >> > >
> >>
> >> The silver should give the alloy higher strength, better creep
> resistance
> >> and a higher melting point. Perhaps your application benefits from one
> of
> >> these differences?
> >>
> >> Regards,
> >>
> >>
> >>
> >> Eric Christison
Eric Christison
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Date: Mon, 23 Jul 2001 13:55:48 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re:
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2b.189ba642.288dbf24_boundary"
--part1_2b.189ba642.288dbf24_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
LY,
Here's a few links to check out information about Low Inductance Capacitor
Arrays:
http://www.ryston.cz/pdf/avx/ti_nee.pdf
http://www.avxcorp.com/docs/techinfo/LI_TI.pdf
http://www.avxcorp.com/docs/catalogs/liarray.pdf
http://www.kyocera.com/kai/semiparts/pdfs/flipchip.pdf
http://lc.cray.com/models/cbga/
-Steve Gregory-
> I need your advice. Any information would be helpful.
>
> My boss asked me to check into the dimension feasibility of
> putting LICA in the Flip chip packages, such as, What is the clearance
> between the edge of the die to the edge
> of heat sink we need for LICA? How about the thickness of LICA vs. the
> heat sink? I will use uF range of LICA for my study.
>
> Thanks,
>
> YL
>
--part1_2b.189ba642.288dbf24_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>LY,
<BR>
<BR>Here's a few links to check out information about Low Inductance Capacitor
<BR>Arrays:
<BR>
<BR>http://www.ryston.cz/pdf/avx/ti_nee.pdf
<BR>http://www.avxcorp.com/docs/techinfo/LI_TI.pdf
<BR>http://www.avxcorp.com/docs/catalogs/liarray.pdf
<BR>http://www.kyocera.com/kai/semiparts/pdfs/flipchip.pdf
<BR>http://lc.cray.com/models/cbga/
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I need your advice. Any information would be helpful.
<BR>
<BR>My boss asked me to check into the dimension feasibility of
<BR>putting LICA in the Flip chip packages, such as, What is the clearance
<BR>between the edge of the die to the edge
<BR>of heat sink we need for LICA? How about the thickness of LICA vs. the
<BR>heat sink? I will use uF range of LICA for my study.
<BR>
<BR>Thanks,
<BR>
<BR>YL
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_2b.189ba642.288dbf24_boundary--
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Date: Mon, 29 Oct 2001 12:40:15 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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We are experiencing a problem with Technet. For some reason some old =
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Date: Thu, 2 Aug 2001 13:44:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rick Howieson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rick Howieson <[log in to unmask]>
Subject: IPC 600
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IPC-A-600 states "Printed boards should be of uniform quality and shall
conform to the IPC-6010 series." and that "IPC-A-600 is a complementary
document,..."
Can one interpret this as IPC-6010 series being a requirement if IPC-A-600
is being quoted?
Thanks,
Rick Howieson
www.deltagroupinc.com
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Date: Thu, 16 Aug 2001 08:56:39 +0900
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Johnny Kim <[log in to unmask]>
Subject: Re: Cost effective Standard via size.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
We only start adding the extra charge considering the Lot size.....from
below 4mils and 12mils for the finished hole size.
-----Original Message-----
From: Jean-Luc Lehmann [mailto:[log in to unmask]]
Sent: Wednesday, August 15, 2001 7:00 PM
To: [log in to unmask]
Subject: Re: [TN] Cost effective Standard via size.
I found out that "standard" PCB fabs usually start to charge extra cost
if
you go below 20 mils hole diameter (0.5mm). But it much depends on the
tooling they got.
Similarly I use trace width above 8 mils (200um).
Jean-Luc Lehmann
Ken Patel
<[log in to unmask] To: [log in to unmask]
OM> cc:
Sent by: Subject: [TN] Cost
effective Standard via size.
TechNet
<[log in to unmask]
ORG>
15.08.01
00:41
Please
respond to
"TechNet
E-Mail
Forum."
What is the standard minimum finished via size that will not add cost
too much? I do not want to specify the very small via which will drive
the price very high and at the same time not too big via size from the
real estate point of view.
re,
Ken Patel
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Date: Wed, 8 Aug 2001 09:05:23 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Contamination Concern after Strip
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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An ionic test can be misleading as you can have zero ionics and still have
100% surface contamination with non-ionic.
If you want to know what is there then you will need to do a lab based
investigation as suggested.
On a pragmatic basis you can do a wire bond and then do a pull test.
Alternatively even more pragmatically you might just try some over volts
through the wire. Any trapped organics will vaporise and blow the wire off
or the wire will melt. There is reasonable correlation between surface junk
and pull results, at least to start. The over volts is a crude yes no but
have seen known percent over volts used as an inline test on power devices.
Mike Fenner
Indium Corporation of Europe
T: + 44 1908 580 400
F: + 44 1908 580 411
M: + 44 7810 526 317
W: www.indium.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Andrew Hoggan
Sent: Tuesday, August 07, 2001 6:04 PM
To: [log in to unmask]
Subject: Re: [TN] Contamination Concern after Strip
Well Bill,
I'll happily stand correction, but I think it's difficult to confirm gold
cleanliness. With copper you can try a spot of etch or flux on the copper
area, if there's mask residue then the chemical won't touch the copper,
normally you'll notice the difference between oxidised copper and the fresh
etched. With gold you couldn't get away with that. If you can get your board
into a SEM-EDX chamber you could look for organic residue on the gold
surface.
Best regards,
Andrew Hoggan
BBA Associates Ltd
www.bba-associates.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Bill Christoffel
Sent: 07 August 2001 14:04
To: [log in to unmask]
Subject: [TN] Contamination Concern after Strip
Input Needed !
We currently use a board that is designed for gold ball bonding (COB)
and have specified electroplated gold as the top metal layer. This
board also uses a Tayio solder mask material that is flood coated over
the top, including the gold pads then photo imaged/etched. to expose
specific gold pads for wire bonding. My concern is that the solder
mask may be leaving some type of contamination on the bonding pads. If
so, I'm looking for recommendations on how to verify cleanliness, other
than ionically (which we do) and how to remove any contamination.
Thanks,
Bill C.
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Date: Mon, 23 Jul 2001 16:14:25 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Re: Inspection Criteria
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_d3.17f8d6e6.288ddfa1_boundary"
--part1_d3.17f8d6e6.288ddfa1_boundary
Content-Type: text/plain; charset="US-ASCII"
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Hi Jeff!
When you said you needed some pictures, that was my cue...hehe. I took a
scrap board and flexed it until I saw a crack, and then took a picture. Go to:
http://stevezeva.homestead.com/index.html
You can see the crack pretty clearly in the picture. This is a 1206 cap
mounted on a .062" thick board. I don't know what the dielectric is..It
really suprised me how much flex it required to produce a visible crack...and
I emphasize visible. There probably was a crack there before I could see it.
In this picture, the capacitor is definately history...the termination has
fractured as you can see...
Just thought you might like a picture...
-Steve Gregory-
> Kathy, et al,
>
> Thank you for your detailed input. In regards to your first paragraph, I am
> actually looking for some good quality photos of cracked solder joints on
> capacitors. We are getting some cracks along the solder joint of an 0805 SMT
> capacitor, probably due to board flex (these capacitors are located along
> the board edge). Do you have any photos you could share with me so I can
> show our inspectors what is acceptable/not acceptable.
>
> Anything would be of help, I do not have the capabilities/equipment to take
> photos of these defects in house.
>
> Rgds,
> John
>
> John Fahey
> Manufacturing Engineer
> Echelon Corp
>
> 415 Oakmead Parkway
> Sunnyvale
> CA 94085
> [log in to unmask]
> Phone: 408 938 5330
> Fax: 408 328 3804
>
--part1_d3.17f8d6e6.288ddfa1_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jeff!
<BR>
<BR>When you said you needed some pictures, that was my cue...hehe. I took a
<BR>scrap board and flexed it until I saw a crack, and then took a picture. Go to:
<BR>
<BR>http://stevezeva.homestead.com/index.html
<BR>
<BR>You can see the crack pretty clearly in the picture. This is a 1206 cap
<BR>mounted on a .062" thick board. I don't know what the dielectric is..It
<BR>really suprised me how much flex it required to produce a visible crack...and
<BR>I emphasize visible. There probably was a crack there before I could see it.
<BR>
<BR>In this picture, the capacitor is definately history...the termination has
<BR>fractured as you can see...
<BR>
<BR>Just thought you might like a picture...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Kathy, et al,
<BR>
<BR>Thank you for your detailed input. In regards to your first paragraph, I am
<BR>actually looking for some good quality photos of cracked solder joints on
<BR>capacitors. We are getting some cracks along the solder joint of an 0805 SMT
<BR>capacitor, probably due to board flex (these capacitors are located along
<BR>the board edge). Do you have any photos you could share with me so I can
<BR>show our inspectors what is acceptable/not acceptable.
<BR>
<BR>Anything would be of help, I do not have the capabilities/equipment to take
<BR>photos of these defects in house.
<BR>
<BR>Rgds,
<BR>John
<BR>
<BR>John Fahey
<BR>Manufacturing Engineer
<BR>Echelon Corp
<BR>
<BR>415 Oakmead Parkway
<BR>Sunnyvale
<BR>CA 94085
<BR>[log in to unmask]
<BR>Phone: 408 938 5330
<BR>Fax: 408 328 3804
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_d3.17f8d6e6.288ddfa1_boundary--
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Date: Mon, 23 Jul 2001 14:05:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jorge Rodriguez <[log in to unmask]>
Subject: X-Ray Laminography Services
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Fellow Technetters
I am looking for an X-Ray laminography Lab to inspect solder joints on some
BGAs. Do you know of any lab that provides these type of service?
Any information would be appreciated.
Jorge Rodriguez
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Date: Mon, 29 Oct 2001 19:20:35 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mason Hu <[log in to unmask]>
Subject: Minimum dielectric spacing for 48V trace and GND
What is the minimum dielectric spacing for a 48V trace and its return path
on the adjacent layer?
IPC-2221 recommends 0.1 mm (~4 mil). Is it enough?
Thanks
Mason Hu
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Date: Tue, 30 Oct 2001 11:03:03 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Inge Schildermans <[log in to unmask]>
Subject: Press-fit hole dimensions
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi all,
I was looking for an international standard which describes the tolerances on the dimensions of press-fit holes, since we had some troubles in production. I did not found anything in IPC, but I did in IEC-60352-6.
In this standard they did not make a difference between Sn-Pb finish and electroplated or immersion finish. I think this is strange since Sn/Pb has better smearing properties than the other finishes, and therefore can have other tolerances on the finishes
hole diameter. In the table they also make a difference between the diameter prior to plating and after plating. Can anyone tell me if it is necessary to define the drill diameter? In my opinion, the copper thickness in the hole and the finished hole
diameter are the only parameters which are of importance. Another strange thing is that comparing the different hole diameters, the difference between the drilled and finished hole is not always the same.
Can someone help me out of this?
Thanks,
Inge, Alcatel
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Date: Tue, 30 Oct 2001 10:07:21 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Stephen R. Gregory" <[log in to unmask]>
Subject: Is the Listserver back up?
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_c1.161a9049.29101c29_boundary"
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Content-Transfer-Encoding: 7bit
I sent a thank you to the listserver, and got a "you're welcome" back,
but havent't seen any traffic...
Just checking....
-Steve Gregory-
--part1_c1.161a9049.29101c29_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I sent a thank you to the listserver, and got a "you're welcome" back,
<BR>but havent't seen any traffic...
<BR>
<BR>Just checking....
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_c1.161a9049.29101c29_boundary--
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Date: Tue, 30 Oct 2001 09:24:13 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Land Patterns
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="=_712B993A.C9A8C580"
This is a MIME message. If you are reading this text, you may want to
consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_712B993A.C9A8C580
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Content-Disposition: inline
Could you add thermal profile information to the request list?
Kathy=20
--=_712B993A.C9A8C580
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Could you add thermal profile information to the request list?</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_712B993A.C9A8C580--
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Date: Tue, 30 Oct 2001 09:27:52 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Blasts from the past?!??
Mime-Version: 1.0
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--=_A4FE4CEF.CAABC683
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Yeah, I thought my email was slow but really....
Kathy=20
--=_A4FE4CEF.CAABC683
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2919.6307" name=GENERATOR></HEAD>
<BODY
style="FONT: 10pt Abadi MT Condensed Light; MARGIN-LEFT: 2px; MARGIN-TOP: 2px">
<DIV>Yeah, I thought my email was slow but really....</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_A4FE4CEF.CAABC683--
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Date: Tue, 30 Oct 2001 08:39:21 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Patrick Lam <[log in to unmask]>
Subject: Thermal Relief in Planes
X-To: [log in to unmask]
Mime-Version: 1.0
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Hi TechNetters,
According to IPC-2222, 9.0, the total web width should be 60% of the minimum pad
size. If the pad ties to copper planes both on top and bottom, should the web be
60% or half of 60%.
Thanks,
Patrick
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Date: Tue, 30 Oct 2001 10:53:54 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: Technet accepting posts again
X-cc: Jack Crawford <[log in to unmask]>
Mime-Version: 1.0
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The Technet list is open for accepting posts. The problem with all the old =
posts being sent back to the list was due to an unidentified mail server =
overseas which had apparently held hundreds of old Technet postings from =
this past summer. For some reason, through an incorrect configuration on =
their part, it was sending all those old, held e-mails back to the Technet =
list.
That is why you were being bombarded with all the old Technet posts. We =
have rectified the situation here at IPC by blocking the offending carrier =
from sending back to Technet.
I did delete 400+ emails from the Technet queue, the vast majority of =
which are old recycled posts, but there may have been a few original posts =
that may have been deleted. So if you did try to send out a new post in =
the last 24 hours and have not seen it come thu, you may post it again.=20
I apologize for the mess of e-mails that you've all received, and hope =
that your <Delete> key holds up!=20
______________
Keach Sasamori
IS Administrator
IPC
2215 Sanders Rd.
Northbrook, IL 60062
Ph: (847) 790-5315=20
Fax: (847) 504-2315
e-mail: [log in to unmask]
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Date: Tue, 30 Oct 2001 10:19:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Looking for reliable test clip for 128 pin QFP
> Hi Folks,
>
> If anyone has first-hand experience with a reliable test adapter that can
> be used repeatedly with a 128 pin flat pak, I'd appreciate getting company
> and contact information. I'm looking for an adapter to test parts that
> have been assembled to boards.
>
> Thanks in advance,
> Terri
>
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Date: Tue, 30 Oct 2001 12:45:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crain, Bob" <[log in to unmask]>
Subject: Re: Solder analysis results - Stratification
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
My experience has been that the pot definitely does stratify. A couple of
years ago, we failed a solder analysis (not even close to the requirements).
When we started asking questions, it turned out that the operator dipped
shallow from a static 800 pound pot. We ran the wave for 15 minutes and
dipped deeper - presto, the solder pot passed with its usual numbers. After
that, we beefed up the work instructions for taking samples.
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Date: Tue, 30 Oct 2001 09:56:17 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Component Mounting Techniques for Shock and Vibration
MIME-Version: 1.0
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All,
I know that IPC-D-275 is superseded by IPC-2221 and 2222. As I don't
have the new ones, I want to make sure that following statements are
still correct which I have taken form IPC-D-275.
4.1.8.1 Component Mounting Techniques for Shock and Vibration
Axial leaded components weighing less than 5 grams (0.18 oz)
per lead shall be mounted with their bodies in intimate contact with the
board. Dimensional criteria for lead bending and spacing shall be as
specified in 4.2. Axial leaded components weighing 5 grams (0.18 oz) or
more, per lead should be secured to the board utilizing mounting clamps.
If the clamps are not practical due to density considerations, adhesive
bonding techniques should be employed such that the solder connections
are not the only means of mechanical support. These techniques are used
for components weighing more than 5 grams (0.18 oz) when high vibration
requirements must be met. (see paragraph 3.7.3.2 and figures 4-5 and
4-6.)
re,
Ken patel
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Date: Tue, 30 Oct 2001 13:31:47 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: Thermal Relief in Planes
MIME-Version: 1.0
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Patrick,
The total web widths should be divided by the number of internal plane
connections.
Regards,
Gary
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Date: Tue, 30 Oct 2001 11:52:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Schaefer <[log in to unmask]>
Subject: IPC-2226 : Does it Exist? / HDI Resources
Mime-Version: 1.0
Content-Type: multipart/alternative; boundary="=_A6FC4EF1.1B7A00FC"
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consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_A6FC4EF1.1B7A00FC
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
I was looking through the IPC 2220 Series of specifications, and noticed a =
reference to IPC-2226 "High Density Interconnect Structure Design".
IPC does not list this specification as being available for purchase on =
their website - does anyone know the status of this specification?
Is it possible to obtain a preliminary copy?
Also, does anyone have any links to HDI / Microvia design information?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
1000 Waverley Street =20
Winnipeg, MB R3T 0P3 =20
--=_A6FC4EF1.1B7A00FC
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><FONT size=3D1>I was looking through the IPC 2220 Series of specificat=
ions,=20
and noticed a reference to IPC-2226 "High Density Interconnect Structure=20=
Design".</FONT></DIV>
<DIV><FONT size=3D1>IPC does not list this specification as being =
available for=20
purchase on their website - does anyone know the status of this=20
specification?</FONT></DIV>
<DIV><FONT size=3D1>Is it possible to obtain a preliminary copy?</FONT></DI=
V>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Also, does anyone have any links to HDI / Microvia =
design=20
information?</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Thanks,</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Dave=20
Schaefer &=
nbsp; &nbs=
p; =20
Voice: (204)478-8059<BR>Senior PCB=20
Designer &=
nbsp; =20
FAX: (204)942-3001<BR>Symbol=20
Technologies &nb=
sp; =20
Email: <A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
<BR>1000=20
Waverley=20
Street &nb=
sp; =20
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1></FONT> </DIV></BODY></HTML>
--=_A6FC4EF1.1B7A00FC--
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Date: Tue, 30 Oct 2001 14:11:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jerry Mosur <[log in to unmask]>
Subject: Solder Joint Analysis
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello all,
Don't worry, ... you can read on. I am not posting any links!
I wonder if anyone can shed some light on the following topic:
Using IPC-SM-782 Land Pattern program one has to input Solder Joint
Design Goals (Min.) for Toe, Heel and Side for any SMD part. However the
Surface Mount Design and Land Pattern Standards states that those dimensions
"have been determined based on industry empirical knowledge and reliability
testing".
That is fine, but how about those parts that are either too new or used very
rarely?
I am attempting to design a pattern for a Chip Capacitor 5550 with a
thickness of 2.5mm.
Could anyone share his/her SMD assembly empirical knowledge and know-how and
answer the following questions:
- what would be an optimum number (mm) for each parameter for that
particular part?
- what are those numbers based on?
- is there a formula that determines the correct ratio between the part's
dimension(s) and Solder Joint size?
Thanks in advance
Jerry
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Date: Tue, 30 Oct 2001 12:18:59 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Maxwell <[log in to unmask]>
Subject: Re: Solder Joint Analysis
In-Reply-To: <[log in to unmask] .com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
>Jerry,
If the capacitor is ceramic boy will you have fun keeping it from cracking
during reflow cool down and PWA handling.
John Maxwell
>Hello all,
>
>Don't worry, ... you can read on. I am not posting any links!
>I wonder if anyone can shed some light on the following topic:
> Using IPC-SM-782 Land Pattern program one has to input Solder Joint
>Design Goals (Min.) for Toe, Heel and Side for any SMD part. However the
>Surface Mount Design and Land Pattern Standards states that those dimensions
>"have been determined based on industry empirical knowledge and reliability
>testing".
>That is fine, but how about those parts that are either too new or used very
>rarely?
>I am attempting to design a pattern for a Chip Capacitor 5550 with a
>thickness of 2.5mm.
>Could anyone share his/her SMD assembly empirical knowledge and know-how and
>answer the following questions:
>- what would be an optimum number (mm) for each parameter for that
>particular part?
>- what are those numbers based on?
>- is there a formula that determines the correct ratio between the part's
>dimension(s) and Solder Joint size?
>
>Thanks in advance
>
>Jerry
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Tue, 30 Oct 2001 14:22:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: IPC-2226 : Does it Exist? / HDI Resources
MIME-Version: 1.0
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boundary="----_=_NextPart_001_01C16178.3F672F42"
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charset="iso-8859-1"
Hi Dave
Go to microvia.com also Michael Fitts of Fitts Solutions can be a good
source also there is HDI publication.
Shahed
-----Original Message-----
From: David Schaefer [mailto:[log in to unmask]]
Sent: Tuesday, October 30, 2001 11:52 AM
To: [log in to unmask]
Subject: [TN] IPC-2226 : Does it Exist? / HDI Resources
I was looking through the IPC 2220 Series of specifications, and noticed a
reference to IPC-2226 "High Density Interconnect Structure Design".
IPC does not list this specification as being available for purchase on
their website - does anyone know the status of this specification?
Is it possible to obtain a preliminary copy?
Also, does anyone have any links to HDI / Microvia design information?
Thanks,
Dave Schaefer Voice: (204)478-8059
Senior PCB Designer FAX: (204)942-3001
Symbol Technologies Email: [log in to unmask]
<mailto:[log in to unmask]>
1000 Waverley Street
Winnipeg, MB R3T 0P3
------_=_NextPart_001_01C16178.3F672F42
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px">
<DIV><SPAN class=3D887432519-30102001><FONT size=3D1>Hi =
Dave</FONT></SPAN></DIV>
<DIV><SPAN class=3D887432519-30102001><FONT size=3D1>Go to microvia.com =
also Michael=20
Fitts of Fitts Solutions can be a good source also there is HDI=20
publication.</FONT></SPAN></DIV>
<DIV><SPAN class=3D887432519-30102001><FONT =
size=3D1></FONT></SPAN> </DIV>
<DIV><SPAN class=3D887432519-30102001><FONT =
size=3D1></FONT></SPAN> </DIV>
<DIV><SPAN class=3D887432519-30102001><FONT =
size=3D1>Shahed</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> David Schaefer=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, October 30, =
2001 11:52=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] IPC-2226 : =
Does it=20
Exist? / HDI Resources<BR><BR></FONT></DIV>
<DIV><FONT size=3D1>I was looking through the IPC 2220 Series of =
specifications,=20
and noticed a reference to IPC-2226 "High Density Interconnect =
Structure=20
Design".</FONT></DIV>
<DIV><FONT size=3D1>IPC does not list this specification as being =
available for=20
purchase on their website - does anyone know the status of this=20
specification?</FONT></DIV>
<DIV><FONT size=3D1>Is it possible to obtain a preliminary =
copy?</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Also, does anyone have any links to HDI / =
Microvia design=20
information?</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Thanks,</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Dave=20
=
Schaefer &nbs=
p; &nbs=
p; =20
Voice: (204)478-8059<BR>Senior PCB=20
=
Designer &nbs=
p; =20
FAX: (204)942-3001<BR>Symbol=20
=
Technologies =
=20
Email: <A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
<BR>1000=20
Waverley=20
=
Street =
=20
<BR>Winnipeg, MB R3T 0P3 </FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1></FONT> </DIV></BLOCKQUOTE></BODY></HTML>
------_=_NextPart_001_01C16178.3F672F42--
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=========================================================================
Date: Tue, 30 Oct 2001 14:27:36 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dennis Fritz <[log in to unmask]>
Subject: Re: IPC-2226 : Does it Exist? / HDI Resources
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
I believe the 2226 is in the proposal stage, but not issued. Lionel Fullwood
of Wong's in Hong Kong is the chairman of the effort on the standard - I have
his e-mail as [log in to unmask] I do not know the progress they made in
Orlando as I had schedule conflicts.
There should be an IPC design guideline for HDI design - while not a
standard, it should get you on the map. Check again on the IPC website for
that. I forget the number.
Denny Fritz
---------------------------------------------------------------------------------
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Date: Tue, 30 Oct 2001 14:28:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Schwarzkopf, Todd" <[log in to unmask]>
Subject: Printed Circuit Assembly Cleaning
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
We have some boards that are coming from the assembly house that are failing
test. We suspect that there is residue from the flux still on the board.
I believe my assembly house uses a cleanable no-clean solder. These are
high voltage boards. I am very ignorant in this area and this is all of the
information my boss is telling me. These boards used to be built in house
and worked. They started failing after outsourcing our assemblies. Can
someone give me some information and or links so I can educate myself on
this subject. My boss wants me to come up with a cleaning specification for
our printed circuit assemblies. I do not even know enough to ask questions.
Any help will be greatly appreciated.
Thanks,
Todd Schwarzkopf, C.I.D.
PCB Designer
PerkinElmer Instruments
801 S. Illinois Ave.
Oak Ridge, TN 37831-0895
[log in to unmask]
Voice: (865) 481-2427
Fax: (865) 481-2438
---------------------------------------------------------------------------------
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=========================================================================
Date: Tue, 30 Oct 2001 14:44:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Erickson, Gary" <[log in to unmask]>
Subject: Re: IPC-2226 : Does it Exist? / HDI Resources
MIME-Version: 1.0
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Try IPC/JPCA-2315 !!
Regards,
Gary
-----Original Message-----
From: Dennis Fritz [mailto:[log in to unmask]]
Sent: Tuesday, October 30, 2001 2:28 PM
To: [log in to unmask]
Subject: Re: [TN] IPC-2226 : Does it Exist? / HDI Resources
I believe the 2226 is in the proposal stage, but not issued. Lionel
Fullwood
of Wong's in Hong Kong is the chairman of the effort on the standard - I
have
his e-mail as [log in to unmask] I do not know the progress they made in
Orlando as I had schedule conflicts.
There should be an IPC design guideline for HDI design - while not a
standard, it should get you on the map. Check again on the IPC website for
that. I forget the number.
Denny Fritz
----------------------------------------------------------------------------
-----
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E-mail Archives
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional
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ext.5315
----------------------------------------------------------------------------
-----
------_=_NextPart_001_01C1617B.4CAB7020
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>RE: [TN] IPC-2226 : Does it Exist? / HDI Resources</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=3D2>Try IPC/JPCA-2315 !!</FONT>
</P>
<P><FONT SIZE=3D2>Regards,</FONT>
</P>
<P><FONT SIZE=3D2>Gary</FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Dennis Fritz [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Tuesday, October 30, 2001 2:28 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [TN] IPC-2226 : Does it Exist? / HDI =
Resources</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>I believe the 2226 is in the proposal stage, but not =
issued. Lionel Fullwood</FONT>
<BR><FONT SIZE=3D2>of Wong's in Hong Kong is the chairman of the effort =
on the standard - I have</FONT>
<BR><FONT SIZE=3D2>his e-mail as [log in to unmask] I do =
not know the progress they made in</FONT>
<BR><FONT SIZE=3D2>Orlando as I had schedule conflicts.</FONT>
</P>
<P><FONT SIZE=3D2>There should be an IPC design guideline for HDI =
design - while not a</FONT>
<BR><FONT SIZE=3D2>standard, it should get you on the map. Check =
again on the IPC website for</FONT>
<BR><FONT SIZE=3D2>that. I forget the number.</FONT>
</P>
<P><FONT SIZE=3D2>Denny Fritz</FONT>
</P>
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Date: Tue, 30 Oct 2001 13:48:54 -0600
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ashok Dhawan <[log in to unmask]>
Subject: Re: Panelized Boards
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Dean
Can you fax me also. My Fax # 204-631-7294. Thanks in advance.
Ashok Dhawan P.Eng.
Engineering
C-MAC Network Systems Inc.
1455 Mountain Roar
Winnipeg Manitoba R2X 2Y9
WWW.CMAC.COM
TEL (204) 631 7208
FAX (204) 631 7294
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Dean Lillibridge
> Sent: Wednesday, August 15, 2001 1:45 PM
> To: [log in to unmask]
> Subject: Re: [TN] Panelized Boards
>
>
> if you don't mind supplying me with your fax number, I can fax over some
> considerations that we have used for panelizing boards.
> --Dean Lillibridge
> NEWvENTURE TECHNOLOGIES
> (860) 253-7057
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
> Sent: Wednesday, August 15, 2001 1:46 PM
> To: [log in to unmask]
> Subject: [TN] Panelized Boards
>
>
> I have a 3.5" x 5.5", .063" thick board we will be building in
> somewhat high
> quantities (3,000+/month). This size board is just on the edge as far as
> having to put it into a basket to run through our in-line aqueous
> cleaner to
> keep it from moving around. I do not want the operators to have
> to put this
> many boards in baskets during production runs. So, my thoughts have turned
> to panelizing these boards, perhaps in a 2x2 arrangement. This would go
> through the cleaner with no problem. I do not have a lot of experience in
> the best designs for panels. What are the advantages/disadvantages between
> v-score and tabs? If using tabs, how many are required to maintain the
> rigidity of the panel during reflow? Does there have to be a border around
> the boards? Are fiducials required on the panel in addition to
> the fiducials
> already on the individual boards? Any other issues I may have missed?
>
> Thanks.
>
>
> Bob
>
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Date: Tue, 30 Oct 2001 16:35:38 EST
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Solder Joint Analysis
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Hi Jerry,
Solder joint size per se is not relevant for SJ reliability; only the SJ
thickness is of primary importance. you should follow the guidelines in
IPC-D-279.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Wed, 31 Oct 2001 08:08:27 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "<Peter George Duncan>" <[log in to unmask]>
Subject: Re: Land Patterns
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Thermal profile information is difficult to include on individual component
data sheets, as it depends on the solder you're going to use and the
thermal mass of other components around it on the board assembly.
Has a stone been set rolling down a mossy hill with this thread?
Pter Duncan
Kathy Kuhlow
<Kathy@BTW-IN To: [log in to unmask]
C.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Land Patterns
<[log in to unmask]
ORG>
10/30/01
11:24 PM
Please
respond to
"TechNet
E-Mail
Forum."
Could you add thermal profile information to the request list?
Kathy
(See attached file: TEXT.htm)
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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Date: Tue, 30 Oct 2001 19:23:36 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: AW: [TN] Antw: [TN] exposing intermetallic on BGA pads..
.
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I believe it to be LT 1 um, but I'd ask Paul Vianco at Sandia Laboratories
505-844-3429. Dr. Vianco wrote the "AWS Soldering Handbook, 3rd Edition".
So, he is qualified.
Please let me know the answer.
Dave Fish
----- Original Message -----
From: "Bev Christian" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, October 26, 2001 8:45 AM
Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA pads.. .
> TechNetters,
> Questions of my sex aside.. got your attention now, right?
>
> I will ask again what do people expect for the average thickness of the
> tin/nickel intermetallic. The closest answer I got was the rate of
growth,
> but not what one expects it to start at after a single reflow. I bring it
> up here as it is related to the current discussion.
>
> regards,
> Bev Christian
> Resaerch in Motion
>
> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: October 26, 2001 1:30 PM
> To: [log in to unmask]
> Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA
> pads...
>
>
> Guenter,
>
> As you replied to me personally, I respected your not posting on the
> TechNet. So, I said it was someone else but everyone knows it must be you.
> Simply, I didn't/don't want to betray your confidence as I respect your
> privacy.
>
> Earl
>
> ps. I am enjoying this and learning much from this conversation. Still, I
am
> stirring the pot for everyone to benefit. I'm too old to add much but if I
> can elicit responses from real experts, like you, we will all learn more
>
> Earl
>
> ----- Original Message -----
> From: "Guenter Grossmann" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Friday, October 26, 2001 8:46 AM
> Subject: Re: [TN] AW: [TN] Antw: [TN] exposing intermetallic on BGA
pads...
>
>
> Earl
> Well, I think some acceptance criteria is necessary since if there isn't
> even no solder is accepted. However, I agree that in many cases I feel
that
> the acceptance criteria mare more designed in a manner that they can be
> controlled rather than in respect to reliability.
>
> Regarding your comment of IMC and the discussion we had offline I thought
> abut the thing at home:
> - Suppose you do a good job in designing your solder profile. This means,
in
> my understanding, that just enough heat is brought into a PCB that all
> joints are formed and as little heat as possible stresses the components.
As
> an effect the IMC will be very thin.
> - Suppose again that you rework. Again you do a good job in removing the
> remaining tin thoroughly. To do so you need to keep the pad to be cleaned
at
> elevated temperature for quite a while.
>
> The result will be, that
> - Because of thoroughly removing the solder you expose IMC or
> - Because the IMC is thin and the pad is warm for some time the remaining
> little amount of tin that covers the IMC is transformed into IMC.
>
> Hence, one can say that a job too well done leads to a poor solder joint.
> And thus ( just to steer the pot a bit as you like it) if you instruct
> people for repairing solder joints and it works, your instruction wasn't
too
> accurate? ( HeHe)
>
> Have a great weekend
>
> Ps: What do you mean by : you spoke with someone who is also much
respected
> in this field?
>
>
>
> Guenter Grossmann
>
> Swiss Federal Institute for Materials Testing and Research EMPA
> Centre for Reliability
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax : xx41 1823 4054
> mail: [log in to unmask]
>
> --------------------------------------------------------------------------
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Date: Tue, 30 Oct 2001 19:39:59 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Component Mounting Techniques for Shock and Vibration
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IPC-D-275, 4.1.8.1, paragraph 1 is repeated word for word in IPC-2221,
8.1.9.1, paragraph 1, as you state [except, of course, the numbering of the
referenced paragraphs and figures]. The paragraph following your paragraph
is substantially different.
Dave Fish
----- Original Message -----
From: "Ken Patel" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, October 30, 2001 9:56 AM
Subject: [TN] Component Mounting Techniques for Shock and Vibration
> All,
> I know that IPC-D-275 is superseded by IPC-2221 and 2222. As I don't
> have the new ones, I want to make sure that following statements are
> still correct which I have taken form IPC-D-275.
>
> 4.1.8.1 Component Mounting Techniques for Shock and Vibration
> Axial leaded components weighing less than 5 grams (0.18 oz)
> per lead shall be mounted with their bodies in intimate contact with the
> board. Dimensional criteria for lead bending and spacing shall be as
> specified in 4.2. Axial leaded components weighing 5 grams (0.18 oz) or
> more, per lead should be secured to the board utilizing mounting clamps.
> If the clamps are not practical due to density considerations, adhesive
> bonding techniques should be employed such that the solder connections
> are not the only means of mechanical support. These techniques are used
> for components weighing more than 5 grams (0.18 oz) when high vibration
> requirements must be met. (see paragraph 3.7.3.2 and figures 4-5 and
> 4-6.)
>
>
> re,
> Ken patel
>
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Date: Tue, 30 Oct 2001 19:50:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Valquirio Carvalho <[log in to unmask]>
Subject: Re: Press-fit hole dimensions
In-Reply-To: <[log in to unmask]>
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Hi Inge,
In some cases the drilled hole diameter is critical to the success of the
press fit connection. The manufacturer of the press fit component may
specify the drilled hole size along with the plated hole size and plated
hole size tolerance for a given component. In the case of some small
(finished hole size 0.022") compliant pins I had to work with, the hole size
prior to plating was more important than the finished hole size when looking
at the required insertion force. It is now our policy to call out the
drilled hole size on the fab drawing along with the finished hole size and
finished hole size tolerance for holes that will receive press fit
components whenever the manufacturer recommends a drilled hole size.
As far as board finish goes, I have seen similar results when working with
Sn/Pb and gold as a general rule. One other thing to consider is the finish
of the component. While pressing pin with a Sn/Pb finish into a board I
haven't noticed much difference in insertion force with varied board
finishes. I have however noticed that pressing a gold finished lead into a
gold finished board requires a significantly higher force. That however has
not caused us to change the hole size on the board, yet.
Either way, I recommend you work closely with the manufacturer of the
component that you want to press while defining your board characteristics.
Regardless of which manufacturer I have dealt with (Amp, EPT, Teradyne, FCI,
etc...), I have received the right information to make that part work on a
given board.
I hope this helps...
Valquirio N. Carvalho
Mfg. Engineer
Teradyne, Inc.
P.S. I don't work in the connector division of Teradyne. I work in the
board assembly end of things.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Inge Schildermans
Sent: Tuesday, October 30, 2001 5:03 AM
To: [log in to unmask]
Subject: [TN] Press-fit hole dimensions
Hi all,
I was looking for an international standard which describes the tolerances
on the dimensions of press-fit holes, since we had some troubles in
production. I did not found anything in IPC, but I did in IEC-60352-6.
In this standard they did not make a difference between Sn-Pb finish and
electroplated or immersion finish. I think this is strange since Sn/Pb has
better smearing properties than the other finishes, and therefore can have
other tolerances on the finishes
hole diameter. In the table they also make a difference between the
diameter prior to plating and after plating. Can anyone tell me if it is
necessary to define the drill diameter? In my opinion, the copper thickness
in the hole and the finished hole
diameter are the only parameters which are of importance. Another strange
thing is that comparing the different hole diameters, the difference between
the drilled and finished hole is not always the same.
Can someone help me out of this?
Thanks,
Inge, Alcatel
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Date: Tue, 30 Oct 2001 17:22:11 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: modeling
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hi,
i've tried to download this evolver program, but smart download keeps timing out. have you downloaded it from the umn site?
phil
-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Tuesday, October 23, 2001 7:49 AM
To: [log in to unmask]
Subject: Re: [TN] modeling
Hi Waleed!
Go to:
http://www.ctcms.nist.gov/programs/solder/
There you'll find a program called "Surface Evolver" that you can use to model various solder joints...plus there's also a few other good links from that page.
-Steve Gregory-
Dear:
Does anyone know anything about modeling ( solder joint
,traces,leads,..).
thanks
waleed
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<DIV><SPAN class=117052101-31102001><FONT face=Arial color=#0000ff
size=2>hi,</FONT></SPAN></DIV>
<DIV><SPAN class=117052101-31102001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=117052101-31102001><FONT face=Arial color=#0000ff size=2>i've
tried to download this evolver program, but smart download keeps timing
out. have you downloaded it from the umn site?</FONT></SPAN></DIV>
<DIV><SPAN class=117052101-31102001><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=117052101-31102001><FONT face=Arial color=#0000ff
size=2>phil</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Stephen R. Gregory
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, October 23, 2001 7:49
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
modeling<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi
Waleed! <BR><BR>Go to: <BR><BR>http://www.ctcms.nist.gov/programs/solder/
<BR><BR>There you'll find a program called "Surface Evolver" that you can use
to model various solder joints...plus there's also a few other good links from
that page. <BR><BR>-Steve Gregory- <BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">Dear:
<BR> Does
anyone know anything about modeling ( solder joint <BR>,traces,leads,..).
<BR><BR> thanks
<BR> waleed <BR></FONT><FONT lang=0
face=Arial color=#000000 size=3
FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0 face=Arial
color=#000000 size=2
FAMILY="SANSSERIF"><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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Date: Wed, 31 Oct 2001 08:21:39 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: Edward Szpruch <[log in to unmask]>
Subject: Re: Technet accepting posts again
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Thanks a lot.
This is really funny to think,that there is someone,who accumulated too =
much
Technet posts and now is leaking.
Maybe he needs to install some kind of overflow to "trash" or pressure
relief device???
Edward Szpruch
Eltek Ltd
P.O.Box 159 ; 49101 Petah Tikva Israel
Tel ++972 3 9395050 , Fax ++972 3 9309581
e-mail [log in to unmask]
> -----Original Message-----
> From: Keach Sasamori [SMTP:[log in to unmask]]
> Sent: =E2 =E0=E5=F7=E8=E5=E1=F8 30 2001 18:54
> To: [log in to unmask]
> Subject: [TN] Technet accepting posts again
>=20
> The Technet list is open for accepting posts. The problem with all =
the old
> posts being sent back to the list was due to an unidentified mail =
server
> overseas which had apparently held hundreds of old Technet postings =
from
> this past summer. For some reason, through an incorrect configuration =
on
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>=20
> That is why you were being bombarded with all the old Technet posts. =
We
> have rectified the situation here at IPC by blocking the offending =
carrier
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>=20
> I did delete 400+ emails from the Technet queue, the vast majority of
> which are old recycled posts, but there may have been a few original =
posts
> that may have been deleted. So if you did try to send out a new post =
in
> the last 24 hours and have not seen it come thu, you may post it =
again.=20
>=20
> I apologize for the mess of e-mails that you've all received, and =
hope
> that your <Delete> key holds up!=20
>=20
>=20
>=20
> ______________
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Date: Wed, 31 Oct 2001 09:12:43 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: Printed Circuit Assembly Cleaning
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Hi Todd,
I don't know exactly what you are looking for, but some excellent starting =
points for information about board cleaning are:
http://www.residues.com/libraries1.htm=20
http://www.protonique.com/unepstoc
http://www.precisioncleaningweb.com
With the search-engine on http://www.smtinfo.net/smtlinks.html (that's my =
own webpage) you should be able to find some more URL's of interest.
Hope this helps,
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> "Schwarzkopf, Todd" <[log in to unmask]> 10/30 8:28 pm =
>>>
We have some boards that are coming from the assembly house that are =
failing
test. We suspect that there is residue from the flux still on the board.
I believe my assembly house uses a cleanable no-clean solder. These are
high voltage boards. I am very ignorant in this area and this is all of =
the
information my boss is telling me. These boards used to be built in house
and worked. They started failing after outsourcing our assemblies. Can
someone give me some information and or links so I can educate myself on
this subject. My boss wants me to come up with a cleaning specification =
for
our printed circuit assemblies. I do not even know enough to ask =
questions.
Any help will be greatly appreciated.
Thanks,
Todd Schwarzkopf, C.I.D.
PCB Designer
PerkinElmer Instruments
801 S. Illinois Ave.
Oak Ridge, TN 37831-0895
[log in to unmask]
Voice: (865) 481-2427
Fax: (865) 481-2438
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Date: Tue, 30 Oct 2001 21:04:06 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
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From: sk zhang <[log in to unmask]>
Subject: some process questions--
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Date: Wed, 31 Oct 2001 09:33:48 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Smt Low profile connectors
Hi All
We just had a customer raise a concern regarding some SMT connectors. What
they noticed was the solder tails all being raised in the solder. Not 1
lead on any connector was flat to the pad.
What we noticed was the solder tails are not on the same plane as the
fitting nails of the connectors. When you place the connector flat to the
PCB, the solder nails are off the pad by about 0.005", which can cause a
problem when you have a 0.006" stencil.
I have contacted the manufacture but have yet to hear anything.
Has anyone run across this concern before? Any info would be appreciated
Thanks
Andre
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Date: Wed, 31 Oct 2001 16:05:01 -0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Cathy Killen <[log in to unmask]>
Subject: 0402 Resistors & Caps
MIME-Version: 1.0
Content-Type: text/plain
Does anyone know the surface mount land pattern for 0402 resistors and caps?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
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Date: Wed, 31 Oct 2001 08:10:37 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Glynn Shaw <[log in to unmask]>
Subject: Wanted: Used TMA
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Thermal-Mechanical Analyzer desired for measuring laminate cure and TD-260.
Please respond off-line.
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Date: Wed, 31 Oct 2001 11:14:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Raymond <[log in to unmask]>
Subject: Re: Smt Low profile connectors
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hi Andre,
We don't use many SMT connectors, so we don't see what you're
seeing... however it sure reminds me of the many companies who make PBGA
devices and who use the JEDEC package specification which states .008"
maximum coplanarity - I have the same question as you... "How do I process
this part with a .005" or .006" thick stencil??? " Luckily, so far, the
majority of PBGA parts have FAR less than .008" :)
Bill...
At 09:33 AM 10/31/2001 -0600, you wrote:
>Hi All
>
>We just had a customer raise a concern regarding some SMT connectors. What
>they noticed was the solder tails all being raised in the solder. Not 1
>lead on any connector was flat to the pad.
>What we noticed was the solder tails are not on the same plane as the
>fitting nails of the connectors. When you place the connector flat to the
>PCB, the solder nails are off the pad by about 0.005", which can cause a
>problem when you have a 0.006" stencil.
>I have contacted the manufacture but have yet to hear anything.
>
>Has anyone run across this concern before? Any info would be appreciated
>
>Thanks
>Andre
>
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Date: Wed, 31 Oct 2001 11:30:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: STRIPPING MAGNET WIRE
MIME-Version: 1.0
Content-Type: text/plain
Looking for a recommendation for a chemical stripper to strip bi-filar (?)
magnet wire. Any suggestions?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Wed, 31 Oct 2001 11:43:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sherry Warner <[log in to unmask]>
Subject: Re: STRIPPING MAGNET WIRE
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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=46or the magnetic wire we have used in the past this has worked well:
Insulstrip Jell
Ambion Corporation
37 Naugatuck Drive
Naugatuck, CT 06770
(203) 723-1437
>Looking for a recommendation for a chemical stripper to strip bi-filar (?)
>magnet wire. Any suggestions?
>
>Jim Marsico
>Senior Engineer
>Production Engineering
>EDO Electronics Systems Group
>[log in to unmask] <mailto:[log in to unmask]>
>631-595-5879
>
>---------------------------------------------------------------------=20
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Date: Wed, 31 Oct 2001 16:32:16 -0000
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: 0402 Resistors & Caps
MIME-Version: 1.0
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The overall footprint is 2.248mm x 0.738mm made up of two pads 0.738x0.896mm with a gap of 0.456mm between
Dougal Stewart
email [log in to unmask]
telephone +44 1896 822204
mobile +44 7984 629667
-----Original Message-----
From: Cathy Killen [SMTP:[log in to unmask]]
Sent: 31 October 2001 16:05
To: [log in to unmask]
Subject: [TN] 0402 Resistors & Caps
Does anyone know the surface mount land pattern for 0402 resistors and caps?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
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Date: Wed, 31 Oct 2001 18:54:15 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: STRIPPING MAGNET WIRE
MIME-Version: 1.0
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In a former life, I used to sell 4 enamel strippers and even
manufactured a fifth. These were based mainly on organic-acidified
methylene chloride blends and used to work with about 2 minutes
immersion. However, each enamel type required a different formulation.
Also, you might try ordinary paint strippers: these will work with many
enamels.
Brian
"Marsico, James" wrote:
>
> Looking for a recommendation for a chemical stripper to strip bi-filar (?)
> magnet wire. Any suggestions?
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Wed, 31 Oct 2001 11:54:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: 0402 Resistors & Caps
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Cathy,
Go to www.toplinedummy.com .
-----Original Message-----
From: Cathy Killen [mailto:[log in to unmask]]
Sent: Wednesday, October 31, 2001 11:05 AM
To: [log in to unmask]
Subject: [TN] 0402 Resistors & Caps
Does anyone know the surface mount land pattern for 0402 resistors and caps?
Thanks in advance.
Cathy Killen
Training Instructor
Smtek Europe Ltd.
The information contained in the E-mail is confidential. It is intended only
for the stated addressee(s) and access to it by any other person is
unauthorised.
The views expressed in this E-mail are those of the author, and do not
represent the views of Smtek Europe, its associates or subsidiaries, unless
otherwise expressly indicated.
Please note: It is your responsibility to scan this E-mail for viruses.
----------------------------------------------------------------------------
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Date: Wed, 31 Oct 2001 10:59:18 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: solder, adhesives, prepregs, etc.
Need your help on subject becoming more prevalent in these times. Used
Thermount, CLTE, and other adhesive/preg types in various designs for CTE
matching, thermal characteristics, and RF stuff.
Need to know more about advanced bonding materials to replace solders
joining various material surfaces. Solder ok in some applications. Adhesives
more positive in others.
Have used some silver bearing adhesives with RF stuff but often does not
adequately replace solder, as often discussed on this forum - especially
this month.
Might need radar absorbant and reflective characteristics in one bundle. Too
much to ask?
Primarily looking for what's available in the MLB and RF world without
getting into TOP SECRET stuff though the application obviously borders on
confidential.
Still need help with removing solder and intermetallics for better solder
joints but that question to be debated for some time I think. Looking
forward to answers suggested by Dave Fish and requests by Bev.
Earl Moon
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Date: Wed, 31 Oct 2001 10:37:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Kittel <[log in to unmask]>
Subject: Copper Invar Copper and BGA's
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Dear TechNet,
We have a requirement to design a CIC board using a 31mm x 31mm BGA. I am
concerned that if we design such a monster, we will not be able to replace
the BGA at a rework station because of the high thermal mass of the core.
Is anyone using BGA's on Copper Invar Copper boards? Help!
Jim Kittel
L-3 Communications
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Date: Wed, 31 Oct 2001 11:46:29 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Stanik <[log in to unmask]>
Subject: Re: STRIPPING MAGNET WIRE
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Beck Chemicals of Cleveland, Ohio used to sell a product called
EPOXYSTRIP T-251-C specifically for removing insulating varnishes
and epoxies from wire and such. It worked great.
> Looking for a recommendation for a chemical stripper to strip bi-filar (?)
> magnet wire. Any suggestions?
>
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Date: Wed, 31 Oct 2001 12:03:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Copper Invar Copper and BGA's
X-To: Jim Kittel <[log in to unmask]>
Is it the 10 mil tailoring core CIC type close to the surface? If so, this
is done with relatively "normal" rework profiling, procedures, and processes
depending on the thermal contacts to the device from the core just as if
originally soldered considering carefully the relief required. If it is the
constraining type, like 60 mil core in the MLB center, depending on layers
sandwiched around it, and has many thermal contacts to the BGA, it can be
more difficult depending on the original soldering profile.
Is this a super/perimeter BGA or, most likely, ceramic? If so, the device's
heat sink also will cause problems. On it goes. Suggest running the
experiment on dummy boards with likewise dummy components. We all need to
know more in this area of expanding concern.
MoonMan
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Date: Wed, 31 Oct 2001 10:40:38 -0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kramer <[log in to unmask]>
Organization: ThermalWorks, Inc.
Subject: Re: Copper Invar Copper and BGA's
MIME-Version: 1.0
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----- Original Message -----
From: "Jim Kittel" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, October 31, 2001 9:37 AM
Subject: [TN] Copper Invar Copper and BGA's
> Dear TechNet,
> We have a requirement to design a CIC board using a 31mm x 31mm BGA. I am
> concerned that if we design such a monster, we will not be able to replace
> the BGA at a rework station because of the high thermal mass of the core.
> Is anyone using BGA's on Copper Invar Copper boards? Help!
>
> Jim Kittel
> L-3 Communications
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>
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