Hi All Hope some one can help? We have have a board from a customer which has a PSSop-16 with a Backside Ground ( #RF2119DBP). The stencil house has made a cutout that is slightly smaller then the ground on the device. The ground plane area on the card is basically the size of the body of the part with 10 via holes in it. The customer wants evidance of solder reflow on the ends (Tinning of the Gold Plate). Current stencil does not get enough paste to do this and we are concerned that if we make the cut out larger then the device contact, the part may ride on top of the extra solder and result in opens/insufficients on the leads. Also I have been unable to find a recomended land/paste pattern for this type of device. Any ideas would be appreciated. --------------------------------------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------