Ray Prasad's text Surface Mount Technology: Chapter 7, page 315 has an illustration of what he calls "robber pads". They are not simply additional pads but small patterns perpendicular to the lands of the SOIC. He gives no data. Guy Ramsey Senior Lab Technician / Instructor E-Mail: [log in to unmask] <mailto:[log in to unmask]> Ph: (610) 362-1200 x107 Fax: (610) 362-1290 -----Original Message----- From: TechNet [mailto:[log in to unmask]]On Behalf Of Adrian Irwin Sent: Wednesday, August 15, 2001 2:07 PM To: [log in to unmask] Subject: Re: [TN] Wavesoldering SOIC's Thanks for the reply, I am actually the Black Belt leading the project but have no real process knowledge of Wavesoldering. I have an Engineer in the team who has a high level of knowledge in this area. This Engineer is closely linked to the SMART group and the feedback I am getting is that thief pads are no longer required. I am challenging this statement as the data currently being collected suggests that a thief pad may remove a large percentage of the defects. Is there any documentation to support the need of a thief pad ? Could you also comment on the expected PPM rate for wavesoldering SMT. Thanks for the fishbone, I will add these possible factors to our existing one fishbone. Thanks Neil Atkinson <Neil.Atkinson@stad To: 'Adrian Irwin' <[log in to unmask]>, 'IPC Technet' ium.co.uk> <[log in to unmask]> cc: 08/15/01 01:47 PM Subject: RE: Wavesoldering SOIC's Try a pad layout with thief pads connected to the last two pads by a very fine track. We developed this layout during a six sigma project and found it better than anything else. Does anyone else out there use this method - or should I have patented it before giving my secrets away?? Random bridges elsewhere sound to me like a process problem - perhaps you need to do more @measuring and analysing' to determine the real KPIV's before putting all your money on layout. I have carried out a few six sigma project on wave soldering so please stay in touch on how you get on. A good starting point is a good Ishikawa diagram (attached). Neil Neil Atkinson - Quality Manager Stadium Electronic Controls Division Stephen House, Brenda Road, Hartlepool TS25 2BQ (UK) <<CED ws.ppt>> -----Original Message----- From: Adrian Irwin [mailto:[log in to unmask]] Sent: 14 August 2001 12:10 Subject: Wavesoldering SOIC's I am currently involved in Black Belt project which has focussed on Wavesolder defects. We wave 0805 SMT assemblies and the majority of the defects are shorts on SOIC's. Approximately 50% of the solder shorts are on the back 2 pins, with the remaining shorts being distributed randomly across the other pins. We do not use thief pads but have elongated the pad. The current size is 0.5mm / 2mm. Do we realy need thief pads because as we are seeing 50% of the solder shorts distributed randomly across all other pins? and is it possible to achieve sub 50 ppm (DPMO) for SOIC's? Has anybody tried using a pad design that increments in length as they progress to the back pins? I am looking to set up a test pcb that will optimise the pad design, any suggestions on other pad shapes. Any help on this problem would be greatly received. ############################################################################ ######### Attention: This message is for the named person's use only. It may contain confidential, proprietary or legally privileged information. No confidentiality or privilege is waived or lost by any mistransmission. If you receive this message in error, please immediately delete it and all copies of it from your system, destroy any hard copies of it securely and notify the sender. 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(See attached file: CED ws.ppt) (See attached file: CED ws.ppt) ---------------------------------------------------------------------------- ----- Technet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------- ----- --------------------------------------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt delivery of Technet send the following message: SET Technet NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------