Help, I got an engineer moaning at me for an explanation of one of my std
design rules...

When designing a board layout, with high voltages on, I have to apply
spacing rules dependant upon the
voltage, I.E. if its at 400V I use approximately a 4mm gap between tracks.
However, the same tracks that are at 400v can come to a TO220 transistor
pads, which would be a lot closer, especially
when the transistor leads enter the body of the transistor, seemingly
negating any spacing rule that is applied on the board layout?

This has come about when I told him that "he cant put them tracks 2 thick
under that 10mm pitch cap its at 400v!" (or words to that effect).

Can someone explain the voltage/spacing rule to me sot I can pass it on.

Also, what effect does having a solder mask have on this? I always have
solder mask so any non mask problems would not arise.

Many thanks - Matthew Lamkin.

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