Earl,
I just
got in and saw your pictures. Very
interesting!
You just have to wait for the rest of the world to catch up to you
:-)
Although, I must admit that I am a little out of my
league, having no experience with 1.5 mil thick GaAs devices, I am sure that a
1.5 mil thick wafer, even GaAs, would be very flexible - but I can not see why
one would knowingly induce flexure in a device like that.
What
type of problem is showing up. Did they totally 'smoke', or just
parametric failures? - or did I not look back far enough in (possibly) unopened
posts?
Ingemar, over at Ericsson, might have a few
comments.
As for
me, if it is truely warped to this extent (and not some fluke of sectioning), my
first impression is that it is a potential indication of where voiding
'was'. I know this may be way off base, but as the melt cooled from a
semi-liquid state at 280°C, or so, the apparent pressure of any trapped gas will
drop. Just off-the-cuff, but from AuSn reflow to room temp will yield an
apparent void pressure of about 1/2 atmosphere. Thus, if the device is
flexible enough, maybe the 1 atmosphere of pressure outside the device is
causing the device to conform to the void. Far fetched, I
know.
But
continue the thought process if using something like SEC vacuum reflow
equipment. Normally, one would process the part at reduced pressure
(10-100 mT) during reflow, then proir to solidification increase the pressure to
3-5 Atm, thereby reducing the size of any residual voids. The pressure
would be maintained as the part cooled and solidified. A device that thin,
could certainly flex with these pressure differentials.
If it
is not an artifact of sectioning, and the device is not simply 'tipped' to one
side, I believe 'dimpling' of the surface of the chip would be a strong
indication of the presence (past or present) of voids beneath (Just like the
membrane of a silicone MEMs absolute pressure sensor dimples down in the
center).
Keep
us posted on what you find out.
Steven
Creswick
Gentex
Corp
Hey Moonman!
Pic's are up! Go to:
http://stevezeva.homestead.com/index.html
-Steve
Gregory-
Ladies and others,
Steve is kindly posting more ugly
pictures of the continuing component
failure analysis saga. Damn
exciting stuff, eh?
The first picture shows a "normal" view of the
device in question's
x-section. The basic construction is shown but
please note the transistor
warpage conforming to it's eutectic bond that
varies significantly in
thickness as in the next image.
Don't
know if this is a problem. Does GaAs like to "bend" that much? is the
thin section of the eutectic causing thermal problems? I don't know
because
I ain't no semiconductor expert like some of you who have kindly
answered
before.
Input appreciated with a promise of more ugly
pics not the leas of which
will be SEM/EDX analysis of the "real"
construction and the show stopper as
acoustic microscopy images taken
from the bottom side of the device after
the CIC flange is ground and
polished to a respectable depth so a 100 Mhz
transducer can sonically
examine the various layers for voiding or other
anomalies. Jeez, isn't
this great?
MoonMan