Mitch, On our high-speed boards, power is not on a plane; it is routed (usually, on it's own layer) in a 'star' strategy, with individual lines supplying power to different parts of the circuit. Ground is on a plane and is, usually, the 2nd layer down. Since micro vias require such a low aspect ratio (we maintain ~ .7:1 or less), designing a board with 50-100 ohm micro-strip lines is a real challenge, especially, if you also need to need to maintain trace width => 10 mils! This is our current configuration for 50-ohm, controlled impedance on the top layer combined with 8-mil blind vias in CSP pads. Our CSPs are .5 mm (19.7 mil) pitch with .3 mm (11.8 mil) pads. For PCBs that have CSP with only ground pads on the inside - 4-layer PCB Layer 2 is a ground plane 50-ohm line width = ~ 10 mils 8-mil layer 1 to layer 2 blind via Layer 1 base copper thickness = .7 mils Dielectric thickness, layer 1 to layer 2 = 4.6 mils 4.6 + .7 = 5.3 mils - therefore, 5.3 / 8 = .6625:1 aspect ratio 14-mil CSP pads with 8-mil blind micro vias in ground pads (pad size must be 6 over hole size for micro vias, 10 over for mechanical drill). We actually would like to have 12-mil CSP pads but had to increase their size to accommodate the 8-mil via, since we need the increased dielectric thickness in order to keep our line width up to 10 mils at 50 ohms. Sheesh! Gets tiring just typing it! :) For PCBs that have CSP with signal pads on the inside - 6-layer PCB Layer 2 is a signal layer for signals out of the center of the CSP Layer 3 is a ground plane 50-ohm line width = ~ 12.25 mils 5-mil layer 1 to layer 2 blind via 8-mil layer 1 to layer 3 blind via Layer 1 base copper thickness = .7 mils Layer 2 copper thickness = .7 mils Dielectric thickness, layer 1 to layer 2 and layer 5 to layer 6 = 2.3 mils Dielectric thickness, layer 2 to layer 3 and layer 4 to layer 5 = 2.3 mils Layer 1 to 2 - 2.3 + .7 = 3 mils - therefore, 3 / 5 = .6:1 aspect ratio Layer 1 to 3 - 2.3 + 2.3 + .7 + .7 = 6 mils - therefore, 6 / 8 = .75:1 aspect ratio In this case, 6 layers are necessary in order to keep from splitting up the ground plane directly under the CSP. Splitting the ground plane up with signal lines from the center of the CSP can create an antenna effect at higher (GHz) frequencies. I hope this has been of some help to you and/or some others. If you need additional help, please contact me with direct email. Ray -----Original Message----- From: [log in to unmask] [mailto:[log in to unmask]] Sent: Wednesday, April 04, 2001 10:33 AM To: DesignerCouncil E-Mail Forum.; Ray Humphrey; [log in to unmask] Subject: Re: [DC] Blind and Buried Vias ---------Included Message---------- > From: "Ray Humphrey" <[log in to unmask]> > Subject: Re: [DC] Blind and Buried Vias > We are starting to design with .5mm pitch, .3mm pad CSPs. This doesn't > leave room on the inner pads for anything except in-pad, micro vias. This > is especially true for PCBs in the 2 to 6 GHz range. Whhhoooya! Hi Ray, I've been looking into uVias and "vias in pads" for some time now, and have a question. Working with high speed devices nowadays the engineers are very concerned with the inductance losses at the devices, and I've worked on board where the engineer wanted two caps per power pin to cut down on the inductance loss. Going to uVias and the likes (anything under the .8mm BGAs), what does your engineer do to account for the losses since the uVias don't go directly to a power plane? And, with the line widths required for 2.5Ghz and above, and the dielectric thickness' needed for 100ohm differential signalling, and the like I can't even get directly to a GND plane. Any suggestions? Mitch _____________________________________________________________ Tired of limited space on Yahoo and Hotmail? Free 100 Meg email account available at http://www.dacafe.com --------------------------------------------------------------------------------- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. To set a vacation stop for delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------