Please be cautious on the IPC/EIA J-STD-001C interpretation.  6.4.2.2 does NOT identify this as a defect.  It refers the user to review clause 1.4 with the implication that the supplier/use have to determine how to classify nonconformance to this requirement.  The newly published IPC-HDBK-001 w/Amendment 1 provides some good words to help with the understanding (copied here), as well as an extensive cross-reference of changes between the B and C revisions.  Jack Crawford, IPC Director of Assembly Standards and Technology
 
"When the word shall appears in the document, it is stated that the associated requirement is binding. That means that the manufacturer needs to take action in order to comply with the requirements of the standard. In many cases, this is class specific, and the requirements of the text block explain the particular requirement for any given class of product.

"Where a text block includes a ‘‘No Requirement,’’ this is a characteristic that has no associated requirement in the standard. The manufacturer will need to consider the hardware being assembled and determine if a requirement needs to be imposed or if ‘‘no requirement’’ is adequate for the resultant hardware. Where a text block includes an ‘‘Acceptable’’ condition, as is the case in some situations for Class 1 hardware, the requirement does not lead to a hardware condition that requires disposition. In many instances, a unique text block exists that includes the words ‘‘Requirement See 1.4.’’ When this is given, it means that this requirement must be met for compliance to the standard.

"The manufacturer (assembler) is tasked with determining the course of action to take. As needed, the user (customer) may participate in the development of corrective actions. J-STD-001C does not address hardware conditions with the ‘‘Requirement See 1.4’’ phrase but rather manufacturing system failures (such as process control, material compatibility, etc.). A review of the noncompliance and the appropriate corrective action plan with the customer may be required depending on the severity of the noncompliance or an internal correction may be enough."

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Hello all.  We recently received some boards with some of the chip resistors placed with their resistive elements towards the board.  J-STD-001B and C view this as violation for both Class 2 and Class 3.  However when you compare this with IPC-A-610C it is only a process indicator for Classes 2 and 3.  The relevant sections are

 

J-STD-001C

 

6.4.2.2 Devices with External Deposited Elements

 

IPC-A-610C

 

12.3.2 Chip Components – Termination Variations – Deposited Electrical Elements – Mounting Upside Down.

 

So…..who is correct?  Does it matter?

 

Alex Krstic

 

NovAtel Inc.