Hi Clive! Take a look at paragraph 6.4.3, page 59 in the IPC-HDBK-001 document- a good explanation of why "stacking" is frowned upon can be found there. The two main reasons for not stacking are: 1) component damage; (2) manufacturability. Good luck. Dave Hillman Rockwell Collins [log in to unmask] Clive ffitch <[log in to unmask]>@IPC.ORG> on 10/20/2000 04:58:35 AM Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to [log in to unmask] Sent by: TechNet <[log in to unmask]> To: [log in to unmask] cc: Subject: [TN] IPC Standards on Stacked Chip Components All, I've searched the TechNet archives and only found similar confusion. From my perspective in electronics packaging design, I am looking for standards/documented reasons (evidence for others - you know how it is!) NOT to stack chip resistors/capacitors. Reasons basically boil down to reliability concerns for high-rel use, and I am advising against such courses of action. The issue is where stacking of components might be covered in the IPC specs. The only reference I have been able to find is in the now superceded IPC-D-275, in para. 4.4.2.1 "End-Capped Discrete components" which quite catagorically states "...shall not be stacked, nor shall they bridge spacing between other parts or components... see Figure 4-38". The figure is equally explicit. However, when I consult the new IPC-2221 Printed Board Design Standard, I find all this has gone! The only reference I now find in its place, is in the latest Rev.C of IPC J-STD-001 in para. 6.4.2.1 "Mounting of Parts on Parts (Stacking)" which states "When part stacking is permitted by the assembly drawing/documentation, parts shall not violate minimum electrical clearance...". This now implies that even for Class 3, if its on the drawing you can do it. Which means you can still put it on the drawing for high-rel Class 3 and do it, as long as you don't short it out! Which rather neatly avoids the issue and bounces it back on the user of the Standard. So, why has the clear statement against this gone from the IPC design standard? Does the IPC - and the rest of industry - think that stacking components for Class 3 is now OK? For our own case in point, I have advised adhesively mounting the additional chip locally to the first, and using jumper wires. Regards, Clive ffitch MBUK Stevenage, England --------------------------------------------------------------------------------- TechNet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF TECHNET Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- TechNet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF TECHNET Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------