1. Possibly, for worst case scenario, this formula was given to cover any via design, whether thru, blind, or buried. 2. Consider copper plating thickness as all-inclusive. Some pcb manufacturers use 2 processes for plating; the first is a thin plating of electroless copper, the second is the heavier electro-plated copper. The first plating process in this case adds a negligible amount of thickness, unless the pcb fabricator uses all electroless plating (can't imagine why). 3. Gold and silver platings are typically very thin, and add little to the current-carrying capacity of a trace or via. For tin/lead plating, solder has a resistance about 7 or 8 times that of copper, and the finished thickness of solder is not consistent from batch to batch. I typically specify a finished thickness (of solder) in the range og 0.0003" to 0.002". We went through the exercise of determining this years ago, and our conclusion was the thickness of tin/lead platings need not be considered. (Another reason not to consider tin/lead plating is that for SMT boards, a consistently thin coating of a solderable material is the best surface to solder SMD devices to, to reduce coplanarity issues.) Hope that helps. Some body else may want to elaborate on this... back to the salt mines for me... Roger M. Stoops, C.I.D., PCB Designer Spectra Precision Inc./Trimble Navigation Ltd. 5475 Kellenburger Rd. Dayton, OH 45424-1099 USA Ph: 937.233.8921 or 937.233.4574 ext 288 Fax: 937.233.7511 Lum Wee Mei <[log in to unmask] To: [log in to unmask] ORG.SG> cc: Sent by: Subject: [TN] Via current current capacity TechNet <[log in to unmask] ORG> 08/11/00 05:59 AM Please respond to "TechNet E-Mail Forum."; Please respond to Lum Wee Mei I came across this paragraph in Printed Circuit Handbook by Clyde Coombs, Jr stating : "Consider a 0.04" diameter hole plated to a 2oz internal poew plane with 0.001" minimum copper in the hole. The copper hole wall is equivalent to 0.04 x 0.001 x pi = 125 x 10exp -6 sq. in. "The copper plating of the hole wall is the smallest conductor in the path and for purposes of calculation in current-carrying capacity, consider it an internal conductor of a multilayer." My questions are : 1. Why consider the copper plating of the hole wall as internal layer and not external? 2. Is the copper plating here which is 0.001" refers to only the electroless copper thickness or inclusive of copper plating? 3. Why is the tin-lead plating or gold plating never be considered when calculating current-carrying capacity for component hole or via? Hope to learn more from your experts out there. Regards. ############################################################## TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c ############################################################## To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TECHNET <your full name> To unsubscribe: SIGNOFF TECHNET ############################################################## Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information. If you need assistance - contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ############################################################## ############################################################## TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c ############################################################## To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TECHNET <your full name> To unsubscribe: SIGNOFF TECHNET ############################################################## Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information. If you need assistance - contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ##############################################################