Please do not send attachments as they can include viruses.  I would like to
see the information.

Carey
-----Original Message-----
From: Clive ffitch <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Thursday, March 16, 2000 1:00 AM
Subject: Re: [TN] ITO conductive coating for glass

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Date:         Thu, 16 Mar 2000 11:16:56 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Severson, Scott M." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Severson, Scott M." <[log in to unmask]>
Subject:      Re: VOC legislation - evolved to dark
X-To:         Richard Tilbrook <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

All,

This question took an interesting turn, so I went for an expert opinion from
my Physics professor.  See the following:

Scott

>Good Morning Dr. Otto,
>
>I have been involved in a philosophical discussion concerning Infrared
>radiation spectrums.  Some of the questions that have come up that nobody
>can seem to answer are as follows:
>
>    1)    At what point does a substance quit emitting an infrared
>radiation? Absolute zero?
>
>    2)    Do most substances emit IR radiation?
>                I think that it is a relative thing based on the
surrounding
>of the object.  In order to achieve equilibrium the object will either
>absorb or give of IR radiation (heat) based on the temperature differential
>between it and its surroundings.
>
>Any comments.
>
>Scott

Hi, Scott:

In answer to question 1):  All matter emits blackbody radiation due to
thermal motion, at any temperature above absolute zero.  However, the peak
wavelength is inversely proportional to temperature, given by (peak
wavelength in meters) x (temperature in Kelvin) = 2.898 x 10^3 m-K.  So,
as the temperature gets smaller, the peak wavelength gets longer.  At body
temperature, this peak is around 10 microns, in the Far Infrared.  At
higher temperatures, the peak wavelength decreases until an appreciable
amount of light is in the visible region ("red-hot").  At lower
temperatures, the wavelength increases, into the microwave region (1 mm
waves at about 3 Kelvin), and eventually to radio wavelengths, in the
milli-Kelvin region.  However, the amount of power emitted is proportional
to T^4, so as the temperature drops, the amount of power drops drastically.

Question 2):  Every substance emits IR, although substances which are
"black" (good absorbers) are the best emitters.  The "emissivity" is a
measure of how good an emitter a particular substance is.  A perfect black
body has an emissivity of 1.0,  whereas polished copper has an emissivity
of about 0.02, meaning that it emits only 2% as well as a black body.

You are correct in thinking that it is a relative thing, since the
surroundings are also emitting IR continuously.  This is one of the heat
transfer mechanisms that help establish temperature equilibrium.  To check
this, all you have to do is stand near a window (out of direct sunlight) on
a cold winter day.  You can feel cold "radiating in" at you on the side
nearest the window, because your blackbody radiation is radiating away to
the outside world, and less radiation is radiating back at you from the
colder outside environment.

So, in a nutshell, the rate of heat transfer due to radiation is
approximately proportional to the temperature differential between the
object and its surroundings.  This is known as "Newton's Law of Cooling".

Have Fun!

-- Dr. Otto



-----Original Message-----
From: Richard Tilbrook [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 9:22 AM
To: [log in to unmask]
Subject: Re: [TN] VOC legislation - evolved to dark


I am not in any way en expert, but I would have thought that the sea emits
IR at a
low level, especially when compared to a human body. I would also have
thought that
a block of dry ice would emit a tiny amount of IR, possibly not detectable
with
current equipment. I would have thought that something like a low
temperature
superconductor, when in superconductive state, would emit no IR. Is this so?
Or
would something have to be at absolute zero to emit no IR?

Richard





[log in to unmask] on 16/03/2000 13:05:35
Please respond to [log in to unmask]@INTERNET@wtgw
To:     [log in to unmask]@INTERNET@wtgw
cc:
Subject:        Re: [TN] VOC legislation - evolved to dark

                   *** WARNING ***

This mail has originated outside your organization,
either from an external partner or the Global Internet.
     Keep this in mind if you answer this message.


Nope... they wouldn't be dead.. The sea, even if very cold still has an IR
Signature itself... Proof, add an ice cube, do IR detection magnification,
you can sea the cube as colder... Even colder dry ice will give you better
differentiation.

Alain Savard

-----Original Message-----
From: Smith Russell MSM LAPO US [mailto:[log in to unmask]]
Sent: March 16, 2000 8:13 AM
To: [log in to unmask]
Subject: Re: [TN] VOC legislation - evolved to dark


Ah , to throw the proverbial Monkey Wrench into the works
         Have you considered submergence in Water, Either Sea of Fresh?
        Since IR transmission in Water is minimal , Aquatic plants and
animals exist in the ambient temperature. ( trying to raise body temperature
in such a heat sink would be a tremendous energy cost )
        Since there is no discernible infrared signature from the aquatic
life,
          then by the logic would they not be considered dead?

Russell Smith
Ciba Specialty Chemicals

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Date:         Thu, 16 Mar 2000 09:20:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      ito
MIME-Version: 1.0
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hi,

indium tin oxide

phil

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Date:         Thu, 16 Mar 2000 12:22:38 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hollandsworth, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hollandsworth, Ron" <[log in to unmask]>
Subject:      Spamming and The Good Ole Boys
Mime-Version: 1.0
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Opinion of someone whos been on this TechNet for about four years or so.

I just ask some questions about Gold removal..  Yeah this is Good Ole Ron
Hollandsworth . . .  I understand the breadth of my problem, things I could
possibly do, and end the end with some joking around, what a sensible thing
is to do.

Even with the chidding, I picked out right from wrong, costly things to do,
and dangerous things to do.  If I don't know whats going on with a subject I
delete or if curious, let it ride for a while.


Anyhow,  it's Thursday  almost Friday, March Madness is here,  and blah blah
blah, see I feel better already.

Still a good forum

Hey Jeff What's happening?
Ron Hollandsworth

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Date:         Thu, 16 Mar 2000 11:26:10 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: VOC legislation - evolved to dark
X-To:         "Severson, Scott M." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

~clap clap clap...~ Bravo...


----- Original Message -----
From: Severson, Scott M. <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 9:16 AM
Subject: Re: [TN] VOC legislation - evolved to dark


> All,
>
> This question took an interesting turn, so I went for an expert opinion
from
> my Physics professor.  See the following:
>
> Scott
>
> >Good Morning Dr. Otto,
> >
> >I have been involved in a philosophical discussion concerning Infrared
> >radiation spectrums.  Some of the questions that have come up that nobody
> >can seem to answer are as follows:
> >
> >    1)    At what point does a substance quit emitting an infrared
> >radiation? Absolute zero?
> >
> >    2)    Do most substances emit IR radiation?
> >                I think that it is a relative thing based on the
> surrounding
> >of the object.  In order to achieve equilibrium the object will either
> >absorb or give of IR radiation (heat) based on the temperature
differential
> >between it and its surroundings.
> >
> >Any comments.
> >
> >Scott
>
> Hi, Scott:
>
> In answer to question 1):  All matter emits blackbody radiation due to
> thermal motion, at any temperature above absolute zero.  However, the peak
> wavelength is inversely proportional to temperature, given by (peak
> wavelength in meters) x (temperature in Kelvin) = 2.898 x 10^3 m-K.  So,
> as the temperature gets smaller, the peak wavelength gets longer.  At body
> temperature, this peak is around 10 microns, in the Far Infrared.  At
> higher temperatures, the peak wavelength decreases until an appreciable
> amount of light is in the visible region ("red-hot").  At lower
> temperatures, the wavelength increases, into the microwave region (1 mm
> waves at about 3 Kelvin), and eventually to radio wavelengths, in the
> milli-Kelvin region.  However, the amount of power emitted is proportional
> to T^4, so as the temperature drops, the amount of power drops
drastically.
>
> Question 2):  Every substance emits IR, although substances which are
> "black" (good absorbers) are the best emitters.  The "emissivity" is a
> measure of how good an emitter a particular substance is.  A perfect black
> body has an emissivity of 1.0,  whereas polished copper has an emissivity
> of about 0.02, meaning that it emits only 2% as well as a black body.
>
> You are correct in thinking that it is a relative thing, since the
> surroundings are also emitting IR continuously.  This is one of the heat
> transfer mechanisms that help establish temperature equilibrium.  To check
> this, all you have to do is stand near a window (out of direct sunlight)
on
> a cold winter day.  You can feel cold "radiating in" at you on the side
> nearest the window, because your blackbody radiation is radiating away to
> the outside world, and less radiation is radiating back at you from the
> colder outside environment.
>
> So, in a nutshell, the rate of heat transfer due to radiation is
> approximately proportional to the temperature differential between the
> object and its surroundings.  This is known as "Newton's Law of Cooling".
>
> Have Fun!
>
> -- Dr. Otto
>
>
>
> -----Original Message-----
> From: Richard Tilbrook [mailto:[log in to unmask]]
> Sent: Thursday, March 16, 2000 9:22 AM
> To: [log in to unmask]
> Subject: Re: [TN] VOC legislation - evolved to dark
>
>
> I am not in any way en expert, but I would have thought that the sea emits
> IR at a
> low level, especially when compared to a human body. I would also have
> thought that
> a block of dry ice would emit a tiny amount of IR, possibly not detectable
> with
> current equipment. I would have thought that something like a low
> temperature
> superconductor, when in superconductive state, would emit no IR. Is this
so?
> Or
> would something have to be at absolute zero to emit no IR?
>
> Richard
>
>
>
>
>
> [log in to unmask] on 16/03/2000 13:05:35
> Please respond to [log in to unmask]@INTERNET@wtgw
> To:     [log in to unmask]@INTERNET@wtgw
> cc:
> Subject:        Re: [TN] VOC legislation - evolved to dark
>
>                    *** WARNING ***
>
> This mail has originated outside your organization,
> either from an external partner or the Global Internet.
>      Keep this in mind if you answer this message.
>
>
> Nope... they wouldn't be dead.. The sea, even if very cold still has an IR
> Signature itself... Proof, add an ice cube, do IR detection magnification,
> you can sea the cube as colder... Even colder dry ice will give you better
> differentiation.
>
> Alain Savard
>
> -----Original Message-----
> From: Smith Russell MSM LAPO US [mailto:[log in to unmask]]
> Sent: March 16, 2000 8:13 AM
> To: [log in to unmask]
> Subject: Re: [TN] VOC legislation - evolved to dark
>
>
> Ah , to throw the proverbial Monkey Wrench into the works
>          Have you considered submergence in Water, Either Sea of Fresh?
>         Since IR transmission in Water is minimal , Aquatic plants and
> animals exist in the ambient temperature. ( trying to raise body
temperature
> in such a heat sink would be a tremendous energy cost )
>         Since there is no discernible infrared signature from the aquatic
> life,
>           then by the logic would they not be considered dead?
>
> Russell Smith
> Ciba Specialty Chemicals
>
> ##############################################################
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> information.
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> 847-509-9700 ext.5315
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>
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Date:         Thu, 16 Mar 2000 11:26:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Worst than spam
X-To:         "Howieson, Rick" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Rick, you don't know what your title is? Hmmm, I've only been here two years
and I'll never forget my job title, are you ready for this...Manager of
Quality Assurance, Safety, Information, Complaints [internal & external],
Reliability, Business Systems Responsibility, Internal Network, Computer
Systems, Training, Web Issues and Quality Management Systems Coordinator.

Needless to say my business card is on a 3" X 5"...

I gotta say though, I really love what I do and wouldn't want to change a
thing...

Franklin

----- Original Message -----
From: Howieson, Rick <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 8:35 AM
Subject: Re: [TN] Worst than spam


> In the four or so months I've been with TechNet, I can honestly say that
> I have gained a wealth of knowledge in a short period I may not have
> gotten elsewhere. Some topics don't directly relate to my job function
> (whatever that might be today) but it is valuable information from a
> well educated and experienced group. I enjoy the occasional ribbing,
> joking ... call it what you may it breaks up the monotony of sometimes
> being too serious.
> Thank You TechNet!
> Rick Howieson
> GTC
>
> >-----Original Message-----
> >From:  Jeff Hempton [SMTP:[log in to unmask]]
> >Sent:  Thursday, March 16, 2000 9:10 AM
> >To:    [log in to unmask]
> >Subject:       Re: [TN] Worst than spam
> >
> >     I have to admit, through the course of time, it's the "Emergency
topic
> >     of the Hour" in my factory that grabs my interest, and many topics I
> >     hit the delete key. Am I interested in "gold" topics today? No.
> >
> >      But holy cow, it's now a major issue on two of our high volume
> >     products, and I'm referencing the blessed TechNet archives!!!
> >
> >     After battling board contamination, solder balls, soldermask flakes,
> >     via plugging, embrittlement, (add your emergency of the day), I
enjoy
> >     tid-bits of humor mixed with the technical stuff, sometimes it makes
> >     the end of the day a little more bearable!
> >     Just me $.02....
> >
> >     Jeff Hempton
> >     UT Electronic Controls
> >
> >
> >______________________________ Forward Header
> >__________________________________
> >Subject: Re: [TN] Worst than spam
> >Author:  Brian Ellis <[log in to unmask]> at Internet
> >Date:    03/16/2000 6:05 PM
> >
> >
> >Phil
> >
> >All work, no play....
> >
> >Anyway, to the average guy, what percentage of the messages are actually
> >relevant to
> >his work? 10%?
> >
> >Brian
> >
> >"Phillip E. Hinton" wrote:
> >
> >> Technetters
> >>
> >> I am finding that "Technet" is becoming a "good old boys club" where
> >>members
> >> sit around and tell jokes and trade insults.  When 1/2 of my technet
> >>message
> >> are not worth reading, I want to dump the whole thing.  Why do not
those
> >>guys
> >> who like to "get away" from the tech forum form another forum where
they
> >>can
> >> do their thing.
> >> I am suggesting that we use technet for what it was meant to do.
> >>
> >> Phil Hinton
> >>
> >> ##############################################################
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> >> information.
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> >> 847-509-9700 ext.5315
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=========================================================================
Date:         Thu, 16 Mar 2000 11:37:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: UV cured white marking ink
X-To:         JACOB MOZEL <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0136_01BF8F3C.0F598D00"

This is a multi-part message in MIME format.

------=_NextPart_000_0136_01BF8F3C.0F598D00
Content-Type: text/plain;
        charset="windows-1255"
Content-Transfer-Encoding: quoted-printable

UV cured white marking inkWe're using a UV ink I believe from Coates. =
I've never witnessed nor heard from any customer about yellowing.=20

Franklin
  ----- Original Message -----=20
  From: JACOB MOZEL=20
  To: [log in to unmask]
  Sent: Thursday, March 16, 2000 7:02 AM
  Subject: [TN] UV cured white marking ink


  We consider using white, UV cured marking ink. Our doubts are due to =
the "fame" of those inks, which states, that the yellowing of the ink =
during the UV curing is unavoidable.

   Could anybody comment, based on experience printing those inks.=20

  Thanks=20

  Jacob=20


------=_NextPart_000_0136_01BF8F3C.0F598D00
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>UV cured white marking ink</TITLE>
<META content=3D"text/html; charset=3Dwindows-1255" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>We're using a UV ink I believe from =
Coates. I've=20
never witnessed nor heard from any customer about yellowing. =
</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>JACOB MOZEL</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 16, 2000 =
7:02=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] UV cured white =
marking=20
  ink</DIV>
  <DIV><BR></DIV>
  <P><FONT face=3DArial size=3D2>We consider using white, UV cured =
marking ink. Our=20
  doubts are due to the "fame" of those inks, which states, that the =
yellowing=20
  of the ink during the UV curing is unavoidable.</FONT></P>
  <P><FONT face=3DArial size=3D2>&nbsp;Could anybody comment, based on =
experience=20
  printing those inks.</FONT> </P>
  <P><FONT face=3DArial size=3D2>Thanks </FONT></P>
  <P><FONT face=3DArial size=3D2>Jacob</FONT> =
</P></BLOCKQUOTE></BODY></HTML>

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Date:         Thu, 16 Mar 2000 12:50:43 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
Subject:      Re: UV cured white marking ink
X-To:         Franklin Asbell <[log in to unmask]>
In-Reply-To:  <013901bf8f7f$1e4dd8a0$6400a8c0@franklin>
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UV cured white marking inkI have seen White ink turn yellow or brownish in
color but only after being re H.A.S.L

William W. DeCray III
Waytec Electronics Corp
Sales Engineer
PHONE:(804) 237-6391 ext 115
FAX:    (804) 237-1324
E-mail:<[log in to unmask]>
Web <http://www.waytec.com>
FTP <ftp://ftp.waytec.com>



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Franklin Asbell
Sent: Thursday, March 16, 2000 2:38 PM
To: [log in to unmask]
Subject: Re: [TN] UV cured white marking ink


We're using a UV ink I believe from Coates. I've never witnessed nor heard
from any customer about yellowing.

Franklin
  ----- Original Message -----
  From: JACOB MOZEL
  To: [log in to unmask]
  Sent: Thursday, March 16, 2000 7:02 AM
  Subject: [TN] UV cured white marking ink


  We consider using white, UV cured marking ink. Our doubts are due to the
"fame" of those inks, which states, that the yellowing of the ink during the
UV curing is unavoidable.

   Could anybody comment, based on experience printing those inks.

  Thanks

  Jacob


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>UV cured white marking ink</TITLE>
<META content=3D"text/html; charset=3Dwindows-1255" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#0000ff face=3D"Comic Sans MS"><SPAN =
class=3D110234917-16032000>I=20
have seen White ink turn yellow or brownish in color but only after =
being re=20
H.A.S.L</SPAN></FONT></DIV>
<DIV>&nbsp;</DIV>
<P><FONT size=3D2>William W. DeCray III<BR>Waytec Electronics =
Corp<BR>Sales=20
Engineer<BR>PHONE:(804) 237-6391 ext 115<BR>FAX:&nbsp;&nbsp;&nbsp; (804) =

237-1324<BR>E-mail:&lt;[log in to unmask]&gt;<BR>Web &lt;<A=20
href=3D"http://www.waytec.com/" =
target=3D_blank>http://www.waytec.com</A>&gt;<BR>FTP=20
&lt;<A href=3D"ftp://ftp.waytec.com/"=20
target=3D_blank>ftp://ftp.waytec.com</A>&gt;<BR><BR></FONT></P>
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Franklin =
Asbell<BR><B>Sent:</B>=20
Thursday, March 16, 2000 2:38 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] UV cured white marking=20
ink<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>We're using a UV ink I believe from =
Coates. I've=20
never witnessed nor heard from any customer about yellowing. =
</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>JACOB MOZEL</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 16, 2000 =
7:02=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] UV cured white =
marking=20
  ink</DIV>
  <DIV><BR></DIV>
  <P><FONT face=3DArial size=3D2>We consider using white, UV cured =
marking ink. Our=20
  doubts are due to the "fame" of those inks, which states, that the =
yellowing=20
  of the ink during the UV curing is unavoidable.</FONT></P>
  <P><FONT face=3DArial size=3D2>&nbsp;Could anybody comment, based on =
experience=20
  printing those inks.</FONT> </P>
  <P><FONT face=3DArial size=3D2>Thanks </FONT></P>
  <P><FONT face=3DArial size=3D2>Jacob</FONT> =
</P></BLOCKQUOTE></BODY></HTML>

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BEGIN:VCARD
VERSION:2.1
N:DeCray;Bill
FN:Bill DeCray
ORG:Waytec Electronics
TITLE:Methods Engineer
TEL;WORK;VOICE:(804) 237-6391
TEL;HOME;VOICE:(804) 525-2093
TEL;WORK;FAX:(804) 239-1324
ADR;WORK:;;1104 McConville Road;Lynchburg;Virginia;24506;United States =
of America
LABEL;WORK;ENCODING=3DQUOTED-PRINTABLE:1104 McConville =
Road=3D0D=3D0ALynchburg, Virginia 24506=3D0D=3D0AUnited States of Am=3D
erica
EMAIL;PREF;INTERNET:[log in to unmask]
REV:20000228T134054Z
END:VCARD

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Date:         Thu, 16 Mar 2000 10:03:16 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Eric Miller <[log in to unmask]>
Subject:      Re: MCM Lead Tinning Equipment and/or Contractors
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Try Corfin Industries, they are located at: Corfin Industries, 7B Raymond
Ave, Unit 7, Salem New Hampshire. Andy Bloom Or Tom Hamel. 603-893-9900.
They are the in the industry.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Timothy Tezak
Sent: Thursday, March 16, 2000 7:02 AM
To: [log in to unmask]
Subject: [TN] MCM Lead Tinning Equipment and/or Contractors


Can anyone send me information on equipment and/or contractors that can do
both gold removal and subsequent tinning of leaded MCM devices?

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Date:         Thu, 16 Mar 2000 12:13:24 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: UV cured white marking ink
X-To:         Bill Decray <[log in to unmask]>
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UV cured white marking inkOf course, added thermal cycles to just about =
anything will discolor it (let your minds wander on that one)

What I was referring to was our finished product, being used as it was =
intended by our customer, being right the first time, and perhaps after =
minor touch-ups or repairs by our customer.

We had a customer in here last month, the boards they brought with them =
had been through six-month environmental testing, gotta say the symbol =
was yellow on those bad boys... But they went through in part, a 3-day =
caustic/humid cucyl representing 10 years aging.

As far as yellowing symbol, if it yellows after the first thermo-cycle =
I'd say you got some poor symbol ink and need to replace it.

Franklin
  ----- Original Message -----=20
  From: Bill Decray=20
  To: [log in to unmask]
  Sent: Thursday, March 16, 2000 9:50 AM
  Subject: Re: [TN] UV cured white marking ink


  I have seen White ink turn yellow or brownish in color but only after =
being re H.A.S.L

  William W. DeCray III
  Waytec Electronics Corp
  Sales Engineer
  PHONE:(804) 237-6391 ext 115
  FAX:    (804) 237-1324
  E-mail:<[log in to unmask]>
  Web <http://www.waytec.com>
  FTP <ftp://ftp.waytec.com>



  -----Original Message-----
  From: TechNet [mailto:[log in to unmask]]On Behalf Of Franklin Asbell
  Sent: Thursday, March 16, 2000 2:38 PM
  To: [log in to unmask]
  Subject: Re: [TN] UV cured white marking ink


  We're using a UV ink I believe from Coates. I've never witnessed nor =
heard from any customer about yellowing.=20

  Franklin
    ----- Original Message -----=20
    From: JACOB MOZEL=20
    To: [log in to unmask]
    Sent: Thursday, March 16, 2000 7:02 AM
    Subject: [TN] UV cured white marking ink


    We consider using white, UV cured marking ink. Our doubts are due to =
the "fame" of those inks, which states, that the yellowing of the ink =
during the UV curing is unavoidable.

     Could anybody comment, based on experience printing those inks.=20

    Thanks=20

    Jacob=20


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        charset="windows-1255"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>UV cured white marking ink</TITLE>
<META content=3D"text/html; charset=3Dwindows-1255" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Of course, added thermal cycles to just =
about=20
anything will discolor it (let your minds wander on that =
one)</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>What I was referring to was our =
finished product,=20
being used as it was intended by our customer, being right the first =
time, and=20
perhaps after minor touch-ups or repairs by our customer.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>We had a customer in here last month, =
the boards=20
they brought with them had been through six-month environmental testing, =
gotta=20
say the symbol was yellow on those bad boys... But they went through in =
part, a=20
3-day caustic/humid cucyl representing 10 years aging.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>As far as yellowing symbol, if it =
yellows after the=20
first thermo-cycle I'd say you got some poor symbol ink and need to =
replace=20
it.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>Bill =
Decray</A>=20
</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 16, 2000 =
9:50=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] UV cured =
white marking=20
  ink</DIV>
  <DIV><BR></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Comic Sans MS"><SPAN =
class=3D110234917-16032000>I=20
  have seen White ink turn yellow or brownish in color but only after =
being re=20
  H.A.S.L</SPAN></FONT></DIV>
  <DIV>&nbsp;</DIV>
  <P><FONT size=3D2>William W. DeCray III<BR>Waytec Electronics =
Corp<BR>Sales=20
  Engineer<BR>PHONE:(804) 237-6391 ext 115<BR>FAX:&nbsp;&nbsp;&nbsp; =
(804)=20
  237-1324<BR>E-mail:&lt;<A=20
  href=3D"mailto:[log in to unmask]">[log in to unmask]</A>&gt;<BR>Web =
&lt;<A=20
  href=3D"http://www.waytec.com"=20
  target=3D_blank>http://www.waytec.com</A>&gt;<BR>FTP &lt;<A=20
  href=3D"ftp://ftp.waytec.com"=20
  target=3D_blank>ftp://ftp.waytec.com</A>&gt;<BR><BR></FONT></P>
  <DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
  [mailto:[log in to unmask]]<B>On Behalf Of </B>Franklin =
Asbell<BR><B>Sent:</B>=20
  Thursday, March 16, 2000 2:38 PM<BR><B>To:</B>=20
  [log in to unmask]<BR><B>Subject:</B> Re: [TN] UV cured white marking=20
  ink<BR><BR></FONT></DIV>
  <DIV><FONT face=3DArial size=3D2>We're using a UV ink I believe from =
Coates. I've=20
  never witnessed nor heard from any customer about yellowing. =
</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT face=3DArial size=3D2>Franklin</FONT></DIV>
  <BLOCKQUOTE=20
  style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
    <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
    <DIV=20
    style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
    <A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>JACOB=20
    MOZEL</A> </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
    [log in to unmask]>[log in to unmask]</A> </DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 16, =
2000 7:02=20
    AM</DIV>
    <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] UV cured white =
marking=20
    ink</DIV>
    <DIV><BR></DIV>
    <P><FONT face=3DArial size=3D2>We consider using white, UV cured =
marking ink.=20
    Our doubts are due to the "fame" of those inks, which states, that =
the=20
    yellowing of the ink during the UV curing is unavoidable.</FONT></P>
    <P><FONT face=3DArial size=3D2>&nbsp;Could anybody comment, based on =
experience=20
    printing those inks.</FONT> </P>
    <P><FONT face=3DArial size=3D2>Thanks </FONT></P>
    <P><FONT face=3DArial size=3D2>Jacob</FONT>=20
</P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>

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Date:         Thu, 16 Mar 2000 13:29:00 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
CONNECTOR FINGERS.
MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE THEY
ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS

William W. DeCray III
Waytec Electronics Corp
Sales Engineer
PHONE:(804) 237-6391 ext 115
FAX:    (804) 237-1324
E-mail:<[log in to unmask]>
Web <http://www.waytec.com>
FTP <ftp://ftp.waytec.com>

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Date:         Thu, 16 Mar 2000 10:37:55 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Sean Hager <[log in to unmask]>
Subject:      Re: Worst than spam
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

The irony of an AOL user complaining of to much spam.

I like tech-net just the way it is.

Sean



From: "Phillip E. Hinton" <[log in to unmask]> on 03/16/2000 03:27 PM GMT

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
      to [log in to unmask]

To:   [log in to unmask]
cc:    (bcc: Sean Hager/US/Centigram)
Subject:  [TN] Worst than spam




Technetters

I am finding that "Technet" is becoming a "good old boys club" where
members
sit around and tell jokes and trade insults.  When 1/2 of my technet
message
are not worth reading, I want to dump the whole thing.  Why do not those
guys
who like to "get away" from the tech forum form another forum where they
can
do their thing.
I am suggesting that we use technet for what it was meant to do.

Phil Hinton

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Date:         Thu, 16 Mar 2000 11:37:08 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      Re: VOC legislation - evolved to dark
X-To:         Richard Tilbrook <[log in to unmask]>

Richard,
        By definition, if an electron moves, it radiates energy (photons),
but not necessarily infrared.  So if a superconductor is conducting current,
electrons are changing positions and emitting energy.  The only way to stop
the emission of energy is to stop the movement of charged particles, which
means the object would have to be in the ground state of energy, which is at
absolute zero.  (This is why models of atoms showing electrons orbiting the
nucleus are untrue.  Electrons orbiting a nucleus would radiate all of their
energy until they collapsed into the nucleus.)

Ryan G.

> -----Original Message-----
> From: Richard Tilbrook [SMTP:[log in to unmask]]
> Sent: Thursday, March 16, 2000 8:22 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] VOC legislation - evolved to dark
>
> I am not in any way en expert, but I would have thought that the sea emits
> IR at a
> low level, especially when compared to a human body. I would also have
> thought that
> a block of dry ice would emit a tiny amount of IR, possibly not detectable
> with
> current equipment. I would have thought that something like a low
> temperature
> superconductor, when in superconductive state, would emit no IR. Is this
> so? Or
> would something have to be at absolute zero to emit no IR?
>
> Richard
>
>
>
>
>
> [log in to unmask] on 16/03/2000 13:05:35
> Please respond to [log in to unmask]@INTERNET@wtgw
> To:     [log in to unmask]@INTERNET@wtgw
> cc:
> Subject:        Re: [TN] VOC legislation - evolved to dark
>
>                    *** WARNING ***
>
> This mail has originated outside your organization,
> either from an external partner or the Global Internet.
>      Keep this in mind if you answer this message.
>
>
> Nope... they wouldn't be dead.. The sea, even if very cold still has an IR
> Signature itself... Proof, add an ice cube, do IR detection magnification,
> you can sea the cube as colder... Even colder dry ice will give you better
> differentiation.
>
> Alain Savard
>
> -----Original Message-----
> From: Smith Russell MSM LAPO US [mailto:[log in to unmask]]
> Sent: March 16, 2000 8:13 AM
> To: [log in to unmask]
> Subject: Re: [TN] VOC legislation - evolved to dark
>
>
> Ah , to throw the proverbial Monkey Wrench into the works
>          Have you considered submergence in Water, Either Sea of Fresh?
>         Since IR transmission in Water is minimal , Aquatic plants and
> animals exist in the ambient temperature. ( trying to raise body
> temperature
> in such a heat sink would be a tremendous energy cost )
>         Since there is no discernible infrared signature from the aquatic
> life,
>           then by the logic would they not be considered dead?
>
> Russell Smith
> Ciba Specialty Chemicals
>
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Date:         Thu, 16 Mar 2000 13:39:02 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Larry Tawyea <[log in to unmask]>
Subject:      Re: Worst than spam
X-To:         [log in to unmask]
MIME-Version: 1.0
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To Technet and Phil,

I agree, this is not a club to tell jokes or converse in personal banter.

Larry Tawyea

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Date:         Thu, 16 Mar 2000 13:49:08 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Electromigration demonstration...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

How the heck are yew good ol' boys doin'?

(Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk with a
mouthful of terbacky...(hitchin' my bib overalls up)

Anyhoo, a while back, some good ol' boy posted a simple way to actually show
electromigration (fancy word for us country boys ain't it) in progress...you
could actually see it happening. Something about using an overhead projector
and a 9-volt battery...or something like that.

Does anybody remember that? I need some way to graphically show this
phenomena  happening...('nuther fancy word huh?...phenomena...)

YEEEE-HAW!!!
(that's good ol' boy talk for thanks a lot!)

-Steve "Jethro" Gregory- (GRIN)

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Date:         Thu, 16 Mar 2000 12:54:26 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Kell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Kell <[log in to unmask]>
Subject:      BRUSHES TO REMOVE SOLDER BALLS -Reply
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Actually, I just purchased a toothbrush for home use (teeth).  Its call a =
SONICARE and sells at drugstores and Walmart for under $100.  It comes =
with two heads and additional heads are $15.

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Date:         Thu, 16 Mar 2000 11:00:28 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      Re: ??: [TN] Gold Removal
X-To:         "Misner, Bruce" <[log in to unmask]>,
              "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Bruce, Ryan, et al.
I wasn't saying that 30 microinches of gold would embrittle a solder joint.
Truth is, I didn't know (until now) how much it would take. All I knew was
that too much gold would lead to problems, and it sounded to me like this
fellow to whom I replied believed you could put as much on as you wanted and
never think about it. I wanted to dispel that.
Tim Reeves
PS I am with a board fab-we just don't do our own immersion gold.
> ----------
> From:         Misner, Bruce
> Sent:         Thursday, March 16, 2000 5:11
> Subject:      Re: ??: [TN] Gold Removal
>
> Enough. 30u Inches of Au IS NOT enough to embrittle solder joints. I've
> done
> it on space flight hardware for years in the 1980's and have performed
> every
> test, environmental screen and evaluation imaginable with no detriment and
> have satisfied NASA and the Air Force.  Satisfy your QA with an MRB,
> accept
> the boards, send a SCAR to the vendor, save your schedule and save your
> headache for something real. Next Topic.
>
> > ----------
> > From:         Paul Klasek[SMTP:[log in to unmask]]
> > Reply To:     TechNet E-Mail Forum.;Paul Klasek
> > Sent:         Wednesday, March 15, 2000 8:04 PM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] ??: [TN] Gold Removal
> >
> > Oh, gee, ehm, Ryan, mate, close, not sure if enough :
> > 1
> > Steve's maths ?(sorry Steve, you ARE one of the LEGENDS):
> > "nearly" 75u" = 1.875um (or close enough);
> > is NOT in line with ITRI's recommended 1.5um ceiling :
> > me the coward never had guts to digest even 1um on soldered pads .
> > I'll give you; with latest pad size trends (smaller); you may creep
> touch
> > higher,
> > but i do know if i'd got totally stoned and placed more than 1umAu on
> > specs,
> > my fellow in QA would be after my skin .
> > Besides, Tim 's been just quizzing me where the hell do i squeeze 0.5um
> > from
> > flush;
> > whining bitterly all he gets from his fabs is 0.25um tops on flash .
> > Record i MEASURED on flash was some 0.8um,
> > so i presume it's my turn in Tim's shoes :
> > Where would you get saturation's which throws 75u" on Ni ?
> > Presume only academic maths ?
> >
> > And the bible talks, i think (?) about 4% , not 3,
> > but i won't be making scenes about that one
> > (less is better, almost, hahaha)
> >
> > And NiAu (0.5umAu average = 20u") costs us less than HASL .
> >
> > Getting gold ears from all this off hip traffic ;
> > getting dark here too: Inge : deleted some dozen methaned messages today
> !
> >
> > All in good humor Ryan , ok ?, just let's retain the functionality.
> >
> >
> > Paul
> >
> > -----Original Message-----
> > From: Ryan Grant [mailto:[log in to unmask]]
> > Sent: Thursday, 16 March 2000 10:47
> > To: [log in to unmask]
> > Subject: Re: [TN] ??: [TN] Gold Removal
> >
> >
> > I agree with this.  Do the math.  If a five mil stencil is used, and the
> > component leads are NOT gold plated, the board gold thickness can reach
> > nearly 75 micro inches before the percentage of gold in the joint
> reaches
> > the magical number of 3%.  Below 3%, gold is not shown to induce
> > embrittlement.  If you are soldering to BGA balls, there is even more
> Tin
> > to
> > dilute the gold, so the gold thickness can be even thicker.  The reason
> > for
> > the 5 to 8 micro inches of gold thickness is, that is the MINIMUM needed
> > to
> > prevent oxidation of the nickel.  Thicker gold is more expensive in
> terms
> > of
> > processing and material cost, and it is unnecessary, so why do it?
> >
> > Of course, if I buy a new stereo, and it has a scratch on it, I'll take
> it
> > back.  Functionality be damned.  Rick can do the same with his boards.
> >
> > Ryan G.
> >
> > > -----Original Message-----
> > > From: Timothy Reeves [SMTP:[log in to unmask]]
> > > Sent: Wednesday, March 15, 2000 3:08 PM
> > > To:   [log in to unmask]
> > > Subject:      Re: [TN] ??: [TN] Gold Removal
> > >
> > > Does anyone agree with this? I hope not.
> > >
> > > > ----------
> > > > From:         Jonathan A Noquil
> > > > Sent:         Tuesday, March 14, 2000 15:57
> > > > Subject:      Re: ??: [TN] Gold Removal
> > > >
> > > > Higher gold thickness does not affect
> > > > reliability (solderability),
> > >
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Date:         Thu, 16 Mar 2000 13:54:48 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Paul Bitchel <[log in to unmask]>
Subject:      Disconnect form tech net
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Please disconnect me from tech net.
Thanks

http://www.apcc.com

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Date:         Thu, 16 Mar 2000 11:13:02 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              KK Chin <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         KK Chin <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Steve,

Dr. William Kenyon responded to my technet posting last year with the
demonstration method which was of great help to me. The passage is pasted below.
The article  was also posted in his column in the SMT magazine, April 99.

K.K. Chin
Artesyn Technologies
Fremont, CA

-----------------------------------------------------------------------------------------------
There is a simple EmR (electromigration resistance) test you can
do -- I put it in a recent (April) SMT column that I write each
month on cleaning issues.

Here it is, just copied and pasted from the last edit.
Fun with Dendrites-
Readers have expressed interest in the reliability concerns
caused by dendritic
growth, or cathode-anode filament formation.  Whatever the name,
it usually
results in catastrophic in-service failure of the PCB in service.
Since many PCB
fabricators are reluctant to make any process changes based on
the possibility
of an obscure failure mechanism, as long the bare and assembled
PCBs pass the
ionic cleanliness test, it seemed appropriate to provide a simple
demonstration
of the phenomenon that assemblers can use to get the attention of
their PCB
suppliers.
There Here is a simple, inexpensive test that anyone using
hot-air solder
leveled (HASL) or infrared fused PCBs can do. First, obtain a
scrap board that
has been through PCB supplierUs HASL process. Find two parallel
traces on the
PCB that are at least 5 cm long. Cut the traces at both ends to
isolate them
from the rest of the circuitry. Solder some 5 cm. wires to the
positive and
negative terminals of a standard 9 V battery, then attach
mini-alligator clips
to the ends of the wires. Using a sharp knife straight-edge
razor, peel up the
opposite ends of the cut traces, so you can attach the
mini-alligator clips to
the bent-up ends of the traces. (One could solder the battery
wires to the
traces with type-R rosin, but this could introduce doubt in the
results. The
clips or a connector if the design has wires going to a set of

Fax To:  Amanda OUBrien @ SMT
Magazine                            Page 4/5

connector fingers is better.)  Obtain some DI water. and a decent
10-30x
microscope.  If a microscope is not available, a powerful
magnifying glass can
be used. Put the isolated traces under the microscope and bring
them into focus.
Arrange the PCB to see both traces and the laminate gap between
them. Next, hook
the 9 V battery terminal wires to the opposite ends of the
isolated traces; so
one trace is positive and the other is negative. Now, very
carefully place a
drop of DI water on the isolated traces so it bridges the gap
between the traces
in the field of view of the microscope. See how long it takes for
the dendrites
to grow from cathode to anode, timing the progress with a stop
watch if desired.
Usually one sees the drop of water start to bubble a little, and
then a metallic
tree-like growth will cross the gap from cathode to anode.  The
resulting
metallic dendrites are quite brittle, which probably accounts for
the well-known
fix of banging a defective PCB on the table and having it spring
to life again.
What has happened is that all the dendrites (current leakage
paths) have been
shattered.  Will it happen again over time, especially with
exposure to elevated
humidity conditions? Absolutely. This test will make believers
out of those who
think all one has to do is pass the ionic cleanliness test and
that pure water
never hurts anything.  The problem with HASL or infrared fused
tin/lead plated
PCBs is  was typically the organic fluid that forms the basis of
the traditional
HASL or reflow fluids.  It only took takes a little on the
surface to give the
current leakage, resulting in the dendritic growth problem.  The
only pass/fail
value available that is based on test work is about 1
microgram/sq. cm per
0.001" of trace or pad separation.  So a 0.050S space can
tolerate 50 mg., while
a 0.010S space can tolerate 10 mg.  According to this source,
most PCBs will
have hundreds to thousands of mg./sq. cm of such fluid residues
on them.
Literature data are is available on the effects of various flux
residues and
cleaning methods on test PCBs that had such fluids on them or had
any traces of
these fluids removed prior to the soldering and cleaning tests.
Newer fluids
either eliminate or minimize this problem, but the test is so
easy to do on
scrap boards that it is good insurance prior to accepting a lot
of PCBs and
releasing them to production.

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Date:         Thu, 16 Mar 2000 11:05:05 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      Re: (non-tech) "Wurst, then Spam"
MIME-Version: 1.0
Content-Type: text/plain

Things are going downhill, one way or another
Tim Reeves
> ----------
> From:         Robert Welch
> Sent:         Thursday, March 16, 2000 8:22
> Subject:      Re: Worst than spam
>
> I second that
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phillip E. Hinton
> Sent: Thursday, March 16, 2000 10:28 AM
> To: [log in to unmask]
> Subject: [TN] Worst than spam
>
>
> Technetters
>
> I am finding that "Technet" is becoming a "good old boys club" where
> members
> sit around and tell jokes and trade insults.  When 1/2 of my technet
> message
> are not worth reading, I want to dump the whole thing.  Why do not those
> guys
> who like to "get away" from the tech forum form another forum where they
> can
> do their thing.
> I am suggesting that we use technet for what it was meant to do.
>
> Phil Hinton
>
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Date:         Thu, 16 Mar 2000 13:09:57 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              rampinc <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         rampinc <[log in to unmask]>
Organization: RAMPinc.
Subject:      Re:
X-To:         Bill Decray <[log in to unmask]>
MIME-Version: 1.0
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Bill,
What is your application of this connector? Assuming it is a card edge connector, how
many insertions are required, what is the connecor insertion force, what is the contact
geometry and are they using contact lube or not, tin ( white or any other shades) may
cause more problems. Also it is important to keep same plated finish ( Au-Au or Sn-Sn)
on both parts ie contact fingers and contact spring.

Please discuss off line if you need more details about contact reliability issues
involved.

Bill Decray wrote:

> CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> CONNECTOR FINGERS.
> MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE THEY
> ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
>
> William W. DeCray III
> Waytec Electronics Corp
> Sales Engineer
> PHONE:(804) 237-6391 ext 115
> FAX:    (804) 237-1324
> E-mail:<[log in to unmask]>
> Web <http://www.waytec.com>
> FTP <ftp://ftp.waytec.com>
>
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Date:         Thu, 16 Mar 2000 13:15:04 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              rampinc <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         rampinc <[log in to unmask]>
Organization: RAMPinc.
Subject:      Re: Electromigration demonstration...
X-To:         [log in to unmask]
MIME-Version: 1.0
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Hello Steve,

It is simple. On a PCB select an area where two conductors are running parallel to each
other. Connect a  power source through a rheostat. Apply some water drops so as to
cover two tracks. Tap water will be fine. Increase voltage slowly and you should see
migration growth ( depending conductivity of water which you can change by adding
common salt to water). Have fun.

"Stephen R. Gregory" wrote:

> How the heck are yew good ol' boys doin'?
>
> (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk with a
> mouthful of terbacky...(hitchin' my bib overalls up)
>
> Anyhoo, a while back, some good ol' boy posted a simple way to actually show
> electromigration (fancy word for us country boys ain't it) in progress...you
> could actually see it happening. Something about using an overhead projector
> and a 9-volt battery...or something like that.
>
> Does anybody remember that? I need some way to graphically show this
> phenomena  happening...('nuther fancy word huh?...phenomena...)
>
> YEEEE-HAW!!!
> (that's good ol' boy talk for thanks a lot!)
>
> -Steve "Jethro" Gregory- (GRIN)
>
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Date:         Thu, 16 Mar 2000 13:25:27 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              rampinc <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         rampinc <[log in to unmask]>
Organization: RAMPinc.
Subject:      Re: Worst than spam
X-To:         [log in to unmask]
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Thank Phillip.

You have pointed out a problem which is on the mind of many of us. An occasional smirk
aside, lately the forum has become a banter for few. It is OK if they e-mail their
beautiful uplifting philosophical thoughts to their friends only, rather than
broadcasting to the entire community. ( This is making  >90 % of the postings good for
the delete key).

Again thanks for bringing it to the front.



"Phillip E. Hinton" wrote:

> Technetters
>
> I am finding that "Technet" is becoming a "good old boys club" where members
> sit around and tell jokes and trade insults.  When 1/2 of my technet message
> are not worth reading, I want to dump the whole thing.  Why do not those guys
> who like to "get away" from the tech forum form another forum where they can
> do their thing.
> I am suggesting that we use technet for what it was meant to do.
>
> Phil Hinton
>
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Date:         Thu, 16 Mar 2000 11:16:23 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Kim <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Kim <[log in to unmask]>
Subject:      stain&gold plating
MIME-Version: 1.0
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              boundary="----_=_NextPart_001_01BF8F7C.20D8AFF0"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01BF8F7C.20D8AFF0
Content-Type: text/plain;
        charset="KS_C_5601-1987"

 I am looking for suggestions on "How to remove a stain on gold surface and
why does a stain happen on gold surface after plating?"
 In electroless Ni/immersion Au plating, I have found many stain problems
after plating. Threre are varied shapes of stains such as a spot, a line,
and an irregulare shpae.
 Anyone who can suggest a better idea?

 thank you!

------_=_NextPart_001_01BF8F7C.20D8AFF0
Content-Type: text/html;
        charset="KS_C_5601-1987"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3DKS_C_5601-1987">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2650.12">
<TITLE>stain&amp;gold plating</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>&nbsp;I am looking for suggestions on &quot;How to =
remove a stain on gold surface and why does a stain happen on gold =
surface after plating?&quot;</FONT></P>

<P><FONT SIZE=3D2>&nbsp;In electroless Ni/immersion Au plating, I have =
found many stain problems after plating. Threre are varied shapes of =
stains such as a spot, a line, and an irregulare shpae. </FONT></P>

<P><FONT SIZE=3D2>&nbsp;Anyone who can suggest a better idea?</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;thank you!</FONT>
</P>

</BODY>
</HTML>
------_=_NextPart_001_01BF8F7C.20D8AFF0--

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=========================================================================
Date:         Wed, 15 Mar 2000 19:09:08 -0000
Reply-To:     Michael Fenner <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Fenner <[log in to unmask]>
Organization: Bonding Services & Products
Subject:      Re: VOC legislation
X-To:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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The exact  opposite

Mike

----- Original Message -----
From: Ingemar Hernefjord (EMW) <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 15, 2000 11:18 AM
Subject: Re: [TN] VOC legislation


> However, THIS is a very severe question to you guys: all speak about the speed of light. And
all know what, even the man with the hanging tongue and Noble Prize. But nobody speak about the
speed of dark! So, what's speed of dark?
>

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Date:         Thu, 16 Mar 2000 13:44:44 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: stain&gold plating
X-To:         David Kim <[log in to unmask]>
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              boundary="----=_NextPart_000_001E_01BF8F4D.C9A43960"

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Content-Type: text/plain;
        charset="KS_C_5601-1987"
Content-Transfer-Encoding: quoted-printable

stain&gold platingDavid,

There is no doubt an endless list of what would cause stains on gold. =
The two most frequent in my experience are contaminates in the gold bath =
and poor final cleaning after plating.

Contaminates in the gold bath usually leave the gold slightly discolored =
and not matter how much you attempt to clean it the stain will never =
come off.

Stains due to poor final clean are easily removed with an IPA solution, =
one quick way to tell if the stain is on the gold surface, take an =
ordinary pencil eraser and try to remove the stain, if it comes off =
you'll probably have good results with a solution clean.

Have fun

Franklin D Asbell


----- Original Message -----=20
  From: David Kim=20
  To: [log in to unmask]
  Sent: Thursday, March 16, 2000 11:16 AM
  Subject: [TN] stain&gold plating


   I am looking for suggestions on "How to remove a stain on gold =
surface and why does a stain happen on gold surface after plating?"

   In electroless Ni/immersion Au plating, I have found many stain =
problems after plating. Threre are varied shapes of stains such as a =
spot, a line, and an irregulare shpae.=20

   Anyone who can suggest a better idea?=20

   thank you!=20


------=_NextPart_000_001E_01BF8F4D.C9A43960
Content-Type: text/html;
        charset="KS_C_5601-1987"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>stain&gold plating</TITLE>
<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>David,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>There is no doubt an endless list of =
what would=20
cause stains on gold. The two most frequent in my experience are =
contaminates in=20
the gold bath and poor final cleaning after plating.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Contaminates in the gold bath usually =
leave the=20
gold slightly discolored and not matter how much you attempt to clean it =
the=20
stain will never come off.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Stains due to poor final clean are =
easily removed=20
with an IPA solution, one quick way to tell if the stain is on the gold =
surface,=20
take an ordinary pencil eraser and try to remove the stain, if it comes =
off=20
you'll probably have good results with a solution clean.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Have fun</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin D Asbell</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>David =
Kim</A>=20
  </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, March 16, 2000 =
11:16=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] stain&amp;gold=20
plating</DIV>
  <DIV><BR></DIV>
  <P><FONT size=3D2>&nbsp;I am looking for suggestions on "How to remove =
a stain=20
  on gold surface and why does a stain happen on gold surface after=20
  plating?"</FONT></P>
  <P><FONT size=3D2>&nbsp;In electroless Ni/immersion Au plating, I have =
found=20
  many stain problems after plating. Threre are varied shapes of stains =
such as=20
  a spot, a line, and an irregulare shpae. </FONT></P>
  <P><FONT size=3D2>&nbsp;Anyone who can suggest a better idea?</FONT> =
</P>
  <P><FONT size=3D2>&nbsp;thank you!</FONT> =
</P></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_001E_01BF8F4D.C9A43960--

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Date:         Thu, 16 Mar 2000 13:05:23 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      Re: Electromigration demonstration...

Jethro,
        I have tried the method that KK Chin spoke of and had some trouble.
I didn't find it as easy as it sounded.

        First of all, not clearly mentioned is that the "easy" migration
will only occur with exposed metal.  So scrape off the solder masking where
ever you intend to place the drop of water.  Also, Gold doesn't migrate
easily, so make sure the board is a HASL (as mentioned by Dr William) or
OSP.  Second, the hydrolysising (is that a word?) water obscures being able
to see anything.  Third, I tried to measure the resistance between the
traces so I knew when I had a bridge.  I found the water would conduct (of
course), but conduction stopped when the water was completely evaporated.
Evaporating a drop of water doesn't take very long.  So I had to continually
add water.  Finally, in my impatience, I found that I had to place a tiny
drop of flux on the spot to get thing started.  (Maybe my boards may were
too clean to get quick results.)

        However, when every works, it works as advertised.  I found that I
could bridge pads or traces quite easily and quickly.  I just had to wait
for the foaming water to disappear and monitor the ammeter to verify
conduction still existed.

Da tater faarma in Idaho

> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Thursday, March 16, 2000 11:49 AM
> To:   [log in to unmask]
> Subject:      [TN] Electromigration demonstration...
>
> How the heck are yew good ol' boys doin'?
>
> (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk
> with a
> mouthful of terbacky...(hitchin' my bib overalls up)
>
> Anyhoo, a while back, some good ol' boy posted a simple way to actually
> show
> electromigration (fancy word for us country boys ain't it) in
> progress...you
> could actually see it happening. Something about using an overhead
> projector
> and a 9-volt battery...or something like that.
>
> Does anybody remember that? I need some way to graphically show this
> phenomena  happening...('nuther fancy word huh?...phenomena...)
>
> YEEEE-HAW!!!
> (that's good ol' boy talk for thanks a lot!)
>
> -Steve "Jethro" Gregory- (GRIN)
>
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Date:         Thu, 16 Mar 2000 15:06:02 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ed Holton <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

My first experience with dendretic growth involved a capacitor on a board
in a highly humid environment (automotive application).  We had dendretic
growth underneath the capacitor.  There were a few variables that helped
aggrevate the situation.   I did a simple experiment to show everyone what
was happening, but it also showed that even if your board was perfectly
clean, as long as there was water and voltage, you will get a dendretic
growth.

I hooked wires onto each end of a 1206 capacitor.  These wires were then
hooked to a 12v power supply (to simulate a car battery).  A drop of DI
water was placed ontop of the capacitor and the power supply turned on.
After a few moments, a dendrite jumped from one end of the capacitor to the
other.  It was pretty cool to watch.  This little experiment earned me the
nickname Mr. Wizard for the next few months.  We had the video camera from
our microscope system focused on the capacitor so everyone could watch it
on the monitor.  We did find in later repeat experiments that it was
sometimes necessary to add water, as it sometimes evaporated quickly due to
the conditions.  (I need to thank John Maxwell, he help me set the
experiment up originally)



Ed Holton
Manufacturing Engineer and Group Leader
Hella Electronics
Telephone (734) 414-0944
Fax (734) 414-0941



                    KK Chin
                    <KK.Chin@ARTE        To:     [log in to unmask]
                    SYN.COM>             cc:
                    Sent by:             Subject:     Re: [TN] Electromigration
                    TechNet              demonstration...
                    <[log in to unmask]
                    ORG>


                    03/16/00
                    02:13 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to KK
                    Chin





Steve,

Dr. William Kenyon responded to my technet posting last year with the
demonstration method which was of great help to me. The passage is pasted
below.
The article  was also posted in his column in the SMT magazine, April 99.

K.K. Chin
Artesyn Technologies
Fremont, CA

-----------------------------------------------------------------------------------------------

There is a simple EmR (electromigration resistance) test you can
do -- I put it in a recent (April) SMT column that I write each
month on cleaning issues.

Here it is, just copied and pasted from the last edit.
Fun with Dendrites-
Readers have expressed interest in the reliability concerns
caused by dendritic
growth, or cathode-anode filament formation.  Whatever the name,
it usually
results in catastrophic in-service failure of the PCB in service.
Since many PCB
fabricators are reluctant to make any process changes based on
the possibility
of an obscure failure mechanism, as long the bare and assembled
PCBs pass the
ionic cleanliness test, it seemed appropriate to provide a simple
demonstration
of the phenomenon that assemblers can use to get the attention of
their PCB
suppliers.
There Here is a simple, inexpensive test that anyone using
hot-air solder
leveled (HASL) or infrared fused PCBs can do. First, obtain a
scrap board that
has been through PCB supplierUs HASL process. Find two parallel
traces on the
PCB that are at least 5 cm long. Cut the traces at both ends to
isolate them
from the rest of the circuitry. Solder some 5 cm. wires to the
positive and
negative terminals of a standard 9 V battery, then attach
mini-alligator clips
to the ends of the wires. Using a sharp knife straight-edge
razor, peel up the
opposite ends of the cut traces, so you can attach the
mini-alligator clips to
the bent-up ends of the traces. (One could solder the battery
wires to the
traces with type-R rosin, but this could introduce doubt in the
results. The
clips or a connector if the design has wires going to a set of

Fax To:  Amanda OUBrien @ SMT
Magazine                            Page 4/5

connector fingers is better.)  Obtain some DI water. and a decent
10-30x
microscope.  If a microscope is not available, a powerful
magnifying glass can
be used. Put the isolated traces under the microscope and bring
them into focus.
Arrange the PCB to see both traces and the laminate gap between
them. Next, hook
the 9 V battery terminal wires to the opposite ends of the
isolated traces; so
one trace is positive and the other is negative. Now, very
carefully place a
drop of DI water on the isolated traces so it bridges the gap
between the traces
in the field of view of the microscope. See how long it takes for
the dendrites
to grow from cathode to anode, timing the progress with a stop
watch if desired.
Usually one sees the drop of water start to bubble a little, and
then a metallic
tree-like growth will cross the gap from cathode to anode.  The
resulting
metallic dendrites are quite brittle, which probably accounts for
the well-known
fix of banging a defective PCB on the table and having it spring
to life again.
What has happened is that all the dendrites (current leakage
paths) have been
shattered.  Will it happen again over time, especially with
exposure to elevated
humidity conditions? Absolutely. This test will make believers
out of those who
think all one has to do is pass the ionic cleanliness test and
that pure water
never hurts anything.  The problem with HASL or infrared fused
tin/lead plated
PCBs is  was typically the organic fluid that forms the basis of
the traditional
HASL or reflow fluids.  It only took takes a little on the
surface to give the
current leakage, resulting in the dendritic growth problem.  The
only pass/fail
value available that is based on test work is about 1
microgram/sq. cm per
0.001" of trace or pad separation.  So a 0.050S space can
tolerate 50 mg., while
a 0.010S space can tolerate 10 mg.  According to this source,
most PCBs will
have hundreds to thousands of mg./sq. cm of such fluid residues
on them.
Literature data are is available on the effects of various flux
residues and
cleaning methods on test PCBs that had such fluids on them or had
any traces of
these fluids removed prior to the soldering and cleaning tests.
Newer fluids
either eliminate or minimize this problem, but the test is so
easy to do on
scrap boards that it is good insurance prior to accepting a lot
of PCBs and
releasing them to production.

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=========================================================================
Date:         Thu, 16 Mar 2000 16:17:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Louis, Edwin @ CSE" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Louis, Edwin @ CSE" <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

You can not use Tin or Tin/Lead as a  contact material. In humidity and air
an oxide film grows which will continually raise the contact resistance over
time. ATT years ago did
a study of metals for physical contacts and found those two platings
unsuitable.
WE used some contact connectors on PWAs that had solder coated fingers. The
vendor claimed that a hermetic seal would form in the contact from the
connector pushing into the solder. We had all kinds of electrical problems.
The solder contact had to be perfectly flat and flat within a specified area
in order for the contact to maintain good conductivity and this was in an
air conditioned office environment. We had to do Ammonium Sulfide and Nitric
Acid vapor exposure tests to guarantee that we had a hermetic seal.

-----Original Message-----
From: Ed Holton [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 3:06 PM
To: [log in to unmask]
Subject: Re: [TN] Electromigration demonstration...


My first experience with dendretic growth involved a capacitor on a board
in a highly humid environment (automotive application).  We had dendretic
growth underneath the capacitor.  There were a few variables that helped
aggrevate the situation.   I did a simple experiment to show everyone what
was happening, but it also showed that even if your board was perfectly
clean, as long as there was water and voltage, you will get a dendretic
growth.

I hooked wires onto each end of a 1206 capacitor.  These wires were then
hooked to a 12v power supply (to simulate a car battery).  A drop of DI
water was placed ontop of the capacitor and the power supply turned on.
After a few moments, a dendrite jumped from one end of the capacitor to the
other.  It was pretty cool to watch.  This little experiment earned me the
nickname Mr. Wizard for the next few months.  We had the video camera from
our microscope system focused on the capacitor so everyone could watch it
on the monitor.  We did find in later repeat experiments that it was
sometimes necessary to add water, as it sometimes evaporated quickly due to
the conditions.  (I need to thank John Maxwell, he help me set the
experiment up originally)



Ed Holton
Manufacturing Engineer and Group Leader
Hella Electronics
Telephone (734) 414-0944
Fax (734) 414-0941



                    KK Chin
                    <KK.Chin@ARTE        To:     [log in to unmask]
                    SYN.COM>             cc:
                    Sent by:             Subject:     Re: [TN]
Electromigration
                    TechNet              demonstration...
                    <[log in to unmask]
                    ORG>


                    03/16/00
                    02:13 PM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to KK
                    Chin





Steve,

Dr. William Kenyon responded to my technet posting last year with the
demonstration method which was of great help to me. The passage is pasted
below.
The article  was also posted in his column in the SMT magazine, April 99.

K.K. Chin
Artesyn Technologies
Fremont, CA

----------------------------------------------------------------------------
-------------------

There is a simple EmR (electromigration resistance) test you can
do -- I put it in a recent (April) SMT column that I write each
month on cleaning issues.

Here it is, just copied and pasted from the last edit.
Fun with Dendrites-
Readers have expressed interest in the reliability concerns
caused by dendritic
growth, or cathode-anode filament formation.  Whatever the name,
it usually
results in catastrophic in-service failure of the PCB in service.
Since many PCB
fabricators are reluctant to make any process changes based on
the possibility
of an obscure failure mechanism, as long the bare and assembled
PCBs pass the
ionic cleanliness test, it seemed appropriate to provide a simple
demonstration
of the phenomenon that assemblers can use to get the attention of
their PCB
suppliers.
There Here is a simple, inexpensive test that anyone using
hot-air solder
leveled (HASL) or infrared fused PCBs can do. First, obtain a
scrap board that
has been through PCB supplierUs HASL process. Find two parallel
traces on the
PCB that are at least 5 cm long. Cut the traces at both ends to
isolate them
from the rest of the circuitry. Solder some 5 cm. wires to the
positive and
negative terminals of a standard 9 V battery, then attach
mini-alligator clips
to the ends of the wires. Using a sharp knife straight-edge
razor, peel up the
opposite ends of the cut traces, so you can attach the
mini-alligator clips to
the bent-up ends of the traces. (One could solder the battery
wires to the
traces with type-R rosin, but this could introduce doubt in the
results. The
clips or a connector if the design has wires going to a set of

Fax To:  Amanda OUBrien @ SMT
Magazine                            Page 4/5

connector fingers is better.)  Obtain some DI water. and a decent
10-30x
microscope.  If a microscope is not available, a powerful
magnifying glass can
be used. Put the isolated traces under the microscope and bring
them into focus.
Arrange the PCB to see both traces and the laminate gap between
them. Next, hook
the 9 V battery terminal wires to the opposite ends of the
isolated traces; so
one trace is positive and the other is negative. Now, very
carefully place a
drop of DI water on the isolated traces so it bridges the gap
between the traces
in the field of view of the microscope. See how long it takes for
the dendrites
to grow from cathode to anode, timing the progress with a stop
watch if desired.
Usually one sees the drop of water start to bubble a little, and
then a metallic
tree-like growth will cross the gap from cathode to anode.  The
resulting
metallic dendrites are quite brittle, which probably accounts for
the well-known
fix of banging a defective PCB on the table and having it spring
to life again.
What has happened is that all the dendrites (current leakage
paths) have been
shattered.  Will it happen again over time, especially with
exposure to elevated
humidity conditions? Absolutely. This test will make believers
out of those who
think all one has to do is pass the ionic cleanliness test and
that pure water
never hurts anything.  The problem with HASL or infrared fused
tin/lead plated
PCBs is  was typically the organic fluid that forms the basis of
the traditional
HASL or reflow fluids.  It only took takes a little on the
surface to give the
current leakage, resulting in the dendritic growth problem.  The
only pass/fail
value available that is based on test work is about 1
microgram/sq. cm per
0.001" of trace or pad separation.  So a 0.050S space can
tolerate 50 mg., while
a 0.010S space can tolerate 10 mg.  According to this source,
most PCBs will
have hundreds to thousands of mg./sq. cm of such fluid residues
on them.
Literature data are is available on the effects of various flux
residues and
cleaning methods on test PCBs that had such fluids on them or had
any traces of
these fluids removed prior to the soldering and cleaning tests.
Newer fluids
either eliminate or minimize this problem, but the test is so
easy to do on
scrap boards that it is good insurance prior to accepting a lot
of PCBs and
releasing them to production.

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=========================================================================
Date:         Fri, 17 Mar 2000 08:50:11 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: ??: [TN] Gold Removal
X-To:         "Misner, Bruce" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Oh' gosh , Bruce, you missed the point .
The subject (of this particular discussion) was 75u" (read it again) not 30.
Coming half cocked to sequence without following the TECHNICAL subject right
through the discussion gives subzero imput.
I objected to 75u" mentioned as too much ;
have no idea why you fire on 30, when that was resolved long time ago .
If you have OTHER opinion on 75u" ; i'll be glad to learn/hear/consider.
Just keep focus please, had enough of non tech as well .
Bit of spice is fine, no more please

paul

-----Original Message-----
From: Misner, Bruce [mailto:[log in to unmask]]
Sent: Friday, 17 March 2000 0:11
To: 'TechNet E-Mail Forum.'; 'Paul Klasek'
Subject: RE: [TN] ??: [TN] Gold Removal


Enough. 30u Inches of Au IS NOT enough to embrittle solder joints. I've done
it on space flight hardware for years in the 1980's and have performed every
test, environmental screen and evaluation imaginable with no detriment and
have satisfied NASA and the Air Force.  Satisfy your QA with an MRB, accept
the boards, send a SCAR to the vendor, save your schedule and save your
headache for something real. Next Topic.

> ----------
> From:         Paul Klasek[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Paul Klasek
> Sent:         Wednesday, March 15, 2000 8:04 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] ??: [TN] Gold Removal
>
> Oh, gee, ehm, Ryan, mate, close, not sure if enough :
> 1
> Steve's maths ?(sorry Steve, you ARE one of the LEGENDS):
> "nearly" 75u" = 1.875um (or close enough);
> is NOT in line with ITRI's recommended 1.5um ceiling :
> me the coward never had guts to digest even 1um on soldered pads .
> I'll give you; with latest pad size trends (smaller); you may creep touch
> higher,
> but i do know if i'd got totally stoned and placed more than 1umAu on
> specs,
> my fellow in QA would be after my skin .
> Besides, Tim 's been just quizzing me where the hell do i squeeze 0.5um
> from
> flush;
> whining bitterly all he gets from his fabs is 0.25um tops on flash .
> Record i MEASURED on flash was some 0.8um,
> so i presume it's my turn in Tim's shoes :
> Where would you get saturation's which throws 75u" on Ni ?
> Presume only academic maths ?
>
> And the bible talks, i think (?) about 4% , not 3,
> but i won't be making scenes about that one
> (less is better, almost, hahaha)
>
> And NiAu (0.5umAu average = 20u") costs us less than HASL .
>
> Getting gold ears from all this off hip traffic ;
> getting dark here too: Inge : deleted some dozen methaned messages today !
>
> All in good humor Ryan , ok ?, just let's retain the functionality.
>
>
> Paul
>
> -----Original Message-----
> From: Ryan Grant [mailto:[log in to unmask]]
> Sent: Thursday, 16 March 2000 10:47
> To: [log in to unmask]
> Subject: Re: [TN] ??: [TN] Gold Removal
>
>
> I agree with this.  Do the math.  If a five mil stencil is used, and the
> component leads are NOT gold plated, the board gold thickness can reach
> nearly 75 micro inches before the percentage of gold in the joint reaches
> the magical number of 3%.  Below 3%, gold is not shown to induce
> embrittlement.  If you are soldering to BGA balls, there is even more Tin
> to
> dilute the gold, so the gold thickness can be even thicker.  The reason
> for
> the 5 to 8 micro inches of gold thickness is, that is the MINIMUM needed
> to
> prevent oxidation of the nickel.  Thicker gold is more expensive in terms
> of
> processing and material cost, and it is unnecessary, so why do it?
>
> Of course, if I buy a new stereo, and it has a scratch on it, I'll take it
> back.  Functionality be damned.  Rick can do the same with his boards.
>
> Ryan G.
>
> > -----Original Message-----
> > From: Timothy Reeves [SMTP:[log in to unmask]]
> > Sent: Wednesday, March 15, 2000 3:08 PM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] ??: [TN] Gold Removal
> >
> > Does anyone agree with this? I hope not.
> >
> > > ----------
> > > From:         Jonathan A Noquil
> > > Sent:         Tuesday, March 14, 2000 15:57
> > > Subject:      Re: ??: [TN] Gold Removal
> > >
> > > Higher gold thickness does not affect
> > > reliability (solderability),
> >
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Date:         Thu, 16 Mar 2000 17:00:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ramsey, Guy" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ramsey, Guy" <[log in to unmask]>
Subject:      White Tin  instead of Gold for edge connectors
X-To:         rampinc <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Can we keep this discussion on the net. We are very interested in this issue
as well. In fact, Bill may be making these boards for us. The mating
connectors are gold in one case. In another the mating connector is tin over
nickel.

-----Original Message-----
From: rampinc [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 4:10 PM
Subject: <No subject given>


Bill,
What is your application of this connector? Assuming it is a card edge
connector, how
many insertions are required, what is the connecor insertion force, what is
the contact
geometry and are they using contact lube or not, tin ( white or any other
shades) may
cause more problems. Also it is important to keep same plated finish ( Au-Au
or Sn-Sn)
on both parts ie contact fingers and contact spring.

Please discuss off line if you need more details about contact reliability
issues
involved.

Bill Decray wrote:

> CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> CONNECTOR FINGERS.
> MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE THEY
> ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
>
> William W. DeCray III
> Waytec Electronics Corp
> Sales Engineer
> PHONE:(804) 237-6391 ext 115
> FAX:    (804) 237-1324
> E-mail:<[log in to unmask]>
> Web <http://www.waytec.com>
> FTP <ftp://ftp.waytec.com>
>
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=========================================================================
Date:         Fri, 17 Mar 2000 11:06:47 +1300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Justin Braime <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Justin Braime <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_012C_01BF9000.E2F7E5C0"

This is a multi-part message in MIME format.

------=_NextPart_000_012C_01BF9000.E2F7E5C0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Here's another question for you...
How do HASL, Gold, and Alpha levelled boards compare with regard to electromigration?

Thanks

Justin Braime
------------------------
Process Engineer
Compuspec Industries Ltd
Auckland, New Zealand
[log in to unmask]

------=_NextPart_000_012C_01BF9000.E2F7E5C0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2014.210" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Here's another question for you...</FONT></DIV>
<DIV><FONT size=3D2>How do HASL, Gold, and Alpha levelled boards compare =
with=20
regard to electromigration?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Thanks</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Justin Braime<BR>------------------------<BR>Process =

Engineer<BR>Compuspec Industries Ltd<BR>Auckland, New =
Zealand</FONT></DIV>
<DIV><FONT size=3D2><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></FONT></D=
IV></BODY></HTML>

------=_NextPart_000_012C_01BF9000.E2F7E5C0--

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Date:         Thu, 16 Mar 2000 16:20:30 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      White Tin  instead of Gold for edge connectors
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Bill,

In my opinion, the use of white tin (I'm assuming you're referring to a flat
solderable tin (no specific proprietary blend intended)) in place of gold on
tabs would offer the same properties except for oxide resistence. The tin is
going to oxide very rapidly, long before they will wear out from use. Now
the appearance of the oxide may not be an issue in and of itself; however,
once the oxide begins, electrical failures will follow.

I'm quite confident also, the gold you are currently using is more durable
then the tin finish options I know are available? Have no data to support
this, but I would guess the repeated insertions of tin would be far limited
then with gold.

Franklin D Asbell

----- Original Message -----
From: Ramsey, Guy <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 2:00 PM
Subject: [TN] White Tin instead of Gold for edge connectors


> Can we keep this discussion on the net. We are very interested in this
issue
> as well. In fact, Bill may be making these boards for us. The mating
> connectors are gold in one case. In another the mating connector is tin
over
> nickel.
>
> -----Original Message-----
> From: rampinc [mailto:[log in to unmask]]
> Sent: Thursday, March 16, 2000 4:10 PM
> Subject: <No subject given>
>
>
> Bill,
> What is your application of this connector? Assuming it is a card edge
> connector, how
> many insertions are required, what is the connecor insertion force, what
is
> the contact
> geometry and are they using contact lube or not, tin ( white or any other
> shades) may
> cause more problems. Also it is important to keep same plated finish
 Au-Au
> or Sn-Sn)
> on both parts ie contact fingers and contact spring.
>
> Please discuss off line if you need more details about contact reliability
> issues
> involved.
>
> Bill Decray wrote:
>
> > CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> > CONNECTOR FINGERS.
> > MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE
THEY
> > ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
> >
> > William W. DeCray III
> > Waytec Electronics Corp
> > Sales Engineer
> > PHONE:(804) 237-6391 ext 115
> > FAX:    (804) 237-1324
> > E-mail:<[log in to unmask]>
> > Web <http://www.waytec.com>
> > FTP <ftp://ftp.waytec.com>
> >
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Date:         Fri, 17 Mar 2000 09:37:38 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: stain&gold plating
X-To:         David Kim <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="KS_C_5601-1987"

Whatever you do , if any QA mgr will suggest you PENCIL ERASERS ; desist ,
go to archives ; we've had a discussion on this bad habit with Dave Hillman
not so long ago .

This is the case of cure worst than illness , address the process .

paul

-----Original Message-----
From: David Kim [mailto:[log in to unmask]]
Sent: Friday, 17 March 2000 6:16
To: [log in to unmask]
Subject: [TN] stain&gold plating



 I am looking for suggestions on "How to remove a stain on gold surface and
why does a stain happen on gold surface after plating?"

 In electroless Ni/immersion Au plating, I have found many stain problems
after plating. Threre are varied shapes of stains such as a spot, a line,
and an irregulare shpae.

 Anyone who can suggest a better idea?

 thank you!

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Date:         Thu, 16 Mar 2000 17:04:55 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: stain&gold plating
X-To:         Paul Klasek <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="KS_C_5601-1987"
Content-Transfer-Encoding: 7bit

Hey now, I only suggested the eraser as an indicator for the type of stain,
i.e. surface, plating contaminate, etc.

I wrote: "...take an ordinary pencil eraser and try to remove the stain, if
it comes off you'll probably have good results with a solution clean."

Notice I followed up with a solution clean.

This lowly Quality Assurance Manager knows a couple things now...

~grinning~

Franklin D Asbell

----- Original Message -----
From: Paul Klasek <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 2:37 PM
Subject: Re: [TN] stain&gold plating


> Whatever you do , if any QA mgr will suggest you PENCIL ERASERS ; desist ,
> go to archives ; we've had a discussion on this bad habit with Dave
Hillman
> not so long ago .
>
> This is the case of cure worst than illness , address the process .
>
> paul
>
> -----Original Message-----
> From: David Kim [mailto:[log in to unmask]]
> Sent: Friday, 17 March 2000 6:16
> To: [log in to unmask]
> Subject: [TN] stain&gold plating
>
>
>
>  I am looking for suggestions on "How to remove a stain on gold surface
and
> why does a stain happen on gold surface after plating?"
>
>  In electroless Ni/immersion Au plating, I have found many stain problems
> after plating. Threre are varied shapes of stains such as a spot, a line,
> and an irregulare shpae.
>
>  Anyone who can suggest a better idea?
>
>  thank you!
>
> ##############################################################
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Date:         Thu, 16 Mar 2000 17:57:16 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kang Zhang <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kang Zhang <[log in to unmask]>
Subject:      ESD issue with microblast conformal coating removal
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

Hi, all

Are there any literature, standard, industry guidelines/specifications done
on the
effects of rework and conformal coating removal on ESD?

Any information is appreciated.

Kang Zhang
Reliability Engineer
ELDEC Corporation

______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com

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Date:         Fri, 17 Mar 2000 00:54:28 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gabriela Bogdan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gabriela Bogdan <[log in to unmask]>
Subject:      Re: ASSY & FAB: vias: To plug or not to plug
X-To:         Ryan Grant <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi, TechNetters!
What plugging is recommended for vias near BGA pads on the BGA side?
Our PCB supplier does not use solder mask. The plugs are printed after hot air
levelling on both sides, with a much thicker material. Sometimes the plugs are very
high . Could it cause problems during solder paste printing?
One other question: How do you ensure that all the pads for BGA have good wetting? When
a SMD component solder joint must be reworked due to a problematic pad, you can see it.
When a solder ball is not connected due to the same problem, you are in big trouble.
How does your incoming inspection deal with this problem?
Thanks,
Gaby

Ryan Grant wrote:

> Hi Jeff,
>         The vias immediately adjacent to BGA pads should be plugged with
> solder mask.  Savvy board shop are smart enough to perform this operation
> last so no chemicals need to be washed off the bare board and out of the
> plugged vias.  Provided your SMT and Wave process does not introduce flux
> into the vias; the only "chemical" that might get trapped is the dirty water
> from the wash (for OA fluxes).
>
>         The via plugging near BGA pads on the BGA side really helps drive
> down the DPMO numbers for BGA soldering defects.  Rework will really prefer
> the plugged vias as well.  It is common for the solder mask web to come off
> during rework BGA pad prep.  The via plug helps hold down the webbing, and
> prevents solder robbing down vias, as well as ball to ball bridging.
>
>         However, in the end, you have to decide for yourself how much this
> extra effort is worth.
>
> Ryan G.
>
> > -----Original Message-----
> > From: Jeff Hempton [SMTP:[log in to unmask]]
> > Sent: Tuesday, March 14, 2000 8:28 AM
> > To:   [log in to unmask]
> > Subject:      [TN] ASSY & FAB: vias: To plug or not to plug
> >
> >      Hi Technetters,
> >        We are researching moving away from plugging our vias with solder
> >      mask (problems and reliability issues) and plugging with solder thru
> >      the wave solder process.
> >      I have read all of the archives, and printed a major novels worth
> >      (thanx for past info group, those archives are a wealth!!) bit one
> >      item is still missing I hope you can respond with info on:
> >
> >      ASSY: Do you have problems with, or design guidelines that address,
> >      the solder filled vias under components, or is this even an issue?
> >
> >      FAB: How do most of your customers address this?
> >
> >      Please, deluge me with your wisdoms, responses and help on this
> > issue.
> >      Thanx in advance group.
> >
> >      Jeff Hempton, Sr. SMD Mfg. Engineer
> >      United Technology Electronic Controls
> >      e-mail:   [log in to unmask]
> >
> > ##############################################################
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Date:         Fri, 17 Mar 2000 10:38:10 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: White Tin  instead of Gold for edge connectors
X-To:         Franklin Asbell <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Concur fully this time Franklin ; this is a rock bottom cheap way .
Have a data on tin and silver (yes, alpha, Justin), versus hasl, or gold,
on resistivities and counts of connections till getting through to copper;
or sliding on oxide ;
would not fax the papers however ; sorry .
That much for tin or silver connectivity (cheap, not recommended even for
1year life designs);
that much said ; still, assembled oak switches with coin silver clips;
where the sheer pressure kept contacts clean ; not same application as
fingers ;
just shows how important is specific application validation .
Touch/slide/rotary/ and other factors change the results in extremes ;

on electromigration the Q is much more complex because of the whiskers
inhibitive alloys;
however on intrinsically safe finishes I'd not compare hasl & gold with
(practically that is , minus palladium and other exotics) with much else .
As the latest round of simulation recommendations indicate ;
specific alloy validations can be easily done
(and are always infinitely better focused than not in house research, fast
too).

pk

-----Original Message-----
From: Franklin Asbell [mailto:[log in to unmask]]
Sent: Friday, 17 March 2000 11:21
To: [log in to unmask]
Subject: [TN] White Tin instead of Gold for edge connectors


Bill,

In my opinion, the use of white tin (I'm assuming you're referring to a flat
solderable tin (no specific proprietary blend intended)) in place of gold on
tabs would offer the same properties except for oxide resistence. The tin is
going to oxide very rapidly, long before they will wear out from use. Now
the appearance of the oxide may not be an issue in and of itself; however,
once the oxide begins, electrical failures will follow.

I'm quite confident also, the gold you are currently using is more durable
then the tin finish options I know are available? Have no data to support
this, but I would guess the repeated insertions of tin would be far limited
then with gold.

Franklin D Asbell

----- Original Message -----
From: Ramsey, Guy <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 2:00 PM
Subject: [TN] White Tin instead of Gold for edge connectors


> Can we keep this discussion on the net. We are very interested in this
issue
> as well. In fact, Bill may be making these boards for us. The mating
> connectors are gold in one case. In another the mating connector is tin
over
> nickel.
>
> -----Original Message-----
> From: rampinc [mailto:[log in to unmask]]
> Sent: Thursday, March 16, 2000 4:10 PM
> Subject: <No subject given>
>
>
> Bill,
> What is your application of this connector? Assuming it is a card edge
> connector, how
> many insertions are required, what is the connecor insertion force, what
is
> the contact
> geometry and are they using contact lube or not, tin ( white or any other
> shades) may
> cause more problems. Also it is important to keep same plated finish
 Au-Au
> or Sn-Sn)
> on both parts ie contact fingers and contact spring.
>
> Please discuss off line if you need more details about contact reliability
> issues
> involved.
>
> Bill Decray wrote:
>
> > CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> > CONNECTOR FINGERS.
> > MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE
THEY
> > ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
> >
> > William W. DeCray III
> > Waytec Electronics Corp
> > Sales Engineer
> > PHONE:(804) 237-6391 ext 115
> > FAX:    (804) 237-1324
> > E-mail:<[log in to unmask]>
> > Web <http://www.waytec.com>
> > FTP <ftp://ftp.waytec.com>
> >
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Date:         Fri, 17 Mar 2000 07:52:29 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jonathan A Noquil <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jonathan A Noquil <[log in to unmask]>
Subject:      Re: stain&gold plating
Mime-Version: 1.0
Content-type: multipart/mixed;
              Boundary="0__=QtNyJKmKjVZVgbWOMrGvv26KVxjCw95hbczZRGq4IkGKSB3QBVQHgI5k"

--0__=QtNyJKmKjVZVgbWOMrGvv26KVxjCw95hbczZRGq4IkGKSB3QBVQHgI5k
Content-type: text/plain; charset=us-ascii
Content-Disposition: inline



Hello David,
     Stain may come from your copper surface condition. If you have a bad
pre-cleaning (Acid clean, soft-etching), it will appear a bad surface after
Electroless/immersion plating. Please try to check your pre-cleaning condition.
Another thing is that if your Electroless Ni rapidly oxidize due to long time
dipping @ water rinse, this you may add an acid rinse after Electroless Ni.

I hope this may help you

Jonathan A. Noquil
R&D
Fairchild semiconductor
Cebu, Phils





David Kim <[log in to unmask]> on 03/17/2000 03:16:23 AM

Please respond to "\"TechNet E-Mail Forum.\" <[log in to unmask]>,        David
      Kim" <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Jonathan A Noquil/Cebu/Fairchild)
Subject:  [TN] stain&gold plating




 I am looking for suggestions on "How to remove a stain on gold surface and
why does a stain happen on gold surface after plating?"
 In electroless Ni/immersion Au plating, I have found many stain problems
after plating. Threre are varied shapes of stains such as a spot, a line,
and an irregulare shpae.
 Anyone who can suggest a better idea?

 thank you!


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Date:         Fri, 17 Mar 2000 10:30:57 +1030
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Dutton <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Dutton <[log in to unmask]>
Subject:      Re: ASSY & FAB: vias: To plug or not to plug
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Content-Type: text/plain; charset="us-ascii"; format=flowed

Hello TechNet gurus,

The discussion on whether to plug or not has been going on for a long time.
There appears to be many things to consider.
We've been recently having poor yields with 19x19 BGAs (1mm pitch) and are
trying to find the reason for this.
We have partially tented vias under the BGAs.(soldermask over the via pads,
but only up to the holes, leaving the holes open).
Via size is 26/12 and 24/12
Pads have been gold plated, but I'm not sure if the gold is heavy enough to
produce soldering problems.
Could we be having CTE mismatch problems, as we are using regular FR4
materials?

A summary of information that I have found, mainly on technet is as follows;

LPI soldermask does not tent well, and cannot be relied upon to adequately
fill a via.
Tenting both sides can result in soldermask voids within the vias, that can
outgas during reflow.
Tenting the top only, still allows wave solder to travel up the via, so
possibly partially reflowing the solder balls, as with open vias.
Tenting bottom only, will stop the wave solder travelling, but we have a
contaminant trapping void on the top side that can outgas again.

 From what I can gather, possible solutions are;

1. To epoxy plug the vias. - Is this a common practice?
2. Make use of blind vias, even micro vias  May be worth investigating the
cost penalty for this. Especially compared to low PWA yields.
         Are we kidding ourselves, thinking that we can use fine pitch BGAs
and uBGAs without going to this technology?
3. Something that I've only heard about, and may be a bit exotic, is to
epoxy plug the vias and overplate copper (with this we can have vias in pad)
         Is this process a reality, or theoretical and perhaps impractical?
4. Avoid wave soldering (I understand that this may be unavoidable due to
thru-hole comps)
5. If there is a choice between BGA and say, PGA, it would be better to use
the PGA device unless absolutely necessary.
         Although BGA use will only increase, and we should learn to work
with the technology.

Any discussion, real experiences, ideas, and general enlightenment would be
appreciated.
Good forum, (even if occasionally off the rails. Green rectangles can get
stale)

Many thanks,

Phil.





Phil Dutton C.I.D.
Senior CAD Technician
IPC Certified Interconnect Designer

Vision Abell Pty Ltd
Second Avenue, Technology Park,
Mawson Lakes.  SOUTH AUSTRALIA  5095
================================
Phone : (08) 8300 4400 (reception)
Fax :           (08) 8349 7420
email:          [log in to unmask]
Internet Page:  http://www.vsl.com.au
================================

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Date:         Thu, 16 Mar 2000 17:43:32 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Shean Dalton <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Shean Dalton <[log in to unmask]>
Subject:      Re: (non-tech) "Wurst, then Spam"
Mime-Version: 1.0
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"I agree" - says Dilbert




 (Embedded
 image moved   Timothy Reeves <[log in to unmask]>
 to file:      03/16/2000 01:05 PM
 pic23326.pcx)




To:   [log in to unmask]
cc:    (bcc: Shean Dalton/ElectrovertUS/Cookson)
Subject:  Re: [TN] (non-tech) "Wurst, then Spam"




Things are going downhill, one way or another
Tim Reeves
> ----------
> From:         Robert Welch
> Sent:         Thursday, March 16, 2000 8:22
> Subject:      Re: Worst than spam
>
> I second that
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phillip E. Hinton
> Sent: Thursday, March 16, 2000 10:28 AM
> To: [log in to unmask]
> Subject: [TN] Worst than spam
>
>
> Technetters
>
> I am finding that "Technet" is becoming a "good old boys club" where
> members
> sit around and tell jokes and trade insults.  When 1/2 of my technet
> message
> are not worth reading, I want to dump the whole thing.  Why do not those
> guys
> who like to "get away" from the tech forum form another forum where they
> can
> do their thing.
> I am suggesting that we use technet for what it was meant to do.
>
> Phil Hinton
>
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Date:         Thu, 16 Mar 2000 19:03:14 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Karen Tellefsen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Karen Tellefsen <[log in to unmask]>
Subject:      Re: IPC subcommittee --- help!
MIME-Version: 1.0
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Absolutely true!  We task group chairmen (chair-people, char women)
are always looking for fresh meat, er, people interested in the task
group's activities.  Email IPC to get the email address of the
appropriate task group chairman.  Attend the IPC meeting at PC
Expo if this is possible.  Jack Crawford monitors this group (I think),
he'd be glad to point you in the right direction.

----------
> From: Timothy Reeves <[log in to unmask]>
> To: [log in to unmask]
> Subject: Re: [TN] IPC subcommittee --- help!
> Date: Wednesday, March 15, 2000 5:38 PM
>
> I think if you just show up at the IPC meeting and go to the task group
> meeting and express interest, you'll probably get drafted!
> Correct me if I'm wrong.
> Tim Reeves
>
> > ----------
> > From:         Ed Cosper
> > Sent:         Wednesday, March 15, 2000 10:56
> > Subject:      IPC subcommittee --- help!
> >
> > Hi all,
> >
> > I'm sure someone out there in technet land can help. I have a front end
> > engineering manager that I would like to see become involved in the IPC
> > controlled impedance task group.  How does she get signed up for this.
> > All
> > help is appreciated.
> >
> > Ed Cosper
> > American Board Companies
> >
>
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Date:         Thu, 16 Mar 2000 19:25:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Worst than Spam
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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been reading technet for the last 4 years - and i am sure - as most of us do
- what interests me - i absorb - what doesn't i delete. I also try to
remember that - the technet has about 1700 odd subscribers - this tells me it
takes every kind of people to make a world......diversity.... ain't it great!!

Rick Fudalewski

Florida CirTech

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Date:         Thu, 16 Mar 2000 16:45:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Darrel Therriault <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Darrel Therriault <[log in to unmask]>
Subject:      Re: ASSY & FAB: vias: To plug or not to plug
In-Reply-To:  <4.2.0.58.20000317095602.00c1a030@imaphost>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Phil,

We have gone through several of the exercises you mention for probably the
same reasons.  We ended up not tenting any vias due to outgas and fluid
entrapment problems, and under BGAs we also found having mask as close to
the hole as possible was preferred.

One item that made the most difference for 1.0 mm BGAs was Hi TG FR4 (170C).
So far this has greatly reduced the solder errors for BGAs and fine pitch QFPs.
We don't design any boards that have either of those components without
hi TG FR4.  It seems to be much better that way.

Good Luck........DT




At 10:30 AM 3/17/00 +1030, Phil Dutton wrote:
>Hello TechNet gurus,
>
>The discussion on whether to plug or not has been going on for a long time.
>There appears to be many things to consider.
>We've been recently having poor yields with 19x19 BGAs (1mm pitch) and are
>trying to find the reason for this.
>We have partially tented vias under the BGAs.(soldermask over the via pads,
>but only up to the holes, leaving the holes open).
>Via size is 26/12 and 24/12
>Pads have been gold plated, but I'm not sure if the gold is heavy enough to
>produce soldering problems.
>Could we be having CTE mismatch problems, as we are using regular FR4
>materials?
>
>A summary of information that I have found, mainly on technet is as follows;
>
>LPI soldermask does not tent well, and cannot be relied upon to adequately
>fill a via.
>Tenting both sides can result in soldermask voids within the vias, that can
>outgas during reflow.
>Tenting the top only, still allows wave solder to travel up the via, so
>possibly partially reflowing the solder balls, as with open vias.
>Tenting bottom only, will stop the wave solder travelling, but we have a
>contaminant trapping void on the top side that can outgas again.
>
> From what I can gather, possible solutions are;
>
>1. To epoxy plug the vias. - Is this a common practice?
>2. Make use of blind vias, even micro vias  May be worth investigating the
>cost penalty for this. Especially compared to low PWA yields.
>         Are we kidding ourselves, thinking that we can use fine pitch BGAs
>and uBGAs without going to this technology?
>3. Something that I've only heard about, and may be a bit exotic, is to
>epoxy plug the vias and overplate copper (with this we can have vias in pad)
>         Is this process a reality, or theoretical and perhaps impractical?
>4. Avoid wave soldering (I understand that this may be unavoidable due to
>thru-hole comps)
>5. If there is a choice between BGA and say, PGA, it would be better to use
>the PGA device unless absolutely necessary.
>         Although BGA use will only increase, and we should learn to work
>with the technology.
>
>Any discussion, real experiences, ideas, and general enlightenment would be
>appreciated.
>Good forum, (even if occasionally off the rails. Green rectangles can get
>stale)
>
>Many thanks,
>
>Phil.
>
>
>
>
>
>Phil Dutton C.I.D.
>Senior CAD Technician
>IPC Certified Interconnect Designer
>
>Vision Abell Pty Ltd
>Second Avenue, Technology Park,
>Mawson Lakes.  SOUTH AUSTRALIA  5095
>================================
>Phone : (08) 8300 4400 (reception)
>Fax :           (08) 8349 7420
>email:          [log in to unmask]
>Internet Page:  http://www.vsl.com.au
>================================
>
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Date:         Thu, 16 Mar 2000 17:25:41 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Patel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Patel <[log in to unmask]>
Subject:      v-scoring with perimeter copper on topside
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Guys,
We are designing a very small board (.5" x 2") on an array. We think, we can
put it on an array with V-score for separation. Individual board has
perimeter copper on topside. It's a double sided board.  There is no
component in the vicinity of perimeter copper.

Knowing this, can I still go for v-score Or for V-grove, there should not be
copper in the cutting area ?

re,
ken patel

______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Thu, 16 Mar 2000 20:51:54 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      No technical content...just humble thanks.
MIME-Version: 1.0
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Hey ya'll...

I just wanna say thanks...and I really mean it. I've been on this list
for...let's see....
hmmmm....I think I made my first post back in 1995...somewhere around then
anyway...

The one thing I want to say, is that this list is made up of people (wow,
Steve! Great observation!...DUH?) I think the occasional diversional thread
(as long as it's not hostile) doesn't hurt...I actually learned something new
with all the posts about the theory of light, how farts aren't really
depleting the ozone, and whatnot...does that have anything to do with printed
circuit assembly? 'Course not...but I did learn something....isn't that what
life is all about? Knowledge? (Besides, the banter brought a smile to my
face...that ain't so bad is it? I think we all need to smile more)

This ain't no reference service that all of us pay for...so let's lighten-up
and understand that what this really is, is a group of human beings that are
simply communicating with each other. Sure we are all part of this deal
because as one facet of what we are, shares a common theme...but to make a
rule to strictly limit our communications, and not allow the human side of us
to come out once inna while, well...well, is just plain boring.

We are not cyborgs..

-Steve Gregory-

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Date:         Fri, 17 Mar 2000 15:06:32 +1300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Justin Braime <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Justin Braime <[log in to unmask]>
Subject:      Re: No technical content...just humble thanks.
X-To:         [log in to unmask]
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Well said Steve!

----- Original Message -----
From: Stephen R. Gregory
To: [log in to unmask]
Sent: Friday, March 17, 2000 2:51 PM
Subject: [TN] No technical content...just humble thanks.


Hey ya'll...

I just wanna say thanks...and I really mean it. I've been on this list
for...let's see....
hmmmm....I think I made my first post back in 1995...somewhere around then
anyway...

The one thing I want to say, is that this list is made up of people (wow,
Steve! Great observation!...DUH?) I think the occasional diversional thread
(as long as it's not hostile) doesn't hurt...I actually learned something new
with all the posts about the theory of light, how farts aren't really
depleting the ozone, and whatnot...does that have anything to do with printed
circuit assembly? 'Course not...but I did learn something....isn't that what
life is all about? Knowledge? (Besides, the banter brought a smile to my
face...that ain't so bad is it? I think we all need to smile more)

This ain't no reference service that all of us pay for...so let's lighten-up
and understand that what this really is, is a group of human beings that are
simply communicating with each other. Sure we are all part of this deal
because as one facet of what we are, shares a common theme...but to make a
rule to strictly limit our communications, and not allow the human side of us
to come out once inna while, well...well, is just plain boring.

We are not cyborgs..

-Steve Gregory-



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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2014.210" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Well said Steve!</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV style=3D"FONT: 10pt arial">----- Original Message -----=20
<DIV style=3D"BACKGROUND: #e4e4e4; font-color: black"><B>From:</B> <A=20
href=3D"mailto:[log in to unmask]" [log in to unmask]>Stephen R. =
Gregory</A>=20
</DIV>
<DIV><B>To:</B> <A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV><B>Sent:</B> Friday, March 17, 2000 2:51 PM</DIV>
<DIV><B>Subject:</B> [TN] No technical content...just humble =
thanks.</DIV></DIV>
<DIV><BR></DIV>Hey ya'll...<BR><BR>I just wanna say thanks...and I =
really mean=20
it. I've been on this list<BR>for...let's see....<BR>hmmmm....I think I =
made my=20
first post back in 1995...somewhere around then<BR>anyway...<BR><BR>The =
one=20
thing I want to say, is that this list is made up of people =
(wow,<BR>Steve!=20
Great observation!...DUH?) I think the occasional diversional =
thread<BR>(as long=20
as it's not hostile) doesn't hurt...I actually learned something =
new<BR>with all=20
the posts about the theory of light, how farts aren't =
really<BR>depleting the=20
ozone, and whatnot...does that have anything to do with =
printed<BR>circuit=20
assembly? 'Course not...but I did learn something....isn't that =
what<BR>life is=20
all about? Knowledge? (Besides, the banter brought a smile to =
my<BR>face...that=20
ain't so bad is it? I think we all need to smile more)<BR><BR>This ain't =
no=20
reference service that all of us pay for...so let's lighten-up<BR>and =
understand=20
that what this really is, is a group of human beings that are<BR>simply=20
communicating with each other. Sure we are all part of this =
deal<BR>because as=20
one facet of what we are, shares a common theme...but to make a<BR>rule =
to=20
strictly limit our communications, and not allow the human side of =
us<BR>to come=20
out once inna while, well...well, is just plain boring.<BR><BR>We are =
not=20
cyborgs..<BR><BR>-Steve Gregory-<BR><BR></BODY></HTML>

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Date:         Thu, 16 Mar 2000 23:01:26 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      (1) [TN] while you're on the subject of GOLD...
X-To:         [log in to unmask]
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In a message dated 3/16/00 1:21:32, [log in to unmask] writes:
>While you're on the subject of gold, when soldering to gold plated tracks,
does the
>presence of the gold make a difference to the soldering temperature?

Hi Richard,
The answer is no; the Au layer, if thick enough, will protect the underlying
Ni from oxidation. It also will promote a faster spreading, not wetting, of
the liquid solder on the Ni surface because of its very fast disolution rate
in Sn. But you still need to wet to Ni, that is disolve some Ni into Sn to
form a metalurgical bond, and that takes lots more thermal energy than
wetting to Cu.

Werner Engelmaier

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Date:         Thu, 16 Mar 2000 23:01:30 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      (2) [TN] while you're on the subject of GOLD...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Ron,
First, I hope to get onto the golf course tomorrow if I get home from APEX.
Second, when you combine different metals, the Liquidus, that is the
temperature above which the whole mixture is liquidous, as well as
theSolidus, that is the temperature below which the whole mixture is solid,
can either go up or down depending on the metals and their percentages.
That is part of the problem in the search for a suitable 'lead-free'
solder--not that I think we need 'lead-free'--since all the options are
environmentally less friendly than Pb.
Werner Engelmaier

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Date:         Mon, 13 Mar 2000 10:26:12 +0100
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Christof Goeke <[log in to unmask]>
Subject:      soldering of receptacles in pcb
MIME-Version: 1.0
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Hi Technetters,

i want to solder receptacles (diameter 2,0mm) in a pcb. my problem is i need
3 rows in a center of 2,54mm like this:

o o o
o o o
o o o
How can i solder the receptacle in the middle?
my idea is to manufacture a pcb with a solder ring around the drilling hole
for the receptacle. So if i put the receptacles in the pcb i only have to
heat the pcb with a hot-air blower and my receptacles have a save electrical
connection with the pcb.
Is this possible? Has anyone experience with something like that?

thanks,
Christof



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<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
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<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">



<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>Hi=20
Technetters,</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>i want=20
to solder receptacles (diameter 2,0mm) in a pcb. my problem is i need 3 =
rows in=20
a center of 2,54mm like this:</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>o o=20
o</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN><SPAN class=3D579110009-13032000><FONT =
color=3D#000000=20
face=3DArial size=3D2>o o o</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN><SPAN class=3D579110009-13032000><FONT =
color=3D#000000=20
face=3DArial size=3D2>o o o</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>How=20
can i solder the receptacle in the middle? </FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>my=20
idea is to manufacture a pcb with a solder ring around the drilling hole =
for the=20
receptacle. So if i put the receptacles in the pcb i only have to heat =
the pcb=20
with a hot-air blower and my receptacles have a save electrical =
connection with=20
the pcb.</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =
size=3D2>Is=20
this possible? Has anyone experience with something like=20
that?</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2>thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=3D579110009-13032000><FONT color=3D#000000 face=3DArial =

size=3D2></FONT></SPAN><SPAN class=3D579110009-13032000><FONT =
color=3D#000000=20
face=3DArial size=3D2>Christof</FONT></SPAN></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2><FONT face=3D"Swis721 BT" size=3D4><FONT size=3D2>
<DIV></DIV></FONT></FONT></FONT></DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

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Date:         Fri, 17 Mar 2000 10:09:21 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         [log in to unmask]
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Steve

The original dendrite wizard was Charles Jennings (if my memory is good) in some US
Govt lab (Sandia???) in the 1970s. He actually made a 16 mm film of it happening (I
have a PAL video copy of it). He said that dendrite formation could be thus provoked on
any substrate between any metals, but the rate and form was very variable for a given
ionic contamination level.

I recommend you put a 10 - 47 kilohm R in series with your battery: it will reduce the
gas formation and keep the dendrites intact longer, because the current is smaller.

BTW, this is not electromigration, it is electrochemical migration, two different
things. The latter is ionic in nature.

Brian

"Stephen R. Gregory" wrote:

> How the heck are yew good ol' boys doin'?
>
> (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk with a
> mouthful of terbacky...(hitchin' my bib overalls up)
>
> Anyhoo, a while back, some good ol' boy posted a simple way to actually show
> electromigration (fancy word for us country boys ain't it) in progress...you
> could actually see it happening. Something about using an overhead projector
> and a 9-volt battery...or something like that.
>
> Does anybody remember that? I need some way to graphically show this
> phenomena  happening...('nuther fancy word huh?...phenomena...)
>
> YEEEE-HAW!!!
> (that's good ol' boy talk for thanks a lot!)
>
> -Steve "Jethro" Gregory- (GRIN)
>
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Date:         Fri, 17 Mar 2000 08:58:18 +0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Clive ffitch <[log in to unmask]>
Subject:      Test - please ignore
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Date:         Fri, 17 Mar 2000 10:57:56 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Tantalum capacitors
MIME-Version: 1.0
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Hi, first I must say I'm glad that humour still exist among you. When we stop kidding (not insulting) and laughing, the situation is most severe. The world around you today is sad, very sad. And humour (call it bla-bla, as some do...) is a divine gift. Sometimes I feel for slamming my door and leave, so much to do, comrades that die before 40 as a result of this insane econo-technocratic hyperactive world running into the wall,  but it happens that someone crosses my way at those occasions (e.g. TechNet) and tell something that is like sun shining through the clouds. So, please, go on mixing in some pleasure in the techno speaking. Like vitamins, but working in seconds...

Now, about tantalum caps. Anyone out there using tantals with FLEXIBLE terminals? Old model, you recognize that, is with a more or less straight and painted body, terminals silvered, tinned or gold plated, most models for soldering. New since a number of years are those with rectangular body, suitable for P-P, and with sort of flexible ribbon terminal that is bent 90 degrees under the body. Those having these are e.g. Kemet, Sprague, Matsuo, Tekelec, Siemens, NEC, AVX/Kyocera to mention some.  OK, they are all excellent for soldering, but for silver epoxy mounting a minor problem occurs: the epoxy wets, not only the terminal but also the body. Then you loose some of the advantage with flexibility. You find a typical outline in IPC-SM-782 Subsection 8.4.

Question: anyone that pick-and-place such creatures for silverepoxy technology? What terminal finish do you order? And do you utilize the flexibel terminal?  How do you get a recommende epoxy line (50-100um) as the component is heavy, do you use some kind of standoff? Anyone that has centrifuged up to 5,000 G's? Anyone with experience from mounting such caps on Arlene/Roger/Taconic with heavymetal backing?

Normal FR4 indoor products with this cap are normally soldered and there are no obstacles. So, we don't have a general problem, but lack some experience for epoxying in special applications.

Also will come back later with discussion about ceramic caps, ferro/piezo effects, aging and such things that has been up recently. Ousten, France, are you out there? Still working with the  RFceramic characterization project? Lost your e-mail adress.

Ingemar Hernefjord
Ericsson Microwave Systems

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Date:         Fri, 17 Mar 2000 10:49:34 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brunker Ed <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brunker Ed <[log in to unmask]>
Subject:      Micro BGAs
MIME-Version: 1.0
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Hi,
Anyone using normal through vias for micro BGAs, 0.8mm pitch???
Regards
Edward Brunker
Principal Process Engineer

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Date:         Fri, 17 Mar 2000 08:15:30 -0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Smith, William (SAO)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Smith, William (SAO)" <[log in to unmask]>
Subject:      Re: (non-tech) "Wurst, then Spam"
X-To:         Shean Dalton <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Should not the subject be "Wurst OR Spam? I don't think that the two really
go that well together....

-----Original Message-----
From: Shean Dalton [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 8:44 PM
To: [log in to unmask]
Subject: Re: [TN] (non-tech) "Wurst, then Spam"






"I agree" - says Dilbert




 (Embedded
 image moved   Timothy Reeves <[log in to unmask]>
 to file:      03/16/2000 01:05 PM
 pic23326.pcx)




To:   [log in to unmask]
cc:    (bcc: Shean Dalton/ElectrovertUS/Cookson)
Subject:  Re: [TN] (non-tech) "Wurst, then Spam"




Things are going downhill, one way or another
Tim Reeves
> ----------
> From:         Robert Welch
> Sent:         Thursday, March 16, 2000 8:22
> Subject:      Re: Worst than spam
>
> I second that
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phillip E. Hinton
> Sent: Thursday, March 16, 2000 10:28 AM
> To: [log in to unmask]
> Subject: [TN] Worst than spam
>
>
> Technetters
>
> I am finding that "Technet" is becoming a "good old boys club" where
> members
> sit around and tell jokes and trade insults.  When 1/2 of my technet
> message
> are not worth reading, I want to dump the whole thing.  Why do not those
> guys
> who like to "get away" from the tech forum form another forum where they
> can
> do their thing.
> I am suggesting that we use technet for what it was meant to do.
>
> Phil Hinton
>
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Date:         Fri, 17 Mar 2000 06:54:11 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dennis Ward <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dennis Ward <[log in to unmask]>
Subject:      One side vs Both side
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Good morning everyone,

Question for all you manufacturing gurus. Is there a
significant advantage, cost wise, to keeping all the components
on the top side of the board versus placing components
on both sides?

Now I do know that they are some NRE cost, but is it
significant? In the past I was taught you should try to
keep every thing on top. But it seems that high density
double side boards are very common. There doesn't
seem to be as much emphasize on consolidating all
the components on the top side.

As an example if you quoted two boards - all things
being equal except that one was populated on the
top and the second board was populated on both
sides what would be the cost difference (if any)?

The reason I ask is that I am laying out a board
that I may be able to squeeze everything on top.
However I'm tempted to just throw discretes on the
bottom of the board. The engineer asked what was
I going to do. I told him that I'd try to keep everything
on top. He then asked "why"? I answered it would be
easier to manufacture, inspect, debug, eliminate some
manufacturing steps and eliminate some cost. But I
started thinking and wondered if my thinking was backwards
and these concerns are negated with the advance of
technology.

Anyway, any advice would be greatly appreciated. Also
I would like to take a moment and thank everyone for
their particpation on this forum. It has proved extremely useful
for me personally. Enough so that a few strings of humor well
not affect my judgement as to the value of this forum. Actually
I enjoy hearing some of the "old timers" discuss the days of tape
and exact-o knives - personally never had the pleasure.

Thanks
Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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Date:         Fri, 17 Mar 2000 08:20:12 -0400
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Collins, Graham" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Collins, Graham" <[log in to unmask]>
Subject:      Re: One side vs Both side
X-To:         Dennis Ward <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dennis
As one from the build 'em side, I have my preferences, but really the people
you should be asking are those who will build the boards.  They will have
preferences based on their equipment set, and their experiences.

Assuming a board where there are a couple of through-hole parts like
connectors, my preferences are (in order):
1) all on one side  (SMT reflow --> Wave)
2) on both sides, but bottomside laid out for partial wave fixtures (SMT
reflow --> SMT reflow --> Wave)
3) double sided, where bottom side parts have to be wave solder attached
(SMT reflow --> SMT glue on --> Wave).

Obviously #1 will give you the best cycle time as you only have to do one
pass through the SMT line.  So it should be less labour to build.  #2 will
normally give a better process yield than #3, so you save a bit on rework.

Also to consider though is the testing of the board - will the "all on top"
solution give you access you need for incircuit testing?  Design for
manufacture has to be a consideration but also keep in mind design for test.

Kudos for pondering and asking the questions!  And have a good weekend!

regards,

Graham Collins
Process Engineer,
Litton Systems Canada, Atlantic Facility
(902) 873-2000 ext 6215


-----Original Message-----
From: Dennis Ward [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 7:54 AM
To: [log in to unmask]
Subject: [TN] One side vs Both side


Good morning everyone,

Question for all you manufacturing gurus. Is there a
significant advantage, cost wise, to keeping all the components
on the top side of the board versus placing components
on both sides?

Now I do know that they are some NRE cost, but is it
significant? In the past I was taught you should try to
keep every thing on top. But it seems that high density
double side boards are very common. There doesn't
seem to be as much emphasize on consolidating all
the components on the top side.

As an example if you quoted two boards - all things
being equal except that one was populated on the
top and the second board was populated on both
sides what would be the cost difference (if any)?

The reason I ask is that I am laying out a board
that I may be able to squeeze everything on top.
However I'm tempted to just throw discretes on the
bottom of the board. The engineer asked what was
I going to do. I told him that I'd try to keep everything
on top. He then asked "why"? I answered it would be
easier to manufacture, inspect, debug, eliminate some
manufacturing steps and eliminate some cost. But I
started thinking and wondered if my thinking was backwards
and these concerns are negated with the advance of
technology.

Anyway, any advice would be greatly appreciated. Also
I would like to take a moment and thank everyone for
their particpation on this forum. It has proved extremely useful
for me personally. Enough so that a few strings of humor well
not affect my judgement as to the value of this forum. Actually
I enjoy hearing some of the "old timers" discuss the days of tape
and exact-o knives - personally never had the pleasure.

Thanks
Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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=========================================================================
Date:         Fri, 17 Mar 2000 07:21:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McGlaughlin, Jeffrey A" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject:      Re: Micro BGAs
X-To:         Brunker Ed <[log in to unmask]>

Ed -

I just completed a design for a 0.8mm pitch 176 ball Micro-star (tm) BGA and
through-hole vias. The vias were 0.008" (0.010" drill) finished hole size in
a 0.018" pad. I would not call these exactly  normal but my fabricator says
that they should be able to produce them (contact me of line for who)...
This is a six layer mixed signal design, with a 12 amp power supply, talk
about nightmares.

Jeffrey A. McGlaughlin
Sr. PCB Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]


        -----Original Message-----
        From:   Brunker Ed [SMTP:[log in to unmask]]
        Sent:   Friday, 17 March, 2000 05:50
        To:     [log in to unmask]
        Subject:        [TN] Micro BGAs

        Hi,
        Anyone using normal through vias for micro BGAs, 0.8mm pitch???
        Regards
        Edward Brunker
        Principal Process Engineer

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Date:         Fri, 17 Mar 2000 09:45:46 -0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jorge Engenharia <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Engenharia <[log in to unmask]>
Subject:      Re: One side vs Both side
X-To:         Dennis Ward <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

  Dennis

  From my manufacturing point of view I see the following:

  One side pass once trough SMD process it is more productive
  Both side pass twice trough SMD process that could be different ( =
glue or
solder again ) it is less productive

  One side means one machine program one set up
  Both sides means two machine program and two set ups ( more work, =
more
time )

  One side goes direct to production
  Both side creates intermediate buffers ( more space ) and more =
careful
during inventory days=20

  One side uses solder reflow
  Both side could use glue that is a less robust process with high =
defect
rate than solder reflow

  One side means less handling, less opportunity for handling related
problem
  Both sides means more handling and more care must be taken

  One side means one stencil
  Both side means two stencil or one stencil plus glue process that =
means
more manufacturing cost

  One side means no special attention to bottom side support of the =
board
  Both side means special attention must be taken to the bottom side of =
the
board since some components could be damaged by the boards support =
system

  One side means one oven pass
  Both sides means two oven pass that degrades OSP boards and causes
solderability issues in wave solder process

  One side could use bare boards pilled up to loader the line
  Both side requires magazine type loader

  I can't comment the cleaning ( wash ) and conformal coating point of =
view
since I don't have experience in these areas, maybe others can comment =
about
...


   I would say that both side process is more cost, less productive and =
less
robust process but if the advantages of both side process is greater =
than
all work that manufacturing will have or the size requirement is =
important
for design of the product then both side could be used. Make a cost =
analyze
and see by yourself which process is better for your company.
  To produce a both side board with small size to be used inside a =
equipment
that has a lot of space available make no sense for me, but if both =
side
reduces the overall cost of your board or you can reduce the size of =
your
equipment ( and if it is a marketing advantage for you product ) don't
hesitate to go to both side process.

  I hope this help

Jorge Dourado de Santana
Maintenance / Process Engr
Microtec - Brazil

=20

> -----Original Message-----
> From: Dennis Ward [SMTP:[log in to unmask]]
> Sent: 17 de Mar=E7o de 2000 08:54
> To:   [log in to unmask]
> Subject:      [TN] One side vs Both side
>=20
> Good morning everyone,
>=20
> Question for all you manufacturing gurus. Is there a
> significant advantage, cost wise, to keeping all the components
> on the top side of the board versus placing components
> on both sides?
>=20
> Now I do know that they are some NRE cost, but is it
> significant? In the past I was taught you should try to
> keep every thing on top. But it seems that high density
> double side boards are very common. There doesn't
> seem to be as much emphasize on consolidating all
> the components on the top side.
>=20
> As an example if you quoted two boards - all things
> being equal except that one was populated on the
> top and the second board was populated on both
> sides what would be the cost difference (if any)?
>=20
> The reason I ask is that I am laying out a board
> that I may be able to squeeze everything on top.
> However I'm tempted to just throw discretes on the
> bottom of the board. The engineer asked what was
> I going to do. I told him that I'd try to keep everything
> on top. He then asked "why"? I answered it would be
> easier to manufacture, inspect, debug, eliminate some
> manufacturing steps and eliminate some cost. But I
> started thinking and wondered if my thinking was backwards
> and these concerns are negated with the advance of
> technology.
>=20
> Anyway, any advice would be greatly appreciated. Also
> I would like to take a moment and thank everyone for
> their particpation on this forum. It has proved extremely useful
> for me personally. Enough so that a few strings of humor well
> not affect my judgement as to the value of this forum. Actually
> I enjoy hearing some of the "old timers" discuss the days of tape
> and exact-o knives - personally never had the pleasure.
>=20
> Thanks
> Dennis Ward
> Net to Net Technologies, Inc.
> 603 427-0600
> [log in to unmask]
> http://www.nettonettech.com
>=20
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> additional
> information.
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=========================================================================
Date:         Fri, 17 Mar 2000 08:17:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: One side vs Both side
X-To:         Dennis Ward <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dennis,

From one of the old guys from when the 741 Op-Amp was a new marvelous
invention.

If your talking about through hole boards, then putting all the components
on the "top" side is the most cost effective.

If your talking surface mount, then it is just a matter of the added steps
to place components on the top and bottom and then reflow the solder.

Regards, Phil Nutting

-----Original Message-----
From: Dennis Ward [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 6:54 AM
To: [log in to unmask]
Subject: [TN] One side vs Both side


Good morning everyone,

Question for all you manufacturing gurus. Is there a
significant advantage, cost wise, to keeping all the components
on the top side of the board versus placing components
on both sides?

Now I do know that they are some NRE cost, but is it
significant? In the past I was taught you should try to
keep every thing on top. But it seems that high density
double side boards are very common. There doesn't
seem to be as much emphasize on consolidating all
the components on the top side.

As an example if you quoted two boards - all things
being equal except that one was populated on the
top and the second board was populated on both
sides what would be the cost difference (if any)?

The reason I ask is that I am laying out a board
that I may be able to squeeze everything on top.
However I'm tempted to just throw discretes on the
bottom of the board. The engineer asked what was
I going to do. I told him that I'd try to keep everything
on top. He then asked "why"? I answered it would be
easier to manufacture, inspect, debug, eliminate some
manufacturing steps and eliminate some cost. But I
started thinking and wondered if my thinking was backwards
and these concerns are negated with the advance of
technology.

Anyway, any advice would be greatly appreciated. Also
I would like to take a moment and thank everyone for
their particpation on this forum. It has proved extremely useful
for me personally. Enough so that a few strings of humor well
not affect my judgement as to the value of this forum. Actually
I enjoy hearing some of the "old timers" discuss the days of tape
and exact-o knives - personally never had the pleasure.

Thanks
Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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=========================================================================
Date:         Fri, 17 Mar 2000 08:19:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         John Brewer <[log in to unmask]>
Subject:      Of lists and OT postings
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Techsters,

It's all well and good to poo-poo off topic postings as just
harmless diversions, but if allowed to propagate it ends up
chasing away core groups of the subscibers who can't
wade through the off topic postings (..."I know this is not
related to Technet, but...") and jokes.

If everyone took the liberty to break the rules we all agreed
to when we signed up, the list would be useless.

I'd suggest there's plenty of other venues to joke around
in, and that folks consider abiding by the lists charter, and
it doesnt take long reading regular posters' writings to
see that their personalities come shining through even
in on-topic posts! :-)

Respectfully,
John

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=========================================================================
Date:         Fri, 17 Mar 2000 07:22:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      To plug or not to plug
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0056_01BF8FE1.80B7B580"

This is a multi-part message in MIME format.

------=_NextPart_000_0056_01BF8FE1.80B7B580
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

One solution we found to the LPI plugging issue is:

STEP 1: Coat, tack, image, cure, then follow up with a UV cure one one =
side.
STEP 2: Repeat step 1 for the opposite side

Yes, this is somewhat time consuming; however, it has worked out great =
in the few exceptional jobs we needed to do this on.

I welcome all other reasonable solutions.

Thanks,

Franklin D Asbell

------=_NextPart_000_0056_01BF8FE1.80B7B580
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>One solution we found to the LPI =
plugging issue=20
is:</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>STEP 1: Coat, tack, image, =
cure,&nbsp;then follow=20
up with a UV cure one one side.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>STEP 2: Repeat step 1 for the opposite=20
side</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Yes, this is somewhat time consuming; =
however, it=20
has worked out great in the few exceptional jobs we needed to do this=20
on.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>I welcome all other reasonable=20
solutions.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Thanks,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin D =
Asbell</FONT></DIV></BODY></HTML>

------=_NextPart_000_0056_01BF8FE1.80B7B580--

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=========================================================================
Date:         Fri, 17 Mar 2000 05:13:19 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              J G <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         J G <[log in to unmask]>
Subject:      ultra-precision laser vs. visual
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello technetters,
Does anyone know of an ultra precise laser height
checker or a camera? I am looking for a system that
can go down to at least .0001 or tighter. Contact me
offline for application. Hint: Steve Gregory, this may
be up your alley, considering your experience. Thanks
in advance for replies.

__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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=========================================================================
Date:         Fri, 17 Mar 2000 14:48:41 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

 Greg, you are challenging our patience, aren't you(small giggle, hope they can accept that). I mail some pictures offline to you from Ag/Pd end cap ceramic capacitors that showed silver migration under humide to wet conditions. Bad, very bad copies. As I have written hundreds of technical reports, I can't save everything, however, I will look in our secretary's corner, maybe with some luck the original will come up. Migration caused shorts within 10 seconds in worst cases. By adding humidity absorbers in that part, no more troubles are heard. That was many years ago. The show was not in a very scientific way, just an attempt to verify artificially what happened in product's reality.

cu offline, hillabilly

Ingemar
PS. I used some non-techno words above, I apologize.



"Stephen R. Gregory" wrote:

> How the heck are yew good ol' boys doin'?
>
> (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk with a
> mouthful of terbacky...(hitchin' my bib overalls up)
>
> Anyhoo, a while back, some good ol' boy posted a simple way to actually show
> electromigration (fancy word for us country boys ain't it) in progress...you
> could actually see it happening. Something about using an overhead projector
> and a 9-volt battery...or something like that.
>
> Does anybody remember that? I need some way to graphically show this
> phenomena  happening...('nuther fancy word huh?...phenomena...)
>
> YEEEE-HAW!!!
> (that's good ol' boy talk for thanks a lot!)
>
> -Steve "Jethro" Gregory- (GRIN)
>

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Date:         Fri, 17 Mar 2000 08:54:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jeff Hempton <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Hempton <[log in to unmask]>
Subject:      To plug or not to plug
Mime-Version: 1.0
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--IMA.Boundary.7451033590
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     Franklin,
     Thanks to everyone for your responses on this so far.
       Do I understand correctly that you use a standard LPI and totally
     cover, or "tent" over the vias, then UV cure, then repeat on other
     side? And the UV cure keeps the LPI from creating a blow-hole during
     assembly? Or are you UV curing a separate "plug" material, then LPI
     covering?
     Jeff Hempton
     UT Electronic Controls


______________________________ Forward Header __________________________________
Subject: [TN] To plug or not to plug
Author:  Franklin Asbell <[log in to unmask]> at Internet
Date:    03/17/2000 7:22 AM


One solution we found to the LPI plugging issue is:

STEP 1: Coat, tack, image, cure, then follow up with a UV cure one one side.
STEP 2: Repeat step 1 for the opposite side

Yes, this is somewhat time consuming; however, it has worked out great in the
few exceptional jobs we needed to do this on.

I welcome all other reasonable solutions.

Thanks,

Franklin D Asbell

--IMA.Boundary.7451033590
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Content-Description: cc:Mail note part

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>One solution we found to the LPI plugging issue
is:</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=Arial size=2>STEP 1: Coat, tack, image, cure,&nbsp;then follow
up with a UV cure one one side.</FONT></DIV>
<DIV><FONT face=Arial size=2>STEP 2: Repeat step 1 for the opposite
side</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=Arial size=2>Yes, this is somewhat time consuming; however, it
has worked out great in the few exceptional jobs we needed to do this
on.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=Arial size=2>I welcome all other reasonable
solutions.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=Arial size=2>Thanks,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=Arial size=2>Franklin D Asbell</FONT></DIV></BODY></HTML>

--IMA.Boundary.7451033590--

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Date:         Fri, 17 Mar 2000 15:09:56 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

Reminds of my own experiment years ago, Brian. I sent pictures to Steve, would be interesting to compare. Silver migration is not anything remarkable, but seemingly, few saw it  happen live. /Ingemar

-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: den 17 mars 2000 09:09
To: [log in to unmask]
Subject: Re: [TN] Electromigration demonstration...


Steve

The original dendrite wizard was Charles Jennings (if my memory is good) in some US
Govt lab (Sandia???) in the 1970s. He actually made a 16 mm film of it happening (I
have a PAL video copy of it). He said that dendrite formation could be thus provoked on
any substrate between any metals, but the rate and form was very variable for a given
ionic contamination level.

I recommend you put a 10 - 47 kilohm R in series with your battery: it will reduce the
gas formation and keep the dendrites intact longer, because the current is smaller.

BTW, this is not electromigration, it is electrochemical migration, two different
things. The latter is ionic in nature.

Brian

"Stephen R. Gregory" wrote:

> How the heck are yew good ol' boys doin'?
>
> (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk with a
> mouthful of terbacky...(hitchin' my bib overalls up)
>
> Anyhoo, a while back, some good ol' boy posted a simple way to actually show
> electromigration (fancy word for us country boys ain't it) in progress...you
> could actually see it happening. Something about using an overhead projector
> and a 9-volt battery...or something like that.
>
> Does anybody remember that? I need some way to graphically show this
> phenomena  happening...('nuther fancy word huh?...phenomena...)
>
> YEEEE-HAW!!!
> (that's good ol' boy talk for thanks a lot!)
>
> -Steve "Jethro" Gregory- (GRIN)
>
> ##############################################################
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Date:         Fri, 17 Mar 2000 08:14:54 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: v-scoring with perimeter copper on topside
X-To:         Ken Patel <[log in to unmask]>
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Ken,

So I understand your situation, the score will be cutting through the copper
on the top side?

Franklin

----- Original Message -----
From: Ken Patel <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 5:25 PM
Subject: [TN] v-scoring with perimeter copper on topside


> Guys,
> We are designing a very small board (.5" x 2") on an array. We think, we
can
> put it on an array with V-score for separation. Individual board has
> perimeter copper on topside. It's a double sided board.  There is no
> component in the vicinity of perimeter copper.
>
> Knowing this, can I still go for v-score Or for V-grove, there should not
be
> copper in the cutting area ?
>
> re,
> ken patel
>
> ______________________________________________________
> Ken Patel                       Phone:  (408) 490-6804
> 1708 McCarthy Blvd.             Fax:    (408) 490-6859
> Milpitas, CA 95035              Beeper: (888) 769-1808
>
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Date:         Fri, 17 Mar 2000 08:18:56 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: To plug or not to plug
X-To:         Jeff Hempton <[log in to unmask]>
MIME-Version: 1.0
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Actually it's a simple UV bump of the thermal cured LPI. Just add's more
'oooomph' to the solder mask.

You can't push the ink over the board at normal speed either, take it nice
and slow and double pushing helps too.

No UV ink is used.

What we learned is when these are done in separate cycles it eliminated any
problems (i.e. blowholes) at the assemblers.

We don't make a practice as it is time consuming but for the have a handful
of product types we do this for, it's work without adverse incidents.

Franklin

----- Original Message -----
From: Jeff Hempton <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 17, 2000 5:54 AM
Subject: [TN] To plug or not to plug


>      Franklin,
>      Thanks to everyone for your responses on this so far.
>        Do I understand correctly that you use a standard LPI and totally
>      cover, or "tent" over the vias, then UV cure, then repeat on other
>      side? And the UV cure keeps the LPI from creating a blow-hole during
>      assembly? Or are you UV curing a separate "plug" material, then LPI
>      covering?
>      Jeff Hempton
>      UT Electronic Controls
>
>
> ______________________________ Forward Header
__________________________________
> Subject: [TN] To plug or not to plug
> Author:  Franklin Asbell <[log in to unmask]> at Internet
> Date:    03/17/2000 7:22 AM
>
>
> One solution we found to the LPI plugging issue is:
>
> STEP 1: Coat, tack, image, cure, then follow up with a UV cure one one
side.
> STEP 2: Repeat step 1 for the opposite side
>
> Yes, this is somewhat time consuming; however, it has worked out great in
the
> few exceptional jobs we needed to do this on.
>
> I welcome all other reasonable solutions.
>
> Thanks,
>
> Franklin D Asbell
>


----------------------------------------------------------------------------
----


> <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
> <HTML><HEAD>
> <META content="text/html; charset=iso-8859-1" http-equiv=Content-Type>
> <META content="MSHTML 5.00.2614.3500" name=GENERATOR>
> <STYLE></STYLE>
> </HEAD>
> <BODY bgColor=#ffffff>
> <DIV><FONT face=Arial size=2>One solution we found to the LPI plugging
issue
> is:</FONT></DIV>
> <DIV>&nbsp;</DIV>
> <DIV><FONT face=Arial size=2>STEP 1: Coat, tack, image, cure,&nbsp;then
follow
> up with a UV cure one one side.</FONT></DIV>
> <DIV><FONT face=Arial size=2>STEP 2: Repeat step 1 for the opposite
> side</FONT></DIV>
> <DIV>&nbsp;</DIV>
> <DIV><FONT face=Arial size=2>Yes, this is somewhat time consuming;
however, it
> has worked out great in the few exceptional jobs we needed to do this
> on.</FONT></DIV>
> <DIV>&nbsp;</DIV>
> <DIV><FONT face=Arial size=2>I welcome all other reasonable
> solutions.</FONT></DIV>
> <DIV>&nbsp;</DIV>
> <DIV><FONT face=Arial size=2>Thanks,</FONT></DIV>
> <DIV>&nbsp;</DIV>
> <DIV><FONT face=Arial size=2>Franklin D Asbell</FONT></DIV></BODY></HTML>
>

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Date:         Fri, 17 Mar 2000 15:21:05 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         Justin Braime <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

Again, you seem to mean chemical migration across the board's members. We have never had any problem that way, as Gold is much more stable than Silver. So is Copper, Lead and Tin. But, in a few cases we have in fact had Copper migrating into the Gold despite a very thick Nickel barrier. How? Explanation was poor Nickel covering on vertical line edges, near conductor foot on FR4. So Copper migrated out the side of the pads and appeared on top. Does not occur at room temp. Otherwise, we use to say, if you get migration, you have not read the first chapters in the designer's guides.  I recommend you to buy from ASM Morris E. Nicholson's 'Electronic Packaging and Corrosion in Microelectronics' . One of dozens of books describing migration. I suppose Werner has written some himself.  /Ingemar

-----Original Message-----
From: Justin Braime [mailto:[log in to unmask]]
Sent: den 16 mars 2000 23:07
To: [log in to unmask]
Subject: Re: [TN] Electromigration demonstration...


Here's another question for you...
How do HASL, Gold, and Alpha levelled boards compare with regard to electromigration?

Thanks

Justin Braime
------------------------
Process Engineer
Compuspec Industries Ltd
Auckland, New Zealand
[log in to unmask] <mailto:[log in to unmask]>

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=========================================================================
Date:         Fri, 17 Mar 2000 08:08:36 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Steve Collins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Steve Collins <[log in to unmask]>
Subject:      Re: v-scoring with perimeter copper on topside
X-To:         Ken Patel <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

I would not v-groove this board if you cannot get relief of the copper on the
top from the edge of the board at least .030. Problem is you will end up with a
burr on the edge of the board that can cause problems when you separate boards.

Steve Collins

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Date:         Fri, 17 Mar 2000 08:17:40 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Kalgren <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Kalgren <[log in to unmask]>
Subject:      Saint Patrick's Day Humor [No Technical Content]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Just thought I'd pass along some St. Paddy's jokes to everyone.
Some of them could be offensive if they weren't just jokes.
Have a great Friday and St. Patrick's Day.
Jokes follow signature.






*********************
"You know, I had me every woman in this town, except of course, me
mother and me sister."
"Well," Sean replied, "between you and me we got'em all."

********************
Pat & Mick landed themselves a job at a sawmill. Just before the
morning break, Pat yelled "Mick, I've lost me finger!"
"Have you now," said Mick. "And how did you do it?"
Pat replied "I just touched this big, shiny spinning thing here like
this... damn! There goes another one!"

********************
Mahoney said to his friend McMaken, "I haven't been feelin' meself
lately!"
"Tis a good thing, too - that was a nasty habit you had!" responded
McMaken.

********************
An Irishman who had a little to drink is driving home from the city
one night and, of course, his car is weaving violently all over the
road. A cop pulls him over. "So," says the cop to the driver, "where
have you been?"
"Why, I've been to the pub of course" slurs the drunk.
"Well," says the cop, "it looks like you've had quite a few to drink
this evening".
"I did all right," the drunk says with a smile.
"Did you know," says the cop, standing straight and folding his arms
across his chest, "that a few intersections back, your wife fell out
of your car?"
"Oh, thank heavens," sighs the drunk. "For a minute there, I thought
I'd gone deaf."

**************************
Brenda O'Malley is home making dinner, as usual, when Tim Finnegan
arrives at her door. "Brenda, may I come in?" he asks. "I've somethin'
to tell ya."
"Of course you can come in, you're always welcome, Tim. But where's
my husband?"
"That's what I'm here to be tellin' ya, Brenda. There was an accident
down at the Guiness brewery..."
"Oh, God no!" cries Brenda. "Please don't tell me..."
"I must, Brenda. Your husband Shamus is dead and gone. I'm sorry."
Finally, she looked up at Tim. "How did it happen, Tim?"
"It was terrible, Brenda.  He fell into a vat of Guiness Stout and
drowned."
"Oh my dear Jesus! But you must tell me true, Tim. Did he at least go
quickly?"
"Well, no Brenda... no."
"No?"
"Fact is, he got out three times to pee."

*******************************
Mary Clancy goes up to Father O'Grady after his Sunday morning
service, and she's in tears. He says, "So what's bothering you,
dear?"
She says, "Oh, Father, I've got terrible news. My husband passed away
last night."
The priest says, "Oh, Mary, that's terrible. Tell me, Mary, did he
have any last requests?"
She says, "Aye, That he did, Father..."
"The priest says, "What did he ask, Mary?"
She says, "He said,'Please, Mary, put down that damn gun...


Eric Kalgren
BFGoodrich Aerospace
Space Flight Systems
[log in to unmask]
(505) 938-5139

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=========================================================================
Date:         Fri, 17 Mar 2000 15:15:17 -0000
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Finlay Buchan <[log in to unmask]>
Subject:      Re: One side vs Both side
X-To:         Jorge Engenharia <[log in to unmask]>
In-Reply-To:  <194A0324C762D2119D340060089E2BE29B91E1@EXCHANGESVRILH>
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Jorge

I know that we manufacture pallets but so do a lot of other companies so
please do not regard this as spam.

If you *have* to place both sides of a pcb,and one side does not have fine
pitched components (less than 15 thou), think about using a 2 or more
aperture print placement reflow carrier.

In one aperture place a raw card, in the second flip the half processed card
then process. At the end of the line take out the completed card and send
the carrier back to the front of the line with the half completed card.

This makes the following changes to your comments

>Subject: Re: [TN] One side vs Both side
>
>
>   Dennis
>
>   From my manufacturing point of view I see the following:
>
>   One side pass once trough SMD process it is more productive
>   Both side pass twice trough SMD process that could be
> different ( glue or
> solder again ) it is less productive
>

Now in the same time - except for placement.


>   One side means one machine program one set up
>   Both sides means two machine program and two set ups ( more
> work, more
> time )

Only one set up

>
>   One side goes direct to production
>   Both side creates intermediate buffers ( more space ) and
> more careful
> during inventory days

No buffer stock except those half completed cards in the carriers.

>
>   One side uses solder reflow
>   Both side could use glue that is a less robust process with
> high defect
> rate than solder reflow

Both sides use reflow

>
>   One side means less handling, less opportunity for handling related
> problem
>   Both sides means more handling and more care must be taken

No change

>
>   One side means one stencil
>   Both side means two stencil or one stencil plus glue
> process that means
> more manufacturing cost

One Stencil

>
>   One side means no special attention to bottom side support
> of the board
>   Both side means special attention must be taken to the
> bottom side of the
> board since some components could be damaged by the boards
> support system

Agreed but carrier can be used to support flimsy cards
>
>   One side means one oven pass
>   Both sides means two oven pass that degrades OSP boards and causes
> solderability issues in wave solder process

No change

>
>   One side could use bare boards pilled up to loader the line
>   Both side requires magazine type loader
>

No change

>   I can't comment the cleaning ( wash ) and conformal coating
> point of view
> since I don't have experience in these areas, maybe others
> can comment about
> ...
>
>
>    I would say that both side process is more cost, less
> productive and less
> robust process but if the advantages of both side process is
> greater than
> all work that manufacturing will have or the size requirement
> is important
> for design of the product then both side could be used. Make
> a cost analyze
> and see by yourself which process is better for your company.
>   To produce a both side board with small size to be used
> inside a equipment
> that has a lot of space available make no sense for me, but
> if both side
> reduces the overall cost of your board or you can reduce the
> size of your
> equipment ( and if it is a marketing advantage for you product ) don't
> hesitate to go to both side process.
>
>   I hope this help
>
> Jorge Dourado de Santana
> Maintenance / Process Engr
> Microtec - Brazil
>


Just another angle - hope this helps

Regards

Fin

Finlay Buchan
Technical Director
Datum Dynamics Ltd           Datum Dynamics Inc
Tel +44 (0)1290 426200       +001 401 683 5300
Fax +44 (0)1290 426212       +001 401 683 3995
Email [log in to unmask]
Web Page http://www.datumdynamics.com

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=========================================================================
Date:         Fri, 17 Mar 2000 07:29:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Regis Froats <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Regis Froats <[log in to unmask]>
Subject:      Re: v-scoring with perimeter copper on topside
X-To:         Ken Patel <[log in to unmask]>
In-Reply-To:  <2.2.32.20000317012541.0075e5b8@kms>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

No.  You should recess the copper depending on the depth of the V-groove
and the score angle or else you run the risk of the copper lifting in the
area of the groove.

At 17:25 03/16/2000 -0800, you wrote:
>Guys,
>We are designing a very small board (.5" x 2") on an array. We think, we can
>put it on an array with V-score for separation. Individual board has
>perimeter copper on topside. It's a double sided board.  There is no
>component in the vicinity of perimeter copper.
>
>Knowing this, can I still go for v-score Or for V-grove, there should not be
>copper in the cutting area ?
>
>re,
>ken patel
>
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
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--
Regis Froats <[log in to unmask]>
Process Engineer - Herco Technology Corp.
13330 Evening Creek Drive North
San Diego, Ca. 92128
Pho:858.679.2800 - Fax:858.679.7565

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Date:         Fri, 17 Mar 2000 09:27:40 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Beerman, Dennis" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Beerman, Dennis" <[log in to unmask]>
Subject:      Re: v-scoring with perimeter copper on topside
X-To:         Steve Collins <[log in to unmask]>

Another potential problem is the exposed copper edges.

        ----------
        From:  Steve Collins [SMTP:[log in to unmask]]
        Sent:  Friday, March 17, 2000 10:09 AM
        To:  [log in to unmask]
        Subject:  Re: [TN] v-scoring with perimeter copper on topside

        I would not v-groove this board if you cannot get relief of the
copper on the
        top from the edge of the board at least .030. Problem is you will
end up with a
        burr on the edge of the board that can cause problems when you
separate boards.

        Steve Collins

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Date:         Fri, 17 Mar 2000 09:30:03 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Kell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Kell <[log in to unmask]>
Subject:      Nail-Head Pin Soldering
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

I recieved a response to my question concerning soldering nailhead pins.  =
However, I mistakedly deleted the response.  I've checked with the network =
people and it would take an act of GOD to retrieve.  I've also checked =
TechNet archives and it does not exist.  Apparently, the response was sent =
to my personal mailbox.

Can the person or persons please resent their answer?

Thanks, I owe you a cup of cybercoffee.

Regards,=20
Dave Kell

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Date:         Fri, 17 Mar 2000 07:44:34 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: ESD issue with microblast conformal coating removal
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

the people at crystal mark have a lot of data about this.  also a don larson at mcclellan air force base, sacramento, ca (not canada).  if you bring up the following thomas register url, you will get the address and telephone no.  basically, if you don't take great care, abrasive blasting will light up your pwa.

http://www.crystalmark.thomasregister.com/olc/crystalmark/compnts.htm

phil

-----Original Message-----
From: Kang Zhang [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 2:57 PM
To: [log in to unmask]
Subject: [TN] ESD issue with microblast conformal coating removal


Hi, all

Are there any literature, standard, industry guidelines/specifications done
on the
effects of rework and conformal coating removal on ESD?

Any information is appreciated.

Kang Zhang
Reliability Engineer
ELDEC Corporation

______________________________________________________
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Date:         Fri, 17 Mar 2000 16:47:27 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      silver migration
X-To:         "Stephen R. Gregory" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

Hi, original report found faster than I expected. Took small part out of it, special for Steve. He can give it to somebody else if of interest. //Ingemar

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Date:         Fri, 17 Mar 2000 07:57:36 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Vaughan, Ralph H" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Vaughan, Ralph H" <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We ran a similar test to the parallel trace one...used Y-coupons from pwb
panel.  Results same as previously described..Twist on the test was to also
run an identical coupon except put 1-2 mils of acrylic conformal coat over
traces.  Even tho power/water drop was maintained, no ---migration after 2
months.  (I know speaking of conformal coat is like
fingernails-on-chalkboard to you commercial tykes...sorry)

Ralph Vaughan
Boeing-Atlanta

> ----------
> From:         Ingemar Hernefjord
> (EMW)[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Ingemar Hernefjord (EMW)
> Sent:         Friday, March 17, 2000 9:09 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] Electromigration demonstration...
>
> Reminds of my own experiment years ago, Brian. I sent pictures to Steve,
> would be interesting to compare. Silver migration is not anything
> remarkable, but seemingly, few saw it  happen live. /Ingemar
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: den 17 mars 2000 09:09
> To: [log in to unmask]
> Subject: Re: [TN] Electromigration demonstration...
>
>
> Steve
>
> The original dendrite wizard was Charles Jennings (if my memory is good)
> in some US
> Govt lab (Sandia???) in the 1970s. He actually made a 16 mm film of it
> happening (I
> have a PAL video copy of it). He said that dendrite formation could be
> thus provoked on
> any substrate between any metals, but the rate and form was very variable
> for a given
> ionic contamination level.
>
> I recommend you put a 10 - 47 kilohm R in series with your battery: it
> will reduce the
> gas formation and keep the dendrites intact longer, because the current is
> smaller.
>
> BTW, this is not electromigration, it is electrochemical migration, two
> different
> things. The latter is ionic in nature.
>
> Brian
>
> "Stephen R. Gregory" wrote:
>
> > How the heck are yew good ol' boys doin'?
> >
> > (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk
> with a
> > mouthful of terbacky...(hitchin' my bib overalls up)
> >
> > Anyhoo, a while back, some good ol' boy posted a simple way to actually
> show
> > electromigration (fancy word for us country boys ain't it) in
> progress...you
> > could actually see it happening. Something about using an overhead
> projector
> > and a 9-volt battery...or something like that.
> >
> > Does anybody remember that? I need some way to graphically show this
> > phenomena  happening...('nuther fancy word huh?...phenomena...)
> >
> > YEEEE-HAW!!!
> > (that's good ol' boy talk for thanks a lot!)
> >
> > -Steve "Jethro" Gregory- (GRIN)
> >
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Date:         Fri, 17 Mar 2000 11:00:18 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      HELP!! Press-fit connector!
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi guys!

I know this is gonna be a long-shot...but we've got ourselves in quite a
quandry.
We have a board we build here that uses DIN 41612 press-fit connectors. The
connector that we used before came from Harting, but they've discontinued it.

There's a Erni press-fit that crosses over to the Harting part number, the
footprint matches, the mating dimensions match, so that connector was bought.
The only problem now is that the tooling we have is for the Harting
connector, and doesn't work for the Erni connector. Erni makes the tooling,
but with a lead time of 10-weeks (or something like that...) The buyers
didn't think about that, and neglected to let us manufacturing floor rats
know that a different connector was going to be used on this
assembly...typical, huh?

We've got the boards built, but can't press the connector in...we're supposed
to deliver the boards next week...great huh?

So, what I'm asking is there anybody out there that already has this tooling
that would consider pressing the connectors in for us for a fee? Or have any
other ideas that you might share to help us through this debacle?

I know hind-site is 20/20 but we really need to do something to get us
through now...
I'm only talking about 20-30 boards...

The exact Erni connector is PN# 013131, it's a DIN 41612, Right Angle Male
3-row 96-pin, type C.

Thanks (I told ya' it would be a long shot!)

-Steve Gregory-

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Date:         Fri, 17 Mar 2000 11:18:45 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McMonagle, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McMonagle, Mike" <[log in to unmask]>
Subject:      Re: ESD issue with microblast conformal coating removal
X-To:         Phil Crepeau <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Check out CCR at http://www.ccrco.com, they have an ESD safe microblast
removal chamber and a nifty conformal coating system that doesn't require
component masking.

Mike McMonagle
PCBA Process Engineering
Telxon Corporation
(713) 307-2443 Phone
(713) 307-2581 Fax
www.telxon.com

' Innovative Solutions for
Mobile Information and
Wireless Communications'


-----Original Message-----
From: Phil Crepeau [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 9:45 AM
To: [log in to unmask]
Subject: Re: [TN] ESD issue with microblast conformal coating removal


hi,

the people at crystal mark have a lot of data about this.  also a don larson
at mcclellan air force base, sacramento, ca (not canada).  if you bring up
the following thomas register url, you will get the address and telephone
no.  basically, if you don't take great care, abrasive blasting will light
up your pwa.

http://www.crystalmark.thomasregister.com/olc/crystalmark/compnts.htm

phil

-----Original Message-----
From: Kang Zhang [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 2:57 PM
To: [log in to unmask]
Subject: [TN] ESD issue with microblast conformal coating removal


Hi, all

Are there any literature, standard, industry guidelines/specifications done
on the
effects of rework and conformal coating removal on ESD?

Any information is appreciated.

Kang Zhang
Reliability Engineer
ELDEC Corporation

______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com

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Date:         Fri, 17 Mar 2000 11:19:50 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         To My E-Mail Address <[log in to unmask]>
Subject:      Re: Micro BGAs
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

ED,

We are currently making a couple of designs wth micro-BGA's.  1 has 1 micro
BGA and other has 16 of them.  Both have through hole vias.  Both are 10
layer brds.  THe  engineer had problem with brd layout using Auto ROUTER.
Hand routing did the job.

Call or write for more details.

Rush
Accurate Engg
818-768-3919

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Date:         Fri, 17 Mar 2000 08:40:17 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: ESD issue with microblast conformal coating removal
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

a couple more things about abrasive microblasters.  you need to validate everyone's equipment.  for example, it is not enough merely to supply ionized air to the blasting chamber.  the nozzle needs to be grounded as well as the work.  often this is not sufficient.

it takes some pretty sophisticated equipment and great experimental techniques to assure that the part you are blasting is not being exposed to excessive voltages.  using an instrument that monitors air ionization is not enough.  you need to wire your assembly into an electrostatic voltmeter.

also, be aware that different materials generate wildly different amounts of esd.  there is a polymeric material sold by solidstrip, inc called solidstrip l that used to be the material that generated the least amount of esd.  solidstrip's no. is 302.292.8340.

finally, there is a mantech report (tr94-1) from the army that you would probably find useful.  the last name and no. for a contact was: jeffrey m. carr, 205.876.1661.

phil

-----Original Message-----
From: Kang Zhang [mailto:[log in to unmask]]
Sent: Thursday, March 16, 2000 2:57 PM
To: [log in to unmask]
Subject: [TN] ESD issue with microblast conformal coating removal


Hi, all

Are there any literature, standard, industry guidelines/specifications done
on the
effects of rework and conformal coating removal on ESD?

Any information is appreciated.

Kang Zhang
Reliability Engineer
ELDEC Corporation

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Date:         Fri, 17 Mar 2000 11:41:39 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "(George  Milad)" <[log in to unmask]>
Subject:      Re: stain&gold plating
X-To:         [log in to unmask]
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I second Jonathans analysis that the stain could be a result of staining on
the initial copper substrate. Examine the work before the ENIG line. If you
see uneven reflectivity, then optomize the cleaner (temp and dwell time) and
increase the total microinches(uins) of copper removed (to >50uins) in the
micro-etch step.
George Milad
Shipley Ronal Inc

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Date:         Fri, 17 Mar 2000 19:00:40 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Electromigration demonstration...
X-To:         "Vaughan, Ralph H" <[log in to unmask]>
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Ralph

I wouldn't expect a conformal coating to fail with a water drop, but just try it in a
humid atmosphere and see the difference. An acrylic coating is probably the best from
the point of view of humidity resistance (silicones the worst), but even it is a sieve
to humidity.

Brian

"Vaughan, Ralph H" wrote:

> We ran a similar test to the parallel trace one...used Y-coupons from pwb
> panel.  Results same as previously described..Twist on the test was to also
> run an identical coupon except put 1-2 mils of acrylic conformal coat over
> traces.  Even tho power/water drop was maintained, no ---migration after 2
> months.  (I know speaking of conformal coat is like
> fingernails-on-chalkboard to you commercial tykes...sorry)
>
> Ralph Vaughan
> Boeing-Atlanta
>
> > ----------
> > From:         Ingemar Hernefjord
> > (EMW)[SMTP:[log in to unmask]]
> > Reply To:     TechNet E-Mail Forum.;Ingemar Hernefjord (EMW)
> > Sent:         Friday, March 17, 2000 9:09 AM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] Electromigration demonstration...
> >
> > Reminds of my own experiment years ago, Brian. I sent pictures to Steve,
> > would be interesting to compare. Silver migration is not anything
> > remarkable, but seemingly, few saw it  happen live. /Ingemar
> >
> > -----Original Message-----
> > From: Brian Ellis [mailto:[log in to unmask]]
> > Sent: den 17 mars 2000 09:09
> > To: [log in to unmask]
> > Subject: Re: [TN] Electromigration demonstration...
> >
> >
> > Steve
> >
> > The original dendrite wizard was Charles Jennings (if my memory is good)
> > in some US
> > Govt lab (Sandia???) in the 1970s. He actually made a 16 mm film of it
> > happening (I
> > have a PAL video copy of it). He said that dendrite formation could be
> > thus provoked on
> > any substrate between any metals, but the rate and form was very variable
> > for a given
> > ionic contamination level.
> >
> > I recommend you put a 10 - 47 kilohm R in series with your battery: it
> > will reduce the
> > gas formation and keep the dendrites intact longer, because the current is
> > smaller.
> >
> > BTW, this is not electromigration, it is electrochemical migration, two
> > different
> > things. The latter is ionic in nature.
> >
> > Brian
> >
> > "Stephen R. Gregory" wrote:
> >
> > > How the heck are yew good ol' boys doin'?
> > >
> > > (Spitoooie!!)...'scuse me thar...hadda get rid of my chew, cain't talk
> > with a
> > > mouthful of terbacky...(hitchin' my bib overalls up)
> > >
> > > Anyhoo, a while back, some good ol' boy posted a simple way to actually
> > show
> > > electromigration (fancy word for us country boys ain't it) in
> > progress...you
> > > could actually see it happening. Something about using an overhead
> > projector
> > > and a 9-volt battery...or something like that.
> > >
> > > Does anybody remember that? I need some way to graphically show this
> > > phenomena  happening...('nuther fancy word huh?...phenomena...)
> > >
> > > YEEEE-HAW!!!
> > > (that's good ol' boy talk for thanks a lot!)
> > >
> > > -Steve "Jethro" Gregory- (GRIN)
> > >
> > > ##############################################################
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Date:         Fri, 17 Mar 2000 08:38:47 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ahne Oosterhof <[log in to unmask]>
Subject:      Re: White Tin  instead of Gold for edge connectors
X-To:         Franklin Asbell <[log in to unmask]>
In-Reply-To:  <001701bf8fa6$9c3c3dc0$6400a8c0@franklin>
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You can use connectors with tin plating, but only in applications where the
board has to be removed only rarely! It is also recommended to use
connectors with high contact pressure.
I used it in such an application in an oscilloscope. That family of scopes
lived for over 20 years in the catalog and on customers desks without
getting complaints!

Regards, Ahne Oosterhof.

-----Original Message-----
From:   TechNet [mailto:[log in to unmask]] On Behalf Of Franklin Asbell
Sent:   Thursday, March 16, 2000 16:21 PM
To:     [log in to unmask]
Subject:        [TN] White Tin  instead of Gold for edge connectors

Bill,

In my opinion, the use of white tin (I'm assuming you're referring to a flat
solderable tin (no specific proprietary blend intended)) in place of gold on
tabs would offer the same properties except for oxide resistence. The tin is
going to oxide very rapidly, long before they will wear out from use. Now
the appearance of the oxide may not be an issue in and of itself; however,
once the oxide begins, electrical failures will follow.

I'm quite confident also, the gold you are currently using is more durable
then the tin finish options I know are available? Have no data to support
this, but I would guess the repeated insertions of tin would be far limited
then with gold.

Franklin D Asbell

----- Original Message -----
From: Ramsey, Guy <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 16, 2000 2:00 PM
Subject: [TN] White Tin instead of Gold for edge connectors


> Can we keep this discussion on the net. We are very interested in this
issue
> as well. In fact, Bill may be making these boards for us. The mating
> connectors are gold in one case. In another the mating connector is tin
over
> nickel.
>
> -----Original Message-----
> From: rampinc [mailto:[log in to unmask]]
> Sent: Thursday, March 16, 2000 4:10 PM
> Subject: <No subject given>
>
>
> Bill,
> What is your application of this connector? Assuming it is a card edge
> connector, how
> many insertions are required, what is the connecor insertion force, what
is
> the contact
> geometry and are they using contact lube or not, tin ( white or any other
> shades) may
> cause more problems. Also it is important to keep same plated finish
 Au-Au
> or Sn-Sn)
> on both parts ie contact fingers and contact spring.
>
> Please discuss off line if you need more details about contact reliability
> issues
> involved.
>
> Bill Decray wrote:
>
> > CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> > CONNECTOR FINGERS.
> > MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE
THEY
> > ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
> >
> > William W. DeCray III
> > Waytec Electronics Corp
> > Sales Engineer
> > PHONE:(804) 237-6391 ext 115
> > FAX:    (804) 237-1324
> > E-mail:<[log in to unmask]>
> > Web <http://www.waytec.com>
> > FTP <ftp://ftp.waytec.com>
> >
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Date:         Fri, 17 Mar 2000 18:26:16 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Roland Jaquet <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Roland Jaquet <[log in to unmask]>
Organization: Info-Elec Ltd.
Subject:      Base Material - Shortage?
MIME-Version: 1.0
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Dear Technetters,

I writing here on the behalf of several concerned parties, including some
European OEMs, CEMs and PCB Manufacturers.

Some European manufacturers are worrying about Base Material Shortage, by
shortage it is understood extended delivery Lead-Time.
Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
some more complex Base Material, lead time can run to 14 weeks in some
particular instance.

Do you Technetters from all over the world and from the USA, are witnessing
such increase in delivery time?

Are worrying about it?
Some of you are considering shutting off the plant for some days like some
are considering doing in Europe if it doesn't improve?
Would you comment on your concerns ?
Is there any Base Material Manufacturers here who could give us the status
for their companies?

Please do not over-react to this posting and place big orders as this would
only cause the situation to get worst for most likely no real reason.
PLEASE no "Snow-Ball" effect.

Thank you

Very Best Regards
Roland
Info-Elec Ltd.
Golden Eyes? -  Live and Let Buy...  www.PCB007.com
Providing Global e-Business Solutions For The PCB Industry
Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
+41-79-203-3723
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Date:         Fri, 17 Mar 2000 12:56:59 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Re: Base Material - Shortage?
X-To:         Roland Jaquet <[log in to unmask]>
In-Reply-To:  <024a01bf9036$04a1a780$31550fc3@hp620>
MIME-Version: 1.0
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Roland,

I guess I would have to ask what do you mean by more complex base materials?
I am currently unaware of any
Issues with extended lead time with respect to FR4 or Polyimide type
materials. I will check with purchasing to see
If they have heard anything but so far this is news to me.

Ed Cosper
ABC
Vestal NY

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Roland Jaquet
Sent: Friday, March 17, 2000 12:26 PM
To: [log in to unmask]
Subject: [TN] Base Material - Shortage?

Dear Technetters,

I writing here on the behalf of several concerned parties, including some
European OEMs, CEMs and PCB Manufacturers.

Some European manufacturers are worrying about Base Material Shortage, by
shortage it is understood extended delivery Lead-Time.
Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
some more complex Base Material, lead time can run to 14 weeks in some
particular instance.

Do you Technetters from all over the world and from the USA, are witnessing
such increase in delivery time?

Are worrying about it?
Some of you are considering shutting off the plant for some days like some
are considering doing in Europe if it doesn't improve?
Would you comment on your concerns ?
Is there any Base Material Manufacturers here who could give us the status
for their companies?

Please do not over-react to this posting and place big orders as this would
only cause the situation to get worst for most likely no real reason.
PLEASE no "Snow-Ball" effect.

Thank you

Very Best Regards
Roland
Info-Elec Ltd.
Golden Eyes? -  Live and Let Buy...  www.PCB007.com
Providing Global e-Business Solutions For The PCB Industry
Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
+41-79-203-3723
_______________________________________________________________________

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Date:         Fri, 17 Mar 2000 10:05:34 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Thompson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Thompson <[log in to unmask]>
Subject:      Oven Profile Recommendations?
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I've inherited a system of maintaining oven profiles where each assembly was
given it's own profile.  While this may have been more appropriate with IR,
I don't think that current convection ovens require this many.  I'm
intending to try and reduce our profiles to 6 or so that can cover the range
of products we run.   Is this a practical approach?  I believe it is, but
would appreciate any comments.  I'd also like to get feedback on systems
that are currently being used.  How are you categorizing your profiles
(mass, board size, etc.)?

Thanks.


Rick Thompson
Ventura Electronics Assembly
2665A Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858 voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Fri, 17 Mar 2000 12:07:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      On electromigration and cleanliness
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_001A_01BF9009.6FAA4B40"

This is a multi-part message in MIME format.

------=_NextPart_000_001A_01BF9009.6FAA4B40
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I used the battery and leads to a bare board to show the effects of =
handling contamination.

Works about the same as the other methods

Using a bare board without solder mask and tin/lead reflowed circuits I:

1. Connected a battery to two circuits using a 9 volt and alligator =
clips, the board had gold tabs I clipped onto

2. Then placed a single drop of DI water onto the exposed trace

3. Had the operators and inspectors look at a magnified view of this =
[placed all this under our Mantis]

4. Then...as they were watching this happen, well actually nothing was =
happening at the time, I asked them to very lightly touch the drop of =
water with the tip of their finger...........wow........the activity in =
that little drop was amazing.

5. Then I explained to them the contaminates, oils, etc from just their =
fingertip acted as the catalyst to this reaction they witnessed.

This drove home the importance of proper handling of bare boards to =
avoid contamination.

Franklin

------=_NextPart_000_001A_01BF9009.6FAA4B40
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>I used the battery and leads to a bare =
board to=20
show the effects of handling contamination.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Works about the same as the other=20
methods</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Using a bare board without solder mask =
and tin/lead=20
reflowed&nbsp;circuits I:</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>1. Connected a battery to two circuits =
using a 9=20
volt and alligator clips, the board had gold tabs I clipped =
onto</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>2. Then placed a single drop of DI =
water onto the=20
exposed trace</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>3. Had the operators and inspectors =
look at a=20
magnified view of this [placed all this under our Mantis]</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>4. Then...as they were watching this =
happen, well=20
actually nothing was happening at the time, I asked them to very lightly =
touch=20
the drop of water with the tip of their finger...........wow........the =
activity=20
in that little drop was amazing.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>5. Then I explained to them the =
contaminates, oils,=20
etc from just their fingertip acted as the catalyst to this reaction =
they=20
witnessed.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>This drove home the importance of =
proper handling=20
of bare boards to avoid contamination.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Franklin</FONT></DIV></BODY></HTML>

------=_NextPart_000_001A_01BF9009.6FAA4B40--

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Date:         Fri, 17 Mar 2000 10:12:15 -0800
Reply-To:     "[log in to unmask]" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Scott Rebman <[log in to unmask]>
Organization: PECO Mfg.
Subject:      Re: Base Material - Shortage?
X-To:         Ed Cosper <[log in to unmask]>

I know the lead time on some components, microprocessors, switches, etc. have increased.

-----Original Message-----
From:   Ed Cosper [SMTP:[log in to unmask]]
Sent:   Friday, March 17, 2000 9:57 AM
To:     [log in to unmask]
Subject:        Re: [TN] Base Material - Shortage?

Roland,

I guess I would have to ask what do you mean by more complex base materials?
I am currently unaware of any
Issues with extended lead time with respect to FR4 or Polyimide type
materials. I will check with purchasing to see
If they have heard anything but so far this is news to me.

Ed Cosper
ABC
Vestal NY

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Roland Jaquet
Sent: Friday, March 17, 2000 12:26 PM
To: [log in to unmask]
Subject: [TN] Base Material - Shortage?

Dear Technetters,

I writing here on the behalf of several concerned parties, including some
European OEMs, CEMs and PCB Manufacturers.

Some European manufacturers are worrying about Base Material Shortage, by
shortage it is understood extended delivery Lead-Time.
Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
some more complex Base Material, lead time can run to 14 weeks in some
particular instance.

Do you Technetters from all over the world and from the USA, are witnessing
such increase in delivery time?

Are worrying about it?
Some of you are considering shutting off the plant for some days like some
are considering doing in Europe if it doesn't improve?
Would you comment on your concerns ?
Is there any Base Material Manufacturers here who could give us the status
for their companies?

Please do not over-react to this posting and place big orders as this would
only cause the situation to get worst for most likely no real reason.
PLEASE no "Snow-Ball" effect.

Thank you

Very Best Regards
Roland
Info-Elec Ltd.
Golden Eyes? -  Live and Let Buy...  www.PCB007.com
Providing Global e-Business Solutions For The PCB Industry
Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
+41-79-203-3723
_______________________________________________________________________

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Date:         Fri, 17 Mar 2000 10:16:29 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Chuck Brummer <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Chuck Brummer <[log in to unmask]>
Organization: acuson
Subject:      Re: Base Material - Shortage?
X-To:         Roland Jaquet <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Jaquet,

I had a conversation with a stock advisor on the golf course last week.  He told me
that there is a world wide shortage of woven glass.  This is because the glass is all
being used in fiber optic lines for DSL.  He said it was the hottest thing and this was
the place to put your money.
First thing I thought was when there would be a prepreg shortage.

Obviously second hand info. from outside our industry.  Just passing along what I
heard.

Chuck Brummer
Acuson

Roland Jaquet wrote:

> Dear Technetters,
>
> I writing here on the behalf of several concerned parties, including some
> European OEMs, CEMs and PCB Manufacturers.
>
> Some European manufacturers are worrying about Base Material Shortage, by
> shortage it is understood extended delivery Lead-Time.
> Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
> some more complex Base Material, lead time can run to 14 weeks in some
> particular instance.
>
> Do you Technetters from all over the world and from the USA, are witnessing
> such increase in delivery time?
>
> Are worrying about it?
> Some of you are considering shutting off the plant for some days like some
> are considering doing in Europe if it doesn't improve?
> Would you comment on your concerns ?
> Is there any Base Material Manufacturers here who could give us the status
> for their companies?
>
> Please do not over-react to this posting and place big orders as this would
> only cause the situation to get worst for most likely no real reason.
> PLEASE no "Snow-Ball" effect.
>
> Thank you
>
> Very Best Regards
> Roland
> Info-Elec Ltd.
> Golden Eyes? -  Live and Let Buy...  www.PCB007.com
> Providing Global e-Business Solutions For The PCB Industry
> Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
> +41-79-203-3723
> _______________________________________________________________________
>
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> information.
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Date:         Fri, 17 Mar 2000 10:21:39 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              J G <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         J G <[log in to unmask]>
Subject:      Re: Oven Profile Recommendations?
X-To:         Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello Rick,

My experience(little that there is) is that this is
achieveable, providing that your paste has a large
process window. Paste technology has evolved to more
of a "bell curve" type of profile plot. In the past,
soak time and temp was much more critical. Now, you
can get away with more. Hope I've helped.

jg

--- Rick Thompson <[log in to unmask]>
wrote:
> I've inherited a system of maintaining oven profiles
> where each assembly was
> given it's own profile.  While this may have been
> more appropriate with IR,
> I don't think that current convection ovens require
> this many.  I'm
> intending to try and reduce our profiles to 6 or so
> that can cover the range
> of products we run.   Is this a practical approach?
> I believe it is, but
> would appreciate any comments.  I'd also like to get
> feedback on systems
> that are currently being used.  How are you
> categorizing your profiles
> (mass, board size, etc.)?
>
> Thanks.
>
>
> Rick Thompson
> Ventura Electronics Assembly
> 2665A Park Center Dr.
> Simi Valley, CA 93065
>
> +1 (805) 584-9858 voice
> +1 (805) 584-1529 fax
> [log in to unmask]
>
>
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__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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Date:         Fri, 17 Mar 2000 12:27:50 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Tim Devaul <[log in to unmask]>
Subject:      Wire wraps
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1; name="MEMO 03/17/00 12:31:50"
Content-Transfer-Encoding: quoted-printable

    Hi everyone, I am confused! I am preparing to teach a 610 class (re=
v. B) and I came across a problem dealing with wire wraps.
       Just below figure 3-49 on page 40, item B states that "minimum w=
rap for round posts has less than 180 degrees of contact between the wi=
res and the terminal". This is listed as acceptable for class 1 and  2.=
 However, under figure 3-52 on page 41 it=20
states minimum wrap contacts the terminal 180 degrees, or 90 degrees (i=
f mechanically secured).=20
       My question is; is it acceptable for class 2 to have a wrap less=
 than 180 degrees on a round post or not? Thanks in advance for your he=
lp!
        =20
Tim DeVaul
Total Quality Training and Audit Supervisor
Philips Broadband Networks, Inc.
100 Fairgrounds Dr.
Manlius, New York 13104
Tel: (315) 682-9105 Ext. 2403
Fax: (315)682-9006
Email: [log in to unmask]
=

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Date:         Fri, 17 Mar 2000 13:35:11 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "CSS International Corp." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "CSS International Corp." <[log in to unmask]>
Subject:      Re: Base Material - Shortage?
X-To:         Roland Jaquet <[log in to unmask]>
In-Reply-To:  <024a01bf9036$04a1a780$31550fc3@hp620>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

We have been witnessing the glass yar shortage in the glass fabric
manufacturing.  The shortage is mostly in the G75 yarn which is the base
material for producing the 7628 glass fabric.

The price of the yarn has been increased since late last year and the in
turn the glass fabric as well.

We expect to have some shortage of the rigid CCL.

There are few CCL makers who are able to cope with this type of shortages
but the producers without vertical intergration will have some problems in
the coming months.

If you want more details, you can contact us.


Best Regards,
One Kyu Son




At 06:26 PM 3/17/00, you wrote:
>Dear Technetters,
>
>I writing here on the behalf of several concerned parties, including some
>European OEMs, CEMs and PCB Manufacturers.
>
>Some European manufacturers are worrying about Base Material Shortage, by
>shortage it is understood extended delivery Lead-Time.
>Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
>some more complex Base Material, lead time can run to 14 weeks in some
>particular instance.
>
>Do you Technetters from all over the world and from the USA, are witnessing
>such increase in delivery time?
>
>Are worrying about it?
>Some of you are considering shutting off the plant for some days like some
>are considering doing in Europe if it doesn't improve?
>Would you comment on your concerns ?
>Is there any Base Material Manufacturers here who could give us the status
>for their companies?
>
>Please do not over-react to this posting and place big orders as this would
>only cause the situation to get worst for most likely no real reason.
>PLEASE no "Snow-Ball" effect.
>
>Thank you
>
>Very Best Regards
>Roland
>Info-Elec Ltd.
>Golden Eyes? -  Live and Let Buy...  www.PCB007.com
>Providing Global e-Business Solutions For The PCB Industry
>Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
>+41-79-203-3723
>_______________________________________________________________________
>
>##############################################################
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following text in
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>information.
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>847-509-9700 ext.5315
>##############################################################
>


CSS International Corp.
460 Bergen Boulevard, Suite 209
Palisades Park, NJ 07650  USA
Telephone:    1-201-461-7205 ext. 11 (USA)
                      82-(0)2-853-8810 (Korea)
Facsimile:      1-201-461-6374 (USA)
                      82-(0)2-853-8855 (Korea)
Cellular:         1-201-615-5669 (USA)
                      82-(0)11-523-8810 (Korea)
E-Mail:           [log in to unmask]
                      [log in to unmask] (Personal)

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Date:         Fri, 17 Mar 2000 13:36:43 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jeff Hempton <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jeff Hempton <[log in to unmask]>
Subject:      Nail-Head Pin Soldering
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

     I am not sure if my response is what you were looking for, but here it
     is:

     We are currently using a very effective product we helped to develop
     from WECO (ph:514-694-9136), a Canadian connector company, it is an
     in-line nail-head surface mount connector, excellent solderability,
     self-centering, superb strength in the field, auto-placeable. If you
     would like process info, contact me directly.

     Jeff Hempton
     Sr. Surface Mount Eng'r
     UT Electronic Controls
     [log in to unmask]


______________________________ Forward Header __________________________________
Subject: [TN] Nail-Head Pin Soldering
Author:  Dave Kell <[log in to unmask]> at Internet
Date:    03/17/2000 9:30 AM


I recieved a response to my question concerning soldering nailhead pins.
However, I mistakedly deleted the response.  I've checked with the network
people and it would take an act of GOD to retrieve.  I've also checked TechNet
archives and it does not exist.  Apparently, the response was sent to my
personal mailbox.

Can the person or persons please resent their answer?

Thanks, I owe you a cup of cybercoffee.

Regards,
Dave Kell

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Date:         Fri, 17 Mar 2000 13:53:24 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         To My E-Mail Address <[log in to unmask]>
Subject:      Re: HELP!! Press-fit connector!
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Steve,

One of our customers they had similar problem with press-fit connector.   I
don't think it was right angle though.

Anyway they asked us to prepare a backing plate (in this case we drilled a
0.125" mat'l with a bit larger holes than finished brd holes) that they can
use it as support under the brd.  You can have more thickness by stacking
such plates to create clearance for components.  And after that they used a
hand press to install the connector.  They used metal plate over the
connector to evently distribute the pressure.

Hope this helps.

Rush
Accurate Engg
818-768-3919

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Date:         Fri, 17 Mar 2000 12:12:57 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Impedance Testing
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

I'm struggling a bit with IPC-TM-650 Method 2.5.5.7. The test requires
you to take a measured mean voltage value but does not indicate how many
measurements should be taken. Also, is IPC going to change/revise this
test method to reflect newer test technology/methodology? I'm waiting on
a recent report published by INTEL that addresses a different technique
than what is in TM-650 and would be happy to pass this on to those
interested.
Any info appreciated.
Rick Howieson
General Technology

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Date:         Fri, 17 Mar 2000 13:32:04 -0500
Reply-To:     Jim Gleason <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jim Gleason <[log in to unmask]>
Organization: GSC
Subject:      Re: HELP!! Press-fit connector!
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

----- Original Message -----
From: To My E-Mail Address <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 17, 2000 1:53 PM
Subject: Re: [TN] HELP!! Press-fit connector!


> Steve,
>
> One of our customers they had similar problem with press-fit connector.
I
> don't think it was right angle though.
>
> Anyway they asked us to prepare a backing plate (in this case we drilled a
> 0.125" mat'l with a bit larger holes than finished brd holes) that they
can
> use it as support under the brd.  You can have more thickness by stacking
> such plates to create clearance for components.  And after that they used
a
> hand press to install the connector.  They used metal plate over the
> connector to evently distribute the pressure.
>
> Hope this helps.
>
> Rush
> Accurate Engg
> 818-768-3919
>
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Date:         Fri, 17 Mar 2000 13:32:43 -0500
Reply-To:     Jim Gleason <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jim Gleason <[log in to unmask]>
Organization: GSC
Subject:      Re: HELP!! Press-fit connector!
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Give me a buzz at 972-494-1911. We've done plates for quite a few people.

Jim Gleason

----- Original Message -----
From: To My E-Mail Address <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 17, 2000 1:53 PM
Subject: Re: [TN] HELP!! Press-fit connector!


> Steve,
>
> One of our customers they had similar problem with press-fit connector.
I
> don't think it was right angle though.
>
> Anyway they asked us to prepare a backing plate (in this case we drilled a
> 0.125" mat'l with a bit larger holes than finished brd holes) that they
can
> use it as support under the brd.  You can have more thickness by stacking
> such plates to create clearance for components.  And after that they used
a
> hand press to install the connector.  They used metal plate over the
> connector to evently distribute the pressure.
>
> Hope this helps.
>
> Rush
> Accurate Engg
> 818-768-3919
>
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Date:         Fri, 17 Mar 2000 14:25:45 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Base Material - Shortage?
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In a message dated 03/17/2000 11:30:01 AM Central Standard Time,
[log in to unmask] writes:

<< Dear Technetters,

 I writing here on the behalf of several concerned parties, including some
 European OEMs, CEMs and PCB Manufacturers.

 Some European manufacturers are worrying about Base Material Shortage, by
 shortage it is understood extended delivery Lead-Time.
 Some have seen extended delivery Lead-Time increased by 2 or 4 weeks, on
 some more complex Base Material, lead time can run to 14 weeks in some
 particular instance.

 Do you Technetters from all over the world and from the USA, are witnessing
 such increase in delivery time?

 Are worrying about it?
 Some of you are considering shutting off the plant for some days like some
 are considering doing in Europe if it doesn't improve?
 Would you comment on your concerns ?
 Is there any Base Material Manufacturers here who could give us the status
 for their companies?

 Please do not over-react to this posting and place big orders as this would
 only cause the situation to get worst for most likely no real reason.
 PLEASE no "Snow-Ball" effect.

 Thank you

 Very Best Regards
 Roland
 Info-Elec Ltd.
 Golden Eyes? -  Live and Let Buy...  www.PCB007.com
 Providing Global e-Business Solutions For The PCB Industry
 Roland Jaquet - Tel. +41-22-880-0405   -   Fax. +41-22-880-0409   -   Cell
 +41-79-203-3723 >>

Roland,

Below I've pasted an article I found on the internet about the glass fiber
industry. It is somewhat dated though (1996). But from reading the article,
there was quite a shortage back then, and according to the article many glass
companies (Owens Corning, PPG, etc.) were working hard and opening new plants
to increase capacity.
Surely, it wouldn't take 4-years to ramp-up to meet demand would it?...or
perhaps todays demand was underestimated...

-Steve Gregory-



MARKET FORECAST: GLASS FIBER INDUSTRY SURGES FORWARD

Demand Outstrips Supply as Glassmakers Try to Catch Up Joined at the hip to
the economy, the glass fibers industry is surging again. Used in applications
ranging from satellite parabolic antennas to household insulation, the demand
for glass fibers is so strong it exceeds supply. Producers are pushing hard
to increase capacity. They expect supply pressures to ease late in 1996, but
for the long term, they hope to achieve balance in supply and demand.
Globally, the industry had a record year in 1995. Sales reached $4.3 billion,
up 9% from $3.9 billion in 1994. That increase is largely due to burgeoning
markets in the Pacific Rim and South America, with the double-digit growth in
developing countries. The US market grew a more modest, but healthy 5.5%,
from 1.04billion lb in 1994 to 1.1 billion lb in 1995. The previous year
showed record growth, with a 4% increase to 1.04 billion lb in1994. Since
1990, US glass fiber production has grown by more than 50%, from 706 million
lb/yr in 1990. In the past two years, there was extraordinary demand in all
major markets. The strength of the marine market caught glassmakers by
surprise. It had previously dropped 50% from the 1980s. The automotive,
trucking, construction and anticorrosion markets all benefited from the
strong US economy in 1994.

* SUPPLY SHORTAGES In fact, demand was so high it outstripped supply. Last
year's growth would have been higher had it not been for supply shortages. In
1994 and 1995, glassmakers worked flat out to meet demand. The Composites
Institute (New York, NY) notes that growth of composites will be limited due
to glass fiber shortages. Composite use in 1995 was almost 3180 billion lb,
up 4.4% over 1994. The institute predicts 2.7% growth in 1996, to more than
3260 billion lb.

* EASING SHORTAGES The three major glassmakers are adding capacity:
Owens-Corning (Corning, NY) is adding 682 million lb/yr at its various plants
around the world between now and 1998. Vetrotex CertainTeed (Valley Forge,
PA) will increase glass fiber capacity20% by late 1996. The company is
rebuilding one furnace out of five at its Witchita Falls (TX) plant. PPG has
added a new facility in Chester (SC) with an investment of $50 million.
Initial capacity will be 60 million lb/yr and it will add capacity as needed.
The company points out that this is the first new plant that any major
producer has built in North America in the past 15 years. PPG also has a
facility in Shelby (NC) that is running at maximum capacity of 400 million
lb/yr. Increasing capacity to catch up with supply demands is standard in an
industry that is so dependent upon the general economy. There is always a
long lead time in production and spending decisions must be carefully
targeted since costs are high for increasing capacity. No glassmaker wants to
add capacity, only to see the market crash. Leveling the fluctuations is a
goal for Owens-Corning. The company hopes to end the up-and-down process of
increasing capacity following price increases. It is increasing capacity
through product rationalization and manufacturing simplification. For
example, the Owens-Corning plant in Jackson (TN) is now streamlined. The
plant produces only one product -- wet chopped strands -- which once were
made in three facilities. The company is also aligning itself with growth
markets and focusing on creating a strong global supply network. Through
moves like these, Owens-Corning hopes take some of the cyclicity out of its
business. Presently, it is producing 220 million more pounds than in 1994.
Its capital expenditures totaled $200 million in 1994and 1995, and it plans
an additional $105 million.

US GLASS FIBER DEMAND AND GROWTH PROJECTIONS (lb/year)
1990 706 million
1994 1.04 billion
1995 1.1 billion
1996 1.14 billion
1997 1.19 billion
1998 1.24 billion
1999 1.29 billion
2000 1.34 billion

* PREDICTIONS FOR GROWTH Efforts to manage the cycles are prudent. Still, the
glass fibers industry will remain closely tied to the economy. As such, there
is always the risk of a downturn in the future. Given that possibility, US
glass fiber production is expected to increase4%/yr over the next five years
on an average annual basis. In three primary areas of the glass fibers
market, growth expectations hover around 4%. In the electrical/electronic
segment, growth is expected at 3.5%/yr through 2000. A large portion of this
business is in printed circuit boards, which is shows steady but slow growth.
Fiber optics shows high growth, in double digits, with rates as high as 20%
to 30% in certain regions. Other uses include telecommunications drop wires
and satellite antennas. In transportation, look for growth rates of 5%/yr
through 2000. There is tremendous growth potential in this segment as
composites become more accepted. A prime advantage is their ability to
consolidate parts and simplify manufacturing. Owens-Corning points to the
superplug and radiator support in the Ford Taurus, which previously needed 20
metal parts made at 20 workstations. Now one composite part is snapped into
place, offering weight savings and simplified manufacturing along with a
reduction in labor and equipment. CertainTeed highlights a recent success at
the Composite Institute's Expo: A big prizewinner was a refrigerated railcar
molded with fiber-reinforced plastic. This is an application that didn't
exist previously. Other applications include helicopter blades and armored
vehicles and tanks. In a third major area, construction, 4% growth rates are
expected through 2000. Infrastructure applications worldwide provide the
highest growth in replacing existing concrete and steel. Building uses
include tubs, shower stalls and roofing, and non building applications
include utility poles, transmission towers, and piping.

* GLOBAL OUTLOOK The worldwide picture for glass fibers is strong. Global
demand was 3.3 billion lb in 1995, and growth rates should average 5%/yr
through 2000. In Western Europe, where close to a billion lb of glass fibers
were sold in 1995, growth is expected at 5.5% over the next five years. In
Eastern Europe, including the former Soviet Union, demand for glass fibers
reached 300million lb in 1995 but, at 3%/yr, the outlook is less optimistic
because of the political situation. In the Pacific Rim, where 800 million lb
were sold in 1995,growth could exceed 10% over the next five years, not
including Japan. Representing about half the Pacific Rim, Japan's use may
grow a modest 2%/yr. Predicted growth in Korea may be 8% to 10%.In Asia and
in South America, new markets have opened up. Developing countries are
becoming more affluent and want utilities, roads, bridges and other
infrastructure. In certain countries, rates could jump as high as 15% to 20%.
Leap frogging is apparent in these developing areas where end users choose
composites for first-time builds, thereby skipping metals altogether. In
telecommunications, there is leapfrogging over copper, straight to
fiber-optic filaments.

* PRICE INCREASES: 1996 Glass fiber prices are returning to levels reached
during the1980s. Prices had peaked in 1988 and 1989, during the last
highpoint in demand. During the early 1990s, prices eroded when global supply
exceeded demand. In 1995, following the demand recovery, the average price
returned almost to 1988-1989 levels. On average, reinforcements cost $1/lb.
Glassmakers expect more increases, but at a slower rate in 1996 than in
1994-1995.

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Date:         Fri, 17 Mar 2000 11:32:47 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Perkins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Perkins <[log in to unmask]>
Subject:      double sided reflow problems
MIME-Version: 1.0
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Hi Technetters

        Recently on heavy double reflow boards we have had good reflow on
the first side but when we flip over the integrity of the solder joint which
is now on the bottom has been compromised after the second pass.  The
temperature in the oven is only slightly hotter (peak temperatures around
220C on both sides) to compensate for the added component load. On the
bottom however it seems like the heaver qfp's look like they are trying to
pull away, looking like poor wetting,  leaving a hallow or indentation on
side of the lead or back on the heal fillet.
The quick fix is to add flux to the bottom before reflowing again, but this
is time consuming. This may also require gluing of all these parts to hold
them in place, which is even more time consuming.
Could the answer be to increase the stencil thickness from a 4-mil to a
6-mil to add paste to the board to increase the surface tension helping the
board  hold the qfp's better?
Is this entirely an oven reflow problem?
Does adding flux increase quality all around, or is this a non value added
process?
Does anyone else have experience with boards being run though for a second
pass without flux?


Bob Perkins
Automation Technician/Manufacturing Engineer
[log in to unmask]

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Date:         Fri, 17 Mar 2000 14:54:26 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Oven Profile Recommendations?
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Hi Rick,
Determining and maintaining reflow oven profiles for each assembly is a good
idea regardless of the the reflow method used (excepting vapor phase, of
course). While the heat transfer has improved with the 'Convection' ovens vs.
the 'IR' ovens, the size and thermal masses of components have gotten more
varied.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Fri, 17 Mar 2000 14:59:06 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Meschter, Stephan J" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Meschter, Stephan J" <[log in to unmask]>
Subject:      Re:
X-To:         Bill Decray <[log in to unmask]>
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Bill
Be careful that the tin oxides are not electrically conductive. If there is
vibration present you can have a
build up of tin oxide in the interface. AMP has done a fair amount of work
in this area.
Good luck.
Steph

Stephan Meschter               [log in to unmask]
Lockheed Martin Control Systems  Phone  :(607)770-2332
600 Main Street, MD R52F         FAX    :(607)770-2056
Johnson City, NY 13790-1888      MARCALL: 8 * 255-2332


> ----------
> From:         Bill Decray[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Bill Decray
> Sent:         Thursday, March 16, 2000 1:29 PM
> To:   [log in to unmask]
> Subject:      [TN]
>
> CAN ANYONE GIVE ME SOME INFO ON USING WHITE-TIN IN PLACE OF GOLD FOR
> CONNECTOR FINGERS.
> MY END USER AS CONCERNS ABOUT THE DURABILITY OF THE TIN FINISH SINCE THEY
> ARE PULLING THE CARDS IN AND OUT OF PCI AND MEMORY SLOTS
>
> William W. DeCray III
> Waytec Electronics Corp
> Sales Engineer
> PHONE:(804) 237-6391 ext 115
> FAX:    (804) 237-1324
> E-mail:<[log in to unmask]>
> Web <http://www.waytec.com>
> FTP <ftp://ftp.waytec.com>
>
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Date:         Fri, 17 Mar 2000 15:32:30 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Kell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Kell <[log in to unmask]>
Subject:      Organic Contamination
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Does anyone have experience with IPC-TM-650 method 2.3.38?  This test is =
specified as a manual way to detect surface organics.  Our first attempt =
found that even the untested solution left a visual residue.  The =
acetonitrile is the grade specified, but we are unsure of what is =
expected.  We do not have easy access to analysis equipment to determine =
the source of the residue.

Dave Kell

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Date:         Fri, 17 Mar 2000 16:42:30 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lee Whiteman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lee Whiteman <[log in to unmask]>
Subject:      Re: Oven Profile Recommendations?
X-To:         J G <[log in to unmask]>, [log in to unmask]
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I agree with Werner Engelmaier.

I also suggest that you take into account the soldering atmosphere. For
example, if your equipment can operate with nitrogen or air, you may wish to
document the processing atmosphere.

My recommendation is that you run in nitrogen, whether or not you use IR
Reflow or Convection. It will yield cleaner solder joints, with less visible
residues, and improve solderability.

This is especially true when running Pb-Free solders.

Lee Whiteman
Senior Manufacturing Engineer
ACI / EMPF
Telephone: (610) 362-1200; Ext. 208
FAX: (610) 362-1290
E-Mail: [log in to unmask]

 -----Original Message-----
 From: TechNet [mailto:[log in to unmask]]On Behalf Of Werner Engelmaier
 Sent: Friday, March 17, 2000 2:54 PM
 To: [log in to unmask]
 Subject: Re: [TN] Oven Profile Recommendations?


 Hi Rick,
 Determining and maintaining reflow oven profiles for each assembly
 is a good
 idea regardless of the reflow method used (excepting vapor phase, of
 course). While the heat transfer has improved with the
 'Convection' ovens vs.
 the 'IR' ovens, the size and thermal masses of components have gotten more
 varied.

 Werner Engelmaier
 Engelmaier Associates, L.C.
 Electronic Packaging, Interconnection and Reliability Consulting
 7 Jasmine Run
 Ormond Beach, FL  32174  USA
 Phone: 904-437-8747, Fax: 904-437-8737
 E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Fri, 17 Mar 2000 16:58:41 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Dube <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Dube <[log in to unmask]>
Subject:      Re: Impedance Testing
X-To:         "Howieson, Rick" <[log in to unmask]>
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Certianly am interested in the INTEL report please keep me posted.

Bob Dube

ES&D

-----Original Message-----
From: Howieson, Rick <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Friday, March 17, 2000 2:21 PM
Subject: [TN] Impedance Testing


>I'm struggling a bit with IPC-TM-650 Method 2.5.5.7. The test requires
>you to take a measured mean voltage value but does not indicate how many
>measurements should be taken. Also, is IPC going to change/revise this
>test method to reflect newer test technology/methodology? I'm waiting on
>a recent report published by INTEL that addresses a different technique
>than what is in TM-650 and would be happy to pass this on to those
>interested.
>Any info appreciated.
>Rick Howieson
>General Technology
>
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Date:         Fri, 17 Mar 2000 17:07:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
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Subject:      Bendflex replacement???
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I have been advised that we can no longer obtain bendflex material. Does
anyone know what has replaced this product?  Is it still available from
other sources?

Ed Cosper

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Date:         Fri, 17 Mar 2000 14:29:41 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Tuan Le <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tuan Le <[log in to unmask]>
Subject:      Re: Impedance Testing
X-To:         Bob Dube <[log in to unmask]>
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This message is in MIME format. Since your mail reader does not understand
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Please send me the Intel report as well.

Thank you

-----Original Message-----
From: Bob Dube [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 1:59 PM
To: [log in to unmask]
Subject: Re: [TN] Impedance Testing


Certianly am interested in the INTEL report please keep me posted.

Bob Dube

ES&D

-----Original Message-----
From: Howieson, Rick <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Friday, March 17, 2000 2:21 PM
Subject: [TN] Impedance Testing


>I'm struggling a bit with IPC-TM-650 Method 2.5.5.7. The test requires
>you to take a measured mean voltage value but does not indicate how many
>measurements should be taken. Also, is IPC going to change/revise this
>test method to reflect newer test technology/methodology? I'm waiting on
>a recent report published by INTEL that addresses a different technique
>than what is in TM-650 and would be happy to pass this on to those
>interested.
>Any info appreciated.
>Rick Howieson
>General Technology
>
>##############################################################
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<P><FONT SIZE=3D2>Please send me the Intel report as well.</FONT>
</P>

<P><FONT SIZE=3D2>Thank you</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Bob Dube [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Friday, March 17, 2000 1:59 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [TN] Impedance Testing</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Certianly am interested in the INTEL report please =
keep me posted.</FONT>
</P>

<P><FONT SIZE=3D2>Bob Dube</FONT>
</P>

<P><FONT SIZE=3D2>ES&amp;D</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Howieson, Rick =
&lt;[log in to unmask]&gt;</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask] &lt;[log in to unmask]&gt;</FONT>
<BR><FONT SIZE=3D2>Date: Friday, March 17, 2000 2:21 PM</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Impedance Testing</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>&gt;I'm struggling a bit with IPC-TM-650 Method =
2.5.5.7. The test requires</FONT>
<BR><FONT SIZE=3D2>&gt;you to take a measured mean voltage value but =
does not indicate how many</FONT>
<BR><FONT SIZE=3D2>&gt;measurements should be taken. Also, is IPC going =
to change/revise this</FONT>
<BR><FONT SIZE=3D2>&gt;test method to reflect newer test =
technology/methodology? I'm waiting on</FONT>
<BR><FONT SIZE=3D2>&gt;a recent report published by INTEL that =
addresses a different technique</FONT>
<BR><FONT SIZE=3D2>&gt;than what is in TM-650 and would be happy to =
pass this on to those</FONT>
<BR><FONT SIZE=3D2>&gt;interested.</FONT>
<BR><FONT SIZE=3D2>&gt;Any info appreciated.</FONT>
<BR><FONT SIZE=3D2>&gt;Rick Howieson</FONT>
<BR><FONT SIZE=3D2>&gt;General Technology</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT =
SIZE=3D2>&gt;###########################################################=
###</FONT>
<BR><FONT SIZE=3D2>&gt;TechNet Mail List provided as a free service by =
IPC using LISTSERV 1.8c</FONT>
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SIZE=3D2>&gt;###########################################################=
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[log in to unmask] with following</FONT>
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&lt;your full name&gt;</FONT>
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TECHNET</FONT>
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###</FONT>
<BR><FONT SIZE=3D2>&gt;Please visit IPC web site (<A =
HREF=3D"http://www.ipc.org/html/forum.htm" =
TARGET=3D"_blank">http://www.ipc.org/html/forum.htm</A>) for</FONT>
<BR><FONT SIZE=3D2>additional</FONT>
<BR><FONT SIZE=3D2>&gt;information.</FONT>
<BR><FONT SIZE=3D2>&gt;If you need assistance - contact Keach Sasamori =
at [log in to unmask] or</FONT>
<BR><FONT SIZE=3D2>&gt;847-509-9700 ext.5315</FONT>
<BR><FONT =
SIZE=3D2>&gt;###########################################################=
###</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
</P>

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Date:         Fri, 17 Mar 2000 17:07:28 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Michael Sanders <[log in to unmask]>
Subject:      Re: Impedance Testing
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I would also appreciate the Intel report. Thanks.
                    Michael Sanders
                    Process Engineer/SMTC
                    [log in to unmask]


                                                                       =
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                    Tuan Le                                            =
                   =20
                    <tle@KCAMERIC        To:     [log in to unmask]       =
                   =20
                    A.COM>               cc:                           =
                   =20
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e Testing          =20
                    TechNet                                            =
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                    <[log in to unmask]                                      =
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Please send me the Intel report as well.

Thank you

-----Original Message-----
From: Bob Dube [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 1:59 PM
To: [log in to unmask]
Subject: Re: [TN] Impedance Testing

Certianly am interested in the INTEL report please keep me posted.

Bob Dube

ES&D

-----Original Message-----
From: Howieson, Rick <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Friday, March 17, 2000 2:21 PM
Subject: [TN] Impedance Testing

>I'm struggling a bit with IPC-TM-650 Method 2.5.5.7. The test requires=

>you to take a measured mean voltage value but does not indicate how ma=
ny
>measurements should be taken. Also, is IPC going to change/revise this=

>test method to reflect newer test technology/methodology? I'm waiting =
on
>a recent report published by INTEL that addresses a different techniqu=
e
>than what is in TM-650 and would be happy to pass this on to those
>interested.
>Any info appreciated.
>Rick Howieson
>General Technology
>
>##############################################################
>TechNet Mail List provided as a free service by IPC using LISTSERV 1.8=
c
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>To subscribe/unsubscribe, send a message to [log in to unmask] with
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additional
>information.
>If you need assistance - contact Keach Sasamori at [log in to unmask] or
>847-509-9700 ext.5315
>##############################################################
>

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=

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=========================================================================
Date:         Sat, 18 Mar 2000 15:39:35 +0900
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Fujikura Ltd." <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Fujikura Ltd." <[log in to unmask]>
Subject:      Re: Bendflex replacement???
X-To:         Ed Cosper <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

The bendflex, as a registered trademark, has been gone, however, I am
just wondering we may choose possible material for use in "Bending
possible Flex PWB", my understanding is out of your point?

Toru Koizumi


>I have been advised that we can no longer obtain bendflex material.
Does
>anyone know what has replaced this product?  Is it still available from
>other sources?
>
>Ed Cosper
>

----
Fujikura Ltd.  [log in to unmask]

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Date:         Sat, 18 Mar 2000 10:34:22 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Organic Contamination
X-To:         Dave Kell <[log in to unmask]>
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Dave

Either it means you need a purer acetonitrile (or, to give it a better name to reflect its toxicity, methyl cyanide) or your dropper/slides have not been sufficiently pre-cleaned. Try and see whether there is a visible difference.

Brian

Dave Kell wrote:

> Does anyone have experience with IPC-TM-650 method 2.3.38?  This test is specified as a manual way to detect surface organics.  Our first attempt found that even the untested solution left a visual residue.  The acetonitrile is the grade specified, but we are unsure of what is expected.  We do not have easy access to analysis equipment to determine the source of the residue.
>
> Dave Kell
>
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Date:         Sat, 18 Mar 2000 11:26:19 -0000
Reply-To:     Michael Fenner <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Fenner <[log in to unmask]>
Organization: Bonding Services & Products
Subject:      Re: Tantalum capacitors
X-To:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

This body design is preferable to the previous which looked like two tailed tadpole and gave all
sorts of problems with bleed and very low joint strengths. If you can't solve the problem with
careful shaping of the glue shape prior to placing and placement pressure/pad design such that
the adhesive squidges into correct place (rather than out of it) then you could consider
striping non conductive adhesive between pads to make a dam bar and stand off. Alternative is to
dot insulating adhesive as well as conductive so that  on co curing component is held by both
adhesive types. This is usually OK for high G.


Mike

----- Original Message -----
From: Ingemar Hernefjord (EMW) <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 17, 2000 9:57 AM
Subject: [TN] Tantalum capacitors


>
> Now, about tantalum caps. Anyone out there using tantals with FLEXIBLE terminals? Old model,
you recognize that, is with a more or less straight and painted body, terminals silvered, tinned
or gold plated, most models for soldering. New since a number of years are those with
rectangular body, suitable for P-P, and with sort of flexible ribbon terminal that is bent 90
degrees under the body. Those having these are e.g. Kemet, Sprague, Matsuo, Tekelec, Siemens,
NEC, AVX/Kyocera to mention some.  OK, they are all excellent for soldering, but for silver
epoxy mounting a minor problem occurs: the epoxy wets, not only the terminal but also the body.
Then you loose some of the advantage with flexibility. You find a typical outline in IPC-SM-782
Subsection 8.4.
>
> Question: anyone that pick-and-place such creatures for silverepoxy technology? What terminal
finish do you order? And do you utilize the flexibel terminal?  How do you get a recommende
epoxy line (50-100um) as the component is heavy, do you use some kind of standoff? Anyone that
has centrifuged up to 5,000 G's? Anyone with experience from mounting such caps on
Arlene/Roger/Taconic with heavymetal backing?
>
> Normal FR4 indoor products with this cap are normally soldered and there are no obstacles. So,
we don't have a general problem, but lack some experience for epoxying in special applications.
>
> Also will come back later with discussion about ceramic caps, ferro/piezo effects, aging and
such things that has been up recently. Ousten, France, are you out there? Still working with the
RFceramic characterization project? Lost your e-mail adress.
>
> Ingemar Hernefjord
> Ericsson Microwave Systems

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Date:         Sat, 18 Mar 2000 09:31:10 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Strange email...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Good morning everybody!

Below, I've pasted a message that was waiting in my mailbox for me this
morning. It had a attachment with it (that I didn't open). Is anybody else
getting these? I know of a couple people that have, but I'm wondering if
everybody is? Looking at the email address, and the attachment has me
worried...also the comment in the message; "may be forged".

Just curious...

-Steve Gregory-

Subj:    Returned mail: Too many hops 305 (30 max): from <@pub
Date:   03/18/2000 4:43:00 AM Central Standard Time
From:   [log in to unmask] (Mail Delivery Subsystem)
To: [log in to unmask], [log in to unmask]

File:  Returned.mim (59131 bytes)
DL Time (37333 bps): < 1 minute

[This e-mail contains a MIME (Multipurpose Internet Mail Extensions) file.
The file was specially formatted to be sent over the Internet.  For more
information on opening the attached file, go to Keyword: MIME.]
--------------------
The original message was received at Sat, 18 Mar 2000 04:44:18 -0600 (CST)
from pop2.guangzhou.gd.cn [202.96.128.113] (may be forged)

   ----- The following addresses had permanent fatal errors -----
<[log in to unmask]>

   ----- Transcript of session follows -----
554 Too many hops 305 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
<[log in to unmask]>


----------------------- Headers --------------------------------
Return-Path: <>
Received: from  rly-yg02.mx.aol.com (rly-yg02.mail.aol.com [172.18.147.2]) by
air-yg05.mail.aol.com (v70.19) with ESMTP; Sat, 18 Mar 2000 05:43:00 -0500
Received: from  mail.ipc.org (mail.ipc.org [216.203.207.34]) by
rly-yg02.mx.aol.com (v70.20) with ESMTP; Sat, 18 Mar 2000 05:42:45 -0500
Received: from localhost (localhost)
    by mail.ipc.org (8.8.8+Sun/8.8.8) with internal id EAB27092;
    Sat, 18 Mar 2000 04:44:26 -0600 (CST)
Date: Sat, 18 Mar 2000 04:44:26 -0600 (CST)
From: Mail Delivery Subsystem <[log in to unmask]>
Message-Id: <[log in to unmask]>
To: <[log in to unmask]>
To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/report; report-type=delivery-status;
    boundary="EAB27092.953376266/mail.ipc.org"
Subject: Returned mail: Too many hops 305 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
<[log in to unmask]>
Auto-Submitted: auto-generated (failure)

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Date:         Sat, 18 Mar 2000 17:19:43 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Steve

Difficult to interpret, but somebody with the address
          gzgcec <[log in to unmask]>
made a number of postings to TechNet last autumn (or at least with a supposed date of
last autumn). Some of these did have attachments. I suggest you *may* have hit the
reply button and your contribution went to the list but also to the original sender.
Some of these guys put in false addresses to reduce spam and your reply has been
sitting on a Chinese server waiting to be delivered until finally it has decided that
delivery is not possible and it then sends you this nokandu message.

Alternatively, I see your e-mail address is c/o AOL. These guys are notorious for
losing and delaying messages. Only yesterday, I was correponding with another AOL
member who complained that a message I sent him in January arrived only yesterday. I
referred him to
http://www.aolsucks.org/
http://www.babeonhd.com/aol_sucks.html
both of which documents this, and many other types of problem unique to this ISP (there
are hundreds of other such sites, as well). When I first started on the Internet (1993,
I think), I used CompuServe which had similar problems. Now, don't get me wrong, I'm
not flaming AOL or those who use it but merely stating known problems.

Brian



"Stephen R. Gregory" wrote:

> Good morning everybody!
>
> Below, I've pasted a message that was waiting in my mailbox for me this
> morning. It had a attachment with it (that I didn't open). Is anybody else
> getting these? I know of a couple people that have, but I'm wondering if
> everybody is? Looking at the email address, and the attachment has me
> worried...also the comment in the message; "may be forged".
>
> Just curious...
>
> -Steve Gregory-
>
> Subj:    Returned mail: Too many hops 305 (30 max): from <@pub
> Date:   03/18/2000 4:43:00 AM Central Standard Time
> From:   [log in to unmask] (Mail Delivery Subsystem)
> To: [log in to unmask], [log in to unmask]
>
> File:  Returned.mim (59131 bytes)
> DL Time (37333 bps): < 1 minute
>
> [This e-mail contains a MIME (Multipurpose Internet Mail Extensions) file.
> The file was specially formatted to be sent over the Internet.  For more
> information on opening the attached file, go to Keyword: MIME.]
> --------------------
> The original message was received at Sat, 18 Mar 2000 04:44:18 -0600 (CST)
> from pop2.guangzhou.gd.cn [202.96.128.113] (may be forged)
>
>    ----- The following addresses had permanent fatal errors -----
> <[log in to unmask]>
>
>    ----- Transcript of session follows -----
> 554 Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
>
> ----------------------- Headers --------------------------------
> Return-Path: <>
> Received: from  rly-yg02.mx.aol.com (rly-yg02.mail.aol.com [172.18.147.2]) by
> air-yg05.mail.aol.com (v70.19) with ESMTP; Sat, 18 Mar 2000 05:43:00 -0500
> Received: from  mail.ipc.org (mail.ipc.org [216.203.207.34]) by
> rly-yg02.mx.aol.com (v70.20) with ESMTP; Sat, 18 Mar 2000 05:42:45 -0500
> Received: from localhost (localhost)
>     by mail.ipc.org (8.8.8+Sun/8.8.8) with internal id EAB27092;
>     Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> Date: Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> From: Mail Delivery Subsystem <[log in to unmask]>
> Message-Id: <[log in to unmask]>
> To: <[log in to unmask]>
> To: [log in to unmask]
> MIME-Version: 1.0
> Content-Type: multipart/report; report-type=delivery-status;
>     boundary="EAB27092.953376266/mail.ipc.org"
> Subject: Returned mail: Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
> Auto-Submitted: auto-generated (failure)
>
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Date:         Sat, 18 Mar 2000 11:04:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Steve:

You are on AOL, (as am I) and it is one of the more unfortnate Internet
Service Providers.   The message you got, and the attached file was created
by AOL, because if a message is too long, AOL truncates it, and turns the
remainder into an attached file in the .mim format.  I think, but am not
sure, that the .mim format may be uniquely owned and used by AOL, and that is
the tip off.

Rudy Sedlak
RD Chemical

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Date:         Sat, 18 Mar 2000 13:48:47 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

In a message dated 03/18/2000 9:14:15 AM Central Standard Time,
[log in to unmask] writes:

<< Steve

Difficult to interpret, but somebody with the address
gzgcec <[log in to unmask]> made a number of postings to TechNet
last autumn  [SNIP]

Alternatively, I see your e-mail address is c/o AOL. These guys are notorious
for losing and delaying messages. Only yesterday, I was correponding with
another AOL member who complained that a message I sent him in January
arrived only yesterday [SNIP]

 Brian >>

Hi Brian!

I'm not sure, but I don't think it's just a AOL thing, because Paul Klasek
had been getting them too and asked me about it last week...see his message
to me below. Are Paul and I the only ones getting this? Have any of you out
there got any of those messages? This is getting weird...

-Steve Gregory-

From: Paul Klasek
Sent: Wednesday, 15 March 2000 8:34
To: [log in to unmask]
Subject: FW: Returned mail: Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to <[log in to unmask]>


This is the thing which gives me creeps , note the addresses, 'm not opening
the attachments, help me to form some opinion about it .

This one came this morning, coming daily.
1
Are you getting them too ?
2
If not, should we contact Jack or Hugo ?
3
This billion nice note came this morning too .

thx         paul

-----Original Message-----
From: Mail Delivery Subsystem [mailto:[log in to unmask]]
Sent: Wednesday, 15 March 2000 7:50
To: [log in to unmask]; [log in to unmask]
Subject: Returned mail: Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to <[log in to unmask]>

The original message was received at Tue, 14 Mar 2000 14:50:05 -0600 (CST)
from pop.guangzhou.gd.cn [202.96.128.113]

   ----- The following addresses had permanent fatal errors -----
<[log in to unmask]>

   ----- Transcript of session follows -----
554 Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to<[log in to unmask]>

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Date:         Wed, 15 Mar 2000 10:01:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: ASSY & FAB: vias: To plug or not to plug
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Jeff,
Your problem is one that has not be addressed fully, and in any case will
have 'it depends' answers.
1) solder-filled vias are more reliable than unfilled vias, PROVIDED that the
fill is without voids; vias with solder fills with vods will be less reliable
because of the stress concentration created by the voids. HOWEVER, this is
only a real issue for severe use conditions like automotive and some military.
2) allowing vias to fill with liquid solder during the wave soldering process
has led to partial solder joint reflows and desturbed solder joints on the
top side--this is particularly to be avoided with BGAs.
This is not exactly a deluge, but my 7.3 cents (5 cents after inflation).

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Wed, 15 Mar 2000 11:44:01 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Dube <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Dube <[log in to unmask]>
Subject:      Ionic Contamnation
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

This is one for the board fabricators.

We are currently meeting an Ionic Cleanliness spec for 1 of our customers
set at 0.5 ug/Sq Cm on the finished cards. We are acheiving this using an
extra cleaning step. This is largely manual an fairly time consuming. We've
experimented with using dishwashers and although this has helped with
respect to labor intensity, it hasn't done much to improve cycle time.

Anybody had any experience utilizing conveyorized equipment or putting
improved cleaning in-line with existing processes (both HASL and Immersion
White Tin)?

Bob Dube

ES&D

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Date:         Wed, 15 Mar 2000 19:02:56 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Subject:      Re: Ionic Contamnation
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Bob

Will reply to you off-TechNet

Brian

Bob Dube wrote:

> This is one for the board fabricators.
>
> We are currently meeting an Ionic Cleanliness spec for 1 of our customers
> set at 0.5 ug/Sq Cm on the finished cards. We are acheiving this using an
> extra cleaning step. This is largely manual an fairly time consuming. We've
> experimented with using dishwashers and although this has helped with
> respect to labor intensity, it hasn't done much to improve cycle time.
>
> Anybody had any experience utilizing conveyorized equipment or putting
> improved cleaning in-line with existing processes (both HASL and Immersion
> White Tin)?
>
> Bob Dube
>
> ES&D
>
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Date:         Sun, 19 Mar 2000 09:11:16 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Andy Magee <[log in to unmask]>
Subject:      Bendflex
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Bendflex was always a tricky product to support. It was designed to fill
the narrow niche between flex and rigid board materials. It promised to
be a cheap and easy solution to achieving the features of rigid-flex
boards with a very simple one step process. While it did fulfill that
promise it had enough problems (like marginal solder resistance) to be
generally unattractive. It was outperformed by both ends of the
materials spectrum, so few wanted to venture into the middle with it.

At this point, if traditional rigid-flex is too costly, and the package
demands more conformance than thin rigid boards allow, I'd probably go
with a flex circuit locally stiffened with backers.

Andy Magee - Flex Guru
Senior Consultant, Bourton Group
(937) 435-3629
[log in to unmask]

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Date:         Sat, 18 Mar 2000 19:50:53 -0000
Reply-To:     Michael Fenner <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Fenner <[log in to unmask]>
Organization: Bonding Services & Products
Subject:      Re: Strange email...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Yep I get this stupid message instantly every time I post to Technet along with a couple of
other I am not in out of office and so on messages. The next day I get it again, but not the am
out of offices. I put it down to the listserver thing not being uptodate with a gone away
member. Its mildly annoying, but as I delete about 50% of the stuff on technet anyway its not
THAT annoying.

Ps I am not on AOL.

Mike
----- Original Message -----
From: Stephen R. Gregory <[log in to unmask]>
To: <[log in to unmask]>
Sent: Saturday, March 18, 2000 2:31 PM
Subject: [TN] Strange email...


> Good morning everybody!
>
> Below, I've pasted a message that was waiting in my mailbox for me this
> morning. It had a attachment with it (that I didn't open). Is anybody else
> getting these? I know of a couple people that have, but I'm wondering if
> everybody is? Looking at the email address, and the attachment has me
> worried...also the comment in the message; "may be forged".
>
> Just curious...
>
> -Steve Gregory-
>
> Subj:    Returned mail: Too many hops 305 (30 max): from <@pub
> Date:   03/18/2000 4:43:00 AM Central Standard Time
> From:   [log in to unmask] (Mail Delivery Subsystem)
> To: [log in to unmask], [log in to unmask]
>
> File:  Returned.mim (59131 bytes)
> DL Time (37333 bps): < 1 minute
>
> [This e-mail contains a MIME (Multipurpose Internet Mail Extensions) file.
> The file was specially formatted to be sent over the Internet.  For more
> information on opening the attached file, go to Keyword: MIME.]
> --------------------
> The original message was received at Sat, 18 Mar 2000 04:44:18 -0600 (CST)
> from pop2.guangzhou.gd.cn [202.96.128.113] (may be forged)
>
>    ----- The following addresses had permanent fatal errors -----
> <[log in to unmask]>
>
>    ----- Transcript of session follows -----
> 554 Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
>
>
> ----------------------- Headers --------------------------------
> Return-Path: <>
> Received: from  rly-yg02.mx.aol.com (rly-yg02.mail.aol.com [172.18.147.2]) by
> air-yg05.mail.aol.com (v70.19) with ESMTP; Sat, 18 Mar 2000 05:43:00 -0500
> Received: from  mail.ipc.org (mail.ipc.org [216.203.207.34]) by
> rly-yg02.mx.aol.com (v70.20) with ESMTP; Sat, 18 Mar 2000 05:42:45 -0500
> Received: from localhost (localhost)
>     by mail.ipc.org (8.8.8+Sun/8.8.8) with internal id EAB27092;
>     Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> Date: Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> From: Mail Delivery Subsystem <[log in to unmask]>
> Message-Id: <[log in to unmask]>
> To: <[log in to unmask]>
> To: [log in to unmask]
> MIME-Version: 1.0
> Content-Type: multipart/report; report-type=delivery-status;
>     boundary="EAB27092.953376266/mail.ipc.org"
> Subject: Returned mail: Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
> Auto-Submitted: auto-generated (failure)
>
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Date:         Mon, 20 Mar 2000 08:26:12 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Oven Profile Recommendations?
X-To:         Rick Thompson <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Rick
as few profiles as possible is desirable ; however indeed the sizing, mass
and shadowing on hot jets for example represents quite a challenge ;
remember when we first time introduced big electrolyte cans with small legs;
it took another 7'C to reflow them in shade (had actually to shift few
around for better jet flow).
in the end we've had to go much higher much faster before the things popped
.
That contravened max rise speed on other cer caps to make it interesting
................
no such a thing as category

cu         paul

-----Original Message-----
From: Rick Thompson [mailto:[log in to unmask]]
Sent: Saturday, 18 March 2000 5:06
To: [log in to unmask]
Subject: [TN] Oven Profile Recommendations?


I've inherited a system of maintaining oven profiles where each assembly was
given it's own profile.  While this may have been more appropriate with IR,
I don't think that current convection ovens require this many.  I'm
intending to try and reduce our profiles to 6 or so that can cover the range
of products we run.   Is this a practical approach?  I believe it is, but
would appreciate any comments.  I'd also like to get feedback on systems
that are currently being used.  How are you categorizing your profiles
(mass, board size, etc.)?

Thanks.


Rick Thompson
Ventura Electronics Assembly
2665A Park Center Dr.
Simi Valley, CA 93065

+1 (805) 584-9858 voice
+1 (805) 584-1529 fax
[log in to unmask]

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Date:         Mon, 20 Mar 2000 08:55:52 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         "[log in to unmask]" <[log in to unmask]>,
              "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Mike's just about closest ; and considering that address is "filtered" by
ipc server ;
there is a reason for it we don't know, and Hugo does ;
otherwise the filter would not be in place (Monday piece of deductive
logic), hey ?
Lets see if Keach 's got an opinion about it.
Can we get it off Keach, or do we have to live with this tao cyber ghost ?

pk

-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Sunday, 19 March 2000 5:49
To: [log in to unmask]
Subject: Re: [TN] Strange email...


In a message dated 03/18/2000 9:14:15 AM Central Standard Time,
[log in to unmask] writes:

<< Steve

Difficult to interpret, but somebody with the address
gzgcec <[log in to unmask]> made a number of postings to TechNet
last autumn  [SNIP]

Alternatively, I see your e-mail address is c/o AOL. These guys are
notorious
for losing and delaying messages. Only yesterday, I was correponding with
another AOL member who complained that a message I sent him in January
arrived only yesterday [SNIP]

 Brian >>

Hi Brian!

I'm not sure, but I don't think it's just a AOL thing, because Paul Klasek
had been getting them too and asked me about it last week...see his message
to me below. Are Paul and I the only ones getting this? Have any of you out
there got any of those messages? This is getting weird...

-Steve Gregory-

From: Paul Klasek
Sent: Wednesday, 15 March 2000 8:34
To: [log in to unmask]
Subject: FW: Returned mail: Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to <[log in to unmask]>


This is the thing which gives me creeps , note the addresses, 'm not opening
the attachments, help me to form some opinion about it .

This one came this morning, coming daily.
1
Are you getting them too ?
2
If not, should we contact Jack or Hugo ?
3
This billion nice note came this morning too .

thx         paul

-----Original Message-----
From: Mail Delivery Subsystem [mailto:[log in to unmask]]
Sent: Wednesday, 15 March 2000 7:50
To: [log in to unmask]; [log in to unmask]
Subject: Returned mail: Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to <[log in to unmask]>

The original message was received at Tue, 14 Mar 2000 14:50:05 -0600 (CST)
from pop.guangzhou.gd.cn [202.96.128.113]

   ----- The following addresses had permanent fatal errors -----
<[log in to unmask]>

   ----- Transcript of session follows -----
554 Too many hops 115 (30 max): from
<@public.guangzhou.gd.cn:[log in to unmask]> via pop.guangzhou.gd.cn,
to<[log in to unmask]>

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Date:         Wed, 15 Mar 2000 22:53:09 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Alloy 42 Leaded TSOPS
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

In a message dated 3/15/00 9:29:35, [log in to unmask] writes:
>Steve, couldI have your telephone # so that I could talk to you about our
>TSOP experiences?
Hi Ed,
After wetting all our appetites, it would be appropriate to share your
experiences with the TechNet.
Werner Engelmaier

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Date:         Wed, 15 Mar 2000 22:53:12 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: VOC legislation
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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In a message dated 3/15/00 10:07:16, [log in to unmask] writes:
>Al Gore did not make this statement.  I think you are referring to Dan
>Quayle's quote :
>If we do not succeed, then we run the risk of failure.
>-- Vice President Dan Quayle, to the Phoenix Republican Forum, 3/23/90
>(reported in Esquire, 8/92) Also reported by Reuters, 5/2/90
>Lets not make fun of our future President!
Hi Todd,
while I would not want Dan Quayle as my president, do you really want
somebody so self-delusional as to believe he invented the Internet? did you
see how Stephen Hawkings put Gore down during his White House visit?
Werner

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Date:         Wed, 15 Mar 2000 22:43:12 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: PTH Design For Reliability
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Werner:  What documents:

* Design Guidelines for Reliable Pin Through Hole Technology Printed Board Assemblies
* Pin Through Hole Design & Land Pattern Standard
* Guidelines for Accelerated Reliability Testing of Pin Through Hole Solder Attachments

Thank you

Dave Fish

Werner Engelmaier wrote:

> Hi Dave,
> I surely do not understand your question, and the 2 responses that you have
> received indicate to me that these people also did not understand what it is
> you need.
> Would you restate your query? I was heavily involved with 2 of these
> documents and somewhat with the third, so I should be able to help you.
> Werner Engelmaier
>
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Date:         Mon, 20 Mar 2000 13:48:16 +1200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Justin Braime <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Justin Braime <[log in to unmask]>
Subject:      MTBF
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0186_01BF9272.F1DDDF80"

This is a multi-part message in MIME format.

------=_NextPart_000_0186_01BF9272.F1DDDF80
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

What is the best method for calculating an MTBF figure for your average, run of the mill, electronic assembly?
Are Bellcore TR-332 and MIL-HDBK-217 still the most current standards in this area, or has IPC come out with something?

my humble thanks...

Justin Braime
------------------------
Process Engineer
Compuspec Industries Ltd
Auckland, New Zealand
[log in to unmask]

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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2014.210" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>What is the best method for calculating an MTBF =
figure for=20
your average, run of the mill, electronic assembly?</FONT></DIV>
<DIV><FONT size=3D2>Are Bellcore TR-332 and MIL-HDBK-217 still the most =
current=20
standards in this area, or has IPC come out with something?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>my humble thanks...</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Justin Braime<BR>------------------------<BR>Process =

Engineer<BR>Compuspec Industries Ltd<BR>Auckland, New =
Zealand</FONT></DIV>
<DIV><FONT size=3D2><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></FONT></D=
IV></BODY></HTML>

------=_NextPart_000_0186_01BF9272.F1DDDF80--

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Date:         Mon, 20 Mar 2000 16:10:35 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      MTBF calculus
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Not sure about the "best" method Justin, 217F is current , didn't see
anything quite close  @ IPC's scriptures ;
seen somebody from T-cubed here on Net latelee, otherwise you may check ;
http://www.masterpromotion.com/links1.htm
free calculus download is :
http://www.relexsoftware.com/download.asp

this is Werner's patch, being an ex Bell fellow on this line .

humble servant                       paul

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Date:         Sun, 19 Mar 2000 21:27:10 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Doug <[log in to unmask]>
Subject:      Re: MTBF
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I'm not familiar with 217 but have used Bellcore 332
for a while.  Even copied the charts from 332 into an
Excel spreadsheet to crosscheck the Relex software.
Then used the Relex software.  Can change all sorts
of parameters on the spot.  If you've got a little
time, then just copy the charts out of 332 and fo
it by hand which really isn't that difficult.

The 332 way is very easy.  Pay $150 for the standard,
identify the FITs for each component, it's a snap.

Regards,  Doug McKean

> Justin Braime wrote:
>
> What is the best method for calculating an MTBF figure for your
> average, run of the mill, electronic assembly?
> Are Bellcore TR-332 and MIL-HDBK-217 still the most current standards
> in this area, or has IPC come out with something?

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Date:         Sun, 19 Mar 2000 22:35:35 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, ryu <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         ryu <[log in to unmask]>
Subject:      "Paste in hole" standards?
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Is there any IPC standards ( design. application and inspection )  in
the "paste in hole" area  ( reflowing thru.hole parts) ?  Please let me
know which document(s)should I check if you know it.  Thanks.

Rudolph Yu

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Date:         Thu, 16 Mar 2000 07:11:09 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Misner, Bruce" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Misner, Bruce" <[log in to unmask]>
Subject:      Re: ??: [TN] Gold Removal

Enough. 30u Inches of Au IS NOT enough to embrittle solder joints. I've done
it on space flight hardware for years in the 1980's and have performed every
test, environmental screen and evaluation imaginable with no detriment and
have satisfied NASA and the Air Force.  Satisfy your QA with an MRB, accept
the boards, send a SCAR to the vendor, save your schedule and save your
headache for something real. Next Topic.

> ----------
> From:         Paul Klasek[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Paul Klasek
> Sent:         Wednesday, March 15, 2000 8:04 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] ??: [TN] Gold Removal
>
> Oh, gee, ehm, Ryan, mate, close, not sure if enough :
> 1
> Steve's maths ?(sorry Steve, you ARE one of the LEGENDS):
> "nearly" 75u" = 1.875um (or close enough);
> is NOT in line with ITRI's recommended 1.5um ceiling :
> me the coward never had guts to digest even 1um on soldered pads .
> I'll give you; with latest pad size trends (smaller); you may creep touch
> higher,
> but i do know if i'd got totally stoned and placed more than 1umAu on
> specs,
> my fellow in QA would be after my skin .
> Besides, Tim 's been just quizzing me where the hell do i squeeze 0.5um
> from
> flush;
> whining bitterly all he gets from his fabs is 0.25um tops on flash .
> Record i MEASURED on flash was some 0.8um,
> so i presume it's my turn in Tim's shoes :
> Where would you get saturation's which throws 75u" on Ni ?
> Presume only academic maths ?
>
> And the bible talks, i think (?) about 4% , not 3,
> but i won't be making scenes about that one
> (less is better, almost, hahaha)
>
> And NiAu (0.5umAu average = 20u") costs us less than HASL .
>
> Getting gold ears from all this off hip traffic ;
> getting dark here too: Inge : deleted some dozen methaned messages today !
>
> All in good humor Ryan , ok ?, just let's retain the functionality.
>
>
> Paul
>
> -----Original Message-----
> From: Ryan Grant [mailto:[log in to unmask]]
> Sent: Thursday, 16 March 2000 10:47
> To: [log in to unmask]
> Subject: Re: [TN] ??: [TN] Gold Removal
>
>
> I agree with this.  Do the math.  If a five mil stencil is used, and the
> component leads are NOT gold plated, the board gold thickness can reach
> nearly 75 micro inches before the percentage of gold in the joint reaches
> the magical number of 3%.  Below 3%, gold is not shown to induce
> embrittlement.  If you are soldering to BGA balls, there is even more Tin
> to
> dilute the gold, so the gold thickness can be even thicker.  The reason
> for
> the 5 to 8 micro inches of gold thickness is, that is the MINIMUM needed
> to
> prevent oxidation of the nickel.  Thicker gold is more expensive in terms
> of
> processing and material cost, and it is unnecessary, so why do it?
>
> Of course, if I buy a new stereo, and it has a scratch on it, I'll take it
> back.  Functionality be damned.  Rick can do the same with his boards.
>
> Ryan G.
>
> > -----Original Message-----
> > From: Timothy Reeves [SMTP:[log in to unmask]]
> > Sent: Wednesday, March 15, 2000 3:08 PM
> > To:   [log in to unmask]
> > Subject:      Re: [TN] ??: [TN] Gold Removal
> >
> > Does anyone agree with this? I hope not.
> >
> > > ----------
> > > From:         Jonathan A Noquil
> > > Sent:         Tuesday, March 14, 2000 15:57
> > > Subject:      Re: ??: [TN] Gold Removal
> > >
> > > Higher gold thickness does not affect
> > > reliability (solderability),
> >
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Date:         Thu, 16 Mar 2000 07:23:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Gold Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

~fingers lightly touching the computer screen, sliding over the text you
submitted~

I can sense your frustration with fabricators on this, so I shall slowly
back away before it really gets out of hand........

Franklin


----- Original Message -----
From: Howieson, Rick <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 15, 2000 4:07 PM
Subject: Re: [TN] Gold Removal


> YES! Reject it and send it back to fab. And my answer to your view, if
> you can't build the damn thing to print don't quote it! Enough said.
>
> >-----Original Message-----
> >From:  Franklin Asbell [SMTP:[log in to unmask]]
> >Sent:  Wednesday, March 15, 2000 6:01 PM
> >To:    [log in to unmask]
> >Subject:       [TN] Gold Removal
> >
> >Cyanide in and of itself won't remove gold, it's a lot more detailed than
> >that, and then controlling how much is removed is almost impossible.
> >
> >Speaking from experience, you won't even smell almonds, you might see a
> >humid cloud drifting slowly away from the tank, and the next thing you'll
> >see is the ER doctor telling you things will be just fine.
> >
> >30 microinches of Gold won't affect solderability any different then 10
> >microinches. What it might affect depending on your application is the
> >electrical properties.
> >
> >If 30 microinches is simply intolerable then buff the gold tabs or pads
down
> >to what you believe to be a tolerable level, unless you have access to an
> >XRF or similar device though, you won't know how far you've gone.
> >
> >Sure, reject it all back to the fabricator, have them restart the job,
put
> >everything on a back burner, or better yet, find another supplier,
resubmit
> >gerber, have them do it, of course you'll want to survey them first,
gotta
> >remember to schedule that before we give them the order.
> >
> >~...hmmmm, wondering if I'm being too facetious, nah, not with this
group,
> >they can appreciate the humor in this....grinning~
> >
> >Franklin
> >
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Date:         Mon, 20 Mar 2000 07:31:52 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Willis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Willis <[log in to unmask]>
Subject:      Re: "Paste in hole" standards?
X-To:         ryu <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0009_01BF923E.5C3A1040"

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As far as I know there is not any standards for the process, there does =
not need to be as any process should be well able to meet the =
requirements of level 2 of IPC. I had recommended to IPC through their J =
standard that references to the process and the need to consider =
alternative finishes in the standard is a high priority.

If you contact SMTA in the USA they do have the SMART Group Pin in Hole =
Report plus video and CD ROM on the subject. The SMART Group is the =
European Surface Mount Trade Association.


Bob Willis

Home Page: www.bobwillis.co.uk
Tel: (44) 01245 351502
Fax: (44) 01245 496123
  ----- Original Message -----=20
  From: ryu=20
  To: [log in to unmask]
  Sent: Monday, March 20, 2000 6:35 AM
  Subject: [TN] "Paste in hole" standards?


  Is there any IPC standards ( design. application and inspection )  in
  the "paste in hole" area  ( reflowing thru.hole parts) ?  Please let =
me
  know which document(s)should I check if you know it.  Thanks.

  Rudolph Yu

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1.8c
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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>As far as I know there is not any =
standards for the=20
process, there does not need to be as any process should be well able to =
meet=20
the requirements of level 2 of IPC. I had recommended to IPC through =
their J=20
standard that references to the process and the need to consider =
alternative=20
finishes in the standard is a high priority.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>If you contact SMTA in the USA they do =
have the=20
SMART Group Pin in Hole Report plus video and CD ROM on the subject. The =
SMART=20
Group is the European Surface Mount Trade Association.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>Bob Willis</DIV>
<DIV>&nbsp;</DIV>
<DIV>Home Page: <A=20
href=3D"http://www.bobwillis.co.uk">www.bobwillis.co.uk</A><BR>Tel: (44) =
01245=20
351502<BR>Fax: (44) 01245 496123</DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[log in to unmask]" [log in to unmask]>ryu</A> =
</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
  [log in to unmask]>[log in to unmask]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Monday, March 20, 2000 =
6:35=20
AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] "Paste in hole"=20
  standards?</DIV>
  <DIV><BR></DIV>Is there any IPC standards ( design. application and =
inspection=20
  )&nbsp; in<BR>the "paste in hole" area&nbsp; ( reflowing thru.hole =
parts)=20
  ?&nbsp; Please let me<BR>know which document(s)should I check if you =
know=20
  it.&nbsp; Thanks.<BR><BR>Rudolph=20
  =
Yu<BR><BR>##############################################################<=
BR>TechNet=20
  Mail List provided as a free service by IPC using LISTSERV=20
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1.8c<BR>##############################################################<BR=
>To=20
  subscribe/unsubscribe, send a message to <A=20
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  visit IPC web site (<A=20
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href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>)=20
  for additional<BR>information.<BR>If you need assistance - contact =
Keach=20
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Date:         Mon, 20 Mar 2000 11:24:40 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Grant Emandien <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Grant Emandien <[log in to unmask]>
Subject:      Coating of assemblies with no clean fluxes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi all,

The debate on cleaning of fluxes as well as the use no-clean fluxes seems to
hang around forever. We have been informed by our solder an flux supplier
that assemblies with no clean fluxes can be conformally coated without the
need to clean the boards.

The argument is that the high temperatures of the reflow oven 'burns off'
the active ingredients, leaving only inactive residues. These flux residues
do not have to be cleaned and can supposedly be coated. The rep. believes we
are taking a backward step by possibly opting to use water-based flux. Is
this pure sales talk?

Is anyone able to offer any advice or insight, or been able to assess the
environmental and electrical performance of such assemblies.

Regards
Grant

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Date:         Thu, 16 Mar 2000 07:55:57 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ashok Dhawan <[log in to unmask]>
Organization: C-MAC Electronic Systems Inc.
Subject:      Tools/ methods to remove solder balls
MIME-Version: 1.0
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I am looking for suggestions on " How to remove solder Balls".
We have some designs and tools where nothing can be done economically
except to remove the solder balls manually. We are using "Probe" picks
to do that job.
Anyone who can suggest a better tool or method to remove solder balls ?
The flux used is low residue NC flux.

--

Ashok Dhawan P.Eng
Engineering
C-Mac Electronic Systems Inc.
1455 Mountain Avenue
Winnipeg, Manitoba R2X 2Y9
Canada
Phone: (204) 631-7208
Fax: (204) 631-7294
E-mail: [log in to unmask]
www.cmac.ca


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Date:         Mon, 20 Mar 2000 06:24:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: VOC legislation
X-To:         Todd Harris <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Quayles you mean?

-----Original Message-----
From: Todd Harris [mailto:[log in to unmask]]
Sent: Wednesday, March 15, 2000 12:57
To: [log in to unmask]
Subject: Re: [TN] VOC legislation


Al Gore did not make this statement.  I think you are referring to Dan
Quayle's quote :

If we do not succeed, then we run the risk of failure.
-- Vice President Dan Quayle, to the Phoenix Republican Forum, 3/23/90
(reported in Esquire, 8/92) Also reported by Reuters, 5/2/90

Lets not make fun of our future President!

-----Original Message-----
From: Kasprzak, Bill (esd) USX [mailto:[log in to unmask]]
Sent: Wednesday, March 15, 2000 6:52 AM
To: [log in to unmask]
Subject: Re: [TN] VOC legislation


As long as we're getting on the "lighter" side...

Can the answer to the "Sun or Moon" question be attributed to Al Gore?

After all he once said, "If we don't succeed, we run the risk of failure."

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Dieselberg, Ron [SMTP:[log in to unmask]]
> Sent: Wednesday, March 15, 2000 8:14 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] VOC legislation
>
> Same as speed of light only less bright (brite)!
> Or -186,000 ft/sec whichever you like.
>
> Q. Which is more important, the Sun or the Moon?
> A. If you said Sun you were wrong. The Moon is more important 'cuz it
> shines
> at night when it is dark, whereas the Sun shines in the daytime when it is
> light anyway.
> Ron Dieselberg
>
> -----Original Message-----
> From: Ingemar Hernefjord (EMW)
> [mailto:[log in to unmask]]
> Sent: Wednesday, March 15, 2000 06:19
> To: [log in to unmask]
> Subject: Re: [TN] VOC legislation
>
>
> However, THIS is a very severe question to you guys: all speak about the
> speed of light. And all know what, even the man with the hanging tongue
> and
> Noble Prize. But nobody speak about the speed of dark! So, what's speed of
> dark?
>
> Ingemar
>
>
> Subject: Re: [TN] VOC legislation
>
>
> Yes, but it makes life more interesting :-)
>
> "Ingemar Hernefjord (EMW)" wrote:
>
> > I like the way TechNet members can camouflage electronic technical
> questions..he-he
> > Ingemar
> >
> > Mike
> >
> > I'm not sure what exactly is the biggest contributor of CH4, there are
> so
> many large sources.
> > Whereas the termite is one, I doubt whether it is even one of the
> largest.
> I suspect that it may
> > be the myriad leaks along HP natural gas pipelines, but in terms of
> nature, I'll plump for the
> > anaerobic decomposition of vegetable matter, esp. in wetlands, stagnant
> water, rainforest floors,
> > etc. In fact this includes the termite: as he chews the wood, he digests
> a
> very small percentage
> > of it and the rest passes out where it decomposes to produce the stuff.
> Similarly, much kelp and
> > other sea vegetation decomposes on the sea bed. Interestingly, studies
> have shown that, when the
> > Amazonian rainforest is slashed and burnt and then converted to cattle
> farming, the methane
> > production per hectare actually increases. This is because only a small
> percentage of the cycle of
> > vegetation decomposes anaerobically -  most of it is destroyed
> aerobically
> by microfungi,
> > producing essentially CO2 and H2O.
> >
> > As for the contribution to global warming by canned baked beans ...
> >
> > Brian
> >
> > Michael Fenner wrote:
> >
> > > Well, thank you for that thought...
> > >
> > > I understand though that the biggest contributor of methane to the
> world
> is the humble termite
> > > on account of the fact that there are so many of them.
> > >
> > > Mike
> > >
> >
> > >
> > > > So yes, Mike, we must never forget that a large proportion of VOCs
> can
> > > > be from natural causes.....animal farts...
> > > >
> > > > ....ammonia from pig farms and other animal breeding not to forget..
> imagine what tens of
> > > millions of those animals generate each hour...latest reports say
> ammonia is a real O3
> > > killer....//Ingemar
> > >
> >
>
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Date:         Mon, 20 Mar 2000 11:55:22 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         Grant Emandien <[log in to unmask]>
MIME-Version: 1.0
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Grant

To quote the great Sir Winston Churchill, "Round Objects!" to the rep in
question.

As a manufacturer of conformal coatings I am more than just dismayed at
these sorts of comments. Too frequently, customers are using conformal
coatings to hide reliability problems faced with no-clean regimes. This only
serves to give us a bad name because you may be making the problem bigger
than it would be without the coating - they seal IN as well as out!

Can you coat over no-clean? Yes. How do you achieve this? By using latest
SIR test methods and modelling your full production process on SIR coupons.
The you may find out if it will work.

As some of you may know, Dr Chris Hunt from the British National Physical
Laboratory presented initial results of a major new research study in this
area which caused more than a little disquiet from the recipients.

Contrary to the recent postings on a similar thread from both Brian Ellis
and Per Erik Tegehall, we now have the scientific evidence to prove the
benefit of SIR testing as a reliability predictor.

Now Grant, what is your consequential liability risk if the rep is wrong? Is
your product safety critical? Are you really willing to take this risk on
the say-so of a rep?

Ask him to do the testing for you and prove it!

Hope this helps you.

Regards,
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227
----- Original Message -----
From: Grant Emandien <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 9:24 AM
Subject: [TN] Coating of assemblies with no clean fluxes


> Hi all,
>
> The debate on cleaning of fluxes as well as the use no-clean fluxes seems
to
> hang around forever. We have been informed by our solder an flux supplier
> that assemblies with no clean fluxes can be conformally coated without the
> need to clean the boards.
>
> The argument is that the high temperatures of the reflow oven 'burns off'
> the active ingredients, leaving only inactive residues. These flux
residues
> do not have to be cleaned and can supposedly be coated. The rep. believes
we
> are taking a backward step by possibly opting to use water-based flux. Is
> this pure sales talk?
>
> Is anyone able to offer any advice or insight, or been able to assess the
> environmental and electrical performance of such assemblies.
>
> Regards
> Grant
>
> ##############################################################
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> information.
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> 847-509-9700 ext.5315
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>

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Date:         Mon, 20 Mar 2000 06:01:07 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         [log in to unmask]
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

Hi Rudy & All

I've received the same message via Mindspring on a couple of occasions.  I
delete it now, without opening the letter file.

Kelly
-----Original Message-----
From: <Rudy Sedlak> <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Saturday, March 18, 2000 10:06 AM
Subject: Re: [TN] Strange email...


>Steve:
>
>You are on AOL, (as am I) and it is one of the more unfortnate Internet
>Service Providers.   The message you got, and the attached file was created
>by AOL, because if a message is too long, AOL truncates it, and turns the
>remainder into an attached file in the .mim format.  I think, but am not
>sure, that the .mim format may be uniquely owned and used by AOL, and that
is
>the tip off.
>
>Rudy Sedlak
>RD Chemical
>
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Date:         Mon, 20 Mar 2000 12:16:31 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brunker Ed <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brunker Ed <[log in to unmask]>
Subject:      MICROBGAs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Anyone got any bright ideas for reballing micro BGAs,
Regards
Edward Brunker

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Date:         Mon, 20 Mar 2000 13:33:20 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "d. terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: MICROBGAs
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Edward,

Check out the Solderquick Reballing Kit. Don't know if they can go any =
smaller than 0.8 mm pitch, but they do make specials. There's an online =
catalogue at their website (www.solderquick.com).

Kind regards

Daan Terstegge
SMT Centre
Signaal Communications
Unclassified mail
Personal website: http://surf.to/smtinfo

>>> Brunker Ed <[log in to unmask]> 03/20 1:16 pm >>>
Anyone got any bright ideas for reballing micro BGAs,
Regards
Edward Brunker

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Date:         Mon, 20 Mar 2000 06:29:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         Grant Emandien <[log in to unmask]>
MIME-Version: 1.0
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Mornin' Grant & All -

The argument that conformal coating can be applied satisfactorily over the
leavings of low residue flux, or any other residue, could only be considered
valid if the conformal coating had been retested and passed  the
qualification requirements of IPC-CC-830, MIL-I-46058, or whatever
specification is valid in the case of that material.

IMHO, any statements by the formulator of any of the materials which are not
supported by this data would have to be considered trivia.  I think we've
all seen the cases of vessication, where the water molecule has passed thru
the vapor permeable barrier of the coating and attached itself to a
contaminant on the surface of the board, creating a microscopic cluster of
bubbles.  That is just one example of what may take place.

Regards - Kelly


-----Original Message-----
From: Grant Emandien <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Monday, March 20, 2000 3:29 AM
Subject: [TN] Coating of assemblies with no clean fluxes


>Hi all,
>
>The debate on cleaning of fluxes as well as the use no-clean fluxes seems
to
>hang around forever. We have been informed by our solder an flux supplier
>that assemblies with no clean fluxes can be conformally coated without the
>need to clean the boards.
>
>The argument is that the high temperatures of the reflow oven 'burns off'
>the active ingredients, leaving only inactive residues. These flux residues
>do not have to be cleaned and can supposedly be coated. The rep. believes
we
>are taking a backward step by possibly opting to use water-based flux. Is
>this pure sales talk?
>
>Is anyone able to offer any advice or insight, or been able to assess the
>environmental and electrical performance of such assemblies.
>
>Regards
>Grant
>
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Date:         Mon, 20 Mar 2000 07:47:00 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Nancy Trumbull <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Nancy Trumbull <[log in to unmask]>
Subject:      Re: Wire wraps
Mime-Version: 1.0
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Good morning Tim,
Hope you had a great week end.
My understanding as one of the IPC 610 trainers is
For round post under 3-49 page 40
Yes
Acceptable Class 1 and 2=20
B. Minimum wrap for less than 180=B0 of contact between the wires and the =
terminal.
Page 41 3-52 is for terminal
Please note page 40 is for round posts
When reading 610 it is very importance to note special words.

Also revision C is out.
Your issue is on page  5-37 and is now a Process Indicator for Class 2 and =
is referred to as Terminals - wrap- Turrets and Straight Pins.
revision C is some what easier to understand.
Good luck .
If you need more please feel free to e-mail me directly or call.

616-966-0800 Ext 1242
Nancy T.
>>> Tim Devaul <[log in to unmask]> 03/17/00 01:27PM >>>
    Hi everyone, I am confused! I am preparing to teach a 610 class (rev. =
B) and I came across a problem dealing with wire wraps.
       Just below figure 3-49 on page 40, item B states that "minimum wrap =
for round posts has less than 180 degrees of contact between the wires and =
the terminal". This is listed as acceptable for class 1 and  2. However, =
under figure 3-52 on page 41 it=20
states minimum wrap contacts the terminal 180 degrees, or 90 degrees (if =
mechanically secured).=20
       My question is; is it acceptable for class 2 to have a wrap less =
than 180 degrees on a round post or not? Thanks in advance for your help!
        =20
Tim DeVaul
Total Quality Training and Audit Supervisor
Philips Broadband Networks, Inc.
100 Fairgrounds Dr.
Manlius, New York 13104
Tel: (315) 682-9105 Ext. 2403
Fax: (315)682-9006
Email: [log in to unmask]

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Date:         Mon, 20 Mar 2000 14:43:45 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Grant & Everybody!

I'll be surprised if you get to conformal coat without cleaning.

The other two people you need to check with are the conformal coating
manufacturer and your customer.  If they both said it was okay then you're
in business.

Don't forget IPC-A-610C section: 9.1.2 Defect - Class 1,2,3:
"Any foreign material that violates minimum electrical clearance between
components, lands or conductive surfaces."

I consider a non-conductive residue on a PWA as a defect (foreign material)
until I prove it otherwise - SIR, Salt Fog, . . .

Hans

~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Materials (Process & Manufacturing) Engineer
Warner Robins Air Logistics Center
Avionics Production Division
Manufacturing Branch
380 Second Street, Suite 104
Building: 640, Mail Stop: LYPME
Robins AFB, GA 31098-1638
Voice: (912) 926 - 1970 Fax: (912) 926 - 7164
mailto:[log in to unmask]
http://www.robins.af.mil

-----Original Message-----
From: Grant Emandien [mailto:[log in to unmask]]
Sent: Monday, March 20, 2000 4:25 AM
To: [log in to unmask]
Subject: [TN] Coating of assemblies with no clean fluxes


Hi all,

The debate on cleaning of fluxes as well as the use no-clean fluxes seems to
hang around forever. We have been informed by our solder an flux supplier
that assemblies with no clean fluxes can be conformally coated without the
need to clean the boards.

The argument is that the high temperatures of the reflow oven 'burns off'
the active ingredients, leaving only inactive residues. These flux residues
do not have to be cleaned and can supposedly be coated. The rep. believes we
are taking a backward step by possibly opting to use water-based flux. Is
this pure sales talk?

Is anyone able to offer any advice or insight, or been able to assess the
environmental and electrical performance of such assemblies.

Regards
Grant

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Date:         Mon, 20 Mar 2000 10:00:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ramsey, Guy" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ramsey, Guy" <[log in to unmask]>
Subject:      Re: double sided reflow problems
X-To:         Bob Perkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We observed similar conditions when the components are heavy enough to move,
almost heavy enough to break the surface tension holding them to the board.
We glued the components to the board. It greatly reduced changes in the
appearance of the solder fillets.

-----Original Message-----
From: Bob Perkins [mailto:[log in to unmask]]
Sent: Friday, March 17, 2000 2:33 PM
Subject: double sided reflow problems


Hi Technetters

        Recently on heavy double reflow boards we have had good reflow on
the first side but when we flip over the integrity of the solder joint which
is now on the bottom has been compromised after the second pass.  The
temperature in the oven is only slightly hotter (peak temperatures around
220C on both sides) to compensate for the added component load. On the
bottom however it seems like the heaver qfp's look like they are trying to
pull away, looking like poor wetting,  leaving a hallow or indentation on
side of the lead or back on the heal fillet.
The quick fix is to add flux to the bottom before reflowing again, but this
is time consuming. This may also require gluing of all these parts to hold
them in place, which is even more time consuming.
Could the answer be to increase the stencil thickness from a 4-mil to a
6-mil to add paste to the board to increase the surface tension helping the
board  hold the qfp's better?
Is this entirely an oven reflow problem?
Does adding flux increase quality all around, or is this a non value added
process?
Does anyone else have experience with boards being run though for a second
pass without flux?


Bob Perkins
Automation Technician/Manufacturing Engineer
[log in to unmask]

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Date:         Mon, 20 Mar 2000 08:18:04 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Gold Removal
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Franklin,
In addition to being a CEM we also fab boards of which I spend the
majority of my time. Too many times, and we are also guilty, a fab house
makes the assumption that although not within spec the boards can be
used. This is the point I was trying to make in an effort not to "hurt"
anyone.
Rick

>-----Original Message-----
>From:  Franklin Asbell [SMTP:[log in to unmask]]
>Sent:  Thursday, March 16, 2000 8:23 AM
>To:    [log in to unmask]
>Subject:       Re: [TN] Gold Removal
>
>~fingers lightly touching the computer screen, sliding over the text you
>submitted~
>
>I can sense your frustration with fabricators on this, so I shall slowly
>back away before it really gets out of hand........
>
>Franklin
>
>
>----- Original Message -----
>From: Howieson, Rick <[log in to unmask]>
>To: <[log in to unmask]>
>Sent: Wednesday, March 15, 2000 4:07 PM
>Subject: Re: [TN] Gold Removal
>
>
>> YES! Reject it and send it back to fab. And my answer to your view, if
>> you can't build the damn thing to print don't quote it! Enough said.
>>
>> >-----Original Message-----
>> >From:  Franklin Asbell [SMTP:[log in to unmask]]
>> >Sent:  Wednesday, March 15, 2000 6:01 PM
>> >To:    [log in to unmask]
>> >Subject:       [TN] Gold Removal
>> >
>> >Cyanide in and of itself won't remove gold, it's a lot more detailed than
>> >that, and then controlling how much is removed is almost impossible.
>> >
>> >Speaking from experience, you won't even smell almonds, you might see a
>> >humid cloud drifting slowly away from the tank, and the next thing you'll
>> >see is the ER doctor telling you things will be just fine.
>> >
>> >30 microinches of Gold won't affect solderability any different then 10
>> >microinches. What it might affect depending on your application is the
>> >electrical properties.
>> >
>> >If 30 microinches is simply intolerable then buff the gold tabs or pads
>down
>> >to what you believe to be a tolerable level, unless you have access to an
>> >XRF or similar device though, you won't know how far you've gone.
>> >
>> >Sure, reject it all back to the fabricator, have them restart the job,
>put
>> >everything on a back burner, or better yet, find another supplier,
>resubmit
>> >gerber, have them do it, of course you'll want to survey them first,
>gotta
>> >remember to schedule that before we give them the order.
>> >
>> >~...hmmmm, wondering if I'm being too facetious, nah, not with this
>group,
>> >they can appreciate the humor in this....grinning~
>> >
>> >Franklin
>> >
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Date:         Mon, 20 Mar 2000 10:25:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Timothy Tezak <[log in to unmask]>
Subject:      Needed: NJ/PA Area Acoustic Microscopy Laboratory Services
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hey everyone!

We are located in West Trenton, NJ and we need a local service lab that has
Acoustic Microscopy capabilities.
Can anyone recommend a lab with these capabilities?

Thanks!
Tim Tezak

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Date:         Mon, 20 Mar 2000 07:46:21 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Popielarski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Popielarski <[log in to unmask]>
Subject:      Re: MICROBGA's
X-cc:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_0020_01BF9240.6278A820"

This is a multi-part message in MIME format.

------=_NextPart_000_0020_01BF9240.6278A820
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Ed,

Please visit the website below and take a peek at what we offer. We just
sold a system to 3M that places .012" dia balls on .020" centers in a 15 =
X
15 array (225 balls per device) 8mm square CSP 8 at a time!

Sorry if this sounded like an dvertisment, but the question was:


Date:    Mon, 20 Mar 2000 12:16:31 -0000
From:    Brunker Ed <[log in to unmask]>
Subject: MICROBGAs

Anyone got any bright ideas for reballing micro BGAs,
Regards
Edward Brunker

Regards,

Ed Popielarski
QTA Machine
10 Mc Laren, Ste. D
Irvine, Ca. 92618

Ph: 949-581-6601
Fx: 949-581-2448

http://www.qta.net

Check out our BGA Baller and Process Equipment Services!

------=_NextPart_000_0020_01BF9240.6278A820
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------=_NextPart_000_0020_01BF9240.6278A820--

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Date:         Mon, 20 Mar 2000 10:56:29 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Sheila Smith <[log in to unmask]>
Subject:      Re: Needed: NJ/PA Area Acoustic Microscopy Laboratory Services
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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It's not exactly local, but Sonoscan near Chicago offers lab services and
have given us excellent service.  Their web site www.sonoscan.com has
contact information.  They are very close to O'Hare if you want to wait for
your results, too!

Sheila Smith @ BAE Systems

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Timothy Tezak
Sent: Monday, March 20, 2000 10:25 AM
To: [log in to unmask]
Subject: [TN] Needed: NJ/PA Area Acoustic Microscopy Laboratory Services


Hey everyone!

We are located in West Trenton, NJ and we need a local service lab that has
Acoustic Microscopy capabilities.
Can anyone recommend a lab with these capabilities?

Thanks!
Tim Tezak

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Date:         Mon, 20 Mar 2000 11:14:34 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Charles E. McMahon" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Charles E. McMahon" <[log in to unmask]>
Organization: McMahon Sales Company, Inc.
Subject:      Re: Needed: NJ/PA Area Acoustic Microscopy Laboratory Services
X-To:         [log in to unmask]
MIME-Version: 1.0
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Tim,
We can offer that you those services from New Hampshire if that is close
enough.
If interested contact off-line.

Charlie McMahon
[log in to unmask]

---- Original Message -----
From: Timothy Tezak <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 10:25 AM
Subject: [TN] Needed: NJ/PA Area Acoustic Microscopy Laboratory Services


> Hey everyone!
>
> We are located in West Trenton, NJ and we need a local service lab that
has
> Acoustic Microscopy capabilities.
> Can anyone recommend a lab with these capabilities?
>
> Thanks!
> Tim Tezak
>
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Date:         Mon, 20 Mar 2000 08:33:43 PST
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Glenn Pelkey <[log in to unmask]>
Subject:      Re: MTBF
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi Justin,

        Here's what we do:

1)  Fiber optic assembly:  Bellcore TR-332
2)  Military Assembly:  Mil-Std-217F
3)  An Other Assembly:  Parts count method using supplier data for active
components and any passives that are available.  Use Bellcore as first choice
for any not available, use 217 last.

        Here's some other info to keep in mind when doing reliability
estimates.  First, many people are skeptical of these methods, but I still
find there's value in them.  In the least, it opens up lines of communication
between you and the supplier so that you can be aware of limitations and
potential/past problem areas.
        Second, if you use supplier data, be sure to adjust for temperature
and confidence levels.  Many suppliers will publish 25 C failure rate numbers
and Bellcore asks for 40C.  As you probably know, the higher the temperature,
the higher the failure rate and lower MTBF.  We also like to use 90%
confidence, but you will often find 60% confidence commonly used.  The higher
the confidence, the higher the failure rate.
        Thirdly, Bellcore (Telcordia) TR-332 now costs $1,000.  Good luck
trying to sell management on that.

Some links:
http://telecom-info.telcordia.com/site-cgi/ido/index.html
http://www.enre.umd.edu/mainnojs.html
http://www.quality.org/html/reliable.html

Glenn

Justin Braime <[log in to unmask]> Wrote:
|
| What is the best method for calculating an MTBF figure for your average, run
of the mill, electronic
| assembly?
| Are Bellcore TR-332 and MIL-HDBK-217 still the most current standards in
this area, or has IPC come
| out with something?
|
| my humble thanks...
|
| Justin Braime
| ------------------------
| Process Engineer
| Compuspec Industries Ltd
| Auckland, New Zealand
| [log in to unmask]
|
|

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Date:         Mon, 20 Mar 2000 11:38:38 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Paul Bitchel <[log in to unmask]>
Subject:      Please remove me from Technet
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Please remove me from Technet.
Thanks Paul

http://www.apcc.com

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Date:         Mon, 20 Mar 2000 09:29:04 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hamilton, Richard CLE 4454" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Hey Steve,

Yea, I got one of these last week after I sent a post to TN, this is what I
got back, but about 5 days later!! I just chalked it up to our very poor
email gateway service at the present. I am glad to hear that I am not alone
with this particular sensation!!

Richard Hamilton
Clemar Mfg. / Rain Bird
[log in to unmask]

> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Saturday, March 18, 2000 6:31 AM
> To:   [log in to unmask]
> Subject:      [TN] Strange email...
>
> Good morning everybody!
>
> Below, I've pasted a message that was waiting in my mailbox for me this
> morning. It had a attachment with it (that I didn't open). Is anybody else
> getting these? I know of a couple people that have, but I'm wondering if
> everybody is? Looking at the email address, and the attachment has me
> worried...also the comment in the message; "may be forged".
>
> Just curious...
>
> -Steve Gregory-
>
> Subj:    Returned mail: Too many hops 305 (30 max): from <@pub
> Date:   03/18/2000 4:43:00 AM Central Standard Time
> From:   [log in to unmask] (Mail Delivery Subsystem)
> To: [log in to unmask], [log in to unmask]
>
> File:  Returned.mim (59131 bytes)
> DL Time (37333 bps): < 1 minute
>
> [This e-mail contains a MIME (Multipurpose Internet Mail Extensions) file.
> The file was specially formatted to be sent over the Internet.  For more
> information on opening the attached file, go to Keyword: MIME.]
> --------------------
> The original message was received at Sat, 18 Mar 2000 04:44:18 -0600 (CST)
> from pop2.guangzhou.gd.cn [202.96.128.113] (may be forged)
>
>    ----- The following addresses had permanent fatal errors -----
> <[log in to unmask]>
>
>    ----- Transcript of session follows -----
> 554 Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
>
>
> ----------------------- Headers --------------------------------
> Return-Path: <>
> Received: from  rly-yg02.mx.aol.com (rly-yg02.mail.aol.com [172.18.147.2])
> by
> air-yg05.mail.aol.com (v70.19) with ESMTP; Sat, 18 Mar 2000 05:43:00 -0500
> Received: from  mail.ipc.org (mail.ipc.org [216.203.207.34]) by
> rly-yg02.mx.aol.com (v70.20) with ESMTP; Sat, 18 Mar 2000 05:42:45 -0500
> Received: from localhost (localhost)
>     by mail.ipc.org (8.8.8+Sun/8.8.8) with internal id EAB27092;
>     Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> Date: Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> From: Mail Delivery Subsystem <[log in to unmask]>
> Message-Id: <[log in to unmask]>
> To: <[log in to unmask]>
> To: [log in to unmask]
> MIME-Version: 1.0
> Content-Type: multipart/report; report-type=delivery-status;
>     boundary="EAB27092.953376266/mail.ipc.org"
> Subject: Returned mail: Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
> Auto-Submitted: auto-generated (failure)
>
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Date:         Mon, 20 Mar 2000 11:06:45 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Gold Removal
X-To:         "Howieson, Rick" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Thank you Sir, I understand.

Franklin


----- Original Message -----
From: Howieson, Rick <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 7:18 AM
Subject: Re: [TN] Gold Removal


> Franklin,
> In addition to being a CEM we also fab boards of which I spend the
> majority of my time. Too many times, and we are also guilty, a fab house
> makes the assumption that although not within spec the boards can be
> used. This is the point I was trying to make in an effort not to "hurt"
> anyone.
> Rick
>
> >-----Original Message-----
> >From:  Franklin Asbell [SMTP:[log in to unmask]]
> >Sent:  Thursday, March 16, 2000 8:23 AM
> >To:    [log in to unmask]
> >Subject:       Re: [TN] Gold Removal
> >
> >~fingers lightly touching the computer screen, sliding over the text you
> >submitted~
> >
> >I can sense your frustration with fabricators on this, so I shall slowly
> >back away before it really gets out of hand........
> >
> >Franklin
> >
> >
> >----- Original Message -----
> >From: Howieson, Rick <[log in to unmask]>
> >To: <[log in to unmask]>
> >Sent: Wednesday, March 15, 2000 4:07 PM
> >Subject: Re: [TN] Gold Removal
> >
> >
> >> YES! Reject it and send it back to fab. And my answer to your view, if
> >> you can't build the damn thing to print don't quote it! Enough said.
> >>
> >> >-----Original Message-----
> >> >From:  Franklin Asbell [SMTP:[log in to unmask]]
> >> >Sent:  Wednesday, March 15, 2000 6:01 PM
> >> >To:    [log in to unmask]
> >> >Subject:       [TN] Gold Removal
> >> >
> >> >Cyanide in and of itself won't remove gold, it's a lot more detailed
than
> >> >that, and then controlling how much is removed is almost impossible.
> >> >
> >> >Speaking from experience, you won't even smell almonds, you might see
a
> >> >humid cloud drifting slowly away from the tank, and the next thing
you'll
> >> >see is the ER doctor telling you things will be just fine.
> >> >
> >> >30 microinches of Gold won't affect solderability any different then
10
> >> >microinches. What it might affect depending on your application is the
> >> >electrical properties.
> >> >
> >> >If 30 microinches is simply intolerable then buff the gold tabs or
pads
> >down
> >> >to what you believe to be a tolerable level, unless you have access to
an
> >> >XRF or similar device though, you won't know how far you've gone.
> >> >
> >> >Sure, reject it all back to the fabricator, have them restart the job,
> >put
> >> >everything on a back burner, or better yet, find another supplier,
> >resubmit
> >> >gerber, have them do it, of course you'll want to survey them first,
> >gotta
> >> >remember to schedule that before we give them the order.
> >> >
> >> >~...hmmmm, wondering if I'm being too facetious, nah, not with this
> >group,
> >> >they can appreciate the humor in this....grinning~
> >> >
> >> >Franklin
> >> >
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Date:         Mon, 20 Mar 2000 10:19:22 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hamilton, Richard CLE 4454" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
Subject:      Land Pattern for LED PL-CC-2
MIME-Version: 1.0
Content-Type: text/plain

Does anyone happen to have a suggested land pattern for an LED by Siemens
identified as an PL-CC-2?

Thanks in advance!

Richard Hamilton
Clemar Mfg. / Rain Bird
[log in to unmask]

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Date:         Mon, 20 Mar 2000 12:29:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Pat Kane <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Grant

As with any material selection process, proper evaluation must be undertaken
to determine the end result, -  which is a controlled process providing
reliable product to the field.
In the case of NoClean flux and conformal coating, the primary effort should
be focused at insuring compatibility between your flux and the conformal
coating selected.  The flux vendor should be able to provide data showing lab
testing that indicates the types of conformal coating their flux works with
and ones that don't.

As with any flux, OA or NC, a proper reflow profile to fully activate is
critical.  Un-reacted flux will pose a problem with adhesion of conformal
coatings.

Surface cleanliness for incoming bare boards, in process, and prior to
coating should be investigated to determine if you have the best possible
situation for good coating adhesion.
If you would like to discuss these issues offline, please contact me.

Regards,

Pat Kane
Technical Sales Manager
Contamination Studies Laboratories
765-457-8095   office
765-419-2080   cell

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Date:         Mon, 20 Mar 2000 10:04:52 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      Re: Strange email...
X-To:         "Stephen R. Gregory" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

I got one too, a reply to a posting I had made to the Technet. I assume it's
harmless...just a case of the Internet, or some small part of it, telling me
it had a hard time delivering my message.
Tim Reeves
> ----------
> From:         Stephen R. Gregory
> Sent:         Saturday, March 18, 2000 6:31
> Subject:      Strange email...
>
> Good morning everybody!
>
> Below, I've pasted a message that was waiting in my mailbox for me this
> morning. It had a attachment with it (that I didn't open). Is anybody else
> getting these? I know of a couple people that have, but I'm wondering if
> everybody is? Looking at the email address, and the attachment has me
> worried...also the comment in the message; "may be forged".
>
> Just curious...
>
> -Steve Gregory-
>
> Subj:    Returned mail: Too many hops 305 (30 max): from <@pub
> Date:   03/18/2000 4:43:00 AM Central Standard Time
> From:   [log in to unmask] (Mail Delivery Subsystem)
> To: [log in to unmask], [log in to unmask]
>
> File:  Returned.mim (59131 bytes)
> DL Time (37333 bps): < 1 minute
>
> [This e-mail contains a MIME (Multipurpose Internet Mail Extensions) file.
> The file was specially formatted to be sent over the Internet.  For more
> information on opening the attached file, go to Keyword: MIME.]
> --------------------
> The original message was received at Sat, 18 Mar 2000 04:44:18 -0600 (CST)
> from pop2.guangzhou.gd.cn [202.96.128.113] (may be forged)
>
>    ----- The following addresses had permanent fatal errors -----
> <[log in to unmask]>
>
>    ----- Transcript of session follows -----
> 554 Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
>
>
> ----------------------- Headers --------------------------------
> Return-Path: <>
> Received: from  rly-yg02.mx.aol.com (rly-yg02.mail.aol.com [172.18.147.2])
> by
> air-yg05.mail.aol.com (v70.19) with ESMTP; Sat, 18 Mar 2000 05:43:00 -0500
> Received: from  mail.ipc.org (mail.ipc.org [216.203.207.34]) by
> rly-yg02.mx.aol.com (v70.20) with ESMTP; Sat, 18 Mar 2000 05:42:45 -0500
> Received: from localhost (localhost)
>     by mail.ipc.org (8.8.8+Sun/8.8.8) with internal id EAB27092;
>     Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> Date: Sat, 18 Mar 2000 04:44:26 -0600 (CST)
> From: Mail Delivery Subsystem <[log in to unmask]>
> Message-Id: <[log in to unmask]>
> To: <[log in to unmask]>
> To: [log in to unmask]
> MIME-Version: 1.0
> Content-Type: multipart/report; report-type=delivery-status;
>     boundary="EAB27092.953376266/mail.ipc.org"
> Subject: Returned mail: Too many hops 305 (30 max): from
> <@public.guangzhou.gd.cn:[log in to unmask]> via pop2.guangzhou.gd.cn, to
> <[log in to unmask]>
> Auto-Submitted: auto-generated (failure)
>

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Date:         Mon, 20 Mar 2000 18:03:19 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         "Kelly M. Schriver" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Kelly,

I must challenge your statement:

> "be applied satisfactorily over the
> leavings of low residue flux, or any other residue, could only be
considered
> valid if the conformal coating had been retested and passed  the
> qualification requirements of IPC-CC-830, MIL-I-46058, or whatever
> specification"

This is misleading as it implies that any coating so tested is OK to apply
over no-clean. NOT SO! These specifications require testing of the material
on its own, in isolation on coupons that have been cleaned until they
squeak - there shall be no flux present!

In order to successfully coat over no-clean - and it can be done - you MUST
test the entire process with totally representative coupons of YOUR process.

Consider that a conformal coating is a permanent product to do a permanent
job and seals in as well as out and bingo - if you have something nasty
underneath, then it matters not one jot the specification approvals the
coating may have.

I repeat, it can be done, but I did not say it was easy or straightforward.

Regards :-)
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227
----- Original Message -----
From: Kelly M. Schriver <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 12:29 PM
Subject: Re: [TN] Coating of assemblies with no clean fluxes


> Mornin' Grant & All -
>
> The argument that conformal coating can be applied satisfactorily over the
> leavings of low residue flux, or any other residue, could only be
considered
> valid if the conformal coating had been retested and passed  the
> qualification requirements of IPC-CC-830, MIL-I-46058, or whatever
> specification is valid in the case of that material.
>
> IMHO, any statements by the formulator of any of the materials which are
not
> supported by this data would have to be considered trivia.  I think we've
> all seen the cases of vessication, where the water molecule has passed
thru
> the vapor permeable barrier of the coating and attached itself to a
> contaminant on the surface of the board, creating a microscopic cluster of
> bubbles.  That is just one example of what may take place.
>
> Regards - Kelly
>
>
> -----Original Message-----
> From: Grant Emandien <[log in to unmask]>
> To: [log in to unmask] <[log in to unmask]>
> Date: Monday, March 20, 2000 3:29 AM
> Subject: [TN] Coating of assemblies with no clean fluxes
>
>
> >Hi all,
> >
> >The debate on cleaning of fluxes as well as the use no-clean fluxes seems
> to
> >hang around forever. We have been informed by our solder an flux supplier
> >that assemblies with no clean fluxes can be conformally coated without
the
> >need to clean the boards.
> >
> >The argument is that the high temperatures of the reflow oven 'burns off'
> >the active ingredients, leaving only inactive residues. These flux
residues
> >do not have to be cleaned and can supposedly be coated. The rep. believes
> we
> >are taking a backward step by possibly opting to use water-based flux. Is
> >this pure sales talk?
> >
> >Is anyone able to offer any advice or insight, or been able to assess the
> >environmental and electrical performance of such assemblies.
> >
> >Regards
> >Grant
> >
> >##############################################################
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> >If you need assistance - contact Keach Sasamori at [log in to unmask] or
> >847-509-9700 ext.5315
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=========================================================================
Date:         Mon, 20 Mar 2000 10:12:24 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      listserv strangeness
MIME-Version: 1.0
Content-Type: text/plain

I'm now getting duplicates of messages I got last week (such as this one).
What's going on??
Tim Reeves
PS I'm also not on AOL . No way, no how, never.

> ----------
> From:         Werner Engelmaier
> Sent:         Wednesday, March 15, 2000 19:53
> Subject:      Re: VOC legislation
>
> In a message dated 3/15/00 10:07:16, [log in to unmask] writes:
> >Al Gore did not make this statement.  I think you are referring to Dan
> >Quayle's quote :
> >If we do not succeed, then we run the risk of failure.
> >-- Vice President Dan Quayle, to the Phoenix Republican Forum, 3/23/90
> >(reported in Esquire, 8/92) Also reported by Reuters, 5/2/90
> >Lets not make fun of our future President!
> Hi Todd,
> while I would not want Dan Quayle as my president, do you really want
> somebody so self-delusional as to believe he invented the Internet? did
> you
> see how Stephen Hawkings put Gore down during his White House visit?
> Werner
>
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> additional
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Date:         Mon, 20 Mar 2000 12:38:06 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hamilton, Richard CLE 4454" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
Subject:      OK,....what in the world?????
MIME-Version: 1.0
Content-Type: text/plain

Hello fellow TN junkies,

Talk about strange email.....I have posted two emails earlier about 50
minutes apart about 2 hours ago. I got the normal acceptance email back
within minutes of posting and just now I got two notices (one for each email
sent) from IPC that tells me that the email I have *just* sent seems to be a
duplicate and is being returned to me.

Do I have something generating a second posting at my end, or are other
people seeing this 'thing' also? Talk about Space Camp!?

We had email problems last week and I did a sanity check with Steve (Thanks
by the way) which indicated that the problems were at my end. I am sorry if
the problem is at our end, but I am going bonkers (and 'screaming yellow' at
that!) here. My sanity is being challenged (AGAIN!). I thought me and my
therapist and mother got all that straightened out last week!? Shows ya what
I know!

Thanks for the patience.

Richard Hamilton
Clemar Mfg. / Rain Bird
[log in to unmask]

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=========================================================================
Date:         Mon, 20 Mar 2000 21:43:15 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gabriela Bogdan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gabriela Bogdan <[log in to unmask]>
Subject:      BGA TROUBLE
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi, TechNetters!
For some reason, my letter did not come through the first time (so I was
noticed by the list server).
I asked two questions:
1. The CS via plugging near BGA pads  was done with epoxy by
overprinting plugs over the vias. The plugs are higher than the BGA
pads. Is it OK for solder paste printing on the BGA pads?
2. Some BGA pads are dewetted, but not entirely. We observed this by
checking pad by pad. Our incoming inspection department does not reject
circuits with this degree of dewetting on normal SMT pads, and if the
problem arises during manufacturing, touch up is done. But with BGA it
is another story.
How do you deal with this problem?
Regards,
Gaby

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=========================================================================
Date:         Mon, 20 Mar 2000 12:54:37 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Spamwurst observation and some questions from the "good old boys"
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_000B_01BF926B.72AF24A0"

This is a multi-part message in MIME format.

------=_NextPart_000_000B_01BF926B.72AF24A0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

I totally agree with Phil Hinton. This, and other web based =
opportunities, have turned into a club with the most social members =
taking over. This is not to say technology, or other expertise, is not =
evident. It just means promotion and survival of the fittest with those =
less inclined, but none the less experts, dominates.=20

Phil has been a leader in our industry for many more years than most of =
you all - save Kelly, Brian, Paul, Werner, and many more older than dirt =
- and just as honest and knowledgeable. I only met him once, but have =
followed his exploits and endeavors for years as I once did Dr. Paul =
Craven and I do miss the old days where technology was power, instead of =
witty anecdotes.=20

No matter, the forum serves some well but I do miss more bare board =
expertise from those actually doing the hands on stuff. As for the =
argument about 1700 members I argue there probably would be many more =
but for the social convention applied, accepted, and vigilante enforced.

I would like to ask a few questions, if anyone will now reply.

1) What's the latest on direct laser imaging PCB details, etc.?

2) What's the latest/best first article film control under what =
conditions and with what alignment techniques?

3) What are the latest/best photoimaging systems available and why?

4) What has developed in the way of latest/best lamination techniques =
for high layer count, fine line MLB's with small vias, etc.?


Thanks for the opportunity to make the number jump a bit and you might =
ask whether I am going to build another damn board shop?

Enjoy Phil and all



------=_NextPart_000_000B_01BF926B.72AF24A0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3013.2600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>I totally agree with =
Phil Hinton.=20
This, and other web based opportunities, have turned into a club with =
the most=20
social members taking over. This is not to say technology, or other =
expertise,=20
is not evident. It just means promotion and survival of the fittest with =
those=20
less inclined, but none the less experts, dominates. </FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Phil has been a leader =
in our=20
industry for many more years than most of you all - save Kelly, Brian, =
Paul,=20
Werner, and many more older than dirt - and just as honest and =
knowledgeable. I=20
only met him once, but have followed his exploits and endeavors for =
years as I=20
once did Dr. Paul Craven and I do miss the old days where technology was =
power,=20
instead of witty anecdotes. </FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>No matter, the forum =
serves some well=20
but I do miss more bare board expertise from those actually doing the =
hands on=20
stuff. As for the argument about 1700 members I argue there probably =
would be=20
many more but for the social convention applied, accepted, =
and&nbsp;vigilante=20
enforced.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>I would like to ask a =
few questions,=20
if anyone will now reply.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>1) What's the latest on =
direct laser=20
imaging PCB details, etc.?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>2) What's the =
latest/best first=20
article film control under what conditions and with what alignment=20
techniques?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>3) What are the =
latest/best=20
photoimaging systems available and why?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>4) What has developed =
in the way of=20
latest/best lamination techniques for high layer count, fine line MLB's =
with=20
small vias, etc.?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Thanks for the =
opportunity to make=20
the number jump a bit and you might ask whether I am going to build =
another damn=20
board shop?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Enjoy Phil and =
all</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

------=_NextPart_000_000B_01BF926B.72AF24A0--

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=========================================================================
Date:         Mon, 20 Mar 2000 13:01:14 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Perkins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Perkins <[log in to unmask]>
Subject:      Voids in BGA Balls after reflow
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="----_=_NextPart_000_01BF92AF.6FA51E4C"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_000_01BF92AF.6FA51E4C
Content-Type: text/plain;
        charset="iso-8859-1"

Hello Technetters

        Recently with the help of a high end piece of x-ray equipment we
have noticed voids in the spheres of the bga after reflow, "see
attachment-file".  Has anyone seen this before, or has any idea how the
voids are created?  Also does anyone know if this is a bad or good thing?
Does anyone have any recommendations to the profile?


Thanks
        Bob Perkins
        Automation Technician/Manufacturing Engineer
        Aimtronics
        [log in to unmask]


 <<wboard6.jpg>>

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=========================================================================
Date:         Tue, 21 Mar 2000 08:16:00 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Van Hoang Dinh <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Van Hoang Dinh <[log in to unmask]>
Organization: AEMS
Subject:      Solder Ball
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Good morning all,

1.Anyone known where can I look for a definition of ELECTRICAL DESIGN =
CLEARANCE ?

2.How we define or experiment test to prove that the solder balls are =
entrapped and not cause a solder ball to become dislodged?

THANKS ALL

VAN=20


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Content-Type: text/html;
        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Good morning all,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>1.Anyone known where can I look for a definition of =
ELECTRICAL=20
DESIGN CLEARANCE ?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>2.How we&nbsp;define or experiment test to prove =
that the=20
solder balls are entrapped and not cause a solder ball to become=20
dislodged?</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>THANKS ALL</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>VAN</FONT>&nbsp;</DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

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Date:         Sun, 19 Mar 2000 23:57:57 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Yehuda Weisz <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Yehuda Weisz <[log in to unmask]>
Subject:      - IPC-7095
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Hi everyone,
I have received today a printout of the IPC-7095 working draft.
I wonder if anyone has it on a file and would be kind enough to send it =
to me, since most of the pictures on the printout are not readable.

Thanks,
Yehuda Weisz

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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi everyone,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I have received today a printout of the =
IPC-7095=20
working draft.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I wonder if anyone has it on a file and =
would be=20
kind enough to send it to me, since most of the pictures on the printout =
are not=20
readable.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Thanks,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Yehuda Weisz</FONT></DIV></BODY></HTML>

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Date:         Mon, 20 Mar 2000 14:05:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              phil bavaro <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         phil bavaro <[log in to unmask]>
Subject:      Electrolytic Capacitor Staking Requirements
X-cc:         [log in to unmask]
Mime-Version: 1.0
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OK, I know, I know. Why is anyone still using thru hole parts which have to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that the
vibration does not sever the two leads on these parts.  Historically I have
always asked that these be bonded 360 degrees around the perimeter and a
minimum of 50%, up to a maximum of 100% of the height of the part using a
thixotropic UV cure adhesive.  This way the part could not bend or move at
all.

Using this criteria, I have never seen a failure as a result of the bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time
of course) so that just it connects the board and the bottom of the part
only (maybe as high as .15" total which only allows about .10" of contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the adhesive
has broken loose from the pwb on at least five out of the seven parts and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome.


-----------------------------------------------------
Click here for Free Video!!
http://www.gohip.com/freevideo/

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Date:         Mon, 20 Mar 2000 15:53:21 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Earl Moon <[log in to unmask]>
Subject:      Spamwurst observation and some questions from the "good old
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Hell Paul,

You are dirt, so don't go digging it, just as me. Great to see from you. =
No, I'll never build another but might assist with your assistance and =
some of the good old boys. .

It still all seems the same as so many years past, but for some tweaking =
and innovations, but who's counting.

Anyway, let me know the latest scoop. This academic stuff is driving me =
into the dirt.

Earl

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        charset="iso-8859-1"
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<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Hell Paul,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>You are dirt, so don't =
go digging it,=20
just as me. Great to see from you. No, I'll never build another but =
might assist=20
with your assistance and some of the good old boys. .</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>It still all seems the =
same as so=20
many years past, but for some tweaking and innovations, but who's=20
counting.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Anyway, let me know the =
latest scoop.=20
This academic stuff is driving me into the dirt.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=3D#000000 face=3DArial =
size=3D2>Earl</FONT></DIV></BODY></HTML>

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Date:         Tue, 21 Mar 2000 00:42:50 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gabriela Bogdan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gabriela Bogdan <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         Bob Perkins <[log in to unmask]>
MIME-Version: 1.0
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Bob,
You can search the TechNet archives for voids in BGA solder balls.
Max .allowed voids is about 20% of the ball volume, if I remember well from
the draft of IPC7095.
Bad thing is when the voids are at the interface between ball and component
pad or board. I have also a "High end" x-ray equipment, and to my great
amusement I can make voids appear , disappear and grow depending on voltage
and current. Make sure that your picture is not "overworked" and that what you
see is the real thing. If it is, it seems bad to me. Just for comparison, you
can perform a cross section on a ball with big voids.
Gaby

Bob Perkins wrote:

> Hello Technetters
>
>         Recently with the help of a high end piece of x-ray equipment we
> have noticed voids in the spheres of the bga after reflow, "see
> attachment-file".  Has anyone seen this before, or has any idea how the
> voids are created?  Also does anyone know if this is a bad or good thing?
> Does anyone have any recommendations to the profile?
>
> Thanks
>         Bob Perkins
>         Automation Technician/Manufacturing Engineer
>         Aimtronics
>         [log in to unmask]
>
>  <<wboard6.jpg>>
>
>   ------------------------------------------------------------------------
>                   Name: wboard6.jpg
>    wboard6.jpg    Type: JPEG Image (image/jpeg)
>               Encoding: base64

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Date:         Mon, 20 Mar 2000 18:01:01 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Creswick <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Creswick <[log in to unmask]>
Subject:      Re: Needed: NJ/PA Area Acoustic Microscopy Laboratory Services
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Tim,

It is semi-close.  Check out Sonix

John Goings
Sonix
8700 Morrissette Drive
Springfield, VA  22152
Ph (703) 440-0222 ext 155
Fx (703) 440-9512

I have one of their machines.  Works very well.

Steven Creswick - CTS RF Integrated Modules


At 10:25 AM 3/20/00 -0500, you wrote:
>Hey everyone!
>
>We are located in West Trenton, NJ and we need a local service lab that has
>Acoustic Microscopy capabilities.
>Can anyone recommend a lab with these capabilities?
>
>Thanks!
>Tim Tezak
>
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Date:         Mon, 20 Mar 2000 17:10:12 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Yuen, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Yuen, Mike" <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         Gabriela Bogdan <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I would like to get a new copy of IPC 7095. Who is the chairperson for that
committee?

Thanks,
M. Yuen

                -----Original Message-----
                From:   Gabriela Bogdan [mailto:[log in to unmask]]
                Sent:   Monday, March 20, 2000 4:43 PM
                To:     [log in to unmask]
                Subject:        Re: [TN] Voids in BGA Balls after reflow

                Bob,
                You can search the TechNet archives for voids in BGA solder
balls.
                Max .allowed voids is about 20% of the ball volume, if I
remember well from
                the draft of IPC7095.
                Bad thing is when the voids are at the interface between
ball and component
                pad or board. I have also a "High end" x-ray equipment, and
to my great
                amusement I can make voids appear , disappear and grow
depending on voltage
                and current. Make sure that your picture is not "overworked"
and that what you
                see is the real thing. If it is, it seems bad to me. Just
for comparison, you
                can perform a cross section on a ball with big voids.
                Gaby

                Bob Perkins wrote:

                > Hello Technetters
                >
                >         Recently with the help of a high end piece of
x-ray equipment we
                > have noticed voids in the spheres of the bga after reflow,
"see
                > attachment-file".  Has anyone seen this before, or has any
idea how the
                > voids are created?  Also does anyone know if this is a bad
or good thing?
                > Does anyone have any recommendations to the profile?
                >
                > Thanks
                >         Bob Perkins
                >         Automation Technician/Manufacturing Engineer
                >         Aimtronics
                >         [log in to unmask]
                >
                >  <<wboard6.jpg>>
                >
                >
------------------------------------------------------------------------
                >                   Name: wboard6.jpg
                >    wboard6.jpg    Type: JPEG Image (image/jpeg)
                >               Encoding: base64


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Date:         Tue, 21 Mar 2000 01:15:02 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gabriela Bogdan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gabriela Bogdan <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         "Yuen, Mike" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Mike, I don't know if there is a final document. I got a copy some days ago, but it is
a draft, which was presented by an IPC trainer, and ,as YEHUDA mentioned, almost
unreadable.
Gaby

"Yuen, Mike" wrote:

> I would like to get a new copy of IPC 7095. Who is the chairperson for that
> committee?
>
> Thanks,
> M. Yuen
>
>                 -----Original Message-----
>                 From:   Gabriela Bogdan [mailto:[log in to unmask]]
>                 Sent:   Monday, March 20, 2000 4:43 PM
>                 To:     [log in to unmask]
>                 Subject:        Re: [TN] Voids in BGA Balls after reflow
>
>                 Bob,
>                 You can search the TechNet archives for voids in BGA solder
> balls.
>                 Max .allowed voids is about 20% of the ball volume, if I
> remember well from
>                 the draft of IPC7095.
>                 Bad thing is when the voids are at the interface between
> ball and component
>                 pad or board. I have also a "High end" x-ray equipment, and
> to my great
>                 amusement I can make voids appear , disappear and grow
> depending on voltage
>                 and current. Make sure that your picture is not "overworked"
> and that what you
>                 see is the real thing. If it is, it seems bad to me. Just
> for comparison, you
>                 can perform a cross section on a ball with big voids.
>                 Gaby
>
>                 Bob Perkins wrote:
>
>                 > Hello Technetters
>                 >
>                 >         Recently with the help of a high end piece of
> x-ray equipment we
>                 > have noticed voids in the spheres of the bga after reflow,
> "see
>                 > attachment-file".  Has anyone seen this before, or has any
> idea how the
>                 > voids are created?  Also does anyone know if this is a bad
> or good thing?
>                 > Does anyone have any recommendations to the profile?
>                 >
>                 > Thanks
>                 >         Bob Perkins
>                 >         Automation Technician/Manufacturing Engineer
>                 >         Aimtronics
>                 >         [log in to unmask]
>                 >
>                 >  <<wboard6.jpg>>
>                 >
>                 >
> ------------------------------------------------------------------------
>                 >                   Name: wboard6.jpg
>                 >    wboard6.jpg    Type: JPEG Image (image/jpeg)
>                 >               Encoding: base64
>
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Date:         Mon, 20 Mar 2000 17:30:41 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jerry Cupples <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jerry Cupples <[log in to unmask]>
Subject:      Re: Solder Ball
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/enriched; charset="us-ascii"

At 08:16 AM 3/21/00 +1100, you wrote:

>>>>

<smaller>Good morning all,

</smaller>

<smaller>1.Anyone known where can I look for a definition of ELECTRICAL
DESIGN CLEARANCE ?

</smaller>

<smaller>2.How we define or experiment test to prove that the solder
balls are entrapped and not cause a solder ball to become dislodged?

</smaller>

<smaller>THANKS ALL

</smaller>

<smaller>VAN</smaller>




<<<<<<<<


Typically the specification regarding solderballs is that they cannot
reduce the design clearance by more than some percentage, 50% being one
common callout.


This would mean that if the minimum conductor clearance on the board is
for instance 0.006"(as, 0.006" lines and spaces, without solder mask),
the maximum size of a solder ball (or any conductive foreign material) is
0.003". You could always simply measure the minimum spacing of the finest
pitch component leads or other exposed conductive circuitry on the board.
This would be the "minimum electrical clearance".


And again, I have seen some specifications which forgive any solderball
which is "entrapped in flux" from this requirement. As to the test for
this condition, I'm sure it is vague, and will remain so. I've never seen
any solder ball which could not be dislodged with the right tool and
enough force. My opinion is that these specifications are intended to
exclude solderballs which would not become dislodged with normal handling
and accelerative forces of benign vibration.


If you wish to make an experimental test of your own, I might suggest
that you take a small DC motor fan, fix it to the board in question,
grind or break the blade of the prop to cause it to vibrate. Let it run
in this fashion overnight, and see whether the solderballs stay in
place.


B&K and other audiometric analyzers have attachments to measure the
amplitude and acceleration of vibration, but doing this measurement is
non-trivial. I'm only guessing as to the end use application of the
question, and what the customer might perceive as a reasonable screening
test.


If you are asking for relief from a specification, it is best to do so
with some type of test results in hand.



cheers,



Jerry Cupples

(good old boy at heart)

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Date:         Tue, 21 Mar 2000 10:43:10 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

No need to be so "why anyone" , me one of them, not feelin any shorter .
1
in short no, yo should NOT yield, surviving HALT hanging on one hair "pass"
is hardly the way .
Me the humble inquisitor would seriously question any HALT validation
procedure which would NOT include final visual.
It's clearly no pass, regardless of electrical pass ;
UNLESS the halt is an actual simulation life limit (which i doubt, from the
sound of it) .
2
One cure which i did on numerous designs (PS's main offenders)coping with
G's ;
spread those cans to more of lower ones, if you have the real estate and
budget .
Easy way out (still flooded!),
3
If you can't (likely),
than you have to lecture your keen freshling about basics of force vectors;
hopefully he's physically minded and will be able to understand that a TV
buried in sand is proportionally more stable and not prone to tipping over
to the depth of sink in (hate TV lately, endless bull, pardon the
reminiscence);
the force spread of vertical, diagonal and horizontal vectors in both
negative & positive/pull & push/adhesion & compression/ is not a rocket
science to calculate .

Been through this often enough, DO NOT BUDGE,
this relatively naive physics do account for a lot of recall disasters .
Funny part is the after recall "topping up" does have different signature
again,
remember once the top up layer not quite bonding working it's way out in no
time .

address the procedure (it's almost clearly wrong), than explanation (fault &
why = calculus),
than set the freshling from reinventing the wheel.

Feel with yo, have this "efficient" new age pupils paddling fast circles
around me all the time,
sometimes for years before they realize breaking ice is not for knockers .
Keep a diary , management 's got often selective RAM's .

cu                paul

-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Tuesday, 21 March 2000 9:05
To: [log in to unmask]
Subject: [TN] Electrolytic Capacitor Staking Requirements


OK, I know, I know. Why is anyone still using thru hole parts which have to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that the
vibration does not sever the two leads on these parts.  Historically I have
always asked that these be bonded 360 degrees around the perimeter and a
minimum of 50%, up to a maximum of 100% of the height of the part using a
thixotropic UV cure adhesive.  This way the part could not bend or move at
all.

Using this criteria, I have never seen a failure as a result of the bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time
of course) so that just it connects the board and the bottom of the part
only (maybe as high as .15" total which only allows about .10" of contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the adhesive
has broken loose from the pwb on at least five out of the seven parts and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome.


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Date:         Mon, 20 Mar 2000 13:10:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hollandsworth, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hollandsworth, Ron" <[log in to unmask]>
Subject:      Subj:  Test Equipment Fab/Suppliers
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello TechNet:
I have a question concerning Fabricators/Suppliers in the U.K., for Test
Equipment and Thermal Chambers.

I would like the Web sites if possible, or names of suppliers.

I am not looking for advertising, sales pitches, etc., just the web site
address or name of potential companies.

This is not for spamming, but a ligitimate question.

You can even send e:mail directly to me at:  [log in to unmask]

Thanks
Ron Hollandsworth
Ops Task Leader AME Group
ITT A/CD

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Date:         Mon, 20 Mar 2000 17:01:58 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Keel, Mike" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Keel, Mike" <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

You know you are right.
This looks like a good example of
A less than optimal part being selected;
The mfg guys make it work good. (no failures)
New guys show up and say,
"You guys aren't doing it like that are you ? ?"
"It's really not necessary."
So methods are changed to reflect "current policy".
Then  --  wait for it  . . .
The failures show up in the field and we start the process all over again.
What a fantastic revenue enhancement tool.
Planned Failure Mode
Good luck Phil
I have the feeling you have been around this block before.



                -----Original Message-----
                From:   phil bavaro [mailto:[log in to unmask]]
                Sent:   Monday, March 20, 2000 10:05 PM
                To:     [log in to unmask]
                Subject:        [TN] Electrolytic Capacitor Staking
Requirements

                OK, I know, I know. Why is anyone still using thru hole
parts which have to
                be bonded to the board......!!

                Well. all I can say is that we are and the question I have
for this group
                is what are the requirements for how much and how high.

                Here's the background info:

                An automotive electronics circuit card has about seven very
tall
                electrolytic caps on it which need to be secured to the
board so that the
                vibration does not sever the two leads on these parts.
Historically I have
                always asked that these be bonded 360 degrees around the
perimeter and a
                minimum of 50%, up to a maximum of 100% of the height of the
part using a
                thixotropic UV cure adhesive.  This way the part could not
bend or move at
                all.

                Using this criteria, I have never seen a failure as a result
of the bonding.

                Here's the problem:

                A new engineer decides to minimize the adhesive amount (due
to cycle time
                of course) so that just it connects the board and the bottom
of the part
                only (maybe as high as .15" total which only allows about
.10" of contact
                to the body of the part.  These parts are .75" tall.  The
new engineer
                feels justified because the products which were bonded this
way made it
                thru a HALT test exposure without electrical failures.

                I look at the assemblies which are supposedly OK and find
that the adhesive
                has broken loose from the pwb on at least five out of the
seven parts and
                what is remaining on the parts have fracture lines as well.

                I consider this condition unacceptable and feel that after
environmental
                testing, adhesive bonding should remain intact 100%.

                Am I right or should I yield since the assemblies made it
thru the HALT
                testing?  What bonding requirements do you impose for these
type of parts

                All comments are welcome.


                -----------------------------------------------------
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                http://www.gohip.com/freevideo/


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Date:         Mon, 20 Mar 2000 18:39:56 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         Bob Perkins <[log in to unmask]>

Bob,
        Those voids are too big.  Since many of the voids are near the edges
of the spheres, you may get some of them out will a little more time in
reflow.  (However, other voids will become larger when two or more small
voids combine).  Most voids will never come out of the BGA sphere because it
has nowhere to go but up to the pads on the BGA side.

        As a general rule, voids are bad.  The small voids in your X-ray
photo have been shown by a Motorola study (SMI 96 Proceedings) to be better
for joint reliability.  But as Gabriela said, there is a limit to the size
the void can be.

        The best explanation I have found for the source of voids is Dr
Lee's flux exclusion rate theory.  You can view his paper that was presented
in SMT magazine (Jan 96) at Indium's web site.  If you don't want to read
the paper, the two sentence summary is:  voids are caused by entrapped flux,
and flux residue.  (Note that entrapped flux will still volatize).  Since
paste does not transform from solidus to liquidus instantaneously, (much
like melting ice cubes), the liquid solder will drive the flux and flux
residue out of the solid solder powder until all of the solder powder is
liquid.  The less viscous the flux and residue is, the less likely it will
get entrapped by the liquefying solder.

        If you have the luxury of using Nitrogen, that will help control
voids immensely.  This is because it reduces the amount of oxidation that
occurs, thus reducing the amount of gummy residue that is generated.  (Gummy
residue is more viscous, so it does not move out of the paste as easily.)

        Certain paste will control voids as well.  There is an aqueous paste
that is advertised as reducing voids in BGA balls.  (They advertise in SMT
and Circuits Assembly).  I have used this paste and it does work to control
voids.

        As far as the reflow profile, I think it is still somewhat of a
black art.  (even with the flux exclusion rate theory.)  You will just have
to play around with it a bit.  I have not found anyone who has explained the
dynamics required to reduce BGA voids with the profile, and I haven't had
time to try out my own theories.  i.e.. reducing the time to reflow and
slowing down the reflow spike.

Good luck.  (I would be interested in hearing what you end up doing).

Ryan Grant

> -----Original Message-----
> From: Bob Perkins [SMTP:[log in to unmask]]
> Sent: Monday, March 20, 2000 2:01 PM
> To:   [log in to unmask]
> Subject:      [TN] Voids in BGA Balls after reflow
>
> Hello Technetters
>
>         Recently with the help of a high end piece of x-ray equipment we
> have noticed voids in the spheres of the bga after reflow, "see
> attachment-file".  Has anyone seen this before, or has any idea how the
> voids are created?  Also does anyone know if this is a bad or good thing?
> Does anyone have any recommendations to the profile?
>
>
> Thanks
>         Bob Perkins
>         Automation Technician/Manufacturing Engineer
>         Aimtronics
>         [log in to unmask]
>
>
>  <<wboard6.jpg>> << File: wboard6.jpg >>

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Date:         Mon, 20 Mar 2000 21:33:25 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Bob,
Voids in BGA solder balls (near eutectic, not high melt) after reflow are
normal, but not before reflow.
Voids in the balls prior to reflow reduce the available solder volume, which
may cause opens if large enough.
Voids after reflow are caused by flux/flux action volatiles being trapped by
the horizontal component pads and occur because most BGA solder balls are
barely long enough in the liquid state to produce adequate wetting (and
sometimes not).
Voids are typically in the upper half (near the component) of the balls.
All indications are that the typically occurring voids (not too large, and
not porosities near the interface) do not present a reliability problem; in
fact there are some studies that show some (not significant enough to go for
voids on purpose) increase in life. The possible reasons for this are 1) an
increased solder joint height for a fixed solder volume, 2) the localized and
temporary retardation of the crack propagation by the voids (a la Liberty
Bell).
However, if you need thermal conduction or electrical current carrying
capacity, you definitely do not want voids.
Higher temperatures and longer times in the liquid state will reduce voids,
as well some fluxes/pastes.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Tue, 21 Mar 2000 15:55:30 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "[log in to unmask]" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "[log in to unmask]" <[log in to unmask]>
Subject:      Question: Film to Gerber - how?
In-Reply-To:  <000901bf8954$f2bb90e0$6400a8c0@franklin>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Hi Ya'll,

I got again this old problem. I have the films, but need the Gerberdata. Is
there a way to do it without making a complete new design?

Regards

Jens Behrens

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Date:         Tue, 21 Mar 2000 09:33:51 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         Bob Perkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Yes, Bob,
well recognized. We were stunned by solder balls looking like rotten teeth after the soldering/cleaning process. Typical was that all the "caries"  holes were on one and the same side of all balls. Explanation: a)the balls consisted of two zones with different grain phases, caused by the BGA maker's production method. b)we used a flux cleaner that dissolved poor grain bindings in this two-zone interface and the result looked like what happens when a mouse takes a bite in the cheese. Well, there is a whole report about it and MOTA changed the ball concept, since then I have heard of no more such problems. If you want some pictures for comparison, I can send to you, Bob.

It's strange that we still get some soldering problems after decades of knowledge about the processes. One reason may be this: old 'goodies' disappear, newcomers more interested in IT and stockholding affairs. I knew such an ol' goodie at a company, a metalurgical dr from Germany, he WAS soldering personified (devotion and deepest interest), but when he retired noone took over, the lab personel was spread and the new bosses spent no more money. Many new in the game just scrap the surface of the mystery of soldering. Luckily, we have TWI, IM and other institutions nearby, in US there is China Lake, Sandia, Rome, IBM and....and Klein Wassink's soldering bible...oceans of knowhow for those who like digging after treasures.

I take the opportunity to ask about silver adhesive vs. soldering. Just wonder how many percents of the worlds component mounting is done with adhesives instead of solders. The adhesive makers claim that their products fit well for most applications, but many, many hesitate to change from solder to 'glue'. I don't ask for a storm of pros and againsts...not at all, just a qualified guessing from someone: how many percents? What do you think? 5%?

There is a risk that some oldies will talk, how do we stop them? (He-he)

Ingemar Hernefjord
Ericsson Microwave Systems

-----Original Message-----
From: Bob Perkins [mailto:[log in to unmask]]
Sent: den 20 mars 2000 22:01
To: [log in to unmask]
Subject: [TN] Voids in BGA Balls after reflow


Hello Technetters

        Recently with the help of a high end piece of x-ray equipment we
have noticed voids in the spheres of the bga after reflow, "see
attachment-file".  Has anyone seen this before, or has any idea how the
voids are created?  Also does anyone know if this is a bad or good thing?
Does anyone have any recommendations to the profile?


Thanks
        Bob Perkins
        Automation Technician/Manufacturing Engineer
        Aimtronics
        [log in to unmask]


 <<wboard6.jpg>>

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Date:         Tue, 21 Mar 2000 09:17:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Aldrich <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         [log in to unmask]
MIME-version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-transfer-encoding: quoted-printable

Was this a cohesive failure (cracks in the adhesive) or an adhesive=20=
failure (separation of the adhesive from the substrate)

For cohesive failures, you may want to look at the curing method to=20=
ensure all of the material is fully cured, especially with UV curable=20=
adhesives=2E  You also may want to evaluate the ductility of the cured=20=
adhesive=2E  For example, elastomeric silicones (RTV's) may be a better=20=
option than some epoxies which could be more brittle=2E  Reference=20=
IPC-A-610 rev C (new rev), section 4=2E4=2E2 and 4=2E4=2E3 for acceptance=20=
criteria for adhesive bonding=2E  Depending on whether the components=20=
are mounted above the board, 20% to 25% of the circumference needs to=20=
be bonded, and either 50% of the component height needs to be bonded,=20=
or the bottom and sides (w/ no height requirement)=2E

Just some ideas to look for=2E

For adhesive failures, the root of the problem is probably cleanliness=20=
or unsuitable adhesive material=2E

Also, make sure this adhesive material is intended for electronic=20=
applications=2E

Hope this helps=2E

Mike Aldrich
AMETEK Aerospace


______________________________ Reply Separator _________________________________
Subject: [TN] Electrolytic Capacitor Staking Requirements
Author:  MIME:pbavaro@QUALCOMM=2ECOM at INTERNET
Date:    3/20/2000 5:06 PM


OK, I know, I know=2E Why is anyone still using thru hole parts which have to=20=
be bonded to the board=2E=2E=2E=2E=2E=2E!!

Well=2E all I can say is that we are and the question I have for this group=20=
is what are the requirements for how much and how high=2E

Here's the background info:

An automotive electronics circuit card has about seven very tall=20=
electrolytic caps on it which need to be secured to the board so that the=20=
vibration does not sever the two leads on these parts=2E  Historically I have=20=
always asked that these be bonded 360 degrees around the perimeter and a=20=
minimum of 50%, up to a maximum of 100% of the height of the part using a=20=
thixotropic UV cure adhesive=2E  This way the part could not bend or move at=20=
all=2E

Using this criteria, I have never seen a failure as a result of the bonding=2E

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time=20=
of course) so that just it connects the board and the bottom of the part=20=
only (maybe as high as =2E15" total which only allows about =2E10" of contact=20=
to the body of the part=2E  These parts are =2E75" tall=2E  The new engineer=20=
feels justified because the products which were bonded this way made it=20=
thru a HALT test exposure without electrical failures=2E

I look at the assemblies which are supposedly OK and find that the adhesive=20=
has broken loose from the pwb on at least five out of the seven parts and=20=
what is remaining on the parts have fracture lines as well=2E

I consider this condition unacceptable and feel that after environmental=20=
testing, adhesive bonding should remain intact 100%=2E

Am I right or should I yield since the assemblies made it thru the HALT=20=
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome=2E


-----------------------------------------------------=20=
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Date:         Tue, 21 Mar 2000 10:45:10 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Douglas Pauls <[log in to unmask]>
Subject:      Re: Organic Contamination
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

In a message dated 03/20/2000 11:29:04 AM US Eastern Standard Time, CSLPAT
writes:

>
>  Does anyone have experience with IPC-TM-650 method 2.3.38?  This test is
> specified as a manual way to detect surface organics.  Our first attempt
> found that even the untested solution left a visual residue.  The
> acetonitrile is the grade specified, but we are unsure of what is expected.

> We do not have easy access to analysis equipment to determine the source of
> the residue.
>
>  Dave Kell
>

Dave.
This test is a "quick and dirty" (pardon the pun) test for surface organics,
but is largely a meaningless test (in my opinion).  For those not familiar
with the test, HPLC grade acetonitrile (a known carcinogen) is dripped onto a
test substrate (e.g. circuit board) and the runoff collected on a glass
microscope plate.  The solution is allowed to dry.  If you have visible
residue, then you have a "contaminant".  As you have found out, even the
virgin HPLC grade acetonitrile leaves a faint residue.

This test suffers the same problem that all extraction-based test have.
First, the soil you are interested in must be soluble in the extract
solution.  If it won't dissolve in acetonitrile, you won't see it.  Second,
it must be soluble in the amount of time you allow for the extraction.
Running a solution over the board surface gives you only a few seconds of
contact time.  Third, the soil must be soluble at the temperature you choose.
 If the soil does not solubilize easily with room temperature acetonitrile,
you won't see the residue.

Now you run into the problem of test interpretation.  So you get a visible
residue on the glass slide.  So what?!  Is it a good residue or a bad
residue.  You have no way of knowing.  You might use the visible residue
together with the FTIR method found in test method 2.3.39, which is a more
analytical method.  You might be able to determine what organic compound is
present, but you are still left with the question of whether it is a good
residue or a bad residue.  I would suggest that you pick up a copy of IPC
J-Handbook-001 and read section 8.  It goes over the various residue
detection methods and what they mean.  Many test labs offer FTIR analysis.  I
can suggest a few if you are interested.

About the only use I can see for method 2.3.38 is as a process control.  If
you were able to do this test repeatably in the past with no appreciable
visible residue, and now are finding visible residue, something changed and
you better investigate.

What ever possessed you to try this test?  Is there a larger problem that you
are investigating, such as conformal coating not sticking?  Why are you
looking for organics?

Doug Pauls
Technical Director
Contamination Studies Laboratories

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Date:         Tue, 21 Mar 2000 06:50:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: - IPC-7095
X-To:         Yehuda Weisz <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"

Yehuda, send me your email address and I will send you the info off line.
Ron Dieselberg
BAE SYSTEMS Cincinnati Electronics Corp.
[log in to unmask]

-----Original Message-----
From: Yehuda Weisz [mailto:[log in to unmask]]
Sent: Sunday, March 19, 2000 16:58
To: [log in to unmask]
Subject: [TN] - IPC-7095


Hi everyone,
I have received today a printout of the IPC-7095 working draft.
I wonder if anyone has it on a file and would be kind enough to send it to
me, since most of the pictures on the printout are not readable.

Thanks,
Yehuda Weisz

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Date:         Tue, 21 Mar 2000 07:14:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Phil, it sounds like the "new guy" needs to see the results of your
investigation. What good is the staking if it is cracked and/or not properly
adhering to the parts. Obviously the "new guy" needs to take some lessons
from the "old timer" who has been through it! What does upper management
say? What does the customer say? Are they willing to take the risk of
failure to save a few pennies of processing time. Can you company afford to
risk its reputation and good name by shipping an inferior product? I would
think not. Show the new guy why and how you arrived at your position.
Remember "hindsight is always 20/20".
Ron Dieselberg
BAE SYSTEMS Cincinnati Electronics Corp.

-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Monday, March 20, 2000 17:05
To: [log in to unmask]
Subject: [TN] Electrolytic Capacitor Staking Requirements


OK, I know, I know. Why is anyone still using thru hole parts which have to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that the
vibration does not sever the two leads on these parts.  Historically I have
always asked that these be bonded 360 degrees around the perimeter and a
minimum of 50%, up to a maximum of 100% of the height of the part using a
thixotropic UV cure adhesive.  This way the part could not bend or move at
all.

Using this criteria, I have never seen a failure as a result of the bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time
of course) so that just it connects the board and the bottom of the part
only (maybe as high as .15" total which only allows about .10" of contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the adhesive
has broken loose from the pwb on at least five out of the seven parts and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome.


-----------------------------------------------------
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Date:         Tue, 21 Mar 2000 13:08:46 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: OK,....what in the world?????
X-To:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hi Techies

Me to - what's going on??

Regards,
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227
----- Original Message -----
From: Hamilton, Richard CLE 4454 <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 7:38 PM
Subject: [TN] OK,....what in the world?????


> Hello fellow TN junkies,
>
> Talk about strange email.....I have posted two emails earlier about 50
> minutes apart about 2 hours ago. I got the normal acceptance email back
> within minutes of posting and just now I got two notices (one for each
email
> sent) from IPC that tells me that the email I have *just* sent seems to be
a
> duplicate and is being returned to me.
>
> Do I have something generating a second posting at my end, or are other
> people seeing this 'thing' also? Talk about Space Camp!?
>
> We had email problems last week and I did a sanity check with Steve
(Thanks
> by the way) which indicated that the problems were at my end. I am sorry
if
> the problem is at our end, but I am going bonkers (and 'screaming yellow'
at
> that!) here. My sanity is being challenged (AGAIN!). I thought me and my
> therapist and mother got all that straightened out last week!? Shows ya
what
> I know!
>
> Thanks for the patience.
>
> Richard Hamilton
> Clemar Mfg. / Rain Bird
> [log in to unmask]
>
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> information.
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> 847-509-9700 ext.5315
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>

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=========================================================================
Date:         Tue, 21 Mar 2000 13:11:34 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Coating assemblies with no-clean fluxes
X-To:         "Kelly M. Schriver" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_00A0_01BF9336.FB5F3120"

This is a multi-part message in MIME format.

------=_NextPart_000_00A0_01BF9336.FB5F3120
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        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Techies,

This was my posting that was rejected as already sent - but wasn't!?

Kelly,

I must challenge your statement:

> "be applied satisfactorily over the
> leavings of low residue flux, or any other residue, could only be
considered
> valid if the conformal coating had been retested and passed  the
> qualification requirements of IPC-CC-830, MIL-I-46058, or whatever
> specification"

This is misleading as it implies that any coating so tested is OK to =
apply
over no-clean. NOT SO! These specifications require testing of the =
material
on its own, in isolation on coupons that have been cleaned until they
squeak - there shall be no flux present!

In order to successfully coat over no-clean - and it can be done - you =
MUST
test the entire process with totally representative coupons of YOUR =
process.

Consider that a conformal coating is a permanent product to do a =
permanent
job and seals in as well as out and bingo - if you have something nasty
underneath, then it matters not one jot the specification approvals the
coating may have.

I repeat, it can be done, but I did not say it was easy or =
straightforward.

Regards :-)
Graham Naisbitt


Regards,
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227

------=_NextPart_000_00A0_01BF9336.FB5F3120
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2314.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Techies,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>This was my posting that was rejected as already =
sent - but=20
wasn't!?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Kelly,<BR><BR>I must challenge your =
statement:<BR><BR>&gt; "be=20
applied satisfactorily over the<BR>&gt; leavings of low residue flux, or =
any=20
other residue, could only be<BR>considered<BR>&gt; valid if the =
conformal=20
coating had been retested and passed&nbsp; the<BR>&gt; qualification=20
requirements of IPC-CC-830, MIL-I-46058, or whatever<BR>&gt;=20
specification"<BR><BR>This is misleading as it implies that any coating =
so=20
tested is OK to apply<BR>over no-clean. NOT SO! These specifications =
require=20
testing of the material<BR>on its own, in isolation on coupons that have =
been=20
cleaned until they<BR>squeak - there shall be no flux present!<BR><BR>In =
order=20
to successfully coat over no-clean - and it can be done - you =
MUST<BR>test the=20
entire process with totally representative coupons of YOUR=20
process.<BR><BR>Consider that a conformal coating is a permanent product =
to do a=20
permanent<BR>job and seals in as well as out and bingo - if you have =
something=20
nasty<BR>underneath, then it matters not one jot the specification =
approvals=20
the<BR>coating may have.<BR><BR>I repeat, it can be done, but I did not =
say it=20
was easy or straightforward.<BR><BR>Regards :-)<BR>Graham=20
Naisbitt<BR><BR></DIV></FONT>
<DIV><FONT size=3D2>Regards,<BR>Graham Naisbitt</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]
uk</A></FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>WEB: <A=20
href=3D"http://www.concoat.co.uk">http://www.concoat.co.uk</A></FONT></DI=
V>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>CONCOAT Ltd<BR>Alasan House, Albany =
Park<BR>CAMBERLEY GU15 2PL=20
UK</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Tel: +44 (0) 1276 691100&nbsp; Fax: +44 (0) 1276=20
691227</FONT></DIV></BODY></HTML>

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=========================================================================
Date:         Tue, 21 Mar 2000 06:48:20 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         "[log in to unmask]" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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By taking your films and having them scanned with a flatbed scanner i.e.
(ICON makes a good scanner),
but have someone do it that has done it in the past. There are ways of
making mistakes and could cost you scrap
if done incorrectly.

William W. DeCray III
Waytec Electronics Corp
Sales Engineer
PHONE:(804) 237-6391 ext 115
FAX:    (804) 237-1324
E-mail:<[log in to unmask]>
Web <http://www.waytec.com>
FTP <ftp://ftp.waytec.com>



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Tuesday, March 21, 2000 2:55 AM
To: [log in to unmask]
Subject: [TN] Question: Film to Gerber - how?


Hi Ya'll,

I got again this old problem. I have the films, but need the Gerberdata. Is
there a way to do it without making a complete new design?

Regards

Jens Behrens

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BEGIN:VCARD
VERSION:2.1
N:DeCray;Bill
FN:Bill DeCray
ORG:Waytec Electronics
TITLE:Methods Engineer
TEL;WORK;VOICE:(804) 237-6391
TEL;HOME;VOICE:(804) 525-2093
TEL;WORK;FAX:(804) 239-1324
ADR;WORK:;;1104 McConville Road;Lynchburg;Virginia;24506;United States =
of America
LABEL;WORK;ENCODING=3DQUOTED-PRINTABLE:1104 McConville =
Road=3D0D=3D0ALynchburg, Virginia 24506=3D0D=3D0AUnited States of Am=3D
erica
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=========================================================================
Date:         Tue, 21 Mar 2000 11:31:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Blomberg, Rainer (FL51)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Blomberg, Rainer (FL51)" <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Phil,
I offer the following from our workmanship criteria for space quality
hardware:
Cement fillet on both sides of component.
Length of Fillet to be minimum 80% of body length.
(need not be continuous)

Width (W) of fillet (on each side of the component) within =BD D to 1 D
        (D is the component body diameter)

Height (H) of fillet visible to a maximum =BE of the component body =
radius.

There is no measurable minimum height, but if you meet the other size
criteria, the height will normally take care of itself when the =
adhesive is
applied.  I feel any bond that is more than half-way up the body =
constitutes
encapsulation, not bonding, and excessive for your purposes (unless the
material is VERY compliant).  We have never had a failure with the =
above
criteria (provided there is adhesion to component and board).

Hope this helps,

R. G. Blomberg
Honeywell - Space Systems
Staff Production Engineer
(727) 539-5534 voice
727-539-4469 Fax
[log in to unmask]



-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Monday, March 20, 2000 5:05 PM
To: [log in to unmask]
Subject: [TN] Electrolytic Capacitor Staking Requirements


OK, I know, I know. Why is anyone still using thru hole parts which =
have to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this =
group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that =
the
vibration does not sever the two leads on these parts.  Historically I =
have
always asked that these be bonded 360 degrees around the perimeter and =
a
minimum of 50%, up to a maximum of 100% of the height of the part using =
a
thixotropic UV cure adhesive.  This way the part could not bend or move =
at
all.

Using this criteria, I have never seen a failure as a result of the =
bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle =
time
of course) so that just it connects the board and the bottom of the =
part
only (maybe as high as .15" total which only allows about .10" of =
contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the =
adhesive
has broken loose from the pwb on at least five out of the seven parts =
and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after =
environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of =
parts

All comments are welcome.


-----------------------------------------------------
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=========================================================================
Date:         Tue, 21 Mar 2000 08:32:10 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      activity of No clean

Hi Technetters;
        I'm evaluating some no clean solder paste, and I need some advice.
I have reflown samples on some OSP coated coupons.  Before and after
measurements have given me a relative scale of which pastes wet better than
others. That is what I like to see.  Except that these are no cleans.  Which
means, better wetting on OSP = higher activity.
        The number of different board types and materials involved are so
numerous, I can't practically send a proper representative of production
boards out for SIR testing on my own.  (We are a CEM).
        All of these paste have passed BellCore and IPC SIR requirements.
All product is class II.  So can I accept the best wetting paste,  should I
go with the least wetting paste, or go middle line?
        What is your opinion of the most practical way of balancing the
processing window of wetting Vs reliability?

Thanks for you help

Ryan Grant
MCMS Process Development

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=========================================================================
Date:         Tue, 21 Mar 2000 10:38:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Jens,

There are a few places we use to have artwork scanned. Merriweather, QC
Graphics, to name a couple. An internet search can get you the contact
information.

I'll forward this message to our CAM department, they can send you contact
info if you need it?

Franklin D Asbell

----- Original Message -----
From: [log in to unmask] <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 11:55 PM
Subject: [TN] Question: Film to Gerber - how?


> Hi Ya'll,
>
> I got again this old problem. I have the films, but need the Gerberdata.
Is
> there a way to do it without making a complete new design?
>
> Regards
>
> Jens Behrens
>
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Date:         Tue, 21 Mar 2000 10:48:43 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dave Kell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dave Kell <[log in to unmask]>
Subject:      Re: Organic Contamination -Reply
Mime-Version: 1.0
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I understand what you mean about these types of tests.  For years, I have =
have been questioned about ionic cleanliness that seems to fluctuate with =
no process changes.

I was tasked to perform the test by a customer that read IPC-FC- 250, =
which "required" the test for qualification.  Since the device is =
implanted, any contamination is questioned.  I will take your advice and =
consult outside analysis if necessary.

Thank you
Dave

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Date:         Tue, 21 Mar 2000 15:51:24 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Matthew Lamkin <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Matthew Lamkin <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
MIME-Version: 1.0
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I queried this with a local firm last week, and it can be done, but at a
cost.
It was about 300 pounds plus for a 12" square (ish) size PTH board.
Taken from ancient 2:1 artworks.

The ability to do it is there, you just have to find someone near to
you.


>-----Original Message-----
>From:  [log in to unmask] [SMTP:[log in to unmask]]
>Sent:  Tuesday, March 21, 2000 7:56 AM
>To:    [log in to unmask]
>Subject:       [TN] Question: Film to Gerber - how?
>
>Hi Ya'll,
>
>I got again this old problem. I have the films, but need the Gerberdata. Is
>there a way to do it without making a complete new design?
>
>Regards
>
>Jens Behrens
>
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Date:         Tue, 21 Mar 2000 17:59:32 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "d. terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: activity of No clean
Mime-Version: 1.0
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Hi Ryan,

Higher activity does not necessarily mean that the residues after =
soldering are more corrosive.=20
So if you are really confident that all these pastes meet your reliablity =
criteria I would choose the paste with the best wetting properties. Futher =
I would feel much more confident with an extensive report of i.e. =
Trace-labs, than with a glossy brochure with nothing more than the words =
"pass".

Kind regards

Daan Terstegge
SMT Centre
Signaal Communications
Unclassified mail
Personal website: http://surf.to/smtinfo

>>> Ryan Grant <[log in to unmask]> 03/21 4:32 pm >>>
Hi Technetters;
        I'm evaluating some no clean solder paste, and I need some advice.
I have reflown samples on some OSP coated coupons.  Before and after
measurements have given me a relative scale of which pastes wet better =
than
others. That is what I like to see.  Except that these are no cleans.  =
Which
means, better wetting on OSP =3D higher activity.
        The number of different board types and materials involved are so
numerous, I can't practically send a proper representative of production
boards out for SIR testing on my own.  (We are a CEM).
        All of these paste have passed BellCore and IPC SIR requirements.
All product is class II.  So can I accept the best wetting paste,  should =
I
go with the least wetting paste, or go middle line?
        What is your opinion of the most practical way of balancing the
processing window of wetting Vs reliability?

Thanks for you help

Ryan Grant
MCMS Process Development

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Date:         Tue, 21 Mar 2000 07:23:40 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ramsey, Guy" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ramsey, Guy" <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Does the component contact the board? Requirements for adhesive bonding
change if the component is elevated. The IPC-A-610 requirement for class
three is 50% of the length of the component and 25% of the diameter.
Adhesion (before and after testing) must be evident.

Elevated components weighing more than 7g must be bonded in at least four
places evenly spaced around the component and at least 20% of the total
periphery must be bonded, adhering to both the board and the component.


-----Original Message-----
From: phil bavaro [mailto:[log in to unmask]]
Sent: Monday, March 20, 2000 5:05 PM
Subject: Electrolytic Capacitor Staking Requirements


OK, I know, I know. Why is anyone still using thru hole parts which have to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that the
vibration does not sever the two leads on these parts.  Historically I have
always asked that these be bonded 360 degrees around the perimeter and a
minimum of 50%, up to a maximum of 100% of the height of the part using a
thixotropic UV cure adhesive.  This way the part could not bend or move at
all.

Using this criteria, I have never seen a failure as a result of the bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time
of course) so that just it connects the board and the bottom of the part
only (maybe as high as .15" total which only allows about .10" of contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the adhesive
has broken loose from the pwb on at least five out of the seven parts and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome.


-----------------------------------------------------
Click here for Free Video!!
http://www.gohip.com/freevideo/

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Date:         Tue, 21 Mar 2000 08:57:07 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ahne Oosterhof <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         "[log in to unmask]" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Yes it is possible.
Contact SCANCAD in Morrison, CO: 1-303-697-8888.
They can give you a quote on such a job.

Regards, Ahne Oosterhof

-----Original Message-----
From:   TechNet [mailto:[log in to unmask]] On Behalf Of [log in to unmask]
Sent:   Monday, March 20, 2000 23:56 PM
To:     [log in to unmask]
Subject:        [TN] Question: Film to Gerber - how?

Hi Ya'll,

I got again this old problem. I have the films, but need the Gerberdata. Is
there a way to do it without making a complete new design?

Regards

Jens Behrens

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Date:         Tue, 21 Mar 2000 11:27:29 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         John Laur <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

I had asked the scanning question awhile back.  The following are what I received from the group.

Applied Cam Engineering
545 West Lambert Rd
Brea Ca. 92621
Internet: [log in to unmask]
Modem:    +714.529-7313
Voice:    +714.529-1553
FAX:      +714.529-4202
Edward G. Shea

Artnet Technology Inc.
2109 O'Toole Ave. Suite G
San Jose, CA
Phone: (408) 954-8383
Fax: (408) 954-8380

Custom Photo & Design
340 Qinnipiac St. Bldg 35
Wallingford, CT 06492
phone: (203)-265-4479 Ray Long
fax: (203)-284-8740

Infinite Graphics
Minneapolis, MN
(612) 721-6283
Ron Videen

Infinite Technologies Inc.
17332 Von Karman Ave. #145
Irvine, CA
Phone: (714) 975-0765
Fax: (714) 975-0601

Merriwether Circuit Design, Inc
40 Hill Ave.
Fort Walton Beach, FL 32548
Phone: (904) 243-8144
Fax: (904) 243-9455


Phototool Engineering
Chelmsford, MA
has a scanning system from ScanCAD
508-256-8530
Mark Devereaux

ScanCad International
Denver
303-986-7707


John Laur
Rockwell Automation / Allen-Bradley
1201 South Second Street
Milwaukee, WI.  53204

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Date:         Tue, 21 Mar 2000 14:45:34 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Burtt, Nigel" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Burtt, Nigel" <[log in to unmask]>
Subject:      Digitaltest MTS300 ICT/ATE

Would anyone care to share (off-line from the forum if necessary) their
experiences with Digitaltest ICT/ATE equipment. I am particularly interested
in the MTS300 and European users.

Thanks

Nigel Burtt
Production Engineering Manager
D - European HQ
Email: [log in to unmask]
Tel:     +44 (0)1793 842132 [direct line with voicemail]
Fax:    +44 (0)1793 842101

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Date:         Tue, 21 Mar 2000 12:28:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         Matthew Lamkin <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
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This is a multi-part message in MIME format.

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I HAVE GOOD SERVICE THAT IS VERY COST EFFECTIVE YOU MY CONTACT ME FOR MORE
INFO

William W. DeCray III
Waytec Electronics Corp
Sales Engineer
PHONE:(804) 237-6391 ext 115
FAX:    (804) 237-1324
E-mail:<[log in to unmask]>
Web <http://www.waytec.com>
FTP <ftp://ftp.waytec.com>



-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Matthew Lamkin
Sent: Tuesday, March 21, 2000 10:51 AM
To: [log in to unmask]
Subject: Re: [TN] Question: Film to Gerber - how?


I queried this with a local firm last week, and it can be done, but at a
cost.
It was about 300 pounds plus for a 12" square (ish) size PTH board.
Taken from ancient 2:1 artworks.

The ability to do it is there, you just have to find someone near to
you.


>-----Original Message-----
>From:  [log in to unmask] [SMTP:[log in to unmask]]
>Sent:  Tuesday, March 21, 2000 7:56 AM
>To:    [log in to unmask]
>Subject:       [TN] Question: Film to Gerber - how?
>
>Hi Ya'll,
>
>I got again this old problem. I have the films, but need the Gerberdata. Is
>there a way to do it without making a complete new design?
>
>Regards
>
>Jens Behrens
>
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BEGIN:VCARD
VERSION:2.1
N:DeCray;Bill
FN:Bill DeCray
ORG:Waytec Electronics
TITLE:Methods Engineer
TEL;WORK;VOICE:(804) 237-6391
TEL;HOME;VOICE:(804) 525-2093
TEL;WORK;FAX:(804) 239-1324
ADR;WORK:;;1104 McConville Road;Lynchburg;Virginia;24506;United States =
of America
LABEL;WORK;ENCODING=3DQUOTED-PRINTABLE:1104 McConville =
Road=3D0D=3D0ALynchburg, Virginia 24506=3D0D=3D0AUnited States of Am=3D
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Date:         Tue, 21 Mar 2000 08:46:35 -0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jorge Engenharia <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Engenharia <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         Bob Perkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Bob,

  This is copy / paste from draft version of IPC 7095 ( issued may 1999 )
...

7.3 Assembly accept/reject criteria
7.3.1 Voids in solder joint
a. Sources of Voids
There can be voids in solder balls, or at the solder joints to the BGA, or
at the solder joints to
the PCB. Various sources or reasons can be responsible for these voids.
Voids can be carried over from original voids in solder balls. These voids
could be the result
of ball manufacture process or materials used. Voids can be induced into the
reflowed solder
joint by either the voids in the original component solder ball, or during
the reflow attachment
process. These voids could be the result of ball manufacture process or
attach process
parameters, or board design (e.g., via in pad), or materials used.
Voids can also form near the PCB-Ball interface during BGA attach to PCB.
These voids are
typically induced during the assembly process, which is typically flux that
has been vaporized
during the reflow process, and entrapped during the solidification of the
molten solder. The
source of vaporized flux can be either from flux itself (typically rework),
or flux which is one
of the constituents of the solder paste used in the reflow assembly process.
Voids can also be formed via expanded air from plugged vias (via in pad
consideration) in
the PCB. Expanding air from plugged via under pad may also create a void in
molten ball.
Typically most voids are detected in the middle to top (ball / BGA
interface) of the reflowed
solder joint. This is expected because the entrapped air bubble and the
vaporized flux,
which is applied to the PCB BGA pads, rises during the reflow profile. This
occurs when the
applied solder paste and the BGA's collapsible eutectic solder ball(s) melt
together during the
reflow profile (typically 235 to 240 *C peak temperature). If the reflow
profile cycle doesn't
allow sufficient time for either the entrapped air or vaporized flux to
escape, a void is formed
as the molten solder solidifies in the cool down area of the reflow profile.
Therefore, the
development of the reflow profile is extremely important as a contributor to
the formation of
voids. BGA components having non-collapsible balls (high temperature solder
(90% Pb 10%
Sn, with a melting point of 302 *C) typically will have little or none
induced voids because the
ball solder metallurgy never melts during the reflow profile. Voids in
solder joints are not new
because of the use of collapsible BGAs. Voids can be detected under leaded
components
when using x-ray equipment. However leaded component solder joints are
usually visually
inspected, not x-rayed, and therefore never detected.
b. Impact of Voids
The questions are how many and how large are these voids allowable in the
product that will
impact the product's required reliability. Another question is where in the
"Z-axis" in
conjunction with the void size is also allowable without impacting the
required reliability.
Voids at either interface, solder ball to BGA or BGA to PCB, can have
quality and reliability
implications depending on their size, number, and location. Gases entrapped
in the voids
may give rise to stress while expanding and contracting during heat
excursions. They can
serve as stress initiation (and in some cases, stress absorption points).
They can start (and
in some cases, terminate) a stress crack. Their elimination or, at least,
substantial reduction
is preferred.
80
Large voids are more detrimental but small pre-existing voids can merge
during reflow to
create large voids.
Voids reduce the mechanical strength of the interface by reducing the
interface area. The
impact of their presence is a function of the properties (such as CTEs) of
the materials
surrounding the solder and their dimensional location, shapes and
relationships.
c. Inspection of Assemblies for Voids
Inspection of BGA joints using an x-ray can detect these voids. A sample
in-coming x-ray
inspection should bring the issue to light.
X-ray analysis is therefore required for the inspection and the detection of
voids in BGA
solder joints. Unlike a leaded component, BGAs have solder joints that are
not only on the
component's periphery, but have internal solder joints that are not
inspectable by normal
visual techniques. X-ray equipment is required for inspection or detection
of voids in BGA's
solder joints. This is probably one of the two new pieces of equipment (the
other could be hot
gas rework equipment) that's required for the qualification of a SMT BGA
assembly line. X-ray
equipment can range from $30K to $500K. The lower cost equipment is
transmission x-ray,
whereas the higher cost equipment is x-ray laminography. The difference
between the
two pieces of analytical equipment is that the transmission x-ray can only
detect a void, but
can not determine where the void exist in the "Z-axis" (bottom, middle, or
top of the solder
joint). The x-ray laminography via programming can take slices of the solder
joint in the "Z-axis",
and determine the location of the void(s). Typically because of the high
cost of x-ray
laminography equipment, only larger or high volume assembly shops can afford
this
equipment. One lower cost scenario for achieving either sampling or 100%
x-ray inspection
of BGAs would be to have a transmission x-ray in each SMT line. If a
suspicious void is
detected, that the suspicious assembly is taken off line for finer analysis
and defect
determination on off line x-ray laminography equipment.
d. Elimination of Voids
The assemblers can work with their suppliers to eliminate voids in the
incoming BGA solder
balls.
The manufacturers can adjust their process and/or materials to eliminate
these voids. The
user can work with the supplier to eliminate voids in incoming BGAs.
Recently and typically,
little or no voids are detected in the incoming BGA solder joints.
Reflow time-temperature profile, flux amount, type and properties should be
investigated for
improvement. Such voids can again be eliminated through material and/or
process
adjustment and optimization.
e. Accept/reject criteria for voids in solder balls:
With constantly decreasing BGA pad sizes, solder ball sizes and pad pitches,
the product
dimensional parameters will be continually changing on the production floor.
Materials and
processes will be changing to attain pricing, throughput, quality and
reliability goals. There
will be a continuous need for process development for changing
configurations.
81
Voids and other defects will be encountered in various stages of product's
developmental
and manufacturing ramp up life. It will be necessary to maintain a minimum
acceptable
standard so that the product is manufacturable, meets customer expectations,
has a useful
working life and meets product reliability requirements.
The manufacturers need to be encouraged to use process control for
continuous product
improvement. Voids are an anomaly. Manufacturer should work towards their
elimination
using available statistical process control and process improvement tools.
A general presence of voids should indicate a need to control and/or to
improve process and
materials. An accept/reject limit can be used to help the manufacturer
realize the need to
eliminate voids. As an example, a reject limit of no more than 5% solder
balls with voids set
by a customer can alert the manufacturer that presence of voids is not
acceptable. A
profusion of voids all over the part or a general presence of voids should
not be considered
an acceptable norm.
Voids, when present, will normally have a distribution of sizes. The size of
the largest
probable void can be estimated from measurements performed on a sample. A
largest
probable size detrimental to the life of the contact should not be
acceptable. The
unacceptable void size may vary from one BGA design to another.
A void larger than 25% of solder ball contact area diameter (~6% of contact
area) can be
rendered unacceptable by a customer, again to encourage elimination of
voids. (see Figure
36) Any such criterion will be used in conjunction with the reject criteria
for the proportion of
voided acceptable solder balls.
When there are more than one voids per solder ball, then the dimensions of
the voids will be
added to calculate the total voiding in that solder ball.
Solder outline
Void outline
d
0.25 d
Figure 36 Example of voided area at land and board interface
Defective determination is made by the product's reliability requirements.
Typically the
maximum allowable size void is 30% of the solder ball diameter (equivalent
to 11% of area).
This can be either one void, or the summation of many voids. Unfortunately
the currently
algorithms for x-ray laminography doesn't perform the summation of the
voids. X-ray
laminography via programming can determine a defect greater than the
pre-determined size.
Therefore if the diameter of a reflowed solder joint is .030", the maximum
size of the void in
the middle of the joint would be .009". If the .009" void was detected at
either the top (BGA
interface) or bottom (PCB interface) that joint would be rejected because
the diameter of that
joint at that slice would be less than .030", and the void would be greater
than 30% of the
diameter.
The theory is believed that the voids at either interface can be more of a
reliability problem.
Greater stress is achieved at the interfaces as the distance from the
neutral point grows, and
the component substrate and PCB are of different materials. This causes
greater stress
because of the possible mismatch of CTEs. However stress testing / thermal
cycling with
voids at 30% have not failed medical class III criteria. Smaller voids are
believed by some to
be more favorable than no voids at all. The reason being as a crack is
propagated, upon
reaching a small void, the void stops the crack propagation. Voids have been
either reduced
or eliminated with the use of a nitrogen blanket during the reflow process.
Accept/reject criteria for the number and size of voids, on the one hand
discourages a
general presence of voids which indicates an out of control process and on
the other hand
encourages the manufacturer to use necessary tools for process and material
improvement.

> -----Original Message-----
> From: Bob Perkins [SMTP:[log in to unmask]]
> Sent: 20 de Março de 2000 18:01
> To:   [log in to unmask]
> Subject:      [TN] Voids in BGA Balls after reflow
>
> Hello Technetters
>
>         Recently with the help of a high end piece of x-ray equipment we
> have noticed voids in the spheres of the bga after reflow, "see
> attachment-file".  Has anyone seen this before, or has any idea how the
> voids are created?  Also does anyone know if this is a bad or good thing?
> Does anyone have any recommendations to the profile?
>
>
> Thanks
>         Bob Perkins
>         Automation Technician/Manufacturing Engineer
>         Aimtronics
>         [log in to unmask]
>
>
>  <<wboard6.jpg>> << File: wboard6.jpg >>

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Date:         Tue, 21 Mar 2000 12:38:21 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         [log in to unmask]
MIME-Version: 1.0
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Hi Phil,
You write:
>Here's the background info:
>An automotive electronics circuit card has about seven very tall
>electrolytic caps on it which need to be secured to the board so that the
>vibration does not sever the two leads on these parts.  Historically I have
>always asked that these be bonded 360 degrees around the perimeter and a
>minimum of 50%, up to a maximum of 100% of the height of the part using a
>thixotropic UV cure adhesive.  This way the part could not bend or move at
all.
>Using this criteria, I have never seen a failure as a result of the bonding.
>Here's the problem:
>A new engineer decides to minimize the adhesive amount (due to cycle time
>of course) so that just it connects the board and the bottom of the part
>only (maybe as high as .15" total which only allows about .10" of contact
>to the body of the part.  These parts are .75" tall.  The new engineer
>feels justified because the products which were bonded this way made it
>thru a HALT test exposure without electrical failures.
>I look at the assemblies which are supposedly OK and find that the adhesive
>has broken loose from the pwb on at least five out of the seven parts and
>what is remaining on the parts have fracture lines as well.
>I consider this condition unacceptable and feel that after environmental
>testing, adhesive bonding should remain intact 100%.
>Am I right or should I yield since the assemblies made it thru the HALT
>testing?  What bonding requirements do you impose for these type of parts

1) If "the adhesive has broken loose from the pwb on at least five out of the
seven parts and what is remaining on the parts have fracture lines as well",
how can this be defined as having "made it thru the HALT testing"?
2) Who annointed this particular HALT test (duration, loading) to be
representative of the loading in use for anything representing the desired
life of this automotive electronics? There is a lot of testing going on that
is Highly Accelerated only in the sense that it does produce failures early,
but does NOT accelerate the damage mechanisms at work in actual product.
3)  There are a lot of single-sided CEM-1 unsupported through-hole assemblies
produced today [it is cheap]; it is not surprising that these fail in the
automotive under the hood environment which is the most severe common use
environment by far.

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Date:         Tue, 21 Mar 2000 07:45:41 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Phil,

So does that mean that if your house is still standing after the earthquake,
but the foundation is cracked, that it is OK to move right back in? I
wouldn't think so.

If the bonding has cracked and broken, it is a structural failure.
Electrical failure is probably just around the corner. Reducing the amount
of adhesive as a means of reducing cycle time doesn't seem correct as you
have already established how much adhesive is necessary to hold down the
parts.

If cycle time reduction is the motivation behind what you're trying to
accomplish, the entire assembly process should be studied for possible
restraints throughout the entire process. I think the objective should be to
try build what you're already making in a shorter time period before making
changes to the acceptance criteria as a means of cycle time reduction.

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: phil bavaro [SMTP:[log in to unmask]]
> Sent: Monday, March 20, 2000 5:05 PM
> To:   [log in to unmask]
> Subject:      [TN] Electrolytic Capacitor Staking Requirements
>
> OK, I know, I know. Why is anyone still using thru hole parts which have
> to
> be bonded to the board......!!
>
> Well. all I can say is that we are and the question I have for this group
> is what are the requirements for how much and how high.
>
> Here's the background info:
>
> An automotive electronics circuit card has about seven very tall
> electrolytic caps on it which need to be secured to the board so that the
> vibration does not sever the two leads on these parts.  Historically I
> have
> always asked that these be bonded 360 degrees around the perimeter and a
> minimum of 50%, up to a maximum of 100% of the height of the part using a
> thixotropic UV cure adhesive.  This way the part could not bend or move at
> all.
>
> Using this criteria, I have never seen a failure as a result of the
> bonding.
>
> Here's the problem:
>
> A new engineer decides to minimize the adhesive amount (due to cycle time
> of course) so that just it connects the board and the bottom of the part
> only (maybe as high as .15" total which only allows about .10" of contact
> to the body of the part.  These parts are .75" tall.  The new engineer
> feels justified because the products which were bonded this way made it
> thru a HALT test exposure without electrical failures.
>
> I look at the assemblies which are supposedly OK and find that the
> adhesive
> has broken loose from the pwb on at least five out of the seven parts and
> what is remaining on the parts have fracture lines as well.
>
> I consider this condition unacceptable and feel that after environmental
> testing, adhesive bonding should remain intact 100%.
>
> Am I right or should I yield since the assemblies made it thru the HALT
> testing?  What bonding requirements do you impose for these type of parts
>
> All comments are welcome.
>
>
> -----------------------------------------------------
> Click here for Free Video!!
> http://www.gohip.com/freevideo/
>
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Date:         Tue, 21 Mar 2000 12:33:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Brad L. Matthies" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brad L. Matthies" <[log in to unmask]>
Organization: Raven Industries, Inc.
Subject:      No clean flux.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Technetters,

We, like everyone else, will be switching to a no clean flux in our SMT
area.  I am interested in any ones responses to making this switch.
What issues have you encountered?  Are you having to redesign your
stencils to control the volume of solder paste?  What have you been
doing with your PCB/parts suppliers to control the quality of the raw
goods you receive for use with no clean?

Thanks for your input,
Brad M.
Process Engineer
Raven Industries, Inc.

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Date:         Wed, 22 Mar 2000 03:03:37 +0800
Reply-To:     [log in to unmask]
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From:         Evergreen PCB <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
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SGkgSmVucywNClRoZSB3b3JzdCB3YXkgdG8gZG8gaXQgYnkgc2NhbiBzb2Z0d2FyZS4NClRoZXJl
IGFyZSBhIGxvdCBzb2x1dGlvbi4NCkVkZHkNCg0KLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0N
CkZyb206IFRlY2hOZXQgW21haWx0bzpUZWNoTmV0QElQQy5PUkddT24gQmVoYWxmIE9mIFBDQkFA
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IyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMj

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Date:         Tue, 21 Mar 2000 08:14:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Anne Ledger <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Anne Ledger <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Jens,

You need to find a scanning service.  We use one in California
that does a great job.  They scan our customer's film and give us back
gerber and a drill file.  We can then have the CAM engineers
do some "clean up" on it (comparing to the film copies) and send
out plots for approval.  Once the customer has approved, it can be
released to fabrication.  The only negative is that the gerber data is
unintelligent and as far as I know, can not be reloaded into a CAD
software program.

Hope that helps.

Anne Ledger
EMDS, Inc.
[log in to unmask]

> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Tuesday, March 21, 2000 2:56 AM
> To:   [log in to unmask]
> Subject:      [TN] Question: Film to Gerber - how?
>
> Hi Ya'll,
>
> I got again this old problem. I have the films, but need the
> Gerberdata. Is
> there a way to do it without making a complete new design?
>
> Regards
>
> Jens Behrens
>
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Date:         Tue, 21 Mar 2000 14:07:18 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Nancy Trumbull <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Nancy Trumbull <[log in to unmask]>
Subject:      Re: Solder Ball
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Van

Per IPC 610C page A-1
Electrical Clearance =20
The minimum spacing between conductors between conductive patterns, layer =
to layer conductive spaces ( z axis ) and between conductive materials ( =
such as conductive markings or mounting hardware )  and conductors shall =
be in accordance with Table 6-1.
If needed let me know and I'll fax it to you.

Again from 610c page 6-23
Entrapped / encapsulated / attached is intended to mean normal service =
environment of the product will not cause a solder ball to become =
dislodged.
Testing would be a customer standard.
As: vibration, reliability. shipping................ so on so on.
Please remember the words
entrap and encapsulate and what they  mean.
Hope this helped
There's  my two cents again
Nancy T




>>> Van Hoang Dinh <[log in to unmask]> 03/20/00 04:16PM >>>
Good morning all,

1.Anyone known where can I look for a definition of ELECTRICAL DESIGN =
CLEARANCE ?

2.How we define or experiment test to prove that the solder balls are =
entrapped and not cause a solder ball to become dislodged?

THANKS ALL

VAN=20

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Date:         Tue, 21 Mar 2000 13:36:34 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Charles Barker <[log in to unmask]>
Subject:      Baking FR4 boards
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Greetings all you knowledgable persons!

1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an air
conditioned environment at about 50+/- 10% RH, how many months would you allow
to pass before you would recommend baking them prior to reflow?

2. What would be your bake cycle?

Thanks,

Charlie B.

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Date:         Tue, 21 Mar 2000 14:36:56 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lee Whiteman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lee Whiteman <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

ACI Technologies can convert the film to Gerber. Give us a call for
additional details.

Sincerely,

L. Britt
ACI Technologies
Email [log in to unmask]
Phone 1-610-362-1200 X 217
FAX 1-610-362-1290

Lee Whiteman
Senior Manufacturing Engineer
ACI / EMPF
Telephone: (610) 362-1200; Ext. 208
FAX: (610) 362-1290
E-Mail: [log in to unmask]

 -----Original Message-----
 From: TechNet [mailto:[log in to unmask]]On Behalf Of John Laur
 Sent: Tuesday, March 21, 2000 12:27 PM
 To: [log in to unmask]
 Subject: Re: [TN] Question: Film to Gerber - how?


 I had asked the scanning question awhile back.  The following are
 what I received from the group.

 Applied Cam Engineering
 545 West Lambert Rd
 Brea Ca. 92621
 Internet: [log in to unmask]
 Modem:    +714.529-7313
 Voice:    +714.529-1553
 FAX:      +714.529-4202
 Edward G. Shea

 Artnet Technology Inc.
 2109 O'Toole Ave. Suite G
 San Jose, CA
 Phone: (408) 954-8383
 Fax: (408) 954-8380

 Custom Photo & Design
 340 Qinnipiac St. Bldg 35
 Wallingford, CT 06492
 phone: (203)-265-4479 Ray Long
 fax: (203)-284-8740

 Infinite Graphics
 Minneapolis, MN
 (612) 721-6283
 Ron Videen

 Infinite Technologies Inc.
 17332 Von Karman Ave. #145
 Irvine, CA
 Phone: (714) 975-0765
 Fax: (714) 975-0601

 Merriwether Circuit Design, Inc
 40 Hill Ave.
 Fort Walton Beach, FL 32548
 Phone: (904) 243-8144
 Fax: (904) 243-9455


 Phototool Engineering
 Chelmsford, MA
 has a scanning system from ScanCAD
 508-256-8530
 Mark Devereaux

 ScanCad International
 Denver
 303-986-7707


 John Laur
 Rockwell Automation / Allen-Bradley
 1201 South Second Street
 Milwaukee, WI.  53204

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Date:         Tue, 21 Mar 2000 14:39:23 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Vapor Phase reflow chemicals and equipment..
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi ya'll!

I got some general questions about vapor phase reflow. I went back and looke=
d=20
at all the responses to Jason Gregory's (no relation...that I know of anyway=
)=20
question about vapor phase reflow.

We may get some business that will require it. It's for oil well downhole=20
boards that will be soldered with a SN96/AG04 solderpaste. I've got a 10-zon=
e=20
Conceptronics oven that I can create a profile that will reflow the paste,=20
but I don't think it will do it in a manner that won't cook the parts. With=20
vapor phase, you can get the board down in the vapor, reflow the solder, and=
=20
get it back out before the parts fry...

The liquidous for the SN96/AG 04 is somewhere between 221=BA - 229=BA C., so=
 the=20
regular Fluorinert (FC-70) won't work as it's boiling point is 215=BA C. I=20
checked on the FC-71 and it's boiling point is 253=BA C....so that looks lik=
e=20
the one I should use.

Problem is, don't know where to get it. I've called 3-M and left a message,=20
but haven't got a call back yet...

This all is just in the planning stages now...we haven't got the business=20
yet. But I'm being asked what it will take for us to have vapor phase=20
capabilitiy. I've been web searching and mostly what I've found on the NET i=
s=20
used equipment, Centech, HTI, Baron Blakeslee....who makes new vapor phase=20
equipment now? Also, what kind of ball-park figures will we need to spend fo=
r=20
a decent vapor phase unit?

If anybody knows, what kind of money (per gallon) are we talking about for=20
FC-71? There will also be a secondary chemical that we'll need to use to=20
contain the FC-71 won't there? Or has the equipment technology advanced=20
enough so a secondary chemical isn't needed? I rememember using freon the=20
last time I worked with a vapor phase unit.

As usual, thanks a lot!

-Steve Gregory-

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Date:         Tue, 21 Mar 2000 13:09:26 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dewey Whittaker <[log in to unmask]>
Organization: Honeywell Inc.
Subject:      Re: Baking FR4 boards
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="------------5F03D97FCCE5E77A4C9BA8C7"

--------------5F03D97FCCE5E77A4C9BA8C7
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Charles Barker wrote:

> Greetings all you knowledgable persons!
>
> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an air
> conditioned environment at about 50+/- 10% RH, how many months would you allow
> to pass before you would recommend baking them prior to reflow?
>
> 2. What would be your bake cycle?
>
> Thanks,
>
> Charlie B.
>
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Without knowing any other variables and being conservative,72 hours is your window for the Aerospace Industry.
Dewey

--
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]



--------------5F03D97FCCE5E77A4C9BA8C7
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Charles Barker wrote:
<blockquote TYPE=CITE>Greetings all you knowledgable persons!
<p>1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in
an air
<br>conditioned environment at about 50+/- 10% RH, how many months would
you allow
<br>to pass before you would recommend baking them prior to reflow?
<p>2. What would be your bake cycle?
<p>Thanks,
<p>Charlie B.
<p>##############################################################
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Without knowing any other variables and being conservative,72 hours is
your window for the Aerospace Industry.
<br>Dewey
<pre>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</pre>
&nbsp;</html>

--------------5F03D97FCCE5E77A4C9BA8C7--

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=========================================================================
Date:         Tue, 21 Mar 2000 13:42:25 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Intel Test Methodology
MIME-Version: 1.0
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As I mentioned last week here is the Intel report on impedance testing.
The Intel URL to download the .pdf file is:
http://developer.intel.com/design/chipsets/applnots/#rdram

Regards,
Rick Howieson
GTC

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Date:         Wed, 22 Mar 2000 07:49:54 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Van Hoang Dinh <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Van Hoang Dinh <[log in to unmask]>
Organization: AEMS
Subject:      Re: Solder Ball
X-To:         Nancy Trumbull <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Good morning Nancy

Thank you very much for your help. I really need the table 6-1. would you
please fax for me.
Facsimile : 61 2 9748 7065

----- Original Message -----
From: Nancy Trumbull <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 22, 2000 6:07 AM
Subject: Re: [TN] Solder Ball


Hi Van

Per IPC 610C page A-1
Electrical Clearance
The minimum spacing between conductors between conductive patterns, layer to
layer conductive spaces ( z axis ) and between conductive materials ( such
as conductive markings or mounting hardware )  and conductors shall be in
accordance with Table 6-1.
If needed let me know and I'll fax it to you.

Again from 610c page 6-23
Entrapped / encapsulated / attached is intended to mean normal service
environment of the product will not cause a solder ball to become dislodged.
Testing would be a customer standard.
As: vibration, reliability. shipping................ so on so on.
Please remember the words
entrap and encapsulate and what they  mean.
Hope this helped
There's  my two cents again
Nancy T




>>> Van Hoang Dinh <[log in to unmask]> 03/20/00 04:16PM >>>
Good morning all,

1.Anyone known where can I look for a definition of ELECTRICAL DESIGN
CLEARANCE ?

2.How we define or experiment test to prove that the solder balls are
entrapped and not cause a solder ball to become dislodged?

THANKS ALL

VAN

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Date:         Tue, 21 Mar 2000 16:04:00 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bill Decray <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bill Decray <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/mixed;
              boundary="----=_NextPart_000_005D_01BF934F.12318D40"

This is a multi-part message in MIME format.

------=_NextPart_000_005D_01BF934F.12318D40
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hello Fellow TechNet Helpers,

Does anyone have information on shelf life of white tin finished product.
Any information on white tin or your experiences with white tin would be
greatly appreciated.

Thanks for your help in advance!

William W. DeCray III
Waytec Electronics Corp
Sales Engineer
PHONE:(804) 237-6391 ext 115
FAX:    (804) 237-1324
E-mail:<[log in to unmask]>
Web <http://www.waytec.com>
FTP <ftp://ftp.waytec.com>


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        name="Bill DeCray.vcf"
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BEGIN:VCARD
VERSION:2.1
N:DeCray;Bill
FN:Bill DeCray
ORG:Waytec Electronics
TITLE:Methods Engineer
TEL;WORK;VOICE:(804) 237-6391
TEL;HOME;VOICE:(804) 525-2093
TEL;WORK;FAX:(804) 239-1324
ADR;WORK:;;1104 McConville Road;Lynchburg;Virginia;24506;United States =
of America
LABEL;WORK;ENCODING=3DQUOTED-PRINTABLE:1104 McConville =
Road=3D0D=3D0ALynchburg, Virginia 24506=3D0D=3D0AUnited States of Am=3D
erica
EMAIL;PREF;INTERNET:[log in to unmask]
REV:20000228T134054Z
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Date:         Tue, 21 Mar 2000 16:05:31 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Vapor Phase update...
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi ya'll!

Well, I just got through talking with someone at 3M...the FC-71 product has=20
been discontinued. The highest boiling point heat transfer fluid they make i=
s=20
the FC-70 which boils at 215 =BA C. Just for grins I asked how much that stu=
ff=20
sells for, and was told that it's sold by the pound. A gallon weighs 15-lbs,=
=20
and it's $60.00 a pound! YOWZA! $900 a gallon!!!

Called Galden Fluids, and they have a heat transfer fluid they call HT250=20
which boils at 250=BA C. The say their stuff =20
(http://www.inlandvacuum.com/galden.html) is a non ODP chemical. The spec=20
sheet for all their stuff is at (http://www.inlandvacuum.com/galdenspecs.htm=
l)

A gallon of the HT250 is around $560...anybody ever use this stuff?

Still haven't found anything about the equipment. There's some used stuff ou=
t=20
there but like Brian said in his post, I want to make sure I find something=20
that I won't have to keep pouring this "liquid gold" into to be able run=20
it...like the owl says; "I give a hoot, I don't wanna pollute!" (not=20
mentioning the cost).=20

-Steve Gregory-

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=========================================================================
Date:         Tue, 21 Mar 2000 21:08:54 -0000
Reply-To:     Michael Fenner <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Fenner <[log in to unmask]>
Organization: Bonding Services & Products
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

I suppose a concern here is small batch size, and VPR does bring a certain amount of piece of
mind with respect to uniform heating which I suppose you are equating to small delta T. This is
a two way street, The amount of heat you are going to stuff into your assemblies will also be
quite large, be interesting to know if any one has any numbers for internal temperatures on
devices VPR  in FC71 equivalents.....

Personally I think that if you have a 10 zone convection machine this should be well able to
reflow Sn/Ag soldered aeemblies. If you haven't already, before you blow a few $0000 on VPR why
not invest a few $00 on a data profiler and see what your max thermal excursions really are?


Mike

----- Original Message -----
From: Stephen R. Gregory <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 21, 2000 7:39 PM
Subject: [TN] Vapor Phase reflow chemicals and equipment..


Hi ya'll!

I got some general questions about vapor phase reflow. I went back and looked
at all the responses to Jason Gregory's (no relation...that I know of anyway)
question about vapor phase reflow.

We may get some business that will require it. It's for oil well downhole
boards that will be soldered with a SN96/AG04 solderpaste. I've got a 10-zone
Conceptronics oven that I can create a profile that will reflow the paste,
but I don't think it will do it in a manner that won't cook the parts. With
vapor phase, you can get the board down in the vapor, reflow the solder, and
get it back out before the parts fry...

The liquidous for the SN96/AG 04 is somewhere between 221º - 229º C., so the
regular Fluorinert (FC-70) won't work as it's boiling point is 215º C. I
checked on the FC-71 and it's boiling point is 253º C....so that looks like
the one I should use.

Problem is, don't know where to get it. I've called 3-M and left a message,
but haven't got a call back yet...

This all is just in the planning stages now...we haven't got the business
yet. But I'm being asked what it will take for us to have vapor phase
capabilitiy. I've been web searching and mostly what I've found on the NET is
used equipment, Centech, HTI, Baron Blakeslee....who makes new vapor phase
equipment now? Also, what kind of ball-park figures will we need to spend for
a decent vapor phase unit?

If anybody knows, what kind of money (per gallon) are we talking about for
FC-71? There will also be a secondary chemical that we'll need to use to
contain the FC-71 won't there? Or has the equipment technology advanced
enough so a secondary chemical isn't needed? I rememember using freon the
last time I worked with a vapor phase unit.

As usual, thanks a lot!

-Steve Gregory-

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Date:         Tue, 21 Mar 2000 20:56:59 -0000
Reply-To:     Michael Fenner <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Michael Fenner <[log in to unmask]>
Organization: Bonding Services & Products
Subject:      Re: OK,....what in the world?????
X-To:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Yeap my recent posting was also rejected but still managed to provoke the too many times bounced
message!!!

I suppose the new server thingmebob has a bug or two still.

Mike


----- Original Message -----
From: Hamilton, Richard CLE 4454 <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 7:38 PM
Subject: [TN] OK,....what in the world?????


> Hello fellow TN junkies,
>
> Talk about strange email.....I have posted two emails earlier about 50
> minutes apart about 2 hours ago. I got the normal acceptance email back
> within minutes of posting and just now I got two notices (one for each email
> sent) from IPC that tells me that the email I have *just* sent seems to be a
> duplicate and is being returned to me.
>
> Do I have something generating a second posting at my end, or are other
> people seeing this 'thing' also? Talk about Space Camp!?
>
> We had email problems last week and I did a sanity check with Steve (Thanks
> by the way) which indicated that the problems were at my end. I am sorry if
> the problem is at our end, but I am going bonkers (and 'screaming yellow' at
> that!) here. My sanity is being challenged (AGAIN!). I thought me and my
> therapist and mother got all that straightened out last week!? Shows ya what
> I know!
>
> Thanks for the patience.
>
> Richard Hamilton
> Clemar Mfg. / Rain Bird
> [log in to unmask]
>
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> 847-509-9700 ext.5315
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>

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=========================================================================
Date:         Tue, 21 Mar 2000 16:24:08 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: Baking FR4 boards
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Isn't the 72 hours before bake a requirement for polyimide instead of FR4?

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Dewey Whittaker
1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an air

conditioned environment at about 50+/- 10% RH, how many months would you
allow
to pass before you would recommend baking them prior to reflow?
2. What would be your bake cycle?
Thanks,
Charlie B.
####################################
Without knowing any other variables and being conservative,72 hours is your
window for the Aerospace Industry.
Dewey
--
Dewey Whittaker

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Date:         Tue, 21 Mar 2000 15:08:51 -0700
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              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dewey Whittaker <[log in to unmask]>
Organization: Honeywell Inc.
Subject:      Re: Baking FR4 boards
X-To:         Alain Savard <[log in to unmask]>
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--------------6614B84657E212EA5F898994
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Alain Savard wrote:

> Isn't the 72 hours before bake a requirement for polyimide instead of FR4?
>
> Alain Savard, B.Sc.
> Chemical Process Analyst
> CAE Electronics Ltd.
> e-mail: [log in to unmask]
>
> -----Original Message-----
> From: Dewey Whittaker
> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an air
>
> conditioned environment at about 50+/- 10% RH, how many months would you
> allow
> to pass before you would recommend baking them prior to reflow?
> 2. What would be your bake cycle?
> Thanks,
> Charlie B.
> ####################################
> Without knowing any other variables and being conservative,72 hours is your
> window for the Aerospace Industry.
> Dewey
> --
> Dewey Whittaker
>
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> 847-509-9700 ext.5315
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If it were Polyimide,it would be 24 hours(realistically 8 hours).Through testing and proper storage conditions,each design could have a much greater
processing window.4 hours at 100 degrees C. is the bake.
Dewey

--
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]



--------------6614B84657E212EA5F898994
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Alain Savard wrote:
<blockquote TYPE=CITE>Isn't the 72 hours before bake a requirement for
polyimide instead of FR4?
<p>Alain Savard, B.Sc.
<br>Chemical Process Analyst
<br>CAE Electronics Ltd.
<br>e-mail: [log in to unmask]
<p>-----Original Message-----
<br>From: Dewey Whittaker
<br>1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored
in an air
<p>conditioned environment at about 50+/- 10% RH, how many months would
you
<br>allow
<br>to pass before you would recommend baking them prior to reflow?
<br>2. What would be your bake cycle?
<br>Thanks,
<br>Charlie B.
<br>####################################
<br>Without knowing any other variables and being conservative,72 hours
is your
<br>window for the Aerospace Industry.
<br>Dewey
<br>--
<br>Dewey Whittaker
<p>##############################################################
<br>TechNet Mail List provided as a free service by IPC using LISTSERV
1.8c
<br>##############################################################
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text in
<br>the body:
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<br>##############################################################
<br>Please visit IPC web site (<a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>)
for additional
<br>information.
<br>If you need assistance - contact Keach Sasamori at [log in to unmask] or
<br>847-509-9700 ext.5315
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If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
testing and proper storage conditions,each design could have a much greater
processing window.4 hours at 100 degrees C. is the bake.
<br>Dewey
<pre>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</pre>
&nbsp;</html>

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Date:         Tue, 21 Mar 2000 17:19:49 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         [log in to unmask]
MIME-Version: 1.0
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In a message dated 03/21/2000 3:08:44 PM Central Standard Time,=20
[log in to unmask] writes:

<< Personally I think that if you have a 10 zone convection machine this=20
should be well able to reflow Sn/Ag soldered aeemblies. If you haven't=20
already, before you blow a few $0000 on VPR why not invest a few $00 on a=20
data profiler and see what your max thermal excursions really are?
=20
=20
 Mike>>

Hi Mike!

I've got a ECD Super Mole, and I've done some experiments with a sample of=20
SN96/AG04 high temp solder paste, dummy components...so I know I can create=20=
a=20
profile with the paste...but I don't know what I did to the components, they=
=20
were dummies. I peaked out at 248=BA C on one of my profiles and saw a max r=
amp=20
of  3.2=BA per second during my final ramp into the spike zone. That was=20
because I learned that you need to keep your preheat and soak down around=20
traditional 63/37 temperatures, otherwise you'll fry all the activity out of=
=20
the flux and get nothing but a bunch of solderballs when things go=20
liquidous...you'll get a fillet all right, but it's just covered with solder=
=20
balls. So my profile looks pretty normal until you get to the end, then I=20
pour the coals to her! My set points are about 300-315=BA C at the end.

The deal is, is that the business that we may get is currently being built=20
using vapor phase reflow...and seem to be getting good results and=20
reliability. As you may know, you can't afford to have one of these downhole=
=20
boards fail after you've got it 5,000 feet in the ground...takes a little=20
time and money to pull everything back up again so you can repair it. So=20
rather than take chances by changing the reflow process, I was just asked to=
=20
see what it would take to give us vapor phase capability.=20

I would love to be able to feel confident enough to say that the convection=20
oven I have is fine, but I don't have enough experience working on the edge=20
(temperature-wise) to say that one process is better than the other.

-Steve Gregory-

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Date:         Tue, 21 Mar 2000 18:20:45 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Scott Mcanall <[log in to unmask]>
Subject:      Re: Subj:  Test Equipment Fab/Suppliers
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Scott J. McAnall
Robotic Process Systems, Inc.
www.rpstest.com
www.rpsrobot.com
www.rpssoldersyt.com
www.rpsautomation.com

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Date:         Tue, 21 Mar 2000 16:32:23 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Baking FR4 boards
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Out of curiosity, where are these requirements stated?
Rick

>-----Original Message-----
>From:  Dewey Whittaker [SMTP:[log in to unmask]]
>Sent:  Tuesday, March 21, 2000 3:09 PM
>To:    [log in to unmask]
>Subject:       Re: [TN] Baking FR4 boards
>
>Alain Savard wrote:
>
>> Isn't the 72 hours before bake a requirement for polyimide instead of FR4?
>>
>> Alain Savard, B.Sc.
>> Chemical Process Analyst
>> CAE Electronics Ltd.
>> e-mail: [log in to unmask]
>>
>> -----Original Message-----
>> From: Dewey Whittaker
>> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an
>>air
>>
>> conditioned environment at about 50+/- 10% RH, how many months would you
>> allow
>> to pass before you would recommend baking them prior to reflow?
>> 2. What would be your bake cycle?
>> Thanks,
>> Charlie B.
>> ####################################
>> Without knowing any other variables and being conservative,72 hours is your
>> window for the Aerospace Industry.
>> Dewey
>> --
>> Dewey Whittaker
>>
>> ##############################################################
>> TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
>> ##############################################################
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>>text in
>> the body:
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>>additional
>> information.
>> If you need assistance - contact Keach Sasamori at [log in to unmask] or
>> 847-509-9700 ext.5315
>> ##############################################################
>
>If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
>testing and proper storage conditions,each design could have a much greater
>processing window.4 hours at 100 degrees C. is the bake.
>Dewey
>
>--
>Dewey Whittaker
>Honeywell -- Air Transport Systems Division
>US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
>Phone: +1 602 436 436-2766
>NSFnet: [log in to unmask]
>
>
>
><!doctype html public "-//w3c//dtd html 4.0 transitional//en">
><html>
>Alain Savard wrote:
><blockquote TYPE=CITE>Isn't the 72 hours before bake a requirement for
>polyimide instead of FR4?
><p>Alain Savard, B.Sc.
><br>Chemical Process Analyst
><br>CAE Electronics Ltd.
><br>e-mail: [log in to unmask]
><p>-----Original Message-----
><br>From: Dewey Whittaker
><br>1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored
>in an air
><p>conditioned environment at about 50+/- 10% RH, how many months would
>you
><br>allow
><br>to pass before you would recommend baking them prior to reflow?
><br>2. What would be your bake cycle?
><br>Thanks,
><br>Charlie B.
><br>####################################
><br>Without knowing any other variables and being conservative,72 hours
>is your
><br>window for the Aerospace Industry.
><br>Dewey
><br>--
><br>Dewey Whittaker
><p>##############################################################
><br>TechNet Mail List provided as a free service by IPC using LISTSERV
>1.8c
><br>##############################################################
><br>To subscribe/unsubscribe, send a message to [log in to unmask] with
>following
>text in
><br>the body:
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><br>##############################################################
><br>Please visit IPC web site (<a
>href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a
>>)
>for additional
><br>information.
><br>If you need assistance - contact Keach Sasamori at [log in to unmask] or
><br>847-509-9700 ext.5315
><br>##############################################################</blockquot
>e>
>If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
>testing and proper storage conditions,each design could have a much greater
>processing window.4 hours at 100 degrees C. is the bake.
><br>Dewey
><pre>--&nbsp;
>Dewey Whittaker
>Honeywell -- Air Transport Systems Division
>US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
>Phone: +1 602 436 436-2766
>NSFnet: [log in to unmask]</pre>
>&nbsp;</html>
>

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Date:         Tue, 21 Mar 2000 19:39:08 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jon Moore <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
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I have had excellent success coating over no-clean fluxes.  As Pat states,
you must do the testing and verify compatibility with the two chemistries

Jon Moore

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Date:         Tue, 21 Mar 2000 19:46:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
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Hi Steve,
Downhole drilling electronics sees the most severe operational loading of any
ellectronic assemblies. Design this stuff as robust as possible with the
least CTE-mismatch as possible, and be careful with the encapsulant material
chosen.
Vapor phase soldering is a good idea; but, is there nothing between 253 and
215C?
Good luck!
Werner Engelmaier

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Date:         Tue, 21 Mar 2000 20:43:30 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
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In a message dated 03/21/2000 6:46:27 PM Central Standard Time, Engelmaier
writes:

> Hi Steve,
>  Downhole drilling electronics sees the most severe operational loading of
> any ellectronic assemblies. Design this stuff as robust as possible with
the
> least CTE-mismatch as possible, and be careful with the encapsulant
material
> chosen.
>  Vapor phase soldering is a good idea; but, is there nothing between 253
and
> 215C?
>  Good luck!
>  Werner Engelmaier

Hi Werner!

Yeah, don't have tell me about how harsh an environment these boards will
see, it's easy for anyone to imagine what these boards will go though. They
go into a metal "tool" (about 9 boards per tool) that's about 8"-10" in
diameter and about 10-feet long.

The boards are very thin width-wise (less than 2-inches) and about a foot
long. They are polyimide (I think) PCB's with a lot of copper in them. We
don't control the designs, we're just gonna try and build them.

After going back and looking at the Galden Fluids spec's, they do make a
chemical that has a boiling point of 230 degrees C. I suppose with vapor
phase you don't have to follow the standard guidelines for reflow profiling
of hitting a peak of 20-30 degrees above liquidous of the alloy...that's more
for standard reflow equipment isn't it?

With a chemical like the Galden HT230, I won't have to worry so much that
there will be any temperature lags that one may see with convection or IR
reflow....

I'm still looking for equipment though...

Thanks Werner!

-Steve Gregory-

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Date:         Tue, 21 Mar 2000 22:02:52 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         [log in to unmask]
MIME-Version: 1.0
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Steve:  On equipment:

1.  Posted on SMTnet by J.J. Thomas ([log in to unmask] ) on October 12, 1999 at
7:22:41 AM EST … "We (Compunetix, Inc.) need to sell a Centech Vapor Phase. What would
be a good asking price. TIA" <= a match made in ... ???
2.  R&D Technical Services purchased the rights to Centech Equipment Division.  R&D
Technical Services (Centech) 12261 Suite A Nicollet Ave S Burnsville, MN 55337 (612)
707-1931 fax 6739 sales@rdtechnicalservices
3.  I'll bet many used equipment brokers have inventories of vapor phase equipment in
dusty warehouses that they understandably don't list on their sites.  You don't need
contacts for those types do you?

Dave Fish

"Stephen R. Gregory" wrote:

> <snip>
>
> I'm still looking for equipment though...
>
> Thanks Werner!
>
> -Steve Gregory-
>
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Date:         Wed, 22 Mar 2000 10:45:30 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Tantalum capacitors
X-To:         Michael Fenner <[log in to unmask]>
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Content-Type: text/plain; charset="iso-8859-1"

Thanks Mike,
would like some demo pictures if you have..//Ingemar

-----Original Message-----
From: Michael Fenner [mailto:[log in to unmask]]
Sent: den 18 mars 2000 12:26
To: TechNet E-Mail Forum.; Ingemar Hernefjord (EMW)
Subject: Re: [TN] Tantalum capacitors


This body design is preferable to the previous which looked like two tailed tadpole and gave all
sorts of problems with bleed and very low joint strengths. If you can't solve the problem with
careful shaping of the glue shape prior to placing and placement pressure/pad design such that
the adhesive squidges into correct place (rather than out of it) then you could consider
striping non conductive adhesive between pads to make a dam bar and stand off. Alternative is to
dot insulating adhesive as well as conductive so that  on co curing component is held by both
adhesive types. This is usually OK for high G.


Mike

----- Original Message -----
From: Ingemar Hernefjord (EMW) <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 17, 2000 9:57 AM
Subject: [TN] Tantalum capacitors


>
> Now, about tantalum caps. Anyone out there using tantals with FLEXIBLE terminals? Old model,
you recognize that, is with a more or less straight and painted body, terminals silvered, tinned
or gold plated, most models for soldering. New since a number of years are those with
rectangular body, suitable for P-P, and with sort of flexible ribbon terminal that is bent 90
degrees under the body. Those having these are e.g. Kemet, Sprague, Matsuo, Tekelec, Siemens,
NEC, AVX/Kyocera to mention some.  OK, they are all excellent for soldering, but for silver
epoxy mounting a minor problem occurs: the epoxy wets, not only the terminal but also the body.
Then you loose some of the advantage with flexibility. You find a typical outline in IPC-SM-782
Subsection 8.4.
>
> Question: anyone that pick-and-place such creatures for silverepoxy technology? What terminal
finish do you order? And do you utilize the flexibel terminal?  How do you get a recommende
epoxy line (50-100um) as the component is heavy, do you use some kind of standoff? Anyone that
has centrifuged up to 5,000 G's? Anyone with experience from mounting such caps on
Arlene/Roger/Taconic with heavymetal backing?
>
> Normal FR4 indoor products with this cap are normally soldered and there are no obstacles. So,
we don't have a general problem, but lack some experience for epoxying in special applications.
>
> Also will come back later with discussion about ceramic caps, ferro/piezo effects, aging and
such things that has been up recently. Ousten, France, are you out there? Still working with the
RFceramic characterization project? Lost your e-mail adress.
>
> Ingemar Hernefjord
> Ericsson Microwave Systems

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=========================================================================
Date:         Wed, 22 Mar 2000 10:46:26 -0000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Vapor Phase update...
X-To:         [log in to unmask]
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Steve,

I make a vapour phase system and will send you all the info. We also do the
Heat Transfer Fluids (HTF).

Our system is a patented process where the whole process is carried out in a
sealed chamber - discontinuous process. The advantage of which is to
minimise the loss of HTF. It also facilitates intrusive reflow.

Now, before I get slammed, you asked and I responded, everything else is
offline! Anyone wants more, call me directly.

Regards,
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227
----- Original Message -----
From: Stephen R. Gregory <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 21, 2000 9:05 PM
Subject: [TN] Vapor Phase update...


> Hi ya'll!
>
> Well, I just got through talking with someone at 3M...the FC-71 product
has
> been discontinued. The highest boiling point heat transfer fluid they make
is
> the FC-70 which boils at 215 º C. Just for grins I asked how much that
stuff
> sells for, and was told that it's sold by the pound. A gallon weighs
15-lbs,
> and it's $60.00 a pound! YOWZA! $900 a gallon!!!
>
> Called Galden Fluids, and they have a heat transfer fluid they call HT250
> which boils at 250º C. The say their stuff
> (http://www.inlandvacuum.com/galden.html) is a non ODP chemical. The spec
> sheet for all their stuff is at
(http://www.inlandvacuum.com/galdenspecs.html)
>
> A gallon of the HT250 is around $560...anybody ever use this stuff?
>
> Still haven't found anything about the equipment. There's some used stuff
out
> there but like Brian said in his post, I want to make sure I find
something
> that I won't have to keep pouring this "liquid gold" into to be able run
> it...like the owl says; "I give a hoot, I don't wanna pollute!" (not
> mentioning the cost).
>
> -Steve Gregory-
>
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=========================================================================
Date:         Wed, 22 Mar 2000 07:44:40 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Subject:      Re: Vapor Phase update...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Steve:

Back 'round 10 years ago or so, we were exclusively using vapor phase =
as our
main reflow unit. We had (still have in storage) a Centech Machine. We =
used
the machine daily for an 8 hour shift. My recollection was that once =
the
machine was filled, we added approximately a half gallon of =
replenishment
material over a 6 month period. So, while the initial filing of the =
machine
was expensive, it lasts quite a while with minimal losses (unless you =
think
that $50/month is expensive). The vapor zone we had was fully contained =
with
only a slot at either end for the board to enter and exit. The only =
reason
we stopped using the vapor phase was due to our board sizes were =
getting too
big for our machine. We did not get another vapor phase machine because =
the
prevailing thought at that time was that the Fluorinert material would
eventually become a banned material like Freon and Tri-chlor.=20

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Stephen R. Gregory [SMTP:[log in to unmask]]
> Sent: Tuesday, March 21, 2000 4:06 PM
> To:   [log in to unmask]
> Subject:      [TN] Vapor Phase update...
>=20
> Hi ya'll!
>=20
> Well, I just got through talking with someone at 3M...the FC-71 =
product
> has=20
> been discontinued. The highest boiling point heat transfer fluid they =
make
> is=20
> the FC-70 which boils at 215 =BA C. Just for grins I asked how much =
that
> stuff=20
> sells for, and was told that it's sold by the pound. A gallon weighs
> 15-lbs,=20
> and it's $60.00 a pound! YOWZA! $900 a gallon!!!
>=20
> Called Galden Fluids, and they have a heat transfer fluid they call =
HT250=20
> which boils at 250=BA C. The say their stuff =20
> (http://www.inlandvacuum.com/galden.html) is a non ODP chemical. The =
spec=20
> sheet for all their stuff is at
> (http://www.inlandvacuum.com/galdenspecs.html)
>=20
> A gallon of the HT250 is around $560...anybody ever use this stuff?
>=20
> Still haven't found anything about the equipment. There's some used =
stuff
> out=20
> there but like Brian said in his post, I want to make sure I find
> something=20
> that I won't have to keep pouring this "liquid gold" into to be able =
run=20
> it...like the owl says; "I give a hoot, I don't wanna pollute!" (not=20
> mentioning the cost).=20
>=20
> -Steve Gregory-
>=20
> ##############################################################
> TechNet Mail List provided as a free service by IPC using LISTSERV =
1.8c
> ##############################################################
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> following text in
> the body:
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> additional
> information.
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> 847-509-9700 ext.5315
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=========================================================================
Date:         Wed, 22 Mar 2000 06:51:19 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Coating assemblies with no-clean fluxes
X-To:         Graham Naisbitt <[log in to unmask]>
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Hi Graham -

Thanks - I had intended that my original post indicate that the testing =
was to be performed on specimen composed of the selected conformal =
coating applied over the specific residues of whatever.  Guess I got in =
a bit of a hurry.

Pursuit of a workable flux which leaves only a sterile, inert, fully =
polemerized residue still eludes us.  Sort of like the alchemists of old =
pursuing conversion of lead to gold.

Regards - Kelly
    -----Original Message-----
    From: Graham Naisbitt <[log in to unmask]>
    To: Kelly M. Schriver <[log in to unmask]>; TechNet =
<[log in to unmask]>
    Date: Tuesday, March 21, 2000 9:11 AM
    Subject: Coating assemblies with no-clean fluxes
   =20
   =20
    Techies,
   =20
    This was my posting that was rejected as already sent - but wasn't!?
   =20
    Kelly,
   =20
    I must challenge your statement:
   =20
    > "be applied satisfactorily over the
    > leavings of low residue flux, or any other residue, could only be
    considered
    > valid if the conformal coating had been retested and passed  the
    > qualification requirements of IPC-CC-830, MIL-I-46058, or whatever
    > specification"
   =20
    This is misleading as it implies that any coating so tested is OK to =
apply
    over no-clean. NOT SO! These specifications require testing of the =
material
    on its own, in isolation on coupons that have been cleaned until =
they
    squeak - there shall be no flux present!
   =20
    In order to successfully coat over no-clean - and it can be done - =
you MUST
    test the entire process with totally representative coupons of YOUR =
process.
   =20
    Consider that a conformal coating is a permanent product to do a =
permanent
    job and seals in as well as out and bingo - if you have something =
nasty
    underneath, then it matters not one jot the specification approvals =
the
    coating may have.
   =20
    I repeat, it can be done, but I did not say it was easy or =
straightforward.
   =20
    Regards :-)
    Graham Naisbitt
   =20
   =20
    Regards,
    Graham Naisbitt
   =20
    [log in to unmask]
   =20
    WEB: http://www.concoat.co.uk
   =20
    CONCOAT Ltd
    Alasan House, Albany Park
    CAMBERLEY GU15 2PL UK
   =20
    Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227

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        charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>

<META content=3Dtext/html;charset=3Diso-8859-1 =
http-equiv=3DContent-Type><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 =
Transitional//EN">
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
<STYLE></STYLE>

</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 size=3D2>Hi Graham -</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Thanks - I had intended that my original post =
indicate that=20
the testing was to be performed on specimen composed of the selected =
conformal=20
coating applied over the specific residues of whatever.&nbsp; Guess I =
got in a=20
bit of a hurry.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Pursuit of a workable flux which leaves only a =
sterile, inert,=20
fully polemerized residue still eludes us.&nbsp; Sort of like the =
alchemists of=20
old pursuing conversion of lead to gold.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Regards - Kelly</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 solid 2px; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
    <DIV><FONT face=3DArial size=3D2><B>-----Original =
Message-----</B><BR><B>From:=20
    </B>Graham Naisbitt &lt;<A=20
    =
href=3D"mailto:[log in to unmask]">[log in to unmask]co.=
uk</A>&gt;<BR><B>To:=20
    </B>Kelly M. Schriver &lt;<A=20
    =
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>&g=
t;;=20
    TechNet &lt;<A=20
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A>&gt;<BR><B>Date:=20
    </B>Tuesday, March 21, 2000 9:11 AM<BR><B>Subject: </B>Coating =
assemblies=20
    with no-clean fluxes<BR><BR></DIV></FONT>
    <DIV><FONT size=3D2>Techies,</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>This was my posting that was rejected as already =
sent -=20
    but wasn't!?</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>Kelly,<BR><BR>I must challenge your =
statement:<BR><BR>&gt;=20
    &quot;be applied satisfactorily over the<BR>&gt; leavings of low =
residue=20
    flux, or any other residue, could only be<BR>considered<BR>&gt; =
valid if the=20
    conformal coating had been retested and passed&nbsp; the<BR>&gt;=20
    qualification requirements of IPC-CC-830, MIL-I-46058, or =
whatever<BR>&gt;=20
    specification&quot;<BR><BR>This is misleading as it implies that any =
coating=20
    so tested is OK to apply<BR>over no-clean. NOT SO! These =
specifications=20
    require testing of the material<BR>on its own, in isolation on =
coupons that=20
    have been cleaned until they<BR>squeak - there shall be no flux=20
    present!<BR><BR>In order to successfully coat over no-clean - and it =
can be=20
    done - you MUST<BR>test the entire process with totally =
representative=20
    coupons of YOUR process.<BR><BR>Consider that a conformal coating is =
a=20
    permanent product to do a permanent<BR>job and seals in as well as =
out and=20
    bingo - if you have something nasty<BR>underneath, then it matters =
not one=20
    jot the specification approvals the<BR>coating may have.<BR><BR>I =
repeat, it=20
    can be done, but I did not say it was easy or=20
    straightforward.<BR><BR>Regards :-)<BR>Graham =
Naisbitt<BR><BR></DIV></FONT>
    <DIV><FONT size=3D2>Regards,<BR>Graham Naisbitt</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2><A=20
    =
href=3D"mailto:[log in to unmask]">[log in to unmask]
uk</A></FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>WEB: <A=20
    =
href=3D"http://www.concoat.co.uk">http://www.concoat.co.uk</A></FONT></DI=
V>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>CONCOAT Ltd<BR>Alasan House, Albany =
Park<BR>CAMBERLEY GU15=20
    2PL UK</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>Tel: +44 (0) 1276 691100&nbsp; Fax: +44 (0) 1276 =

    691227</FONT></DIV></BLOCKQUOTE></BODY></HTML>

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=========================================================================
Date:         Wed, 22 Mar 2000 08:47:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Blomberg, Rainer (FL51)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Blomberg, Rainer (FL51)" <[log in to unmask]>
Subject:      Re: Baking FR4 boards
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Dewey,

Here at Space Systems in Florida, we have an in-house soldering process
spec. that requires vacuum bake at least 4 days (96 hrs) prior to wave
soldering.  It is intended for Polyimide boards.  The time window was
established from test data that showed how fast moisture is re-absorbed
after bake-out.  We have not had problems with using this relatively large
window.

R. G. Blomberg
Honeywell - Space Systems
Staff Production Engineer
(727) 539-5534 voice
727-539-4469 Fax
[log in to unmask]

-----Original Message-----
From: Dewey Whittaker [mailto:[log in to unmask]]
Sent: Tuesday, March 21, 2000 5:09 PM
To: [log in to unmask]
Subject: Re: [TN] Baking FR4 boards


Alain Savard wrote:

Isn't the 72 hours before bake a requirement for polyimide instead of FR4?

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]


-----Original Message-----
From: Dewey Whittaker
1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an air



conditioned environment at about 50+/- 10% RH, how many months would you
allow
to pass before you would recommend baking them prior to reflow?
2. What would be your bake cycle?
Thanks,
Charlie B.
####################################
Without knowing any other variables and being conservative,72 hours is your
window for the Aerospace Industry.
Dewey
--
Dewey Whittaker


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If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
testing and proper storage conditions,each design could have a much greater
processing window.4 hours at 100 degrees C. is the bake.
Dewey
--

Dewey Whittaker

Honeywell -- Air Transport Systems Division

US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036

Phone: +1 602 436 436-2766

NSFnet: [log in to unmask]



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<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=572181413-22032000>Dewey,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=572181413-22032000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=572181413-22032000>Here
at Space Systems in Florida, we have an in-house soldering process spec. that
requires vacuum bake at least 4 days (96 hrs) prior to wave soldering.&nbsp; It
is intended for Polyimide boards.&nbsp; The time window was established from
test data that showed how fast moisture is re-absorbed after bake-out.&nbsp; We
have not had problems with using this relatively large
window.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=572181413-22032000></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=572181413-22032000>
<P><FONT color=#800000 face="MS Sans Serif" size=2>R. G.
Blomberg</FONT><B></B><B></B><B></B> <BR><B><FONT color=#ff0000
face="MS Shell Dlg" size=1>Honeywell</FONT></B><FONT color=#ff0000
face="MS Shell Dlg" size=1></FONT><B></B><B> <FONT color=#000000
face="MS Shell Dlg" size=1>-</FONT></B> <FONT color=#800000 face="MS Sans Serif"
size=1>S</FONT><FONT color=#800000 face="MS Sans Serif" size=1>pace
Systems</FONT> <BR><FONT color=#800000 face="MS Sans Serif" size=1>Staff
Production Engineer</FONT> <BR><FONT color=#800000 face="MS Sans Serif"
size=1>(727) 539-5534 voice</FONT> <BR><FONT color=#800000 face="MS Sans Serif"
size=1>727-539-4469 Fax</FONT> <BR><FONT color=#800000 face="MS Sans Serif"
size=1>r</FONT><FONT color=#800000 face="MS Sans Serif"
size=1>ainer.</FONT><FONT color=#800000 face="MS Sans Serif"
size=1>[log in to unmask]</FONT> </P></SPAN></FONT></DIV>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
  size=2>-----Original Message-----<BR><B>From:</B> Dewey Whittaker
  [mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, March 21, 2000
  5:09 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Baking FR4
  boards<BR><BR></DIV></FONT>Alain Savard wrote:
  <BLOCKQUOTE TYPE="CITE">Isn't the 72 hours before bake a requirement for
    polyimide instead of FR4?
    <P>Alain Savard, B.Sc. <BR>Chemical Process Analyst <BR>CAE Electronics Ltd.
    <BR>e-mail: [log in to unmask]
    <P>-----Original Message----- <BR>From: Dewey Whittaker <BR>1. Typically,
    for multi-layer (6-8 layers), FR4, SMT boards stored in an air
    <P>conditioned environment at about 50+/- 10% RH, how many months would you
    <BR>allow <BR>to pass before you would recommend baking them prior to
    reflow? <BR>2. What would be your bake cycle? <BR>Thanks, <BR>Charlie B.
    <BR>#################################### <BR>Without knowing any other
    variables and being conservative,72 hours is your <BR>window for the
    Aerospace Industry. <BR>Dewey <BR>-- <BR>Dewey Whittaker
    <P>##############################################################
    <BR>TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
    <BR>############################################################## <BR>To
    subscribe/unsubscribe, send a message to [log in to unmask] with following
    text in <BR>the body: <BR>To subscribe:&nbsp;&nbsp; SUBSCRIBE TECHNET
    &lt;your full name&gt; <BR>To unsubscribe:&nbsp;&nbsp; SIGNOFF TECHNET
    <BR>##############################################################
    <BR>Please visit IPC web site (<A
    href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</A>)
    for additional <BR>information. <BR>If you need assistance - contact Keach
    Sasamori at [log in to unmask] or <BR>847-509-9700 ext.5315
    <BR>##############################################################</P></BLOCKQUOTE>If
  it were Polyimide,it would be 24 hours(realistically 8 hours).Through testing
  and proper storage conditions,each design could have a much greater processing
  window.4 hours at 100 degrees C. is the bake. <BR>Dewey <PRE>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</PRE>&nbsp; </BLOCKQUOTE></BODY></HTML>

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Date:         Wed, 22 Mar 2000 06:51:24 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dewey Whittaker <[log in to unmask]>
Organization: Honeywell Inc.
Subject:      Re: Baking FR4 boards
X-To:         "Howieson, Rick" <[log in to unmask]>
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"Howieson, Rick" wrote:

> Out of curiosity, where are these requirements stated?
> Rick
>
> >-----Original Message-----
> >From:  Dewey Whittaker [SMTP:[log in to unmask]]
> >Sent:  Tuesday, March 21, 2000 3:09 PM
> >To:    [log in to unmask]
> >Subject:       Re: [TN] Baking FR4 boards
> >
> >Alain Savard wrote:
> >
> >> Isn't the 72 hours before bake a requirement for polyimide instead of FR4?
> >>
> >> Alain Savard, B.Sc.
> >> Chemical Process Analyst
> >> CAE Electronics Ltd.
> >> e-mail: [log in to unmask]
> >>
> >> -----Original Message-----
> >> From: Dewey Whittaker
> >> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an
> >>air
> >>
> >> conditioned environment at about 50+/- 10% RH, how many months would you
> >> allow
> >> to pass before you would recommend baking them prior to reflow?
> >> 2. What would be your bake cycle?
> >> Thanks,
> >> Charlie B.
> >> ####################################
> >> Without knowing any other variables and being conservative,72 hours is your
> >> window for the Aerospace Industry.
> >> Dewey
> >> --
> >> Dewey Whittaker
> >>
> >> ##############################################################
> >> TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
> >> ##############################################################
> >> To subscribe/unsubscribe, send a message to [log in to unmask] with following
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> >> Please visit IPC web site (http://www.ipc.org/html/forum.htm) for
> >>additional
> >> information.
> >> If you need assistance - contact Keach Sasamori at [log in to unmask] or
> >> 847-509-9700 ext.5315
> >> ##############################################################
> >
> >If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
> >testing and proper storage conditions,each design could have a much greater
> >processing window.4 hours at 100 degrees C. is the bake.
> >Dewey
> >
> >--
> >Dewey Whittaker
> >Honeywell -- Air Transport Systems Division
> >US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
> >Phone: +1 602 436 436-2766
> >NSFnet: [log in to unmask]
> >
> >
> >
> ><!doctype html public "-//w3c//dtd html 4.0 transitional//en">
> ><html>
> >Alain Savard wrote:
> ><blockquote TYPE=CITE>Isn't the 72 hours before bake a requirement for
> >polyimide instead of FR4?
> ><p>Alain Savard, B.Sc.
> ><br>Chemical Process Analyst
> ><br>CAE Electronics Ltd.
> ><br>e-mail: [log in to unmask]
> ><p>-----Original Message-----
> ><br>From: Dewey Whittaker
> ><br>1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored
> >in an air
> ><p>conditioned environment at about 50+/- 10% RH, how many months would
> >you
> ><br>allow
> ><br>to pass before you would recommend baking them prior to reflow?
> ><br>2. What would be your bake cycle?
> ><br>Thanks,
> ><br>Charlie B.
> ><br>####################################
> ><br>Without knowing any other variables and being conservative,72 hours
> >is your
> ><br>window for the Aerospace Industry.
> ><br>Dewey
> ><br>--
> ><br>Dewey Whittaker
> ><p>##############################################################
> ><br>TechNet Mail List provided as a free service by IPC using LISTSERV
> >1.8c
> ><br>##############################################################
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> >following
> >text in
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> ><br>##############################################################
> ><br>Please visit IPC web site (<a
> >href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a
> >>)
> >for additional
> ><br>information.
> ><br>If you need assistance - contact Keach Sasamori at [log in to unmask] or
> ><br>847-509-9700 ext.5315
> ><br>##############################################################</blockquot
> >e>
> >If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
> >testing and proper storage conditions,each design could have a much greater
> >processing window.4 hours at 100 degrees C. is the bake.
> ><br>Dewey
> ><pre>--&nbsp;
> >Dewey Whittaker
> >Honeywell -- Air Transport Systems Division
> >US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
> >Phone: +1 602 436 436-2766
> >NSFnet: [log in to unmask]</pre>
> >&nbsp;</html>
> >
>
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In our own internal specifications and for some of our assemblies it is overkill,but given the cost of a lot of our products and the end use it is
cheap insurance.
Dewey

--
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]



--------------BCBECBD89457951E37AADACF
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
"Howieson, Rick" wrote:
<blockquote TYPE=CITE>Out of curiosity, where are these requirements stated?
<br>Rick
<p>>-----Original Message-----
<br>>From:&nbsp; Dewey Whittaker [SMTP:[log in to unmask]]
<br>>Sent:&nbsp; Tuesday, March 21, 2000 3:09 PM
<br>>To:&nbsp;&nbsp;&nbsp; [log in to unmask]
<br>>Subject:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Re: [TN] Baking FR4 boards
<br>>
<br>>Alain Savard wrote:
<br>>
<br>>> Isn't the 72 hours before bake a requirement for polyimide instead
of FR4?
<br>>>
<br>>> Alain Savard, B.Sc.
<br>>> Chemical Process Analyst
<br>>> CAE Electronics Ltd.
<br>>> e-mail: [log in to unmask]
<br>>>
<br>>> -----Original Message-----
<br>>> From: Dewey Whittaker
<br>>> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored
in an
<br>>>air
<br>>>
<br>>> conditioned environment at about 50+/- 10% RH, how many months would
you
<br>>> allow
<br>>> to pass before you would recommend baking them prior to reflow?
<br>>> 2. What would be your bake cycle?
<br>>> Thanks,
<br>>> Charlie B.
<br>>> ####################################
<br>>> Without knowing any other variables and being conservative,72 hours
is your
<br>>> window for the Aerospace Industry.
<br>>> Dewey
<br>>> --
<br>>> Dewey Whittaker
<br>>>
<br>>> ##############################################################
<br>>> TechNet Mail List provided as a free service by IPC using LISTSERV
1.8c
<br>>> ##############################################################
<br>>> To subscribe/unsubscribe, send a message to [log in to unmask] with
following
<br>>>text in
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<br>>> To unsubscribe:&nbsp;&nbsp; SIGNOFF TECHNET
<br>>> ##############################################################
<br>>> Please visit IPC web site (<a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>)
for
<br>>>additional
<br>>> information.
<br>>> If you need assistance - contact Keach Sasamori at [log in to unmask]
or
<br>>> 847-509-9700 ext.5315
<br>>> ##############################################################
<br>>
<br>>If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
<br>>testing and proper storage conditions,each design could have a much
greater
<br>>processing window.4 hours at 100 degrees C. is the bake.
<br>>Dewey
<br>>
<br>>--
<br>>Dewey Whittaker
<br>>Honeywell -- Air Transport Systems Division
<br>>US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
<br>>Phone: +1 602 436 436-2766
<br>>NSFnet: [log in to unmask]
<br>>
<br>>
<br>>
<br>>&lt;!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<br>>&lt;html>
<br>>Alain Savard wrote:
<br>>&lt;blockquote TYPE=CITE>Isn't the 72 hours before bake a requirement
for
<br>>polyimide instead of FR4?
<br>>&lt;p>Alain Savard, B.Sc.
<br>>&lt;br>Chemical Process Analyst
<br>>&lt;br>CAE Electronics Ltd.
<br>>&lt;br>e-mail: [log in to unmask]
<br>>&lt;p>-----Original Message-----
<br>>&lt;br>From: Dewey Whittaker
<br>>&lt;br>1. Typically, for multi-layer (6-8 layers), FR4, SMT boards
stored
<br>>in an air
<br>>&lt;p>conditioned environment at about 50+/- 10% RH, how many months
would
<br>>you
<br>>&lt;br>allow
<br>>&lt;br>to pass before you would recommend baking them prior to reflow?
<br>>&lt;br>2. What would be your bake cycle?
<br>>&lt;br>Thanks,
<br>>&lt;br>Charlie B.
<br>>&lt;br>####################################
<br>>&lt;br>Without knowing any other variables and being conservative,72
hours
<br>>is your
<br>>&lt;br>window for the Aerospace Industry.
<br>>&lt;br>Dewey
<br>>&lt;br>--
<br>>&lt;br>Dewey Whittaker
<br>>&lt;p>##############################################################
<br>>&lt;br>TechNet Mail List provided as a free service by IPC using LISTSERV
<br>>1.8c
<br>>&lt;br>##############################################################
<br>>&lt;br>To subscribe/unsubscribe, send a message to [log in to unmask]
with
<br>>following
<br>>text in
<br>>&lt;br>the body:
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full name>
<br>>&lt;br>To unsubscribe:&amp;nbsp;&amp;nbsp; SIGNOFF TECHNET
<br>>&lt;br>##############################################################
<br>>&lt;br>Please visit IPC web site (&lt;a
<br>>href="<a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>"><a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>&lt;/a
<br>>>)
<br>>for additional
<br>>&lt;br>information.
<br>>&lt;br>If you need assistance - contact Keach Sasamori at [log in to unmask]
or
<br>>&lt;br>847-509-9700 ext.5315
<br>>&lt;br>##############################################################&lt;/blockquot
<br>>e>
<br>>If it were Polyimide,it would be 24 hours(realistically 8 hours).Through
<br>>testing and proper storage conditions,each design could have a much
greater
<br>>processing window.4 hours at 100 degrees C. is the bake.
<br>>&lt;br>Dewey
<br>>&lt;pre>--&amp;nbsp;
<br>>Dewey Whittaker
<br>>Honeywell -- Air Transport Systems Division
<br>>US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
<br>>Phone: +1 602 436 436-2766
<br>>NSFnet: [log in to unmask]&lt;/pre>
<br>>&amp;nbsp;&lt;/html>
<br>>
<p>##############################################################
<br>TechNet Mail List provided as a free service by IPC using LISTSERV
1.8c
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text in
<br>the body:
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<br>##############################################################
<br>Please visit IPC web site (<a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>)
for additional
<br>information.
<br>If you need assistance - contact Keach Sasamori at [log in to unmask] or
<br>847-509-9700 ext.5315
<br>##############################################################</blockquote>
In our own internal specifications and for some of our assemblies it is
overkill,but given the cost of a lot of our products and the end use it
is cheap insurance.
<br>Dewey
<pre>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</pre>
&nbsp;</html>

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Date:         Wed, 22 Mar 2000 07:44:37 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         [log in to unmask]
MIME-Version: 1.0
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Hi Steve & All -

On the subject of used equipment - be extremely cautious.  A great deal of
the stuff sitting around moldering in warehouses will turn out to be
articles which have not had the best in maintenance, and may even be
suffering from a severe case of rot from previous usage.  These units can
generate small quanitities of HCl, which is removed by the acid stripper, if
the unit is properly maintained.  (I've seen quite a few that weren't.)  The
second issue, will obviously be the availabililty of repair/rebuild parts.
You may also find that these units have mechanical timers, which require a
fair amount of operator input to set-up and monitor.

Reflow fluid is only one issue, in the area of consumables.  The second is
the question of what containment media is used to prevent escape or major
loss of the reflow fluid.  In the days past, this was one of the freons
which has since gone out of production.  This freon blanket, was in turn
kept in place by a refrigeration or water cooling coil around the upper
third of the batch unit.  If you go forward with this effort, you will need
to be careful about the selection of a cover blanket media suitable for the
temperature of the refllow fluid.  Exhaust vent location and velocity also
needs to be set-up carefully - too high an airflow rate can siphon off the
cover blanket vapors, allowing loss of the primary fluid vapors.

We had a couple of experiences on a batch unit (using FC-70/FC-71), where
the temp controllers failed and ran the boil sump heaters wide open.  This
in turn overran the capability of the freon blanket to contain the reflow
vapors.  Fortunately, we had added some instrumentation around the units
upper lip and did a manual shut down without major problems.

I am not sure about the availability of solder pastes and fluxes for vapor
phase use.  This is another item which will need to be checked, since the
process is not in as high usage as it once was.

Regards - Kelly

-----Original Message-----
From: Stephen R. Gregory <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Tuesday, March 21, 2000 7:47 PM
Subject: Re: [TN] Vapor Phase reflow chemicals and equipment..


>In a message dated 03/21/2000 6:46:27 PM Central Standard Time, Engelmaier
>writes:
>
>> Hi Steve,
>>  Downhole drilling electronics sees the most severe operational loading
of
>> any ellectronic assemblies. Design this stuff as robust as possible with
>the
>> least CTE-mismatch as possible, and be careful with the encapsulant
>material
>> chosen.
>>  Vapor phase soldering is a good idea; but, is there nothing between 253
>and
>> 215C?
>>  Good luck!
>>  Werner Engelmaier
>
>Hi Werner!
>
>Yeah, don't have tell me about how harsh an environment these boards will
>see, it's easy for anyone to imagine what these boards will go though. They
>go into a metal "tool" (about 9 boards per tool) that's about 8"-10" in
>diameter and about 10-feet long.
>
>The boards are very thin width-wise (less than 2-inches) and about a foot
>long. They are polyimide (I think) PCB's with a lot of copper in them. We
>don't control the designs, we're just gonna try and build them.
>
>After going back and looking at the Galden Fluids spec's, they do make a
>chemical that has a boiling point of 230 degrees C. I suppose with vapor
>phase you don't have to follow the standard guidelines for reflow profiling
>of hitting a peak of 20-30 degrees above liquidous of the alloy...that's
more
>for standard reflow equipment isn't it?
>
>With a chemical like the Galden HT230, I won't have to worry so much that
>there will be any temperature lags that one may see with convection or IR
>reflow....
>
>I'm still looking for equipment though...
>
>Thanks Werner!
>
>-Steve Gregory-
>
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Date:         Wed, 22 Mar 2000 08:51:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mark Weckworth <[log in to unmask]>
Subject:      Spots on Cu surfaces after OSP coating
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Back in '97, a message was posted asking about dark spots on OSP surfaces.  The
message described it as looking like the "fungus" you would see on an old
orange.  These spots seem localized and are found on the BGA pads and annular
rings.  I would like to know if anyone has any more insight as to what it may
be, what causes it, and how to prevent it.  Aside form that single message and
single response back in '97, nothing else appears in the archives.

Any information would be greatly appreciated.

Thanks in advance,

Mark W

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Date:         Wed, 22 Mar 2000 09:10:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Carano,Michael" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Carano,Michael" <[log in to unmask]>
Subject:      Re: Spots on Cu surfaces after OSP coating
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Mark,

Do these spots look "crystalline" in nature? I ask this because, while I
have never seen it as dark, sometimes the active component of an OSP can
crystallize out of solution and deposit as a crystal structure. I recall the
spots actually looked white. Under a 10X power on  a scope you could examine
the spot more closely, if you haven't already. You could try to clean the
spot with a swab of rubbing alcohol. If the spot cleans easily, it could
indicate that the material is organic in nature. Possibly an ionic residue
reacting in some way?

Good luck,

Mike

        -----Original Message-----
        From:   Mark Weckworth [SMTP:[log in to unmask]]
        Sent:   Wednesday, March 22, 2000 7:52 AM
        To:     [log in to unmask]
        Subject:        [TN] Spots on Cu surfaces after OSP coating

        Back in '97, a message was posted asking about dark spots on OSP
surfaces.  The
        message described it as looking like the "fungus" you would see on
an old
        orange.  These spots seem localized and are found on the BGA pads
and annular
        rings.  I would like to know if anyone has any more insight as to
what it may
        be, what causes it, and how to prevent it.  Aside form that single
message and
        single response back in '97, nothing else appears in the archives.

        Any information would be greatly appreciated.

        Thanks in advance,

        Mark W

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Date:         Wed, 22 Mar 2000 09:16:11 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: Baking FR4 boards
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

There is no actual requirement, it is more of a factual moisture absorption
effect. Polyimide absorbs water a lot faster then FR4. I don't know of much
of a problem with using FR4 up to 6 months old. After that we may recommend
prebake. This is an in-house specification, I don't know of any IPC
specification for it.



Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Dewey Whittaker
Subject: Re: [TN] Baking FR4 boards


"Howieson, Rick" wrote:
Out of curiosity, where are these requirements stated?
Rick
>-----Original Message-----
>From:  Dewey Whittaker
>Subject:       Re: [TN] Baking FR4 boards
>
>Alain Savard wrote:
>
>> Isn't the 72 hours before bake a requirement for polyimide instead of
FR4?
>>
>> Alain Savard, B.Sc.
>> Chemical Process Analyst
>> CAE Electronics Ltd.
>> e-mail: [log in to unmask]
>>
>> -----Original Message-----
>> From: Dewey Whittaker
>> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an
>>air
>>
>> conditioned environment at about 50+/- 10% RH, how many months would you
>> allow
>> to pass before you would recommend baking them prior to reflow?
>> 2. What would be your bake cycle?
>> Thanks,
>> Charlie B.

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Date:         Wed, 22 Mar 2000 06:38:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Vaughan, Ralph H" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Vaughan, Ralph H" <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Just curious...what sorts of temperatures/durations do these downhole
drilling electronics see?

Ralph Vaughan

> ----------
> From:         Werner Engelmaier[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;[log in to unmask]
> Sent:         Tuesday, March 21, 2000 7:46 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] Vapor Phase reflow chemicals and equipment..
>
> Hi Steve,
> Downhole drilling electronics sees the most severe operational loading of
> any
> ellectronic assemblies. Design this stuff as robust as possible with the
> least CTE-mismatch as possible, and be careful with the encapsulant
> material
> chosen.
> Vapor phase soldering is a good idea; but, is there nothing between 253
> and
> 215C?
> Good luck!
> Werner Engelmaier
>
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Date:         Wed, 22 Mar 2000 10:10:15 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Phillip E. Hinton" <[log in to unmask]>
Subject:      Re: Vapor Phase reflow chemicals and equipment..
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Ralph

In downhole drilling the electronic units will often see 200 deg. C for
several weeks or the tools may come out of the hole and lay in a  snow bank
in Alaska or Siberia for a a couple of weeks and then return to another hole
for a repeat of the hot downhole opertion again.  It requires some different
techniques, solders, finishes etc. to withstand this harsh operating
envirorment.

Phil Hinton

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Date:         Wed, 22 Mar 2000 09:14:00 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Baking FR4 boards
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Understand, especially with through hole mounting and the problems with
blow holes. But I believe Dewey was talking about SMT. With thin
coatings in a humid environment I'm sure the copper can become oxidized
and create soldering problems. What about moisture after assembly and
prior to say conformal coating?
Rick

>-----Original Message-----
>From:  Alain Savard [SMTP:[log in to unmask]]
>Sent:  Wednesday, March 22, 2000 7:16 AM
>To:    [log in to unmask]
>Subject:       Re: [TN] Baking FR4 boards
>
>There is no actual requirement, it is more of a factual moisture absorption
>effect. Polyimide absorbs water a lot faster then FR4. I don't know of much
>of a problem with using FR4 up to 6 months old. After that we may recommend
>prebake. This is an in-house specification, I don't know of any IPC
>specification for it.
>
>
>
>Alain Savard, B.Sc.
>Chemical Process Analyst
>CAE Electronics Ltd.
>e-mail: [log in to unmask]
>
>-----Original Message-----
>From: Dewey Whittaker
>Subject: Re: [TN] Baking FR4 boards
>
>
>"Howieson, Rick" wrote:
>Out of curiosity, where are these requirements stated?
>Rick
>>-----Original Message-----
>>From:  Dewey Whittaker
>>Subject:       Re: [TN] Baking FR4 boards
>>
>>Alain Savard wrote:
>>
>>> Isn't the 72 hours before bake a requirement for polyimide instead of
>FR4?
>>>
>>> Alain Savard, B.Sc.
>>> Chemical Process Analyst
>>> CAE Electronics Ltd.
>>> e-mail: [log in to unmask]
>>>
>>> -----Original Message-----
>>> From: Dewey Whittaker
>>> 1. Typically, for multi-layer (6-8 layers), FR4, SMT boards stored in an
>>>air
>>>
>>> conditioned environment at about 50+/- 10% RH, how many months would you
>>> allow
>>> to pass before you would recommend baking them prior to reflow?
>>> 2. What would be your bake cycle?
>>> Thanks,
>>> Charlie B.
>
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Date:         Wed, 22 Mar 2000 11:39:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Wolfe, Robert" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Wolfe, Robert" <[log in to unmask]>
Subject:      Re: Land Pattern for LED PL-CC-2
X-To:         "Hamilton, Richard CLE 4454" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Richard,
We have used the following on a number of designs with no problems. (at
least that we have been made aware of).

Pads size is .060 x .090 (1.5mm x 2.3mm)
Pads spaced center to center at .120 (3.05mm)

Therefore the IPC equivilent dimensions from 782A based on a chip type part
(cap/res) would be as follows.
Z  = .180 (4.6mm)
G = .060 (1.5mm)
C = .120 (3.05mm)
X =  .090 (1.5mm)
Y = .060 (2.3mm)

Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]
> -----Original Message-----
> From: Hamilton, Richard CLE 4454 [SMTP:[log in to unmask]]
> Sent: Monday, March 20, 2000 12:19 PM
> To:   [log in to unmask]
> Subject:      [TN] Land Pattern for LED PL-CC-2
>
> Does anyone happen to have a suggested land pattern for an LED by Siemens
> identified as an PL-CC-2?
>
> Thanks in advance!
>
> Richard Hamilton
> Clemar Mfg. / Rain Bird
> [log in to unmask]
>
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Date:         Wed, 22 Mar 2000 11:50:02 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Charles E. McMahon" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Charles E. McMahon" <[log in to unmask]>
Organization: McMahon Sales Company, Inc.
Subject:      BARE BOARD TEST MACHINES
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hello Tech-Net:

I am asking for suggestions as to the best bare board tester that can be
purchased for high density SMT designs.

Design rules include 1.5 mil SMT pads and 3 mil pitch.
Volume is low.
We already have a flying probe but want to add a dual access test fixture.
Direct IPC 356 net list down load is also required.

Suggestions of where to go (and what the pricing might be) would be most
appreciated.

Thank you

Charlie McMahon
[log in to unmask]



----- Original Message -----
From: Wolfe, Robert <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 22, 2000 11:39 AM
Subject: Re: [TN] Land Pattern for LED PL-CC-2


> Richard,
> We have used the following on a number of designs with no problems. (at
> least that we have been made aware of).
>
> Pads size is .060 x .090 (1.5mm x 2.3mm)
> Pads spaced center to center at .120 (3.05mm)
>
> Therefore the IPC equivilent dimensions from 782A based on a chip type
part
> (cap/res) would be as follows.
> Z  = .180 (4.6mm)
> G = .060 (1.5mm)
> C = .120 (3.05mm)
> X =  .090 (1.5mm)
> Y = .060 (2.3mm)
>
> Executone Inter-Tel Business Information Systems, Inc.
> Robert M. Wolfe C.I.D.
> Lead PCB Designer
> 478 Wheelers Farms Road
> Milford, CT 06460
> Phone: 203-882-6405
> Fax:   203-882-2727
> Email: [log in to unmask]
> > -----Original Message-----
> > From: Hamilton, Richard CLE 4454 [SMTP:[log in to unmask]]
> > Sent: Monday, March 20, 2000 12:19 PM
> > To:   [log in to unmask]
> > Subject:      [TN] Land Pattern for LED PL-CC-2
> >
> > Does anyone happen to have a suggested land pattern for an LED by
Siemens
> > identified as an PL-CC-2?
> >
> > Thanks in advance!
> >
> > Richard Hamilton
> > Clemar Mfg. / Rain Bird
> > [log in to unmask]
> >
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Date:         Wed, 22 Mar 2000 09:56:00 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Luis Alcantra <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Luis Alcantra <[log in to unmask]>
Subject:      ?BEST PROFILE FOR GOLD PLATED PINS
Mime-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
Content-Transfer-Encoding: 7BIT

Hi every one:
             We are currently experiencing some dificulties soldering gold
plated pins, they go on a 1/2 of an inch square pcb w/a cap an a resistor.
we had tried several profiles with no satisfactory results, we are using
kester #Sn63Pb37 solder on a Vitronics 722 20 zone reflow oven as follows:
165-175-250-  -260-260-260-260-260-280-400 degrees temp. it may seen to
high but our pcb fixture is thick an pcb bar holders on each side.

The problem is solder looks GRAINNY/COLD any suggestions for a good solder
paste/profile?

regards.

LUIS ALCANTARA
ENGINEERING DEPT.
[log in to unmask]
(623) 516-3700

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Date:         Wed, 22 Mar 2000 12:22:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Valladares, Hector A (FL51)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Valladares, Hector A (FL51)" <[log in to unmask]>
Subject:      Re: ?BEST PROFILE FOR GOLD PLATED PINS
X-To:         Luis Alcantra <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Check the amount of gold in your pins first you may have more gold than you
can properly dissolve in the paste you are putting on your PWA. The grainy
look may com from a slow cool down based on your thick holder info. Look at
your total gold content first you may be dealing with possible gold
embrittlement.
Good luck

Hector Valladares
Honeywell -SASSO
Production Staff Engineer
727.539.3683 voice
727.539.4469 Fax
[log in to unmask]



-----Original Message-----
From: Luis Alcantra [mailto:[log in to unmask]]
Sent: Wednesday, March 22, 2000 11:56 AM
To: [log in to unmask]
Subject: [TN] ?BEST PROFILE FOR GOLD PLATED PINS


Hi every one:
             We are currently experiencing some dificulties soldering gold
plated pins, they go on a 1/2 of an inch square pcb w/a cap an a resistor.
we had tried several profiles with no satisfactory results, we are using
kester #Sn63Pb37 solder on a Vitronics 722 20 zone reflow oven as follows:
165-175-250-  -260-260-260-260-260-280-400 degrees temp. it may seen to
high but our pcb fixture is thick an pcb bar holders on each side.

The problem is solder looks GRAINNY/COLD any suggestions for a good solder
paste/profile?

regards.

LUIS ALCANTARA
ENGINEERING DEPT.
[log in to unmask]
(623) 516-3700

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Date:         Wed, 22 Mar 2000 19:30:57 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Christophe CROCOMBETTE <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Christophe CROCOMBETTE <[log in to unmask]>
Subject:      RECOATING OF GOLD FINGERS

Hi techers,

has anybody already tried to re-coat used gold fingers (edge board connectors) in order to improve their livetimes ?
is there a standardised method to strip the old Au/Ni layer and to coat  a new one which would not damage the PWA ?
thanks all

Chris

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Date:         Wed, 22 Mar 2000 13:20:21 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jim Mayes <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jim Mayes <[log in to unmask]>
Subject:      Downhole temperatures
X-To:         "Vaughan, Ralph H" <[log in to unmask]>
In-Reply-To:  <[log in to unmask]
              oeing.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

 > 200 C




_________________________________________________________________
James C. Mayes (Jim)            Office  1 281 285 7631
Manager, Common Products        Fax     1 281 285 4506
          and Standardization
Schlumberger - SPC              Alternate  285 8337 (Rose)
200 Gillingham Rm 604   Home   In LDAP
Sugar Land, Texas 77478 Pager   In LDAP

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Date:         Wed, 22 Mar 2000 14:32:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brent Stayer <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brent Stayer <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
Mime-Version: 1.0
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--=_550CB9C3.32533D75
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My experience with UV curable glue in HALT has not been favorable.  It =
will probably work fine in most applications, but crack when put through =
extreme temperature.  I'm not telling you to back off on the what works =
for you, however, we had to go away from it because we conducted HASS on =
100% of our products and was not reliable after HASS.  We switched over to =
E6000 (brand name) which could take the extremes.  E6000 requires a longer =
cure time which caused more problems for manufacturing than UV curable, =
but we were more worried about reliability than making product faster in =
production.

>>> [log in to unmask] 03/20/00 05:05PM >>>
OK, I know, I know. Why is anyone still using thru hole parts which have =
to
be bonded to the board......!!

Well. all I can say is that we are and the question I have for this group
is what are the requirements for how much and how high.

Here's the background info:

An automotive electronics circuit card has about seven very tall
electrolytic caps on it which need to be secured to the board so that the
vibration does not sever the two leads on these parts.  Historically I =
have
always asked that these be bonded 360 degrees around the perimeter and a
minimum of 50%, up to a maximum of 100% of the height of the part using a
thixotropic UV cure adhesive.  This way the part could not bend or move at
all.

Using this criteria, I have never seen a failure as a result of the =
bonding.

Here's the problem:

A new engineer decides to minimize the adhesive amount (due to cycle time
of course) so that just it connects the board and the bottom of the part
only (maybe as high as .15" total which only allows about .10" of contact
to the body of the part.  These parts are .75" tall.  The new engineer
feels justified because the products which were bonded this way made it
thru a HALT test exposure without electrical failures.

I look at the assemblies which are supposedly OK and find that the =
adhesive
has broken loose from the pwb on at least five out of the seven parts and
what is remaining on the parts have fracture lines as well.

I consider this condition unacceptable and feel that after environmental
testing, adhesive bonding should remain intact 100%.

Am I right or should I yield since the assemblies made it thru the HALT
testing?  What bonding requirements do you impose for these type of parts

All comments are welcome.


-----------------------------------------------------
Click here for Free Video!!
http://www.gohip.com/freevideo/

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Date:         Wed, 22 Mar 2000 14:38:29 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Julie Dixon <[log in to unmask]>
Subject:      Low Current Density Smut
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Dear Net,

1. Is there a name, we use smut, for the slimy, dark brown-black deposit in
low
current density areas on panels in acid copper plating? It wipes off as a goo
down
to the foil copper.
2. Is it related to DML boards only? Palladium on surface issue?
Or is it related to DML's reaction with the brightner system in the plating
bath?
I've been told it's brightner related, but it never occurs on anything not
DML'd.

 -Cold panels 70 F almost always manifest it.
 - But recently we saw it on 74 F panels plated at 35 asf for the first 5
minutes.
   a. bath had been inactive for 5 days, but continuously filtered, and air
agitation
       had been on for 2 hours prior to plate. Anode film?
   b. design was a horrendous mismatch of copper area. We panelized best we
could
        front side-   1-9"         9-18"     the front 1-9" area smutted.
Other area were ok.
                         10x            1x
                         copper area
        back side-   1-9"         9-18"
                           1x           10x

Any experience with this? We thought we'd shelved this prob. with 98 F rinses
in the
pre plate. Sulfuric dip and plating bath are at the mercy of ambient
conditions, typic
74 F.

Thanks,
Julie

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Date:         Wed, 22 Mar 2000 15:01:35 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi
In a message dated 03/22/0 15:32:35, [log in to unmask] writes:
>My experience with UV curable glue in HALT has not been favorable.  It
>will probably work fine in most applications, but crack when put through
>extreme temperature.  I'm not telling you to back off on the what works
>for you, however, we had to go away from it because we conducted HASS on
>100% of our products and was not reliable after HASS.  We switched over
>to E6000 (brand name) which could take the extremes.  E6000 requires a
>longer cure time which caused more problems for manufacturing than UV
curable,
>but we were more worried about reliability than making product faster in
>production.
People think that HASS and HALT are magic bullets--HIGHLY ACCELERATED=HIGHLY
DESTRUCTIVE. For most electronic assemblies these HA/HA (bun fully intended)
tests a misleading, overly destructive, and have the effectiveness of a
'security blanket' (security blankets keep the goblins away, and my grandkids
swear that it works).
Werner Engelmaier

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Date:         Wed, 22 Mar 2000 15:12:31 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Oberle, Wade" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Oberle, Wade" <[log in to unmask]>
Subject:      process control of final cleanliness in a no-clean world
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dear technetters,
        How do all of you in the no-clean world monitor and control board
cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
monitor our 'cleaning' process.  Do some of you still use an ionic
contamination tester or do you use SIR testing or nothing or what?

Thanks in advance for your advice.

Wade Oberle


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Date:         Wed, 22 Mar 2000 16:48:33 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Russell S Gregory <[log in to unmask]>
Subject:      Bonding details for Blind Vias
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Dear Technet,

I am puzzled about the recommended process for sequential bonding of via
layers to give blind vias with resin caps that can be used when plated over
for electrical test points?

Do you Oxide treat the plated inner layer and then bond the board allowing
the prepreg to flow up the plated via? How do u stop the resin spewing out?
What is the best type of release film?  Is there anything special to look out
for in the bonding process?
What do u do after u bonding prior to subsequent PTH plating? Is it best to
brush or desmear or both?

Help?

Russ

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Date:         Wed, 22 Mar 2000 17:00:49 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi Paul,
I must assume you don not have grandchildren; a security blanket is a baby
blanket that most kids use to fall asleep with and for which a replacement is
not acceptable no matter how shabby and threadbare the blanket has become--
and a goblin is ghost, also hobgoblin. Security blankets also have been known
to ward off leprechauns, monsters, witches, dragons, bad guys, and other
assorted imaginary beings kids come up with primarily to delay going
tobed/sleep.
Sorry guys (don't flame me) but I could not resist this one.
Werner

In a message dated 3/22/00 13:31:17, [log in to unmask] writes:
>Got me on this one Werner ;
>WHAT is a security blanket ? and what is a goblin ?
>Got the gist of it (they're close to useless).
>Pardon my down south nonfluence with latest Americana, just puzzled, not
bullet >proof kevlar weave ?
>Paul

>-----Original Message-----
>From: Werner Engelmaier [mailto:[log in to unmask]]
>Sent: Thursday, 23 March 2000 7:02
>To: [log in to unmask]
>Subject: Re: [TN] Electrolytic Capacitor Staking Requirements
>Hi
>In a message dated 03/22/0 15:32:35, [log in to unmask] writes:
>>My experience with UV curable glue in HALT has not been favorable.  It
>>will probably work fine in most applications, but crack when put through
>>extreme temperature.  I'm not telling you to back off on the what works
>>for you, however, we had to go away from it because we conducted HASS on
>>100% of our products and was not reliable after HASS.  We switched over
>>to E6000 (brand name) which could take the extremes.  E6000 requires a
>>longer cure time which caused more problems for manufacturing than UV
>>curable, but we were more worried about reliability than making product
faster
>>in production.
>
>People think that HASS and HALT are magic bullets--HIGHLY ACCELERATED=HIGHLY
>DESTRUCTIVE. For most electronic assemblies these HA/HA (bun fully intended)
>tests a misleading, overly destructive, and have the effectiveness of a
>'security blanket' (security blankets keep the goblins away, and my grandkids
>swear that it works).
>Werner Engelmaier

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=========================================================================
Date:         Wed, 22 Mar 2000 15:08:01 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Kalgren <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Kalgren <[log in to unmask]>
Subject:      Re: Electrolytic Capacitor Staking Requirements
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Werner,=20
You must also include "Teddy Bears" in your lexicon of childhood protective=
 devices.  I know that my Teddy was responsible for my safety after the =
lights were down and suspect that he fought off more monsters than he let =
on.  Probably trying to spare me the gory details!


Eric Kalgren
BFGoodrich Aerospace
Space Flight Systems
[log in to unmask]
(505) 938-5139

>>> Werner Engelmaier <[log in to unmask]> 3/22/2000 3:00:49 PM >>>
Hi Paul,
I must assume you don not have grandchildren; a security blanket is a baby
blanket that most kids use to fall asleep with and for which a replacement =
is
not acceptable no matter how shabby and threadbare the blanket has =
become--
and a goblin is ghost, also hobgoblin. Security blankets also have been =
known
to ward off leprechauns, monsters, witches, dragons, bad guys, and other
assorted imaginary beings kids come up with primarily to delay going
tobed/sleep.
Sorry guys (don't flame me) but I could not resist this one.
Werner

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=========================================================================
Date:         Wed, 22 Mar 2000 16:21:57 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Low Current Density Smut
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

We saw this recently and traced it back to a nylon smear from the
deburring brushes that were not dressed properly. Hope this helps.
Rick Howieson
GTC

>-----Original Message-----
>From:  Julie Dixon [SMTP:[log in to unmask]]
>Sent:  Wednesday, March 22, 2000 12:38 PM
>To:    [log in to unmask]
>Subject:       [TN] Low Current Density Smut
>
>Dear Net,
>
>1. Is there a name, we use smut, for the slimy, dark brown-black deposit in
>low
>current density areas on panels in acid copper plating? It wipes off as a goo
>down
>to the foil copper.
>2. Is it related to DML boards only? Palladium on surface issue?
>Or is it related to DML's reaction with the brightner system in the plating
>bath?
>I've been told it's brightner related, but it never occurs on anything not
>DML'd.
>
> -Cold panels 70 F almost always manifest it.
> - But recently we saw it on 74 F panels plated at 35 asf for the first 5
>minutes.
>   a. bath had been inactive for 5 days, but continuously filtered, and air
>agitation
>       had been on for 2 hours prior to plate. Anode film?
>   b. design was a horrendous mismatch of copper area. We panelized best we
>could
>        front side-   1-9"         9-18"     the front 1-9" area smutted.
>Other area were ok.
>                         10x            1x
>                         copper area
>        back side-   1-9"         9-18"
>                           1x           10x
>
>Any experience with this? We thought we'd shelved this prob. with 98 F rinses
>in the
>pre plate. Sulfuric dip and plating bath are at the mercy of ambient
>conditions, typic
>74 F.
>
>Thanks,
>Julie
>
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=========================================================================
Date:         Wed, 22 Mar 2000 19:10:46 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: Gold Removal Clarification
X-To:         "Misner, Bruce" <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi TechNet Land - Sorry for a tardy response but its been a bit tough catching
up on the email traffic after attending APEX. The responses on the "is 30
microinches of gold going to embrittle the solder joint?" question have been 100
percent right AND wrong! A 30 microinch thickness of gold will not embrittle the
solder joints provided: a) the solder process has enough solder volume to allow
the overall solderjoint gold percentage to stay below 3%; b) the soldering
process used is hot enough for a long enough duration to allow (a) to take
place. I have seen gold embrittlement issues when the gold thickness was 20
microinches - but the solder process was pretty poor. The interaction of the
gold finish and the soldering process is the key to avoiding embrittled
solderjoints.

Dave Hillman
Rockwell Collins
[log in to unmask]





"Misner, Bruce" <[log in to unmask]> on 03/16/2000 07:11:09 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      "Misner, Bruce" <[log in to unmask]>

To:   [log in to unmask]
cc:

Subject:  Re: [TN] ??: [TN] Gold Removal



Enough. 30u Inches of Au IS NOT enough to embrittle solder joints. I've done
it on space flight hardware for years in the 1980's and have performed every
test, environmental screen and evaluation imaginable with no detriment and
have satisfied NASA and the Air Force.  Satisfy your QA with an MRB, accept
the boards, send a SCAR to the vendor, save your schedule and save your
headache for something real. Next Topic.

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=========================================================================
Date:         Thu, 23 Mar 2000 14:40:57 +1100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Voids in BGA Balls after reflow
X-To:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

What a relief : todlers in US of A do not have to wrap up themselves in
kevlar49 composite blankets to dodge bullets from nearby kindergartens as i
mistakenly assumed reading of "security" blankets .
Thanks Werner, you've had me worried for a moment.

Inge, is all correspondence on this polymer versus paste going private = did
you get any response at all ?
Left it one day as to obstain from perceptions of being one of oldies (not
enough for granies):
not a wisper on the subject !

Risk indeed , you know this silver polymer versus solder paste is too hard
to resist .
I'd say yo' are much more unique than 5%, i'd be pretty certain no more than
1% uses conductive polymers for joints.
Less than 15-17 answers would validate my theory .
Some 5 years back when i started auto dispensing i was going to go full way
;
that is dispense and glue all , but all of the trial runs on strenght and
life dismuly failed :
>comparing to solder< . Did few more couple years later , than gave up .
Even when we runned ipc-sm-275 cycling for some 7 months on solder,
most of the failures/false alarms/problems were the silver epoxy event
detector attachments dropping off,
drove me around the bend ,
solved eventually by skipping the original reco of silver gluing AFTER the
assembly;
and did a thin tinned wire wrap with a couple of turns around the worst
offenders going through reflow at the same time,
with some 1" tail for event detector attachment after without thermal impair
to joint.

Did go through them all (polymers), still have a file foot thick : nothing
compared to solder,
with few caps cracking i could justify it in some instances , not as an
overall process .
A relatively few negatives with solder tensions on caps as I remember
Werner's quoting few european studies :
can be addressed by different pad geometries , height of fillets, etc. in a
quite practical ways,
so from civil perspective here it's thumbs up to solders of any kind .

Been actually often thinking ; why Inge ploughs through this hard way ;
but than; noo, he knows, must know what he does .
Did you notice i never actually asked WHY ?, despite being extremely curious
?
Now, since yo opened the topic (notice i did NOT change the mail heading);
lets discuss this under cover of voids :

With this leadfree market manipulations ;
what practical applications would you (say on gold metalisation) see as
comparable to solders ?
That is, would we see a step up from leaded alloys to conductive polymers ?
And in short term , considering your long battle with flakes,
what's the application (thermal sensitive?)you have on hands?
Did you address the resistivity changes ?

-----Original Message-----
From: Ingemar Hernefjord (EMW)
[mailto:[log in to unmask]]
Sent: Tuesday, 21 March 2000 19:34
To: [log in to unmask]
Subject: Re: [TN] Voids in BGA Balls after reflow


Yes, Bob,
well recognized. We were stunned by solder balls looking like rotten teeth
after the soldering/cleaning process. Typical was that all the "caries"
holes were on one and the same side of all balls. Explanation: a)the balls
consisted of two zones with different grain phases, caused by the BGA
maker's production method. b)we used a flux cleaner that dissolved poor
grain bindings in this two-zone interface and the result looked like what
happens when a mouse takes a bite in the cheese. Well, there is a whole
report about it and MOTA changed the ball concept, since then I have heard
of no more such problems. If you want some pictures for comparison, I can
send to you, Bob.

It's strange that we still get some soldering problems after decades of
knowledge about the processes. One reason may be this: old 'goodies'
disappear, newcomers more interested in IT and stockholding affairs. I knew
such an ol' goodie at a company, a metalurgical dr from Germany, he WAS
soldering personified (devotion and deepest interest), but when he retired
noone took over, the lab personel was spread and the new bosses spent no
more money. Many new in the game just scrap the surface of the mystery of
soldering. Luckily, we have TWI, IM and other institutions nearby, in US
there is China Lake, Sandia, Rome, IBM and....and Klein Wassink's soldering
bible...oceans of knowhow for those who like digging after treasures.

I take the opportunity to ask about silver adhesive vs. soldering. Just
wonder how many percents of the worlds component mounting is done with
adhesives instead of solders. The adhesive makers claim that their products
fit well for most applications, but many, many hesitate to change from
solder to 'glue'. I don't ask for a storm of pros and againsts...not at all,
just a qualified guessing from someone: how many percents? What do you
think? 5%?

There is a risk that some oldies will talk, how do we stop them? (He-he)

Ingemar Hernefjord
Ericsson Microwave Systems

-----Original Message-----
From: Bob Perkins [mailto:[log in to unmask]]
Sent: den 20 mars 2000 22:01
To: [log in to unmask]
Subject: [TN] Voids in BGA Balls after reflow


Hello Technetters

        Recently with the help of a high end piece of x-ray equipment we
have noticed voids in the spheres of the bga after reflow, "see
attachment-file".  Has anyone seen this before, or has any idea how the
voids are created?  Also does anyone know if this is a bad or good thing?
Does anyone have any recommendations to the profile?


Thanks
        Bob Perkins
        Automation Technician/Manufacturing Engineer
        Aimtronics
        [log in to unmask]


 <<wboard6.jpg>>

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=========================================================================
Date:         Wed, 22 Mar 2000 20:55:46 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Kenneth Stephens <[log in to unmask]>
Subject:      Re: Question: Film to Gerber - how?
X-To:         Anne Ledger <[log in to unmask]>
In-Reply-To:  <E3F39BDE675ED31192CE00508B2C8CAB05DA31@POSTMASTER2>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Gerber data can be "converted" to GenCAD data by using GraphicCode's GCPlace
software.  Some of us do this as a service for hire.  You may choose to
procure the software.  Check www.graphicode.com for more information on the
software.

   \----------------------\
    \  Kenneth G. Stephens \
     \ President            \
CAD--->CAD 2 CAM, Inc.       >---CAM
     / www.cad2cam.com      /
    /  503-246-4692        /
   /----------------------/

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Anne Ledger
> Sent: Tuesday, March 21, 2000 5:14 AM
> To: [log in to unmask]
> Subject: Re: [TN] Question: Film to Gerber - how?
>
>
> Jens,
>
> You need to find a scanning service.  We use one in California
> that does a great job.  They scan our customer's film and give us back
> gerber and a drill file.  We can then have the CAM engineers
> do some "clean up" on it (comparing to the film copies) and send
> out plots for approval.  Once the customer has approved, it can be
> released to fabrication.  The only negative is that the gerber data is
> unintelligent and as far as I know, can not be reloaded into a CAD
> software program.
>
> Hope that helps.
>
> Anne Ledger
> EMDS, Inc.
> [log in to unmask]
>
> > -----Original Message-----
> > From: [log in to unmask] [SMTP:[log in to unmask]]
> > Sent: Tuesday, March 21, 2000 2:56 AM
> > To:   [log in to unmask]
> > Subject:      [TN] Question: Film to Gerber - how?
> >
> > Hi Ya'll,
> >
> > I got again this old problem. I have the films, but need the
> > Gerberdata. Is
> > there a way to do it without making a complete new design?
> >
> > Regards
> >
> > Jens Behrens
> >
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=========================================================================
Date:         Thu, 23 Mar 2000 06:21:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Steffen, Don E" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Steffen, Don E" <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         "Oberle, Wade" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Wade

I am a Senior Quality Engineer at VDO Control Systems in Auburn, IN. We
started into the process of switching over to a No Clean Process. We have
enforced the SIR testing to be done by our suppliers. We use the Omega Meter
as a measurable for the incoming bare boards and also to measure the
assemblies again prior to any coatings or pottings.

I hope this has helped you

Donn Steffen
(219)925-8887
dsteffen@vdo-com

-----Original Message-----
From: Oberle, Wade [mailto:[log in to unmask]]
Sent: Wednesday, March 22, 2000 4:13 PM
To: [log in to unmask]
Subject: [TN] process control of final cleanliness in a no-clean world


Dear technetters,
        How do all of you in the no-clean world monitor and control board
cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
monitor our 'cleaning' process.  Do some of you still use an ionic
contamination tester or do you use SIR testing or nothing or what?

Thanks in advance for your advice.

Wade Oberle


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Date:         Thu, 23 Mar 2000 07:39:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Ed Holton <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         "Steffen, Don E" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Don, please tell us more.  Several years ago, (at a former company) I was
involved in the switch to no-clean flux.  We wanted our board vendors to
guarantee an incoming cleanliness level and met with varying successes.
Some flat out disagreed and argued that they could not, others complied,
and others supplied data that varied.  Sometimes, they would send a cert.
with the cleanliness and when we would check, it would not match.  They all
wanted to know what cleanliness level was acceptable.  We set a
specification number, and asked them to meet them.  Unfortunately, since we
used the boards so fast (10K+ per day), if we had a shipment that fell
outside the cleanliness level, we often were forced to used the boards or
else we would shut our automotive customers down due to lack of boards.

We did a lot of testing to determine minimal cleanliness levels, but this
level would vary based on application, and we were not about to set a level
for each board, etc.

So, just curious, what level have you set for incoming inspection, and how
well are your suppliers meeting and working with this spec.  I am hoping
that much has changed in this area in the past few years, and when I am
forced to resolve this problem in the future it will be much easier.

Ed Holton
Manufacturing Engineer and Group Leader
Hella Electronics
Telephone (734) 414-0944
Fax (734) 414-0941



                    "Steffen, Don
                    E"                   To:     [log in to unmask]
                    <dsteffen@VDO        cc:
                    .COM>                Subject:     Re: [TN] process control of
                    Sent by:             final cleanliness in a no-clean world
                    TechNet
                    <[log in to unmask]
                    ORG>


                    03/23/00
                    06:21 AM
                    Please
                    respond to
                    "TechNet
                    E-Mail
                    Forum.";
                    Please
                    respond to
                    "Steffen, Don
                    E"





Wade

I am a Senior Quality Engineer at VDO Control Systems in Auburn, IN. We
started into the process of switching over to a No Clean Process. We have
enforced the SIR testing to be done by our suppliers. We use the Omega
Meter
as a measurable for the incoming bare boards and also to measure the
assemblies again prior to any coatings or pottings.

I hope this has helped you

Donn Steffen
(219)925-8887
dsteffen@vdo-com

-----Original Message-----
From: Oberle, Wade [mailto:[log in to unmask]]
Sent: Wednesday, March 22, 2000 4:13 PM
To: [log in to unmask]
Subject: [TN] process control of final cleanliness in a no-clean world


Dear technetters,
        How do all of you in the no-clean world monitor and control board
cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
monitor our 'cleaning' process.  Do some of you still use an ionic
contamination tester or do you use SIR testing or nothing or what?

Thanks in advance for your advice.

Wade Oberle


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=========================================================================
Date:         Thu, 23 Mar 2000 21:09:38 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Nick Liang>" <[log in to unmask]>
Subject:      Selenium?
MIME-Version: 1.0
Content-Type: text/plain; charset="big5"

All:
Any Selenium exist in PCB process?
(Se)
Later,
-----------------------------------------------
Nick Liang
Customer Service Supervisor
Quality Assurance Division
Gold Circuit Electronics Ltd.
Tel : (886) 03-4612541 Ext 3402
Fax: (886) 03-4522094
Cell: (886) 0939-102150
E-Mail : [log in to unmask]
------------------------------------------------

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Date:         Thu, 23 Mar 2000 08:46:21 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hollandsworth, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hollandsworth, Ron" <[log in to unmask]>
Subject:      Re: No-Clean Question
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Wade:
Do a SIR test on your flux/paste whatever you are using.  If you have
surface mount and wavesolder operation, then run a SIR for SMT paste, a SIR
for wavesolder, and if you have mixed technology you should do a SIR using
all elements of your process.

Some customers want cleaning no matter what kind of flux you are using do to
the nature of the product (we have this situation).  You can use an omega
meter.  If you passed SIR testing, process some test boards the same way and
check them using your omegameter.  Clean the boards and check them in the
omegameter.  This will give you a baseline of what kind of cleanliness to
expect.  We have product that does not require cleaning and product that
does require cleaning even though we are using a No-clean and Low-residue
technology.  We also eliminated two large inline cleaners and a host of
other items like fire suppression at wave, flux thinner, etc., by going to a
No-clean/Low-residue soldering solution.  We still have a cleaner and still
use it a lot.  We do have an omegameter at the end of the cleaner and we use
it as well.

Sir test to qualify the flux and SIR test to qualify your process.  I
believe it's IPC-650 has the information for SIR testing.  Personally, I
called Robisan Labs and ask questions to Susan Mansilla before wasting a lot
of dummy parts, boards, my time, money, and Robisan's time.  You can also
call Contamination Studies Labs and talk to one of the Ionic Blues Brothers
(Doug Pauls I believe is into SIR testing).  CSL's Terry Munson provided us
with a lot of up front info on No-clean/Low-residue before we started.
Another great resource is Dave Hillman, at Rockwell Collins.

Ron Hollandsworth
Ops Task Leader AME Group
ITT A/CD

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Date:         Thu, 23 Mar 2000 08:50:00 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Rich Edgar <[log in to unmask]>
Subject:      Re: Selenium?
X-To:         [log in to unmask]
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There may be.  Some electroless coppers could have Selenium in their
formulations in  PPM concentrations.  Rare, but maybe.

Rich Edgar
Florida CirTech Inc.

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Date:         Thu, 23 Mar 2000 08:54:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Anne Ledger <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Anne Ledger <[log in to unmask]>
Subject:      Referral for GIL Boards.
MIME-Version: 1.0
Content-Type: text/plain

Good Morning Technet,

We are looking for a fabrication house that is doing GIL 1000 or 1100
material.  We aren't but have a customer that needs some and we'd like
to
get a couple of names to refer them to.

All inputs will be passed to the customer, either from the Technet or
contact me direct, [log in to unmask]

Thanks,
Anne Ledger
EMDS, Inc.

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Date:         Thu, 23 Mar 2000 10:04:57 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Drill bit control
MIME-Version: 1.0
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Just curious,

How many board shops are still using color coding to control the number of
re-sharps?  Currently, we primarily use flute length to control our
re-sharps. However, we think we are finding a significant difference of how
many re-sharps different re-sharp houses can get when a shop only specifies
flute length. We have learned that depending on the re-sharp house and
specific operators, the amount of flute removed when re-sharpening can vary
from as low as .0015 mils up to .007 mils. This would suggest that the
number of hits a drill sees before it is discarded for flute length can vary
by as much as 3-5,000.

The reason for this posting is due to a recently seen increase in drill
debris. Especially on .0135 holes. We are thinking that there may be a
significant difference in the evacuation properties of a bit that has been
re-sharpened 4 times ( or 6,000 hits ) verses a bit that has been
re-sharpened 6 times ( or 9'000 hits ).

Any thoughts on this matter?

Ed Cosper
ABC

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Date:         Thu, 23 Mar 2000 07:42:32 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Regis Froats <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Regis Froats <[log in to unmask]>
Subject:      Re: Drill bit control
X-To:         Ed Cosper <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

When repointing via overall length, you need to do a wear analysis on the
tool after use to determine the minimum amount of stock removal needed to
repoint the tool to insure a good point.  Depending on your product mix and
drill parameters (feed/speed, hit count, stack height, etc.), your minimum
removal could be as little as .002 or as much as .007.  Margin wear is the
critical factor for hole wall quality.  Work with your supplier to help you
determine your minimum stock removal, which will vary upon diameter ranges.

At 10:04 03/23/2000 -0500, you wrote:
>Just curious,
>
>How many board shops are still using color coding to control the number of
>re-sharps?  Currently, we primarily use flute length to control our
>re-sharps. However, we think we are finding a significant difference of how
>many re-sharps different re-sharp houses can get when a shop only specifies
>flute length. We have learned that depending on the re-sharp house and
>specific operators, the amount of flute removed when re-sharpening can vary
>from as low as .0015 mils up to .007 mils. This would suggest that the
>number of hits a drill sees before it is discarded for flute length can vary
>by as much as 3-5,000.
>
>The reason for this posting is due to a recently seen increase in drill
>debris. Especially on .0135 holes. We are thinking that there may be a
>significant difference in the evacuation properties of a bit that has been
>re-sharpened 4 times ( or 6,000 hits ) verses a bit that has been
>re-sharpened 6 times ( or 9'000 hits ).
>
>Any thoughts on this matter?
>
>Ed Cosper
>ABC
>
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>

--
Regis Froats <[log in to unmask]>
Process Engineer - Herco Technology Corp.
13330 Evening Creek Drive North
San Diego, Ca. 92128
Pho:858.679.2800 - Fax:858.679.7565

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Date:         Thu, 23 Mar 2000 11:15:08 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Re: Drill bit control
X-To:         Regis Froats <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Regis,

Thanks for the response. We have done extensive wear analysis, which was the
original base of deciding to move away from color coding. However, our wear
analysis only focused on the point and cutting edge. I am now wondering what
effect extended hits has on the flute itself with respect to how it channels
debris up the length of the flute and expels it out of the top of the hole.
I can visualize how the more hits on a drill could possible effect the flute
channel due to effects of normal  run out and deflection variations. I

Ed Cosper

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Regis Froats
Sent: Thursday, March 23, 2000 10:43 AM
To: [log in to unmask]
Subject: Re: [TN] Drill bit control

When repointing via overall length, you need to do a wear analysis on the
tool after use to determine the minimum amount of stock removal needed to
repoint the tool to insure a good point.  Depending on your product mix and
drill parameters (feed/speed, hit count, stack height, etc.), your minimum
removal could be as little as .002 or as much as .007.  Margin wear is the
critical factor for hole wall quality.  Work with your supplier to help you
determine your minimum stock removal, which will vary upon diameter ranges.

At 10:04 03/23/2000 -0500, you wrote:
>Just curious,
>
>How many board shops are still using color coding to control the number of
>re-sharps?  Currently, we primarily use flute length to control our
>re-sharps. However, we think we are finding a significant difference of how
>many re-sharps different re-sharp houses can get when a shop only specifies
>flute length. We have learned that depending on the re-sharp house and
>specific operators, the amount of flute removed when re-sharpening can vary
>from as low as .0015 mils up to .007 mils. This would suggest that the
>number of hits a drill sees before it is discarded for flute length can
vary
>by as much as 3-5,000.
>
>The reason for this posting is due to a recently seen increase in drill
>debris. Especially on .0135 holes. We are thinking that there may be a
>significant difference in the evacuation properties of a bit that has been
>re-sharpened 4 times ( or 6,000 hits ) verses a bit that has been
>re-sharpened 6 times ( or 9'000 hits ).
>
>Any thoughts on this matter?
>
>Ed Cosper
>ABC
>
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>information.
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--
Regis Froats <[log in to unmask]>
Process Engineer - Herco Technology Corp.
13330 Evening Creek Drive North
San Diego, Ca. 92128
Pho:858.679.2800 - Fax:858.679.7565

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Date:         Thu, 23 Mar 2000 09:25:22 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dewey Whittaker <[log in to unmask]>
Organization: Honeywell Inc.
Subject:      Re: Drill bit control
X-To:         Ed Cosper <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="------------F37D95FDCE2DE38C59BA4275"

--------------F37D95FDCE2DE38C59BA4275
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Content-Transfer-Encoding: 7bit

Is the question how many resharps could a resharp resharp if a resharp could resharp resharps?All humor aside,when we were fabricating our own PWB's
we monitored the number of hits per drill on the .016 and .0135 holes.We had different numbers based on the materials.The last holes drilled were
always in the coupon.Evaluation of the microsection validated those controls.DOE's should be conducted to determine the number of hits and resharps
each different construction can tolerate.Adequate PCP's should be in place then to keep you from throwing away good drills or drilling bad holes.
Dewey



Ed Cosper wrote:

> Just curious,
>
> How many board shops are still using color coding to control the number of
> re-sharps?  Currently, we primarily use flute length to control our
> re-sharps. However, we think we are finding a significant difference of how
> many re-sharps different re-sharp houses can get when a shop only specifies
> flute length. We have learned that depending on the re-sharp house and
> specific operators, the amount of flute removed when re-sharpening can vary
> from as low as .0015 mils up to .007 mils. This would suggest that the
> number of hits a drill sees before it is discarded for flute length can vary
> by as much as 3-5,000.
>
> The reason for this posting is due to a recently seen increase in drill
> debris. Especially on .0135 holes. We are thinking that there may be a
> significant difference in the evacuation properties of a bit that has been
> re-sharpened 4 times ( or 6,000 hits ) verses a bit that has been
> re-sharpened 6 times ( or 9'000 hits ).
>
> Any thoughts on this matter?
>
> Ed Cosper
> ABC
>
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> information.
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> 847-509-9700 ext.5315
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--
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]



--------------F37D95FDCE2DE38C59BA4275
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Is the question how many resharps could a resharp resharp if a resharp
could resharp resharps?All humor aside,when we were fabricating our own
PWB's we monitored the number of hits per drill on the .016 and .0135 holes.We
had different numbers based on the materials.The last holes drilled were
always in the coupon.Evaluation of the microsection validated those controls.DOE's
should be conducted to determine the number of hits and resharps each different
construction can tolerate.Adequate PCP's should be in place then to keep
you from throwing away good drills or drilling bad holes.
<br>Dewey
<br>&nbsp;
<br>&nbsp;
<p>Ed Cosper wrote:
<blockquote TYPE=CITE>Just curious,
<p>How many board shops are still using color coding to control the number
of
<br>re-sharps?&nbsp; Currently, we primarily use flute length to control
our
<br>re-sharps. However, we think we are finding a significant difference
of how
<br>many re-sharps different re-sharp houses can get when a shop only specifies
<br>flute length. We have learned that depending on the re-sharp house
and
<br>specific operators, the amount of flute removed when re-sharpening
can vary
<br>from as low as .0015 mils up to .007 mils. This would suggest that
the
<br>number of hits a drill sees before it is discarded for flute length
can vary
<br>by as much as 3-5,000.
<p>The reason for this posting is due to a recently seen increase in drill
<br>debris. Especially on .0135 holes. We are thinking that there may be
a
<br>significant difference in the evacuation properties of a bit that has
been
<br>re-sharpened 4 times ( or 6,000 hits ) verses a bit that has been
<br>re-sharpened 6 times ( or 9'000 hits ).
<p>Any thoughts on this matter?
<p>Ed Cosper
<br>ABC
<p>##############################################################
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1.8c
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<pre>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</pre>
&nbsp;</html>

--------------F37D95FDCE2DE38C59BA4275--

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Date:         Thu, 23 Mar 2000 12:41:38 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Warped Boards...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi ya'll!

I've been wave soldering an assembly today and they've warped on me...not
coming off the wave, but as they cool down.

They come off the wave nice and flat, but curl up along all three edges
except for the one edge where there's a right angle connector along the
length of the edge and secured in with three screws. I'd bet if the connector
wasn't there, that edge would curl too. I use a titanium stiffener on the
back edge of the board when waving it, and tried to see if I left it on while
it was cooling might prevent the curling..but it still curls.
The board thickness by the way is .062" and about 10" X 12"

I've been told that when these boards were built in the past, and they're
pretty sure they didn't have this problem...

What could cause this? I know how the layers are stacked makes a difference.
But if I'm to believe that this problem wasn't there the last time the boards
were built, the layer stack-up shouldn't be an issue.

Could it be something the way the weave of fiber cloth in the different
layers are oriented to each other?

Trying to figure this out...

-Steve Gregory-

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Date:         Thu, 23 Mar 2000 13:34:02 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: Warped Boards...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Steve,

One factor can be ground planes or large areas of foil in or on the boards.
This is one of the reasons that many people now use a mesh style ground
plane... unless you are purposely trying to create a huge capacitor.

Are you running the same "recipe" as the last time the board was run?

And yes, it could be something to do with the construction of the FR4.

Regards,

Phil Nutting
Manufacturing Engineer
Kaiser Systems, Inc.

-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, March 23, 2000 12:42 PM
To: [log in to unmask]
Subject: [TN] Warped Boards...


Hi ya'll!

I've been wave soldering an assembly today and they've warped on me...not
coming off the wave, but as they cool down.

They come off the wave nice and flat, but curl up along all three edges
except for the one edge where there's a right angle connector along the
length of the edge and secured in with three screws. I'd bet if the
connector
wasn't there, that edge would curl too. I use a titanium stiffener on the
back edge of the board when waving it, and tried to see if I left it on
while
it was cooling might prevent the curling..but it still curls.
The board thickness by the way is .062" and about 10" X 12"

I've been told that when these boards were built in the past, and they're
pretty sure they didn't have this problem...

What could cause this? I know how the layers are stacked makes a difference.
But if I'm to believe that this problem wasn't there the last time the
boards
were built, the layer stack-up shouldn't be an issue.

Could it be something the way the weave of fiber cloth in the different
layers are oriented to each other?

Trying to figure this out...

-Steve Gregory-

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Date:         Thu, 23 Mar 2000 13:45:19 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Babyak <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Babyak <[log in to unmask]>
Subject:      Re: Warped Boards...
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=US-ASCII
Content-transfer-encoding: 7BIT

If the boards were built flat in the past, something changed when
manufacturing the board.  There's a good chance the board was
cross-plied (the grain in the cores is different from the grain in the
prepreg).  If you know the type of prepreg used (7628, 1080, etc.)
you can burn the board using a torch to expose the weave.  Once
you've burned the resin, you peel layers off until you get to the core
and prepreg.  You then count the bundles in one inch.  7628 for
example has 44 bundles in warp (grain) direction and 32 in the fill
direction.  If the core and prepreg contain 7628, the number of
bundles should be the same in the one direction.

There could also be problems in the process of manufacturing the
board.  If there are heaters out on one side of the press platens,
the rate of rise is different from one side versus the other.  This will
cause different stresses in the material.  There's also some theory
to stress relieve the core material before lay up by baking at 250F
for 30-60 minutes.  Did your supplier change this?  Also some
laminate suppliers stress relieve their material before shipment.
Sometimes they don't if they get busy.



Rick Babyak
Process Engineer
Proto Circuit Inc.
7 Ascot Parkway
Cuyahoga Falls, OH 44223
330-572-3401  Fax:330-572-3434
[log in to unmask]

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Date:         Thu, 23 Mar 2000 14:05:42 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mark R Ford <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mark R Ford <[log in to unmask]>
Subject:      Re: Drill bit control
X-To:         [log in to unmask]
MIME-Version: 1.0
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Ed,

If your concern is that an increased number of hits on a tool will impact
the tools ability to evacuate debris, your looking in the wrong
direction.  Only design characteristics can impact debris evacuation as
far as the tools are concerned (those design characteristics being flute
form, flute to land ratio, helix angle, and flute length).  You may want
to check the vacuum and be sure that it is pulling adequate in/H2O.
Also, make sure that you do not have too much vacuum as it can cause an
effect known as oil canning (the vacuum sucks the entry off the stack
while the pressure foot insert is in contact with the production stack).


There are other items that you can look at but I do not believe the
debris problem you have is do to too many resharps.  However, if you
suspect that your repoint supplier is "skim pointing" your drills, mark
some tools with a UV ink and measure overall length when the drill come
back (you'll need a black light to find your marked drills).  Some
repointers will skim point to speed up the repointing process ( an
average repointer can point 1000 tools in an eight hour shift when taking
five mils of stock...that same repointer can get 2000 points in an eight
hour shift when only removing 2 mils of stock).

You really need to work with your machine and tool supplier to solve this
problem if it persist.  If you would like more of my opinions contact me
off the Technet and I'll be happy to help.

Regards,

Mark R. Ford  -  Megatool

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Date:         Thu, 23 Mar 2000 14:31:37 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Robert Welch <[log in to unmask]>
Subject:      Re: Low Current Density Smut
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
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1. Smut is a good term.
2. In past life, have had to run DM real quick or micro-etch the p---sss out
of it. Watch your hold times.
3. Never let an acid copper bath set for over 24 hours without at least a
minimal low current dummy to start the bath up with.  I don't know about the
e voodoo anode film but you can watch this smut being created in the first
few seconds of a hull cell test and compare it to dummied Vs non-dummied and
correlate to current density all at the same time.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Julie Dixon
Sent: Wednesday, March 22, 2000 2:38 PM
To: [log in to unmask]
Subject: [TN] Low Current Density Smut


Dear Net,

1. Is there a name, we use smut, for the slimy, dark brown-black deposit in
low
current density areas on panels in acid copper plating? It wipes off as a
goo
down
to the foil copper.
2. Is it related to DML boards only? Palladium on surface issue?
Or is it related to DML's reaction with the brightner system in the plating
bath?
I've been told it's brightner related, but it never occurs on anything not
DML'd.

 -Cold panels 70 F almost always manifest it.
 - But recently we saw it on 74 F panels plated at 35 asf for the first 5
minutes.
   a. bath had been inactive for 5 days, but continuously filtered, and air
agitation
       had been on for 2 hours prior to plate. Anode film?
   b. design was a horrendous mismatch of copper area. We panelized best we
could
        front side-   1-9"         9-18"     the front 1-9" area smutted.
Other area were ok.
                         10x            1x
                         copper area
        back side-   1-9"         9-18"
                           1x           10x

Any experience with this? We thought we'd shelved this prob. with 98 F
rinses
in the
pre plate. Sulfuric dip and plating bath are at the mercy of ambient
conditions, typic
74 F.

Thanks,
Julie

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Date:         Thu, 23 Mar 2000 12:49:35 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "ROMERO, DAVID" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "ROMERO, DAVID" <[log in to unmask]>
Subject:      Ceramic Capacitor Strength Versus Size
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I have been battling SMT ceramic capacitor cracking problems for a while, as
I am sure most of you have.  I am experiencing cracking from mechanical and
most likely thermal stress as well.  I have addressed many of these issues
(depanelization, profile, etc...) using literature from MLC manufacturer's
technical information.  I am now looking for a general capacitor size vs.
strength data for various stresses.  I know that generally larger parts are
more likely to have problems but for each size of cap it is difficult to
compare.  I have looked at RAC data as well as IPC, and have not found
anything exactly like what I am looking for.

Does anyone know of a source of such information or the best place to start
compiling a list of my own?

Any suggestions would be appreciated.

Thanks

David Romero

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Date:         Thu, 23 Mar 2000 14:21:56 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Brad L. Matthies" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brad L. Matthies" <[log in to unmask]>
Organization: Raven Industries, Inc.
Subject:      3D Desktop Paste Inspection.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I am evaluating adding a desktop 3D paste inspection unit to our SMT
lines.  We are not large enough to start out with an inline unit.  I am
wondering what king of experience other have had with these systems and
if so which ones would you recommend and why?  We are evaluating Cyber
Optics, I-Systems and ASC International's units.  Any input would be
greatly appreciated.

Regards,
BLM

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Date:         Thu, 23 Mar 2000 15:26:49 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Ceramic Capacitor Strength Versus Size
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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In a message dated 03/23/2000 2:05:18 PM Central Standard Time,
[log in to unmask] writes:

<< I have been battling SMT ceramic capacitor cracking problems for a while,
as
 I am sure most of you have.  I am experiencing cracking from mechanical and
 most likely thermal stress as well.  I have addressed many of these issues
 (depanelization, profile, etc...) using literature from MLC manufacturer's
 technical information.  I am now looking for a general capacitor size vs.
 strength data for various stresses.  I know that generally larger parts are
 more likely to have problems but for each size of cap it is difficult to
 compare.  I have looked at RAC data as well as IPC, and have not found
 anything exactly like what I am looking for.

 Does anyone know of a source of such information or the best place to start
 compiling a list of my own?

 Any suggestions would be appreciated.

 Thanks

 David Romero >>

Hi David!

Have you been to the AVX website yet? They've got a couple of good *.PDF
articles that gives some good info about zero defect assembly with
multi-layer capacitors. The URL's are:

http://www.avxcorp.com/docs/techinfo/!smtinfo.pdf
http://www.avxcorp.com/docs/techinfo/smzero.pdf

-Steve Gregory-

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Date:         Thu, 23 Mar 2000 16:36:10 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Re: Warped Boards...
X-To:         [log in to unmask]
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
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Steve,

Try to run a few bare boards without components and see it they warp. If
they do then you have a board problem. Bare board warpage is typically a
result of unbalanced design or a bad lay up. If they do not warp,  then it
possible the component could be warping the board. Does the part have any
components that could act as heat sinks or are large with a lot of metal?

Just a thought.

Ed Cosper

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Stephen R. Gregory
Sent: Thursday, March 23, 2000 12:42 PM
To: [log in to unmask]
Subject: [TN] Warped Boards...

Hi ya'll!

I've been wave soldering an assembly today and they've warped on me...not
coming off the wave, but as they cool down.

They come off the wave nice and flat, but curl up along all three edges
except for the one edge where there's a right angle connector along the
length of the edge and secured in with three screws. I'd bet if the
connector
wasn't there, that edge would curl too. I use a titanium stiffener on the
back edge of the board when waving it, and tried to see if I left it on
while
it was cooling might prevent the curling..but it still curls.
The board thickness by the way is .062" and about 10" X 12"

I've been told that when these boards were built in the past, and they're
pretty sure they didn't have this problem...

What could cause this? I know how the layers are stacked makes a difference.
But if I'm to believe that this problem wasn't there the last time the
boards
were built, the layer stack-up shouldn't be an issue.

Could it be something the way the weave of fiber cloth in the different
layers are oriented to each other?

Trying to figure this out...

-Steve Gregory-

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Date:         Thu, 23 Mar 2000 16:41:08 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Selenium?
X-To:         [log in to unmask]
MIME-Version: 1.0
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mmmm......think there r some laminate manufacturers that use selenium in
there manufacturing process. found a compnay that whenever they analyze their
solder in the HASL - it keeps rising slightly by ppm's every other month or
so.


regards

Rich Fudalewski

FCT

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Date:         Thu, 23 Mar 2000 17:06:36 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "May William D (Dean) CNIN" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "May William D (Dean) CNIN" <[log in to unmask]>
Subject:      Measuring plated thru hole copper
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We are looking to buy a hand held unit to measure plated thru hole copper
thickness.  I know CMI makes one but it can only measure a minimum hole size
of 35 mils.  Are there any other vendors out there that make hand held
units.

Would appreciate any information.

Thanks!

Wm. Dean May
NSWC Crane
Bldg. 38, Code 8086
300 Highway 361
Crane, IN 47522
812-854-3073

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Date:         Thu, 23 Mar 2000 16:21:37 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
X-To:         "May William D (Dean) CNIN" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Are you looking for a device to measure thickness on individual holes? O
overall through hole plating. The CMI device is very accurate at measuring
hole wall copper thickness.

Yes, it has hole size limitaitons but it's not the actual hole you are
measuring, right? You might consider adding a few probe holes around the
panel, the CMI unit works great in that way.

Franklin


----- Original Message -----
From: May William D (Dean) CNIN <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 23, 2000 2:06 PM
Subject: [TN] Measuring plated thru hole copper


> We are looking to buy a hand held unit to measure plated thru hole copper
> thickness.  I know CMI makes one but it can only measure a minimum hole
size
> of 35 mils.  Are there any other vendors out there that make hand held
> units.
>
> Would appreciate any information.
>
> Thanks!
>
> Wm. Dean May
> NSWC Crane
> Bldg. 38, Code 8086
> 300 Highway 361
> Crane, IN 47522
> 812-854-3073
>
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Date:         Thu, 23 Mar 2000 21:39:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Eric Yakobson <[log in to unmask]>
Subject:      Re: Low Current Density Smut
X-To:         Julie Dixon <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi Julie,

The formation of smut is dependent on both factors -- the presence of palladium
on the copper surface and the presence of certain organic additives in your
plating bath.  If Pd activation is not used or the plating solution is
additive-free or if palladium layer is covered with a dense and thick
electroless copper deposit -- it won't form .  As far as I know the presence of
anode film is not a factor.  My guess is that this smut consists of cuprous and
cupric oxide mixture.  During electrodeposition cupric ion goes through a
cuprous state and under certain conditions may not reduce all the way to the
metallic state.  Some organic additives in your plating bath and chloride ion
may stabilize cuprous by complexing it.  Although the exact smut formation
mechanism is not entirely understood, there are some things you can do to reduce
it.  Please contact me offline if interested.

Eric Yakobson





Julie Dixon <[log in to unmask]> on 03/22/2000 11:38:29 AM

To:   [log in to unmask]
cc:
Subject:  [TN] Low Current Density Smut



Dear Net,

1. Is there a name, we use smut, for the slimy, dark brown-black deposit in
low
current density areas on panels in acid copper plating? It wipes off as a goo
down
to the foil copper.
2. Is it related to DML boards only? Palladium on surface issue?
Or is it related to DML's reaction with the brightner system in the plating
bath?
I've been told it's brightner related, but it never occurs on anything not
DML'd.

 -Cold panels 70 F almost always manifest it.
 - But recently we saw it on 74 F panels plated at 35 asf for the first 5
minutes.
   a. bath had been inactive for 5 days, but continuously filtered, and air
agitation
       had been on for 2 hours prior to plate. Anode film?
   b. design was a horrendous mismatch of copper area. We panelized best we
could
        front side-   1-9"         9-18"     the front 1-9" area smutted.
Other area were ok.
                         10x            1x
                         copper area
        back side-   1-9"         9-18"
                           1x           10x

Any experience with this? We thought we'd shelved this prob. with 98 F rinses
in the
pre plate. Sulfuric dip and plating bath are at the mercy of ambient
conditions, typic
74 F.

Thanks,
Julie

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Date:         Thu, 23 Mar 2000 22:09:56 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: Low Current Density Smut
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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low current density smut - number 1 - a 74F bath is in pretty good shape. why
wud 98F water have anything to do with the formation of smut?

2- just out of curiosity (wud need to see the panel) - how is the current
density on that/the panel/panels were the smut was formed? u said 35 asf -
but what did that actual rack get?

Rick Fudalewski

FCT

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Date:         Fri, 24 Mar 2000 08:32:05 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: Ceramic Capacitor Strength Versus Size
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Real good pages, Steve, to be an oldie, you are very alert. David, I know a guy who has been simulating and calculating soldering of caps and like for years. Maybe, he is not willing to tell everything, but you can at least try. I send his adress offline, he has little time to act as a world oracle. Anyway, we have cooperation with Kemet, AVX, Kyocera, Murata etc, and we have learnt that the geometry of the solder joint is of crucial importance. We have extremly large boards in some applications, with metal back and Teflon. Mounting ceramic caps on such boards is seemingly crazy, but works well since many years. Another guy you can contact if you want deeper knowhow about the stress mechanisms is prof. Akay in Indiana. He has a whole group busy with your things. <[log in to unmask]>.
Good Luck
Ingemar Hernefjord

-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: den 23 mars 2000 21:27
To: [log in to unmask]
Subject: Re: [TN] Ceramic Capacitor Strength Versus Size


In a message dated 03/23/2000 2:05:18 PM Central Standard Time,
[log in to unmask] writes:

<< I have been battling SMT ceramic capacitor cracking problems for a while,
as
 I am sure most of you have.  I am experiencing cracking from mechanical and
 most likely thermal stress as well.  I have addressed many of these issues
 (depanelization, profile, etc...) using literature from MLC manufacturer's
 technical information.  I am now looking for a general capacitor size vs.
 strength data for various stresses.  I know that generally larger parts are
 more likely to have problems but for each size of cap it is difficult to
 compare.  I have looked at RAC data as well as IPC, and have not found
 anything exactly like what I am looking for.

 Does anyone know of a source of such information or the best place to start
 compiling a list of my own?

 Any suggestions would be appreciated.

 Thanks

 David Romero >>

Hi David!

Have you been to the AVX website yet? They've got a couple of good *.PDF
articles that gives some good info about zero defect assembly with
multi-layer capacitors. The URL's are:

http://www.avxcorp.com/docs/techinfo/!smtinfo.pdf
http://www.avxcorp.com/docs/techinfo/smzero.pdf

-Steve Gregory-

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Date:         Mon, 20 Mar 2000 11:24:40 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Grant Emandien <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Grant Emandien <[log in to unmask]>
Subject:      Coating of assemblies with no clean fluxes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi all,

The debate on cleaning of fluxes as well as the use no-clean fluxes seems to
hang around forever. We have been informed by our solder an flux supplier
that assemblies with no clean fluxes can be conformally coated without the
need to clean the boards.

The argument is that the high temperatures of the reflow oven 'burns off'
the active ingredients, leaving only inactive residues. These flux residues
do not have to be cleaned and can supposedly be coated. The rep. believes we
are taking a backward step by possibly opting to use water-based flux. Is
this pure sales talk?

Is anyone able to offer any advice or insight, or been able to assess the
environmental and electrical performance of such assemblies.

Regards
Grant

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Date:         Fri, 24 Mar 2000 07:16:48 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
MIME-Version: 1.0
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Don't know how to tell you this Franklin, put copper plating in small
diameter holes (below 0.014") is not the same as in larger holes. In small
holes, you may get much thicker plating at the surface and near the knee of
the hole then what you get near the centre of the hole. Back when we had our
in-house plating shop, way back in '97, I had looked into getting such a
device and found it unreliable at best. It gives a good approximation, but
it measures an overall average, not the thinnest points. But technologies
may have changed since I looked into this.

My 2 cents worth,

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Franklin Asbell
Subject: Re: [TN] Measuring plated thru hole copper

Are you looking for a device to measure thickness on individual holes? O
overall through hole plating. The CMI device is very accurate at measuring
hole wall copper thickness.

Yes, it has hole size limitaitons but it's not the actual hole you are
measuring, right? You might consider adding a few probe holes around the
panel, the CMI unit works great in that way.

Franklin

----- Original Message -----
From: May William D (Dean) CNIN
Subject: [TN] Measuring plated thru hole copper

> We are looking to buy a hand held unit to measure plated thru hole copper
> thickness.  I know CMI makes one but it can only measure a minimum hole
size
> of 35 mils.  Are there any other vendors out there that make hand held
> units.
>
> Would appreciate any information.
>
> Thanks!
>
> Wm. Dean May
> NSWC Crane
> Bldg. 38, Code 8086
> 300 Highway 361
> Crane, IN 47522
> 812-854-3073

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Date:         Fri, 24 Mar 2000 07:19:56 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Oops hit the reply button too fast.

Pulse plating may greatly help to reduce plated copper difference in
thickness for different hole sizes. But you have to get use to that
technology.

Have a great day,

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]


-----Original Message-----
From: Alain Savard
Sent: March 24, 2000 7:17 AM
To: 'TechNet E-Mail Forum.'
Subject: RE: [TN] Measuring plated thru hole copper


Don't know how to tell you this Franklin, put copper plating in small
diameter holes (below 0.014") is not the same as in larger holes. In small
holes, you may get much thicker plating at the surface and near the knee of
the hole then what you get near the centre of the hole. Back when we had our
in-house plating shop, way back in '97, I had looked into getting such a
device and found it unreliable at best. It gives a good approximation, but
it measures an overall average, not the thinnest points. But technologies
may have changed since I looked into this.

My 2 cents worth,

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Franklin Asbell
Subject: Re: [TN] Measuring plated thru hole copper

Are you looking for a device to measure thickness on individual holes? O
overall through hole plating. The CMI device is very accurate at measuring
hole wall copper thickness.

Yes, it has hole size limitaitons but it's not the actual hole you are
measuring, right? You might consider adding a few probe holes around the
panel, the CMI unit works great in that way.

Franklin

----- Original Message -----
From: May William D (Dean) CNIN
Subject: [TN] Measuring plated thru hole copper

> We are looking to buy a hand held unit to measure plated thru hole copper
> thickness.  I know CMI makes one but it can only measure a minimum hole
size
> of 35 mils.  Are there any other vendors out there that make hand held
> units.
>
> Would appreciate any information.
>
> Thanks!
>
> Wm. Dean May
> NSWC Crane
> Bldg. 38, Code 8086
> 300 Highway 361
> Crane, IN 47522
> 812-854-3073

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Date:         Fri, 24 Mar 2000 07:52:54 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Douglas Pauls <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         [log in to unmask]
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

In a message dated 03/22/2000 4:11:05 PM US Eastern Standard Time,
[log in to unmask] writes:

>         How do all of you in the no-clean world monitor and control board
>  cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
>  monitor our 'cleaning' process.  Do some of you still use an ionic
>  contamination tester or do you use SIR testing or nothing or what?

Wade,
How did you do process control before you went no-clean?  You can still use
an Omegameter or Ionograph (or other such instrument) as PROCESS CONTROL, but
you have to throw out everything you know about "good" adn "bad" numbers.
Those instruments work for process control, but not for accept-reject.   The
result that you get will probably be higher, because the weak organic acid
activators come off of the board and make the isoproapnol-water solution
conductive.  The materials are benign on a board surface.  You should do some
correlation studies between accelerated electrical testing, such as burn-in
or life tests, and Omegameter readings.  Determine what maximum reading
correlates to failures in such accelerated testing.  Then use that as your
maximum control limit.

Doug Pauls
CSL

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Date:         Fri, 24 Mar 2000 05:31:25 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              peter blokhuis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         peter blokhuis <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
X-To:         "May William D (Dean) CNIN" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Fischer Technology makes one, but the minimum
measurable size is not substantially smaller than 35
mils.  One of their reps numbers is 716-631-8103.

--- "May William D (Dean) CNIN"
<[log in to unmask]> wrote:
> We are looking to buy a hand held unit to measure
> plated thru hole copper
> thickness.  I know CMI makes one but it can only
> measure a minimum hole size
> of 35 mils.  Are there any other vendors out there
> that make hand held
> units.
>
> Would appreciate any information.
>
> Thanks!
>
> Wm. Dean May
> NSWC Crane
> Bldg. 38, Code 8086
> 300 Highway 361
> Crane, IN 47522
> 812-854-3073
>
>
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Date:         Fri, 24 Mar 2000 08:33:20 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Julie Dixon <[log in to unmask]>
Subject:      Low Current Density Smut
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Rick,

We had a problem early this year when our heated rinse water wasn't heated
and
panels in the pre plate were hitting 58 F rinses and a 68 F sulfuric dip then
smutting
when hitting a 74 F acid copper plating bath. I used a thermal scanner from
the
dry film room and noticed the panels were 68 F also when hitting the bath. We
drained the rinses, filled with warm water 98 F (the temp of the cooling
water from
the etcher), and all other conditions exactly the same, the panels plated
perfect.

When the occasional smut monster sneaks into our plant it can usually be tamed
by increasing the ASF to 35-40 ASF for the first 5 minutes of plating. We
metered
the amps at the rack spline. Only thing being, on this particular panel the
copper
area was way uneven. We split the layup in half so all the copper area
wouldn't be
on one side of the panel. But it was a weird balance then,too, as the front
half was
very heavy, the far half very light; and just the opposite on the other side
of the panel.
Thus, I wondered how this affected the overall distribution of ASF across the
panel.

This whole smut thing is only a very occasional experience when conditions
must
be ripe. From what we experience, contributing factors are 2 trips through
the DML
line, aging preplate, cold weather, organics creeping in the plating bath.
Still within
our pm windows but sometimes there appears to be another factor we can't
finger
which throws us out. The net has suggested pd in microetches to be a factor
and
over and under etching in general to be issues in smut. I think we'll try a
proprietary
microetch my DML advisor is suggesting which is supposed to eliminate smut for
ever. Believe that? I just use a generic now, so I'm going to try it. I'll
let you all know
how it works out.

Thanks for your input,
Julie

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Date:         Fri, 24 Mar 2000 08:23:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bev Christian <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Wade,
Further to what Doug wrote,  you can also correlate cleanliness tester
readings to what you "normally" (or otherwise ;(  )   see on your boards.
In the early 90's, while I was with Nortel Networks, through a two-lab test
program we found that most circuit packs manufactured with wave or foam
fluxers and no-clean fluxes gave values of 2.5 to 4.5 SOD for a particular
brand of cleanliness tester.  6-8 we took as yellow light and above 10 as a
red light situation - the board probably took a bath in a flux wave and you
usually had flux residues in your edge connectors - not a good scenario.
Pretty seat-of-the -pants, but better than nothing.

Bev Christian
XLTEK

-----Original Message-----
From: Douglas Pauls [mailto:[log in to unmask]]
Sent: March 24, 2000 7:53 AM
To: [log in to unmask]
Subject: Re: [TN] process control of final cleanliness in a no-clean
world


In a message dated 03/22/2000 4:11:05 PM US Eastern Standard Time,
[log in to unmask] writes:

>         How do all of you in the no-clean world monitor and control board
>  cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter
to
>  monitor our 'cleaning' process.  Do some of you still use an ionic
>  contamination tester or do you use SIR testing or nothing or what?

Wade,
How did you do process control before you went no-clean?  You can still use
an Omegameter or Ionograph (or other such instrument) as PROCESS CONTROL,
but
you have to throw out everything you know about "good" adn "bad" numbers.
Those instruments work for process control, but not for accept-reject.   The
result that you get will probably be higher, because the weak organic acid
activators come off of the board and make the isoproapnol-water solution
conductive.  The materials are benign on a board surface.  You should do
some
correlation studies between accelerated electrical testing, such as burn-in
or life tests, and Omegameter readings.  Determine what maximum reading
correlates to failures in such accelerated testing.  Then use that as your
maximum control limit.

Doug Pauls
CSL

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Date:         Fri, 24 Mar 2000 08:46:10 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
X-To:         Alain Savard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Alain,

Of course, I agree. What I was pointing out though, is that device is used
in this shop anyway, to gage general plating thickness only, not limited to
a specific hole size.

We know that is we are plating X amount in a 35 mil hole, we should see Y
amount over the other size holes and across the surface.

When we need more precise thickness data, we would cross-section, XRF, etc,
etc.

Franklin

----- Original Message -----
From: Alain Savard <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 24, 2000 4:16 AM
Subject: Re: [TN] Measuring plated thru hole copper


> Don't know how to tell you this Franklin, put copper plating in small
> diameter holes (below 0.014") is not the same as in larger holes. In small
> holes, you may get much thicker plating at the surface and near the knee
of
> the hole then what you get near the centre of the hole. Back when we had
our
> in-house plating shop, way back in '97, I had looked into getting such a
> device and found it unreliable at best. It gives a good approximation, but
> it measures an overall average, not the thinnest points. But technologies
> may have changed since I looked into this.
>
> My 2 cents worth,
>
> Alain Savard, B.Sc.
> Chemical Process Analyst
> CAE Electronics Ltd.
> e-mail: [log in to unmask]
>
> -----Original Message-----
> From: Franklin Asbell
> Subject: Re: [TN] Measuring plated thru hole copper
>
> Are you looking for a device to measure thickness on individual holes? O
> overall through hole plating. The CMI device is very accurate at measuring
> hole wall copper thickness.
>
> Yes, it has hole size limitaitons but it's not the actual hole you are
> measuring, right? You might consider adding a few probe holes around the
> panel, the CMI unit works great in that way.
>
> Franklin
>
> ----- Original Message -----
> From: May William D (Dean) CNIN
> Subject: [TN] Measuring plated thru hole copper
>
> > We are looking to buy a hand held unit to measure plated thru hole
copper
> > thickness.  I know CMI makes one but it can only measure a minimum hole
> size
> > of 35 mils.  Are there any other vendors out there that make hand held
> > units.
> >
> > Would appreciate any information.
> >
> > Thanks!
> >
> > Wm. Dean May
> > NSWC Crane
> > Bldg. 38, Code 8086
> > 300 Highway 361
> > Crane, IN 47522
> > 812-854-3073
>
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Date:         Fri, 24 Mar 2000 16:04:51 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Ingemar Hernefjord (EMW)" <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         Bev Christian <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"

Nice to see you again, Bev. As you are now a company head I thought you said adieu to TechNet for good.
Ingemar Hernefjord

Subject: Re: [TN] process control of final cleanliness in a no-clean
world


Wade,
Further to what Doug wrote,  you can also correlate cleanliness tester
readings to what you "normally" (or otherwise ;(  )   see on your boards.
In the early 90's, while I was with Nortel Networks, through a two-lab test
program we found that most circuit packs manufactured with wave or foam
fluxers and no-clean fluxes gave values of 2.5 to 4.5 SOD for a particular
brand of cleanliness tester.  6-8 we took as yellow light and above 10 as a
red light situation - the board probably took a bath in a flux wave and you
usually had flux residues in your edge connectors - not a good scenario.
Pretty seat-of-the -pants, but better than nothing.

Bev Christian
XLTEK

--

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Date:         Fri, 24 Mar 2000 16:36:55 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "d. terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Re: ?BEST PROFILE FOR GOLD PLATED PINS
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Luis,

IPC-A-610 revision B states in chapter 4.1 : "There are solder alloy =
compositions, lead or printed board platings and special soldering =
processes that may produce dull matte, gray, or grainy appearing solders =
that are normal for the material or process involved. These joints are =
acceptable".
What you're seeing is a result of gold in the solderjoint, not of the =
temperature profile. You can test this by pretinning some of these parts.
Whether the amount of gold in the joints (gold embrittlement) is acceptable=
 for your product is another discussion.=20

Kind regards

Daan Terstegge
SMT Centre
Signaal Communications
Unclassified mail
Personal website: http://surf.to/smtinfo=20

>>> Luis Alcantra <[log in to unmask]> 03/22 5:56 pm >>>
Hi every one:
             We are currently experiencing some dificulties soldering gold
plated pins, they go on a 1/2 of an inch square pcb w/a cap an a resistor.
we had tried several profiles with no satisfactory results, we are using
kester #Sn63Pb37 solder on a Vitronics 722 20 zone reflow oven as follows:
165-175-250-  -260-260-260-260-260-280-400 degrees temp. it may seen to
high but our pcb fixture is thick an pcb bar holders on each side.

The problem is solder looks GRAINNY/COLD any suggestions for a good solder
paste/profile?

regards.

LUIS ALCANTARA
ENGINEERING DEPT.
[log in to unmask]
(623) 516-3700

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Date:         Fri, 24 Mar 2000 09:31:06 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Measuring plated thru hole copper
MIME-Version: 1.0
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Alain,
That average takes into consideration the thinnest points(from what I
have found). The CMI unit operates on the eddy current principle.
Baaaaack in 1992 I performed a gage R&R on this unit and found it to be
extremely reliable for our process, i.e. 1.2 - 1.5 mils of copper in the
hole. I plan on doing another study on the current unit we use and will
post those interested. Aside from pinning or cross sectioning I've found
this to be most efficient if the instrument being used is reliable,
again for your process.
Rick
GTC

>-----Original Message-----
>From:  Alain Savard [SMTP:[log in to unmask]]
>Sent:  Friday, March 24, 2000 5:17 AM
>To:    [log in to unmask]
>Subject:       Re: [TN] Measuring plated thru hole copper
>
>Don't know how to tell you this Franklin, put copper plating in small
>diameter holes (below 0.014") is not the same as in larger holes. In small
>holes, you may get much thicker plating at the surface and near the knee of
>the hole then what you get near the centre of the hole. Back when we had our
>in-house plating shop, way back in '97, I had looked into getting such a
>device and found it unreliable at best. It gives a good approximation, but
>it measures an overall average, not the thinnest points. But technologies
>may have changed since I looked into this.
>
>My 2 cents worth,
>
>Alain Savard, B.Sc.
>Chemical Process Analyst
>CAE Electronics Ltd.
>e-mail: [log in to unmask]
>
>-----Original Message-----
>From: Franklin Asbell
>Subject: Re: [TN] Measuring plated thru hole copper
>
>Are you looking for a device to measure thickness on individual holes? O
>overall through hole plating. The CMI device is very accurate at measuring
>hole wall copper thickness.
>
>Yes, it has hole size limitaitons but it's not the actual hole you are
>measuring, right? You might consider adding a few probe holes around the
>panel, the CMI unit works great in that way.
>
>Franklin
>
>----- Original Message -----
>From: May William D (Dean) CNIN
>Subject: [TN] Measuring plated thru hole copper
>
>> We are looking to buy a hand held unit to measure plated thru hole copper
>> thickness.  I know CMI makes one but it can only measure a minimum hole
>size
>> of 35 mils.  Are there any other vendors out there that make hand held
>> units.
>>
>> Would appreciate any information.
>>
>> Thanks!
>>
>> Wm. Dean May
>> NSWC Crane
>> Bldg. 38, Code 8086
>> 300 Highway 361
>> Crane, IN 47522
>> 812-854-3073
>
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Date:         Fri, 24 Mar 2000 11:57:41 -0500
Reply-To:     "[log in to unmask]" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gerard O'Brien <[log in to unmask]>
Organization: Photocircuits Corporation
Subject:      test facilities

I need a recommendation for an independent test lab capable of running
failure analysis on electrolytic capacitors. Any input would be greatly
appreciated.

Regards
Gerard O'Brien
Photocircuits Corp.

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Date:         Fri, 24 Mar 2000 11:18:12 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Oberle, Wade" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Oberle, Wade" <[log in to unmask]>
Subject:      moisture sensitive components
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dear Technetters,
        How do you define or classify moisture sensitive components?  I
always think of plastic BGAs as being an example of moisture sensitive parts
but that is based on word of mouth.  I have never read that in a 'Component
data sheet'.  Please point me in the right direction as to where to find a
list of particular package types or part numbers that are 'moisture
sensitive'.

Thanks in advance.

Wade Oberle

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Date:         Fri, 24 Mar 2000 09:45:07 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Patel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Patel <[log in to unmask]>
Subject:      Realiability info: Failure rate with confedence level
Mime-Version: 1.0
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Reliability/Quality Guru,
I received this question from our engineering department.

Currently, they are seeing 1 system crash out of 10 times. They want to
improve the crash rate to 1 failure every 30 times with 90% confidence
level. They want to know how many operation "X" they will run with no more
than "Y" failures with 90% confidence level which will yield 1 failure every
30 times.

I do not know how to solve it as haven't practiced it. Am I providing enough
information or what information is needed to make a sense out of it? What
kind of model it will fit, Poisson, Binomial, etc?

Any help will be highly appreciated.

re,
ken patel


______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Fri, 24 Mar 2000 09:53:43 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      laminate stress relief
MIME-Version: 1.0
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Good Day, TechNet!
board fabs: what (if any) baking of incoming core material do you do to
minimize movement of layers. We try to have the material at 250=B0F for =
one
hour based on what someone told us quite a while back. Without going =
through
a big DOE, I'd like to ascertain if that's enough.
Danke sch=F6n.

Timothy Reeves
ECD Circuit Board Division
13626 South Freeman Road
Mulino, OR 97042
[log in to unmask]
(503) 829-9108 (800) 228-8198  FAX (503) 829-5482

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Date:         Fri, 24 Mar 2000 11:56:59 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Franklin Asbell <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Franklin Asbell <[log in to unmask]>
Subject:      Re: laminate stress relief
X-To:         Timothy Reeves <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

Timothy,

Baking? We're supposed to be baking that stuff?

Franklin


----- Original Message -----
From: Timothy Reeves <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 24, 2000 9:53 AM
Subject: [TN] laminate stress relief


Good Day, TechNet!
board fabs: what (if any) baking of incoming core material do you do to
minimize movement of layers. We try to have the material at 250°F for one
hour based on what someone told us quite a while back. Without going through
a big DOE, I'd like to ascertain if that's enough.
Danke schön.

Timothy Reeves
ECD Circuit Board Division
13626 South Freeman Road
Mulino, OR 97042
[log in to unmask]
(503) 829-9108 (800) 228-8198  FAX (503) 829-5482

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Date:         Fri, 24 Mar 2000 10:05:16 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alan Cochrane <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alan Cochrane <[log in to unmask]>
Organization: @Home Network
Subject:      Re: Realiability info: Failure rate with confedence level
X-To:         Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ken,
There is a great program out called "statgraphics" it has a module which
is called "forecasting" and it will, given a set of variables, do a
pretty fair job of determining anticipated failure rates.  It also has
every type of graphing function you may want.

Regards,

Alan B. Cochrane


Ken Patel wrote:
>
> Reliability/Quality Guru,
> I received this question from our engineering department.
>
> Currently, they are seeing 1 system crash out of 10 times. They want to
> improve the crash rate to 1 failure every 30 times with 90% confidence
> level. They want to know how many operation "X" they will run with no more
> than "Y" failures with 90% confidence level which will yield 1 failure every
> 30 times.
>
> I do not know how to solve it as haven't practiced it. Am I providing enough
> information or what information is needed to make a sense out of it? What
> kind of model it will fit, Poisson, Binomial, etc?
>
> Any help will be highly appreciated.
>
> re,
> ken patel
>
> ______________________________________________________
> Ken Patel                       Phone:  (408) 490-6804
> 1708 McCarthy Blvd.             Fax:    (408) 490-6859
> Milpitas, CA 95035              Beeper: (888) 769-1808
>
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Date:         Fri, 24 Mar 2000 13:27:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lou Hart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Subject:      Re: Realiability info: Failure rate with confedence level
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding:  quoted-printable

Ken and Technetters, Poisson statistics apply here.  Go to a table or =
nomograph of the cumulative Poisson distribution, which are likely to be =
in a quality or reliability engineering handbook. =20

I checked the one on page 35 of O'Connor's Practical Reliability =
Engineering, 3rd edition, and generated this small table.

X       Y
74      0
147     1
203     2
285     5

Lou Hart, CRE=20

----------
From:   Ken Patel[SMTP:[log in to unmask]]
Sent:   Friday, March 24, 2000 12:45 PM
To:     [log in to unmask]
Subject:        [TN] Realiability info: Failure rate with confedence level

Reliability/Quality Guru,
I received this question from our engineering department.

Currently, they are seeing 1 system crash out of 10 times. They want to
improve the crash rate to 1 failure every 30 times with 90% confidence
level. They want to know how many operation "X" they will run with no =
more
than "Y" failures with 90% confidence level which will yield 1 failure =
every
30 times.

I do not know how to solve it as haven't practiced it. Am I providing =
enough
information or what information is needed to make a sense out of it? =
What
kind of model it will fit, Poisson, Binomial, etc?

Any help will be highly appreciated.

re,
ken patel


______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Fri, 24 Mar 2000 11:37:34 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Tracy Black <[log in to unmask]>
Subject:      Electroless Gold Plating
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi all you active Tech-Netters:

I am looking for a specification for Electroless Gold Plating; ASTM or
MIL-G/-STD, either is O.K.  Does anybody know where I might find any
information on the application of Electroless Gold, i.e. the pitfalls and
problems with odd geometry.

Tracy

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Date:         Fri, 24 Mar 2000 13:48:40 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tempea, Ioan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: moisture sensitive components
MIME-Version: 1.0
Content-Type: text/plain

Wade,

the definition of moisture sensisivity and the levels are in J-STD-020A. You
can download it for free at the JEDEC website,
http://www.jedec.org/DOWNLOAD/default_joint.htm.

As for associated levels to each component, you must have it indicated on
the bag in which the components come from the manufacturer, not in the data
sheet. Be careful, most ICs and not only are moisture sensitive, regardless
of the package, SOs, PLCCs, QFPs, etc.

So, if you want to elucidate the status of your components you have to see
the original bag, the one that comes at the incoming inspection. After that,
it is possible that the stockroom personnel remove the bags in order to make
the components fit in the locations. Let's call it innocence.

Regards,
Ioan

> -----Original Message-----
> From: Oberle, Wade [SMTP:[log in to unmask]]
> Sent: Friday, March 24, 2000 12:18 PM
> To:   [log in to unmask]
> Subject:      [TN] moisture sensitive components
>
> Dear Technetters,
>         How do you define or classify moisture sensitive components?  I
> always think of plastic BGAs as being an example of moisture sensitive
> parts
> but that is based on word of mouth.  I have never read that in a
> 'Component
> data sheet'.  Please point me in the right direction as to where to find a
> list of particular package types or part numbers that are 'moisture
> sensitive'.
>
> Thanks in advance.
>
> Wade Oberle
>
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Date:         Fri, 24 Mar 2000 14:16:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Dube <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Dube <[log in to unmask]>
Subject:      Re: laminate stress relief
X-To:         Timothy Reeves <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit

Stress releif baking needs to be done above the Tg for the material. Most
would hold at that temperature for 4 hours min. The cool down rate is
critical because of the various CTEs of the laminate constituents (glass,
epoxy, copper). Somewhere around 4 deg/min F back thru the Tg is usually
what's recommended.

Bob Dube

-----Original Message-----
From: Timothy Reeves <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Friday, March 24, 2000 12:56 PM
Subject: [TN] laminate stress relief


Good Day, TechNet!
board fabs: what (if any) baking of incoming core material do you do to
minimize movement of layers. We try to have the material at 250°F for one
hour based on what someone told us quite a while back. Without going through
a big DOE, I'd like to ascertain if that's enough.
Danke schön.

Timothy Reeves
ECD Circuit Board Division
13626 South Freeman Road
Mulino, OR 97042
[log in to unmask]
(503) 829-9108 (800) 228-8198  FAX (503) 829-5482

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Date:         Fri, 24 Mar 2000 14:51:32 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: laminate stress relief
X-To:         Bob Dube <[log in to unmask]>
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Isn't this stuff supposed to have been baked already during manufacture =
of
the cores?

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Bob Dube=20
Subject: Re: [TN] laminate stress relief

Stress releif baking needs to be done above the Tg for the material. =
Most
would hold at that temperature for 4 hours min. The cool down rate is
critical because of the various CTEs of the laminate constituents =
(glass,
epoxy, copper). Somewhere around 4 deg/min F back thru the Tg is =
usually
what's recommended.

Bob Dube

-----Original Message-----
From: Timothy Reeves=20
Subject: [TN] laminate stress relief

board fabs: what (if any) baking of incoming core material do you do to
minimize movement of layers. We try to have the material at 250=B0F for =
one
hour based on what someone told us quite a while back. Without going =
through
a big DOE, I'd like to ascertain if that's enough.

Timothy Reeves

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Date:         Fri, 24 Mar 2000 14:03:03 PST
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Glenn Pelkey <[log in to unmask]>
Subject:      Re: Realiability info: Failure rate with confedence level
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi Ken,

        I get pretty much the same numbers as the other replies.  Binomial
assumes independent and equally likely.  The Poisson is an approximation of
the Binomial under certain conditions (large sample size (n), small defect
percentage (p), and n x p< or = 7, or so says my thick Stats book).
        Your question is the same as inspection sampling.  Except with
inspection sampling, they also through in the Hypergeometric.  (Here's one of
those terms to through out and impress your friends!)  With reliability,
failures are a function of time.  However, with software, there is no time
dependance (i.e. no aging).

Using Excel,

Binomial:
Sample Size (X) Failures (Y)
----------------------  ----------------
      76                     0
    129              1
    176              2
    221              3
    265              4
    308              5

Poisson:
Sample Size (X) Failures (Y)
----------------------  ----------------
      70                     0
    118              1
    162              2
    203              3
    242              4  Violates Rule, use Binomial
    281              5  Violates Rule, use Binomial

Glenn

Ken Patel <[log in to unmask]> Wrote:
|
| Reliability/Quality Guru,
| I received this question from our engineering department.
|
| Currently, they are seeing 1 system crash out of 10 times. They want to
| improve the crash rate to 1 failure every 30 times with 90% confidence
| level. They want to know how many operation "X" they will run with no more
| than "Y" failures with 90% confidence level which will yield 1 failure every
| 30 times.
|
| I do not know how to solve it as haven't practiced it. Am I providing enough
| information or what information is needed to make a sense out of it? What
| kind of model it will fit, Poisson, Binomial, etc?
|
| Any help will be highly appreciated.
|
| re,
| ken patel
|
|
| ______________________________________________________
| Ken Patel                       Phone:  (408) 490-6804
| 1708 McCarthy Blvd.             Fax:    (408) 490-6859
| Milpitas, CA 95035              Beeper: (888) 769-1808
|
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Date:         Sat, 25 Mar 2000 13:48:27 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         Grant Emandien <[log in to unmask]>
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Grant

As a general rule, coating over flux residues is dangerous IMHO. There
may be a few exceptions, but these are generally unavailable to the
common mortal. Let us look at what is left on a board:
- unmodified flux residues (it is BS to say that they are "burnt off"),
possibly a dibasic carboxylic acid, maybe with organic halides, maybe
with rosin or something similar
- ionic salts (tin, lead, copper etc. carboxylates, halides, etc.)
- polymerised flux residues
- contaminants from boards and components, which may include
inadequately washed water-soluble fluxes etc.
- residues from rheological modifiers, maybe glycols etc. (hygroscopic)

If you leave all these on the board and then coat over them, you are in
DEEP trouble.

One possible exception is where the flux is a fairly concentrated adipic
acid type and where the coating is an epoxy which requires adipic acid
for cross-linking, but this is hairy a) because it will be impossible to
guarantee stoichiometry, b) it will not be homogeneous and c) you still
have all the other gunge under the coating. The automobile industry use
this technique (ever wonder why there are so many modern cars with
failures of the electronics?).

The short answer is your vendor is a liar.

Brian


Grant Emandien wrote:
>
> Hi all,
>
> The debate on cleaning of fluxes as well as the use no-clean fluxes seems to
> hang around forever. We have been informed by our solder an flux supplier
> that assemblies with no clean fluxes can be conformally coated without the
> need to clean the boards.
>
> The argument is that the high temperatures of the reflow oven 'burns off'
> the active ingredients, leaving only inactive residues. These flux residues
> do not have to be cleaned and can supposedly be coated. The rep. believes we
> are taking a backward step by possibly opting to use water-based flux. Is
> this pure sales talk?
>
> Is anyone able to offer any advice or insight, or been able to assess the
> environmental and electrical performance of such assemblies.
>
> Regards
> Grant
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
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     Web services division:
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Date:         Sat, 25 Mar 2000 14:12:06 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         "Oberle, Wade" <[log in to unmask]>
MIME-Version: 1.0
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Wade

I agree with the others but would add one minor point. Qualify your
process as "safe" according to your needs. Measure the ionic
contamination with whatever instrument you will on, say, 20 boards from
a similar batch, keeping the test going to near-asymptote (say less that
1% conductivity change in one minute). Note these final values and
calculate the mean and standard deviation (ideally, the distribution
should be a neat bell-curve). For that type of board, run regular tests
in production: if they fall significantly outside the mean +/- SD
(either higher or lower), then your process is probably going off the
rails. Note that a lower reading of contamination may be just as
dangerous as a higher one, because it signifies a change in the process
parameters.

Brian

"Oberle, Wade" wrote:
>
> Dear technetters,
>         How do all of you in the no-clean world monitor and control board
> cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
> monitor our 'cleaning' process.  Do some of you still use an ionic
> contamination tester or do you use SIR testing or nothing or what?
>
> Thanks in advance for your advice.
>
> Wade Oberle
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
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Date:         Sat, 25 Mar 2000 14:22:33 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: Vapor Phase update...
X-To:         [log in to unmask]
MIME-Version: 1.0
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Steve

Yes it is non-ODP but it is VERY GWP!

I have used a Galden at 260-265°C, many years ago. Quite satisfied with
it.

I have yet to see a non-emitting machine, although some are pretty low.

Bill: There is no reason, at this time, to think that PFCs will be
generally banned like CFC solvents. However, they may be heavily taxed,
or worse, in some countries. Trichloroethylene, to the best of my
knowledge, has been banned only in Sweden. Maybe you are meaning
1,1,1-trichloroethane (which is not usually abbreviated to trichlor),
which has been banned as an ozone-depleter????? That is a horse of a
totally different colour.

Brian

"Stephen R. Gregory" wrote:
>
> Hi ya'll!
>
> Well, I just got through talking with someone at 3M...the FC-71 product has
> been discontinued. The highest boiling point heat transfer fluid they make is
> the FC-70 which boils at 215 º C. Just for grins I asked how much that stuff
> sells for, and was told that it's sold by the pound. A gallon weighs 15-lbs,
> and it's $60.00 a pound! YOWZA! $900 a gallon!!!
>
> Called Galden Fluids, and they have a heat transfer fluid they call HT250
> which boils at 250º C. The say their stuff
> (http://www.inlandvacuum.com/galden.html) is a non ODP chemical. The spec
> sheet for all their stuff is at (http://www.inlandvacuum.com/galdenspecs.html)
>
> A gallon of the HT250 is around $560...anybody ever use this stuff?
>
> Still haven't found anything about the equipment. There's some used stuff out
> there but like Brian said in his post, I want to make sure I find something
> that I won't have to keep pouring this "liquid gold" into to be able run
> it...like the owl says; "I give a hoot, I don't wanna pollute!" (not
> mentioning the cost).
>
> -Steve Gregory-
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Sat, 25 Mar 2000 10:05:36 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Doug <[log in to unmask]>
Subject:      Re: Bellcore: Silver & Tin
MIME-Version: 1.0
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Forwarded from

David Spencer wrote:

> Background
> I have been working on, or should I say
> "I have been worked over by..", the
> requirements of GR-78-CORE. Requirement
> R6-8 states, "Silver shall not be used
> as a conductor or contact finish. []
> Tin shall not be used as a conductor or
> contact finish unless subjected to an
> approved reflow process."
>
> During our prototype phase, we have used
> immersion gold. Our Mfg. Eng. wants to
> move to immersion silver or white tin,
> because the gold is expensive and can have
> solderability/reliability problems related
> to the nickel plating under the gold flash.
>
> Questions
> Does anyone have a ruling on the use of
> silver or white tin immersion finishes from
> any of the RBOC's as it relates to the
> requirements of GR-78-CORE?
>
> Are there any documented tests of these
> finishes available, i.e. accelerated aging,
> solderability, insulation resistance, etc ?
>
> Does anyone have experience with either of
> these finishes in the hygroscopic dust/gaseous
> contamination test suite from GR-63-CORE?
>
> Thanks for your help!
> Dave Spencer

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Date:         Sat, 25 Mar 2000 17:22:37 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Karen Tellefsen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
Comments:     RFC822 error: <W> Incorrect or incomplete address field found and
              ignored.
From:         Karen Tellefsen <[log in to unmask]>
Subject:      Re: Bellcore: Silver & Tin
X-To:         [log in to unmask]
MIME-Version: 1.0
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I've run GR-78 EM tests on immersion silver and it passes.
It also passes with low-solids no-clean flux, comb up.
I can email data if you wish.

Some of my colleagues looked at the solderability
of immersion Ag, it's good, but HASL is better.

I suspect that hygroscopic dust/FMG exposure would quickly
degrade the solderability of immersion Ag.

----------
> From: Doug <[log in to unmask]>
> To: [log in to unmask]
> Subject: Re: [TN] Bellcore: Silver & Tin
> Date: Saturday, March 25, 2000 1:05 PM
>
> Forwarded from
>
> David Spencer wrote:
>
> > Background
> > I have been working on, or should I say
> > "I have been worked over by..", the
> > requirements of GR-78-CORE. Requirement
> > R6-8 states, "Silver shall not be used
> > as a conductor or contact finish. []
> > Tin shall not be used as a conductor or
> > contact finish unless subjected to an
> > approved reflow process."
> >
> > During our prototype phase, we have used
> > immersion gold. Our Mfg. Eng. wants to
> > move to immersion silver or white tin,
> > because the gold is expensive and can have
> > solderability/reliability problems related
> > to the nickel plating under the gold flash.
> >
> > Questions
> > Does anyone have a ruling on the use of
> > silver or white tin immersion finishes from
> > any of the RBOC's as it relates to the
> > requirements of GR-78-CORE?
> >
> > Are there any documented tests of these
> > finishes available, i.e. accelerated aging,
> > solderability, insulation resistance, etc ?
> >
> > Does anyone have experience with either of
> > these finishes in the hygroscopic dust/gaseous
> > contamination test suite from GR-63-CORE?
> >
> > Thanks for your help!
> > Dave Spencer
>
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Date:         Sun, 26 Mar 2000 19:44:52 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Bellcore: Silver & Tin
X-To:         [log in to unmask]
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit

David Spencer wrote:
> Background
> I have been working on, or should I say "I have been worked over by..", the
> requirements of GR-78-CORE. Requirement R6-8 states, "Silver shall not be
used
> as a conductor or contact finish. [] Tin shall not be used as a conductor or
> contact finish unless subjected to an approved reflow process."
>
> During our prototype phase, we have used immersion gold. Our Mfg. Eng.
wants to
> move to immersion silver or white tin, because the gold is expensive and
can have
> solderability/reliability problems related to the nickel plating under the
gold flash.
>
> Questions
> Does anyone have a ruling on the use of silver or white tin immersion
finishes from
> any of the RBOC's as it relates to the requirements of GR-78-CORE?
>
> Are there any documented tests of these finishes available, i.e.
accelerated aging,
> solderability, insulation resistance, etc ?
>
> Does anyone have experience with either of these finishes in the
hygroscopic
> dust/gaseous contamination test suite from GR-63-CORE?
>
> Thanks for your help!
> Dave Spencer

Hi Dave,
Be careful with Ag; I am sure you heard about 'gold embrittlement' of
solder--silver is worse.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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Date:         Sun, 26 Mar 2000 21:20:02 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Joe Barocio <[log in to unmask]>
Subject:      Dielectric Constant of FR4
In-Reply-To:  <009f01bf9526$ecb5da60$6400a8c0@franklin>
MIME-Version: 1.0
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I'm seeing variations of up to 60% in capacitance between signal traces
and ground plane on a stripline PWB; trace widths appear to be
consistent among PWB's . Can these diffferences be attributed to
variations in the dielectric constant of the FR4 material?

Is there a method to check board layer thickness without actually
sectioninng, and destroying, the PWB's?

Any help would be greatly appreciated.

Joe Barocio
[log in to unmask]

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Date:         Mon, 27 Mar 2000 15:53:18 +0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Le Dai Tri <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Le Dai Tri <[log in to unmask]>
Subject:      European Specification for Halogen free Material ?
MIME-Version: 1.0
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        boundary="----=_NextPart_001_00DB_01BF9804.91D4D980"


------=_NextPart_001_00DB_01BF9804.91D4D980
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        charset="x-user-defined"
Content-Transfer-Encoding: quoted-printable

Dear Technetters:

Japanese spec for Halogen free Material (CCL) is=20
        Chlorine (Cl) contents: 0.09% or less
        Bromine (Br) contents: 0.09% or less

Then I am looking for European specification for Halogen free Material.=20
Does anybody know about it and where I might find any information ?

Any input would be greatly appreciated.

Best regards,
TRI                                                                      =
                =20
E-Mail: [log in to unmask]

------=_NextPart_001_00DB_01BF9804.91D4D980
Content-Type: text/html;
        charset="x-user-defined"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dx-user-defined" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2314.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DVNI-Times size=3D2>Dear Technetters:<BR><BR>Japanese =
spec for=20
Halogen free Material (CCL) is </FONT></DIV>
<DIV><FONT face=3DVNI-Times size=3D2>&nbsp;&nbsp;&nbsp; =
&nbsp;&nbsp;&nbsp; Chlorine=20
(Cl) contents: 0.09% or less</FONT></DIV>
<DIV><FONT face=3DVNI-Times size=3D2>
<DIV><FONT face=3DVNI-Times =
size=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
Bromine (Br) contents: 0.09% or less</FONT></DIV>
<DIV>&nbsp;</DIV></FONT></DIV>
<DIV><FONT face=3DVNI-Times size=3D2>Then I am looking for&nbsp;European =

specification for Halogen free Material. </FONT></DIV>
<DIV><FONT face=3DVNI-Times size=3D2>Does anybody know about it and =
where I might=20
find any information ?</FONT></DIV>
<DIV><FONT face=3DVNI-Times size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DVNI-Times size=3D2>Any input would be greatly=20
appreciated.</DIV></FONT>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DVNI-Times size=3D2>Best regards,</FONT></DIV>
<DIV><FONT face=3DVNI-Times=20
size=3D2>TRI&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;<BR>E-Mail:=20
<A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]
</A>&nbsp;</FONT></DIV></BODY></HTML>

------=_NextPart_001_00DB_01BF9804.91D4D980--

------=_NextPart_000_00DA_01BF9804.91D4D980
Content-Type: text/x-vcard;
        name="LE DAI TRI.vcf"
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment;
        filename="LE DAI TRI.vcf"

BEGIN:VCARD
VERSION:2.1
N:TRI;LE;DAI;Deputy Manager of Development Section
FN:LE DAI TRI
ORG:Fujitsu Computer Products of Vietnam, Inc.;PWB Manufacturing
TITLE:Deputy Manager of Development Section
TEL;WORK;VOICE:84-61-836.563
TEL;WORK;FAX:84-61-836.573
ADR;WORK;ENCODING=3DQUOTED-PRINTABLE:;Development section;Bien Hoa =
Industrial Zone II=3D0D=3D0A;Bien Hoa;Dong Nai;000=3D
0;Vietnam
LABEL;WORK;ENCODING=3DQUOTED-PRINTABLE:Development section=3D0D=3D0ABien =
Hoa Industrial Zone II=3D0D=3D0A=3D0D=3D0ABien Hoa, Do=3D
ng Nai 0000=3D0D=3D0AVietnam
EMAIL;PREF;INTERNET:[log in to unmask]
REV:20000327T085318Z
END:VCARD

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Date:         Sun, 26 Mar 2000 23:51:20 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Graham Naisbitt <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Graham Naisbitt <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         Grant Emandien <[log in to unmask]>
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Deja Vu. Haven't we been here before?

Regards,
Graham Naisbitt

[log in to unmask]

WEB: http://www.concoat.co.uk

CONCOAT Ltd
Alasan House, Albany Park
CAMBERLEY GU15 2PL UK

Tel: +44 (0) 1276 691100  Fax: +44 (0) 1276 691227
----- Original Message -----
From: Grant Emandien <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 20, 2000 10:24 AM
Subject: [TN] Coating of assemblies with no clean fluxes


> Hi all,
>
> The debate on cleaning of fluxes as well as the use no-clean fluxes seems
to
> hang around forever. We have been informed by our solder an flux supplier
> that assemblies with no clean fluxes can be conformally coated without the
> need to clean the boards.
>
> The argument is that the high temperatures of the reflow oven 'burns off'
> the active ingredients, leaving only inactive residues. These flux
residues
> do not have to be cleaned and can supposedly be coated. The rep. believes
we
> are taking a backward step by possibly opting to use water-based flux. Is
> this pure sales talk?
>
> Is anyone able to offer any advice or insight, or been able to assess the
> environmental and electrical performance of such assemblies.
>
> Regards
> Grant
>
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Date:         Mon, 27 Mar 2000 11:52:17 +0100
Reply-To:     Alan Brewin <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alan Brewin <[log in to unmask]>
Subject:      Re: Coating of assemblies with no clean fluxes
X-To:         Brian Ellis <[log in to unmask]>
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Dear Brian/Grant,

Amen. Supporting customers using conformal coating products, as I do, this
is one of the most commonly asked questions, and I agree with Brian's
answer.

In fact this is why we use SIR as a research tool in development and many
people who chose to coat over no-clean validate their mix of process
chemicals and process settings with SIR.

Other residues can also come from handling, especially if staff have been
used to a process where the boards were cleaned in the past.

Regards,

Alan Brewin.
Concoat Ltd.

-----Original Message-----
From: Brian Ellis <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: 25 March 2000 13:56
Subject: Re: [TN] Coating of assemblies with no clean fluxes


>Grant
>
>As a general rule, coating over flux residues is dangerous IMHO. There
>may be a few exceptions, but these are generally unavailable to the
>common mortal. Let us look at what is left on a board:
>- unmodified flux residues (it is BS to say that they are "burnt off"),
>possibly a dibasic carboxylic acid, maybe with organic halides, maybe
>with rosin or something similar
>- ionic salts (tin, lead, copper etc. carboxylates, halides, etc.)
>- polymerised flux residues
>- contaminants from boards and components, which may include
>inadequately washed water-soluble fluxes etc.
>- residues from rheological modifiers, maybe glycols etc. (hygroscopic)
>
>If you leave all these on the board and then coat over them, you are in
>DEEP trouble.
>
>One possible exception is where the flux is a fairly concentrated adipic
>acid type and where the coating is an epoxy which requires adipic acid
>for cross-linking, but this is hairy a) because it will be impossible to
>guarantee stoichiometry, b) it will not be homogeneous and c) you still
>have all the other gunge under the coating. The automobile industry use
>this technique (ever wonder why there are so many modern cars with
>failures of the electronics?).
>
>The short answer is your vendor is a liar.
>
>Brian
>
>
>Grant Emandien wrote:
>>
>> Hi all,
>>
>> The debate on cleaning of fluxes as well as the use no-clean fluxes seems
to
>> hang around forever. We have been informed by our solder an flux supplier
>> that assemblies with no clean fluxes can be conformally coated without
the
>> need to clean the boards.
>>
>> The argument is that the high temperatures of the reflow oven 'burns off'
>> the active ingredients, leaving only inactive residues. These flux
residues
>> do not have to be cleaned and can supposedly be coated. The rep. believes
we
>> are taking a backward step by possibly opting to use water-based flux. Is
>> this pure sales talk?
>>
>> Is anyone able to offer any advice or insight, or been able to assess the
>> environmental and electrical performance of such assemblies.
>>
>> Regards
>> Grant
>>
>> ##############################################################
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>> information.
>> If you need assistance - contact Keach Sasamori at [log in to unmask] or
>> 847-509-9700 ext.5315
>> ##############################################################
>
>--
>Brian Ellis
>Protonique SA
>PO Box 78
>CH-1032 Romanel-sur-Lausanne, Switzerland
>Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
>E-mail: [log in to unmask]
>URL: Technical and consultancy divisions:
>       http://www.protonique.com
>     Web services division:
>       http://www.protonique.com/webserv
>
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Date:         Mon, 27 Mar 2000 07:30:52 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: Dielectric Constant of FR4
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Joe,

Dielectric constant doesn't vary this much, otherwise it wouldn't be much of
a constant would it? Did you request test coupons with your boards? How
about impedance coupons?

You can section either type of coupon whenever in doubt, but you have to
request them first. Otherwise you might just be out of luck.

Have a nice day,

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Joe Barocio
Subject: [TN] Dielectric Constant of FR4

I'm seeing variations of up to 60% in capacitance between signal traces
and ground plane on a stripline PWB; trace widths appear to be
consistent among PWB's . Can these diffferences be attributed to
variations in the dielectric constant of the FR4 material?

Is there a method to check board layer thickness without actually
sectioninng, and destroying, the PWB's?

Joe Barocio
[log in to unmask]

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Date:         Mon, 27 Mar 2000 14:56:38 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lou Hart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
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TechNetters,  (and Brian), I suggest looking into statistical process =
control techniques for something like this.  A standard Shewart chart =
would be the thing.  In fact, I plan on doing it myself in the very near =
future, thanks to Brian's earlier suggestions on cleanliness testing =
techniques.

If you take 1 standard deviation as a "control limit" you'll have lots =
of false alarms.  The purpose of SPC is not so much to tell you when to =
do something, but rather when not to do something, to leave things =
alone.  A while back, a technetter said he'd made a chart, but found =
points always inside the limits.  That's exactly the way things you want =
things to be.  Go to work on something else and don't waste time =
tinkering with a well-behaved process.  Unless it is producing bad =
stuff, in which case you need a new process.
Lou Hart

----------
From:   Brian Ellis[SMTP:[log in to unmask]]
Sent:   Saturday, March 25, 2000 8:12 AM
To:     [log in to unmask]
Subject:        Re: [TN] process control of final cleanliness in a no-clean =
world

Wade

I agree with the others but would add one minor point. Qualify your
process as "safe" according to your needs. Measure the ionic
contamination with whatever instrument you will on, say, 20 boards from
a similar batch, keeping the test going to near-asymptote (say less that
1% conductivity change in one minute). Note these final values and
calculate the mean and standard deviation (ideally, the distribution
should be a neat bell-curve). For that type of board, run regular tests
in production: if they fall significantly outside the mean +/- SD
(either higher or lower), then your process is probably going off the
rails. Note that a lower reading of contamination may be just as
dangerous as a higher one, because it signifies a change in the process
parameters.

Brian

"Oberle, Wade" wrote:
>
> Dear technetters,
>         How do all of you in the no-clean world monitor and control =
board
> cleanliness.  In the days of OA flux, we used an Ionograph or =
Omegameter to
> monitor our 'cleaning' process.  Do some of you still use an ionic
> contamination tester or do you use SIR testing or nothing or what?
>
> Thanks in advance for your advice.
>
> Wade Oberle
>
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additional
> information.
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> 847-509-9700 ext.5315
> ##############################################################

--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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=========================================================================
Date:         Mon, 27 Mar 2000 16:35:47 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              James Barry <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         James Barry <[log in to unmask]>
Subject:      Flex soldermask & PIC
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello fellow Tec-netters - I'm in need of having some flexible solder mask
and/or Dupont PIC applied to some flex product. My question is - "are there
any companies offering this service/process in the New England area".

Thanks

Jim Barry
President & General Mgr.
StrataFlex, Inc.
One Wall Street
Hudson, NH 03051

Phone: (603) 882-1884
Fax:     (603) 882-1830
Web: http://www.strataflex.com/

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Date:         Mon, 27 Mar 2000 15:48:54 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gary Camac <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gary Camac <[log in to unmask]>
Organization: Dickey-john Corp.
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         Lou Hart <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/mixed; boundary="------------70A86FB91316FFCB0821BF94"

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--------------70A86FB91316FFCB0821BF94
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Good afternoon everyone,

A few years back I used  Ionograph testing to try and prove statistical control of my in-line washing process.  I was always within the spec limit, but I could never show a normal distribution.  The data was collected from tests on all varieties of assemblies: single and double sided through hole, and single and double sided mixed technology.

Then it dawned on me that I was throwing apples and oranges in the same crate.  Since the topography of these assemblies are different,  I concluded that I needed charts for each assembly type.  Hmm....quess again Sherlock.  Once again I could not get a normal distribution.

I could  not come up with any assignable causes to explain the lack of a normal distribution.  Since I never had any test outside the spec limit, I had a hard time justifying putting more of my time in the effort.  As you all know, you have to know when to fish and when to cut bait.

Lou Hart wrote:

> TechNetters,  (and Brian), I suggest looking into statistical process control techniques for something like this.  A standard Shewart chart would be the thing.  In fact, I plan on doing it myself in the very near future, thanks to Brian's earlier suggestions on cleanliness testing techniques.
>
> If you take 1 standard deviation as a "control limit" you'll have lots of false alarms.  The purpose of SPC is not so much to tell you when to do something, but rather when not to do something, to leave things alone.  A while back, a technetter said he'd made a chart, but found points always inside the limits.  That's exactly the way things you want things to be.  Go to work on something else and don't waste time tinkering with a well-behaved process.  Unless it is producing bad stuff, in which case you need a new process.
> Lou Hart
>
> ----------
> From:   Brian Ellis[SMTP:[log in to unmask]]
> Sent:   Saturday, March 25, 2000 8:12 AM
> To:     [log in to unmask]
> Subject:        Re: [TN] process control of final cleanliness in a no-clean world
>
> Wade
>
> I agree with the others but would add one minor point. Qualify your
> process as "safe" according to your needs. Measure the ionic
> contamination with whatever instrument you will on, say, 20 boards from
> a similar batch, keeping the test going to near-asymptote (say less that
> 1% conductivity change in one minute). Note these final values and
> calculate the mean and standard deviation (ideally, the distribution
> should be a neat bell-curve). For that type of board, run regular tests
> in production: if they fall significantly outside the mean +/- SD
> (either higher or lower), then your process is probably going off the
> rails. Note that a lower reading of contamination may be just as
> dangerous as a higher one, because it signifies a change in the process
> parameters.
>
> Brian
>
> "Oberle, Wade" wrote:
> >
> > Dear technetters,
> >         How do all of you in the no-clean world monitor and control board
> > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
> > monitor our 'cleaning' process.  Do some of you still use an ionic
> > contamination tester or do you use SIR testing or nothing or what?
> >
> > Thanks in advance for your advice.
> >
> > Wade Oberle
> >
> > ##############################################################
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> --
> Brian Ellis
> Protonique SA
> PO Box 78
> CH-1032 Romanel-sur-Lausanne, Switzerland
> Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> E-mail: [log in to unmask]
> URL: Technical and consultancy divisions:
>        http://www.protonique.com
>      Web services division:
>        http://www.protonique.com/webserv
>
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begin:vcard
n:Camac;Gary R.
tel;fax:217-438-2640
tel;work:217-438-2288
x-mozilla-html:FALSE
org:DICKEY-john Corp.
version:2.1
email;internet:[log in to unmask]
title:Senior Manufacturing Engineer
adr;quoted-printable:;;5200 DICKEY-john Road=0D=0AP.O. Box10;Auburn;Il;62615;USA
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--------------70A86FB91316FFCB0821BF94--

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=========================================================================
Date:         Mon, 27 Mar 2000 14:51:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Chuck Brummer <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Chuck Brummer <[log in to unmask]>
Organization: acuson
Subject:      Re: Flex soldermask & PIC
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James,

We process the DuPont PC 1010 and would be willing to run flexible panels for you if
they fit into our process size and capability. But we are West Coast, LA area.   Call
me please.

Chuck Brummer
Acuson, AIM
818-734-4930

James Barry wrote:

> Hello fellow Tec-netters - I'm in need of having some flexible solder mask
> and/or Dupont PIC applied to some flex product. My question is - "are there
> any companies offering this service/process in the New England area".
>
> Thanks
>
> Jim Barry
> President & General Mgr.
> StrataFlex, Inc.
> One Wall Street
> Hudson, NH 03051
>
> Phone: (603) 882-1884
> Fax:     (603) 882-1830
> Web: http://www.strataflex.com/
>
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Date:         Mon, 27 Mar 2000 16:22:06 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Moe, Brian" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Moe, Brian" <[log in to unmask]>
Subject:      PWB Testing
MIME-Version: 1.0
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I am trying to establish testing requirements for my factory location.  I
need some help with the following information:

1.  Types of testing  IEC, IPC, etc.
2.  Names of laboratories that can do the testing.

Thank you
Brian Moe

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Date:         Mon, 27 Mar 2000 20:09:49 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: PWB Testing
X-To:         [log in to unmask]
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In a message dated 03/27/2000 6:32:22 PM Central Standard Time,
[log in to unmask] writes:

> I am trying to establish testing requirements for my factory location.  I
>  need some help with the following information:
>
>  1.  Types of testing  IEC, IPC, etc.
>  2.  Names of laboratories that can do the testing.
>
>  Thank you
>  Brian Moe

Hi Brian!

Hate to be a stickler for details, but you've left out just a few things.
Such as:

Where are you? What kind of testing are you looking for? PCB acceptability,
functional testing, MDA, ESS...what?

The gurus on this list might be able to help if you shared just a teeny bit
more detail...

I read the "HBO" in your email address, better make sure these HBO boards
work, I might be a unsatisfied customer one day if they didn't! (just
kidding!)

-Steve Gregory-

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Date:         Mon, 27 Mar 2000 20:37:42 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
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Hi Brian
Bare Board testing and the associated requirements can be found in IPC-6012,
if you have rigid boards; IPC-6013 if you have flex or flex-rigid.

Assembly type requirements can be found in IPC ANSI/J-STD-001.

If you want actual tests (life cycle etc) on assemblies, it is a whole
different subject
and we need to know a lot about your product.

Zero in on which of the above you are interested in and we all will try to
help

Susan Mansilla
Technical Director
Robisan Lab

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Date:         Tue, 28 Mar 2000 08:40:00 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Martin Christie <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Martin Christie <[log in to unmask]>
Subject:      Re: Realiability info: Failure rate with confedence level
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Alan,

Where can we find "Statgraphics"?

Martin Christie

===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
24/03/00 18:05
>Ken,
>There is a great program out called "statgraphics" it has a module which
>is called "forecasting" and it will, given a set of variables, do a
>pretty fair job of determining anticipated failure rates.  It also has
>every type of graphing function you may want.
>
>Regards,
>
>Alan B. Cochrane
>
>
>Ken Patel wrote:
>>
>> Reliability/Quality Guru,
>> I received this question from our engineering department.
>>
>> Currently, they are seeing 1 system crash out of 10 times. They want to
>> improve the crash rate to 1 failure every 30 times with 90% confidence
>> level. They want to know how many operation "X" they will run with no more
>> than "Y" failures with 90% confidence level which will yield 1 failure every
>> 30 times.
>>
>> I do not know how to solve it as haven't practiced it. Am I providing enough
>> information or what information is needed to make a sense out of it? What
>> kind of model it will fit, Poisson, Binomial, etc?
>>
>> Any help will be highly appreciated.
>>
>> re,
>> ken patel
>>
>> ______________________________________________________
>> Ken Patel                       Phone:  (408) 490-6804
>> 1708 McCarthy Blvd.             Fax:    (408) 490-6859
>> Milpitas, CA 95035              Beeper: (888) 769-1808
>>
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Date:         Tue, 28 Mar 2000 10:04:24 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         Lou Hart <[log in to unmask]>
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Lou, Gary

I agree that a single SD limit can be misleading. This is why I put the
sentence in the plural and added the word 'significantly'.

I also understand that, with an Ionograph, it may be difficult to obtain
a true Gaussian curve because of the very nature of its operation adding
bananas to the apples and pears. We had a similar problem with the
dynamic Contaminometer. With an Omega Meter or similar, providing you do
not stop the test before near-asymptote, it would be easier. On the
static Contaminometer or, at least, the better models, we had a system
which, if near-asymptote was not reached within 15 minutes, it
mathematically analysed the resultant curve into its component
exponential curves and then extrapolated them together to infinite time,
thus obtaining the true asymptotic value (as well as giving us a lot
more info by examining the shape of each component and hence the
contaminant type). Each type of board had its own file. By the time we
had ca. 20 results in a file, it approached a normal curve with a
constant process: with 50 results, it was nearly always good
(occasionally with a single maverick -- unexplained -- value). If a
subsequent single value was apparently out-of-tolerance, a vague warning
appeared on the print-out of the individual test. If another one was
out-of-tolerance in the same direction, then the warning was stronger
and a third one stated a probability of the process going wrong. If the
SD widened significantly over a number of tests, then another warning
appeared. So, yes, I believe SPC can be useful, especially if it is
automatic like this.

We had the same algorithms in the dynamic Contaminometer, but they were
less precise because there were more variables in the measurement
process, despite the fact that we automatically had the same base-line
conductivity for all measurements. I believe that this variability was
due to more leaching from the ionics in the laminate which were more
poorly controlled than the soldering/cleaning process. We noted it
especially when changing from batch to batch of a given board,
especially with different makes of laminate but sometimes even with the
same manufacturer but, presumably, different lots.

Brian

Lou Hart wrote:
>
> TechNetters,  (and Brian), I suggest looking into statistical process control techniques for something like this.  A standard Shewart chart would be the thing.  In fact, I plan on doing it myself in the very near future, thanks to Brian's earlier suggestions on cleanliness testing techniques.
>
> If you take 1 standard deviation as a "control limit" you'll have lots of false alarms.  The purpose of SPC is not so much to tell you when to do something, but rather when not to do something, to leave things alone.  A while back, a technetter said he'd made a chart, but found points always inside the limits.  That's exactly the way things you want things to be.  Go to work on something else and don't waste time tinkering with a well-behaved process.  Unless it is producing bad stuff, in which case you need a new process.
> Lou Hart
>
> ----------
> From:   Brian Ellis[SMTP:[log in to unmask]]
> Sent:   Saturday, March 25, 2000 8:12 AM
> To:     [log in to unmask]
> Subject:        Re: [TN] process control of final cleanliness in a no-clean world
>
> Wade
>
> I agree with the others but would add one minor point. Qualify your
> process as "safe" according to your needs. Measure the ionic
> contamination with whatever instrument you will on, say, 20 boards from
> a similar batch, keeping the test going to near-asymptote (say less that
> 1% conductivity change in one minute). Note these final values and
> calculate the mean and standard deviation (ideally, the distribution
> should be a neat bell-curve). For that type of board, run regular tests
> in production: if they fall significantly outside the mean +/- SD
> (either higher or lower), then your process is probably going off the
> rails. Note that a lower reading of contamination may be just as
> dangerous as a higher one, because it signifies a change in the process
> parameters.
>
> Brian
>
> "Oberle, Wade" wrote:
> >
> > Dear technetters,
> >         How do all of you in the no-clean world monitor and control board
> > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter to
> > monitor our 'cleaning' process.  Do some of you still use an ionic
> > contamination tester or do you use SIR testing or nothing or what?
> >
> > Thanks in advance for your advice.
> >
> > Wade Oberle
> >
> > ##############################################################
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>
> --
> Brian Ellis
> Protonique SA
> PO Box 78
> CH-1032 Romanel-sur-Lausanne, Switzerland
> Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> E-mail: [log in to unmask]
> URL: Technical and consultancy divisions:
>        http://www.protonique.com
>      Web services division:
>        http://www.protonique.com/webserv
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Tue, 28 Mar 2000 06:25:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         Gary Camac <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Gary, Assuming that the Ionograph operates on much the same principle as the
Omegameter, I offer this possible answer to your inconsistencies: ARE YOU
SURE THAT YOU HAVE CALCULATED THE "TOTAL" SURFACE AREA CORRECTLY? "TOTAL
SURFACE AREA" MUST INCLUDE NOT ONLY THE SURFACE AREA OF THE BOARD, BUT THE
"TOTAL" SURFACE AREA OF EVERY PART ON THE ASSEMBLY. I RAN TESTS USING THE
SIX BOARD SURFACES AND A GUESSTIMATE OF THE PART SURFACES AND GOT
INCONSISTENT ANSWERS TOO. WHEN THE "TOTAL" SURFACE AREAS OF THE PARTS WAS
REALLY MEASURED AND CALCULATED THE RESULTS BECAME MORE CONSISTENT. It had me
going for a while too.
Hope this thought helps.
Ron Dieselberg
BAE SYSTEMS
Cincinnati Electronics Corp.

-----Original Message-----
From: Gary Camac [mailto:[log in to unmask]]
Sent: Monday, March 27, 2000 16:49
To: [log in to unmask]
Subject: Re: [TN] process control of final cleanliness in a no-clean
world


Good afternoon everyone,

A few years back I used  Ionograph testing to try and prove statistical
control of my in-line washing process.  I was always within the spec limit,
but I could never show a normal distribution.  The data was collected from
tests on all varieties of assemblies: single and double sided through hole,
and single and double sided mixed technology.

Then it dawned on me that I was throwing apples and oranges in the same
crate.  Since the topography of these assemblies are different,  I concluded
that I needed charts for each assembly type.  Hmm....quess again Sherlock.
Once again I could not get a normal distribution.

I could  not come up with any assignable causes to explain the lack of a
normal distribution.  Since I never had any test outside the spec limit, I
had a hard time justifying putting more of my time in the effort.  As you
all know, you have to know when to fish and when to cut bait.

Lou Hart wrote:

> TechNetters,  (and Brian), I suggest looking into statistical process
control techniques for something like this.  A standard Shewart chart would
be the thing.  In fact, I plan on doing it myself in the very near future,
thanks to Brian's earlier suggestions on cleanliness testing techniques.
>
> If you take 1 standard deviation as a "control limit" you'll have lots of
false alarms.  The purpose of SPC is not so much to tell you when to do
something, but rather when not to do something, to leave things alone.  A
while back, a technetter said he'd made a chart, but found points always
inside the limits.  That's exactly the way things you want things to be.  Go
to work on something else and don't waste time tinkering with a well-behaved
process.  Unless it is producing bad stuff, in which case you need a new
process.
> Lou Hart
>
> ----------
> From:   Brian Ellis[SMTP:[log in to unmask]]
> Sent:   Saturday, March 25, 2000 8:12 AM
> To:     [log in to unmask]
> Subject:        Re: [TN] process control of final cleanliness in a
no-clean world
>
> Wade
>
> I agree with the others but would add one minor point. Qualify your
> process as "safe" according to your needs. Measure the ionic
> contamination with whatever instrument you will on, say, 20 boards from
> a similar batch, keeping the test going to near-asymptote (say less that
> 1% conductivity change in one minute). Note these final values and
> calculate the mean and standard deviation (ideally, the distribution
> should be a neat bell-curve). For that type of board, run regular tests
> in production: if they fall significantly outside the mean +/- SD
> (either higher or lower), then your process is probably going off the
> rails. Note that a lower reading of contamination may be just as
> dangerous as a higher one, because it signifies a change in the process
> parameters.
>
> Brian
>
> "Oberle, Wade" wrote:
> >
> > Dear technetters,
> >         How do all of you in the no-clean world monitor and control
board
> > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter
to
> > monitor our 'cleaning' process.  Do some of you still use an ionic
> > contamination tester or do you use SIR testing or nothing or what?
> >
> > Thanks in advance for your advice.
> >
> > Wade Oberle
> >
> > ##############################################################
> > TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
> > ##############################################################
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> > information.
> > If you need assistance - contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > ##############################################################
>
> --
> Brian Ellis
> Protonique SA
> PO Box 78
> CH-1032 Romanel-sur-Lausanne, Switzerland
> Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> E-mail: [log in to unmask]
> URL: Technical and consultancy divisions:
>        http://www.protonique.com
>      Web services division:
>        http://www.protonique.com/webserv
>
> ##############################################################
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Date:         Tue, 28 Mar 2000 08:36:42 -0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jorge Engenharia <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Engenharia <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

    Hello technetters,

   All responses were related with some action involved, but what is =
the
risks related for those people that DO NOTHING ?
   There are a lot of small business that has no capability/knowledge =
to
deal with this and only assembly the board following basics =
manufacturing
process.

    TIA=20
Jorge Dourado de Santana
Maintenance / Process Engr
Microtec - Brazil



> -----Original Message-----
> From: Oberle, Wade [SMTP:[log in to unmask]]
> Sent: 22 de Mar=E7o de 2000 18:13
> To:   [log in to unmask]
> Subject:      [TN] process control of final cleanliness in a no-clean
> world
>=20
> Dear technetters,
>         How do all of you in the no-clean world monitor and control =
board
> cleanliness.  In the days of OA flux, we used an Ionograph or =
Omegameter
> to
> monitor our 'cleaning' process.  Do some of you still use an ionic
> contamination tester or do you use SIR testing or nothing or what?
>=20
> Thanks in advance for your advice.
>=20
> Wade Oberle
>=20
>=20
> ##############################################################
> TechNet Mail List provided as a free service by IPC using LISTSERV =
1.8c
> ##############################################################
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> following text in
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> additional
> information.
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> 847-509-9700 ext.5315
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Date:         Tue, 28 Mar 2000 14:17:14 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         "Dieselberg, Ron" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ron

First thing: Gary and I, in my previous answer, are assuming that we are
talking about a single type of PCB. Secondly, we are talking about
"no-clean" assemblies where 95% of the ionics come from the flux itself
(typically) and thirdly, most of the flux residues will remain on the
board surface and most certainly will not climb onto the top surface of
all the components or even onto the sides.

Your argument is therefore a non-sequitur. If you have n ug/cm2 eq. NaCl
of ionics on the board itself and calculated to the board surface and
this is at what you consider the level of safety, you will be lulled
into a false sense of security by finding you have n/3 or n/4 ug/cm2 eq.
NaCl because your total area with components is 3 or 4 times greater
than without (as can happen). Your board will certainly fail just as
readily.

This business of component area is a total red herring (see my book for
a full discussion) and was introduced initially in MIL-P-28809A as a sop
to assemblers who found that with the specified RMA to MIL-F-14256
fluxes and CFC-113 azeotropes, it was impossible to meet the
requirements of the original 28809 which specified board area alone.
Similarly, in the UK, the initial project of DEF-SPEC 00/10-3 specified
board area only, but as a sop to complainers, they added that this may
be voluntarily weighted to an extra 10% max. to compensate for the
contaminants that do reach the components. About 20 years ago, I took
some cleaned assemblies, snipped off the components and measured the
board and the components separately per cm2 of the board alone area. I
forget the actual figures but I do remember that they averaged about 90%
of the contaminants were on the board and 10% on the components (I think
this was the rationale that the UK Ministry of Defence in Bromley, Kent,
used for their 10% weighting, as I was working very closely with them,
at that time).

So my advice has always been, forget the components totally because any
error in so doing will be fail-safe i.e. the resultant apparent
contamination will be slightly higher in doing so.

Brian

PS BTW, the original 28809A used the word "estimate" of the component
area. The Contaminometer had an automatic means of estimating it, if the
value was required, which was accurate to +/- 10% with ordinary-sized
components, somewhat more with very large ones. I think this feature
still exists in the Multicore version of these instruments, but, as I am
no longer involved with them, I cannot tell for sure.

"Dieselberg, Ron" wrote:
>
> Gary, Assuming that the Ionograph operates on much the same principle as the
> Omegameter, I offer this possible answer to your inconsistencies: ARE YOU
> SURE THAT YOU HAVE CALCULATED THE "TOTAL" SURFACE AREA CORRECTLY? "TOTAL
> SURFACE AREA" MUST INCLUDE NOT ONLY THE SURFACE AREA OF THE BOARD, BUT THE
> "TOTAL" SURFACE AREA OF EVERY PART ON THE ASSEMBLY. I RAN TESTS USING THE
> SIX BOARD SURFACES AND A GUESSTIMATE OF THE PART SURFACES AND GOT
> INCONSISTENT ANSWERS TOO. WHEN THE "TOTAL" SURFACE AREAS OF THE PARTS WAS
> REALLY MEASURED AND CALCULATED THE RESULTS BECAME MORE CONSISTENT. It had me
> going for a while too.
> Hope this thought helps.
> Ron Dieselberg
> BAE SYSTEMS
> Cincinnati Electronics Corp.
>
> -----Original Message-----
> From: Gary Camac [mailto:[log in to unmask]]
> Sent: Monday, March 27, 2000 16:49
> To: [log in to unmask]
> Subject: Re: [TN] process control of final cleanliness in a no-clean
> world
>
> Good afternoon everyone,
>
> A few years back I used  Ionograph testing to try and prove statistical
> control of my in-line washing process.  I was always within the spec limit,
> but I could never show a normal distribution.  The data was collected from
> tests on all varieties of assemblies: single and double sided through hole,
> and single and double sided mixed technology.
>
> Then it dawned on me that I was throwing apples and oranges in the same
> crate.  Since the topography of these assemblies are different,  I concluded
> that I needed charts for each assembly type.  Hmm....quess again Sherlock.
> Once again I could not get a normal distribution.
>
> I could  not come up with any assignable causes to explain the lack of a
> normal distribution.  Since I never had any test outside the spec limit, I
> had a hard time justifying putting more of my time in the effort.  As you
> all know, you have to know when to fish and when to cut bait.
>
> Lou Hart wrote:
>
> > TechNetters,  (and Brian), I suggest looking into statistical process
> control techniques for something like this.  A standard Shewart chart would
> be the thing.  In fact, I plan on doing it myself in the very near future,
> thanks to Brian's earlier suggestions on cleanliness testing techniques.
> >
> > If you take 1 standard deviation as a "control limit" you'll have lots of
> false alarms.  The purpose of SPC is not so much to tell you when to do
> something, but rather when not to do something, to leave things alone.  A
> while back, a technetter said he'd made a chart, but found points always
> inside the limits.  That's exactly the way things you want things to be.  Go
> to work on something else and don't waste time tinkering with a well-behaved
> process.  Unless it is producing bad stuff, in which case you need a new
> process.
> > Lou Hart
> >
> > ----------
> > From:   Brian Ellis[SMTP:[log in to unmask]]
> > Sent:   Saturday, March 25, 2000 8:12 AM
> > To:     [log in to unmask]
> > Subject:        Re: [TN] process control of final cleanliness in a
> no-clean world
> >
> > Wade
> >
> > I agree with the others but would add one minor point. Qualify your
> > process as "safe" according to your needs. Measure the ionic
> > contamination with whatever instrument you will on, say, 20 boards from
> > a similar batch, keeping the test going to near-asymptote (say less that
> > 1% conductivity change in one minute). Note these final values and
> > calculate the mean and standard deviation (ideally, the distribution
> > should be a neat bell-curve). For that type of board, run regular tests
> > in production: if they fall significantly outside the mean +/- SD
> > (either higher or lower), then your process is probably going off the
> > rails. Note that a lower reading of contamination may be just as
> > dangerous as a higher one, because it signifies a change in the process
> > parameters.
> >
> > Brian
> >
> > "Oberle, Wade" wrote:
> > >
> > > Dear technetters,
> > >         How do all of you in the no-clean world monitor and control
> board
> > > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter
> to
> > > monitor our 'cleaning' process.  Do some of you still use an ionic
> > > contamination tester or do you use SIR testing or nothing or what?
> > >
> > > Thanks in advance for your advice.
> > >
> > > Wade Oberle
> > >
> > > ##############################################################
> > > TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
> > > ##############################################################
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> following text in
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> additional
> > > information.
> > > If you need assistance - contact Keach Sasamori at [log in to unmask] or
> > > 847-509-9700 ext.5315
> > > ##############################################################
> >
> > --
> > Brian Ellis
> > Protonique SA
> > PO Box 78
> > CH-1032 Romanel-sur-Lausanne, Switzerland
> > Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> > E-mail: [log in to unmask]
> > URL: Technical and consultancy divisions:
> >        http://www.protonique.com
> >      Web services division:
> >        http://www.protonique.com/webserv
> >
> > ##############################################################
> > TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
> > ##############################################################
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Tue, 28 Mar 2000 14:25:59 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: process control of final cleanliness in a no-clean world
X-To:         Jorge Engenharia <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Jorge

At your risk and peril :-)

A lot depends what you are making. To take the two extremes:
1. You are manufacturing Furbies or similar toys by the 100,000/month. A
failure of 1 or 2 per month is cheaper to replace under guarantee than
to take adequate quality qualification and assurance steps. You would
start to worry only if the failure rate of guarantee replacements
exceeded, say, 100/month.
2. You are manufacturing geostationary satellite telecoms relays where
repair/replacement is quasi-impossible. In this case, if you did not
take adequate measures to qualify and assure your quality, you would be
foolish.

In reality, you are probably somewhere between these extremes. It is
therefore up to you to decide what is an acceptable risk and what is not
and take measures accordingly.

Brian

Jorge Engenharia wrote:
>
>     Hello technetters,
>
>    All responses were related with some action involved, but what is the
> risks related for those people that DO NOTHING ?
>    There are a lot of small business that has no capability/knowledge to
> deal with this and only assembly the board following basics manufacturing
> process.
>
>     TIA
> Jorge Dourado de Santana
> Maintenance / Process Engr
> Microtec - Brazil
>
> > -----Original Message-----
> > From: Oberle, Wade [SMTP:[log in to unmask]]
> > Sent: 22 de Março de 2000 18:13
> > To:   [log in to unmask]
> > Subject:      [TN] process control of final cleanliness in a no-clean
> > world
> >
> > Dear technetters,
> >         How do all of you in the no-clean world monitor and control board
> > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter
> > to
> > monitor our 'cleaning' process.  Do some of you still use an ionic
> > contamination tester or do you use SIR testing or nothing or what?
> >
> > Thanks in advance for your advice.
> >
> > Wade Oberle
> >
> >
> > ##############################################################
> > TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
> > ##############################################################
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> > additional
> > information.
> > If you need assistance - contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
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>
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> information.
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> 847-509-9700 ext.5315
> ##############################################################

--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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=========================================================================
Date:         Tue, 28 Mar 2000 20:52:31 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jonathan A Noquil <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jonathan A Noquil <[log in to unmask]>
Subject:      Re: sputtering
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hello intellectual people out there!



does anybody knows a  company who is doing sputtering on wafers to make the Al
      surface solderable?

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Date:         Mon, 1 Jan 1996 00:08:30 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lou Hart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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John, FYI  from TechNet.  Deals with cleanliness testing when components are on board.  Lou

-----Original Message-----
From:   Brian Ellis [SMTP:[log in to unmask]]
Sent:   Tuesday, March 28, 2000 7:17 AM
To:     [log in to unmask]
Subject:        Re: [TN] process control of final cleanliness in a no-clean world

Ron

First thing: Gary and I, in my previous answer, are assuming that we are
talking about a single type of PCB. Secondly, we are talking about
"no-clean" assemblies where 95% of the ionics come from the flux itself
(typically) and thirdly, most of the flux residues will remain on the
board surface and most certainly will not climb onto the top surface of
all the components or even onto the sides.

Your argument is therefore a non-sequitur. If you have n ug/cm2 eq. NaCl
of ionics on the board itself and calculated to the board surface and
this is at what you consider the level of safety, you will be lulled
into a false sense of security by finding you have n/3 or n/4 ug/cm2 eq.
NaCl because your total area with components is 3 or 4 times greater
than without (as can happen). Your board will certainly fail just as
readily.

This business of component area is a total red herring (see my book for
a full discussion) and was introduced initially in MIL-P-28809A as a sop
to assemblers who found that with the specified RMA to MIL-F-14256
fluxes and CFC-113 azeotropes, it was impossible to meet the
requirements of the original 28809 which specified board area alone.
Similarly, in the UK, the initial project of DEF-SPEC 00/10-3 specified
board area only, but as a sop to complainers, they added that this may
be voluntarily weighted to an extra 10% max. to compensate for the
contaminants that do reach the components. About 20 years ago, I took
some cleaned assemblies, snipped off the components and measured the
board and the components separately per cm2 of the board alone area. I
forget the actual figures but I do remember that they averaged about 90%
of the contaminants were on the board and 10% on the components (I think
this was the rationale that the UK Ministry of Defence in Bromley, Kent,
used for their 10% weighting, as I was working very closely with them,
at that time).

So my advice has always been, forget the components totally because any
error in so doing will be fail-safe i.e. the resultant apparent
contamination will be slightly higher in doing so.

Brian

PS BTW, the original 28809A used the word "estimate" of the component
area. The Contaminometer had an automatic means of estimating it, if the
value was required, which was accurate to +/- 10% with ordinary-sized
components, somewhat more with very large ones. I think this feature
still exists in the Multicore version of these instruments, but, as I am
no longer involved with them, I cannot tell for sure.

"Dieselberg, Ron" wrote:
>
> Gary, Assuming that the Ionograph operates on much the same principle as the
> Omegameter, I offer this possible answer to your inconsistencies: ARE YOU
> SURE THAT YOU HAVE CALCULATED THE "TOTAL" SURFACE AREA CORRECTLY? "TOTAL
> SURFACE AREA" MUST INCLUDE NOT ONLY THE SURFACE AREA OF THE BOARD, BUT THE
> "TOTAL" SURFACE AREA OF EVERY PART ON THE ASSEMBLY. I RAN TESTS USING THE
> SIX BOARD SURFACES AND A GUESSTIMATE OF THE PART SURFACES AND GOT
> INCONSISTENT ANSWERS TOO. WHEN THE "TOTAL" SURFACE AREAS OF THE PARTS WAS
> REALLY MEASURED AND CALCULATED THE RESULTS BECAME MORE CONSISTENT. It had me
> going for a while too.
> Hope this thought helps.
> Ron Dieselberg
> BAE SYSTEMS
> Cincinnati Electronics Corp.
>
> -----Original Message-----
> From: Gary Camac [mailto:[log in to unmask]]
> Sent: Monday, March 27, 2000 16:49
> To: [log in to unmask]
> Subject: Re: [TN] process control of final cleanliness in a no-clean
> world
>
> Good afternoon everyone,
>
> A few years back I used  Ionograph testing to try and prove statistical
> control of my in-line washing process.  I was always within the spec limit,
> but I could never show a normal distribution.  The data was collected from
> tests on all varieties of assemblies: single and double sided through hole,
> and single and double sided mixed technology.
>
> Then it dawned on me that I was throwing apples and oranges in the same
> crate.  Since the topography of these assemblies are different,  I concluded
> that I needed charts for each assembly type.  Hmm....quess again Sherlock.
> Once again I could not get a normal distribution.
>
> I could  not come up with any assignable causes to explain the lack of a
> normal distribution.  Since I never had any test outside the spec limit, I
> had a hard time justifying putting more of my time in the effort.  As you
> all know, you have to know when to fish and when to cut bait.
>
> Lou Hart wrote:
>
> > TechNetters,  (and Brian), I suggest looking into statistical process
> control techniques for something like this.  A standard Shewart chart would
> be the thing.  In fact, I plan on doing it myself in the very near future,
> thanks to Brian's earlier suggestions on cleanliness testing techniques.
> >
> > If you take 1 standard deviation as a "control limit" you'll have lots of
> false alarms.  The purpose of SPC is not so much to tell you when to do
> something, but rather when not to do something, to leave things alone.  A
> while back, a technetter said he'd made a chart, but found points always
> inside the limits.  That's exactly the way things you want things to be.  Go
> to work on something else and don't waste time tinkering with a well-behaved
> process.  Unless it is producing bad stuff, in which case you need a new
> process.
> > Lou Hart
> >
> > ----------
> > From:   Brian Ellis[SMTP:[log in to unmask]]
> > Sent:   Saturday, March 25, 2000 8:12 AM
> > To:     [log in to unmask]
> > Subject:        Re: [TN] process control of final cleanliness in a
> no-clean world
> >
> > Wade
> >
> > I agree with the others but would add one minor point. Qualify your
> > process as "safe" according to your needs. Measure the ionic
> > contamination with whatever instrument you will on, say, 20 boards from
> > a similar batch, keeping the test going to near-asymptote (say less that
> > 1% conductivity change in one minute). Note these final values and
> > calculate the mean and standard deviation (ideally, the distribution
> > should be a neat bell-curve). For that type of board, run regular tests
> > in production: if they fall significantly outside the mean +/- SD
> > (either higher or lower), then your process is probably going off the
> > rails. Note that a lower reading of contamination may be just as
> > dangerous as a higher one, because it signifies a change in the process
> > parameters.
> >
> > Brian
> >
> > "Oberle, Wade" wrote:
> > >
> > > Dear technetters,
> > >         How do all of you in the no-clean world monitor and control
> board
> > > cleanliness.  In the days of OA flux, we used an Ionograph or Omegameter
> to
> > > monitor our 'cleaning' process.  Do some of you still use an ionic
> > > contamination tester or do you use SIR testing or nothing or what?
> > >
> > > Thanks in advance for your advice.
> > >
> > > Wade Oberle
> > >
> > > ##############################################################
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> > > 847-509-9700 ext.5315
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> >
> > --
> > Brian Ellis
> > Protonique SA
> > PO Box 78
> > CH-1032 Romanel-sur-Lausanne, Switzerland
> > Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> > E-mail: [log in to unmask]
> > URL: Technical and consultancy divisions:
> >        http://www.protonique.com
> >      Web services division:
> >        http://www.protonique.com/webserv
> >
> > ##############################################################
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> > information.
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> additional
> > information.
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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=========================================================================
Date:         Tue, 28 Mar 2000 15:54:42 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "d. terstegge" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "d. terstegge" <[log in to unmask]>
Subject:      Flex-rigid with Teflon
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Hi Technetters,

One of our customers has designed a flex-rigid board where the rigid parts =
are made of Rogers 4300, and the flexmaterial is adhesiveless polyimide. =
They will have the board build at a fabhouse that does not have any =
experience with this unusual combination of materials. It seems to me that =
there's quite a bit of risk here....
Although I'm only responsible for assembly, I want my customers project to =
be succesfull. For this reason I'd like to ask this group whether anyone =
has experience with boards like these. All comments are highly appreciated.=


Kind regards

Daan Terstegge
Unclassified mail
Personal website: http://surf.to/smtinfo

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Date:         Mon, 1 Jan 1996 00:40:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lou Hart <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lou Hart <[log in to unmask]>
Subject:      Re: process control of final cleanliness in a no-clean world
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding:  quoted-printable

Hi again, Brian, et al.,

Thanks for further insights into Contaminometer operation.   Nice to =
know that is helps interpret measurements of standard deviation as well, =
that's another critical part of process control.  Understanding the =
measurement process is fundamental in any process control effort.  =
Believe I've said this in the past, but am convinced it's true.

Brian, when you say out-of-tolerance, do you mean out-of-control?  One =
of the things about SPC is that if a process is in good shape, you get =
the warning before anything goes out of tolerance.  If a process is bad, =
you can get out of tolerance but still be in control, in which case the =
process needs to be revamped.  To be precise, I'm thinking about control =
charts for individual measurements.

Which leads to another thought.  Gary, you say the data are not normal.  =
Does this mean, the data taken as individual measurements over a long =
time?  I'm assuming that's the case.  If a process were getting out of =
control, it would not produce normal data.  By the way, how did you =
determine it's not normal?  There are numerous tests for normality in =
statistical literature and in software packages.  And I recall a book by =
Hahn and Shapiro, published in 67, the title of which I forget, which =
had a lot of plots of data randomly drawn from a normal distribution.  =
On the normal probability paper, ideally the plots would have been =
straight lines, but they got some pretty wavy looking things - and these =
from a normal distribution.

Contamination data, strictly speaking, would not follow a normal =
distribution, since the numbers cannot go below 0.  Something I will =
have to be careful about.

If your subgroup data, such as you might get if you measured 5 boards =
from a lot, are not normally distributed, it doesn't make much =
difference since you would plot the means of subgroups on a control =
chart and such means would follow very closely a normal distribution.

And there are transformations that will convert non-normal data to =
normal so you can plot them.  "SPC Methods from Quality Improvement", =
Chapter 9, by Quesenberry, published by Wiley has some discussion. =20

Lou Hart
----------
From:   Brian Ellis[SMTP:[log in to unmask]]
Sent:   Tuesday, March 28, 2000 3:04 AM
To:     [log in to unmask]
Subject:        Re: [TN] process control of final cleanliness in a no-clean =
world

Lou, Gary

I agree that a single SD limit can be misleading. This is why I put the
sentence in the plural and added the word 'significantly'.

I also understand that, with an Ionograph, it may be difficult to obtain
a true Gaussian curve because of the very nature of its operation adding
bananas to the apples and pears. We had a similar problem with the
dynamic Contaminometer. With an Omega Meter or similar, providing you do
not stop the test before near-asymptote, it would be easier. On the
static Contaminometer or, at least, the better models, we had a system
which, if near-asymptote was not reached within 15 minutes, it
mathematically analysed the resultant curve into its component
exponential curves and then extrapolated them together to infinite time,
thus obtaining the true asymptotic value (as well as giving us a lot
more info by examining the shape of each component and hence the
contaminant type). Each type of board had its own file. By the time we
had ca. 20 results in a file, it approached a normal curve with a
constant process: with 50 results, it was nearly always good
(occasionally with a single maverick -- unexplained -- value). If a
subsequent single value was apparently out-of-tolerance, a vague warning
appeared on the print-out of the individual test. If another one was
out-of-tolerance in the same direction, then the warning was stronger
and a third one stated a probability of the process going wrong. If the
SD widened significantly over a number of tests, then another warning
appeared. So, yes, I believe SPC can be useful, especially if it is
automatic like this.

We had the same algorithms in the dynamic Contaminometer, but they were
less precise because there were more variables in the measurement
process, despite the fact that we automatically had the same base-line
conductivity for all measurements. I believe that this variability was
due to more leaching from the ionics in the laminate which were more
poorly controlled than the soldering/cleaning process. We noted it
especially when changing from batch to batch of a given board,
especially with different makes of laminate but sometimes even with the
same manufacturer but, presumably, different lots.

Brian

Lou Hart wrote:
>
> TechNetters,  (and Brian), I suggest looking into statistical process =
control techniques for something like this.  A standard Shewart chart =
would be the thing.  In fact, I plan on doing it myself in the very near =
future, thanks to Brian's earlier suggestions on cleanliness testing =
techniques.
>
> If you take 1 standard deviation as a "control limit" you'll have lots =
of false alarms.  The purpose of SPC is not so much to tell you when to =
do something, but rather when not to do something, to leave things =
alone.  A while back, a technetter said he'd made a chart, but found =
points always inside the limits.  That's exactly the way things you want =
things to be.  Go to work on something else and don't waste time =
tinkering with a well-behaved process.  Unless it is producing bad =
stuff, in which case you need a new process.
> Lou Hart
>
> ----------
> From:   Brian Ellis[SMTP:[log in to unmask]]
> Sent:   Saturday, March 25, 2000 8:12 AM
> To:     [log in to unmask]
> Subject:        Re: [TN] process control of final cleanliness in a =
no-clean world
>
> Wade
>
> I agree with the others but would add one minor point. Qualify your
> process as "safe" according to your needs. Measure the ionic
> contamination with whatever instrument you will on, say, 20 boards =
from
> a similar batch, keeping the test going to near-asymptote (say less =
that
> 1% conductivity change in one minute). Note these final values and
> calculate the mean and standard deviation (ideally, the distribution
> should be a neat bell-curve). For that type of board, run regular =
tests
> in production: if they fall significantly outside the mean +/- SD
> (either higher or lower), then your process is probably going off the
> rails. Note that a lower reading of contamination may be just as
> dangerous as a higher one, because it signifies a change in the =
process
> parameters.
>
> Brian
>
> "Oberle, Wade" wrote:
> >
> > Dear technetters,
> >         How do all of you in the no-clean world monitor and control =
board
> > cleanliness.  In the days of OA flux, we used an Ionograph or =
Omegameter to
> > monitor our 'cleaning' process.  Do some of you still use an ionic
> > contamination tester or do you use SIR testing or nothing or what?
> >
> > Thanks in advance for your advice.
> >
> > Wade Oberle
> >
> > ##############################################################
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1.8c
> > ##############################################################
> > To subscribe/unsubscribe, send a message to [log in to unmask] with =
following text in
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additional
> > information.
> > If you need assistance - contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > ##############################################################
>
> --
> Brian Ellis
> Protonique SA
> PO Box 78
> CH-1032 Romanel-sur-Lausanne, Switzerland
> Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> E-mail: [log in to unmask]
> URL: Technical and consultancy divisions:
>        http://www.protonique.com
>      Web services division:
>        http://www.protonique.com/webserv
>
> ##############################################################
> TechNet Mail List provided as a free service by IPC using LISTSERV =
1.8c
> ##############################################################
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following text in
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additional
> information.
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> 847-509-9700 ext.5315
> ##############################################################
>
> ##############################################################
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1.8c
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additional
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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=========================================================================
Date:         Tue, 28 Mar 2000 10:17:51 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jerry Cupples <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jerry Cupples <[log in to unmask]>
Subject:      Re: sputtering
X-To:         Jonathan A Noquil <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

At 08:52 PM 3/28/00 +0800, you wrote:

>Hello intellectual people out there!
>
>
>
>does anybody knows a  company who is doing sputtering on wafers to make the Al
>       surface solderable?

I will ignore the potential risk of being deemed intellectual, and say this:

Mostek did this years ago with Ti-W co-sputtered, phasing to Cu using a multiple target sputtering setup. See US Patent 4,685,998 (at least intellectual property is mentioned).

We did this in the lab with MRC equipment, and in quasi-production with a Perkin-Elmer system. I'd suggest that you contact the equipment manufacturers, and inquire if they know of someone who uses their machines on a contract basis.

In the Dallas area, way back 17 years, there were a few small operations who would do small jobs, they were mainly in the business of putting harder surfaces on aircraft parts.

I hope this helps.


cheers,

Jerry Cupples
Interphase Corporation

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Date:         Tue, 28 Mar 2000 09:21:03 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Mark M. Lettang" <[log in to unmask]>
Subject:      adhesiveless vs. 3-layer flex (i.e. with adhesive layer)
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hello,

I'm looking for resources (especially journal articles and publications) which
compare/contrast standard 3-layer flex circuits (i.e. where an adhesive layer
bonds a metal foil layer to a substrate such as polyimide) to adhesiveless flex
(i.e. where the metal layer is sputtered or vacuum deposited to the substrate
without the use of an adhesive).

In particular, I'm interested in what product or application requirements would
tend to steer one towards one of these construction vs. the other.

Thanks in advance!

Mark Lettang
[log in to unmask]

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Date:         Tue, 28 Mar 2000 10:38:17 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Silver Embrittlement
X-To:         [log in to unmask]
MIME-Version: 1.0
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Hi Steve,
My comment has nothing to do with Ag-containing solders, but with the effect=
=20
of Ag-plating on component leads. Immersion Ag may be thin enough not to giv=
e=20
you the necessary Ag concentration.
The experience I referred to goes back to about 1982. The industry found=20
out=97and since forgot except for a few old-timers like me=97what silver can=
 do=20
to solder joints, when TI moved some of its PLCC production to Singapore.=20
There somebody decided to Ag-plate the leads. At the first unfortunate=20
recipient of this product, IBM-Austin, the PLCCs started to literally fall=20
off the PCBs when slight bending, such during fixturing for functional=20
testing, put even very small loads onto the solder joints. As a consequence=20
of this scary news (nobody knew about the Ag yet and compliant leads were=20
just invented and without history), 17 competing companies joined forces and=
=20
formed the IEEE Compliant Lead Task Force. =20
Silver, it turns out creates an even weaker intermetallic compound (IMC) wit=
h=20
tin than does gold. The necessary IMC concentration necessary for this effec=
t=20
is about the same as for Au.=20
Because of legal problems (the 2 companies with the lowest PLCC fatigue live=
s=20
threatened to sue everybody involved in the IEEE CLTF), the results, except=20
for some preliminary data, were never published.
If you go back into the TechNet archives, you will find some problems relate=
d=20
to Ag (plating) being discussed.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com=20

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Date:         Tue, 28 Mar 2000 07:54:05 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Tuan Le <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tuan Le <[log in to unmask]>
Subject:      Re: Realiability info: Failure rate with confedence level
X-To:         Martin Christie <[log in to unmask]>
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You can download a demo from www.statgraphics.com

Regards,

Tuan Le

-----Original Message-----
From: Martin Christie [mailto:[log in to unmask]]
Sent: Monday, March 27, 2000 11:40 PM
To: [log in to unmask]
Subject: Re: [TN] Realiability info: Failure rate with confedence level


Alan,

Where can we find "Statgraphics"?

Martin Christie

===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
24/03/00 18:05
>Ken,
>There is a great program out called "statgraphics" it has a module which
>is called "forecasting" and it will, given a set of variables, do a
>pretty fair job of determining anticipated failure rates.  It also has
>every type of graphing function you may want.
>
>Regards,
>
>Alan B. Cochrane
>
>
>Ken Patel wrote:
>>
>> Reliability/Quality Guru,
>> I received this question from our engineering department.
>>
>> Currently, they are seeing 1 system crash out of 10 times. They want to
>> improve the crash rate to 1 failure every 30 times with 90% confidence
>> level. They want to know how many operation "X" they will run with no
more
>> than "Y" failures with 90% confidence level which will yield 1 failure
every
>> 30 times.
>>
>> I do not know how to solve it as haven't practiced it. Am I providing
enough
>> information or what information is needed to make a sense out of it? What
>> kind of model it will fit, Poisson, Binomial, etc?
>>
>> Any help will be highly appreciated.
>>
>> re,
>> ken patel
>>
>> ______________________________________________________
>> Ken Patel                       Phone:  (408) 490-6804
>> 1708 McCarthy Blvd.             Fax:    (408) 490-6859
>> Milpitas, CA 95035              Beeper: (888) 769-1808
>>
>> ##############################################################
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<P><FONT SIZE=3D2>You can download a demo from =
www.statgraphics.com</FONT>
</P>

<P><FONT SIZE=3D2>Regards,</FONT>
</P>

<P><FONT SIZE=3D2>Tuan Le</FONT>
</P>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Martin Christie [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Monday, March 27, 2000 11:40 PM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [TN] Realiability info: Failure rate =
with confedence level</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Alan,</FONT>
</P>

<P><FONT SIZE=3D2>Where can we find &quot;Statgraphics&quot;?</FONT>
</P>

<P><FONT SIZE=3D2>Martin Christie</FONT>
</P>

<P><FONT SIZE=3D2>=3D=3D=3D=3D=3D Original Message from [log in to unmask] =
(TechNet E-Mail Forum.) at</FONT>
<BR><FONT SIZE=3D2>24/03/00 18:05</FONT>
<BR><FONT SIZE=3D2>&gt;Ken,</FONT>
<BR><FONT SIZE=3D2>&gt;There is a great program out called =
&quot;statgraphics&quot; it has a module which</FONT>
<BR><FONT SIZE=3D2>&gt;is called &quot;forecasting&quot; and it will, =
given a set of variables, do a</FONT>
<BR><FONT SIZE=3D2>&gt;pretty fair job of determining anticipated =
failure rates.&nbsp; It also has</FONT>
<BR><FONT SIZE=3D2>&gt;every type of graphing function you may =
want.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;Regards,</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;Alan B. Cochrane</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;Ken Patel wrote:</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; Reliability/Quality Guru,</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; I received this question from our =
engineering department.</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; Currently, they are seeing 1 system crash =
out of 10 times. They want to</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; improve the crash rate to 1 failure every =
30 times with 90% confidence</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; level. They want to know how many operation =
&quot;X&quot; they will run with no more</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; than &quot;Y&quot; failures with 90% =
confidence level which will yield 1 failure every</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; 30 times.</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; I do not know how to solve it as haven't =
practiced it. Am I providing enough</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; information or what information is needed =
to make a sense out of it? What</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; kind of model it will fit, Poisson, =
Binomial, etc?</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; Any help will be highly appreciated.</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; re,</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; ken patel</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; =
______________________________________________________</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; Ken =
Patel&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Phone:&nbsp; (408) 490-6804</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; 1708 McCarthy =
Blvd.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp; Fax:&nbsp;&nbsp;&nbsp; (408) 490-6859</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; Milpitas, CA =
95035&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp; Beeper: (888) 769-1808</FONT>
<BR><FONT SIZE=3D2>&gt;&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&gt; =
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Date:         Tue, 28 Mar 2000 12:58:52 -0400
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Eric Yakobson <[log in to unmask]>
Subject:      Re: Silver Embrittlement
X-To:         Werner Engelmaier <[log in to unmask]>
X-cc:         [log in to unmask]
Mime-Version: 1.0
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              Boundary="0__=3vNZqtSPi6yByRKirX1FiDxO9crAdfVKjZ15oZC40tEOZ79gxeP5gnP5"

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Werner,

We had this argument awhile back.  The original question was about immersion
finishes -- tin and silver.  Your warning was about (orders of magnitude
thicker) electroplated deposits on lead frames..........?!

Secondly, if silver IMC concentration is the same as for gold, how do people use
2 -- 5% silver-containing alloys?


Eric Yakobson




Werner Engelmaier <[log in to unmask]> on 03/28/2000 07:38:17 AM

To:   [log in to unmask]
cc:
Subject:  Re: [TN] Silver Embrittlement



Hi Steve,
My comment has nothing to do with Ag-containing solders, but with the effect
of Ag-plating on component leads. Immersion Ag may be thin enough not to give
you the necessary Ag concentration.
The experience I referred to goes back to about 1982. The industry found
out
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Content-type: text/plain; charset=iso-8859-1
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=F9and since forgot except for a few old-timers like me=

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Content-type: text/plain; charset=us-ascii
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--0__=3vNZqtSPi6yByRKirX1FiDxO9crAdfVKjZ15oZC40tEOZ79gxeP5gnP5
Content-type: text/plain; charset=iso-8859-1
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=F9what silver can do
to solder joints, when TI moved some of its PLCC production to Singapor=
e.
There somebody decided to Ag-plate the leads. At the first unfortunate
recipient of this product, IBM-Austin, the PLCCs started to literally f=
all
off the PCBs when slight bending, such during fixturing for functional
testing, put even very small loads onto the solder joints. As a consequ=
ence
of this scary news (nobody knew about the Ag yet and compliant leads we=
re
just invented and without history), 17 competing companies joined force=
s and
formed the IEEE Compliant Lead Task Force.
Silver, it turns out creates an even weaker intermetallic compound (IMC=
) with
tin than does gold. The necessary IMC concentration necessary for this =
effect
is about the same as for Au.
Because of legal problems (the 2 companies with the lowest PLCC fatigue=
 lives
threatened to sue everybody involved in the IEEE CLTF), the results, ex=
cept
for some preliminary data, were never published.
If you go back into the TechNet archives, you will find some problems r=
elated
to Ag (plating) being discussed.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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=

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Date:         Tue, 28 Mar 2000 10:16:39 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Eric Kalgren <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Eric Kalgren <[log in to unmask]>
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Mime-Version: 1.0
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Hey all!

I am currently working on my Senior Design project for my EE degree. =20

Without going into too many of the details, I was wondering if anyone can =
answer the following question:

Does a socket-type device exist that will convert an QFP to a PGA?

We are working on a custom VXI interface for BFGoodrich and our sponsor =
engineer wants us to look for PGAs so that we can build a prototype on a =
wire wranp board and avoid having a PCB built (at least in this stage of =
the game).

Thanks!



Eric Kalgren
BFGoodrich Aerospace
Space Flight Systems
[log in to unmask]
(505) 938-5139

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Date:         Tue, 28 Mar 2000 11:10:10 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Flex
MIME-Version: 1.0
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I need some enlightenment/help. IPC-A-600F Section 4.1.7 addresses
solder wicking under the coverlay of flex circuits. The paragraph at the
top states migration does not extend into the bend or flex transition
area. Would this be the area where your measurements for acceptability
begin or does the measurement start at the clearance in the coverlay? No
one at IPC can answer this and they are waiting for their expert, Don
Dupriest (Lockheed) to return their call. Don if you are out there
please call me (505)345-5591 X3064.
Thanks in advance,
Rick Howieson
GTC

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Date:         Tue, 28 Mar 2000 10:22:33 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: Chip packaging question
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

some years ago, for prototyping a design, we designed adapter boards that interfaced qfp's to pga patterns.  the qfp's were soldered to the adapter board which also had pins soldered to it.  this assembly was then plugged into sockets on a wirewrap board.  they were pretty simple, inexpensive designs.

if you have trouble finding the exact combination of pga pattern to w/w board pattern, this would be the way to go.

phil



-----Original Message-----
From: Eric Kalgren [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 9:17 AM
To: [log in to unmask]
Subject: [TN] Chip packaging question


Hey all!

I am currently working on my Senior Design project for my EE degree.

Without going into too many of the details, I was wondering if anyone can answer the following question:

Does a socket-type device exist that will convert an QFP to a PGA?

We are working on a custom VXI interface for BFGoodrich and our sponsor engineer wants us to look for PGAs so that we can build a prototype on a wire wranp board and avoid having a PCB built (at least in this stage of the game).

Thanks!



Eric Kalgren
BFGoodrich Aerospace
Space Flight Systems
[log in to unmask]
(505) 938-5139

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Date:         Tue, 28 Mar 2000 10:26:31 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Patel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Patel <[log in to unmask]>
Subject:      Solderability of TSOP...
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Guys,
We have encountered problem related to component solderability, looks like!
We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
part has very small foot area which make a direct contact with the pad on
the boards.

The problem we have encountered is that many boards fail at ICT but will
pass once we touch it up using solder iron. Solder at the TSOP location
looks good and also in the surrounding vicinity. I do not see any profile
problem. There is no toe fillet but I can see the heel filet rising on the
lead. Pads are designed longer so that parts made by others can fit too.

What can be possible causes of the problem? I tried look at the WEB but
looks like parts are made using eutectic solder and not Alloy 42 but can't
ruled out it was not specifically mentioned.


re,
ken patel
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Tue, 28 Mar 2000 13:32:32 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Subject:      Re: Chip packaging question
X-To:         Eric Kalgren <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Eric,

Yeah, I did this about a year ago when we basically "Socketed" a QFP (25 mil
pitch 132 pin QFP), so that we could test various copies of firmware. I
believe the company that has a line of this type of adapters was Ironwood
Electronics in St. Paul, Minnesota. They can be reached at 651-452-8100. I
think they have a website at www.ironwoodelectronics.com.

Good Luck,

Bill Kasprzak
Moog Inc.

> -----Original Message-----
> From: Eric Kalgren [SMTP:[log in to unmask]]
> Sent: Tuesday, March 28, 2000 12:17 PM
> To:   [log in to unmask]
> Subject:      [TN] Chip packaging question
>
> Hey all!
>
> I am currently working on my Senior Design project for my EE degree.
>
> Without going into too many of the details, I was wondering if anyone can
> answer the following question:
>
> Does a socket-type device exist that will convert an QFP to a PGA?
>
> We are working on a custom VXI interface for BFGoodrich and our sponsor
> engineer wants us to look for PGAs so that we can build a prototype on a
> wire wranp board and avoid having a PCB built (at least in this stage of
> the game).
>
> Thanks!
>
>
>
> Eric Kalgren
> BFGoodrich Aerospace
> Space Flight Systems
> [log in to unmask]
> (505) 938-5139
>
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Date:         Tue, 28 Mar 2000 13:33:03 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cyker, Howard A (Howie)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cyker, Howard A (Howie)" <[log in to unmask]>
Subject:      Re: Chip packaging question
X-To:         Eric Kalgren <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Try:

Advanced Interconnections
5 Energy Way
P.O. Box 1019
West Warwick, RI  02893
1-800-424-9850
www.advintcorp.com

> Howard A. Cyker
> Lucent Technologies
> Email [log in to unmask]
> Phone 978-960-2964
> Fax 978-960-1187
>
>
> ----------
> From:         Eric Kalgren[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Eric Kalgren
> Sent:         Tuesday, March 28, 2000 12:16 PM
> To:   [log in to unmask]
> Subject:      [TN] Chip packaging question
>
> Hey all!
>
> I am currently working on my Senior Design project for my EE degree.
>
> Without going into too many of the details, I was wondering if anyone can
> answer the following question:
>
> Does a socket-type device exist that will convert an QFP to a PGA?
>
> We are working on a custom VXI interface for BFGoodrich and our sponsor
> engineer wants us to look for PGAs so that we can build a prototype on a
> wire wranp board and avoid having a PCB built (at least in this stage of
> the game).
>
> Thanks!
>
>
>
> Eric Kalgren
> BFGoodrich Aerospace
> Space Flight Systems
> [log in to unmask]
> (505) 938-5139
>
> ##############################################################
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Date:         Tue, 28 Mar 2000 14:07:44 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Anne Ledger <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Anne Ledger <[log in to unmask]>
Subject:      Controlled Impedance Testing
MIME-Version: 1.0
Content-Type: text/plain

TechNet,

Does anyone have a list of companies that
provide controlled impedance testing as a service?
We have an immediate need.  Thanks in advance
for any input.

Anne Ledger
EMDS, Inc.

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Date:         Tue, 28 Mar 2000 14:13:50 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      Re: Chip packaging question
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

In a message dated 03/28/2000 11:22:00 AM Central Standard Time,
[log in to unmask] writes:

<< Hey all!

 I am currently working on my Senior Design project for my EE degree.

 Without going into too many of the details, I was wondering if anyone can
answer the following question:

 Does a socket-type device exist that will convert an QFP to a PGA?

 We are working on a custom VXI interface for BFGoodrich and our sponsor
engineer wants us to look for PGAs so that we can build a prototype on a wire
wranp board and avoid having a PCB built (at least in this stage of the game).

 Thanks!>>

Hi Eric!

Go to:

http://www.adapters.com/catalog/catalog_f.pdf
or
http://www.arieselec.com/products/correct.htm
or
http://www.adapter-tech.com/prod03.htm

-Steve Gregory-

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Date:         Tue, 28 Mar 2000 14:19:19 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bev Christian <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: Solderability of TSOP...
X-To:         Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Ken,
First I don't think you really mean to say the part leads are made with
eutectic solder or Alloy 42.  The leads are either Alloy 42 or copper, with
a lead finish of eutectic solder, other tin/lead solder alloy or maybe even
TI palladium.

So you have sufficient pads size for good fillets, good soldering of other
parts, good profile and heel fillets.  Hmmm.  My question would then be, do
the failures look like the lead has pulled right out of the fillet, with
bare lead frame material showing.  If this is the case and the leads are
indeed Alloy 42, then this has been seen before, is related to the final
processing of the Alloy 42 and I think has been discussed here on TechNet.
Check the archives.

regards,
Bev Christian
XLTEK

-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: March 28, 2000 1:27 PM
To: [log in to unmask]
Subject: [TN] Solderability of TSOP...


Guys,
We have encountered problem related to component solderability, looks like!
We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
part has very small foot area which make a direct contact with the pad on
the boards.

The problem we have encountered is that many boards fail at ICT but will
pass once we touch it up using solder iron. Solder at the TSOP location
looks good and also in the surrounding vicinity. I do not see any profile
problem. There is no toe fillet but I can see the heel filet rising on the
lead. Pads are designed longer so that parts made by others can fit too.

What can be possible causes of the problem? I tried look at the WEB but
looks like parts are made using eutectic solder and not Alloy 42 but can't
ruled out it was not specifically mentioned.


re,
ken patel
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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=========================================================================
Date:         Tue, 28 Mar 2000 20:24:35 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Subject:      Re: Flex-rigid with Teflon
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1252"

Hi Daan,

Check out the Rogers Corp. website http://www.rogers-corp.com/cmu/index.htm

It has a lot of interesting info although a quick search didn't turn up
4300.  I'd strongly recommend talking to one of their Applications Engineers
- they have decades of experience to draw from.

Hans

~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Materials (Process & Manufacturing) Engineer
Warner Robins Air Logistics Center
Avionics Production Division
Manufacturing Branch
380 Second Street, Suite 104
Building: 640, Mail Stop: LYPME
Robins AFB, GA 31098-1638
Voice: (912) 926 - 1970 Fax: (912) 926 - 7164
mailto:[log in to unmask]
http://www.robins.af.mil

-----Original Message-----
From: d. terstegge [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 8:55 AM
To: [log in to unmask]
Subject: [TN] Flex-rigid with Teflon


Hi Technetters,

One of our customers has designed a flex-rigid board where the rigid parts
are made of Rogers 4300, and the flexmaterial is adhesiveless polyimide.
They will have the board build at a fabhouse that does not have any
experience with this unusual combination of materials. It seems to me that
there's quite a bit of risk here....
Although I'm only responsible for assembly, I want my customers project to
be succesfull. For this reason I'd like to ask this group whether anyone has
experience with boards like these. All comments are highly appreciated.

Kind regards

Daan Terstegge
Unclassified mail
Personal website: http://surf.to/smtinfo

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Date:         Tue, 28 Mar 2000 11:30:48 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Regis Froats <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Regis Froats <[log in to unmask]>
Subject:      Re: Controlled Impedance Testing
X-To:         Anne Ledger <[log in to unmask]>
In-Reply-To:  <E3F39BDE675ED31192CE00508B2C8CAB05DC9B@POSTMASTER2>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Try www.introbotics.com.  They're in Albuquerque, NM  Ph. 505.345.7785

At 14:07 03/28/2000 -0500, you wrote:
>TechNet,
>
>Does anyone have a list of companies that
>provide controlled impedance testing as a service?
>We have an immediate need.  Thanks in advance
>for any input.
>
>Anne Ledger
>EMDS, Inc.
>
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--
Regis Froats <[log in to unmask]>
Process Engineer - Herco Technology Corp.
13330 Evening Creek Drive North
San Diego, Ca. 92128
Pho:858.679.2800 - Fax:858.679.7565

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Date:         Tue, 28 Mar 2000 14:26:42 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bev Christian <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      REQUEST FOR SOLDER BALL INFO
X-cc:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

TechNet,
Ross Berntson of Indium and myself have volunteered, as members of the IPC
Solder Paste Task Group, to take another look at the solder ball test for
the handbook the group is working on.  So we do not re-invent the wheel, I
was wondering if some of you "older" members of our fraternity could point
us in the direction of articles, papers, etc. we should peruse so we do not
reinvent the wheel.  Thanks for your help!

regards,
Bev Christian
Director of Electronics Manufacturing
XLTEK
2568 Bristol Circle,
Oakville, Ontario
Canada   L6H 5S1
1-800-387-7516

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Date:         Tue, 28 Mar 2000 13:54:47 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Wilber Heath <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Wilber Heath <[log in to unmask]>
Subject:      ESD for Schematics
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII

We are currently trying to get all of our paperwork used on the
production floor into some type of static dissapative bags to prevent
static charges. As we use a lot of schematics that are printed as
large
as 'E' size, it has been difficult to find ESD envelopes of this size
to
put the schemartics into. We have thought of some kind of protective
lamination, but I have yet to find anything available to do this with.
Another thought I had was to use deionizing fans, but am not sure if
this would suffice. Does anyone out there have any ideas or things
that
you have used that solves this dilemma??

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Date:         Tue, 28 Mar 2000 21:12:20 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Hinners Hans Civ WRALC/LYPME <[log in to unmask]>
Subject:      Re: sputtering
X-To:         Jonathan A Noquil <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1252"
Content-Transfer-Encoding: quoted-printable

Hi Jonathan and Tech Net,

You mean Si wafers right?

Check with http://www.semiconductor.net
Semiconductor International magazine's website.

And also check out this 1997 Applied Materials press release.

APPLIED MATERIALS ANNOUNCES ADVANCEMENT IN ALUMINUM PLANARIZATION =
TECHNOLOGY

New Aluminum Low Pressure Seed (ALPS=99) Chamber Enables =
Cost-Effective, High
Performance Via Fill for 0.25 micron Memory Devices=20

http://www.appliedmaterials.com/newsroom/pr-00099.html

Hans

~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Materials (Process & Manufacturing) Engineer
Warner Robins Air Logistics Center
Avionics Production Division
Manufacturing Branch
380 Second Street, Suite 104
Building: 640, Mail Stop: LYPME
Robins AFB, GA 31098-1638
Voice: (912) 926 - 1970 Fax: (912) 926 - 7164
mailto:[log in to unmask]
http://www.robins.af.mil


-----Original Message-----
From: Jonathan A Noquil [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 7:53 AM
To: [log in to unmask]
Subject: Re: [TN] sputtering


Hello intellectual people out there!



does anybody knows a  company who is doing sputtering on wafers to make =
the
Al
      surface solderable?

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Date:         Tue, 28 Mar 2000 15:04:11 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Thorup, John" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Thorup, John" <[log in to unmask]>
Subject:      Re: ESD for Schematics
X-To:         Wilber Heath <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

I think the issue here is that you want to get your shop traveler slips into
dissipative carriers and your work instructions into static dissipative
binders and such.  The goal would be to protect the work in progress from
these plastic carriers, not the paper inside.  As a rule paper is not a
problem unless it is laminated, lacquered or has some other (usually glossy)
coating on it.  Paper, being naturally hygroscopic, will absorb humidity
from the air, be somewhat dissapative and will not normally will not
generate or hold a charge ( does not apply to Tyvek and other synthetics).
Try to charge up a piece of paper and check it with one of those small, hand
held, static field meters.
John Thorup


> -----Original Message-----
> From: Wilber Heath [SMTP:[log in to unmask]]
> Sent: Tuesday, March 28, 2000 11:55 AM
> To:   [log in to unmask]
> Subject:      [TN] ESD for Schematics
>
>  We are currently trying to get all of our paperwork used on the
> production floor into some type of static dissapative bags to prevent
> static charges. As we use a lot of schematics that are printed as
> large
> as 'E' size, it has been difficult to find ESD envelopes of this size
> to
> put the schemartics into. We have thought of some kind of protective
> lamination, but I have yet to find anything available to do this with.
> Another thought I had was to use deionizing fans, but am not sure if
> this would suffice. Does anyone out there have any ideas or things
> that
> you have used that solves this dilemma??
>
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Date:         Tue, 28 Mar 2000 15:25:20 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Patel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Patel <[log in to unmask]>
Subject:      Re: Solderability of TSOP...
X-To:         Bev Christian <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Bev,
You are right in catching and educating me on Alloy 42, lead material v/s
plating. As the data sheet doesn't show the lead material & plating for 44
pin TSOP, I have assumed that the plating will be same as 32 pin TSOP which
is copper leads.

We do not see any failure visually using regular microscope, it's a big
problem for us on this thin TSOP. If any of our technetters has found
similar situation and how it was resolved will help us in getting at the
bottom of the problem. I have asked Cypress for lead related info with type
of plating and will ask our test guy if they can nail it down to particular
pin for further microscopic inspection.

re,
ken patel

At 02:19 PM 3/28/2000 -0500, Bev Christian wrote:
>Ken,
>First I don't think you really mean to say the part leads are made with
>eutectic solder or Alloy 42.  The leads are either Alloy 42 or copper, with
>a lead finish of eutectic solder, other tin/lead solder alloy or maybe even
>TI palladium.
>
>So you have sufficient pads size for good fillets, good soldering of other
>parts, good profile and heel fillets.  Hmmm.  My question would then be, do
>the failures look like the lead has pulled right out of the fillet, with
>bare lead frame material showing.  If this is the case and the leads are
>indeed Alloy 42, then this has been seen before, is related to the final
>processing of the Alloy 42 and I think has been discussed here on TechNet.
>Check the archives.
>
>regards,
>Bev Christian
>XLTEK
>
>-----Original Message-----
>From: Ken Patel [mailto:[log in to unmask]]
>Sent: March 28, 2000 1:27 PM
>To: [log in to unmask]
>Subject: [TN] Solderability of TSOP...
>
>
>Guys,
>We have encountered problem related to component solderability, looks like!
>We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
>part has very small foot area which make a direct contact with the pad on
>the boards.
>
>The problem we have encountered is that many boards fail at ICT but will
>pass once we touch it up using solder iron. Solder at the TSOP location
>looks good and also in the surrounding vicinity. I do not see any profile
>problem. There is no toe fillet but I can see the heel filet rising on the
>lead. Pads are designed longer so that parts made by others can fit too.
>
>What can be possible causes of the problem? I tried look at the WEB but
>looks like parts are made using eutectic solder and not Alloy 42 but can't
>ruled out it was not specifically mentioned.
>
>
>re,
>ken patel
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
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>
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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=========================================================================
Date:         Wed, 29 Mar 2000 07:48:17 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jonathan A Noquil <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jonathan A Noquil <[log in to unmask]>
Subject:      Re: SnCu , SnCuAg or SnAg Plating
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hello TechNetters,

      Does anybody knows any company doing SnCu, SnCuAg or SnAg plating?

Can we vary the alloy concentration? Can we achieve plating finish for this
      alloys that can stand of at least 300 Deg Temperature?



Appreciate your help very much



Salamat kaayo

Jonathan

Fairchild semiconductor

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Date:         Tue, 28 Mar 2000 16:24:39 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: Solderability of TSOP...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

you should try to gently move each lead, side-to-side, with a fine needle.  this should find any fractured solder joint that your microscope may overlook.

phil

-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 3:25 PM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


Bev,
You are right in catching and educating me on Alloy 42, lead material v/s
plating. As the data sheet doesn't show the lead material & plating for 44
pin TSOP, I have assumed that the plating will be same as 32 pin TSOP which
is copper leads.

We do not see any failure visually using regular microscope, it's a big
problem for us on this thin TSOP. If any of our technetters has found
similar situation and how it was resolved will help us in getting at the
bottom of the problem. I have asked Cypress for lead related info with type
of plating and will ask our test guy if they can nail it down to particular
pin for further microscopic inspection.

re,
ken patel

At 02:19 PM 3/28/2000 -0500, Bev Christian wrote:
>Ken,
>First I don't think you really mean to say the part leads are made with
>eutectic solder or Alloy 42.  The leads are either Alloy 42 or copper, with
>a lead finish of eutectic solder, other tin/lead solder alloy or maybe even
>TI palladium.
>
>So you have sufficient pads size for good fillets, good soldering of other
>parts, good profile and heel fillets.  Hmmm.  My question would then be, do
>the failures look like the lead has pulled right out of the fillet, with
>bare lead frame material showing.  If this is the case and the leads are
>indeed Alloy 42, then this has been seen before, is related to the final
>processing of the Alloy 42 and I think has been discussed here on TechNet.
>Check the archives.
>
>regards,
>Bev Christian
>XLTEK
>
>-----Original Message-----
>From: Ken Patel [mailto:[log in to unmask]]
>Sent: March 28, 2000 1:27 PM
>To: [log in to unmask]
>Subject: [TN] Solderability of TSOP...
>
>
>Guys,
>We have encountered problem related to component solderability, looks like!
>We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
>part has very small foot area which make a direct contact with the pad on
>the boards.
>
>The problem we have encountered is that many boards fail at ICT but will
>pass once we touch it up using solder iron. Solder at the TSOP location
>looks good and also in the surrounding vicinity. I do not see any profile
>problem. There is no toe fillet but I can see the heel filet rising on the
>lead. Pads are designed longer so that parts made by others can fit too.
>
>What can be possible causes of the problem? I tried look at the WEB but
>looks like parts are made using eutectic solder and not Alloy 42 but can't
>ruled out it was not specifically mentioned.
>
>
>re,
>ken patel
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
>##############################################################
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>
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Tue, 28 Mar 2000 16:57:03 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jack Petyak <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jack Petyak <[log in to unmask]>
Subject:      Plating processes
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Anyone have any input about how to analyze carriers
and brighteners in plating baths? What about potential
problems with gold plating?

I'll probably have more plating process questions as I
get deeper into my project so if the experts can offer
any advice I'd appreciate any help.

Thanks, Jack

__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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Date:         Tue, 28 Mar 2000 22:04:41 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Edward J. Valentine" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Edward J. Valentine" <[log in to unmask]>
Subject:      Re: ESD for Schematics
X-To:         Wilber Heath <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Wilber -

I'm not trying to be facetious or anything, but I would suggest you try
using a smaller format for documentation to your production floor.  B size
is about the biggest you can easily handle say at a workbench, lets say for
troubleshooting (A size is preferred).  C size can be used with some
difficulty, but D and E size are really awkward.

If you want to get really large ESD bags, try Static Control Components in
Sanford, NC at (800) 488-2426.  They can make custom sizes in addition to
standard sizes.  If you have any problems, please feel free to contact me
off TechNet.

Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask]
Website: http://www.ems-consulting.com

----- Original Message -----
From: Wilber Heath <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 28, 2000 2:54 PM
Subject: [TN] ESD for Schematics


> We are currently trying to get all of our paperwork used on the
> production floor into some type of static dissapative bags to prevent
> static charges. As we use a lot of schematics that are printed as
> large
> as 'E' size, it has been difficult to find ESD envelopes of this size
> to
> put the schemartics into. We have thought of some kind of protective
> lamination, but I have yet to find anything available to do this with.
> Another thought I had was to use deionizing fans, but am not sure if
> this would suffice. Does anyone out there have any ideas or things
> that
> you have used that solves this dilemma??
>
> ##############################################################
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Date:         Wed, 29 Mar 2000 10:39:57 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jonathan A Noquil <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jonathan A Noquil <[log in to unmask]>
Subject:      Re: Plating processes
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Brighteners /carriers concentration can be analyzed by qualiplate CVS (cyclic
voltametric stripping). However for gold plating baths this does not apply.
Usually brighteners in gold plating baths are not being analyzed, they were just
be added in direct proportions with gold content in a bath. So if you know the
gold content, you have the idea how much brightener you will add.]

Hope this helps

Jonathan
Fairchild semiconductor
Package Technology Group








Jack Petyak <[log in to unmask]> on 03/29/2000 08:57:03 AM

Please respond to "\"TechNet E-Mail Forum.\" <[log in to unmask]>,        Jack
      Petyak" <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Jonathan A Noquil/Cebu/Fairchild)
Subject:  [TN] Plating processes




Anyone have any input about how to analyze carriers
and brighteners in plating baths? What about potential
problems with gold plating?

I'll probably have more plating process questions as I
get deeper into my project so if the experts can offer
any advice I'd appreciate any help.

Thanks, Jack

__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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Date:         Wed, 29 Mar 2000 06:42:08 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Dieselberg, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Dieselberg, Ron" <[log in to unmask]>
Subject:      Re: ESD for Schematics
X-To:         "Thorup, John" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I have to somewhat disagree with what you say (no disrespect intended). Even
though paper is somewhat hygroscopic it can still be an ESD danger in the
workplace. Papers are usually moved or shuffled around as they are used and
this "contact and separation" can spell the death knell for sensitive
devices. We use static dissipative protectors on all paper products where
possible. Large drawings, if required, can be photographically reduced or
folded or cut up to fit the dissipative protectors available.
It all depends upon the degree of protection you commit to for your product
and your customer. Many of our products ride on space vehicles and therefore
ESD protection needs to be as good as it can possibly get!
Ron Dieselberg
BAE SYSTEMS
Cincinnati Electronics Corp.

-----Original Message-----
From: Thorup, John [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 18:04
To: [log in to unmask]
Subject: Re: [TN] ESD for Schematics


I think the issue here is that you want to get your shop traveler slips into
dissipative carriers and your work instructions into static dissipative
binders and such.  The goal would be to protect the work in progress from
these plastic carriers, not the paper inside.  As a rule paper is not a
problem unless it is laminated, lacquered or has some other (usually glossy)
coating on it.  Paper, being naturally hygroscopic, will absorb humidity
from the air, be somewhat dissapative and will not normally will not
generate or hold a charge ( does not apply to Tyvek and other synthetics).
Try to charge up a piece of paper and check it with one of those small, hand
held, static field meters.
John Thorup


> -----Original Message-----
> From: Wilber Heath [SMTP:[log in to unmask]]
> Sent: Tuesday, March 28, 2000 11:55 AM
> To:   [log in to unmask]
> Subject:      [TN] ESD for Schematics
>
>  We are currently trying to get all of our paperwork used on the
> production floor into some type of static dissapative bags to prevent
> static charges. As we use a lot of schematics that are printed as
> large
> as 'E' size, it has been difficult to find ESD envelopes of this size
> to
> put the schemartics into. We have thought of some kind of protective
> lamination, but I have yet to find anything available to do this with.
> Another thought I had was to use deionizing fans, but am not sure if
> this would suffice. Does anyone out there have any ideas or things
> that
> you have used that solves this dilemma??
>
> ##############################################################
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Date:         Wed, 29 Mar 2000 15:51:58 +1000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Peter Tremewen <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Peter Tremewen <[log in to unmask]>
Subject:      Double sided mixed technology P.W.B.s....
MIME-Version: 1.0
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Hi to all,

                I have recently joined the list and enjoyed lurking in
the shadows for a little while. However, the company I am working for
has now decided to design double sided mixed technology P.W.B.s for
manufacture. Having had little experiance with this, I would apreciate
it if anyone out there could steer me in the corrct direction regarding
some text books or articals on it......    Thanks.

        Peter Tremewen

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Date:         Wed, 29 Mar 2000 08:04:02 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Scott E. Stewart" <[log in to unmask]>
Subject:      Shipley Ronal No Accelerator Electroless Cu System
MIME-Version: 1.0
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     Hi Everyone,
     I just wanted to get some opinions on Shipley Ronal's Electroless
     Copper 3350 Process which uses no Accelerator.  We manufacture PC
     Boards with hole sizes .018" to .008" and were interested in finding
     out what present users of this process and past users of this process
     think about this process.  Have there been issues with small hole
     voiding?

     Regards,

     S. Stewart

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Date:         Wed, 29 Mar 2000 08:23:56 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Shadow direct metalization process
MIME-Version: 1.0
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Hi all,

Many shops have installed and are running Electrochemicals shadow process.
We have been running it over 6 years now. However, as hole sized get smaller
we are seeing more voids than usual. The actual cause of the voids is
somewhat of a debate at this time. The effect of not having a fixer module
on our shadow line seems to be primary focus at this time. Perhaps those of
you who are using shadow and are drilling .0135 holes would care to share
your experience along these lines. What is your opinion on a fixer module.
Is it necessary?  If we install one, do you think it will help reducing
voids in small holes.

The supplier highly recommends it but I never loose sight of the fact that
they are in business to sell equipment. So, without any intention of
slighting our suppliers suggestions ( who I find the majority of the time
correct is their recommendations) , I always inquire with folks actually
using the products before I decide to endorse spending any money that may
not be necessary.


All comments are appreciated.

Ed Cosper

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Date:         Wed, 29 Mar 2000 09:32:57 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      More than you wanted to know about No Accelerator Electroless Cu
              System
X-To:         [log in to unmask]
MIME-Version: 1.0
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Mr. Stewart:

It is early, and I am just waking up as I type this, and thought I would use
your question as a trigger to discuss the no-accelerator type electroless
Copper plating system.  Incidently, everyone that I know using it loves it,
and says their results are better than using an accelerator, and with good
reason, it is chemically, a better system.

The no-accelerator concept is Shipley "borrowing" a concept that was actually
invented by IBM.  The "best" catalyst is one that deposits the most Paladium,
and removes the most Tin.  The normal Fluoboric Acid based accelerators
remove both.  IBM did some experiments back in the days when they actually
made boards, and purely by accident discovered that the best possible
accelerator was dilute (5%) warm (100 F) caustic soda.  The funny part of
that is they did not have a clue why it worked so well, other than it left
all the Paladium, and removed most of the Tin.
(I talked to the guy presenting the paper about this project, and wound up
explaining the chemistry of his own invention to him!)

The reason why it worked so well is that the Tin left on the board is in the
Stannic state, which is soluble only in dilute caustic, and in HF (Fluoboric
decomposes slightly, releasing trace amounts of HF).  So the caustic
accelerator dissolves the Stannic Tin, and leaves the Palladium behind.

Shipley saw this concept, and simply took it one step farther, since the
electroless Copper bath contains Caustic, and eliminated the accelerator.
Sure Tin builds in the bath, but with bail outs, etc, it never gets too high.

Good system, wish I were selling it.

The really funny part of this discussion is that since I do not have any
commercial interest in the product, such a discussion is okay.  If I were
selling it, a discussion like this would be "Ganz Verboten"....  Rules can
never meet the actual needs of real life.

Rudy Sedlak
RD Chemical Company

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Date:         Wed, 29 Mar 2000 06:38:38 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Balakrishnan Gopalan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Balakrishnan Gopalan <[log in to unmask]>
Subject:      Thermally Enhanced Packages!
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Hello TechNetters!

Can any of you suggest good literature (website,
articles or papers) as related to "Thermally Enhanced
Packages" with respect to

1. Applications & drive towards these packages
2. Methods & issues of Heat Spreader Attach
3. Issues in First & Second level reliability

Any level of information would be greatly appreciated.
Looking forward to your feedback.

Thanks & Regards

Balki
Graduate Research Associate
State University of New York
Binghamton, NY.


__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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Date:         Wed, 29 Mar 2000 09:48:33 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Commercial Interest was "More than... No Accelerator Electroless
              Cu System"
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Rudy,

I think that explaining the system when a question is asked, is not that big
a problem with the mailing list. But ONLY if a question is asked. It may be
a problem to few, but not me for sure. As long as the answer is SHORT, the
text is not just a big commercial, I don't really see a problem with that.
You could even leave a web site address in the answer and I wouldn't be
offended. Your expertise is always appreciated, blatant commercialism is
not.

Just my 2 cents,

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: <Rudy Sedlak>
Subject: [TN] More than you wanted to know about No Accelerator
Electroless Cu System
Good system, wish I were selling it.

The really funny part of this discussion is that since I do not have any
commercial interest in the product, such a discussion is okay.  If I were
selling it, a discussion like this would be "Ganz Verboten"....  Rules can
never meet the actual needs of real life.

Rudy Sedlak
RD Chemical Company

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Date:         Wed, 29 Mar 2000 09:58:19 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Wolfe, Robert" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Wolfe, Robert" <[log in to unmask]>
Subject:      Re: ESD for Schematics
X-To:         "Edward J. Valentine" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I would agree with Ed as far as size easily handled on floor.
We standardized our schematic dwg format size as D however we plot all
schematics at 1/2 scale which is a B size. You would need to have all text
on the schematic be min .100 on the full size, .125 is optimum. They are
very readable. We usually provide plot files also. The copies do tend to get
a little wider line so get a little muddled but are still readable. However
if you provide a plot file to print on a B-size laser or provide the copy
right off the B-size laser the prints are very good. You could then probably
find 11x17 static bags.

Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]


> -----Original Message-----
> From: Edward J. Valentine [SMTP:[log in to unmask]]
> Sent: Tuesday, March 28, 2000 10:05 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] ESD for Schematics
>
> Wilber -
>
> I'm not trying to be facetious or anything, but I would suggest you try
> using a smaller format for documentation to your production floor.  B size
> is about the biggest you can easily handle say at a workbench, lets say
> for
> troubleshooting (A size is preferred).  C size can be used with some
> difficulty, but D and E size are really awkward.
>
> If you want to get really large ESD bags, try Static Control Components in
> Sanford, NC at (800) 488-2426.  They can make custom sizes in addition to
> standard sizes.  If you have any problems, please feel free to contact me
> off TechNet.
>
> Ed Valentine
> Electronics Manufacturing Solutions
> 8612 Mourning Dove Road, Raleigh, NC 27615
> Phone: (919) 270-5145, Fax: (919) 847-9971
> Email: [log in to unmask]
> Website: http://www.ems-consulting.com
>
> ----- Original Message -----
> From: Wilber Heath <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, March 28, 2000 2:54 PM
> Subject: [TN] ESD for Schematics
>
>
> > We are currently trying to get all of our paperwork used on the
> > production floor into some type of static dissapative bags to prevent
> > static charges. As we use a lot of schematics that are printed as
> > large
> > as 'E' size, it has been difficult to find ESD envelopes of this size
> > to
> > put the schemartics into. We have thought of some kind of protective
> > lamination, but I have yet to find anything available to do this with.
> > Another thought I had was to use deionizing fans, but am not sure if
> > this would suffice. Does anyone out there have any ideas or things
> > that
> > you have used that solves this dilemma??
> >
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Date:         Wed, 29 Mar 2000 10:14:25 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         To My E-Mail Address <[log in to unmask]>
Subject:      Re: Controlled Impedance Testing
X-To:         [log in to unmask]
MIME-Version: 1.0
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TRy Pacific test labs

they are very good at this.

Call at 661-257-1437
ask for Kathy Kingsbury or Mike Shin

Rashesh

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Date:         Wed, 29 Mar 2000 10:14:38 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: Commercial Interest was "More than... No Accelerator
              Electroless Cu ...
X-To:         [log in to unmask]
MIME-Version: 1.0
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Thank you.

Rudy Sedlak

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Date:         Wed, 29 Mar 2000 10:02:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David A Gerson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David A Gerson <[log in to unmask]>
Subject:      Looking for some help............again.
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Good morning TechNetters.  I appreciate all of the feedback, response and
referrals you've provided in the past.  With your help I have made valuable
contacts that otherwise never would have occurred.  Once again I am asking for
assistance in my networking activities.

I am a Senior Consultant for Bell Oaks Company, a thirty year old executive
search firm headquartered in Atlanta, Georgia.  Just recently my firm has been
retained to assist one of our clients in locating a Sustaining Engineer.  This
is a highly visible position that heavily involved in the new product
development of state of the art, SMT, pick and place robots.  Ideally, I would
like to find someone who has at least four years experience in PCB assembly with
a focus in process improvements.  If anyone knows someone who may be qualified,
or is personally interested, feel free to contact me at (678) 287-2030 or by
Email at [log in to unmask]  Thank you for your time and consideration.  I
look forward to hearing from you.

Take care,

David A. Gerson
Senior Consultant
Bell Oaks Company
www.belloaks.com

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Date:         Wed, 29 Mar 2000 10:18:48 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David A Gerson <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David A Gerson <[log in to unmask]>
Subject:      Re: Controlled Impedance Testing
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Rashesh-

Was this in response to the email requesting networking assistance I just sent
out??  I wasn't sure if these are two people who might be relevent for a
Sustaning Engineer position or it was for someone else's benefit.

Thank you,

David Gerson
Senior Consultant
Bell Oaks Company
www.belloaks.com




To My E-Mail Address <[log in to unmask]> on 03/29/2000 10:14:25 AM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      [log in to unmask]

To:   [log in to unmask]
cc:    (bcc: David A Gerson/ME/Atlanta/Bell Oaks Company)

Subject:  Re: [TN] Controlled Impedance Testing




TRy Pacific test labs

they are very good at this.

Call at 661-257-1437
ask for Kathy Kingsbury or Mike Shin

Rashesh

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Date:         Wed, 29 Mar 2000 16:45:13 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Wilton Jenny <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Wilton Jenny <[log in to unmask]>
Subject:      Packaging of gold plated SM devices/Standards for base soldered
              devices.

Does anyone have any info on how to package gold plated SM devices which are
not moisture sensitive internally. I just need to know what humidity level to
store them at to obtain the optimum shelf life.
Also does anyone know of any quality standards in existence (IPC or others)
regarding the solder quality of base soldered devices (voids etc).

I would appreciate any help you can offer me on these items as I am struggling!


Many thanks

Jenny Wilton
Producibility Technician
BAE Systems
Vicarage Lane
Ilford
Essex
IG1 4AQ

Tel:- 0208-553-8177
Fax:- 0208-553-8196

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Date:         Wed, 29 Mar 2000 11:09:27 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Roger Mouton <[log in to unmask]>
Subject:      Re: Shadow direct metalization process
X-To:         [log in to unmask]
MIME-Version: 1.0
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Date:         Wed, 29 Mar 2000 11:12:55 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Roger Mouton <[log in to unmask]>
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Ed,

Do the fixer.  They don't just want to sell equipment.  You may contact me
off line to discuss it further.

RM
(714) 745-0108

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Date:         Wed, 29 Mar 2000 08:17:11 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Khalaf, Bilal" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Khalaf, Bilal" <[log in to unmask]>
Subject:      TDR a system of multiple Xmission media
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I need to TDR a complete system that includes Coax cables, microstrip and
stripline PCBs. What do I set my Propagation Delay to? The slowest of the
three? i.e. the "bottleneck"'s speed?

Thanks in advance for your assistance.
Bilal

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Date:         Thu, 30 Mar 2000 00:28:07 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Poh Kong Hui <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Poh Kong Hui <[log in to unmask]>
Subject:      : Unstable Fuji PDG
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Hi,

We are encountering the PDG unstable issue.

For example, the same PDG used today, but cannot be used may be after
a few days later. And we need to spend time doing the re-fine tuning.

Sometime, the new PDG is created, but need time to be spent on the fine
tune. And there seems to be no simple way, just to teach the component,
but rather by using 'try & error' method to perform the fine-tuning process.

We are not encountering such kind of issues on the Yamaha or Panasert or
Sanyo machine.

Is there a solution to this Fuji unstable PDG issue ? I am looking forwards
to it.


Poh

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Date:         Wed, 29 Mar 2000 17:21:33 +0100
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Finlay Buchan <[log in to unmask]>
Subject:      Re: Double sided mixed technology P.W.B.s....
X-To:         Peter Tremewen <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Peter

I know that you have a million design rules to carry about in your head when
designing these but can you also try not to forget about the pallet
manufacturer. I have put down a few design rules relating to clearances
around smt and pth parts so that effective pallets can be manufactured.

These can be found by going to our web page http://www.datumdynamics.com and
selecting "Design Rules for Selective Wave Solder".

Hope this helps, If you wish you could send me the Gerber files (embedded
aperture if possible) and I will comment and mark up any changes which would
make the board better to flow.

Regards

Fin

Finlay Buchan
Technical Director
Datum Dynamics Ltd           Datum Dynamics Inc
Tel +44 (0)1290 426200       +1 401 683 5300
Fax +44 (0)1290 426212       +1 401 683 3995
Email [log in to unmask]
Web Page http://www.datumdynamics.com




> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Tremewen
> Sent: 29 March 2000 06:52
> To: [log in to unmask]
> Subject: [TN] Double sided mixed technology P.W.B.s....
>
>
> Hi to all,
>
>                 I have recently joined the list and enjoyed lurking in
> the shadows for a little while. However, the company I am working for
> has now decided to design double sided mixed technology P.W.B.s for
> manufacture. Having had little experiance with this, I would apreciate
> it if anyone out there could steer me in the corrct direction
> regarding
> some text books or articals on it......    Thanks.
>
>         Peter Tremewen
>
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Date:         Wed, 29 Mar 2000 11:43:28 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Wolfe, Robert" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Wolfe, Robert" <[log in to unmask]>
Subject:      Change Associated Files in NT4 SP6a
X-To:         Designers Council <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Need a little help.
I have accidently set up an association for files with the .hgl extension
for a program AutoView.
If I go to My Computer/View/Options/File Types you can supposedly change
this. However once there, there is no listing
for the .hgl If you delete or Edit any of  the Autoview info you end up
having to reinstall Autoview. If you try and make a new association with
.hgl it tells you already in use as hgl_auto_file yet that is not listed in
the files types either to be able to edit.
Our MIS group had no answers either. All I want is to be able to undo the
association of only the .hgl file type
with any program and can' t seem to get there form here.
TIA
Bob
Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]

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Date:         Wed, 29 Mar 2000 12:07:04 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Nutting <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Nutting <[log in to unmask]>
Subject:      Re: Change Associated Files in NT4 SP6a
X-To:         "Wolfe, Robert" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Bob,

Try opening Windows NT Explorer, click on View/Options/File Types.  This
should get you to a screen that allows you to Edit, Remove or add a New
Type.

Regards,

Phi Nutting
Manufacturing Engineer
Kaiser Systems, Inc.

-----Original Message-----
From: Wolfe, Robert [mailto:[log in to unmask]]
Sent: Wednesday, March 29, 2000 11:43 AM
To: [log in to unmask]
Subject: [TN] Change Associated Files in NT4 SP6a


Need a little help.
I have accidently set up an association for files with the .hgl extension
for a program AutoView.
If I go to My Computer/View/Options/File Types you can supposedly change
this. However once there, there is no listing
for the .hgl If you delete or Edit any of  the Autoview info you end up
having to reinstall Autoview. If you try and make a new association with
.hgl it tells you already in use as hgl_auto_file yet that is not listed in
the files types either to be able to edit.
Our MIS group had no answers either. All I want is to be able to undo the
association of only the .hgl file type
with any program and can' t seem to get there form here.
TIA
Bob
Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]

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Date:         Wed, 29 Mar 2000 12:13:30 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Tom Taylor <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Tom Taylor <[log in to unmask]>
Organization: Taylor Consulting Services
Subject:      Re: Change Associated Files in NT4 SP6a
X-To:         "Wolfe, Robert" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

The following may help.  Since it involves editing the registry, the normal
caveats apply (back up your system, etc.).  Depending on how MIS set up your
system, you may have to get Administrator privileges on the local machine.
I've used the following procedure on SP5.  SP6a "should not" be any
different.

1.  Choose Run from the Start menu, enter 'regedt32' and click OK.
2.  Select the window labeled "HKEY_LOCAL_MACHINE".
3.  Scroll down to the folder icon labeled "SOFTWARE" and double-click to
expand.
4.  Scroll down to the folder icon labeled "Classes" and double-click to
expand.
5.  Scroll down to the folder icon labeled ".hgl" and select it.
6.  Hit the Del key.  Click 'Yes' on the confirmation message box.

You might want to try out some of the public Microsoft newsgroups for future
NT problems.

-- Tom Taylor, Taylor Consulting Services

----- Original Message -----
From: Wolfe, Robert <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 29, 2000 11:43 AM
Subject: [TN] Change Associated Files in NT4 SP6a


> Need a little help.
> I have accidently set up an association for files with the .hgl extension
> for a program AutoView.
> If I go to My Computer/View/Options/File Types you can supposedly change
> this. However once there, there is no listing
> for the .hgl If you delete or Edit any of  the Autoview info you end up
> having to reinstall Autoview. If you try and make a new association with
> .hgl it tells you already in use as hgl_auto_file yet that is not listed
in
> the files types either to be able to edit.
> Our MIS group had no answers either. All I want is to be able to undo the
> association of only the .hgl file type
> with any program and can' t seem to get there form here.
> TIA
> Bob
> Executone Inter-Tel Business Information Systems, Inc.
> Robert M. Wolfe C.I.D.
> Lead PCB Designer
> 478 Wheelers Farms Road
> Milford, CT 06460
> Phone: 203-882-6405
> Fax:   203-882-2727
> Email: [log in to unmask]
>
> ##############################################################
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following text in
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Date:         Wed, 29 Mar 2000 13:00:23 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Jack Bradshaw <[log in to unmask]>
Subject:      Gold electroplate
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Does anyone have a source for gold electroplate in the southern NH area.  (I
am in Hampstead)

Jack Bradshaw
ATFSI
603/329-7322
Fax -7208

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Date:         Wed, 29 Mar 2000 11:11:31 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      Re: Change Associated Files in NT4 SP6a
X-To:         "Wolfe, Robert" <[log in to unmask]>

Robert,
        The easiest way to change the associations of files is to use
winfile.  It will look and operate like windows explorer.  It is somewhat
buried in your windows directories so either use "find file" in the start
menu or run "winfile" from the start menu.  Once you are in winfile, just
find the file you want to change the association of, and change the
association.  The option is under the "File" menu.  I usually have the best
luck changing the association back to "none".  (I use this thing so often I
have put shortcut to winfile on my desktop).

Regards
Ryan Grant

> -----Original Message-----
> From: Wolfe, Robert [SMTP:[log in to unmask]]
> Sent: Wednesday, March 29, 2000 9:43 AM
> To:   [log in to unmask]
> Subject:      [TN] Change Associated Files in NT4 SP6a
>
> Need a little help.
> I have accidently set up an association for files with the .hgl extension
> for a program AutoView.
> If I go to My Computer/View/Options/File Types you can supposedly change
> this. However once there, there is no listing
> for the .hgl If you delete or Edit any of  the Autoview info you end up
> having to reinstall Autoview. If you try and make a new association with
> .hgl it tells you already in use as hgl_auto_file yet that is not listed
> in
> the files types either to be able to edit.
> Our MIS group had no answers either. All I want is to be able to undo the
> association of only the .hgl file type
> with any program and can' t seem to get there form here.
> TIA
> Bob
> Executone Inter-Tel Business Information Systems, Inc.
> Robert M. Wolfe C.I.D.
> Lead PCB Designer
> 478 Wheelers Farms Road
> Milford, CT 06460
> Phone: 203-882-6405
> Fax:   203-882-2727
> Email: [log in to unmask]
>
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> information.
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> 847-509-9700 ext.5315
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=========================================================================
Date:         Wed, 29 Mar 2000 10:25:58 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ken Patel <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ken Patel <[log in to unmask]>
Subject:      Looking Foam inspection criteria
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

Guys,
I am in a process of making a foam inspection criteria used in system
packaging for our in-coming QA folks. Does any one has guideline/procedure
which  I can follow to accept or reject the foam?

We may have to modify the received procedure.

re,
ken patel
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Wed, 29 Mar 2000 13:24:32 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Wolfe, Robert" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Wolfe, Robert" <[log in to unmask]>
Subject:      Associated files
MIME-Version: 1.0
Content-Type: text/plain

Thanks to all who answered.
The easiest way was to use winfile it worked just fine.
Thanks
Bob

Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]

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Date:         Wed, 29 Mar 2000 13:24:26 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Erat, Wolfgang" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Erat, Wolfgang" <[log in to unmask]>
Subject:      boards for high current loads
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----_=_NextPart_001_01BF99AC.06E9897A"

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------_=_NextPart_001_01BF99AC.06E9897A
Content-Type: text/plain

Hello

I have a number of requests on my desk where customers need some areas of
boards with very thick copper (6 to 12 ounces for some heavy duty current)
and the rest of the board with standard fineline features.

Heavy duty plating ?? double imaging ?? etching through a bunch of copper ?
none are attractive options.
Any and all ideas on alternate processes would be appreciated.

Thanks, Wolfgang

[log in to unmask]



------_=_NextPart_001_01BF99AC.06E9897A
Content-Type: text/html

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">
<META NAME="Generator" CONTENT="MS Exchange Server version 5.5.2448.0">
<TITLE>boards for high current loads</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=2 FACE="Courier New">Hello </FONT>
</P>

<P><FONT SIZE=2 FACE="Courier New">I have a number of requests on my desk where customers need some areas of</FONT>
<BR><FONT SIZE=2 FACE="Courier New">boards with very thick copper (6 to 12 ounces for some heavy duty current)</FONT>
<BR><FONT SIZE=2 FACE="Courier New">and the rest of the board with standard fineline features.</FONT>
</P>

<P><FONT SIZE=2 FACE="Courier New">Heavy duty plating ?? double imaging ?? etching through a bunch of copper ?</FONT>
<BR><FONT SIZE=2 FACE="Courier New">none are attractive options. </FONT>
<BR><FONT SIZE=2 FACE="Courier New">Any and all ideas on alternate processes would be appreciated. </FONT>
</P>

<P><FONT SIZE=2 FACE="Courier New">Thanks, Wolfgang </FONT>
</P>

<P><FONT SIZE=2 FACE="Courier New">[log in to unmask]&nbsp;&nbsp; </FONT>
</P>
<BR>

</BODY>
</HTML>
------_=_NextPart_001_01BF99AC.06E9897A--

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Date:         Wed, 29 Mar 2000 13:41:13 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Tom Burek <[log in to unmask]>
Subject:      Pick and Place of Melf Parts.
MIME-version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-transfer-encoding: quoted-printable

Does anyone have any good ideas on how to pick and place a Melf component=20=
without it sliding or falling off of the nozzle?  We are using a QSP2 but=20=
have had some difficulty keeping it on the nozzle during pick and place=2E=20=
 Any experience would be greatly appreciated=2E
Thank You,
Tom Burek

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Date:         Wed, 29 Mar 2000 13:52:12 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "McGlaughlin, Jeffrey A" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "McGlaughlin, Jeffrey A" <[log in to unmask]>
Subject:      Re: boards for high current loads
X-To:         "Erat, Wolfgang" <[log in to unmask]>

Wolfgang -

There are a number of fabricators that can do selective plating for high
current areas of a PCB. One, I have worked with, claims to be able to plate
up to 0.031" thickness. Contact me off-line if you need contact information
I will see if I can find it.

Jeffrey A. McGlaughlin
Sr. PCB Designer
Battelle Memorial Institute
Columbus Ohio
[log in to unmask]


        -----Original Message-----
        From:   Erat, Wolfgang [SMTP:[log in to unmask]]
        Sent:   Wednesday, 29 March, 2000 13:24
        To:     [log in to unmask]
        Subject:        [TN] boards for high current loads

        Hello

        I have a number of requests on my desk where customers need some
areas of
        boards with very thick copper (6 to 12 ounces for some heavy duty
current)
        and the rest of the board with standard fineline features.

        Heavy duty plating ?? double imaging ?? etching through a bunch of
copper ?
        none are attractive options.
        Any and all ideas on alternate processes would be appreciated.

        Thanks, Wolfgang

        [log in to unmask]



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Date:         Wed, 29 Mar 2000 14:12:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Scott Stewart <[log in to unmask]>
Subject:      Enthone Envision DMS-E Direct Metalization
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit

     Hi All,
     Is there anyone out there running Enthone's DMS-E direct metalization
     process?

     If so, what kind of yields are you getting?

     Any problems with small holes (.008" - .016")?

     Do you have horizontal conveyorized process or vertical and if
     horizontal what equipment are you using?  Does your equipment have
     triple rinsing?  Do you have a micro etch between the desmear and
     DMS-E part of the line?  Is your desmear vertical or horizontal?


     Best Regards,

     Scott

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Date:         Wed, 29 Mar 2000 14:10:49 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Royce Taylor <[log in to unmask]>
Subject:      Re: Pick and Place of Melf Parts.
X-To:         Tom Burek <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit

     Tom,

     Most equipment vendors sell special nozzles for MELF's, they are
     either molded to fit the contour of the melf body or have a Vee notch
     cut in the nozzle. Universal, Mydata, Siemens, Quad (machines I have
     used) all sell these kinds of nozzles

     Royce
     **********************************************************
     Royce Taylor
     Sr. SMT Process Engineer
     Hadco Value Added Manufacturing
     10 Manor Parkway
     Salem, NH 03079
     (603)896-2192 voice
     (603)896-2006 fax
     (800)973-4679 pager
     email: [log in to unmask]



______________________________ Reply Separator _________________________________
Subject: [TN] Pick and Place of Melf Parts.
Author:  Tom Burek <[log in to unmask]> at smtplink-hadco
Date:    3/29/00 1:41 PM


Does anyone have any good ideas on how to pick and place a Melf component
without it sliding or falling off of the nozzle?  We are using a QSP2 but have
had some difficulty keeping it on the nozzle during pick and place.  Any
experience would be greatly appreciated.
Thank You,
Tom Burek

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Date:         Wed, 29 Mar 2000 14:16:59 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Scott Stewart <[log in to unmask]>
Subject:      White Tin
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit

     Hi All,
     Does anyone have information on White Tin as an alternative finish to
     HASL, OSP's, Ni/Au?  How are the ionics?  What Chemical Suppliers
     would you recommend for White Tin?

     Regards,

     Scott

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Date:         Wed, 29 Mar 2000 12:19:53 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Howieson, Rick" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Howieson, Rick" <[log in to unmask]>
Subject:      Re: Shadow direct metalization process
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Ed,
Get a fixer. Also, the majority of the problems we run into are lack of
maintenance controls, not only with the chemistry but more so with the
mechanics of the equipment. We also have Electrochem audit our processes
on a quarterly basis, after all it's their job if they want our
continued business.
Rick
GTC

>-----Original Message-----
>From:  Ed Cosper [SMTP:[log in to unmask]]
>Sent:  Wednesday, March 29, 2000 6:24 AM
>To:    [log in to unmask]
>Subject:       [TN] Shadow direct metalization process
>
>Hi all,
>
>Many shops have installed and are running Electrochemicals shadow process.
>We have been running it over 6 years now. However, as hole sized get smaller
>we are seeing more voids than usual. The actual cause of the voids is
>somewhat of a debate at this time. The effect of not having a fixer module
>on our shadow line seems to be primary focus at this time. Perhaps those of
>you who are using shadow and are drilling .0135 holes would care to share
>your experience along these lines. What is your opinion on a fixer module.
>Is it necessary?  If we install one, do you think it will help reducing
>voids in small holes.
>
>The supplier highly recommends it but I never loose sight of the fact that
>they are in business to sell equipment. So, without any intention of
>slighting our suppliers suggestions ( who I find the majority of the time
>correct is their recommendations) , I always inquire with folks actually
>using the products before I decide to endorse spending any money that may
>not be necessary.
>
>
>All comments are appreciated.
>
>Ed Cosper
>
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Date:         Wed, 29 Mar 2000 11:41:13 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bob Perkins <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bob Perkins <[log in to unmask]>
Subject:      Re: Pick and Place of Melf Parts.
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Tom

        It sounds like you need a melf nozzle, this is a nozzle with the
same curvature at the tip as the melf.  We have two types, regular melf size
and mini melf size. Siemens supplies these in their nozzle library. You may
be able to take a small round needle file and create one yourself.

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Date:         Wed, 29 Mar 2000 16:36:35 -0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Jorge Engenharia <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Jorge Engenharia <[log in to unmask]>
Subject:      Re: Pick and Place of Melf Parts.
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

 Tom,

   The real solution is special nozzles, but until you didn't buy them =
try
to reduce all speeds in the machine ( pick, vision, position and place =
) for
the melfs and also try to increase the vacuum level. If production
requirements didn't allow increase machine cycle time then hand =
placement
could be a short term solution ( be careful with polarity !!! )

Jorge Dourado de Santana
Maintenance / Process Engr
Microtec - Brazil

=20

> -----Original Message-----
> From: Royce Taylor [SMTP:[log in to unmask]]
> Sent: 29 de Mar=E7o de 2000 16:11
> To:   [log in to unmask]
> Subject:      Re: [TN] Pick and Place of Melf Parts.
>=20
>      Tom,
>=20
>      Most equipment vendors sell special nozzles for MELF's, they are
>      either molded to fit the contour of the melf body or have a Vee =
notch
>      cut in the nozzle. Universal, Mydata, Siemens, Quad (machines I =
have
>      used) all sell these kinds of nozzles
>=20
>      Royce
>      **********************************************************
>      Royce Taylor
>      Sr. SMT Process Engineer
>      Hadco Value Added Manufacturing
>      10 Manor Parkway
>      Salem, NH 03079
>      (603)896-2192 voice
>      (603)896-2006 fax
>      (800)973-4679 pager
>      email: [log in to unmask]
>=20
>=20
>=20
> ______________________________ Reply Separator
> _________________________________
> Subject: [TN] Pick and Place of Melf Parts.
> Author:  Tom Burek <[log in to unmask]> at smtplink-hadco
> Date:    3/29/00 1:41 PM
>=20
>=20
> Does anyone have any good ideas on how to pick and place a Melf =
component
> without it sliding or falling off of the nozzle?  We are using a QSP2 =
but
> have
> had some difficulty keeping it on the nozzle during pick and place.  =
Any
> experience would be greatly appreciated.
> Thank You,
> Tom Burek
>=20
> ##############################################################
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1.8c
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> additional
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>=20
> ##############################################################
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1.8c
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> additional
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> 847-509-9700 ext.5315
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Date:         Wed, 29 Mar 2000 15:10:19 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Hollandsworth, Ron" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Hollandsworth, Ron" <[log in to unmask]>
Subject:      Re: White Tin
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Scott:

We sampled White Immersion Tin finish on some boards and to date no
problems.  Class 3 product, Military, Communication gear.  No assembly
issues, SMT, or thru hole.  Boards were a mixed technology.  All is well so
far.  Boards are in units in extended stress testing, have been for sometime
now with no failures yet.

Ron Hollandsworth
ITT A/CD

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=========================================================================
Date:         Wed, 29 Mar 2000 21:03:44 +0100
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "[log in to unmask]" <[log in to unmask]>
Subject:      Re: Shadow direct metalization process
X-To:         Ed Cosper <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ed Cosper wrote:
>
> Hi all,
>
> Many shops have installed and are running Electrochemicals shadow process.
> We have been running it over 6 years now. However, as hole sized get smaller
> we are seeing more voids than usual. The actual cause of the voids is
> somewhat of a debate at this time. The effect of not having a fixer module
> on our shadow line seems to be primary focus at this time. Perhaps those of
> you who are using shadow and are drilling .0135 holes would care to share
> your experience along these lines. What is your opinion on a fixer module.
> Is it necessary?  If we install one, do you think it will help reducing
> voids in small holes.
>
> The supplier highly recommends it but I never loose sight of the fact that
> they are in business to sell equipment. So, without any intention of
> slighting our suppliers suggestions ( who I find the majority of the time
> correct is their recommendations) , I always inquire with folks actually
> using the products before I decide to endorse spending any money that may
> not be necessary.
>
> All comments are appreciated.
>
> Ed Cosper
> ##############################################################
Go for the fixer it will prevent excessive Shadow in the holes and on
inner layer copper.
As for voids this can be caused if the whole board including holes are
not bone dry before
the micro etch. The smaller the hole the more difficult to dry it.

We have been plating 16:1 aspect ratio holes in boards up to 0.25" using
Shadow since 1995
and do not get voids.

I hope my comments may help as it is nice to think that I am now able to
give something in
return for seeing you Shadow line in 1994.

Regards

Roger Hammond

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Date:         Wed, 29 Mar 2000 13:26:26 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ray Aguilar <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ray Aguilar <[log in to unmask]>
Subject:      Re: Change Associated Files in NT4 SP6a
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

hello,=20

My ext to hgl is "Autocad ..... HGL"=20

I simply removed the association.

Then I associated it back.

Seem fine.

Raymond  Aguilar  C.I.D.
Manager, Engineering Configuration
TACAN Corporation Inc.
2330 Faraday Avenue
Carldbad, CA. 92008
V:(760)-438-8362 x 3258
F:(760)-438-2412
E-mail [log in to unmask]
www.tacan.com

ISO 9001 Certified




>>> "Wolfe, Robert" <[log in to unmask]> 03/29/00 08:43AM >>>
Need a little help.
I have accidently set up an association for files with the .hgl extension
for a program AutoView.
If I go to My Computer/View/Options/File Types you can supposedly change
this. However once there, there is no listing
for the .hgl If you delete or Edit any of  the Autoview info you end up
having to reinstall Autoview. If you try and make a new association with
.hgl it tells you already in use as hgl_auto_file yet that is not listed =
in
the files types either to be able to edit.
Our MIS group had no answers either. All I want is to be able to undo the
association of only the .hgl file type
with any program and can' t seem to get there form here.
TIA
Bob
Executone Inter-Tel Business Information Systems, Inc.
Robert M. Wolfe C.I.D.
Lead PCB Designer
478 Wheelers Farms Road
Milford, CT 06460
Phone: 203-882-6405
Fax:   203-882-2727
Email: [log in to unmask]

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Date:         Wed, 29 Mar 2000 15:54:41 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ian Slater <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ian Slater <[log in to unmask]>
Organization: GE HARRIS Energy Control Systems
Subject:      ESD Standards
MIME-Version: 1.0
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Can anyone recommend a set of ESD standards for electronics
manufacturing?

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Date:         Wed, 29 Mar 2000 16:15:16 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Dewey Whittaker <[log in to unmask]>
Organization: Honeywell Inc.
Subject:      Re: ESD Standards
X-To:         Ian Slater <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="------------FFCB8C8C7B466E837A079BE3"

--------------FFCB8C8C7B466E837A079BE3
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> EIA-625 and our own internal controls are used.

Dewey


> Can anyone recommend a set of ESD standards for electronics
> manufacturing?
>
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--
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]



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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>

<blockquote TYPE=CITE>EIA-625 and our own internal controls are used.</blockquote>
Dewey
<br>&nbsp;
<blockquote TYPE=CITE>Can anyone recommend a set of ESD standards for electronics
<br>manufacturing?
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<pre>--&nbsp;
Dewey Whittaker
Honeywell -- Air Transport Systems Division
US Mail: P.O. Box 21111 MS: M16A2 Phoenix AZ 85036
Phone: +1 602 436 436-2766
NSFnet: [log in to unmask]</pre>
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Date:         Wed, 29 Mar 2000 15:16:28 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cash, Alan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cash, Alan" <[log in to unmask]>
Subject:      Re: ESD Standards
X-To:         Ian Slater <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Contact the ESD Association, they just released ANSI/ESD S20.20.
Their E mail address is [log in to unmask]

Al lCash

-----Original Message-----
From: Ian Slater [mailto:[log in to unmask]]
Sent: Wednesday, March 29, 2000 4:55 PM
To: [log in to unmask]
Subject: [TN] ESD Standards


Can anyone recommend a set of ESD standards for electronics
manufacturing?

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Date:         Wed, 29 Mar 2000 16:12:56 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Darrel Therriault <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Darrel Therriault <[log in to unmask]>
Subject:      B/P Yields
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed

Technetters/Fabricators,

My supplier is having a problem with yield on our backplane (~.200",
SMOBC/HASL).  It seems to be centering around
hole plugging from HASL.  FHS are .024", .028", .032" for both pressfit and
pth connectors.  Is this a typical problem for
these requirements??

If so, what are other finishes to consider to achieve higher yields but not
introduce large cost adders??

Comments and suggestions appreciated.

Tks........DT

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Date:         Wed, 29 Mar 2000 19:58:08 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              David Fish <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         David Fish <[log in to unmask]>
Subject:      Re: ESD Standards
X-To:         "Cash, Alan" <[log in to unmask]>
MIME-Version: 1.0
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S20.20 is downloadable at: http://www.esda.org/pdf_files/s2020std.pdf

"Cash, Alan" wrote:

> Contact the ESD Association, they just released ANSI/ESD S20.20.
> Their E mail address is [log in to unmask]
>
> Al lCash
>
> -----Original Message-----
> From: Ian Slater [mailto:[log in to unmask]]
> Sent: Wednesday, March 29, 2000 4:55 PM
> To: [log in to unmask]
> Subject: [TN] ESD Standards
>
> Can anyone recommend a set of ESD standards for electronics
> manufacturing?
>
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Date:         Wed, 29 Mar 2000 21:10:16 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Charles E. McMahon" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Charles E. McMahon" <[log in to unmask]>
Organization: McMahon Sales Company, Inc.
Subject:      Re: B/P Yields
X-To:         Darrel Therriault <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Darrel:

HASL on 200 mil thick boards is in my view asking for trouble. I would
suggest alternatives to HASL at the very least.
If I understand correctly, are you having your press-fit holes plug with
solder due to the HASL process?
Charlie

--- Original Message -----
From: Darrel Therriault <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, March 29, 2000 7:12 PM
Subject: [TN] B/P Yields


> Technetters/Fabricators,
>
> My supplier is having a problem with yield on our backplane (~.200",
> SMOBC/HASL).  It seems to be centering around
> hole plugging from HASL.  FHS are .024", .028", .032" for both pressfit
and
> pth connectors.  Is this a typical problem for
> these requirements??
>
> If so, what are other finishes to consider to achieve higher yields but
not
> introduce large cost adders??
>
> Comments and suggestions appreciated.
>
> Tks........DT
>
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Date:         Wed, 29 Mar 2000 21:58:07 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ron Yanuszewski <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ron Yanuszewski <[log in to unmask]>
Subject:      Re: B/P Yields
X-To:         Darrel Therriault <[log in to unmask]>
MIME-Version: 1.0
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Darrell:

We are using OSP on .200" thick with .022" & .024" holes for compliant connectors.

Darrel Therriault wrote:

> Technetters/Fabricators,
>
> My supplier is having a problem with yield on our backplane (~.200",
> SMOBC/HASL).  It seems to be centering around
> hole plugging from HASL.  FHS are .024", .028", .032" for both pressfit and
> pth connectors.  Is this a typical problem for
> these requirements??
>
> If so, what are other finishes to consider to achieve higher yields but not
> introduce large cost adders??
>
> Comments and suggestions appreciated.
>
> Tks........DT
>
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Date:         Thu, 30 Mar 2000 08:30:50 +0300
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Gabriela Bogdan <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Gabriela Bogdan <[log in to unmask]>
Subject:      Re: White Tin
X-To:         "Hollandsworth, Ron" <[log in to unmask]>
MIME-Version: 1.0
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Ron,
please could you tell me what flux and solder paste you use in your application?
Thanks,
Gaby

"Hollandsworth, Ron" wrote:

> Scott:
>
> We sampled White Immersion Tin finish on some boards and to date no
> problems.  Class 3 product, Military, Communication gear.  No assembly
> issues, SMT, or thru hole.  Boards were a mixed technology.  All is well so
> far.  Boards are in units in extended stress testing, have been for sometime
> now with no failures yet.
>
> Ron Hollandsworth
> ITT A/CD
>
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Date:         Thu, 30 Mar 2000 10:03:55 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Kevin Berry <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Kevin Berry <[log in to unmask]>
Subject:      Re: Thermally Enhanced Packages!
X-To:         Balakrishnan Gopalan <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Balki,
Take a look at the TI web site. search for PowerPAD or technical brief
SLMA002 and download the PDF file. The paper publishes thermal management
methods and results for a range of standard surface mount packages.
Alternatively, look in the SMI '98 proceedings. (page 151) Also in the
proceedings is a paper from ChipPAC presenting the thermal performance of a
modified  BGA. (page 769)

Regards,

-----Original Message-----
From: Balakrishnan Gopalan [mailto:[log in to unmask]]
Sent: 29 March 2000 15:39
To: [log in to unmask]
Subject: [TN] Thermally Enhanced Packages!


Hello TechNetters!

Can any of you suggest good literature (website,
articles or papers) as related to "Thermally Enhanced
Packages" with respect to

1. Applications & drive towards these packages
2. Methods & issues of Heat Spreader Attach
3. Issues in First & Second level reliability

Any level of information would be greatly appreciated.
Looking forward to your feedback.

Thanks & Regards

Balki
Graduate Research Associate
State University of New York
Binghamton, NY.


__________________________________________________
Do You Yahoo!?
Talk to your friends online with Yahoo! Messenger.
http://im.yahoo.com

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Date:         Thu, 30 Mar 2000 11:11:36 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Jan Merstrand (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Jan Merstrand (EMW)" <[log in to unmask]>
Subject:      Solder at lower temperature
MIME-Version: 1.0
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Hi guys and girls!!

I have a question that I think many of you can answer.
Today we solder FET chips with Au/Sn solder onto a DBC substrate with =
Au surface.
The soldering area of the FET is Chromium/Nickel/Silver.

I want to replace the Au/Sn solder with "something else".. I don't want =
to glue the chip to place, only solder.
The FET working temperature reaches up to 120degC.

Any ideas on what kind of solder to use?=20
__________________________________________________
Jan Merstrand
Microwave MCM, Design/Production Support
Ericsson Microwave Systems AB. Defence Manufacturing
Office address: Bergfotsgatan 2, SE-431 84 M=F6lndal
Phone: +46 31 747 0725, Fax: +46 31 747 3515

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Date:         Thu, 30 Mar 2000 06:02:18 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Commercial Interest was "More than... No Accelerator
              Electroless             Cu System"
X-To:         Alain Savard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Good morning Alain & All -

I, for one, found Rudy's description informative and educational.  Seems
like that's a lot of what this forum is about.  Even us old dogs can learn a
few things, now and then.

Regards - Kelly

-----Original Message-----
From: Alain Savard <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Wednesday, March 29, 2000 8:55 AM
Subject: [TN] Commercial Interest was "More than... No Accelerator
Electroless Cu System"


>Rudy,
>
>I think that explaining the system when a question is asked, is not that
big
>a problem with the mailing list. But ONLY if a question is asked. It may be
>a problem to few, but not me for sure. As long as the answer is SHORT, the
>text is not just a big commercial, I don't really see a problem with that.
>You could even leave a web site address in the answer and I wouldn't be
>offended. Your expertise is always appreciated, blatant commercialism is
>not.
>
>Just my 2 cents,
>
>Alain Savard, B.Sc.
>Chemical Process Analyst
>CAE Electronics Ltd.
>e-mail: [log in to unmask]
>

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Date:         Thu, 30 Mar 2000 06:24:05 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: Looking Foam inspection criteria
X-To:         Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Ken -

From your description, this sounds as if it is probably expanded polystyrene
(EPS) molded packaging forms, am I right?  Inspection of this stuff in your
facility, on your nickel, can turn into a money pit in a hurry!!

Suppliers of EPS products are generally sited fairly close to the users,
which helps minimize shipping costs, etc.  If this is the case, I would
strongly recommend your product assurance folks work with the molder to see
what the most economical solution to the question is.   Since these type
materials tend to be molded by the truckload and larger, I would strongly
suggest some sort of sampling plan, perhaps done when the molds are first
put in operation, then repeated at some interval.

I have seen this type packaging checked with a quick fit of a dummy part or
parts, or with plug type go/no-go gages.

Regards - Kelly

-----Original Message-----
From: Ken Patel <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Wednesday, March 29, 2000 12:25 PM
Subject: [TN] Looking Foam inspection criteria


>Guys,
>I am in a process of making a foam inspection criteria used in system
>packaging for our in-coming QA folks. Does any one has guideline/procedure
>which  I can follow to accept or reject the foam?
>
>We may have to modify the received procedure.
>
>re,
>ken patel
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
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Date:         Thu, 30 Mar 2000 14:44:39 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Sticky question
Mime-Version: 1.0
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Hi all

What polymers are used for anisotropic adhesives?

Best regards

Guenter

Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :      xx41 1823 4054
mail:     [log in to unmask]

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Date:         Thu, 30 Mar 2000 07:47:36 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kasprzak, Bill (esd) USX" <[log in to unmask]>
Subject:      Re: Change Associated Files in NT4 SP6a
X-To:         "Wolfe, Robert" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Bob,

I'm not an expert at this but, I think if you delete the line from the
win.ini file in your windows directory you'll take care of it after you
re-boot.

I've included a few lines from my win.ini file to show you what it looks
like.

cdr=n:\inset-30\hjpro.exe ^.cdr
ed6=n:\inset-30\hjpro.exe ^.ed6
hgl=n:\inset-30\hjpro.exe ^.hgl
lbm=n:\inset-30\hjpro.exe ^.lbm
mcs=n:\inset-30\hjpro.exe ^.mcs

        Just delete the line.


        Bill Kasprzak
        Moog Inc.



> -----Original Message-----
> From: Wolfe, Robert [SMTP:[log in to unmask]]
> Sent: Wednesday, March 29, 2000 11:43 AM
> To:   [log in to unmask]
> Subject:      [TN] Change Associated Files in NT4 SP6a
>
> Need a little help.
> I have accidently set up an association for files with the .hgl extension
> for a program AutoView.
> If I go to My Computer/View/Options/File Types you can supposedly change
> this. However once there, there is no listing
> for the .hgl If you delete or Edit any of  the Autoview info you end up
> having to reinstall Autoview. If you try and make a new association with
> .hgl it tells you already in use as hgl_auto_file yet that is not listed
> in
> the files types either to be able to edit.
> Our MIS group had no answers either. All I want is to be able to undo the
> association of only the .hgl file type
> with any program and can' t seem to get there form here.
> TIA
> Bob
> Executone Inter-Tel Business Information Systems, Inc.
> Robert M. Wolfe C.I.D.
> Lead PCB Designer
> 478 Wheelers Farms Road
> Milford, CT 06460
> Phone: 203-882-6405
> Fax:   203-882-2727
> Email: [log in to unmask]
>
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Date:         Thu, 30 Mar 2000 06:45:12 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Kelly M. Schriver" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Kelly M. Schriver" <[log in to unmask]>
Subject:      Re: boards for high current loads
X-To:         "Erat, Wolfgang" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
              boundary="----=_NextPart_000_00EB_01BF9A13.7F9090A0"

This is a multi-part message in MIME format.

------=_NextPart_000_00EB_01BF9A13.7F9090A0
Content-Type: text/plain;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Morning Wolfgang & All -

I've had fairly good success in the past using additive bus bars which =
are installed on the board towards the end of the assembly process.  =
This helps to avoid difficulties both at the board fabrication and the =
assembly stages.  There are quite a number of suppliers of these =
devices, or most board fabricators can etch custom forms to your design, =
from copper sheet.

The use of extremely heavy copper is possible, but it tends to increase =
the probability of board warpage and also acts as a heat sink during the =
assembly soldering process.  If this approach is the only possibility, =
then I would suggest you enlist your board fabricators assistance before =
design completion in order to arrive at a solution both of you can live =
with.   There are several houses that do specialize in the heavy power =
boards - all seem to have their own recipes for success.

You may need to consider laminates with a higher Tg to accomodate =
prolonged solder cycle durations.  SMOBC on external conductors is =
almost essential to prevent solder globs picking up on the heavy copper =
areas during wave soldering.

Regards - Kelly
    -----Original Message-----
    From: Erat, Wolfgang <[log in to unmask]>
    To: [log in to unmask] <[log in to unmask]>
    Date: Wednesday, March 29, 2000 12:28 PM
    Subject: [TN] boards for high current loads
   =20
   =20
    Hello=20

    I have a number of requests on my desk where customers need some =
areas of=20
    boards with very thick copper (6 to 12 ounces for some heavy duty =
current)=20
    and the rest of the board with standard fineline features.=20

    Heavy duty plating ?? double imaging ?? etching through a bunch of =
copper ?=20
    none are attractive options.=20
    Any and all ideas on alternate processes would be appreciated.=20

    Thanks, Wolfgang=20

    [log in to unmask]  =20

   =20


------=_NextPart_000_00EB_01BF9A13.7F9090A0
Content-Type: text/html;
        charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>

<META content=3Dtext/html;charset=3Diso-8859-1 =
http-equiv=3DContent-Type><TITLE>boards for high current =
loads</TITLE><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 size=3D2>Morning Wolfgang &amp; All =
-</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>I've had fairly good success in the past using =
additive bus=20
bars which are installed on the board towards the end of the assembly=20
process.&nbsp; This helps to avoid difficulties both at the board =
fabrication=20
and the assembly stages.&nbsp; There are quite a number of suppliers of =
these=20
devices, or most board fabricators can etch custom forms to your design, =
from=20
copper sheet.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>The use of extremely heavy copper is possible, but =
it tends to=20
increase the probability of board warpage and also acts as a heat sink =
during=20
the assembly soldering process.&nbsp; If this approach is the only =
possibility,=20
then I would suggest you enlist your board fabricators assistance =
<U>before=20
design completion</U> in order to arrive at a solution both of you can =
live=20
with.&nbsp;&nbsp; There are several houses that do specialize in the =
heavy power=20
boards - all seem to have their own recipes for success.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>You may need to consider laminates with a higher Tg =
to=20
accomodate prolonged solder cycle durations.&nbsp; SMOBC on external =
conductors=20
is almost essential to prevent solder globs picking up on the heavy =
copper areas=20
during wave soldering.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Regards - Kelly</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 solid 2px; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
    <DIV><FONT face=3DArial size=3D2><B>-----Original =
Message-----</B><BR><B>From:=20
    </B>Erat, Wolfgang &lt;<A=20
    =
href=3D"mailto:[log in to unmask]">[log in to unmask]
</A>&gt;<BR><B>To:=20
    </B><A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> &lt;<A=20
    href=3D"mailto:[log in to unmask]">[log in to unmask]</A>&gt;<BR><B>Date:=20
    </B>Wednesday, March 29, 2000 12:28 PM<BR><B>Subject: </B>[TN] =
boards for=20
    high current loads<BR><BR></DIV></FONT>
    <P><FONT face=3D"Courier New" size=3D2>Hello </FONT></P>
    <P><FONT face=3D"Courier New" size=3D2>I have a number of requests =
on my desk=20
    where customers need some areas of</FONT> <BR><FONT face=3D"Courier =
New"=20
    size=3D2>boards with very thick copper (6 to 12 ounces for some =
heavy duty=20
    current)</FONT> <BR><FONT face=3D"Courier New" size=3D2>and the rest =
of the=20
    board with standard fineline features.</FONT> </P>
    <P><FONT face=3D"Courier New" size=3D2>Heavy duty plating ?? double =
imaging ??=20
    etching through a bunch of copper ?</FONT> <BR><FONT face=3D"Courier =
New"=20
    size=3D2>none are attractive options. </FONT><BR><FONT =
face=3D"Courier New"=20
    size=3D2>Any and all ideas on alternate processes would be =
appreciated.=20
    </FONT></P>
    <P><FONT face=3D"Courier New" size=3D2>Thanks, Wolfgang </FONT></P>
    <P><FONT face=3D"Courier New" size=3D2><A=20
    =
href=3D"mailto:[log in to unmask]">[log in to unmask]
</A>&nbsp;&nbsp;=20
    </FONT></P><BR></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_00EB_01BF9A13.7F9090A0--

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Date:         Thu, 30 Mar 2000 08:08:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Re: B/P Yields
X-To:         Darrel Therriault <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

In one word.  YES!    .200 thick parts with  holes that small will tend to
plug at HAL every time. It most likely will not affect every hole on a board
but I would bet it effects some holes on every board.  This is also very
difficult and time consuming to sort for. I would not be surprised if you
actually received some plugged hole even after your suppliers inspection.

ED Cosper

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Darrel Therriault
Sent: Wednesday, March 29, 2000 7:13 PM
To: [log in to unmask]
Subject: [TN] B/P Yields

Technetters/Fabricators,

My supplier is having a problem with yield on our backplane (~.200",
SMOBC/HASL).  It seems to be centering around
hole plugging from HASL.  FHS are .024", .028", .032" for both pressfit and
pth connectors.  Is this a typical problem for
these requirements??

If so, what are other finishes to consider to achieve higher yields but not
introduce large cost adders??

Comments and suggestions appreciated.

Tks........DT

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Date:         Thu, 30 Mar 2000 15:27:33 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: Sticky question
X-To:         Guenter Grossmann <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Guenter

According to Johann Lau's book on conductive adhesives, they are mainly
epoxy resins, although other resins may also be used. If you are very
interested in this subject, the book is fantastically good and covers
all aspects of conductive adhesives.

Best regards

Brian

Guenter Grossmann wrote:
>
> Hi all
>
> What polymers are used for anisotropic adhesives?
>
> Best regards
>
> Guenter
>
> Guenter Grossmann
> Swiss Federal Institute for Materials Testing and Research EMPA
> Centre for Reliability
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax :      xx41 1823 4054
> mail:     [log in to unmask]
>
> ##############################################################
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> information.
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> 847-509-9700 ext.5315
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Thu, 30 Mar 2000 14:23:57 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Matthew Lamkin <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Matthew Lamkin <[log in to unmask]>
Subject:      Re: [DC] Change Associated Files in NT4 SP6a
X-To:         "DesignerCouncil E-Mail Forum." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Try holding down "SHIFT" and right clicking on a .HGL file from within
Windows Explorer, then selecting
something like wordpad etc. & ticking the "always use this program" box.

This will remove the previous association & put it on a program that
you'd prefer it to be on.

Matthew Lamkin
Printed Circuitboard Draughtsman
Protec Fire Detection PLC.


>-----Original Message-----
>From:  Wolfe, Robert [SMTP:[log in to unmask]]
>Sent:  Wednesday, March 29, 2000 5:43 PM
>To:    [log in to unmask]
>Subject:       [DC] Change Associated Files in NT4 SP6a
>
>Need a little help.
>I have accidently set up an association for files with the .hgl extension
>for a program AutoView.
>If I go to My Computer/View/Options/File Types you can supposedly change
>this. However once there, there is no listing
>for the .hgl If you delete or Edit any of  the Autoview info you end up
>having to reinstall Autoview. If you try and make a new association with
>.hgl it tells you already in use as hgl_auto_file yet that is not listed in
>the files types either to be able to edit.
>Our MIS group had no answers either. All I want is to be able to undo the
>association of only the .hgl file type
>with any program and can' t seem to get there form here.
>TIA
>Bob
>Executone Inter-Tel Business Information Systems, Inc.
>Robert M. Wolfe C.I.D.
>Lead PCB Designer
>478 Wheelers Farms Road
>Milford, CT 06460
>Phone: 203-882-6405
>Fax:   203-882-2727
>Email: [log in to unmask]

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Date:         Thu, 30 Mar 2000 15:33:07 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cecilia Alkhagen (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cecilia Alkhagen (EMW)" <[log in to unmask]>
Subject:      Re: Sticky question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hello,

Just a little coorection! "Johan Liu" is the name of the author and the book is called "conductive adhesives for electronics packaging".

/Cecilia

-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: den 30 mars 2000 15:28
To: [log in to unmask]
Subject: Re: [TN] Sticky question


Guenter

According to Johann Lau's book on conductive adhesives, they are mainly
epoxy resins, although other resins may also be used. If you are very
interested in this subject, the book is fantastically good and covers
all aspects of conductive adhesives.

Best regards

Brian

Guenter Grossmann wrote:
>
> Hi all
>
> What polymers are used for anisotropic adhesives?
>
> Best regards
>
> Guenter
>
> Guenter Grossmann
> Swiss Federal Institute for Materials Testing and Research EMPA
> Centre for Reliability
> 8600 Duebendorf
> Switzerland
>
> Phone: xx41 1 823 4279
> Fax :      xx41 1823 4054
> mail:     [log in to unmask]
>
> ##############################################################
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> information.
> If you need assistance - contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ##############################################################

--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Thu, 30 Mar 2000 09:02:43 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Lee Whiteman <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Lee Whiteman <[log in to unmask]>
Subject:      Re: ESD Standards
X-To:         Ian Slater <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Here's a few ESD Standards for you. While some may be out of print, they are
still valuable references.

1. MIL-HDBK 263A - Electrostatic Discharge Handbook for Protection of
Electrical and Electronic Parts, Assemblies, and Equipment.

2. MIL-STD 1686B - Electrostatic Discharge Control Program for Protection of
Electrical and Electronic Parts, Assemblies, and Equipment.

3. EIA-625 - Requirements for Handling Electrostatic Discharge Sensitive
(ESDS) Devices.

4. NHB 5300.4 (3L) Requirements for Electrostatic Discharge Control.

5. ANSI/EOS/ESD-S3.1-1991 - For Protection of Electrostatic Discharge
Susceptible Items - Ionization.

6. EOS/ESD-S6.1-1991 - EOS/ESD Associated Standard for Protection of
Electrostatic Discharge Susceptible Items - Grounding-Recommended Practice

7. ESD-ADV3.2-1995 - ESD Association Advisory for Protection of
Electrostatic Discharge Susceptible Items - Selection and Acceptance of Air
Ionizers.

You may also wish to get a copy of these ESD related documents. They can be
found on the JEDEC Website: http://www.jedec.org/

1. JESD22-A114-A - Electrostatic Discharge Sensitivity Testing Human Body
Model.

2. JESD22-A115-A - Electrostatic Discharge Sensitivity Testing Machine
Model.

You may also wish to check out the documents on the ESD Association website:
http://www.borg.com/~eosesd/

If you have any additional questions, please give me a call.

Lee Whiteman
Senior Manufacturing Engineer
ACI / EMPF
Telephone: (610) 362-1200; Ext. 208
FAX: (610) 362-1290
E-Mail: [log in to unmask]

 -----Original Message-----
 From: TechNet [mailto:[log in to unmask]]On Behalf Of Ian Slater
 Sent: Wednesday, March 29, 2000 5:55 PM
 To: [log in to unmask]
 Subject: [TN] ESD Standards


 Can anyone recommend a set of ESD standards for electronics
 manufacturing?

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Date:         Thu, 30 Mar 2000 08:11:25 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Misner, Bruce" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Misner, Bruce" <[log in to unmask]>
Subject:      Re: Solder at lower temperature
X-To:         "Jan Merstrand (EMW)" <[log in to unmask]>

Jan,

The FET requires 2 things: excellent thermal path and wire bonds. AuSn
provides a thin interface with minimal voiding without flux (although N2
enviornment or blanket is required). This is good for both requirements and
hence has always been the material of choice in this situation, especially
for high rel applications (I see you are a Defense contractor). It also has
the added benefit of not leaching Au (because it already is 80% Au) and
allows additional processing of other areas of the assembly at solder temps
without reflowing the original interface. Unfortunately, I'm not familar
with acronim "DBC" for substrate (European vs American?).  If you can better
define this material I might be able to make other suggestions for FET
attach.

One last note is that FETs can reach high delta T junction temp. This
combined with the operating temp can bring the interface dangerously in the
range of typical solder (SN63) reflow temps.  Hope this helps.

Bruce Misner

> ----------
> From:         Jan Merstrand (EMW)[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Jan Merstrand (EMW)
> Sent:         Thursday, March 30, 2000 4:11 AM
> To:   [log in to unmask]
> Subject:      [TN] Solder at lower temperature
>
> Hi guys and girls!!
>
> I have a question that I think many of you can answer.
> Today we solder FET chips with Au/Sn solder onto a DBC substrate with Au
> surface.
> The soldering area of the FET is Chromium/Nickel/Silver.
>
> I want to replace the Au/Sn solder with "something else".. I don't want to
> glue the chip to place, only solder.
> The FET working temperature reaches up to 120degC.
>
> Any ideas on what kind of solder to use?
> __________________________________________________
> Jan Merstrand
> Microwave MCM, Design/Production Support
> Ericsson Microwave Systems AB. Defence Manufacturing
> Office address: Bergfotsgatan 2, SE-431 84 Mölndal
> Phone: +46 31 747 0725, Fax: +46 31 747 3515
>
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Date:         Thu, 30 Mar 2000 09:27:13 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Terveen, James @ NARDAEAST" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Terveen, James @ NARDAEAST" <[log in to unmask]>
Subject:      MMIC attach
MIME-Version: 1.0
Content-Type: text/plain

I need a little help on a new design that Eng.in coming up with.  They
would like to take an Alumina substrate and attach a MMIC to it.  The
substrate is a MicroBGA.  We have a clean room operation in our facility
and do wire bonding but I do not have enough knowledge on how this would
be done.  Whether to solder it or use epoxy.  and it either then what
would the material be.  So if anyone can help with how the mmic should
be attached to the substrate or direct me to some good literature it
would be greatly appreciated.

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Date:         Thu, 30 Mar 2000 09:49:29 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cash, Alan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cash, Alan" <[log in to unmask]>
Subject:      Re: ESD Standards
X-To:         Lee Whiteman <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

The new ESD Association  web site is www.esda.org.
MIL-STD 1686 is at Rev. C. The MIL-HDBK is at Rev.B and is out of date in
some areas such as classification of sensitivity of parts.  There is no
handbook for MIL-STD 1686C. ANSI/ESD S20.20 contains a complete listing of
the ESD Association standards and test methods and can be downloaded from
the web site. The standard also identifies the susceptibility test methods
for assemblies and equipment.

Al Cash
President
Midwest Chapter ESD Association
Chapter web page:  WWW.midwestesd.org
E-Mail:  [log in to unmask]
Phone:  847-259-9600 X 6764
-----Original Message-----
From: Lee Whiteman [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 8:03 AM
To: [log in to unmask]
Subject: Re: [TN] ESD Standards


Here's a few ESD Standards for you. While some may be out of print, they are
still valuable references.

1. MIL-HDBK 263A - Electrostatic Discharge Handbook for Protection of
Electrical and Electronic Parts, Assemblies, and Equipment.

2. MIL-STD 1686B - Electrostatic Discharge Control Program for Protection of
Electrical and Electronic Parts, Assemblies, and Equipment.

3. EIA-625 - Requirements for Handling Electrostatic Discharge Sensitive
(ESDS) Devices.

4. NHB 5300.4 (3L) Requirements for Electrostatic Discharge Control.

5. ANSI/EOS/ESD-S3.1-1991 - For Protection of Electrostatic Discharge
Susceptible Items - Ionization.

6. EOS/ESD-S6.1-1991 - EOS/ESD Associated Standard for Protection of
Electrostatic Discharge Susceptible Items - Grounding-Recommended Practice

7. ESD-ADV3.2-1995 - ESD Association Advisory for Protection of
Electrostatic Discharge Susceptible Items - Selection and Acceptance of Air
Ionizers.

You may also wish to get a copy of these ESD related documents. They can be
found on the JEDEC Website: http://www.jedec.org/

1. JESD22-A114-A - Electrostatic Discharge Sensitivity Testing Human Body
Model.

2. JESD22-A115-A - Electrostatic Discharge Sensitivity Testing Machine
Model.

You may also wish to check out the documents on the ESD Association website:
http://www.borg.com/~eosesd/

If you have any additional questions, please give me a call.

Lee Whiteman
Senior Manufacturing Engineer
ACI / EMPF
Telephone: (610) 362-1200; Ext. 208
FAX: (610) 362-1290
E-Mail: [log in to unmask]

 -----Original Message-----
 From: TechNet [mailto:[log in to unmask]]On Behalf Of Ian Slater
 Sent: Wednesday, March 29, 2000 5:55 PM
 To: [log in to unmask]
 Subject: [TN] ESD Standards


 Can anyone recommend a set of ESD standards for electronics
 manufacturing?

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=========================================================================
Date:         Thu, 30 Mar 2000 17:07:45 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Brian Ellis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Brian Ellis <[log in to unmask]>
Organization: Protonique SA
Subject:      Re: Sticky question
X-To:         "Cecilia Alkhagen (EMW)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Sorry, my memory fails me :(

Brian

"Cecilia Alkhagen (EMW)" wrote:
>
> Hello,
>
> Just a little coorection! "Johan Liu" is the name of the author and the book is called "conductive adhesives for electronics packaging".
>
> /Cecilia
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: den 30 mars 2000 15:28
> To: [log in to unmask]
> Subject: Re: [TN] Sticky question
>
> Guenter
>
> According to Johann Lau's book on conductive adhesives, they are mainly
> epoxy resins, although other resins may also be used. If you are very
> interested in this subject, the book is fantastically good and covers
> all aspects of conductive adhesives.
>
> Best regards
>
> Brian
>
> Guenter Grossmann wrote:
> >
> > Hi all
> >
> > What polymers are used for anisotropic adhesives?
> >
> > Best regards
> >
> > Guenter
> >
> > Guenter Grossmann
> > Swiss Federal Institute for Materials Testing and Research EMPA
> > Centre for Reliability
> > 8600 Duebendorf
> > Switzerland
> >
> > Phone: xx41 1 823 4279
> > Fax :      xx41 1823 4054
> > mail:     [log in to unmask]
> >
> > ##############################################################
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>
> --
> Brian Ellis
> Protonique SA
> PO Box 78
> CH-1032 Romanel-sur-Lausanne, Switzerland
> Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
> E-mail: [log in to unmask]
> URL: Technical and consultancy divisions:
>        http://www.protonique.com
>      Web services division:
>        http://www.protonique.com/webserv
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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Date:         Thu, 30 Mar 2000 09:13:02 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Misner, Bruce" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Misner, Bruce" <[log in to unmask]>
Subject:      Re: MMIC attach
X-To:         "Terveen, James @ NARDAEAST" <[log in to unmask]>

James,

Most MMIC devices are low power enough to mount with Ag epoxy, however,
unlike bipolar or CMOS devices, they typically are made of very thin
(.004-.006) GaAs and contain air bridges. This means they are brittle and
you cannot contact the top side of the die. Hence die attach must be done
with tweezers for very low volume or a custom die collet for higher volumes.
Epoxy amount is critical to maintain a thin (.001), uniform interface
thickness for RF performance and prevent epoxy from coming over the top of
the die or contaminating the collet... typical epoxy fillets will not be
maintained.

Wire bonding is atypical as well.  Ultrasonics tend to create microcracks or
worse and should be minimized. You can compensate for this through higher
substrate and/or bond tool temperatures.

Also be prepared for removing them from Gel Paks. You will probably need a
Gel Pak release station. Contact me off line if you need more help.

Best of Luck, they're a challenge,

Bruce Misner

> ----------
> From:         Terveen, James @
> NARDAEAST[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Terveen, James @ NARDAEAST
> Sent:         Thursday, March 30, 2000 9:27 AM
> To:   [log in to unmask]
> Subject:      [TN] MMIC attach
>
> I need a little help on a new design that Eng.in coming up with.  They
> would like to take an Alumina substrate and attach a MMIC to it.  The
> substrate is a MicroBGA.  We have a clean room operation in our facility
> and do wire bonding but I do not have enough knowledge on how this would
> be done.  Whether to solder it or use epoxy.  and it either then what
> would the material be.  So if anyone can help with how the mmic should
> be attached to the substrate or direct me to some good literature it
> would be greatly appreciated.
>
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Date:         Thu, 30 Mar 2000 10:29:55 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      SMT DEFECT RATES (DPMO)
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Dear Technet:

I've been tasked by my superiors to query industry to find out what other
electronic assemblers are yielding off of their surface mount line.  To
compare apples to apples, here are my specifics:

We assemble SMT for military/high rel.  The majority of the parts are
ceramic leadless chip carriers  (LCCs) and ceramic chip components
(resistors, caps, diodes).  We're starting to track solder defects more
closely when the assemblies come right off the line, and we don't like what
we see.  The major anomaly is insufficient solder fillet on the LCCs.
(There could be one joint insufficient out of 20. By the way, solder paste
deposits are perfect!)  Whether or not these are actually defects is under
discussion.

What I'd like to know is:
1)      What kind of defect rates (PPM) are others, building similar
assemblies, getting from their SMT lines.
2)      Does anyone experience insufficient solder on LCCs?

Thanks,
Jim M.
AIL Systems Inc.
631-595-5879

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Date:         Thu, 30 Mar 2000 17:49:13 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Jan Merstrand (EMW)" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Jan Merstrand (EMW)" <[log in to unmask]>
Subject:      Re: Solder at lower temperature
X-To:         "Misner, Bruce" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Bruce,
DBC stands for Direct Bonded Copper. It's a process where you plate Cu =
on substrates and often used in for example hightemp amp applications.=20
Stellar Industries is one of many who make this..  =
http://www.stellarind.com/5metllz.html

Yes I know, the FET needs a very good thermal path and wire bond.
To solder the FET with Au/Sn requires high temperature, but if a =
substrate has combined ThickFilm (to which you mount components with =
Ag-epoxy) with DBC (to which you solder the FET) and want to replace =
the FET. That's a problem.
Our Ag-epoxy don't appreciate high temperatures and you can't avoid =
heating up the surrounding components, when trying to remove the FET, =
because of the the concept (TF & DBC).=20
From there, I see two ways. Either replace the epoxy or replace the =
solder to one kind where the surrounding temperature, when removing =
FET, won't harm the Ag-epoxy. So, a low(-er) temperature solder around =
160-200degC would be nice.
Any ideas? Anyone?

__________________________________________________
Jan Merstrand
Microwave MCM, Design/Production Support
Ericsson Microwave Systems AB. Defence Manufacturing
Office address: Bergfotsgatan 2, SE-431 84 M=F6lndal
Phone: +46 31 747 0725, Fax: +46 31 747 3515



> -----Original Message-----
> From: Misner, Bruce [mailto:[log in to unmask]]
> Sent: den 30 mars 2000 16:11
> To: [log in to unmask]
> Subject: Re: [TN] Solder at lower temperature
>=20
>=20
> Jan,
>=20
> The FET requires 2 things: excellent thermal path and wire bonds. =
AuSn
> provides a thin interface with minimal voiding without flux=20
> (although N2
> enviornment or blanket is required). This is good for both=20
> requirements and
> hence has always been the material of choice in this=20
> situation, especially
> for high rel applications (I see you are a Defense=20
> contractor). It also has
> the added benefit of not leaching Au (because it already is=20
> 80% Au) and
> allows additional processing of other areas of the assembly=20
> at solder temps
> without reflowing the original interface. Unfortunately, I'm=20
> not familar
> with acronim "DBC" for substrate (European vs American?).  If=20
> you can better
> define this material I might be able to make other suggestions for =
FET
> attach.
>=20
> One last note is that FETs can reach high delta T junction temp. This
> combined with the operating temp can bring the interface=20
> dangerously in the
> range of typical solder (SN63) reflow temps.  Hope this helps.
>=20
> Bruce Misner
>=20
> > ----------
> > From:         Jan Merstrand=20
> (EMW)[SMTP:[log in to unmask]]
> > Reply To:     TechNet E-Mail Forum.;Jan Merstrand (EMW)
> > Sent:         Thursday, March 30, 2000 4:11 AM
> > To:   [log in to unmask]
> > Subject:      [TN] Solder at lower temperature
> >
> > Hi guys and girls!!
> >
> > I have a question that I think many of you can answer.
> > Today we solder FET chips with Au/Sn solder onto a DBC=20
> substrate with Au
> > surface.
> > The soldering area of the FET is Chromium/Nickel/Silver.
> >
> > I want to replace the Au/Sn solder with "something else"..=20
> I don't want to
> > glue the chip to place, only solder.
> > The FET working temperature reaches up to 120degC.
> >
> > Any ideas on what kind of solder to use?
> > __________________________________________________
> > Jan Merstrand
> > Microwave MCM, Design/Production Support
> > Ericsson Microwave Systems AB. Defence Manufacturing
> > Office address: Bergfotsgatan 2, SE-431 84 M=F6lndal
> > Phone: +46 31 747 0725, Fax: +46 31 747 3515
> >
> > ##############################################################
> > TechNet Mail List provided as a free service by IPC using=20
> LISTSERV 1.8c
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> > additional
> > information.
> > If you need assistance - contact Keach Sasamori at [log in to unmask] =
or
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>=20
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> for additional
> information.
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>=20

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Date:         Thu, 30 Mar 2000 11:09:30 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Edward J. Valentine" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Edward J. Valentine" <[log in to unmask]>
Subject:      Re: SMT DEFECT RATES (DPMO)
X-To:         "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Jim - A side question - Are you pretinning your LCC's?  If not, you should
seriously consider the pre-tinning operation, especially if the Gold
castellations are contaminated. You would know this ahead of time by
verifying the coverage after pre-tinning. And, in my experience, the
pretinning produced significantly better soldering results even though you
are adding additional process steps. Ed/

Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask]
Website: http://www.ems-consulting.com

----- Original Message -----
From: Marsico, James <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, March 30, 2000 10:29 AM
Subject: [TN] SMT DEFECT RATES (DPMO)


> Dear Technet:
>
> I've been tasked by my superiors to query industry to find out what other
> electronic assemblers are yielding off of their surface mount line.  To
> compare apples to apples, here are my specifics:
>
> We assemble SMT for military/high rel.  The majority of the parts are
> ceramic leadless chip carriers  (LCCs) and ceramic chip components
> (resistors, caps, diodes).  We're starting to track solder defects more
> closely when the assemblies come right off the line, and we don't like
what
> we see.  The major anomaly is insufficient solder fillet on the LCCs.
> (There could be one joint insufficient out of 20. By the way, solder paste
> deposits are perfect!)  Whether or not these are actually defects is under
> discussion.
>
> What I'd like to know is:
> 1)      What kind of defect rates (PPM) are others, building similar
> assemblies, getting from their SMT lines.
> 2)      Does anyone experience insufficient solder on LCCs?
>
> Thanks,
> Jim M.
> AIL Systems Inc.
> 631-595-5879
>
> ##############################################################
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Date:         Thu, 30 Mar 2000 11:15:13 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "Stephen R. Gregory" <[log in to unmask]>
Subject:      PCB Layout Service...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Hi ya'll!

I'm soliciting for some help, or maybe an opportunity for a design guru out
there. We've got a customer who has come to us to give some assistance and
input on a product they're developing...problem is, we don't do board layout.

It's a military customer who is building a ethernet hub unit for a armored
vehicle. The board is going to be about 5" X 6" and mixed technology, and
will go into a box.

From looking at the schematics, it has a 208-pin QFP, a PLCC or two, a few
DIP IC's, some PTH transformers, a bunch of passives, and a smattering of PTH
connectors. The customer asked me if I knew of any design houses that I could
recommend to do the layout. I know of a few back in California, but they
dealt mostly with commercial products, and as I said, this is military.

Is there anyone out there that would be willing to take the job on and is
familiar with military requirements? You can email me off-line and I'll give
my contact the information of how to get in touch with you. Oh by the way,
they wanted the layout done yesterday...(always that way huh?)

I'm coming to the TechNet for this request cause you're my "buddies"...

Thanks a bunch!

-Steve Gregory-

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Date:         Thu, 30 Mar 2000 11:27:40 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              James Barry <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         James Barry <[log in to unmask]>
Subject:      Re: PCB Layout Service...
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Try KADFLEX Myron Hastings (owner) 603-881-3000

-----Original Message-----
From: Stephen R. Gregory [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 11:15 AM
To: [log in to unmask]
Subject: [TN] PCB Layout Service...


Hi ya'll!

I'm soliciting for some help, or maybe an opportunity for a design guru out
there. We've got a customer who has come to us to give some assistance and
input on a product they're developing...problem is, we don't do board
layout.

It's a military customer who is building a ethernet hub unit for a armored
vehicle. The board is going to be about 5" X 6" and mixed technology, and
will go into a box.

From looking at the schematics, it has a 208-pin QFP, a PLCC or two, a few
DIP IC's, some PTH transformers, a bunch of passives, and a smattering of
PTH
connectors. The customer asked me if I knew of any design houses that I
could
recommend to do the layout. I know of a few back in California, but they
dealt mostly with commercial products, and as I said, this is military.

Is there anyone out there that would be willing to take the job on and is
familiar with military requirements? You can email me off-line and I'll give
my contact the information of how to get in touch with you. Oh by the way,
they wanted the layout done yesterday...(always that way huh?)

I'm coming to the TechNet for this request cause you're my "buddies"...

Thanks a bunch!

-Steve Gregory-

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Date:         Thu, 30 Mar 2000 08:36:00 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              peter blokhuis <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         peter blokhuis <[log in to unmask]>
Subject:      Re: Shipley Ronal No Accelerator Electroless Cu System
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii

Scott, in contrast to Rudy's comments, my experience
with this bath is that it ALWAYS builds up an excess
of tin and becomes unstable.  Monitoring the SG
closely, and then dumping half the bath volume when it
got too high, became a routine.


--- "Scott E. Stewart" <[log in to unmask]> wrote:
>      Hi Everyone,
>      I just wanted to get some opinions on Shipley
> Ronal's Electroless
>      Copper 3350 Process which uses no Accelerator.
> We manufacture PC
>      Boards with hole sizes .018" to .008" and were
> interested in finding
>      out what present users of this process and past
> users of this process
>      think about this process.  Have there been
> issues with small hole
>      voiding?
>
>      Regards,
>
>      S. Stewart
>
>
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__________________________________________________
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Date:         Thu, 30 Mar 2000 10:52:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Misner, Bruce" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Misner, Bruce" <[log in to unmask]>
Subject:      Re: SMT DEFECT RATES (DPMO)
X-To:         "Edward J. Valentine" <[log in to unmask]>

Jim,

I would have to agree with Ed. Pre-tinning should help immensly, just be
careful of leaching, although it shouldn't be a concern unless you plan on
recycling LCC's off reject boards.

Bruce Misner

> ----------
> From:         Edward J. Valentine[SMTP:[log in to unmask]]
> Reply To:     TechNet E-Mail Forum.;Edward J. Valentine
> Sent:         Thursday, March 30, 2000 11:09 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] SMT DEFECT RATES (DPMO)
>
> Jim - A side question - Are you pretinning your LCC's?  If not, you should
> seriously consider the pre-tinning operation, especially if the Gold
> castellations are contaminated. You would know this ahead of time by
> verifying the coverage after pre-tinning. And, in my experience, the
> pretinning produced significantly better soldering results even though you
> are adding additional process steps. Ed/
>
> Ed Valentine
> Electronics Manufacturing Solutions
> 8612 Mourning Dove Road, Raleigh, NC 27615
> Phone: (919) 270-5145, Fax: (919) 847-9971
> Email: [log in to unmask]
> Website: http://www.ems-consulting.com
>
> ----- Original Message -----
> From: Marsico, James <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Thursday, March 30, 2000 10:29 AM
> Subject: [TN] SMT DEFECT RATES (DPMO)
>
>
> > Dear Technet:
> >
> > I've been tasked by my superiors to query industry to find out what
> other
> > electronic assemblers are yielding off of their surface mount line.  To
> > compare apples to apples, here are my specifics:
> >
> > We assemble SMT for military/high rel.  The majority of the parts are
> > ceramic leadless chip carriers  (LCCs) and ceramic chip components
> > (resistors, caps, diodes).  We're starting to track solder defects more
> > closely when the assemblies come right off the line, and we don't like
> what
> > we see.  The major anomaly is insufficient solder fillet on the LCCs.
> > (There could be one joint insufficient out of 20. By the way, solder
> paste
> > deposits are perfect!)  Whether or not these are actually defects is
> under
> > discussion.
> >
> > What I'd like to know is:
> > 1)      What kind of defect rates (PPM) are others, building similar
> > assemblies, getting from their SMT lines.
> > 2)      Does anyone experience insufficient solder on LCCs?
> >
> > Thanks,
> > Jim M.
> > AIL Systems Inc.
> > 631-595-5879
> >
> > ##############################################################
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> additional
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> 847-509-9700 ext.5315
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>

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Date:         Thu, 30 Mar 2000 11:20:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Brad L. Matthies" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brad L. Matthies" <[log in to unmask]>
Organization: Raven Industries, Inc.
Subject:      Overhead Projection Inspection Equipment.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

TN,

I have been working with our QA department on an overlay project using
ESD mylar-like sheets for inspecting SMT boards for missing/extra
components post-reflow.  We were wondering if anyone knows of a system
that uses technology similar to an overhead projector to display
component locations onto the board surface for inspection?  We are
interested in this in place of the overlays.  I do not recall seeing
anything like this out at APEX recently, but our QA Manager says he has
seen something like this.  Any help would be appreciated.

BLM

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Date:         Thu, 30 Mar 2000 10:01:36 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: Overhead Projection Inspection Equipment.
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

this ain't exactly an overhead projection system, but it's close.  a company makes an optical inspection station that compares a known good board against another.  it alternately projects the good and the test board in the same field of view.  images that are missing or different in shape appear to flicker and are easy to spot.  if you are interested in the vendor, contact me off the net.

phil

-----Original Message-----
From: Brad L. Matthies [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 9:21 AM
To: [log in to unmask]
Subject: [TN] Overhead Projection Inspection Equipment.


TN,

I have been working with our QA department on an overlay project using
ESD mylar-like sheets for inspecting SMT boards for missing/extra
components post-reflow.  We were wondering if anyone knows of a system
that uses technology similar to an overhead projector to display
component locations onto the board surface for inspection?  We are
interested in this in place of the overlays.  I do not recall seeing
anything like this out at APEX recently, but our QA Manager says he has
seen something like this.  Any help would be appreciated.

BLM

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Date:         Thu, 30 Mar 2000 13:12:46 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Bev Christian <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Bev Christian <[log in to unmask]>
Subject:      Re: Solderability of TSOP...
X-To:         Phil Crepeau <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Haven't we had this discussion before?  My fear would be that following
Phil's advice will CREATE fractured solder joints.

Bev Christian
XLTEK

-----Original Message-----
From: Phil Crepeau [mailto:[log in to unmask]]
Sent: March 28, 2000 7:25 PM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


hi,

you should try to gently move each lead, side-to-side, with a fine needle.
this should find any fractured solder joint that your microscope may
overlook.

phil

-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 3:25 PM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


Bev,
You are right in catching and educating me on Alloy 42, lead material v/s
plating. As the data sheet doesn't show the lead material & plating for 44
pin TSOP, I have assumed that the plating will be same as 32 pin TSOP which
is copper leads.

We do not see any failure visually using regular microscope, it's a big
problem for us on this thin TSOP. If any of our technetters has found
similar situation and how it was resolved will help us in getting at the
bottom of the problem. I have asked Cypress for lead related info with type
of plating and will ask our test guy if they can nail it down to particular
pin for further microscopic inspection.

re,
ken patel

At 02:19 PM 3/28/2000 -0500, Bev Christian wrote:
>Ken,
>First I don't think you really mean to say the part leads are made with
>eutectic solder or Alloy 42.  The leads are either Alloy 42 or copper, with
>a lead finish of eutectic solder, other tin/lead solder alloy or maybe even
>TI palladium.
>
>So you have sufficient pads size for good fillets, good soldering of other
>parts, good profile and heel fillets.  Hmmm.  My question would then be, do
>the failures look like the lead has pulled right out of the fillet, with
>bare lead frame material showing.  If this is the case and the leads are
>indeed Alloy 42, then this has been seen before, is related to the final
>processing of the Alloy 42 and I think has been discussed here on TechNet.
>Check the archives.
>
>regards,
>Bev Christian
>XLTEK
>
>-----Original Message-----
>From: Ken Patel [mailto:[log in to unmask]]
>Sent: March 28, 2000 1:27 PM
>To: [log in to unmask]
>Subject: [TN] Solderability of TSOP...
>
>
>Guys,
>We have encountered problem related to component solderability, looks like!
>We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
>part has very small foot area which make a direct contact with the pad on
>the boards.
>
>The problem we have encountered is that many boards fail at ICT but will
>pass once we touch it up using solder iron. Solder at the TSOP location
>looks good and also in the surrounding vicinity. I do not see any profile
>problem. There is no toe fillet but I can see the heel filet rising on the
>lead. Pads are designed longer so that parts made by others can fit too.
>
>What can be possible causes of the problem? I tried look at the WEB but
>looks like parts are made using eutectic solder and not Alloy 42 but can't
>ruled out it was not specifically mentioned.
>
>
>re,
>ken patel
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
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>
______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Thu, 30 Mar 2000 10:26:04 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Phil Crepeau <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Phil Crepeau <[log in to unmask]>
Subject:      Re: Solderability of TSOP...
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

hi,

you are certainly correct about this, and i'm glad to have an opportunity to clarify the intention of my response.  this technique was offered as a tool to get to the bottom of a very strange situation where intermittents were being experienced yet there was no visual indication that the component lead-to-board connection was defective.  it has worked for me.

you definitely wouldn't want to do this as a normal inspection process.

phil

-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 10:13 AM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


Haven't we had this discussion before?  My fear would be that following
Phil's advice will CREATE fractured solder joints.

Bev Christian
XLTEK

-----Original Message-----
From: Phil Crepeau [mailto:[log in to unmask]]
Sent: March 28, 2000 7:25 PM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


hi,

you should try to gently move each lead, side-to-side, with a fine needle.
this should find any fractured solder joint that your microscope may
overlook.

phil

-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Tuesday, March 28, 2000 3:25 PM
To: [log in to unmask]
Subject: Re: [TN] Solderability of TSOP...


Bev,
You are right in catching and educating me on Alloy 42, lead material v/s
plating. As the data sheet doesn't show the lead material & plating for 44
pin TSOP, I have assumed that the plating will be same as 32 pin TSOP which
is copper leads.

We do not see any failure visually using regular microscope, it's a big
problem for us on this thin TSOP. If any of our technetters has found
similar situation and how it was resolved will help us in getting at the
bottom of the problem. I have asked Cypress for lead related info with type
of plating and will ask our test guy if they can nail it down to particular
pin for further microscopic inspection.

re,
ken patel

At 02:19 PM 3/28/2000 -0500, Bev Christian wrote:
>Ken,
>First I don't think you really mean to say the part leads are made with
>eutectic solder or Alloy 42.  The leads are either Alloy 42 or copper, with
>a lead finish of eutectic solder, other tin/lead solder alloy or maybe even
>TI palladium.
>
>So you have sufficient pads size for good fillets, good soldering of other
>parts, good profile and heel fillets.  Hmmm.  My question would then be, do
>the failures look like the lead has pulled right out of the fillet, with
>bare lead frame material showing.  If this is the case and the leads are
>indeed Alloy 42, then this has been seen before, is related to the final
>processing of the Alloy 42 and I think has been discussed here on TechNet.
>Check the archives.
>
>regards,
>Bev Christian
>XLTEK
>
>-----Original Message-----
>From: Ken Patel [mailto:[log in to unmask]]
>Sent: March 28, 2000 1:27 PM
>To: [log in to unmask]
>Subject: [TN] Solderability of TSOP...
>
>
>Guys,
>We have encountered problem related to component solderability, looks like!
>We are using Cypress Semi TSOP (SRAM-SM 71016 64kx16, ASYNC TSOP-44). This
>part has very small foot area which make a direct contact with the pad on
>the boards.
>
>The problem we have encountered is that many boards fail at ICT but will
>pass once we touch it up using solder iron. Solder at the TSOP location
>looks good and also in the surrounding vicinity. I do not see any profile
>problem. There is no toe fillet but I can see the heel filet rising on the
>lead. Pads are designed longer so that parts made by others can fit too.
>
>What can be possible causes of the problem? I tried look at the WEB but
>looks like parts are made using eutectic solder and not Alloy 42 but can't
>ruled out it was not specifically mentioned.
>
>
>re,
>ken patel
>______________________________________________________
>Ken Patel                       Phone:  (408) 490-6804
>1708 McCarthy Blvd.             Fax:    (408) 490-6859
>Milpitas, CA 95035              Beeper: (888) 769-1808
>
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______________________________________________________
Ken Patel                       Phone:  (408) 490-6804
1708 McCarthy Blvd.             Fax:    (408) 490-6859
Milpitas, CA 95035              Beeper: (888) 769-1808

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Date:         Thu, 30 Mar 2000 13:18:42 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cash, Alan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cash, Alan" <[log in to unmask]>
Subject:      Re: Overhead Projection Inspection Equipment.
X-To:         "Brad L. Matthies" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Try Manix they marketed an overhead projection system some years ago. I
believe that they were purchased and have a different name.

Al Cash

-----Original Message-----
From: Brad L. Matthies [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 11:21 AM
To: [log in to unmask]
Subject: [TN] Overhead Projection Inspection Equipment.


TN,

I have been working with our QA department on an overlay project using
ESD mylar-like sheets for inspecting SMT boards for missing/extra
components post-reflow.  We were wondering if anyone knows of a system
that uses technology similar to an overhead projector to display
component locations onto the board surface for inspection?  We are
interested in this in place of the overlays.  I do not recall seeing
anything like this out at APEX recently, but our QA Manager says he has
seen something like this.  Any help would be appreciated.

BLM

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Date:         Thu, 30 Mar 2000 13:21:19 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Cash, Alan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Cash, Alan" <[log in to unmask]>
Subject:      Re: Overhead Projection Inspection Equipment.
X-To:         "Brad L. Matthies" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

See contact systems for an overhead projection system with parts carousels


Al Cash
-----Original Message-----
From: Brad L. Matthies [mailto:[log in to unmask]]
Sent: Thursday, March 30, 2000 11:21 AM
To: [log in to unmask]
Subject: [TN] Overhead Projection Inspection Equipment.


TN,

I have been working with our QA department on an overlay project using
ESD mylar-like sheets for inspecting SMT boards for missing/extra
components post-reflow.  We were wondering if anyone knows of a system
that uses technology similar to an overhead projector to display
component locations onto the board surface for inspection?  We are
interested in this in place of the overlays.  I do not recall seeing
anything like this out at APEX recently, but our QA Manager says he has
seen something like this.  Any help would be appreciated.

BLM

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Date:         Fri, 31 Mar 2000 07:41:55 +0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Michael T. Andres" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
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Subject:      Aknowledgement

Thank you for sending me an e-mail.
Good Luck and may God Bless you always...

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Date:         Thu, 30 Mar 2000 19:36:51 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         [log in to unmask]
Subject:      Re: SMT DEFECT RATES (DPMO)
X-To:         [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit

Jim:  How are you?  Hope all is well!!!  If you could forward any information
to me regarding your task of determining "acceptable" or "realististic"
reject rates I would sincerely appreciate it.  Do you have any type of
deadline you are working under?  If I can help you in any way, let me know!!!
  Best Regards, Bill Black

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Date:         Thu, 30 Mar 2000 17:01:47 -0800
Reply-To:     Karl Sauter <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Karl Sauter <[log in to unmask]>
Subject:      Re: Spec for "Lumps" on PCB
MIME-Version: 1.0
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Mike,

I am not aware of any industry specification.  We specify that
maximum soldermask/plugmask height on finished PWBs shall not
exceed 0.0025 inches over copper.

Regards,
Karl Sauter
Sun Microsystems
[log in to unmask]


> Date: Thu, 2 Mar 2000 12:19:31 -0500
> From: Michael Forrester <[log in to unmask]>
> Subject: [TN] Spec for "Lumps" on PCB
> To: [log in to unmask]
>
> Our boards are primarily fine pitch surface mount.  We currently have a
> problem with the height of the solder mask over our via's being too high
> causing the solder stencil not to sit flat to the board.  The height of
> the vias solder mask included) are 4 mils higher than the rest of the
> board (including solder mask  I believe the actual problem is that we
> have the vias filled with epoxy and the height of the epoxy in relation
> to the top of the via pad is too high.  Is there a spec (IPC,JEDIC,MIL)
> that covers such an issue?  If not, what do others spec out to insure
> that there is no interference from "lumps".  Thank you.
>
> Best Regards,
>
> Mike Forrester
> LeCroy Corp.
> [log in to unmask]
>
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Date:         Thu, 30 Mar 2000 20:27:07 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Craig Ropp <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Craig Ropp <[log in to unmask]>
Subject:      Re: Spec for "Lumps" on PCB
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable

Michael,
If I understand your question regarding a Specification for Guidance =
please refer to the following: IPC-SM-840C>>>> SEC 3.4.8 2nd paragraph =
references uniform in appearance, free of foreign  materials, and =
roughness which would interfere with assembly. You may also want to review =
SEC 6.7 on hole plugging- via protection. I hope this information is =
beneficial.
Thanks,=20
Craig Ropp=20

>>> [log in to unmask] 3/2/00 11:19:31 AM >>>
Our boards are primarily fine pitch surface mount.  We currently have a =
problem
with the height of the solder mask over our via's being
too high causing the solder stencil not to sit flat to the board.  The =
height of
the vias solder mask included) are 4 mils higher than the rest
of the board (including solder mask  I believe the actual problem is that =
we
have the vias filled with epoxy and the
height of the epoxy in relation to the top of the via pad is too high.  Is =
there
a spec (IPC,JEDIC,MIL) that covers such an issue?  If not, what
do others spec out to insure that there is no interference from "lumps".  =
Thank
you.

Best Regards,

Mike Forrester
LeCroy Corp.
[log in to unmask]

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Date:         Thu, 30 Mar 2000 22:01:59 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Creswick <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Creswick <[log in to unmask]>
Subject:      Re: Solder at lower temperature
X-To:         "Jan Merstrand (EMW)" <[log in to unmask]>
Mime-Version: 1.0
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Jan,

Actally, there are many solders within range of termperatures which you
specify.  However, practically, I am not so sure I would recommend any to
you without knowing the requirements of your system.

You probably already knew that MOSFET manufacturers normally attach their
devices to copper slugs using high lead alloys such as Sn10Pb88Ag2,
Sn10Pb90, Sn5/Pb95 or other variations incorporating Indium as well.  Check
data books or web sites for International Rectifier, XYIS, and others.  Each
of these alloys has the benefit of being very ductile, absorbing the thermal
coefficient of expansion mis-match between the high expansion copper slug
and the low expansion silicon chip - allowing the device to survive many
power cycles.  On the other hand, most of these alloys melt at 300+=B0C and
need to be reflowed in a hydrogen or reducing atmosphere. Thermal
conductivity is so so, but the joint isn't more than 25-50um thick, so it
becomes relatively negligible, if it is void free.

By going to any number of SnPb, SnAg, or SnPbAg alloys you will gain the
decreased liquidus temperature which you desire, but give up much of the
ductility of the traditional high lead alloys.  However, since you are
currently using AuSn, you don't have a very ductile system in the first
place - the redeeming grace is that the composite thermal expansion of the
DBC substrate (~7-10ppm/=B0C - depending on foil to ceramic ratio) is much
closer to the silicon (2-3ppm/=B0C) than copper (17-18ppm/=B0C).   Net=
 result
after device attachment, the device is under compression - better than the
opposite!

If your substrate were aluminum nitride (4-5ppm/=B0C) the structure could be
even better.  But, not knowing your design etc. this may not be suitable to
your application.  I believe that Brush Wellman (and maybe Stellar) did
offer the effective equivalent of DBC on AlN. =20

In either case, if you choose to go to a Sn, Pb, or In bearing alloy go
lightly on the gold plating, unless it is required elsewhere for wire
bonding.  =20
PbIn or other alloys.  Daughter-boards alleviate some of these problems, but
may create others.  There should always be a nickel plating layer between
the copper and the gold.

The traditional Pb/In alloys work well for this application, but it sure
helps to have hydrogen or reducing atmosphere reflow capability.  Fluxes do
a great job of creating voids!  Scientific Sealing Technology vacuum reflow
equipment also is a big benefit, but again, thou shalt not use flux!

Depending upon the circuit, in some fault conditions, the junctions can get
rather hot - hot enough to melt Sn63!  Consider what safeguard you require
in the event of a fault?

Review your solder preform manufacturer's selection of alloys for one within
your temperature range.  Consider your system requirements, and any
re-qualification liabilities.  If you still wish to proceed, buy some ribbon
stock of the alloy/s you wish to evaluate.  Cut them to size manually, and
attach some devices.  Acoustically, or x-ray scan the interface for voiding.
Do some die shear and power cycling of the devices.

To conclude - even though the AuSn causes you repairablity problems, please
attack the problem with your eyes wide open.  Sometimes, low temp solders in
situations like this can be too good to be true.  Be careful!

Steve









At 11:11 AM 3/30/00 +0200, you wrote:
>Hi guys and girls!!
>
>I have a question that I think many of you can answer.
>Today we solder FET chips with Au/Sn solder onto a DBC substrate with Au
surface.
>The soldering area of the FET is Chromium/Nickel/Silver.
>
>I want to replace the Au/Sn solder with "something else".. I don't want to
glue the chip to place, only solder.
>The FET working temperature reaches up to 120degC.
>
>Any ideas on what kind of solder to use?=20
>__________________________________________________
>Jan Merstrand
>Microwave MCM, Design/Production Support
>Ericsson Microwave Systems AB. Defence Manufacturing
>Office address: Bergfotsgatan 2, SE-431 84 M=F6lndal
>Phone: +46 31 747 0725, Fax: +46 31 747 3515
>
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Date:         Thu, 30 Mar 2000 22:02:02 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Creswick <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Creswick <[log in to unmask]>
Subject:      Re: MMIC attach
X-To:         "Terveen, James @ NARDAEAST" <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"

James,

We would normally attach a uBGA with a mimimal amount of tacky flux to hold
in it place during reflow.  Depending on whos uBGA it is, and how it is
constructed, some will also underfill the finished part.

I always try to keep soldering and wirebonding as far apart as possible.
Soldering in a clean room many times makes it an 'un-clean' room unless the
reflow equipment is properly vented and maintained.

Check out Tessera's web page for their uBGA.  You are likely to find
processing guidelines there as well.

Steve




At 09:27 AM 3/30/00 -0500, you wrote:
>I need a little help on a new design that Eng.in coming up with.  They
>would like to take an Alumina substrate and attach a MMIC to it.  The
>substrate is a MicroBGA.  We have a clean room operation in our facility
>and do wire bonding but I do not have enough knowledge on how this would
>be done.  Whether to solder it or use epoxy.  and it either then what
>would the material be.  So if anyone can help with how the mmic should
>be attached to the substrate or direct me to some good literature it
>would be greatly appreciated.
>
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Date:         Fri, 31 Mar 2000 09:34:49 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Guenter Grossmann <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Guenter Grossmann <[log in to unmask]>
Subject:      Antw: Re: [TN] Sticky question
X-To:         [log in to unmask]
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Hi Brian

Thanks a lot for your answer.=20
Is it really so that also the anisotropic conductive adhesives ( those =
conducting only in the Z-axis when pressed together with heat ) are of =
Epoxy?
By the way, it's good you escaped Switzerland. Have you ever seen any =
weather report? Brrrrrrrrrrrrrr.

All the best

Guenter

Guenter Grossmann
Swiss Federal Institute for Materials Testing and Research EMPA
Centre for Reliability
8600 Duebendorf
Switzerland

Phone: xx41 1 823 4279
Fax :      xx41 1823 4054
mail:     [log in to unmask]

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Date:         Fri, 31 Mar 2000 10:01:17 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              =?iso-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         =?iso-8859-1?Q?TOE_/Torben_=D8steraa?= <[log in to unmask]>
Subject:      oxide alternatives
MIME-Version: 1.0
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Dear TechNetters,=20

It seems that the 'oxide alternatives' all have a problem
processing rolled copper (RA), as e.g. used fore some flex
constructions. Due to the different structure, there is hardly
any coloring, and the surface structure must also be quite different.

Does this mean we are stuck with the oxides?. If not, what
alternatives are available.? That is, apart from doing
nothing.=20

regards

Torben =D8steraa
Printca AS

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Date:         Fri, 31 Mar 2000 07:22:13 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Marsico, James" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Marsico, James" <[log in to unmask]>
Subject:      Re: SMT DEFECT RATES (DPMO)
X-To:         "Misner, Bruce" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

The LCCs we use are all pre-tinned.  If not received that way, we send them
out to a tinning house.
Thanks,
Jim M.


        -----Original Message-----
        From:   Misner, Bruce [SMTP:[log in to unmask]]
        Sent:   Thursday, March 30, 2000 11:52 AM
        To:     [log in to unmask]
        Subject:        Re: [TN] SMT DEFECT RATES (DPMO)

        Jim,

        I would have to agree with Ed. Pre-tinning should help immensly,
just be
        careful of leaching, although it shouldn't be a concern unless you
plan on
        recycling LCC's off reject boards.

        Bruce Misner

        > ----------
        > From:         Edward J. Valentine[SMTP:[log in to unmask]]
        > Reply To:     TechNet E-Mail Forum.;Edward J. Valentine
        > Sent:         Thursday, March 30, 2000 11:09 AM
        > To:   [log in to unmask]
        > Subject:      Re: [TN] SMT DEFECT RATES (DPMO)
        >
        > Jim - A side question - Are you pretinning your LCC's?  If not,
you should
        > seriously consider the pre-tinning operation, especially if the
Gold
        > castellations are contaminated. You would know this ahead of time
by
        > verifying the coverage after pre-tinning. And, in my experience,
the
        > pretinning produced significantly better soldering results even
though you
        > are adding additional process steps. Ed/
        >
        > Ed Valentine
        > Electronics Manufacturing Solutions
        > 8612 Mourning Dove Road, Raleigh, NC 27615
        > Phone: (919) 270-5145, Fax: (919) 847-9971
        > Email: [log in to unmask]
        > Website: http://www.ems-consulting.com
        >
        > ----- Original Message -----
        > From: Marsico, James <[log in to unmask]>
        > To: <[log in to unmask]>
        > Sent: Thursday, March 30, 2000 10:29 AM
        > Subject: [TN] SMT DEFECT RATES (DPMO)
        >
        >
        > > Dear Technet:
        > >
        > > I've been tasked by my superiors to query industry to find out
what
        > other
        > > electronic assemblers are yielding off of their surface mount
line.  To
        > > compare apples to apples, here are my specifics:
        > >
        > > We assemble SMT for military/high rel.  The majority of the
parts are
        > > ceramic leadless chip carriers  (LCCs) and ceramic chip
components
        > > (resistors, caps, diodes).  We're starting to track solder
defects more
        > > closely when the assemblies come right off the line, and we
don't like
        > what
        > > we see.  The major anomaly is insufficient solder fillet on the
LCCs.
        > > (There could be one joint insufficient out of 20. By the way,
solder
        > paste
        > > deposits are perfect!)  Whether or not these are actually
defects is
        > under
        > > discussion.
        > >
        > > What I'd like to know is:
        > > 1)      What kind of defect rates (PPM) are others, building
similar
        > > assemblies, getting from their SMT lines.
        > > 2)      Does anyone experience insufficient solder on LCCs?
        > >
        > > Thanks,
        > > Jim M.
        > > AIL Systems Inc.
        > > 631-595-5879
        > >
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Date:         Fri, 31 Mar 2000 07:46:35 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Rick Babyak <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Rick Babyak <[log in to unmask]>
Subject:      via plugging
MIME-Version: 1.0
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Is there any acceptance criteria or a spec out there that covers via
plugging with mask/ink?



Rick Babyak
Process Engineer
Proto Circuit Inc.
7 Ascot Parkway
Cuyahoga Falls, OH 44223
330-572-3401  Fax:330-572-3434
[log in to unmask]

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Date:         Fri, 31 Mar 2000 15:24:48 +0200
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Grant Emandien <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Grant Emandien <[log in to unmask]>
Subject:      Use of reclaimed devices
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi all,

I noticed in a forum contributor's email the practice of using reclaimed
ICs. Surely this is not accepted practice. I ask this because a supplier of
ours had requested the possibility of doing this as he had a shortage on the
ICs in question and the fact that they were particularly expensive.

Needless to say, we rejected this notion as we are clueless on the
consequences of such practice.

Regards
Grant

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Date:         Fri, 31 Mar 2000 08:53:43 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Terveen, James @ NARDAEAST" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Terveen, James @ NARDAEAST" <[log in to unmask]>
Subject:      gold immersion plating
MIME-Version: 1.0
Content-Type: text/plain

I have seen this process (gold immersion plating) mentioned many times
on different postings.  Can someone explain this process to me so a
person of little or no understanding can understand.  Or direct me to
some articles or literature to help me understand.

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Date:         Fri, 31 Mar 2000 09:05:19 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "(George  Milad)" <[log in to unmask]>
Subject:      Plating Subcommitte meeting at IPC-Expo
MIME-Version: 1.0
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The IPC Imaging/Developing Subcommittee (4-13) has organized a discussion
group
during the Spring IPC EXPO in San Diego on "Developing Photoresists for Fine
Line Applications".

The IPC Plating Subcommittee (4-14)  welcomes all PCB manufacturers, who wish
to be involved in the creation of a "Gold Standard" to replace the defunct
Mil Spec.

Mike Toben who is heading the same effort for the ASTM will share with the
group where that team is to-day. Ideally IPC, MilSpec and ASTM would be in
agreement.

The meeting is scheduled for Monday April 3 from 1:30 to 3:00 pm in
conjunction with the IPC-Expo in San Diego.  The meeting location will be in
the final program in the Committee Meeting section.
Subcommittee Chair
George Milad
Shipley Co.

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Date:         Fri, 31 Mar 2000 09:09:48 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "(George  Milad)" <[log in to unmask]>
Subject:      New Gold Standard IPC Plating Subcommittee (4-14)
MIME-Version: 1.0
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The IPC Plating Subcommittee (4-14) is presently working on a new Gold
Standard.
If you are interested in participating, attending or contributing to this
Standard, come to the meeting.
The meeting is scheduled for Monday April 3 from 1:30 to 3:00 pm in
conjunction with the IPC-Expo in San Diego.  The meeting location will be in
the final program in the Committee Meeting section.
Subcommittee Chair
George Milad
Shipley Co.

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Date:         Fri, 31 Mar 2000 09:16:40 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Available used plotter
MIME-Version: 1.0
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HI all,

Several weeks ago I posted that I had a used plotter that we had just
replaced and we wanted to see if anyone would like to pick up a very
reasonable price.  Several of you inquired about the plotter and asked for
specifics.

As previously mentioned,  we no longer need it and really don't want to
store it. It was working fine when we uninstalled it and has been producing
all of our tools for the last few years. We would like to see it go to a
good home and be used. Obviously it will be sold "As is" with no warrantee.
Another important note is that this plotter has been maintained under a
maintenance contract with Barco/Gerber since it has been here. If you have
any questions regarding the condition of this equipment at the time it was
un installed, please feel free to contact Art Malcomb at Barco.  His email
is [log in to unmask]

The plotter is as follows:


GERBER  Model 28 9528Sturbo (English)
Age: Approx: 1990
Min resolution:  Dual resolution: 2500dpi/5000 dpi software selectable
Min aperture size it can plot:  .002"
Type of laser:  Blue light 488nm  air cooled argon ion
Film Size it can handle:  up to 20x26

If anyone is interested, please feel free to contact me offline. I'm looking
for any reasonable offer. The purchasing party will have to take care of the
freight.

Ed Cosper
American Board Companies, inc.
Vestal, NY

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Date:         Fri, 31 Mar 2000 09:26:42 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Rudy Sedlak>" <[log in to unmask]>
Subject:      Re: gold immersion plating--An attempted explanation
X-To:         [log in to unmask]
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James:

Metals in solution are too low in electrons, and thus have a positive charge.
 Solid metals, in their shiney form, have the proper number of electrons.
When a more "active" metal (meaning a metal that does not bind its electrons
tightly) is immersed into a solution of a metal that does bind its electrons
tightly, like Gold, the electrons shift from the substrate metal, (the
substrate under Gold is almost always Nickel) to the metal in solution,
causing the metal in solution to plate out spontaneously on to the substrate
metal....in other words, a Nickel coated PCB, when immersed into a solution
of Gold, will cause the Gold to plate out spontaneously on to the Nickel, and
in the process some of the Nickel is dissolved and goes into solution.

This continues until the substrate Nickel is covered, and no more Nickel is
available for this chemical reaction, and you wind up with around 7-8
microinches (0.2 micron) of Gold from this type of plating.

Hope this helped...

Rudy Sedlak
RD Chemical Company

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Date:         Fri, 31 Mar 2000 09:28:07 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Dennis Fritz>" <[log in to unmask]>
Subject:      Re: gold immersion plating
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Immersion plating is a chemical replacement reaction between two metals.  The
reaction is driven by the difference in electromotive potential between the
metals (sort of like a reverse battery).  The more noble metal is deposited,
and the other metal dissolved into solution.  As gold is the most noble
element, it will immersion plate on most other metals, (given that a proper
electrolyte and complexing chemical is present for the dissolving metal).
The key is finding  electrolytes that can "hold" both the metal to be plated
and the species to be dissolved - over time and at high capacity.

In the most common application on circuit boards, previously plated
electroless nickel is dissolved and gold deposited to give "electroless
nickel/immersion gold" surface finishes.  Other immersion reactions common
are Immersion silver and immersion tin (copper being replaced in both
reactions).

Denny Fritz
MacDermid, Inc
Waterbury, CT

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Date:         Fri, 31 Mar 2000 06:52:51 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mike Bailey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mike Bailey <[log in to unmask]>
Subject:      Re: via plugging
X-To:         Rick Babyak <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

I haven't seen any industry guidelines, however, occasionally a customer who
has been "burned" will specify .002 max.  This is achievable with straight
masking operations.  If performing separate "postplugging" operations after
primary mask application and surface finishing etc., it's important to
insure that the primary mask has a clearance at the location that is to be
postplugged.  Otherwise if the hole is partially plugged etc., the secondary
masking operation will leave a very undesirable bump approx. .005-.006 high.
These specialized operations drive inspectors and CAM operators absolutely
crazy. Additionally, most customers are neither consistent with their data
or assembly needs.  Typically, the masking information is the least
considered by a designer.  Couple this with third party contract assemblers
and you have numerous opportunities for error.

Mike Bailey
Director of Engineering
McCurdy Circuits Inc.
4900 E. Hunter Ave.
Anaheim, CA  92870
Phone: 714 507-4900 Ext 253
FAX: 714 507-4911
e-mail: [log in to unmask] <mailto:[log in to unmask]>

-----Original Message-----
From: Rick Babyak [mailto:[log in to unmask]]
Sent: Friday, March 31, 2000 4:47 AM
To: [log in to unmask]
Subject: [TN] via plugging


Is there any acceptance criteria or a spec out there that covers via
plugging with mask/ink?



Rick Babyak
Process Engineer
Proto Circuit Inc.
7 Ascot Parkway
Cuyahoga Falls, OH 44223
330-572-3401  Fax:330-572-3434
[log in to unmask]

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Date:         Fri, 31 Mar 2000 09:49:14 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         "<Dennis Fritz>" <[log in to unmask]>
Subject:      Re: oxide alternatives
X-To:         [log in to unmask]
MIME-Version: 1.0
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In a message dated 00-03-31 03:03:48 EST, you write:

<< It seems that the 'oxide alternatives' all have a problem
 processing rolled copper (RA), as e.g. used fore some flex
 constructions. Due to the different structure, there is hardly
 any coloring, and the surface structure must also be quite different. >>

The reason for the different "look" is that oxide alternatives, unlike oxide,
attack the copper at grain boundaries. Oxide alternatives do very well with
the columnar grains of ED & HTE foils, and with the equiaxial acid copper
deposits seen with buried via layers.  The coating on RA foil varies, as
different RA foils have different final grain
structures.  It is seen that the amount of annealing is significant in
this respect.  With many RA foils, the oxide alternative coating is
irregular, paler than
usual.

But it bonds!!!  Some flex and flex-rigid customers who run the
process,  are happy with it.  Some customers have received Military
approval for flex which is bonded with oxide alternative.  So, flex and
flex-rigid
users are NOT stuck with oxide after all, which is good because they suffer
more from the limited material compatibilities (sensitive to hot alkali) of
oxide than most
fabricators.  If cosmetic issues become important, shopping around for RA's
which will coat more uniformly should resolve the problem.

Denny Fritz
MacDermid

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Date:         Fri, 31 Mar 2000 08:08:01 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ryan Grant <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ryan Grant <[log in to unmask]>
Subject:      Re: via plugging

Mike,
        What is the "primary mask clearance at the location to be
postplugged" requirements?  I would like to pass this information on to our
DFM guys.

Thanks
Ryan Grant

> -----Original Message-----
> From: Mike Bailey [SMTP:[log in to unmask]]
> Sent: Friday, March 31, 2000 7:53 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] via plugging
>
> I haven't seen any industry guidelines, however, occasionally a customer
> who
> has been "burned" will specify .002 max.  This is achievable with straight
> masking operations.  If performing separate "postplugging" operations
> after
> primary mask application and surface finishing etc., it's important to
> insure that the primary mask has a clearance at the location that is to be
> postplugged.  Otherwise if the hole is partially plugged etc., the
> secondary
> masking operation will leave a very undesirable bump approx. .005-.006
> high.
> These specialized operations drive inspectors and CAM operators absolutely
> crazy. Additionally, most customers are neither consistent with their data
> or assembly needs.  Typically, the masking information is the least
> considered by a designer.  Couple this with third party contract
> assemblers
> and you have numerous opportunities for error.
>
> Mike Bailey
> Director of Engineering
> McCurdy Circuits Inc.
> 4900 E. Hunter Ave.
> Anaheim, CA  92870
> Phone: 714 507-4900 Ext 253
> FAX: 714 507-4911
> e-mail: [log in to unmask] <mailto:[log in to unmask]>
>
> -----Original Message-----
> From: Rick Babyak [mailto:[log in to unmask]]
> Sent: Friday, March 31, 2000 4:47 AM
> To: [log in to unmask]
> Subject: [TN] via plugging
>
>
> Is there any acceptance criteria or a spec out there that covers via
> plugging with mask/ink?
>
>
>
> Rick Babyak
> Process Engineer
> Proto Circuit Inc.
> 7 Ascot Parkway
> Cuyahoga Falls, OH 44223
> 330-572-3401  Fax:330-572-3434
> [log in to unmask]
>
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Date:         Fri, 31 Mar 2000 16:56:00 +0100
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Martin Christie <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Martin Christie <[log in to unmask]>
Subject:      Re: gold immersion plating--An attempted explanation
Mime-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
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Rudy,

From your explanation I would assume that this process is self limiting in
terms of the amount of the deposit i.e. where you get the 0.2 micron Gold
deposit from.

Am I correct in assuming this?

Martin Christie
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
31/03/00 09:26
>James:
>
>Metals in solution are too low in electrons, and thus have a positive charge.
> Solid metals, in their shiney form, have the proper number of electrons.
>When a more "active" metal (meaning a metal that does not bind its electrons
>tightly) is immersed into a solution of a metal that does bind its electrons
>tightly, like Gold, the electrons shift from the substrate metal, (the
>substrate under Gold is almost always Nickel) to the metal in solution,
>causing the metal in solution to plate out spontaneously on to the substrate
>metal....in other words, a Nickel coated PCB, when immersed into a solution
>of Gold, will cause the Gold to plate out spontaneously on to the Nickel, and
>in the process some of the Nickel is dissolved and goes into solution.
>
>This continues until the substrate Nickel is covered, and no more Nickel is
>available for this chemical reaction, and you wind up with around 7-8
>microinches (0.2 micron) of Gold from this type of plating.
>
>Hope this helped...
>
>Rudy Sedlak
>RD Chemical Company
>
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Date:         Fri, 31 Mar 2000 08:48:22 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Mike Bailey <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Mike Bailey <[log in to unmask]>
Subject:      Re: via plugging
X-To:         Ryan Grant <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

We typically use drill +.006 for the primary image.  The postplugging dot is
drill +16 or .010 over the clearance.  This is typically not an issue unless
the vias are directly adjacent or contained within SMT pads.  There are
DRC's to catch and eliminate this issue.

-----Original Message-----
From: Ryan Grant [mailto:[log in to unmask]]
Sent: Friday, March 31, 2000 7:08 AM
To: [log in to unmask]
Subject: Re: [TN] via plugging


Mike,
        What is the "primary mask clearance at the location to be
postplugged" requirements?  I would like to pass this information on to our
DFM guys.

Thanks
Ryan Grant

> -----Original Message-----
> From: Mike Bailey [SMTP:[log in to unmask]]
> Sent: Friday, March 31, 2000 7:53 AM
> To:   [log in to unmask]
> Subject:      Re: [TN] via plugging
>
> I haven't seen any industry guidelines, however, occasionally a customer
> who
> has been "burned" will specify .002 max.  This is achievable with straight
> masking operations.  If performing separate "postplugging" operations
> after
> primary mask application and surface finishing etc., it's important to
> insure that the primary mask has a clearance at the location that is to be
> postplugged.  Otherwise if the hole is partially plugged etc., the
> secondary
> masking operation will leave a very undesirable bump approx. .005-.006
> high.
> These specialized operations drive inspectors and CAM operators absolutely
> crazy. Additionally, most customers are neither consistent with their data
> or assembly needs.  Typically, the masking information is the least
> considered by a designer.  Couple this with third party contract
> assemblers
> and you have numerous opportunities for error.
>
> Mike Bailey
> Director of Engineering
> McCurdy Circuits Inc.
> 4900 E. Hunter Ave.
> Anaheim, CA  92870
> Phone: 714 507-4900 Ext 253
> FAX: 714 507-4911
> e-mail: [log in to unmask] <mailto:[log in to unmask]>
>
> -----Original Message-----
> From: Rick Babyak [mailto:[log in to unmask]]
> Sent: Friday, March 31, 2000 4:47 AM
> To: [log in to unmask]
> Subject: [TN] via plugging
>
>
> Is there any acceptance criteria or a spec out there that covers via
> plugging with mask/ink?
>
>
>
> Rick Babyak
> Process Engineer
> Proto Circuit Inc.
> 7 Ascot Parkway
> Cuyahoga Falls, OH 44223
> 330-572-3401  Fax:330-572-3434
> [log in to unmask]
>
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=========================================================================
Date:         Fri, 31 Mar 2000 12:14:31 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Alain Savard <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Alain Savard <[log in to unmask]>
Subject:      Re: gold immersion plating--An attempted explanation
X-To:         Martin Christie <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Yes, you are correct. But some variation may be present due to slight
difference in the chemicals involved and exposure time.

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Martin Christie
Subject: Re: [TN] gold immersion plating--An attempted explanation

From your explanation I would assume that this process is self limiting in
terms of the amount of the deposit i.e. where you get the 0.2 micron Gold
deposit from.

Am I correct in assuming this?

Martin Christie
>
>Metals in solution are too low in electrons, and thus have a positive
charge.
> Solid metals, in their shiney form, have the proper number of electrons.
>When a more "active" metal (meaning a metal that does not bind its
electrons
>tightly) is immersed into a solution of a metal that does bind its
electrons
>tightly, like Gold, the electrons shift from the substrate metal, (the
>substrate under Gold is almost always Nickel) to the metal in solution,
>causing the metal in solution to plate out spontaneously on to the
substrate
>metal....in other words, a Nickel coated PCB, when immersed into a solution
>of Gold, will cause the Gold to plate out spontaneously on to the Nickel,
and
>in the process some of the Nickel is dissolved and goes into solution.
>
>This continues until the substrate Nickel is covered, and no more Nickel is
>available for this chemical reaction, and you wind up with around 7-8
>microinches (0.2 micron) of Gold from this type of plating.
>
>Hope this helped...
>
>Rudy Sedlak
>RD Chemical Company

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=========================================================================
Date:         Fri, 31 Mar 2000 10:04:27 -0800
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Delsen Testing Laboratories <[log in to unmask]>
Subject:      Re: via plugging
X-To:         Rick Babyak <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Rick Babyak wrote:

> Is there any acceptance criteria or a spec out there that covers via
> plugging with mask/ink?
>
> Rick Babyak
> Process Engineer
> Proto Circuit Inc.
> 7 Ascot Parkway
> Cuyahoga Falls, OH 44223
> 330-572-3401  Fax:330-572-3434
> [log in to unmask]
>

Rick,

The IPC has begun such an effort.  The Plugged Via Performance Task Group (D-33d) is
scheduled to meet at the Expo in San Diego next Wednesday from 1:30-3:00 pm according
to my program schedule.  The program states "This task group will develop acceptance
criteria for protecting plated-through holes, blind and buried vias.  The work of this
task group will be submitted to the Rigid Board Performance task group for inclusion in
the IPC-6012 B Revision."  If you wish more information, contact me off-line and I'll
see if I can direct you to the proper IPC staff liaison and chairman of this task
group.

Brian McCrory

--

Delsen Testing Laboratories, Inc.
1024 Grand Central Ave.
Glendale,  CA  91201

Phone:  818 247 4106
FAX     818 247 4537
email:  [log in to unmask]
URL:    http://www.delsen.com/

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Date:         Fri, 31 Mar 2000 12:27:16 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Brad L. Matthies" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Brad L. Matthies" <[log in to unmask]>
Organization: Raven Industries, Inc.
Subject:      Via Hole Placement.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

TN,

We are experiencing some manufacturing problems (solder bridging) and
have linked them to via hole placement.  The particular assembly we are
manufacturing has multiple via holes that are within approximately 15
Mils of SMT lands.  Does anyone have a resource that spells out safe
distances of via holes to SMT lands that they can pass along?  We are
getting ready to approach the design group for this product and are
looking for a qualified resource of information that we can use as well
as the design group.

Thanks,
BLM

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Date:         Fri, 31 Mar 2000 10:39:30 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              phil bavaro <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         phil bavaro <[log in to unmask]>
Subject:      Re: Solder at lower temperature
X-To:         Creswick <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
Mime-Version: 1.0
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jan,

We've used solid solder preform made out of Sn63Pb37 (again, no flux)
beneath the FET to do a similar type of attachment.   We had to request a
change in the thickness of gold on the part as the FET manufacturers like
to load up the surface with very thick gold (for mechanical attachment
intent).   The substrate was solid copper with a nickel and gold plating,
but the gold was immersion at 8 microinches max.  Nitrogen was required due
to the lack of flux, but the gold wet just fine


At 10:01 PM 3/30/00 -0500, Creswick wrote:
>Jan,
>
>Actally, there are many solders within range of termperatures which you
>specify.  However, practically, I am not so sure I would recommend any to
>you without knowing the requirements of your system.
>
>You probably already knew that MOSFET manufacturers normally attach their
>devices to copper slugs using high lead alloys such as Sn10Pb88Ag2,
>Sn10Pb90, Sn5/Pb95 or other variations incorporating Indium as well.  Check
>data books or web sites for International Rectifier, XYIS, and others. =
 Each
>of these alloys has the benefit of being very ductile, absorbing the=
 thermal
>coefficient of expansion mis-match between the high expansion copper slug
>and the low expansion silicon chip - allowing the device to survive many
>power cycles.  On the other hand, most of these alloys melt at 300+=B0C and
>need to be reflowed in a hydrogen or reducing atmosphere. Thermal
>conductivity is so so, but the joint isn't more than 25-50um thick, so it
>becomes relatively negligible, if it is void free.
>
>By going to any number of SnPb, SnAg, or SnPbAg alloys you will gain the
>decreased liquidus temperature which you desire, but give up much of the
>ductility of the traditional high lead alloys.  However, since you are
>currently using AuSn, you don't have a very ductile system in the first
>place - the redeeming grace is that the composite thermal expansion of the
>DBC substrate (~7-10ppm/=B0C - depending on foil to ceramic ratio) is much
>closer to the silicon (2-3ppm/=B0C) than copper (17-18ppm/=B0C).   Net=
 result
>after device attachment, the device is under compression - better than the
>opposite!
>
>If your substrate were aluminum nitride (4-5ppm/=B0C) the structure could=
 be
>even better.  But, not knowing your design etc. this may not be suitable to
>your application.  I believe that Brush Wellman (and maybe Stellar) did
>offer the effective equivalent of DBC on AlN. =20
>
>In either case, if you choose to go to a Sn, Pb, or In bearing alloy go
>lightly on the gold plating, unless it is required elsewhere for wire
>bonding.  =20
>PbIn or other alloys.  Daughter-boards alleviate some of these problems,=
 but
>may create others.  There should always be a nickel plating layer between
>the copper and the gold.
>
>The traditional Pb/In alloys work well for this application, but it sure
>helps to have hydrogen or reducing atmosphere reflow capability.  Fluxes do
>a great job of creating voids!  Scientific Sealing Technology vacuum reflow
>equipment also is a big benefit, but again, thou shalt not use flux!
>
>Depending upon the circuit, in some fault conditions, the junctions can get
>rather hot - hot enough to melt Sn63!  Consider what safeguard you require
>in the event of a fault?
>
>Review your solder preform manufacturer's selection of alloys for one=
 within
>your temperature range.  Consider your system requirements, and any
>re-qualification liabilities.  If you still wish to proceed, buy some=
 ribbon
>stock of the alloy/s you wish to evaluate.  Cut them to size manually, and
>attach some devices.  Acoustically, or x-ray scan the interface for=
 voiding.
>Do some die shear and power cycling of the devices.
>
>To conclude - even though the AuSn causes you repairablity problems, please
>attack the problem with your eyes wide open.  Sometimes, low temp solders=
 in
>situations like this can be too good to be true.  Be careful!
>
>Steve
>
>
>
>
>
>
>
>
>
>At 11:11 AM 3/30/00 +0200, you wrote:
>>Hi guys and girls!!
>>
>>I have a question that I think many of you can answer.
>>Today we solder FET chips with Au/Sn solder onto a DBC substrate with Au
>surface.
>>The soldering area of the FET is Chromium/Nickel/Silver.
>>
>>I want to replace the Au/Sn solder with "something else".. I don't want to
>glue the chip to place, only solder.
>>The FET working temperature reaches up to 120degC.
>>
>>Any ideas on what kind of solder to use?=20
>>__________________________________________________
>>Jan Merstrand
>>Microwave MCM, Design/Production Support
>>Ericsson Microwave Systems AB. Defence Manufacturing
>>Office address: Bergfotsgatan 2, SE-431 84 M=F6lndal
>>Phone: +46 31 747 0725, Fax: +46 31 747 3515
>>
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Phillip A. Bavaro
QUALCO/\/\/\/\  Incorporated
Manufacturing Engineer, Staff
[log in to unmask]
Pager (619) 271-3640
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Date:         Fri, 31 Mar 2000 14:32:05 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dennis Ward <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dennis Ward <[log in to unmask]>
Subject:      Soldermask clearance
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Good afternoon everyone,

Problem of the day.

I'm trying to use a conventional via with a .8mm pitch microBGA.
The spacing between the soldermask clearance around the land
pad to the via pad is 2.7 mils. The via is cover with soldermask.
What sort of problems should I expect with this situation? Will
there be a problem? The via and land pad are not necessarily part
of the same net.

In case any one is interested the board parameters
.093 thick board - 10 layers
13 mil via - 23 mils pad
BGA - 9X9 .8mm pitch
BGA ball size @.45mm (17.7 mils)
BGA land pad @12 mils - 16 mil mask opening
SMOBC
LPI mask


Any input appreciated!

Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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Date:         Fri, 31 Mar 2000 13:54:26 -0600
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Mike Pulvermacher <[log in to unmask]>
Subject:      Re: Soldermask clearance
X-To:         Dennis Ward <[log in to unmask]>
In-Reply-To:  <[log in to unmask]>
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset="iso-8859-1"

Dennis,

One factor to consider is that the power plane anti-pads required for the 13
mil via will likely overlap. This means that power and ground vias will not
be able to tie to plane layers directly.

Mike Pulvermacher
Senior PCB/DFM Technologist
Plexus Technology Group
Direct: (920) 751-3295
Fax: (920) 751-5659


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dennis Ward
Sent: Friday, March 31, 2000 1:32 PM
To: [log in to unmask]
Subject: [TN] Soldermask clearance


Good afternoon everyone,

Problem of the day.

I'm trying to use a conventional via with a .8mm pitch microBGA.
The spacing between the soldermask clearance around the land
pad to the via pad is 2.7 mils. The via is cover with soldermask.
What sort of problems should I expect with this situation? Will
there be a problem? The via and land pad are not necessarily part
of the same net.

In case any one is interested the board parameters
.093 thick board - 10 layers
13 mil via - 23 mils pad
BGA - 9X9 .8mm pitch
BGA ball size @.45mm (17.7 mils)
BGA land pad @12 mils - 16 mil mask opening
SMOBC
LPI mask


Any input appreciated!

Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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=========================================================================
Date:         Fri, 31 Mar 2000 12:11:50 -0800
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Timothy Reeves <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Timothy Reeves <[log in to unmask]>
Subject:      Re: via plugging
X-To:         Rick Babyak <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain

Hi Rick,
I asked about this subject recently and got only a few replies, but was
advised to look at the TechNet archives and I found quite a bit there. Use
keywords like via, fill, plug, tent, etc.
Must say I didn't see much in the way of specs or standards though.
Good luck!
Tim Reeves
> ----------
> From:         Rick Babyak
> Sent:         Friday, March 31, 2000 4:46
> Subject:      via plugging
>
> Is there any acceptance criteria or a spec out there that covers via
> plugging with mask/ink?
>
>
>
> Rick Babyak
> Process Engineer
> Proto Circuit Inc.
> 7 Ascot Parkway
> Cuyahoga Falls, OH 44223
> 330-572-3401  Fax:330-572-3434
> [log in to unmask]
>

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Date:         Fri, 31 Mar 2000 15:27:24 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Tempea, Ioan" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Tempea, Ioan" <[log in to unmask]>
Subject:      Re: Via Hole Placement.
MIME-Version: 1.0
Content-Type: text/plain

Hi BLM,

you do not mention if the bridges you see are following reflow, or, most
likely wave soldering.

For wave, we found 10 mils to be a good distance to avoid shorts, so maybe
you should play a little with the soldering parameters.
Another solution, better, is to plug the vias from the side giving the
trouble.

I know this is not the answer you wanted, but I know nothing of specs on
this matter and I felt the need to comment, since the ol' boys are very
quiet lately.

Ioan

> -----Original Message-----
> From: Brad L. Matthies [SMTP:[log in to unmask]]
> Sent: Friday, March 31, 2000 1:27 PM
> To:   [log in to unmask]
> Subject:      [TN] Via Hole Placement.
>
> TN,
>
> We are experiencing some manufacturing problems (solder bridging) and
> have linked them to via hole placement.  The particular assembly we are
> manufacturing has multiple via holes that are within approximately 15
> Mils of SMT lands.  Does anyone have a resource that spells out safe
> distances of via holes to SMT lands that they can pass along?  We are
> getting ready to approach the design group for this product and are
> looking for a qualified resource of information that we can use as well
> as the design group.
>
> Thanks,
> BLM
>
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Date:         Fri, 31 Mar 2000 15:31:25 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Dennis Ward <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Dennis Ward <[log in to unmask]>
Subject:      Re: Soldermask clearance
X-To:         "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit

Mike,

Exellent call! However not every BGA land will need a via
tied to it. I did a quick scan of the micro BGA and did
in fact find one via that would have been isolated from the plane.
The rest are okay. Thanks for the input. Again good call.

Greatly appreciated
Dennis

-----Original Message-----
From:   Mike Pulvermacher [SMTP:[log in to unmask]]
Sent:   Friday, March 31, 2000 2:54 PM
To:     TechNet E-Mail Forum.; Dennis Ward
Subject:        RE: [TN] Soldermask clearance

Dennis,

One factor to consider is that the power plane anti-pads required for the 13
mil via will likely overlap. This means that power and ground vias will not
be able to tie to plane layers directly.

Mike Pulvermacher
Senior PCB/DFM Technologist
Plexus Technology Group
Direct: (920) 751-3295
Fax: (920) 751-5659


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dennis Ward
Sent: Friday, March 31, 2000 1:32 PM
To: [log in to unmask]
Subject: [TN] Soldermask clearance


Good afternoon everyone,

Problem of the day.

I'm trying to use a conventional via with a .8mm pitch microBGA.
The spacing between the soldermask clearance around the land
pad to the via pad is 2.7 mils. The via is cover with soldermask.
What sort of problems should I expect with this situation? Will
there be a problem? The via and land pad are not necessarily part
of the same net.

In case any one is interested the board parameters
.093 thick board - 10 layers
13 mil via - 23 mils pad
BGA - 9X9 .8mm pitch
BGA ball size @.45mm (17.7 mils)
BGA land pad @12 mils - 16 mil mask opening
SMOBC
LPI mask


Any input appreciated!

Dennis Ward
Net to Net Technologies, Inc.
603 427-0600
[log in to unmask]
http://www.nettonettech.com

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=========================================================================
Date:         Fri, 31 Mar 2000 16:18:45 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              "Edward J. Valentine" <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         "Edward J. Valentine" <[log in to unmask]>
Subject:      Re: Via Hole Placement.
X-To:         "Brad L. Matthies" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

BLM -

Although I couldn't find it in the new IPC-SM-782 (Surface Mount Land
Patterns), the old, original version of 782 (March 1987) had the spacing at
0.025" (0.63mm), via pad to smt pad on page 65.  Ed/

Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask]
Website: http://www.ems-consulting.com

----- Original Message -----
From: Brad L. Matthies <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 31, 2000 1:27 PM
Subject: [TN] Via Hole Placement.


> TN,
>
> We are experiencing some manufacturing problems (solder bridging) and
> have linked them to via hole placement.  The particular assembly we are
> manufacturing has multiple via holes that are within approximately 15
> Mils of SMT lands.  Does anyone have a resource that spells out safe
> distances of via holes to SMT lands that they can pass along?  We are
> getting ready to approach the design group for this product and are
> looking for a qualified resource of information that we can use as well
> as the design group.
>
> Thanks,
> BLM
>
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=========================================================================
Date:         Sat, 1 Apr 2000 07:25:42 +1000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: gold immersion plating--An attempted explanation
X-To:         Alain Savard <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Relax Alain :

the original from Martin did have a heading : Rudy, ....... ;
sorry to play a Hawkeye :
but i'd question a need for this kind of "spot" editing .
Otherwise open season , obviously,
just shoot the ducks, not fellows around

thx

paul

-----Original Message-----
From: Alain Savard [mailto:[log in to unmask]]
Sent: Saturday, 1 April 2000 3:15
To: [log in to unmask]
Subject: Re: [TN] gold immersion plating--An attempted explanation


Yes, you are correct. But some variation may be present due to slight
difference in the chemicals involved and exposure time.

Alain Savard, B.Sc.
Chemical Process Analyst
CAE Electronics Ltd.
e-mail: [log in to unmask]

-----Original Message-----
From: Martin Christie
Subject: Re: [TN] gold immersion plating--An attempted explanation

From your explanation I would assume that this process is self limiting in
terms of the amount of the deposit i.e. where you get the 0.2 micron Gold
deposit from.

Am I correct in assuming this?

Martin Christie
>
>Metals in solution are too low in electrons, and thus have a positive
charge.
> Solid metals, in their shiney form, have the proper number of electrons.
>When a more "active" metal (meaning a metal that does not bind its
electrons
>tightly) is immersed into a solution of a metal that does bind its
electrons
>tightly, like Gold, the electrons shift from the substrate metal, (the
>substrate under Gold is almost always Nickel) to the metal in solution,
>causing the metal in solution to plate out spontaneously on to the
substrate
>metal....in other words, a Nickel coated PCB, when immersed into a solution
>of Gold, will cause the Gold to plate out spontaneously on to the Nickel,
and
>in the process some of the Nickel is dissolved and goes into solution.
>
>This continues until the substrate Nickel is covered, and no more Nickel is
>available for this chemical reaction, and you wind up with around 7-8
>microinches (0.2 micron) of Gold from this type of plating.
>
>Hope this helped...
>
>Rudy Sedlak
>RD Chemical Company

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Date:         Fri, 31 Mar 2000 17:31:19 -0500
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Ed Cosper <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Ed Cosper <[log in to unmask]>
Subject:      Thermal stressing
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hi all,

 I need some feedback. Here is the situation.

We had some concerns about marginal interconnects on some 10 layer boards
that had passed the bare printed circuit board bed of nails test at 100
volts. To instill more confidence in the products, the bare printed circuit
boards were submitted for environmental chamber thermal stressing (the 3
cycle test as outlined by IPC). Parts were stressed by an outside lab,
returned, assembled, in circuit tested, burned in, then final tested.

A sample of the parts that passed the final assembly test was sent out again
for the environmental chamber stress test.  The parts were then retested and
all the parts failed test. ( We have not determined why yet.)

Based on this I have two questions.

1) Is it possible to overstress loaded board?
2) Would you expect assembled boards to pass after chamber thermal cycling?
( I don't know if thermal cycling is appropriate for assembled products )

All thoughts are appreciated.

Ed Cosper
ABC

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Date:         Sat, 1 Apr 2000 08:34:04 +1000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Use of reclaimed devices
X-To:         Grant Emandien <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

From purist's point of view ; you may be right Grant ;
but from practical point ?
I'd definitely throw off all caps, etc (tested way high malfunction
consequences data base).
Clueless is the word ; some choice of life test "simulation"
(quick, say days in cycling chamber, or soak ramp up/downs)
would be desirable to gain at least some degree of clue ;
but I did not find any particular drama with lifting expensive chips .
If you lift and replace with validated (say flowmaster 5K) profile (most
chips can take few passes);
you just need a very good technician with feel for physics .
Next down method of working on heat plate (120-150'C)
with one of the ersa's flood tips (on leaded items that is) .
The heat plate to ease thermal shocks, if yo wouldn't buy jets .

Agree it's good base/ethics/etc., what yo say,
but practically, especially for contract folks this is often too lofty ;
they may get few bare boards extra , but not on rockwell treasures .

All above said,
both considerations for and consequences against should be determined by
better than just feels,
(all too)"common sense", emotions or "better safe than sorry" managerial
"decisions" .
Often i found items with proven life gave me fewer nasty surprises than
brand new wonders .
Be it chips or cars . It takes little to gain adequate clues .

Hey ' once (in my sub days, like Steve 's grinding now) we got this clock
chip (no name) with glorious J leads,
just right to reflow easy ; guess what ; those bugs had batteries inside
(found cooked upon autopsy)!
After we've killed a dozen of this beetles (didn'quite pass test guy) ;
asked the customer: who was blissfully unaware of any desirable spec. sheets
.
No sockets designed , handsoldering J's for weeks (on original quote!).
Became a cynic since than .

Regarding you too Grant,

Paul


-----Original Message-----
From: Grant Emandien [mailto:[log in to unmask]]
Sent: Friday, 31 March 2000 23:25
To: [log in to unmask]
Subject: [TN] Use of reclaimed devices


Hi all,

I noticed in a forum contributor's email the practice of using reclaimed
ICs. Surely this is not accepted practice. I ask this because a supplier of
ours had requested the possibility of doing this as he had a shortage on the
ICs in question and the fact that they were particularly expensive.

Needless to say, we rejected this notion as we are clueless on the
consequences of such practice.

Regards
Grant

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=========================================================================
Date:         Sat, 1 Apr 2000 09:22:39 +1000
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              Paul Klasek <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         Paul Klasek <[log in to unmask]>
Subject:      Re: Thermal stressing
X-To:         Ed Cosper <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"

Hi Ed'

I remember Werner quoting some not named classics of satellite assy's,
with half of life "tested" out of them ! By "experts" !
If you'd specify which regime of which standard (No', please)you followed,
that would assist in analysis .
1
YES !
2
yes and no, depends, sometimes full pass indicates wrong application .
If all passes ; you have no idea where the limit is ;
if all fails (my condolences, know how yo feel);
likelihood of hitting it with oversized hammer (specifying wrong >shock<
test!)
is very high indeed (hope it ain't yo' mate).

While i would not believe cycling (likes IPC-SM-785) would fail you this
broad this fast,
following some shock standard could do it easy .

So, the specs of cycles/stress/shock/rises/durations/whatever, please ;
'm sure Werner would pull precedent from his extensive legal files instantly
than .
If obvious ; few of us could know

paul

-----Original Message-----
From: Ed Cosper [mailto:[log in to unmask]]
Sent: Saturday, 1 April 2000 8:31
To: [log in to unmask]
Subject: [TN] Thermal stressing


Hi all,

 I need some feedback. Here is the situation.

We had some concerns about marginal interconnects on some 10 layer boards
that had passed the bare printed circuit board bed of nails test at 100
volts. To instill more confidence in the products, the bare printed circuit
boards were submitted for environmental chamber thermal stressing (the 3
cycle test as outlined by IPC). Parts were stressed by an outside lab,
returned, assembled, in circuit tested, burned in, then final tested.

A sample of the parts that passed the final assembly test was sent out again
for the environmental chamber stress test.  The parts were then retested and
all the parts failed test. ( We have not determined why yet.)

Based on this I have two questions.

1) Is it possible to overstress loaded board?
2) Would you expect assembled boards to pass after chamber thermal cycling?
( I don't know if thermal cycling is appropriate for assembled products )

All thoughts are appreciated.

Ed Cosper
ABC

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=========================================================================
Date:         Fri, 31 Mar 2000 17:34:23 -0700
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              LI YUAN <[log in to unmask]>
Sender:       TechNet <[log in to unmask]>
From:         LI YUAN <[log in to unmask]>
Subject:      Reverse modeling
MIME-Version: 1.0
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Hello,

Some guru in package field mentioned reverse modeling and suggested me to
use it in solder joint reliability modeling. I have not heard of it
before. Have some one had any experience with it? Where can I find any
information?

Thanks,

Yuan Li
Research Associate
CAMPmode (Center For Advanced Manufacturing and Packaging of Microwave,
Optical and Digital Electronics)
University of Colorado at Boulder
CB 427, Boulder, CO 80309-0427
http://saagar.colorado.edu/~liy
(303)492-0481
(303)492-3498 (Fax)

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=========================================================================
Date:         Fri, 31 Mar 2000 21:16:50 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Andy Magee <[log in to unmask]>
Subject:      adhesiveless vs. 3-layer flex (i.e. with adhesive layer)
X-To:         [log in to unmask]
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There were a number of material supplier's papers published a few years
back at the various flex circuit conferences (IPC and others). Most
included a list something like "Why use adhesiveless?".

Here was my list:
Lower CTE for more reliable PTH.
Excellent thermal resistance for elevated temperature processing and
use, wire bonding applications, and multiple lamination cycles.
Thinner for greater flexibility, shorter heat transfer path, and space
savings.
Excellent dimensional stability for finer geometry features, and tighter
tolerances.
Single dielectric for uniform response to, plasma, laser and chemical
processing, as well as improved electrical properties.
Inherent flame retardancy.
Low water absorption.

These advantages were typically offset by higher cost, so they are not a
magic bullet to all your problems.

Andy Magee - Flex Guru
Senior Consultant - Bourton Group
[log in to unmask]
(815) 490-7593

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=========================================================================
Date:         Fri, 31 Mar 2000 21:34:34 -0500
Reply-To:     [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Andy Magee <[log in to unmask]>
Subject:      Flex Solder Wicking
X-To:         [log in to unmask]
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My interpretation is that the requirement to not enter the bend or flex
transition area is in addition to the base acceptability measurement of
wicking at the edge of the coverlay. In other words, if it enters the
bend or flex transition area at all it's not acceptable.

Based on extensive testing experience, this interpretation is consistent
with the principles I laid out on page three of Rogers Technical
Bulletin TB 3026CA, Maximizing Flex Life in Flexible Printed Circuits.
(see http://www.rogers-corp.com/cmu/pdf/proprty1.pdf )


Andy Magee - Flex Guru
Senior Consultant - Bourton Group
[log in to unmask]
(815) 490-7593

Rick wrote,

I need some enlightenment/help. IPC-A-600F Section 4.1.7 addresses
solder wicking under the coverlay of flex circuits. The paragraph at the
top states migration does not extend into the bend or flex transition
area. Would this be the area where your measurements for acceptability
begin or does the measurement start at the clearance in the coverlay? No
one at IPC can answer this and they are waiting for their expert, Don
Dupriest (Lockheed) to return their call. Don if you are out there
please call me (505)345-5591 X3064.
Thanks in advance,
Rick Howieson
GTC

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=========================================================================
Date:         Fri, 31 Mar 2000 21:16:44 -0600
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>,
              [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         David Hillman <[log in to unmask]>
Subject:      Re: White Tin
X-To:         [log in to unmask]
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii

Hi Scott - I just presented some immersion tin and immersion silver test data at
the APEX conference. Take a look at the paper titled "An Investigation of the
Effects of Printed Wiring Board Surface Finish and Conformal Coating For Ball
Grid Array Assembly" in the conference proceedings - it may be useful data
depending on your use environments.

Dave Hillman
Rockwell Collins
[log in to unmask]




Scott Stewart <[log in to unmask]> on 03/29/2000 01:16:59 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      [log in to unmask]

To:   [log in to unmask]
cc:

Subject:  [TN] White Tin



     Hi All,
     Does anyone have information on White Tin as an alternative finish to
     HASL, OSP's, Ni/Au?  How are the ionics?  What Chemical Suppliers
     would you recommend for White Tin?

     Regards,

     Scott

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=========================================================================
Date:         Fri, 31 Mar 2000 23:20:14 EST
Reply-To:     "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender:       TechNet <[log in to unmask]>
From:         Werner Engelmaier <[log in to unmask]>
Subject:      Re: Thermal stressing
X-To:         [log in to unmask]
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Hi Ed,
You are giving us very little to go on. You do not even say whether the
"interconnects" you have problems with are SJs or PTH/PTVs.
>We had some concerns about marginal interconnects on some 10 layer boards
>that had passed the bare printed circuit board bed of nails test at 100
>volts.
This would indicate PTH/PTVs as your problems, but bare board bed-of-nails
testing does not give you any idea whether your board can survive soldering
operations.
>To instill more confidence in the products, the bare printed circuit boards
were >submitted for environmental chamber thermal stressing (the 3 cycle test
as outlined >by IPC).
What "3 cycle test as outlined by IPC" are youtalking about? I am not aware
of any such test, and I have been involved in IPC a loooooong time.
>Parts were stressed by an outside lab, returned, assembled, in circuit
tested, burned >in, then final tested. A sample of the parts that passed the
final assembly test was >sent out again for the environmental chamber stress
test.  The parts were then >retested and all the parts failed test. ( We have
not determined why yet.)
What "environmental chamber stress test"? Temperatures? Cycles? Shock?
>Based on this I have two questions.
>1) Is it possible to overstress loaded board?
Answer: Absolutely.
>2) Would you expect assembled boards to pass after chamber thermal cycling?
That all depends on the details! Properly designed and built assemblies pass
chamber thermal cycling all the time.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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