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December 1999

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Subject:
From:
Brian Ellis <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sat, 18 Dec 1999 10:04:16 +0100
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IMHO, this is a case where concurrent engineering is a must. Get round the table with
the Design Engineer, the Assembly guys, the PCB Fab merchants and Uncle Tom Cobbleigh
and all and thrash out all the details to produce the most economical solution for ALL
concerned. It is useless to produce a perfect design which cannot be manufactured or
assembled. I'm rather puzzled though when you speak of a 560 pin BGA socket. In my
experience, BGAs are usually soldered (or stuck) directly onto the PCB and a 560
pin-out is really a micro-BGA. Under these conditions, I'd use an HDIS layout with the
microvias (say, 50 um diameter) actually under the balls and track widths of about 50
um to give you an easy fan-out. However, I may have the wrong end of the stick. You
could do this easily, though, with just two inner signal HDIS layers and no signal
tracks on the outside under the BGA. This will give you the advantage that you can
place other components right up close to the BGA because there will be no external
fan-out vias to waste as much space as the component itself, or more.

Brian

John Parsons wrote:

> Seasons Greetings!
>
> We have just received a design from a customer which utilizes a
> 560 pin BGA(?) socket.  Here are the details;
>
> -6 Layer board, 4 routing layers 2 plane layers
> -Socket is 5 rows deep
> -Current configuration - 23mil hole on 30mil pad on 50mil grid
> -Routing out with 8mil traces on primary, secondary and two inner
> layers
>
> We have told him that his hole to pad ratio is too small for us to
> manufacture.  Currently our minimum spec is 6mil annular ring (pad
> dia - finished hole size/2) for outer layers and 7.5mil for inners
> (although we will do 6mil on inners if we have to).
>
> He is telling us that he cannot design within these constraints.
>
> What are others doing for this design?  Are you routing out on
> outer layers?  We cannot seem to put our hands on another
> sample design from our files (although I know they are some in
> there somewhere).
>
> Regards
> John Parsons
> Circuit Graphics Ltd.
>
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--
Brian Ellis
Protonique SA
PO Box 78
CH-1032 Romanel-sur-Lausanne, Switzerland
Voice: +41 21-648 23 34 Fax: +41 21-648 24 11
E-mail: [log in to unmask]
URL: Technical and consultancy divisions:
       http://www.protonique.com
     Web services division:
       http://www.protonique.com/webserv

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