We usually define the via in the software program with a different name,  i.e. via30tp.  We also make them square to differentiate between a standard via.  We try to make the via a min. of .040 in. when possible, but sometimes board density precludes this and we end up with a .030 via. for a test point.   By specifically naming the via this allows you to identify them in a report to determine if you have full nodal coverage.  Remember also you save money on your ICT fixture if you keep your test points to a .100 min. spacing.
Hope I helped.
Tom Burek
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 -----Original Message-----
From: [log in to unmask] [SMTP:MIME :[log in to unmask]]
Sent: Wednesday, December 08, 1999 8:40 PM
To: [log in to unmask]
Subject: [TN] electrical testing of bareboards

 << File: ENVELOPE.TXT >>
 --------------------------------------------------------------------------  --
Hello All

could use some insight from the board design community.

how do you define testvias on your boards (vias which are used for ICT or
functional test) ?

how do you (or do you)  differentiate testvias from regular vias ?

we as a board manufacturer must electrically test these vias but it is not
always evident how they are identified.

different copper aperture ?
special soldermask aperture ?
different viasize ?
anything else ?

we are writing a procedure around this, would appreciate any and all
input.

Thanks

Wolfgang
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