Testvias usually will have a soldermask pad.  This pad leaves a hole in the
soldermask for accessability.  So the software would check the padstack of
the pad to see if it is accessable from either the solder(bottom) or
component(top) side of the board.

Ken Stephens, President
CAD 2 CAM, Inc.
http://www.cad2cam.com
503-246-4692

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Erat, Wolfgang
> Sent: Wednesday, December 08, 1999 2:16 PM
> To: [log in to unmask]
> Subject: [TN] electrical testing of bareboards
>
>
> Hello All
>
> could use some insight from the board design community.
>
> how do you define testvias on your boards (vias which are used for ICT or
> functional test) ?
>
> how do you (or do you)  differentiate testvias from regular vias ?
>
> we as a board manufacturer must electrically test these vias but it is not
> always evident how they are identified.
>
> different copper aperture ?
> special soldermask aperture ?
> different viasize ?
> anything else ?
>
> we are writing a procedure around this, would appreciate any and
> all input.
>
> Thanks
>
> Wolfgang
> [log in to unmask]
>
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