Wolfgang,

Most CMs have minimum pad requirements for test probes (ICT).  I believe we
use .032" as a minimum, but there could be other sizes depending on the
type of probe and the supplier.
If you identify a via as a testpoint on a net, you need to also make the
pad the minimum size, which is probably larger then your normal via
pad.  I've also made testpoints as square pads so technicians also know
they are an identified testpoint for ease of location and access.  I try to
incorporate as many of the preferences of my supplier in our design/layout
to make it as testable as possible.  Finding a common ground to identify
and fabricate testpoints between designers and assemblers is a good thing
to do.

In the long run, it usually pays off.

DT

At 05:15 PM 12/8/99 -0500, you wrote:
>Hello All
>
>could use some insight from the board design community.
>
>how do you define testvias on your boards (vias which are used for ICT or
>functional test) ?
>
>how do you (or do you)  differentiate testvias from regular vias ?
>
>we as a board manufacturer must electrically test these vias but it is not
>always evident how they are identified.
>
>different copper aperture ?
>special soldermask aperture ?
>different viasize ?
>anything else ?
>
>we are writing a procedure around this, would appreciate any and all input.
>
>Thanks
>
>Wolfgang
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