Test Engineering wrote:
>
> snip <
>
> Taking notice to the responses before mine, I seen the words "most have",
> "could be", "usually are", in those statements. To those gentlemen, please
> don't take offense, I point these out as the variables I mentioned.

        You are essentially correct, but I must try to redeem myself
        by adding that the "usually"s so prevalent in my post were
        based on allowing for cases beyond our control.

        As soon as I'd have quoted "always" I would book a design
        using .040" vias (norm for us on 8/8 technology) requiring
        ICT access (.040 is an optimum testpad size) and by customer
        edict no soldermask encroachment on signal vias.

        In the aggregate of my "usually"s you can arrive at identi-
        fiable testpoints in cases where the design group is allowed
        to use standards which make such possible.  Granted, it needs
        human interpretation until the CAD community can agree on
        construction and reporting of test sites as elements.
>
> For us to do our job correctly and accurately, a standard definition would
> be perfect. I had stated this to designers during the IPC BBT expo in May
> 99 with little positive response. This is one of many issues where it has
> become imperative for the test and design worlds to converge and together
> deliver the product our customers expect and deserve.
>
        Looks to me like this definition needs to be worked out by
        the CAD system vendors and the IPC-D-356 and GenCAM groups.
        For us, we have three CAD platforms each of which handle
        the ICT test sites in different ways and none of them in a
        fashion easily discernible by the fabrication community...

        Probably the most difficult driver is the ICT world's need
        for vaccuum hold down; this causes preference for surface
        test pads which are frequently endpoints unto themselves.
        In the absense of that need, circuit vias cleared of sol-
        dermask can be used and these normally are not test escapes
        (as long as the soldermask is correctly designed/deployed).

        Regards to all,
--
      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

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