Ed,
Most folk, us included, do not plate the entire surface. We coat the entire
outerlayer side with resist then expose only cheater pads. Some use pads
slightly smaller than the drilled hole. The theory there is to allow plating
solution to pass though the hole and plate only on the exposed inside
vertical edge of the hole. This works well for larger diameter holes. i.e.
>.030. We typically have smaller holes to deal with. For these holes we use
a larger pad on the outerlayers ( about 2 mils larger) This does allow
surface plating on the exposed annular ring. We then strip the blue resist,
recoat and expose the outerlayer side with resist ( so it will not etch ),
then etch the innerlayer circuitry. Once etched, we strip the blue resist
from the outerlayer side, strip the tin resist , and then sand down the
plated "bumps" on the outerlayer side until they are smooth with the
original copper surface, The parts would now be ready for oxide and
multilayer lamination. ( well I think I've got the sequence correct ).. I've
only been interrupted about 10 times while I was trying to answer this for
you. LOL
Hope this helps..
Ed Cosper
----- Original Message -----
From: Brunker Ed <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, November 30, 1999 3:43 AM
Subject: Re: [TN] BLIND VIA FAB:
> Yes, thanks for the response. Yes, I'm referring to the entire surface
> particularly with regard to fine tracking on outer layers.
> Regards
> Edward Brunker
>
> -----Original Message-----
> From: Ed Cosper [mailto:[log in to unmask]]
> Sent: Monday, November 29, 1999 2:39 PM
> To: [log in to unmask]
> Subject: Re: [TN] BLIND VIA FAB:
>
>
> Are you referring to double plating the entire external surface???
>
> Ed Cosper
> ABC
>
> ----- Original Message -----
> From: Brunker Ed <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Thursday, November 25, 1999 3:52 AM
> Subject: [TN] BLIND VIA FAB:
>
>
> > When fabricating PCBs with blind vias, are there any alternatives to
> double
> > plating the outer layers? What design for manufacturability issues are
> there
> > regarding this technology?
> > Regards
> > Edward Brunker
> > Principal Process Engineer
> > Sendo
> > Centrelink House
> > Small Heath Business Park
> > B10 0HJ
> > UK
> >
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