Carey,
I do appreciate the input. I too worked under those conditions but probably
better. I'll keep you posted, but Dr. Bill, or is it Dean (I just can't keep
'em straight but need their glasses) is on the road proving it all for us
and his latest victim.
Thanks,
Earl
----- Original Message -----
From: Carey Pico <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, October 13, 1999 5:09 PM
Subject: Re: [TN] Over My Head in CCGALAND
> Earl
> I worked on a similar problem attaching flip chips to flat panel displays
in
> an R&D project a few years back. Achieving mechanical/physical contact at
> all bumps was the real tough part for me. But I didn't have the luxury
(or
> curse) of paste. So in this case, fixturing (pressure placement if
bumped,
> accurate paste dispensing and paste volume excess for only paste) is what
> I'd spend 90% of my time. And a way to repair needs good design.
> Carey
>
> -----Original Message-----
> From: Bill Davis <[log in to unmask]>
> To: [log in to unmask] <[log in to unmask]>
> Date: Wednesday, October 13, 1999 2:49 PM
> Subject: Re: [TN] Over My Head in CCGALAND
>
>
> >No, I haven't been ignoring you Moon-Man...
> >
> >I'm on a consulting project that is will be using 2800 I/O's initially at
> >1.0, then going to 0.8mm. Not sure the layer count, but I know it's close
> to
> >yours.
> >
> >Anyway, here's the probs I'm encountering:
> > 1. Coplanarity- Just getting the paste & part to a decent level of
> >coplanarity is problematic. Seems like .15 is a good number, but the only
> >commit I get from the IC & assembly house is something that adds up to
0.3.
> >Vertical alignment should spec that total tolerances should always allow
> for
> >50%+ of the column to be in the paste. This stackup should include the
> >tolerances of the PCB fab and the chips.
> > 2. Excessive/insufficient solder. The ball size in the paste, as well
> as
> >MOTS (materials other than solder) need to be minimized.
> > 3. Plan on no-clean- unless you plan on baking these puppies post
> >assembly. 10 days at 50% RH and we still found water and saponifiers
> trapped
> >under the device
> > 4. Eutectic is a must- near eutectic hasn't cut it (60-40 gets
> >intermittent)
> > 5. Clean, clean, clean- make sure the board's OSP level is well
> >controlled and pure. Our best results came from boards that had nothing
on
> >the copper (vacuum packed immediately after a argon cleaning etch- the
> >copper was very clean).
> > 6. Thermal profile- longer at lower temps is better than shorter at
> >higher temps. There is a tendency to rush the profile in order to get
more
> >thru-put- resist the temptation!
> > 7. Do not repair in situ- take the CCGA/BGA totally off and
> >reball/recolumn; then put it back on.
> > 8. Depending on the physical size (guessing you're somewhere around a
> >37.5X37.5), you may want to consider weighting the parts. When we got to
a
> >40X40 device, we found that adding a temporary weight to the top of the
> >device during reflow improved the joint integrity. We used ground down
> >aluminum heatsinks; make sure you model the profile with these, otherwise
> >you'll be running too cold.
> >
> >Let me look at what else we've uncovered & get back to you later.
> >
> >-JAFO
> >
> >-----Original Message-----
> >From: pod [mailto:[log in to unmask]]
> >Sent: Monday, October 11, 1999 4:15 PM
> >To: [log in to unmask]
> >Subject: [TN] Over My Head in CCGALAND
> >
> >
> >Folks,
> >
> >We're doing, rather consistently, 1100 I/O CCGA's (rounded number). Going
> to
> >3,000 on same 1mm pitch and to .8mm. Any suggestions about concerns
> >regarding
> >column straightness, placement accuacy (sinks into mud and stays put),
krud
> >between
> >columns, reflow and rework profiles, and all the usual stuff on 24+ layer
> >boards. Also,
> >going to duplicate current efforts using 24 parts per board. Just
wondering
> >knowing
> >it might be a stretch.
> >
> >Earl Moon
> >
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