Abdulrahman-
thanks for your comments. You added two very important features of the 10
layer stack up I proposed- that it is a short distance to the nearest
pwr/gnd pair, and the possible use of via in pad. For example, as you
mention , if the pwwr/gnd layer is in the center of the board, 032 mils
away, the series self inductance to the decoupling caps will be about 25
nH/inch x 0.03 = 0.75 nH per via. This is 1.5 nH additional inductance. This
is about the difference in inductance between a 1206 and an 0612 capacitor.
Just by changing the stack up, you can improve the performance of your low
cost caps to give them the performance of more expensive caps. Likewise, if
you are using 0612 caps, you could decrease the impedance of your caps, at
100 MHz by almost 1 Ohm. This can be as much as a 50% reduction- big
improvement!
Your second point is also very good, that if the pwr/gnd planes are near the
surface, you have the possibility of reducing the surface trace related
inductance of the decoupling caps by using blind vias in the pads. This
would reduce the sometimes as long as 100 mil surface traces to less than 20
mil. This is an inductance reduction of as much as 5 nH down to 1.5 nH. Also
a really big gain. I am giving a presentation on this very issue- the signal
integrity performance advantages of HDI technology, at the next Automata
user group meeting later this week. I have a link to it on my web site,
<http://www.bogatinenterprises.com/>. For anyone who will not be able to
make it and would like a copy of the presentation, I will be posting a copy
of the handouts on my web site, after Nov 1. I will send a note out when it
is available.
If you must use less than 10 layers, my recommendation is first take away
from the dual stripline and make them stripline. This is 8 layer, but only
two signal layers. Alternatively, start with one plane pair less:
x
y
gnd
pwr
x
y
pwr
gnd
x
y
and start taking out signal layers. The noise on the power and ground
layers, which will contribute to switching noise and especially EMI, will be
directly proportional to the number of power and ground layers. Take out two
of the three planes and you get possibly as much as 3x the noise level.
Examples published by Sun Micro have demonstrated a 10 dB reduction in EMI
in increasing the plane pairs from 1 to 3 plane pairs in 12 to 14 layer
boards- this is a 10x reduction in power or 3x reduction in the voltage
noise.
--eric
Eric Bogatin
BOGATIN ENTERPRISES
Training for Signal Integrity and Interconnect Design
26235 W. 110th Terr.
Olathe, KS 66061
v: 913-393-1305
f: 913-393-1306
pager: 888-775-1138
e: [log in to unmask]
web: <http://www.bogatinenterprises.com/>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of Abd
> ul-Rahman Lomax
> Sent: Sunday, October 24, 1999 11:53 PM
> To: [log in to unmask]
> Subject: Re: [DC] Reducing noise by stack up design
>
>
> At 06:36 PM 10/24/99 -0500, Eric Bogatin wrote:
> >I will offer my brief perspective on the optimum stack up for SI and EMI
> >control.
>
> Thank you, Mr. Bogatin, for your comments in this thread. I do read you on
> the SI list; my own post to DC was merely intended to counter, as
> a printed
> circuit designer and *not* as a signal integrity expert, certain rather
> obsolete design preferences; I've come to understand that, given good
> attention to trace impedance and the like, power/ground bypassing
> is really
> the major issue most often neglected, close power and ground layers being
> the most effective (perhaps the only truly effective) solution; so the
> suggestion that xGxyPy was somehow automatically superior to xyGPxy, I
> felt, needed to be questioned, but gently, since every design can
> bring its
> own unique challenges.
>
> (And good trace impedance control is also more difficult to obtain if the
> coupling between the planes is not well-distributed, whenever the return
> currents must switch planes.)
>
> You suggested GPxyPGxyPG as an ideal stackup, and it certainly has its
> obvious advantages. A power layer is available at a minimum distance below
> the surface; if I am trying to minimize a bypass or ground/power pin
> impedance to plane, eliminating 30 mils of depth could cut
> impedance due to
> the PCB in half, and most of the other half could be eliminated
> with via in
> pad.
>
> So I would think that your ideal construction would also include via in
> pad, perhaps blind vias down to the appropriate plane.
>
> Short of this, if it is not considered feasible to go to ten layers, how
> much difference would we expect to see between the above-described ideal
> stackup and xyPGxy? Further, what eight-layer stackup would be the *most*
> ideal, in general?
>
> [log in to unmask]
> Abdulrahman Lomax
> P.O. Box 690
> El Verano, CA 95433
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