I will offer my brief perspective on the optimum stack up for SI and EMI
control.
First, keep in mind that there are many designs that will work, and many
factors that contribute to acceptable signal integrity, such as the number
and type of active components on the boards, their rise times and noise
margins, the standard and custom busses that are used, the cost target, time
to market, how much risk you want to take, how much margin you want to add,
etc. For these and other reasons, every design is really a custom design.
This is why it is always important to understand the principles and
assumptions behind the design rules, rather than just the rules, when
applying them to your particular design.
Having offered my standard caveat, I'll pass along my recommendations on
stack up design, based on what are generally the largest noise sources.
There are four general classes of SI noise: reflection and ringing, due to
impedance discontinuities, cross talk, which includes SSO noise from
packages and connectors, rail collapse or ground bounce, due to high
impedance in the power and ground distribution and EMI.
You can manage 90% of the impedance discontinuity problems by using
controlled impedance boards, good routing topologies and appropriate
terminations. All of these can be handled in a variety of stack up
configurations. Its not that they are easy to solve, but they are straight
forward. Cross talk, especially SSO is handled by using line to line design
rules for the particular stack up and packages with internal ground planes,
like 4 layer BGAs or two metal layer TBGAs, and careful control of the
return paths, again, with some flexibility in the stack up. These solutions
are straight forward, and not so strongly a function of the stack up chosen.
However, rail collapse, ground bounce and EMI are very strongly dependent on
the stack up. Of the various SI problems to worry about, these are most
often the hardest ones to resolve, and they can most easily be addressed by
the right design of the stack up. All three of these problems are minimized
by keeping the power and ground impedance as low as absolutely possible.
This means select the power and ground planes to be adjacent layers, and do
everything possible within your cost and risk and time budget to make the
dielectric spacing as thin as possible.
To first order, the term you need to minimize is the loop inductance of the
planes. This is dominated by the dielectric thickness. The loop inductance
per square of power/ground planes is about 33 pH/(mil of thickness),
independent of the dielectric constant of the material between the layers.
If you can get 2 mil thick layers, for example with the Hadco ZBC layers,
you can have about 66 pH/square of inductance. This would translate to about
0.2 nH of loop inductance between decoupling capacitors and the packages
they are trying to decouple.
The normal switching currents that must flow in the power and ground
distribution will create a lower voltage drop across the lower inductance of
the planes, generating less rail collapse, less ground bounce and less EMI.
Another configuration of layer stack up, and the use of thicker inner
layers, will decrease the effectiveness of the planes. Your design may work,
but in general, you will always have lower switching noise and EMI with
thinner spacing of adjacent power and ground planes.
If you can only use 4 layers, and EMI is an issue and switching noise is an
issue, as is commonly the case, my recommendation is always use a thin core
between power and ground layers and microstrip signal layers on either side.
Do microstrip signal lines have more differential current EMI noise than
strip line signal lines? yes, but the EMI noise will often be dominated by
the power and ground plane noise, so if you don't minimize this first,
you'll never see the microstrip noise. If you have flexibility in the layers
count, you would want to use a power and ground core, two x-y signal line
pairs on either side, and then another power and ground pair on either side,
with the grounds as the outermost layers, keeping each power and ground
layer pair with thin dielectric. The ideal stack up is:
gnd
pwr
x
y
pwr
gnd
x
y
pwr
gnd
This is a 10 layer board! Anything less is a compromise. But that's why we
have the wonderful design tools we have, to balance the trade offs of cost,
performance and time. Will other stack ups work? probably, but this one, in
general, with have the lowest switching noise and EMI. Of course, you must
do all the other things right about type, placement and routing of
decoupling capacitors, terminations, topology, etc. All things being equal,
this 10 layer stack up will give lowest noise.
I teach many of these concepts in my courses, and I have some papers that
touch on these topics that are available for download from my web site. You
are welcome to download copies from <http://www.bogatinenterprises.com/>
--eric
Eric Bogatin
BOGATIN ENTERPRISES
Training for Signal Integrity and Interconnect Design
26235 W. 110th Terr.
Olathe, KS 66061
v: 913-393-1305
f: 913-393-1306
pager: 888-775-1138
e: [log in to unmask]
web: <http://www.bogatinenterprises.com/>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of Abd
> ul-Rahman Lomax
> Sent: Wednesday, October 20, 1999 6:38 PM
> To: [log in to unmask]
> Subject: Re: [DC] Reducing noise
>
>
> At 11:46 AM 10/20/99 EDT, [log in to unmask] wrote:
> >Hi, I hope someone can help me out here. I'm looking for suggestions on
> >ways to quite down traces that we know are going to be noise
> generators. If
> >using a 6 layer board...what is the best stack up? Should power
> and ground
> >planes always be kept next to each other for optimum capacitive
> performance?
> >Which layer should these noisy lines be kept on? Any help?
>
> I think I would agree with another writer that using layers 2 and 5 for
> power and ground and putting the noise traces on 3 and 4 is probably the
> safest idea; certainly if radiated noise is the concern. But that is not
> the end of the story.
>
> If traces change from, say, layer 2 to 4 or 6, the return current -- or
> most of it -- will ideally change from 2 to 5. To be able to do this
> without substantially increasing the loop area, there must be good
> capacitative coupling between layers 2 and 5. This means that bypass
> capacitors should be distributed liberally, and the length of the trace
> between the via and the pad of the cap should be kept to a minimum. I'd
> really like to see the via be in the pad, but for the assembly problems
> this can create. Also it is desireable, in general, to use smaller rather
> than larger capacitor packages, such as 0603 instead of 0805, to keep
> package inductance to a minimum.
>
> One should also, of course, observe good layer bias so that, in general,
> traces do not parallel each other with nothing but a thin piece prepreg in
> between, and the farther apart the traces are, the better the isolation.
>
> I'm not an RF engineer, so I don't want to say what is the best reference,
> but I will mention that recently when I was asked if I was competent for
> high-speed design, it did not hurt at all that I mentioned I had been
> reading High-Speed Digital Design, A Handbook of Black Magic, by Howard
> Johnson and Martin Graham, which I had bought a few months before from
> amazon.com.
>
> I lot of practices that we used for years, thinking they were good or at
> least not harmful, turn out to be not so great as edge rates increase.
>
> One of the jobs I did for the company that asked me involved redoing the
> work of another designer who insisted on running stringers to bypass caps
> instead of simply dropping a via immediately next to the cap to a power
> plane. He thought he was doing it right by making a direct path from the
> power pins to the associated bypass cap. But connecting the power pins
> directly to the plane and likewise the bypass caps is far more effective,
> it appears, taking better advantage of the distributed capacitance of the
> planes.
>
> In spite of what I wrote about about the stackup, it is conceivable that
> having power as 3 and 4 will be more effective; not enough information was
> provided to give a definitive answer, and it is not necessarily simple....
> On a board with components on both sides, if it can be implemented in 6
> layers, having 3/4 as power planes can be quite effective; the
> impedance of
> the traces on 2/5 can be a reasonable number, say 50 ohms (embedded
> microstrip), with 7 mil traces on 25 mil pitch.
>
> [log in to unmask]
> Abdulrahman Lomax
> P.O. Box 690
> El Verano, CA 95433
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