wow! blame the test vehicle for the failure on ESS (based on the
daisychain...I assume you are doing qualification and failed in
T/H/B)...Blame the Doctors too on the design ...gee, really should just let
you "swim or sink" on your own...but, I do like Big blue and IBM-guys...do
not want them got beatten for no reason at all!
based on the limited information you provided, here is what I would do if I
were you:
(1) pay IBM ($)for Failure analysis...If it is SIR type of test vehicle
(with daisychain), I think you may need LSI tester to pin point where is the
leak or short.  I believe they have a component lab and FA lab for doing
outside work (at least used to be).
(2) Pay IBM well ($$) for root cause analysis (you may have to open your
material/process in order to get some real benefit of root cause.  "Window
dressing" will lead you more costly FA).
(3) Pay IBM more (big time $$$$) for training some of your personnel to do
proper FA.  (be willing to spend sleepless nights to make sure you
understand the steps and why!)...send someone with background in FA and
design/process...Believe me, it is a good investment...You may have to sign
some non-disclosure agreement.. watch what you sign...(you may sign off your
day dream and nightmare too)..
(4) look like so far the only 2 people replied your e-mail are Dr.s! stop
bashing us... you may need us someday (like as a drinking buddy).
                                jk
At 09:12 AM 9/16/99 +0200, you wrote:
>Guten Wienerschnitzel, netters,
>challenge for an IBM-guy if he reads (no, of course he doesn't, big Blue
too big) , maybe my mate and competitor Bev can rise his eyebrow and move
his finger to the keyboard. Topic: multilayer 3D "boards" with IBMs liftoff
and PI dielectric. Reactive Ion etch (O2/He RIE) through mask for removing
PI, followed by WSiN sputter for biting and low current electroplating for
first step making the vias. Vias are finally O2 plasma, SF6 RIE'd. Now, most
seems maybe familiar to you, but, the problem is that the conductors are
only 4um wide and the vias 1um in diameter. Test "board" consists of single
to two layers with very short conductors, daysichained, let's say a hundred
such strips. See it in front of you: gold, under is the via, via goes
horizontally some um, goes up to next gold, .. up, down, up down, like
chaining an ordinarey PWB, but one decade smaller. And, PI is the
dielectric, approx 2um thick. Now, palomas, the Q:
>when these "boards" are temcycled we get interrupts somewhere in the
daisychain, seen as RF signal anomalies. How on earth do we analyse?
Ordinary SEM of surface tells nothing of what's under the conductor.
Finefocus Xray has unsufficient resolution for finding microcracks.
Sonoscan, no. Cross-sectioning, no, weeks of job, little chanse of finding
rupture. Reactive etching will heat and possibly take both Gold and PI. Wet
etching, e.g. KaC? Takes Au, but what do you do with the W under Au? Agree,
more like semiconductor techs.
>
>Oftenly when we have to do with the japs, we describe with hands, paper,
mail, photos and words, and they reply 'yes', 'yes', which is oftenly of
little help. So, Bev (I'm sure you have a recipe in your pocket) and like,
what do I do with the drunken saylor?
>Aussilek, give up, you can't be specialist on everything, you must have
some limitation, please, tell that you are a human and not a Cray. (on that
isle you may say crayfish, I don' t know).
>
>Cu?
>
>Ingemar Hernefjord
>Ericsson Microwave Systems
>
>PS. With HISTACK, I mean that our test samples remind of this EU-thing, but
does not belong to EU at all.
>
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