Ingemar,
I will respond because you ask, but I must confess that this stuff is mostly
out of my league. I am more involved with assembly level and environmental
concerns. I know very little about board fabrication, of any sort. Anyway
that being said, I read your e-mail over a couple of times and I have at
least a couple of questions to offer. You say "we get interrupts somewhere
in the daisychain". Are they there when the boards are removed from the
chamber and sit at RT? If so, can you isolate the problem to a portion of
the board? For instance, could you probe to get it down to a gold
pad/via/through board track/via/gold pad subset of the daisy chain? Are the
vias open to the surface? If so can you test continuity between each gold
pad and the bottom of its via and then between the bottom of the two vias.
Then you would at least know whether the problem was due to the pad/via
connection or the via/via connection. Then you might at least know where to
look and could do some ver careful cross-sectioning followed by EDAX and
Auger. This is probably pretty naive, but this is not my area of expertise.
regards,
Bev Christian
Nortel Networks
> -----Original Message-----
> From: Ingemar Hernefjord (EMW) [SMTP:[log in to unmask]]
> Sent: Thursday, September 16, 1999 3:12 AM
> To: [log in to unmask]
> Subject: [TN] HISTACK, IBM-type, japs
>
> Guten Wienerschnitzel, netters,
> challenge for an IBM-guy if he reads (no, of course he doesn't, big Blue
> too big) , maybe my mate and competitor Bev can rise his eyebrow and move
> his finger to the keyboard. Topic: multilayer 3D "boards" with IBMs
> liftoff and PI dielectric. Reactive Ion etch (O2/He RIE) through mask for
> removing PI, followed by WSiN sputter for biting and low current
> electroplating for first step making the vias. Vias are finally O2 plasma,
> SF6 RIE'd. Now, most seems maybe familiar to you, but, the problem is that
> the conductors are only 4um wide and the vias 1um in diameter. Test
> "board" consists of single to two layers with very short conductors,
> daysichained, let's say a hundred such strips. See it in front of you:
> gold, under is the via, via goes horizontally some um, goes up to next
> gold, .. up, down, up down, like chaining an ordinarey PWB, but one decade
> smaller. And, PI is the dielectric, approx 2um thick. Now, palomas, the Q:
> when these "boards" are temcycled we get interrupts somewhere in the
> daisychain, seen as RF signal anomalies. How on earth do we analyse?
> Ordinary SEM of surface tells nothing of what's under the conductor.
> Finefocus Xray has unsufficient resolution for finding microcracks.
> Sonoscan, no. Cross-sectioning, no, weeks of job, little chanse of finding
> rupture. Reactive etching will heat and possibly take both Gold and PI.
> Wet etching, e.g. KaC? Takes Au, but what do you do with the W under Au?
> Agree, more like semiconductor techs.
>
> Oftenly when we have to do with the japs, we describe with hands, paper,
> mail, photos and words, and they reply 'yes', 'yes', which is oftenly of
> little help. So, Bev (I'm sure you have a recipe in your pocket) and like,
> what do I do with the drunken saylor?
> Aussilek, give up, you can't be specialist on everything, you must have
> some limitation, please, tell that you are a human and not a Cray. (on
> that isle you may say crayfish, I don' t know).
>
> Cu?
>
> Ingemar Hernefjord
> Ericsson Microwave Systems
>
> PS. With HISTACK, I mean that our test samples remind of this EU-thing,
> but does not belong to EU at all.
>
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