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August 1999

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Subject:
From:
Paul Klasek <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 31 Aug 1999 09:17:49 +1000
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lclclcl   ;  lclclclcl ;

Got the plywood dilemma Scott ; we should be actually calling the layers of
glass ; not of copper hey ?
Been just curious if it ever happened ; funny enough it did .
The cross ply should in theory be neutral ; practice seems different .

paul

-----Original Message-----
From: Severson, Scott M. [mailto:[log in to unmask]]
Sent: Monday, 30 August 1999 22:37
To: 'TechNet E-Mail Forum.'; 'Paul Klasek'
Subject: RE: [TN] In Circuit Test


Paul,

Charles Barker hit the nail on the head.  Laminate Theory tells us that a
"balanced" lay-up (as described by Charles) is the most desirable to provide
even stresses in the laminate and thus prevent warp.  In composite
structures (non PCB) it can be even more critical because uni-directional
laminate (vs cross-ply used in boards)is often used at various angle to get
pre-defined properties in a given direction.

Scott

-----Original Message-----
From: Paul Klasek [mailto:[log in to unmask]]
Sent: Friday, August 27, 1999 6:26 PM
To: [log in to unmask]
Subject: Re: [TN] In Circuit Test


interesting , how thick is 52 ? (just curious) .
Earl we have the layers cost dilemma here :
What would be ratios of yields and costs from simple double sided FR4 ;
to 4 layers, 6, 8, >>> etc. ?

And why even's only ; no odd layers ever ?

thanks       paul


-----Original Message-----
From: Enter your name here [mailto:[log in to unmask]]
Sent: Saturday, 28 August 1999 8:22
To: [log in to unmask]
Subject: Re: [TN] In Circuit Test


Your 2  cents noted. No biggy, but we build bare boards up to 52 layers and
loaded cost over too many thousands. Even our cheap stuff ain't cheap. DFM
and T is critical. It just can't happen without concurrent engineering
including all responsible "experts" from design through test.

Earl Moon
----- Original Message -----
From: Darrel Therriault <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, August 27, 1999 11:35 AM
Subject: Re: [TN] In Circuit Test


> TechNet....
>
> I'd like to put in my $.02 for DFT......
>
> We specify 100% netlist coverage for ICT unless there is a compelling
design
> reason why a net can not be accessed.  It's part of our Mfg DFT
requirements.
>
> The rationale.....our boards are expensive and complex.  Having to scrap
> out or spend
> a lot of debug time at Functional costs a lot more in time and resources
> then adding
> some test points or taking up a little more real estate or adding a
> layer.  I think if you
> look at the cost implication of production and service/customers it works
> out to a
> much bigger advantage to have ICT at the highest level possible.
>
> DT
>
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