Your 2  cents noted. No biggy, but we build bare boards up to 52 layers and
loaded cost over too many thousands. Even our cheap stuff ain't cheap. DFM
and T is critical. It just can't happen without concurrent engineering
including all responsible "experts" from design through test.

Earl Moon
----- Original Message -----
From: Darrel Therriault <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, August 27, 1999 11:35 AM
Subject: Re: [TN] In Circuit Test


> TechNet....
>
> I'd like to put in my $.02 for DFT......
>
> We specify 100% netlist coverage for ICT unless there is a compelling
design
> reason why a net can not be accessed.  It's part of our Mfg DFT
requirements.
>
> The rationale.....our boards are expensive and complex.  Having to scrap
> out or spend
> a lot of debug time at Functional costs a lot more in time and resources
> then adding
> some test points or taking up a little more real estate or adding a
> layer.  I think if you
> look at the cost implication of production and service/customers it works
> out to a
> much bigger advantage to have ICT at the highest level possible.
>
> DT
>
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