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August 1999

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Subject:
From:
"Robert D. Green" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 27 Aug 1999 14:04:51 -0400
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     I get these type complaints continuously from the CAD folks.  We
     actually did a study in my last company and found that it was cheaper
     to add an additional layer for routing and have the testpoint access
     than it was to loose 20% of the testpoint coverage and deal with the
     problems coming out of test.

     If you lose test coverage at ATE, you move the problems into
     functional and systems level test.  The costs skyrocket and scrap rate
     soars.

     You have to live with this product for the 1-2 weeks (or so) that it
     takes you to lay it out and get approvals.  Manufacturing has to live
     with it for the life of the product.  A day of your time spent adding
     testability translates in to (as Charles has said) thousands of hours
     of time saved.

     Rob Green
     Manager, Test and CAM Engineering



______________________________ Reply Separator _________________________________
Subject: Re: [TN] In Circuit Test
Author:  Charles Barker <[log in to unmask]> at smtplink-hadco
Date:    8/27/99 11:12 AM


Phil,

I ditto Jeff's remarks. We are ramping up a new product now. The design engineer
didn't pay much attention to ICT. He has had to go back and move stuff around on
a very dense board! Not a pleasent task. This has slowed down our ramp-up rate
considerably. We have also had to go out for a secind genertion test fixture to
accompdate the changes, which takes several weeks and costs beacoup US $$$!

As he mentioned, providing extra test nodes over and above the required ones
would be a feather in your cap! Of course, you don't want to over do this point.
If you have to spend an extra two or three days on a several week long project
squeezing in all the needed nodes, you will save the manufacturing process
hundreds or even thousands of hours in the long run.

This is not something you would do for small run boards, of course. I'm talking
anything complex that would be built in even just the hundreds per month. It
will save many hours of a technician's (quite often not that well trained) time
trouble shooting the finished critter.

Good luck.

Charlie Barker
Sr. Manufacturing Engineer
Input/Output, Inc.
www.i-o.com




Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
      [log in to unmask]








 To:      [log in to unmask]

 cc:      (bcc: Charles Barker/US/I-O INC)



 Subject: Re: [TN] In Circuit Test





Phil Dutton wrote:
>
> Hello,
> I was just wondering how people are dealing with ICT.
> There is a big trend here (over the past year) to provide 100% nodal access
> for ICT.
> A big problem is littering the secondary side of the boards with suitable
> test pads, taking up valuable routing area.
> Often with SMT, the only vias on many of the nets, are to provide the test
> point. (single sided probing fixtures)
> I can see there are some benefits of 100% ICT, but from a designer's point
> of view, we seem to be trading off the benefits of finer pitch devices.
>

        Welcome to modern producibility.

        You can't ramp up production without automated test, if
        there's any kind of complexity to the product.

        You can't effectively do automated test without access to
        every functional pin of every device.

        The fun part?  You should be providing access to unused
        functional pins as well.

        It's an opportunity to excel!  The next step is to work up
        good verification of fixturing rules and then proper data
        handoff...
--

      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

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