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Subject:	Re: Blind Via Separations
From:	Werner Engelmaier <[log in to unmask]>
Reply To:	TechNet E-Mail Forum.
Date:	Thu, 26 Aug 1999 22:29:05 EDT
Content-Type:	text/plain
Parts/Attachments:	text/plain (48 lines)

Hi Dave,
You asked the following and will address your questions is equence.
In a message dated 8/26/99 7:44:18, [log in to unmask] writes:
>QUESTION: Does the PWB community have any test data indicating that
>exposure to frequent, severe thremal transients will not cause such
>separations to propagate into the over-plating, causing failure of
>the interconnect?
No, but we do have data from the more severe applications that they can
propagate.

>Are the selected PCB dielectric materials (FR4, high temperature
glass-epoxy, >polyimide) a factor?
Yes, as well as other parameters such as barrel plating thickness, hole
diameter, PCB thickness, number of severe T-excursions, resin content, etc. I
teach a workshop on this at IPC-Expo in San Diego.
>Is there an industry rationale for this relaxation in our stanadards?
There are 2 IPC task groups at work to get a better more sensitive test to
take the place of the Temperature Stress Test (Solder Float); and to
correlate the test results with t-cycle data. "IPC-6012 par. 3.6.2.1
((Plating Integrity) is silent
on separations between the plated hole wall and the external foil
layers", but this is shoulder cracking and clearly not allowed on production
boards. "IPC-6012 explicitly disallows such separations on interior
conductive foils." So, standards are not really being relaxed. More of a
concern is the drive towards thinner plating in the PTV barrel,

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com

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