Fellow Technetters,

We have recently been seeing PWBs with blind vias
with separations between the foil and the plated hole wall,
although these have been over-plated with new copper (covering both
the foil and the hole barrel). MIL-PRF-55110F par. A.3.6.9.2 (Separations)
allows separation along the vertical edge between the copper foil and
hole wall's conductive surface in exterior layers only. The
earlier MIL-P-55110E par. 3.6.2.1.9.3 (Separations) prohibited all
separations. IPC-6012 par. 3.6.2.1 (Plating Integrity) is silent
on separations between the plated hole wall and the external foil
layers. IPC-6012 explicitly disallows such separations on interior
conductive foils.

QUESTION: Does the PWB community have any test data indicating that
exposure to frequent, severe thremal transients will not cause such
separations to propagate into the over-plating, causing failure of
the interconnect? Are the selected PCB dielectric materials (FR4,
high temperature glass-epoxy, polyimide) a factor? Is there an
industry rationale for this relaxation in our stanadards?

Thanks in advance for responses,

Dave Kumpf
L-3 Communication Systems - East
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