Might as well jump on. At the last place I worked (H-P) our solder pot
temperature was set at 470F - for everything. We had few failures and,
because of our design input as pad sizes providing minimal fillets, we had
very few failures. We had some failures due to contamination provided by
some unruley glue.
Earl Moon
----- Original Message -----
From: Ryan Grant <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, August 24, 1999 12:39 PM
Subject: Re: [TN] Chip Capacitors
> Ed,
> We use 490F (254C) for our solder pot temperatures. Only on rare
> special occasions do we go as high as 500F (260C), and never any lower
> than 490F. (Although, at one time we previously did). Our application
> is high mix, mostly high density, high end product and always with some
> chip caps on the top side. We do not see failures with caps any more
> than what is measured at a DPMO level. (much less than 100 DPM).
> However, I do agree that the CTE of the FR-4 laminate is higher
than
> the ceramic cap, and higher solder pot temperature will create more
> stress at the lead termination of the cap, causing cracks that can
> propagate through the plates inside the cap. The CTE mis-match is
> minimized by preheating the board in the wave machine before reaching
> the solder pot. Improper pre-heat could be one of many factors causing
> the failures.
> How are you conducting the test and how is the failure mode
indicated?
> I would like to ensure that the non-existence of failures at our
> facility is not just because I don't know about them.
>
>
> Thanks
>
> Ryan Grant
> Process Development Engineer
> MCMS
> (208) 898-1145
> FAX (208) 898-2789
> [log in to unmask]
>
> >-----Original Message-----
> >From: Edward Hare, <SEM Lab, Inc.> [SMTP:[log in to unmask]]
> >Sent: Tuesday, August 24, 1999 8:07 AM
> >To: [log in to unmask]
> >Subject: [TN] Chip Capacitors
> >
> >Hi all,
> >
> >Thanks for all replies to my original question about chip capacitor
> >failure rates. I am currently involved in an issue where high leakage
> >current failures (~300 microamps at 50V) occur at a fairly significant
> >rate on chip caps that are on the top side of a mixed PTH/SMT assembly.
> >SMT components are reflowed in an IR oven and then the PTH components
> >are stuffed and wave soldered. I read through John Maxwell's (AVX)
> >papers and it appears that he recommends a solder wave temperature of
> >232 +/- 2 degrees C for assemblies with chip capacitors. My clients use
> >a 260 degree C wave (which I have always thought was typical). Do any
> >of you follow Maxwell's recommendations?
> >
> >Best regards,
> >Ed
> >--
> >
> > SEM Lab, Inc.
> >Scanning Electron Microscopy and Failure Analysis
> > Snohomish, WA
> > (425)335-4400
> > http://www.sem-lab.com
> >
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