Bob,
There are many opinions out there for what works (for certain designs, under
specific conditions) I've read some of the responses. 
As you know very well, not all designs share equal requirements. 

Although we do not use the component you are referring to ADSP-21062 in a
BGA package, we have design rules which work for us, when placing capacitors
for Hi I/O BGA processors (which share the same typical configuration: power
and return connections in the center of the package).

Here is my two cents worth: Wisdom passed on to me from opinions that work
for these specific applications.

1) Work with design engineering to determine how many bulk and high
frequency decoupling capacitors would be needed to compensate for power
demand droop and noise. spikes etc..  I'm not sure of the ADSP-21062 but
typically a microprocessor's current transients are on the order of 1-20 ns
while the typical converter has a reaction time of 1-100 µs. Properly
selected bulk capacitors (ones with low ESR and ESL) will slow the
transients seen by the power source to a rate that the source can supply
until the power source can react to the demand. At the same time, properly
selected high frequency capacitors will slow the transient requirement seen
by the bulk capacitors to a rate at which the bulk capacitors can supply.
2) Position those decoupling capacitors as close as possible to high
frequency noise sources and keep lead lengths extremely short. We place
gangs of decoupling caps directly under the processor on the secondary side
and tie the + and - lands directly to their respective planes. If yours is a
single sided assembly, tie them directly to their respective planes, when
placed as close as possible to the source, conforming to your placement
rules. 
3) Keep ground returns as short as possible to avoid voltage drops - that
is, a low inductance return path.
4) Use full ground planes wherever possible, try not to create voids within
the plane. individualize the via antipads on the plane. i.e. don't gang via
voids in the planes. 
5) Keep inductance as low as possible. by practicing no. 2  
6) Separate your grounds: Avoid connecting sensitive circuitry to high
current returns.
7) Use a single point return: Return all grounds to a common single point.

Hope this works for you!
Rgds,

Mike Beckman
Packaging Engineer                      [log in to unmask]
CH5-157                                 Ofc. (480) 554-4232
5000 W. Chandler Blvd.          Fax (480) 554-7615
Chandler, Arizona 85226         Pgr. (480) 340-3983







-----Original Message-----
From: Bob Vanech [mailto:[log in to unmask]]
Sent: Friday, June 18, 1999 11:25 AM
To: [log in to unmask]
Subject: [TN] Escape path and decoupling for 225-Ball BGA (fwd)


  To All..
           Has anyone out there in Technet world have
some hands on experience with Analog Devices' 225-ball
BGA ADSP-21062. This part is being used on a multilayer,
components both sides, fine pitch design. Since all the
power and return balls are in the center of the package
and the decoupling caps must be right at the power ball
locations, I am wondering what is the best approach for
capacitor locations and escape routes.
            I think that I might have to use the 0402
caps because of spacing, but the assembler would prefer
the 0603. Since every pin-out is used, I cann't delete
any signal pads, I am playing with ganging up the power
and return pads, sharing vias and using the open area
for the caps. That said, has anyone designed this part
into your design and would you be willing to discuss your
pro/con on the design approach. Thanks in advance and
have a great day.
                     Regards,
Bob Vanech                     Bob
Mango Computers
Norwalk, Ct.
(203) 857-4008
x-108