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June 1999

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From:
Doug Pauls <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 16 Jun 1999 07:54:13 EDT
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In a message dated 06/15/1999 9:31:45 AM US Eastern Standard Time,
[log in to unmask] writes:

> Hi Techworld,

Good day.

>
>  lately I have a new concern: PCB cleanliness.

As do most of us.  Are you talking about bare board cleanliness or assembly
level cleanliness?

Bare board cleanliness is still primarily measured by resistivity of solvent
extract (ROSE) using instruments such as Omegameters and Zero Ions.  What is
considered as "acceptable" cleanliness varies between specification and from
company to company.  MIL-P-55110 had a level of 6.5 by that method.  I have
seen companies use anything from 1 to 8 by ROSE.  I have also seen many cases
where ROSE data showed squeeky clean boards, but experienced all kinds of
corrosion and metal migration problems due to entrapped or absorbed residues
which ROSE will often not detect.

There is an increasing use of ion chromatography (IPC-TM-650, method 2.3.28)
to qualify bare board cleanliness and set more realisting bare board control
limits.  Delco-Delphi here in Kokomo has their Q-1000 bare board spec which
qualifies the bare board cleanliness using ion chromatography, ROSE, and
modified-ROSE testing.  The IC results indicate if the fabricator is
acceptable and the corresponding ROSE and mod-ROSE values are used for
process control.

All these are chemical characterization tests.  The measure of board
cleanliness by SIR, such as for Bellcore, is another issue entirely.
Bellcore GR-78, chapter 14.4 shows how clean a fabricators process need to be
for telecommunications stuff.  From the testing our lab does, it is difficult
to meet the specified SIR limits if you have any level of detrimental
residues.

If you are interested in the issue of bare board cleanliness, I would urge
you to join the IPC Bare Board Cleanliness Assessment Task Group, which I
happen to chair.

>
>  Any idea which are the standards that specifficaly treat about no-clean
>  technologies?

There is a task group in the IPC, chaired by Les Hymes, that deals with
implementation of a no-clean assembly process and all the things that you
have to consider, but it is a guidelines document, rather than a
specfication.  Other than that, the answer is no.

>
>  IPC-610 states that each company should make its own criteria.

This is becoming largely true for most IPC specifications.  J-STD-001 takes
the approach that quality is whatever you define with your customer.  If a
ROSE value of 14 is OK for customer 1, then so be it.  If another customer
wants a value of 4, so be it.  The days of a single pass-fail number for the
cleanliness of any assembly is gone, like it or not.  Think about it, would
you think that a nickel-gold RF board would have the same residue sensitivity
as a through-hole non-dense assembly?

>  How did you make your own?

This could be discussed for days on end.  The way that we counsel our clients
is to define a battery of electrical tests which can separate good from
marginal from bad product.  This might be ESS testing, or HALT testing, or
established burn-in tests, and develop designed experiments correlating
residue levels with electrical testing.  Until you can say what residue
levels correlate to unacceptable performance, why do the tests?

>  Did you set the criteria that match your process, or you made
>  the process match the criteria?

Both and neither.  Your testing should be structured so that you can tell
good from bad product, both from an infant mortality standpoint and from a
wear-out standpoint, and then optimize your manufacturing process to
consistently meet what you define as "good" for your product.

Doug Pauls
Technical Director
CSL

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