In IPC-D-279 3.3.10 there is "Pads-Only" design that is used for multilayer
military and space applications. It seems these should be hi-rel type
designs but it makes sense that the solder would be pulled down into the via
robbing solder from the joint. This seems to be a conflict.
Just a thought.

Tom Richardson
Spectracom

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of Mike
Gish
Sent: Friday, June 11, 1999 12:17 PM
To: [log in to unmask]
Subject:


I work for an assembly house in Phoenix Arizona and we have alot of problems
with the situation you have
presented.  Believe me when I tell you there isn't anything that hasn't been
tried!  It's popular for some
reason in the industry to place vias on SMD land patterns, and as you can
imagine when the board comes out
after reflow the solder gets pulled right down into the via usually leaving
the device unsoldered or in
some state of half soldered.  I would advice against it, but understand we
know in some situations it may
be necessary.  What I usually advise our customers who require this type of
situation is:  If it's an
exception and not a rule and you point this out as a precaution on your
assembly drawing specifically
showing the areas that will have to be checked its a situation that can be
managed.  Yes it will cost you
alittle more then your standard board assembly but pointing it out on the
assembly drawing enables the
assembly house to add it as part of their line process!  In fact that goes
for anything special about your
board assembly.  Designer think that assembly drawings are for showing
component location and that it.
Assembly drawings, and the bill of materials is what we use to assemble your
product.  If your job has
really thick ground planes and not thermal relief or you have vias in smd
pads then point that out on your
assembly drawing!

I hope this helps

Mike Gish
Sr. PCB Designer
Ditron Manufacturing, Inc.


Barb Zaepfel wrote:

> I have a situation where the engineer has placed via holes  within SMD
> pads, on a double sided PCBoard.
> IPC-SM-782 (3.6.3.1 & 2)  discusses geometries used to channel or "neck
> down" land areas going to a via to prevent solder migration.
>  I am familiar with blind/ buried via technology (IPC-275 5.4.8.4) used
for
> multilayer printed circuits.  Can anyone give me information on
> placing vias within smd pads and does it fall within a Class -2
> specification?  Please send any info on Assembly processes used
> to  prevent solder migration /insufficient solder fillets, and size
> recommendations of the via/technology used. (IPC does not seem to
> clearly state that vias cannot be placed within smd pads).
> Thanks!
>
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