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May 1999

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Subject:
From:
"Parvez M.S. Patel" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Sun, 16 May 1999 12:34:30 -0400
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hi everybody,
We've been doing some studies on assembly of CSPs , namely ones like the
tessera 46 I/O, FCT ultra CSP to name a few. We assembled these packages on
micrivia-in-pad patterns. These are 15/13.5/11 mil pads with 6 mil design
microvia, using photo/laser/plasma tech. We are seeing voids, as big as the
microvia, and they sit exactly at the via opening. The process we use is
pretty robust, using nitrogen for reflow and the problem is seen for both
solder and flux. The reliability data is still not out,but we expect the
voids to make a diffrence.

Would appreciate some inputs on why/how? and what to do/what not to do?

THanks in anticipation

Parvez M.S. Patel
Graduate Research Associate,
Universal Instruments Corporation,
SUNY - Binghamton, New York.

Ph:     607 779 7215(O)
Fax:    607 779 4646

*************Equilibrium is death. Seek persistent
non-equilibrium***************

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