Hello Technetter's:

Hey, does the following look familiar?   I sent this problem out last week but
was 0 for 1743.  Any responses via Technet or direct would be greatly
appreciated

Our BGA process (for a mixed-tech pcb) historically was to:

   fill (solder) the vias with a bottom-side stencil
   place & reflow the BGA on the top-side
   mask the BGA location and wave the thru-hole components

Note:  via fill required for In-circuit Test for their probes and/or for vacuum.

Question: What is the risk of exposing the BGA vias to the wave?  ie: reflow the
bga, cause voids, or ????


Thanks in advance,

Al Kreplick
Sr. Mfg. Eng.
Teradyne, Inc
Boston, MA
617-422-3726

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