Hi All -

I'm trying to do a current sanit check on some of our design practices, of
which I have been a part for many years.  Our products generally end up in
military aircraft or similar severe environments.  We adopted the practice of
sealing off all active circuitry other than termination and test pads, as a
result of environmental test failures, dendritic growths, etc.  This is done
by tenting or via filling and SMOBC.  The practice also ensures that there are
no melting metals (solder, etc.) that can change form or location unobserved
under part bodies.  Total encapsulation after assembly is generally out of the
question due to weight considerations.

Accordingly, here are the questions of teh week - don't everybody jump on 'em
all at one time:

On the boared fab side of things - for the folks building class 2 & 3  rigid
multilayers: What percentage of your product, destined for severe environment
industrial, automotive and military requires tented or filled vias and SMOBC
on all surfaces except test and termination pads?  In general, what would you
expect this practice to add to the board fab cost - 2%, 5%, 10% or?
(Yes, I've noticed that many cell phones have tented or filled vias and SMOBC
and class them in the severe environment stuff.)

On the assembly side of things: I would appreciate inputs from those of you
producing class 2 & 3 circuit card assemblies for these same envrionments
regarding the use of tented or filled vias and SMOBC, particularly when using
low profile components such as gull wing quads.  What have been your
experiences with sealed vs exposed circuitry and vias, particularly under
parts bodies and similar residue trapping sites?

By the way, the assembled CCA's, etc., are normally conformal coated with
either a sprayed acrylic or urethane.

Regards and TIA - Kelly

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