Chad:
AOQL is a standardized methodology for reporting outgoing defects from a
component supplier. The level at which any component supplier is likely
to attain is highly dependent on the product, its complexity and
maturity.

In general, here's the guidelines I have followed in the past, and are
somewhat arbitrary:
        ASIC (digital) <4M gates: Infancy: 1000 DPPM; Mature: 200 DPPM
        ASIC (digital) >4M gates: Infancy: 1200 DPPM; Mature: 500 DPPM
        ASIC (mixed signal) <4M gates: Infancy: 1200 DPPM; Mature: 700
DPPM
        ASIC (mixed signal) >4M gates: Infancy: 1500 DPPM; Mature: 1000
DPPM
        Commercial devices (except memory) (digital): 60 DPPM
        Commercial devices (mixed signal): 100 DPPM
        Memory devices: 3.5 DPPM/million bits of storage (thus a 1Mx16
DRAM would be 3.5 X 1M X 16 = 56 DPPM)
        Passive components (SMT caps, inductors and resistors- all
cermic/ceramic core): 10~20 DPPM

All of the numbers for semiconductors assume a non-epi, CMOS fab
process.


The 4M gate level appears to be generally where the chip size (driven by
complexity and gate technology) crosses over with the ability of the
tools to prevent defects (predominant particulate driven, though some
are non-particle defects, such as implant anomalies).

Most AOQL levels are negotiated by purchase contract, and should be
readily available from the component manufacturer.

Hope this helps...

> Bill Davis, Ph.D.
> Diamond Multimedia Systems
> Senior Scientist
> Tel. 408.325.7868
> Cell. 408.888.5650
> e-mail: [log in to unmask]
>
>


-----Original Message-----
From: Thibodeau, Chad [mailto:[log in to unmask]]
Sent: Wednesday, February 24, 1999 2:51 PM
To: [log in to unmask]
Subject: [TN] Component Defect Percentage/PPM


I was wondering if anyone knew an industry standard number for
acceptable
defect rates for components.  I.e. an acceptable rate of 10% failure for
components that the supplier can quote so not to have their lot
rejected.
It may be that this differs for different types of components (passives
may
have a much lower rate of failure than say I.C.'s).  Any help is
appreciated.  I did hear Xilinx quote an industry standard AOQL
(Acceptable
Outgoing Quality Level) of 25 ppm, but want to confirm if this is the
same
as I am talking about.  Thanks for any help.

Chad Thibodeau
Component Engineer
[log in to unmask]
2114 W. 7th Street
Tempe, AZ 85281
P-602 333-2138
F-602 921-9012
http://www.efdata.com

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