Bill
Thanks for taking the effort on your reply to this question. We have been wrestling (and I don't mean that
WWF crap) with this question recently and your information was timely ,to say the least. I was wondering
if the PWBs used in your tests were manufactured using positive or negative etchback. Do you feel this
this feature would have any impact on your results?
Gary Camac
bill birch wrote:
> Technet Colleagues,
>
> The pads Vs no pads question has been going around for many years.
> There have traditionally been two trains of thought which are based on the
> products end use environments. The first opinion was driven by the military
> and high end users who believed (based on studies in the 60's, 70's & 80's)
> that the addition of non functional lands on all internal layers would
> increase the reliability of the plated through hole structure. The second
> opinion driven by the majority of PWB manufacturers and the commercial world
> that believe removing non functional lands would increase yields (lowers
> cost), and potentially avoids others issues like internal shorting.
> Secondly, the "lower end" users believe that the life expectancy of their
> products would never reach the point where the subtle differences of pads Vs
> no pads would ever become a factor for interconnect reliability.
>
> The interesting thing is that they are both right, although we need
> to be a little more specific in order to understand the causes and effects
> on the potential failure mechanisms. We have now completed several large
> pads Vs no pad studies for various companies. The continuing trend (which as
> always is product design specific) is as follows: With larger holes
> (component size .035"+) the inclusion of internal lands is positive (10-15%
> increase in long term performance). Conversely, with smaller vias (.010" to
> .021") the inclusion of internal lands is negative (10-30% reduction in long
> term performance).
>
> Our ongoing failure analysis has shown that when .010" - .021" PTV's
> contain pads on all layers, the barrel crack locations are nearly always
> positioned between or adjacent to the two central pads (propagating from
> glass bundles in resin rich areas). With PTV's where pads are removed, the
> cracks occur randomly in the central region of the barrel, but not
> necessarily in the center. We believe this situation is primarily related to
> the distribution and re-distribution of stain.
>
> We have a hypothesis that when the hydro static pressure applies
> strain to the sidewall of the .010" - .021" PTH barrels, the pads in the
> center create a "focal point" for the strain. The pads "channel" the strain
> to the point of least resistance, which tends to be the thinner plating in
> the center of the PTH vias. The small improvements in performance for
> products with pads removed (smaller hole size only) is related to the fact
> that cracks occur in areas away from the center, where the PTH copper is
> slightly thicker.
>
> The situation is different for larger diameter vias, the increased
> surface area of the PTH barrel is more able to re-distribute the stain
> (barrel receives less strain). When the strain is redistributed the non
> functional pads absorb a proportion of the stain (usually seen as land
> rotation), the redistributed strain reduces the relative stress/fatigue
> applied to the barrel.
>
> We must put the question of pads Vs no pads into the perspective of
> the product attributes and the quality of the interconnect. A simple way to
> look at the situation is to consider some of the major factors that
> influence interconnect performance, this is important because the influence
> of pads Vs no pads is very subtle and only becomes a factor under certain
> conditions. We must consider the hierarchical influence of each set of
> conditions and determine if the inclusion of pads will increase or decrease
> interconnect reliability.
>
> Our experience has identified the major considerations that affect
> interconnect reliability (in hierarchical order) are as follows:
>
> 1st Level: Copper plating thickness/quality, (uniformity, ductility,
> elongation, tensile strength).
>
> 2nd Level: Material Tg, CTE, board thickness, hole diameter, number
> of layers (glass to resin ratio).
>
> 3rd Level: Surface finish, PTH metallization, foil thickness,
> construction, grid size).
>
> 4th Level: Design (pads Vs no pads, annular ring, antipad clearance).
>
> Based on the above information we must also consider 2 additional
> major factors that are NOT normally included in studies to determine
> interconnect performance.
>
> 1) Who builds the product is one of the biggest variables in the
> industry, virtually all studies that we have completed (with multiple
> vendors) identified that the supplier was the most dominant factor (on
> products designed and produced using the same attributes, materials, plating
> thickness' etc.). The range of potential performance is very wide (making
> the decision of pads Vs no pads disappear far into the noise!!), if you
> refer back to the hierarchical order it helps to identify where the major
> differences are between numerous PWB suppliers.
>
> 2) The impact of the assembly environment is becoming an important
> issue for certain products. We have completed several studies recently
> which compared the impact of multiple cycles through the IR ovens, in some
> cases the interconnect performance was virtually unaffected, other products
> measured reductions of 80%. The majority of studies were completed by
> testing the as received products, followed by testing after 3 or 5 passes
> through an IR oven (again, the impact was vendor related!!!)
>
> Most mid to high end products are using double sided BGA's on the
> substrates, this requires the board to see 3 IR reflows as a standard, some
> companies want to know if they have the ability to rework the BGA's, thus 5
> cycles was selected to ensure a safety margin.
>
> The environment of your products is an important factor, most
> companies that are concerned about this issue have products that are
> required to perform in very severe temperature/humidity environments, or
> require long term performance (15-25 years). For the majority (98+%) of
> products the working life is shrinking, as technology accelerates, products
> are becoming redundant within 5-10 years.
>
> With all that said, I can not see why removing the non functional
> lands (on smaller via diameters) would influence the products performance.
> All of our data shows that the subtle effects of pads Vs no pads is down in
> the lower influence category, there are clearly much more dominant factors
> that are affecting interconnect performance.
>
> Regards,
>
> Bill Birch
>
> PWB Interconnect Solutions Inc.
>
> At 01:13 PM 2/22/99 -0800, you wrote:
> >Is this a good idea for Class3 style designs? I've heard that removal of
> >inner layer pads could create stress-risor at resin rich region around
> >barrel of a small drilled/plated hole site during temp excursions. If a
> >twelve layer design had removal all the way through (except for the
> >connect), could this then add up? Please advise.
> >
> >-----Original Message-----
> >From: Wilmer, Craig [mailto:[log in to unmask]]
> >Sent: Monday, February 22, 1999 12:50 PM
> >To: [log in to unmask]
> >Subject: Re: [TN] removing unused inner pads ?
> >
> >
> >Jerry,
> >
> >Removing unused inner layer pads is a standard CAM function. Most CAM
> >software tools identify these as pads with no trace termination or
> >connection and/or no drill assignment. I've seen some customers specify
> >in the notes on the fab drawing that it's ok to remove them. If there
> >were any question about usage, the fab shop should leave them as is or
> >preferably contact the customer.
> >
> >Craig Wilmer
> >K*TEC Electronics
> >
> >-----Original Message-----
> >From: Jerome Schwartz x5474 [mailto:[log in to unmask]]
> >Sent: Monday, February 22, 1999 12:50 PM
> >To: [log in to unmask]
> >Subject: [TN] removing unused inner pads ?
> >
> >
> >All,
> >
> > Do a lot of board fabricators remove unused pads ?
> >
> >
> > Regards,
> >
> > Jerry Schwartz, CID
> > IPC Certified Interconnect Designer
> > "May the Schwartz be with you"
> >
> >###################################################
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