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February 1999

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Subject:
From:
Joe Felts <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Mon, 15 Feb 1999 00:51:56 -0700
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Jason,

My comments relate to PTV (not SMT) reliability which [I think] would be
the dominant failure mode for the board you described.  I've taken Werner's
course on high aspect ratio PTV reliability and, IMO it's among the best
tutorials IPC has to offer - backed by solid theory and years of empirical
data.  One of IPC-TR-579's conclusions, as I remember, was that the PWB
fabrication and assembly process alone consumes about 16% of a PWB's "life"
(assuming 5 thermal excursions).  A couple of years ago, while working in
your neighborhood (i.e., Toronto), I wrote an MS Excel program based on the
barrel-fatigue formulas that Engelmaier, et.al. used in IPC-TR-579.  It
usually predicts mean fatigue life anywhere from 8 - 24 cycles to failure
for high aspect ratio plated-through-vias under reflow-type thermal
excursions (i.e., from 20 deg.C to 210 deg.C).  Failure, here, is carefully
defined; for a thick board with several thousand high-aspect ratio PTVs
(e.g., 8:1 or higher), it is a virtual statistical certainty that, after
assembly, the barrel of at least one via has cracked though it may retain
electrical continuity and complete functionality.  [This is a conclusion on
my part and I have no evidence to support it - Werner, please jump in and
correct me if it's too much of a leap...]  High-Tg laminates greatly
enhance PTV reliability by reducing the strain on the copper barrels and
microvias may eventually eliminate the problem altogether.  Anyway, I'd be
happy to run your numbers through my little spreadsheet and fax you the
results; just e-mail me your fax number along with the following
parameters:

- Laminate Tg:                          typically 140C or 170C
- PWB z-axis CTE below the Tg:          default is 50 ppm/deg.C
- PWB z-axis CTE above the Tg:          usually 275-350 ppm/deg.C for a high-layer
resin-rich build
- minimum temp in thermal cycle:        typ. ambient temp 20-25C
- max. temp in thermal cycle:           peak reflow temp. 205-230 C
- PWB thickness:                        .100" in your case
- drilled PTV diameter:                 typ. .010", .0135", .018"
- number of vias per PWB:               anywhere from 200 to 20000
- barrel plating thickness:             default is .0012"
- plating quality index:                        refer to IPC-TR-579; my default is 8 (I don't
have TR-579, but as I
                                        remember, 8 is good but not superior)
- PTH barrel copper ductility:          typ. 15% - 22%; this is one of the most
important parameters -
                                        brittle copper breaks early.
- Weibull distribution shape factor:    default = 3 which is a probability
curve skewed just left of normal

Since your PWB is OSP coated it has seen at least one less thermal
excursion than if it were HASL.
Also, since most of the PTV fatigue damage is done at temperatures above
the Tg - and service temperatures never [??] exceed the laminate Tg -
chances are if it survives assembly and rework, it's good for a long time.

Joe Felts
Independent Engineer
mobile office on world tour - currently in... Phoenix.


-----Original Message-----
From:   Jason P. Bragg [SMTP:[log in to unmask]]
Sent:   Friday, February 12, 1999 8:14 AM
To:     [log in to unmask]
Subject:        [TN] PCB Rework Reliability

Hi Jason,
I have done and published extensive work in the area and give workshops and
consult in the subject matter. However, you can find all you need in IPC-
D-279, Design Guidelines for Reliable Surface Mount Technology Printed
Board
Assemblies, Appendix B. All it takes is a little work on your part. I give
workshops on this topic both at NEPCONWest and IPC Expo.

Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL  32174  USA
Phone: 904-437-8747, Fax: 904-437-8737
E-mail: [log in to unmask]

################################################################

 Has anyone done a study on the correlation of board reliability vs. the
number
of heat cycles a board sees?  Particularly, if a board has been through 2
smt
processes and wavesolder, how much smt rework can one do to the board and
still
feel confident that the product won't fail in the field?  I'm especially
interested in large boards, .100" thick, 18 layer, OSP finish.

____________________________________________________________
Jason Bragg, Component Failure Analyst
Materials Analytical Lab, TPA, Celestica Inc.
Phone: (416)448-6203

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