FR-4 being heavier.......geeesh!  A few notes from an old dog:
burying an outer signal layer (microstrip) to an inner signal layer
between planes (stripline) decreases the Zo about ~66%. Converting
that same microstrip to an embedded microstrip (like lyr 2) decreases
the Zo about ~33%.  The comment about let your fab shop work up the
actuals is correct. These impedance calculators on the internet are
great for ballpark stuff. But the actual builds should be up to the
fabricator
unless a large tolerance is OK. A good example is there is about 5
different
ways to make a .007" dielectric. Each has a different Er. Each would
require
a different linewidth. Not a drastic difference but enough to lop side
the
tolerance. Also, on the outerlayers, as the linewidth decreases the Zo
does
go up. But not incrementally, it does so logarithmically. This is because
the
trace geometry starts approximating wire over ground. Also, the line gets
closer and closer to the reference plane. The trace capacitance starts
fringing
up the trace edges.On traces below .004", the actual Zo is no way near
the
calculations. (Unless you've found a way to compensate for it
Empirically)
Also for large traces on very low Zo.
So don't think it's all black and white. Some of us Never Forget.......

Dave Hoover
(aka, Groovy)

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