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February 1999

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From:
Thomas N Bresnan <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 24 Feb 1999 16:09:42 -0500
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     John, et al;
     There are many variables involved in this calculation, not addressed
     in your examples, however, based on your numbers, the model I (we) use
     here gives me results that match your readings.

     Some items of note:

     Your Dk appears a bit high. For thin dielectrics in your range,
     depending on construction, our experience tells us the Dk could range
     from 4.15 to 4.5. I used 4.3 and got 58 & 53 for your layers 3 & 6.

     You don't make mention of the corresponding layers to 3 & 6, namely 4
     & 7. Do these exhibit the same impedance readings?

     There is an obvious imbalance in the construction, in that one signal
     resides on the same core as the reference plane, while the other is
     across a "fill" of dielectric material. Given that, I would expect to
     see variation across 3 & 6. There is a 35 micron difference in
     dielectric thickness (to the nearest plane) that will certainly
     account for the 3+ Ohm difference.

     Your prediction was probably based on all things being equal, but as
     we have come to learn, that ain't necessarily so <grin>... Feel free
     to continue this thread if we (the `Net community) can offer more
     help!

     regards,

     Tom Bresnan
     Product Engineering Manager
     HADCO Tech Center East


______________________________ Reply Separator _________________________________
Subject: <no subject>
Author:  John Bownass <[log in to unmask]> at SMTPLink-Hadco
Date:    2/23/99 11:30 AM


Colleagues,

I wonder if you can throw any light onto a problem I have with a
specific impedance controlled board where the prediction does not match
the actual measured results.

The board is 12 layer FR4 with controlled impedance on layers 3, 4, 6,
7, 9 and 10.  Layers 2, 5, 8 and 11 being the planes.  So there are two
signal layers between each pair of planes, all impedances should be 48
ohms (+/-10%).

The problem is that the measured impedances from a finished board do not
agree with the prediction based on the actual measurements from a cross
section of the measured board.  I give 2 examples:

All dielectric spacings are copper to copper, all figures in microns:

Layer 3: track width avg 126, spacing to layer 2 = 135, to layer 5 =
260. Thickness = 16.
Layer 6: track width avg 121, spacing to layer 5 = 100, to layer 8 =
270. Thickness = 16.

L3 measured impedance = 57.3 avg, and calculated from above figures =
50.6
L6 measured impedance = 54.3 avg, and calculated from above figures =
46.2

Dielectric constant of 4.6 used.

Of course the Er can be out but it could not explain such a large
difference.

The offset stripline model used works within normal tolerances for all
our other work but for some reason not this particular job.  Any ideas?


Has anyone a model that predicts nearer to the actual results?

Regards

John Bownass

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