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Reply To: | TechNet E-Mail Forum. |
Date: | Wed, 24 Feb 1999 00:41:56 -0500 |
Content-Type: | text/plain |
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WM Cheng wrote:
>
> Hi Technetters,
> Refer to IPC-SM-782, which mention about robber pads to reduce
> solder bridging but doesn't mention about size and shape, is
> there any simple calculation method/rule to design a robber
> pad for the SOIC and TO220 package for wave soldering process?
>
For the SOIC package, we'd use an added pad the same size
as the soldered lands, like a 14-pin device offset on a
16 pin pattern (or centered on an 18-pin pattern for wave in
either direction). Some manufacturing standards call for the
area between "pin 7" and the thief "pin 8" to be filled-in
as one large pad.
On a TO220 we've not had to use thieves so I can't comment.
--
Jeff Seeger Applied CAD Knowledge Inc
Chief Technical Officer Tyngsboro, MA 01879
jseeger "at" appliedcad "dot" com 978 649 9800
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