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January 1999

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Subject:
From:
Andy Mackie <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 28 Jan 1999 12:46:03 -0500
Content-Type:
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I really like Steve's idea of having an SIR board as one of the
panellizations. I've been kicking around the idea of doing a similar thing
on solder paste solderability to OSP's. The idea is to have a couple of
solid conductor lines at right angles to each other somewhere on the board,
then print small solder paste deposits on the lines, with increasing
spacings between them. After reflow, this could be inspected to see what
the largest bridged gap is (in this instance: bridging between widely
spaced pads is the good guy, folks!), and using that as a measure of the
solderability of the substrate. Although there may be interferences such as
printing of paste (voiding), that may be a useful process indicator, too,
as it will also should also give a low result. If you can't visualize this
solderability test: get hold of a copy of Mike Yuen's paper on "0201
Tombstoning and Solderability" at NEPCON West this year.

Incidentally, solder paste is usually 50% by VOLUME of solder metal, so, IN
THEORY, to eliminate squeeze balls/ sideballs/ capillary balls (call 'em
what you will) by stencil design, all you need to do, is the following:

1./ Measure the diameter of the balls you see
2./ Calculate the volume
3./ Make sure that your stencil aperture reduction (for each pad) is equal
to the volume of one capillary ball.

Let me know what you think, folks!

Andy Mackie (Chairman - IPC Solder Paste Task Group)
Praxair Inc.
Ph: 914-345-6402
Fx: 914-345-6405




"Stephen R. Gregory" <[log in to unmask]> on 01/28/99 12:14:01 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
      to [log in to unmask]

To:   [log in to unmask]
cc:    (bcc: Andy Mackie)
Subject:  Re: [TN] Design considerations for No-Clean processes




In a message dated 1/27/99 8:41:13 PM Pacific Standard Time,
[log in to unmask]
writes:

 > Here is one for the Design and Assembly folks.
 > We are a high volume OEM of consumer electronics.
 > My Assembly has converted to a No-Clean process.
 > What are the differences that I should be concerned with at the design
 > level?
 > Should I have concerns about or modify any designs left over from the
 > Aqueous days?
 > Thanks for the help

 > FNK
 >
 >
 > Frank N Kimmey, C.I.D.
 > EM Designer
 > C & K Systems, Inc.
 > 916-353-5366
 > [log in to unmask]

 Hi Frank!

    I was with a memory company when we converted from water soluble to no-
clean, and there were a few suprises for the finance department that
weren't
realized when the decision was initially made to change processes.

    One of he biggest expenses was stencils. We had over 400 different part
numbers of SIMM's, DIMM's, Cache Modules, & PCMCIA products...you wouldn't
believe the number of stencils we had. Well, they were all made when we
washed
everything. Stencil apertures for all passive components were 1 to 1 except
for the industry standard etch factor compensation...and most of you can
guess
what happened when we used those stencils with no clean. You got it!
Squeeze
ball city! Not a big deal when the boards get a bath before they leave the
factory, because they normally always wash off...(that's why everybody
lives
with this process defect in a cleaning environment) but a very big deal
when
you're no-clean. Every last one of the stencils needed to be replaced...and
at
a average of $400 a pop at 400 stencils...(that's ummmm...lessee,...zero
times
zero equals zero, and then 4 times...oops wait, gotta take off my shoes
now..)....uhhhh...just TRUST ME, it's a whole lotta moola! (GRIN)

    Another thing that drove the costs up was the fact that we couldn't buy
material the way we had in the past. Couldn't give those 100,000 board
orders
to fab vendors anymore to keep the prices down, and let the PCB's languish
around on the stockroom shelves oxidizing and expect to solder em' with no-
clean. Same thing went for the DRAM. Used to buy from anybody and
everybody,
but had to be a little more selective when the process changed.

    One thing you might do in your designs, if you haven't already, is to
implement some sort of SIR comb pattern that you put on every one of your
designs. It's up to you where you want it to be. It could be one like
what's
on IPC's B-24 board or as simple as two unmasked traces next to each other.
What we were doing since practically every one of the products we build was
panelized, we put them on the coupons, or skirts of the panel. They went
along
in the process just like the SIMM's did so we would test them. That way
when
we wanted to to a SIR test we wouldn't tie up any shipable product.

     Another thing that I think that's pretty important, is to standardize
on
a surface finish and mask type that you use on all your fabs. We used o get
boards from about 5 or 6 main vendors, and to try and get your arms around
all
of them so they're all giving you the same thing can be a bear, but it
really
makes things easier and more predictable on the production floor.

Good Luck!

-Steve Gregory-

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