Lum Wee Mei wrote:
>
> We are asked to carry out a high current layout design. The PCB layer is
> expected to be at least 10-12 layer with 2oz copper per layer. The layer
> count could be less . The PCB consists of some terminating blocks that
> can handle as high as 150Amp with some HDC connectors whose pin is
> expected to carry at least 7.5Amp per connector pin.
>
> We intend to route each connector pin out and joined them using area
> fill. However, the engineer is questionable whether the large area  fill
> can support 30Amp? I would appreciate some help in this design on the
> followings or others :
>
> How wide should the trace width be?
> How many layer is consider sufficient if 2oz copper is used per layer?
> How do one calculate the current carrying capacity of the trace,
> especially in this design?
>
        The plane (fill) area is rarely the problem, I'd have no fear
        distributing 30 amps over a single 2 oz Cu plane.  The
        problem is usually getting the power onto the plane, as
        for a given level of power there are usually more desti-
        ation pins than source pins.  But of course you must check
        both to be sure.

        For finding current carrying, refer to IPC-D-275 or the
        later spec #2222 (I think).  By looking at the charts,
        I find that for an internal layer you need 500 square
        mils of conductor cross-section to carry 7.5 amps and
        have a thermal rise above ambient of 20o C with 2 oz Cu.

        This translates into a trace width of 200 mils.  You don't
        give the diameter of the hole for your connector pin, so
        check how much copper you have available in the circum-
        ference.  This will help you determine how many layers you
        need to use to get 200 mils worth of conductor off of that
        pin.  Note that you will not be able to meet the normal
        standard for thermal reliefs so wave soldering is out,
        you need to think about how this will get assembled.

        Once you know how many layers are needed, you can make a
        filled area around the pin on how ever many layers are needed
        and use vias to get to the one plane that will carry the
        current.  Of course, if your load pins exceed what can
        be connected on one layer also, you may want to use more
        than one plane.

        Hope this helps,
--

      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312
################################################################